Features
• High-performance and Low-power AVR® 8-bit RISC Architecture
•
•
•
•
•
•
•
•
– 118 Powerful Instructions - Most Single Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
Data and Nonvolatile Program Memory
– 2K/4K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128/256 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Expanded 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9- or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– Programmable UART
– 6-channel, 10-bit ADC
– Master/Slave SPI Serial Interface
Special Microcontroller Features
– Brown-Out Reset Circuit
– Enhanced Power-on Reset Circuit
– Low-Power Idle and Power Down Modes
– External and Internal Interrupt Sources
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.4 mA
– Idle Mode: 1.4 mA
– Power Down Mode: 2V
0.5
LSB
Differential Non-Linearity
VREF > 2V
0.5
LSB
1
LSB
Zero Error (Offset)
Conversion Time
65
Clock Frequency
50
AVCC
Analog Supply Voltage
VREF
Reference Voltage
RREF
Reference Input Resistance
RAIN
Analog Input Resistance
Notes:
Max
VCC - 0.3
1. Minimum for AVCC is 2.7V.
2. Maximum for AVCC is 6.0V.
AT90S/LS2333 and AT90S/LS4433
LSB
260
µs
200
(1)
VCC + 0.3
AGND
6
2
10
100
kHz
(2)
V
AVCC
V
13
kΩ
MΩ
AT90S/LS2333 and AT90S/LS4433
I/O Ports
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI
instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if
configured as input).
Port B
Port B is a 6-bit bi-directional I/O port.
Three I/O memory address locations are allocated for the Port B, one each for the Data Register - PORTB, $18($38), Data
Direction Register - DDRB, $17($37) and the Port B Input Pins - PINB, $16($36). The Port B Input Pins address is read
only, while the Data Register and the Data Direction Register are read/write.
All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
The Port B pins with alternate functions are shown in the following table:
Table 23. Port B Pins Alternate Functions
Port Pin
Alternate Functions
PB0
ICP (Timer/Counter 1 input capture pin)
PB1
OC1 (Timer/Counter 1 output compare match output)
PB2
SS (SPI Slave Select input)
PB3
MOSI (SPI Bus Master Output/Slave Input)
PB4
MISO (SPI Bus Master Input/Slave Output)
PB5
SCK (SPI Bus Serial Clock)
When the pins are used for the alternate function, the DDRB and PORTB register has to be set according to the alternate
function description.
Port B Data Register - PORTB
Bit
7
6
5
4
3
2
1
0
$18 ($38)
-
-
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
PORTB
Port B Data Direction Register - DDRB
Bit
7
6
5
4
3
2
1
0
$17 ($37)
-
-
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
DDRB
Port B Input Pins Address - PINB
Bit
7
6
5
4
3
2
1
0
$16 ($36)
-
-
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
R
R
R
R
R
R
R
R
Initial value
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PINB
59
The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port
B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins
are read.
Port B As General Digital I/O
All 6 pins in Port B have equal functionality when used as digital I/O pins.
PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin
configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTBn has to be
cleared (zero) or the pin has to be configured as an output pin.The port pins are tristated when a reset condition becomes
active, even if the clock is not running.
Table 24. DDBn Effects on Port B Pins
DDBn
PORTBn
I/O
Pull Up
0
0
Input
No
Tri-state (Hi-Z)
0
1
Input
Yes
PBn will source current if ext. pulled low.
1
0
Output
No
Push-Pull Zero Output
1
1
Output
No
Push-Pull One Output
Note:
Comment
n: 5…0, pin number.
Alternate Functions Of Port B
The alternate pin configuration is as follows:
• SCK - Port B, Bit 5
SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured
as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the
description of the SPI port for further details.
• MISO - Port B, Bit 4
MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured
as an input regardless of the setting of DDB4. When the SPI is enabled as a slave, the data direction of this pin is controlled
by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of
the SPI port for further details.
• MOSI - Port B, Bit 3
MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured
as an input regardless of the setting of DDB3. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. See the
description of the SPI port for further details.
• SS - Port B, Bit 2
SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting
of DDB2. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit. See the description of the SPI port for further details.
• OC1 - Port B, Bit1
OC1, Output compare match output: PB1 pin can serve as an external output for the Timer/Counter1 output compare. The
pin has to be configured as an output (DDB1 set (one)) to serve this function. See the timer description on how to enable
this function. The OC1 pin is also the output pin for the PWM mode timer function.
• ICP- Port B, Bit0
ICP, Input Capture Pin: PB0 pin can serve as an external input for the Timer/Counter1 input capture. The pin has to be configured as an input (DDB0 cleared (zero)) to serve this function. See the timer description on how to enable this function.
60
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
Figure 50. Port B Schematic Diagram (Pin PB0)
RD
MOS
PULLUP
RESET
Q
R
D
DDB6
WD
RESET
R
Q
D
PORTB0
PB0
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
ACIC:
ACO:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
COMPARATOR IC ENABLE
COMPARATOR OUTPUT
0
NOISE CANCELER
EDGE SELECT
ICNC1
ICES1
ICF1
1
ACIC
ACO
Figure 51. Port B Schematic Diagram (Pin PB1)
DDB1
PB1
PORTB1
WP:
WD:
RL:
RP:
RD:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
61
Figure 52. Port B Schematic Diagram (Pin PB2)
RD
MOS
PULLUP
RESET
Q
D
DDB2
C
DATA BUS
WD
RESET
Q
D
PORTB2
C
PB2
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
MSTR:
SPE:
MSTR
SPE
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI MASTER ENABLE
SPI ENABLE
SPI SS
Figure 53. Port B Schematic Diagram (Pin PB3)
RD
MOS
PULLUP
RESET
Q
R
D
DDB3
WD
RESET
R
Q
D
PORTB3
PB3
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
MSTR
SPE
SPI MASTER
OUT
SPI SLAVE
IN
62
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
Figure 54. Port B Schematic Diagram (Pin PB4)
RD
MOS
PULLUP
RESET
R
Q
D
DDB4
WD
RESET
R
Q
D
PORTB4
PB4
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
MSTR
SPE
SPI SLAVE
OUT
SPI MASTER
IN
Figure 55. Port B Schematic Diagram (Pin PB5)
RD
MOS
PULLUP
RESET
Q
R
D
DDB5
WD
RESET
R
Q
D
PORTB5
PB5
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
MSTR
SPE
SPI CLOCK
OUT
SPI CLOCK
IN
63
Port C
Port C is a 6-bit bi-directional I/O port.
Three I/O memory address locations are allocated for the Port C, one each for the Data Register - PORTC, $15($35), Data
Direction Register - DDRC, $14($34) and the Port C Input Pins - PINC, $13($33). The Port C Input Pins address is read
only, while the Data Register and the Data Direction Register are read/write.
All port pins have individually selectable pull-up resistors. The Port C output buffers can sink 20mA and thus drive LED displays directly. When pins PC0 to PC5 are used as inputs and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
Port C has an alternate function as analog inputs for the ADC. If some Port C pins are configured as outputs, it is essential
that these do not switch when a conversion is in progress. This might corrupt the result of the conversion.
During Power Down Mode, the schmitt triggers of the digital inputs are disconnected. This allows an analog voltage close
to VCC/2 to be present during power down without causing excessive power consumption.
Port C Data Register - PORTC
Bit
7
6
5
4
3
2
1
0
$15 ($35)
-
-
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
PORTC
Port C Data Direction Register - DDRC
Bit
7
6
5
4
3
2
1
0
$14 ($34)
-
-
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
DDRC
Port C Input Pins Address - PINC
Bit
7
6
5
4
3
2
1
0
$13 ($33)
-
-
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
Read/Write
R
R
R
R
R
R
R
R
Initial value
Q
Q
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PINC
The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each
Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the
pins are read.
Port C As General Digital I/O
All 6 pins in Port C have equal functionality when used as digital I/O pins.
PCn, General I/O pin: The DDCn bit in the DDRC register selects the direction of this pin, if DDCn is set (one), PCn is configured as an output pin. If DDCn is cleared (zero), PCn is configured as an input pin. If PORTCn is set (one) when the pin
configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, PORTCn has to be
cleared (zero) or the pin has to be configured as an output pin.The port pins are tristated when a reset condition becomes
active, even if the clock is not running
64
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
Table 25. DDCn Effects on Port C Pins
DDCn
PORTCn
I/O
Pull Up
0
0
Input
No
Tri-state (Hi-Z)
0
1
Input
Yes
PCn will source current if ext. pulled low.
1
0
Output
No
Push-Pull Zero Output
1
1
Output
No
Push-Pull One Output
Note:
Comment
n: 5…0, pin number
Port C Schematics
Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure.
Figure 56. Port C Schematic Diagrams (Pins PC0 - PC5)
RD
MOS
PULLUP
RESET
Q
D
DDCn
WD
RESET
Q
D
PORTCn
C
PCn
RL
PWRDN
WP
RP
TO ADC MUX
WP:
WD:
RL:
RP:
RD:
PWRDN:
n:
DATA BUS
C
ADCn
WRITE PORTC
WRITE DDRC
READ PORTC LATCH
READ PORTC PIN
READ DDRC
POWER DOWN MODE
0-5
Port D
Port D is an 8 bit bi-directional I/O port with internal pull-up resistors.
Three I/O memory address locations are allocated for Port D, one each for the Data Register - PORTD, $12($32), Data
Direction Register - DDRD, $11($31) and the Port D Input Pins - PIND, $10($30). The Port D Input Pins address is read
only, while the Data Register and the Data Direction Register are read/write.
The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pullup resistors are activated.
Some Port D pins have alternate functions as shown in the following table:
65
Table 26. Port D Pins Alternate Functions
Port Pin
Alternate Function
PD0
RXD (UART Input line)
PD1
TXD (UART Output line)
PD2
INT0 (External interrupt 0 input)
PD3
INT1 (External interrupt 1 input)
PD4
T0 (Timer/Counter 0 external counter input)
PD5
T1 (Timer/Counter 1 external counter input)
PD6
AIN0 (Analog comparator positive input)
PD7
AIN1 (Analog comparator negative input)
Port D Data Register - PORTD
Bit
7
6
5
4
3
2
1
0
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
$12 ($32)
PORTD
Port D Data Direction Register - DDRD
Bit
7
6
5
4
3
2
1
0
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
$11 ($31)
DDRD
Port D Input Pins Address - PIND
Bit
7
6
5
4
3
2
1
0
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
Read/Write
R
R
R
R
R
R
R
R
Initial value
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
$10 ($30)
PIND
The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each
Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the
pins are read.
Port D As General Digital I/O
PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured
as an input pin the MOS pull up resistor is activated. To switch the pull up resistor off the PDn has to be cleared (zero) or
the pin has to be configured as an output pin.The port pins are tristated when a reset condition becomes active, even if the
clock is not running.
66
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
Table 27. DDDn Bits on Port D Pins
DDDn
PORTDn
I/O
Pull Up
0
0
Input
No
Tri-state (Hi-Z)
0
1
Input
Yes
PDn will source current if ext. pulled low.
1
0
Output
No
Push-Pull Zero Output
1
1
Output
No
Push-Pull One Output
Note:
Comment
n: 7,6…0, pin number.
Alternate Functions Of Port D
• AIN1 - Port D, Bit 7
AIN1, Analog Comparator Negative Input. When configured as an input (DDD7 is cleared (zero)) and with the internal MOS
pull up resistor switched off (PD7 is cleared (zero)), this pin also serves as the negative input of the on-chip analog comparator. During power down mode, the schmitt trigger of the digital input is disconnected. This allows analog signals which are
close to VCC/2 to be present during power down without causing excessive power consumption.
• AIN0 - Port D, Bit 6
AIN0, Analog Comparator Positive Input. When configured as an input (DDD6 is cleared (zero)) and with the internal MOS
pull up resistor switched off (PD6 is cleared (zero)), this pin also serves as the positive input of the on-chip analog comparator. During power down mode, the schmitt trigger of the digital input is disconnected. This allows analog signals which are
close to VCC/2 to be present during power down without causing excessive power consumption.
• T1 - Port D, Bit 5
T1, Timer/Counter1 counter source. See the timer description for further details
• T0 - Port D, Bit 4
T0: Timer/Counter0 counter source. See the timer description for further details.
• INT1 - Port D, Bit 3
INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt
description for further details, and how to enable the source.
• INT0 - Port D, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt
description for further details, and how to enable the source.
• TXD - Port D, Bit 1
Transmit Data (Data output pin for the UART). When the UART transmitter is enabled, this pin is configured as an output
regardless of the value of DDD1.
• RXD - Port D, Bit 0
Receive Data (Data input pin for the UART). When the UART receiver is enabled this pin is configured as an input regardless of the value of DDD0. When the UART forces this pin to be an input, a logical one in PORTD0 will turn on the internal
pull-up.
67
Port D Schematics
Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.
Figure 57. Port D Schematic Diagram (Pin PD0)
RD
MOS
PULLUP
RESET
Q
D
DDD0
C
DATA BUS
WD
RESET
Q
D
PORTD0
C
PD0
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
RXD:
RXEN:
RXEN
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART RECEIVE DATA
UART RECEIVE ENABLE
RXD
Figure 58. Port D Schematic Diagram (Pin PD1)
RD
MOS
PULLUP
RESET
Q
R
D
DDD1
C
DATA BUS
WD
RESET
R
Q
D
PORTD1
PD1
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
TXD:
TXEN:
68
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART TRANSMIT DATA
UART TRANSMIT ENABLE
AT90S/LS2333 and AT90S/LS4433
TXEN
TXD
AT90S/LS2333 and AT90S/LS4433
Figure 59. Port D Schematic Diagram (Pins PD2 and PD3)
Figure 60. Port D Schematic Diagram (Pins PD4 and PD5)
DDDn
PDn
PORTBn
WP:
WD:
RL:
RP:
RD:
n:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
4, 5
2
69
Figure 61. Port D Schematic Diagram (Pins PD6 and PD7)
RD
MOS
PULLUP
RESET
Q
D
DDDn
WD
RESET
Q
D
PORTDn
C
PDn
RL
PWRDN
WP
RP
TO COMPARATOR
WP:
WD:
RL:
RP:
RD:
PWRDN:
n:
m:
70
DATA BUS
C
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
POWER DOWN MODE
6, 7
0, 1
AT90S/LS2333 and AT90S/LS4433
AINm
AT90S/LS2333 and AT90S/LS4433
Memory Programming
Program and Data Memory Lock Bits
The AT90S2333/4433 MCU provides two Lock bits which can be left unprogrammed (‘1’) or can be programmed (‘0’) to
obtain the additional features listed in Table 28. The Lock bits can only be erased with the Chip Erase command.
Table 28. Lock Bit Protection Modes
Memory Lock Bits
Protection Type
Mode
LB1
LB2
1
1
1
No memory lock features enabled.
2
0
1
Further programming of the Flash and EEPROM is disabled.(1)
3
0
0
Same as mode 2, and verify is also disabled.
Note:
1. In Parallel mode, programming of the Fuse bits are also disabled. Program the Fuse bits before programming the Lock bits.
Fuse Bits
The AT90S2333/4433 has six Fuse bits, SPIEN, BODLEVEL, BODEN and CKSEL2..0.
• When the SPIEN Fuse is programmed (‘0’), Serial Program and Data Downloading is enabled. Default value is
programmed (‘0’). This bit is not accessible in serial programming mode.
• The BODLEVEL Fuse selects the Brown-Out Detection Level and changes the Start-up times. See “Brown-Out
Detection” on page 21. Default value is unprogrammed (‘1’).
• When the BODEN Fuse is programmed (‘0’), the Brown- Out Detector is enabled. See “Brown-Out Detection” on
page 21. Default value is unprogrammed (‘1’).
• CKSEL2..0: See Table 5, “Reset Delay Selections”, for which combination of CKSEL2..0 to use. Default value is ‘010’.
Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial
and parallel mode. The three bytes reside in a separate address space.
For the AT90S4433(1) they are:
1. $000: $1E (indicates manufactured by Atmel)
2. $001: $92 (indicates 4KB Flash memory)
3. $002: $03 (indicates AT90S4433 device when signature byte $001 is $92)
For AT90S2333(1) they are:
1. $000: $1E (indicates manufactured by Atmel)
2. $001: $91 (indicates 2KB Flash memory)
3. $002: $05 (indicates AT90S2333 device when signature byte $001 is $91)
Note:
1. When both Lock bits are programmed (Lock mode 3), the signature bytes can not be read in serial mode. Reading the signature bytes will return: $00, $01 and $02.
Programming the Flash and EEPROM
Atmel’s AT90S2333/4433 offers 2K/4K bytes of in-system reprogrammable Flash Program memory and 128/256 bytes of
EEPROM Data memory.
The AT90S2333/4433 is shipped with the on-chip Flash Program and EEPROM Data memory arrays in the erased state
(i.e. contents = $FF) and ready to be programmed. This device supports a High-Voltage (12V) Parallel programming mode
and a Low-Voltage Serial programming mode. The +12V is used for programming enable only, and no current of significance is drawn by this pin. The serial programming mode provides a convenient way to download program and data into
the AT90S2333/4433 inside the user’s system.
71
The Program and Data memory arrays on the AT90S2333/4433 are programmed byte-by-byte in either programming
modes. For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the serial programming
mode. During programming, the supply voltage must be in accordance with Table 29.
Table 29. Supply voltage during programming
Part
Serial programming
Parallel programming
AT90LS2333
2.7 - 6.0 V
4.5 - 5.5 V
AT90S2333
4.0 - 6.0 V
4.5 - 5.5 V
AT90LS4433
2.7 - 6.0 V
4.5 - 5.5 V
AT90S4433
4.0 - 6.0 V
4.5 - 5.5 V
Parallel Programming
This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Lock bits and
Fuse bits in the AT90S2333/4433.
Signal Names
In this section, some pins of the AT90S2333/4433 are referenced by signal names describing their function during parallel
programming. See Figure 62 and Table 30. Pins not described in Table 30 are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding are shown
in Table 31.
When pulsing WR or OE, the command loaded determines the action executed. The Command is a byte where the different bits are assigned functions as shown in Table 32.
Figure 62. Parallel Programming
AT90S2333/4433
RDY/BSY
PD1
VCC
PC1 - PC0,
PB5 - PB0
OE
PD2
WR
PD3
BS
PD4
XA0
PD5
XA1
PD6
+12V
+5V
RESET
XTAL1
GND
72
AT90S/LS2333 and AT90S/LS4433
DATA
AT90S/LS2333 and AT90S/LS4433
Table 30. Pin Name Mapping
Signal Name in Programming Mode
Pin Name
I/O
Function
RDY/BSY
PD1
O
0: Device is busy programming, 1: Device is ready for new command
OE
PD2
I
Output Enable (Active low)
WR
PD3
I
Write Pulse (Active low)
BS
PD4
I
Byte Select (‘0’ selects low byte, ‘1’ selects high byte)
XA0
PD5
I
XTAL Action Bit 0
XA1
PD6
I
XTAL Action Bit 1
DATA
PC1-0, PB5-0
I/O
Bidirectional Databus (Output when OE is low)
Table 31. XA1 and XA0 Coding
XA1
XA0
Action when XTAL1 is Pulsed
0
0
Load Flash or EEPROM Address (High or low address byte determined by BS)
0
1
Load Data (High or Low data byte for Flash determined by BS)
1
0
Load Command
1
1
No Action, Idle
Table 32. Command Byte Bit Coding
Command Byte
Command Executed
1000 0000
Chip Erase
0100 0000
Write Fuse Bits
0010 0000
Write Lock Bits
0001 0000
Write Flash
0001 0001
Write EEPROM
0000 1000
Read Signature Bytes
0000 0100
Read Fuse and Lock Bits
0000 0010
Read Flash
0000 0011
Read EEPROM
Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply supply voltage according to Table 29, between VCC and GND.
2. Set the RESET and BS pin to ‘0’ and wait at least 100 ns.
3. Apply 11.5 - 12.5V to RESET. Any activity on BS within 100 ns after +12V has been applied to RESET, will cause
the device to fail entering programming mode.
Chip Erase
The Chip Erase command will erase the Flash and EEPROM memories, and the Lock bits. The Lock bits are not reset until
the Flash and EEPROM have been completely erased. The Fuse bits are not changed. Chip Erase must be performed
before the Flash or EEPROM is reprogrammed.
Load Command “Chip Erase”
73
1. Set XA1, XA0 to ‘10’. This enables command loading.
2. Set BS to ‘0’.
3. Set DATA to ‘1000 0000’. This is the command for Chip erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR a tWLWH_CE wide negative pulse to execute Chip Erase. See Table 33 for tWLWH_CE value. Chip Erase does not
generate any activity on the RDY/BSY pin.
Programming the Flash
A: Load Command “Write Flash”
1. Set XA1, XA0 to ‘10’. This enables command loading.
2. Set BS to ‘0’
3. Set DATA to ‘0001 0000’. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B: Load Address High Byte
1. Set XA1, XA0 to ‘00’. This enables address loading.
2. Set BS to ‘1’. This selects high byte.
3. Set DATA = Address high byte ($00 - $03/$07)
4. Give XTAL1 a positive pulse. This loads the address high byte.
C: Load Address Low Byte
1. Set XA1, XA0 to ‘00’. This enables address loading.
2. Set BS to ‘0’. This selects low byte.
3. Set DATA = Address low byte ($00 - $FF)
4. Give XTAL1 a positive pulse. This loads the address low byte.
D: Load Data Low Byte
1. Set XA1, XA0 to ‘01’. This enables data loading.
2. Set DATA = Data low byte ($00 - $FF)
3. Give XTAL1 a positive pulse. This loads the data low byte.
E: Write Data Low Byte
1. Set BS to ‘0’. This selects low data.
2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low.
3. Wait until RDY/BSY goes high to program the next byte.
(See Figure 63 for signal waveforms.)
F: Load Data High Byte
1. Set XA1, XA0 to ‘01’. This enables data loading.
2. Set DATA = Data high byte ($00 - $FF)
3. Give XTAL1 a positive pulse. This loads the data high byte.
G: Write Data High Byte
1. Set BS to ‘1’. This selects high data.
2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low.
3. Wait until RDY/BSY goes high to program the next byte.
(See Figure 64 for signal waveforms.)
The loaded command and address are retained in the device during programming. For efficient programming, the following
should be considered.
• The command needs only be loaded once when writing or reading multiple memory locations.
74
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
• Address high byte needs only be loaded before programming a new 256 word page in the Flash.
• Skip writing the data value $FF, that is the contents of the entire Flash and EEPROM after a Chip Erase.
These considerations also applies to EEPROM programming, and Flash, EEPROM and Signature bytes reading.
Figure 63. Programming the Flash Waveforms
DATA
$10
ADDR. HIGH
ADDR. LOW
DATA LOW
XA1
XA0
BS
XTAL1
WR
RDY/BSY
RESET
12V
OE
Figure 64. Programming the Flash Waveforms (continued)
DATA
DATA HIGH
XA1
XA0
BS
XTAL1
WR
RDY/BSY
RESET
+12V
OE
Reading the Flash
The algorithm for reading the Flash memory is as follows (refer to Programming the Flash for details on Command and
Address loading):
1. A: Load Command ‘0000 0010’.
2. B: Load Address High Byte ($00 - $03/$07).
3. C: Load Address Low Byte ($00 - $FF).
4. Set OE to ‘0’, and BS to ‘0’. The Flash word low byte can now be read at DATA.
5. Set BS to ‘1’. The Flash word high byte can now be read from DATA.
6. Set OE to ‘1’.
75
Programming the EEPROM
The programming algorithm for the EEPROM data memory is as follows (refer to Programming the Flash for details on
Command, Address and Data loading):
1. A: Load Command ‘0001 0001’.
2. C: Load Address Low Byte ($00 - $7F/$FF).
3. D: Load Data Low Byte ($00 - $FF).
4. E: Write Data Low Byte.
Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to Programming the Flash for details on Command and
Address loading):
1. A: Load Command ‘0000 0011’.
2. C: Load Address Low Byte ($00 - $7F/$FF).
3. Set OE to ‘0’, and BS to ‘0’. The EEPROM data byte can now be read at DATA.
4. Set OE to ‘1’.
Programming the Fuse Bits
The algorithm for programming the Fuse bits is as follows (refer to Programming the Flash for details on Command and
Data loading):
1. A: Load Command ‘0100 0000’.
2. D: Load Data Low Byte. Bit n = ‘0’ programs and bit n = ‘1’ erases the Fuse bit.
Bit 5 = SPIEN Fuse bit
Bit 4 = BODLEVEL Fuse bit
Bit 3 = BODEN Fuse bit
Bit 2 = CKSEL2 Fuse bit
Bit 1 = CKSEL1 Fuse bit
Bit 0 = CKSEL0 Fuse bit
Bit 7-6 = ‘1’. These bits are reserved and should be left unprogrammed (‘1’).
3. Give WR a tWLWH_PFB wide negative pulse to execute the programming, tWLWH_PFB is found in Table 33. Programming
the Fuse bits does not generate any activity on the RDY/BSY pin.
Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to Programming the Flash for details on Command and
Data loading):
1. A: Load Command ‘0010 0000’.
2. D: Load Data Low Byte. Bit n = ‘0’ programs the Lock bit.
Bit 2 = Lock Bit2
Bit 1 = Lock Bit1
Bit 7-3,0 = ‘1’. These bits are reserved and should be left unprogrammed (‘1’).
3. E: Write Data Low Byte.
The Lock bits can only be cleared by executing Chip Erase.
Reading the Fuse and Lock Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to Programming the Flash for details on Command
loading):
1. A: Load Command ‘0000 0100’.
2. Set OE to ‘0’, and BS to ‘0’. The status of the Fuse bits can now be read at DATA (‘0’ means programmed).
76
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
Bit 5 = SPIEN Fuse bit
Bit 4 = BODLEVEL Fuse bit
Bit 3 = BODEN Fuse bit
Bit 2 = CKSEL2 Fuse bit
Bit 1 = CKSEL1 Fuse bit
Bit 0 = CKSEL0 Fuse bit
3. Set BS to ‘1’. The status of the Lock bits can now be read at DATA (‘0’ means programmed).
Bit 2 = Lock Bit2
Bit 1= Lock Bit1
4. Set OE to ‘1’.
Reading the Signature Bytes
The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for details on Command and
Address loading):
1. A: Load Command ‘0000 1000’.
2. C: Load Address Low Byte ($00 - $02).
Set OE to ‘0’, and BS to ‘0’. The selected Signature byte can now be read at DATA.
3. Set OE to ‘1’.
Parallel Programming Characteristics
Figure 65. Parallel Programming Timing
tXLWL
tXHXL
XTAL1
tDVXH
tXLDX tBVWL
tWLWH
WR
tWHRL
tRHBX
Write
Data & Contol
(DATA, XA0/1, BS)
RDY/BSY
OE
DATA
tXLOL
tOLDV
tOHDZ
Read
tWLRH
77
Table 33. Parallel Programming Characteristics TA = 25°C ± 10%, VCC =5V ± 10%
Symbol
Parameter
Min
VPP
Programming Enable Voltage
11.5
IPP
Programming Enable Current
tDVXH
Data and Control Setup before XTAL1 High
67
ns
tXHXL
XTAL1 Pulse Width High
67
ns
tXLDX
Data and Control Hold after XTAL1 Low
67
ns
tXLWL
XTAL1 Low to WR Low
67
ns
tBVWL
BS Valid to WR Low
67
ns
tRHBX
BS Hold after RDY/BSY High
67
ns
67
ns
(1)
tWLWH
WR Pulse Width Low
tWHRL
WR High to RDY/BSY Low(2)
tWLRH
WR Low to RDY/BSY High(2)
0.5
tXLOL
XTAL1 Low to OE Low
67
tOLDV
OE Low to DATA Valid
tOHDZ
OE High to DATA Tristated
tWLWH_CE
WR Pulse Width Low for Chip Erase
tWLWH_PFB
WR Pulse Width Low for Programming the Fuse
Bits
Notes:
Typ
Max
Units
12.5
V
250
µΑ
20
0.7
ns
0.9
ms
ns
20
ns
20
ns
5
10
15
ms
1.0
1.5
1.8
ms
1. Use tWLWH_CE for Chip Erase and tWLWH_PFB for Programming the Fuse Bits.
2. If tWLWH is held longer than tWLRH, no RDY/BSY pulse will be seen.
Serial Downloading
Both the Program and Data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The
serial interface consists of pins SCK, MOSI (input) and MISO (output), see Figure 66. After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed.
Figure 66. Serial Programming and Verify
AT90S2333/4433
+2.7 - 6.0 V
VCC
DATA OUT
INSTR. IN
CLOCK IN
GND
1 to 8 MHz
PB4(MISO)
PB3(MOSI)
PB5(SCK)
RESET
XTAL2
XTAL1
GND
78
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the Program
and EEPROM arrays into $FF.
The Program and EEPROM memory arrays have separate address spaces:
0000 to $03FF/$07FF (AT90S2333/AT90S4433) for Program memory and $0000 to $007F/$00FF
(AT90S2333/AT90S4433) for EEPROM memory.
Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and
XTAL2.The minimum low and high periods for the serial clock (SCK) input are defined as follows:
Low:> 2 XTAL1 clock cycles
High:> 2 XTAL1 clock cycles
Serial Programming Algorithm
When writing serial data to the AT90S2333/AT90S4433, data is clocked on the rising edge of CLK.
When reading data from the AT90S2333/AT90S4433, data is clocked on the falling edge of CLK. See Figure 67, Figure 68
and Table 36 for details.
To program and verify the AT90S2333/AT90S4433 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 35):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to ‘0’. If a crystal is not connected across pins
XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer can not guarantee that
SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two XTAL1 cycles
duration after SCK has been set to ‘0’.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin
MOSI/PB3.
3. The serial programming instructions will not work if the communication is out of syncronization. When in sync, the
second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Wheter the
echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a
positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is
no functional device connected.
4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a
positive pulse, and start over from Step 2. See Table 37 on page 82 for tWD_ERASE value.
5. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the
appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written.
Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait
tWD_PROG before transmitting the next instruction. In an erased device, no $FFs in the data file(s) needs to be programmed. See Table 38 on page 82 for tWD_PROG value.
6. Any memory location can be verified by using the Read instruction which returns the content at the selected
address at serial output MISO/PB4.
7. At the end of the programming session, RESET can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set XTAL1 to ‘0’ (if a crystal is not used).
Set RESET to ‘1’.
Turn VCC power off
79
Data Polling EEPROM
When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value
P1 until the auto-erase is finished, and then the value P2. See Table 34 for P1 and P2 values.
At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values,
the user will have to wait for at least the prescribed time tWD_PROG before programming the next byte. See Table 38 for
tWD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain
$FF, can be skipped. This does not apply if the EEPROM is reprogrammed without first chip-erasing the device.
Table 34. Read Back Value during EEPROM polling
Part
P1
P2
AT90S/LS2333
$00
$FF
AT90S/LS4433
$00
$FF
Data Polling Flash
When a byte is being programmed into the Flash, reading the address location being programmed will give the value $FF.
At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the
next byte can be written. This will not work for the value $FF, so when programming this value, the user will have to wait for
at least tWD_PROG before programming the next byte. As a chip-erased device contains $FF in all locations, programming of
addresses that are meant to contain $FF, can be skipped.
Figure 67. Serial Programming Waveforms
SERIAL DATA INPUT
PB3(MOSI)
MSB
LSB
SERIAL DATA OUTPUT
PB4(MISO)
MSB
LSB
SERIAL CLOCK INPUT
PB5(SCK)
80
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
Table 35. Serial Programming Instruction Set
Instruction
Instruction Format
Operation
Byte 1
Byte 2
Byte 3
Byte4
1010 1100
0101 0011
xxxx xxxx
xxxx xxxx
Enable Serial Programming while
RESET is low.
1010 1100
100x xxxx
xxxx xxxx
xxxx xxxx
Chip Erase Flash and EEPROM
memory arrays.
0010 H000
xxxx xaaa
bbbb bbbb
oooo oooo
Read H (high or low) data o from
Program memory at word address
a:b.
0100 H000
xxxx xaaa
bbbb bbbb
iiii iiii
Write H (high or low) data i to
Program memory at word address
a:b.
Read EEPROM
Memory
1010 0000
xxxx xxxx
bbbb bbbb
oooo oooo
Read data o from EEPROM memory
at address a:b.
Write EEPROM
Memory
1100 0000
xxxx xxxx
bbbb bbbb
iiii iiii
Write data i to EEPROM memory at
address a:b.
1010 1100
1111 1211
xxxx xxxx
xxxx xxxx
Write Lock bits. Set bits 1,2=’0’ to
program Lock bits.
0101 1000
xxxx xxxx
xxxx xxxx
xxxx x21x
Rad Lock bits. ’0’ = programmed, ‘1’ =
unprogrammed.
0011 0000
xxxx xxxx
xxxx xxbb
oooo oooo
Read Signature Byte o at address
b.(1)
1010 1100
1017 6543
xxxx xxxx
xxxx xxxx
Set bits 7 - 3 = ’0’ to program, ‘1’ to
unprogram.
0101 0000
xxxx xxxx
xxxx xxxx
xx87 6543
Read fuse bits. ’0’ = programmed, ‘1’
= unprogrammed.
Programming Enable
Chip Erase
Read Program Memory
Write Program Memory
Write Lock Bits
Read Lock Bits
Read Sigature Bytes
Write Fuse Bits
Read Fuse Bits
Note:
a = address high bits
b = address low bits
H = 0 - Low byte, 1 - High Byte
o = data out
i = data in
x = don’t care
1 = Lock bit 1
2 = Lock bit 2
3 = CKSEL0 Fuse
4 = CKSEL1 Fuse
5 = CKSEL2 Fuse
6 = BODEN Fuse
7 = BODLEVEL Fuse
8 = SPIEN Fuse
Note:
1. The signature bytes are not readable in Lock mode 3, i.e. both Lock bits programmed.
81
Serial Programming Characteristics
Figure 68. Serial Programming Timing
MOSI
tOVSH
SCK
tSHOX
tSLSH
tSHSL
MISO
tSLIV
Table 36. Serial Programming Characteristics
TA = -40°C to 85°C, VCC = 2.7 - 6.0V (Unless otherwise noted)
Symbol
Parameter
Min
1/tCLCL
Oscillator Frequency (VCC = 2.7 - 6.0V)
tCLCL
Oscillator Period (VCC = 2.7 - 6.0V)
1/tCLCL
Oscillator Frequency (VCC = 4.0 - 6.0V)
tCLCL
Oscillator Period (VCC = 4.0 - 6.0V)
tSHSL
Typ
0
Max
Units
4
MHz
250
ns
0
8
MHz
125
ns
SCK Pulse Width High
2 tCLCL
ns
tSLSH
SCK Pulse Width Low
2 tCLCL
ns
tOVSH
MOSI Setup to SCK High
tCLCL
ns
tSHOX
MOSI Hold after SCK High
2 tCLCL
ns
tSLIV
SCK Low to MISO Valid
10
16
32
Table 37. Minimum wait delay after the Chip Erase instruction
Symbol
3.2V
3.6V
4.0V
5.0V
tWD_ERASE
18ms
14ms
12ms
8ms
Table 38. Minimum wait delay after writing a Flash or EEPROM location
Symbol
3.2V
3.6V
4.0V
5.0V
tWD_PROG
9ms
7ms
6ms
4ms
82
AT90S/LS2333 and AT90S/LS4433
ns
AT90S/LS2333 and AT90S/LS4433
Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-1.0V to VCC+0.5V
Voltage on RESET with respect to Ground......-1.0V to +13.0V
Maximum Operating Voltage ............................................ 6.6V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins................................ 300.0 mA
DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(1)
VIL
Input Low Voltage
Except (XTAL, RESET)
-0.5
0.3VCC
VIL1
Input Low Voltage
XTAL
-0.5
0.1(1)
VIL1
VIH
VIH1
VIH2
Input Low Voltage
RESET
Input High Voltage
Except (XTAL, RESET)
Input High Voltage
XTAL
Input High Voltage
RESET
(3)
V
V
(1)
V
0.7 VCC
(2)
VCC + 0.5
V
0.7 VCC
(2)
VCC + 0.5
V
(2)
VCC+0.5
V
0.6
0.5
V
V
-0.5
0.2VCC
0.85 VCC
VOL
Output Low Voltage
(Ports B, C, D)
IOL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 3V
VOH
Output High Voltage(4)
(Ports B, C, D)
IOH = -3 mA, VCC = 5V
IOH = -1.5 mA, VCC = 3V
IIL
Input Leakage
Current I/O pin
VCC = 6V, pin = low
(Absolute value)
8.0
ua
IIH
Input Leakage
Current I/O pin
VCC = 6V, pin = high
(Absolute value)
8.0
ua
RRST
Reset Pull-Up
100
500
kΩ
I/O Pin Pull-Up Resistor
35
120
kΩ
Active 4MHz, VCC = 3V
5.0
mA
Idle 4MHz, VCC = 3V
2.0
mA
Power Down, VCC = 3V
WDT enabled(5)
20.0
µA
Power Down, VCC = 3V
WDT disbled(5)
10
µA
RI/O
ICC
Power Supply Current
4.3
2.2
V
V
83
DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted) (Continued)
Symbol
Parameter
Condition
VACIO
Analog Comparator Input
Offset Voltage
VCC = 5V
IACLK
Analog Comparator Input
Leakage A
VCC = 5V
Vin = VCC/2
Analog Comparator
Propagation Delay
VCC = 2.7V
VCC = 4.0V
tACPD
Notes:
84
Min
Typ
-50
750
500
Max
Units
40
mV
50
nA
ns
1. “Max” means the highest value where the pin is guaranteed to be read as low (logical zero).
2. “Min” means the lowest value where the pin is guaranteed to be read as high (logical one).
3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state
conditions ( non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 300 mA.
2] The sum of all IOL, for port C0-C5 , should not exceed 100 mA.
3] The sum of all IOL, for ports B0-B5, D0-D7 and XTAL2, should not exceed 200 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (3mA at Vcc = 5V, 1.5mA at Vcc = 3V) under steady state
conditions ( non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 300 mA.
2] The sum of all IOL, for port C0-C5 , should not exceed 100 mA.
3] The sum of all IOL, for ports B0-B5, D0-D7 and XTAL2, should not exceed 200 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. Minimum VCC for Power Down is 2V.
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
External Clock Drive Waveforms
Figure 69. External Clock
VIH1
VIL1
Table 39. External Clock Drive
VCC = 2.7V to 6.0V
VCC = 4.0V to 6.0V
Symbol
Parameter
1/tCLCL
Oscillator Frequency
tCLCL
Clock Period
250
125
ns
tCHCX
High Time
100
50
ns
tCLCX
Low Time
100
50
ns
tCLCH
Rise Time
1.6
0.5
µs
tCHCL
Fall Time
1.6
0.5
µs
Min
Max
Min
Max
Units
0
4
0
8
MHz
85
Typical Characteristics
The following charts show typical behavior. These data are characterized, but not tested. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with
rail to rail output is used as clock source.
The power consumption in power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O
pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and
frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance,
VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranted to function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power Down mode with Watchdog timer enabled and Power Down mode
with Watchdog timer disabled represents the differential current drawn by the watchdog timer.
The difference between Power Down mode with Brown Out Detector enabled and Power Down mode with Watchdog timer
disabled represents the differential current drawn by the brown out detector.
Figure 70. Active Supply Current vs. Frequency
ACTIVE SUPPLY CURRENT vs. FREQUENCY
TA= 25˚C
35
Vcc= 6V
30
Vcc= 5.5V
I cc(mA)
25
Vcc= 5V
Vcc= 4.5V
20
Vcc= 4V
15
Vcc= 3.6V
Vcc= 3.3V
10
Vcc= 3.0V
Vcc= 2.7V
5
0
0
1
2
3
4
5
6
7
8
9
10
Frequency (MHz)
86
AT90S/LS2333 and AT90S/LS4433
11
12
13
14
15
AT90S/LS2333 and AT90S/LS4433
Figure 71. Active Supply Current vs. VCC
ACTIVE SUPPLY CURRENT vs. Vcc
FREQUENCY = 4 MHz
14
12
TA = 25˚C
TA = 85˚C
I cc(mA)
10
8
6
4
2
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
Figure 72. Idle Supply Current vs. Frequency
IDLE SUPPLY CURRENT vs. FREQUENCY
TA = 25˚C
18
Vcc= 6V
I cc(mA)
16
14
Vcc= 5.5V
12
Vcc= 5V
10
Vcc= 4.5V
8
Vcc= 4V
6
Vcc= 3.6V
Vcc= 3.3V
Vcc= 3.0V
4
Vcc= 2.7V
2
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Frequency (MHz)
87
Figure 73. Idle Supply Current vs. VCC
IDLE SUPPLY CURRENT vs. Vcc
FREQUENCY = 4 MHz
6
5
TA = 85˚C
4
I cc(mA)
TA = 25˚C
3
2
1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
Figure 74. Power Down Supply Current vs. VCC
POWER DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER DISABLED
25
TA = 85˚C
20
I cc(µΑ)
15
TA = 70˚C
10
5
TA = 45˚C
TA = 25˚C
0
2
2.5
3
3.5
4
4.5
Vcc(V)
88
AT90S/LS2333 and AT90S/LS4433
5
5.5
6
AT90S/LS2333 and AT90S/LS4433
Figure 75. Power Down Supply Current vs. VCC
POWER DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER ENABLED
120
100
I cc(µΑ)
80
TA = 85˚C
TA = 25˚C
60
40
20
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
Figure 76. Power Down Supply Current vs. VCC
POWER DOWN SUPPLY CURRENT vs. Vcc
BROWN OUT DETECTOR ENABLED
140
120
TA = 85˚C
100
TA = 25˚C
I cc(µΑ)
80
60
40
20
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
89
Figure 77. Analog Comparator Current vs. VCC
ANALOG COMPARATOR CURRENT vs. Vcc
0.9
0.8
0.7
TA = 25˚C
0.6
I cc(mA)
TA = 85˚C
0.5
0.4
0.3
0.2
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
Analog comparator offset voltage is measured as absolute offset
Figure 78. Analog Comparator Offset Voltage vs. Common Mode Voltage
ANALOG COMPARATOR OFFSET VOLTAGE vs.
COMMON MODE VOLTAGE
Vcc = 5V
18
16
TA = 25˚C
Offset Voltage (mV)
14
12
TA = 85˚C
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
3
Common Mode Voltage (V)
90
AT90S/LS2333 and AT90S/LS4433
3.5
4
4.5
5
AT90S/LS2333 and AT90S/LS4433
Figure 79. Analog Comparator Offset Voltage vs. Common Mode Voltage
ANALOG COMPARATOR OFFSET VOLTAGE vs.
COMMON MODE VOLTAGE
Vcc = 2.7V
10
TA = 25˚C
Offset Voltage (mV)
8
6
TA = 85˚C
4
2
0
0
0.5
1
1.5
2
2.5
3
Common Mode Voltage (V)
Figure 80. Analog Comparator Input Leakage Current
ANALOG COMPARATOR INPUT LEAKAGE CURRENT
VCC = 6V
TA = 25˚C
60
50
30
I
ACLK
(nA)
40
20
10
0
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
VIN (V)
91
Figure 81. Watchdog Oscillator Frequency vs. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. Vcc
1600
TA = 25˚C
1400
TA = 85˚C
F RC (KHz)
1200
1000
800
600
400
200
0
2
2.5
3
3.5
4
4.5
Vcc (V)
92
AT90S/LS2333 and AT90S/LS4433
5
5.5
6
AT90S/LS2333 and AT90S/LS4433
Sink and source capabilities of I/O ports are measured on one pin at a time.
Figure 82. Pull-Up Resistor Current vs. Input Voltage
PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V
120
TA = 25˚C
100
TA = 85˚C
I
OP (µA)
80
60
40
20
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOP (V)
Figure 83. Pull-Up Resistor Current vs. Input Voltage
PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V
30
TA = 25˚C
25
TA = 85˚C
15
I
OP (µA)
20
10
5
0
0
0.5
1
1.5
2
2.5
3
VOP (V)
93
Figure 84. I/O Pin Sink Current vs. Output Voltage
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
80
70
TA = 25˚C
60
I
OL (mA)
50
40
TA = 85˚C
30
20
10
0
0
0.5
1
1.5
2
2.5
3
VOL (V)
Figure 85. I/O Pin Source Current vs. Output Voltage
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
18
TA = 25˚C
16
14
TA = 85˚C
10
8
I
OH (mA)
12
6
4
2
0
0
0.5
1
1.5
2
2.5
3
VOH (V)
94
AT90S/LS2333 and AT90S/LS4433
3.5
4
4.5
5
AT90S/LS2333 and AT90S/LS4433
Figure 86. I/O Pin Sink Current vs. Output Voltage
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
30
TA = 25˚C
25
20
I
OL (mA)
TA = 85˚C
15
10
5
0
0
0.5
1
1.5
2
VOL (V)
Figure 87. I/O Pin Source Current vs. Output Voltage
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
6
TA = 25˚C
5
4
3
I
OH (mA)
TA = 85˚C
2
1
0
0
0.5
1
1.5
2
2.5
3
VOH (V)
95
Figure 88. I/O Pin Input Threshold Voltage vs. VCC
I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
TA = 25˚C
2.5
Threshold Voltage (V)
2
1.5
1
0.5
0
2.7
4.0
5.0
Vcc
Figure 89. I/O Pin Input Hysteresis vs. VCC
I/O PIN INPUT HYSTERESIS vs. Vcc
TA = 25˚C
0.18
0.16
Input hysteresis (V)
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
2.7
4.0
Vcc
96
AT90S/LS2333 and AT90S/LS4433
5.0
AT90S/LS2333 and AT90S/LS4433
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
$22 ($42)
$21 ($41)
$20 ($40)
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2B)
$0A ($2A)
$09 ($29)
$08 ($28)
$07 ($27)
$06 ($26)
$05 ($25)
$04 ($24)
$03 ($23)
SREG
Reserved
SP
Reserved
GIMSK
GIFR
TIMSK
TIFR
Reserved
Reserved
MCUCR
MCUSR
TCCR0
TCNT0
Reserved
Reserved
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1H
OCR1L
Reserved
Reserved
ICR1H
ICR1L
Reserved
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEAR
EEDR
EECR
Reserved
Reserved
Reserved
PORTB
DDRB
PINB
PORTC
DDRC
PINC
PORTD
DDRD
PIND
SPDR
SPSR
SPCR
UDR
UCSRA
UCSRB
UBRR
ACSR
ADMUX
ADCSR
ADCH
ADCL
UBRRHI
I
SP7
T
SP6
H
SP5
S
SP4
V
SP3
N
SP2
Z
SP1
C
SP0
page 17
page 17
page 17
INT1
INTF1
TOIE1
TOV1
INT0
INTF0
OCIE1
OCF1
-
-
-
-
-
-
-
-
TICIE1
ICF1
-
TOIE0
TOV0
-
page 23
page 24
page 24
page 25
SE
-
SM
-
ISC11
WDRF
-
ISC10
BORF
CS02
ISC01
EXTRF
CS01
ISC00
PORF
CS00
page 26
page 22
page 29
page 30
CTC1
CS12
PWM11
CS11
PWM10
CS10
page 31
page 32
page 33
page 33
page 34
page 34
Timer/Counter0 (8 Bits)
COM11
COM10
ICNC1
ICES1
Timer/Counter1 - Counter Register High Byte
Timer/Counter1 - Counter Register Low Byte
Timer/Counter1 - Output Compare Register High Byte
Timer/Counter1 - Output Compare Register Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
-
-
EEPROM Address Register
EEPROM Data Register
-
PORTD7
PORTD6
DDD7
DDD6
PIND7
PIND6
SPI Data Register
SPIF
WCOL
SPIE
SPE
UART I/O Data Register
RXC
TXC
RXCIE
TXCIE
UART Baud Rate Register
AINBG
ACD
ADCBG
ADEN
ADSC
ADC7
ADC6
-
WDTOE
page 34
page 34
WDE
WDP2
WDP1
WDP0
page 36
page 38
page 38
page 38
-
-
EERIE
EEMWE
EEWE
EERE
PORTB5
DDB5
PINB5
PORTC5
DDC5
PINC5
PORTD5
DDD5
PIND5
PORTB4
DDB4
PINB4
PORTC4
DDC4
PINC4
PORTD4
DDD4
PIND4
PORTB3
DDB3
PINB3
PORTC3
DDC3
PINC3
PORTD3
DDD3
PIND3
PORTB2
DDB2
PINB2
PORTC2
DDC2
PINC2
PORTD2
DDD2
PIND2
PORTB1
DDB1
PINB1
PORTC1
DDC1
PINC1
PORTD1
DDD1
PIND1
PORTB0
DDB0
PINB0
PORTC0
DDC0
PINC0
PORTD0
DDD0
PIND0
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
UDRE
UDRIE
FE
RXEN
OR
TXEN
CHR9
RXB8
TXB8
ACO
ADFR
ADC5
ACI
ADIF
ADC4
ACIE
ADIE
ADC3
ACIC
ACIS1
MUX2
MUX1
ADPS2
ADPS1
ADC9
ADC2
ADC1
UART Baud Rate Register High
ACIS0
MUX0
ADPS0
ADC8
ADC0
page 59
page 59
page 59
page 64
page 64
page 64
page 66
page 66
page 66
page 43
page 43
page 42
page 47
page 47
page 48
page 50
page 50
page 55
page 56
page 57
page 57
page 50
97
Register Summary (Continued)
Address
Name
$02 ($22)
$01 ($21)
$00 ($20)
Reserved
Reserved
Reserved
Notes:
98
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
Instruction Set Summary
Mnemonics
Operands
Description
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
ADC
Rd, Rr
Add with Carry two Registers
ADIW
Rdl,K
Add Immediate to Word
SUB
Rd, Rr
Subtract two Registers
SUBI
Rd, K
Subtract Constant from Register
SBC
Rd, Rr
Subtract with Carry two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
SBIW
Rdl,K
Subtract Immediate from Word
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd,K
Set Bit(s) in Register
CBR
Rd,K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
RCALL
k
Relative Subroutine Call
ICALL
Indirect Call to (Z)
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less Than Zero, Signed
BRHS
k
Branch if Half Carry Flag Set
BRHC
k
Branch if Half Carry Flag Cleared
BRTS
k
Branch if T Flag Set
BRTC
k
Branch if T Flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Branch if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
Operation
Flags
#Clocks
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd ⊕ Rr
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Rd ← Rd • ($FF - K)
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← $FF
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
PC ← Z
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
Rd − Rr − C
Rd − K
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2
2
3
3
4
4
1/2/3
1
1
1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
99
Instruction Set Summary (Continued)
Mnemonics
Operands
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
LDI
Rd, K
LD
Rd, X
LD
Rd, X+
LD
Rd, - X
LD
Rd, Y
LD
Rd, Y+
LD
Rd, - Y
LDD
Rd,Y+q
LD
Rd, Z
LD
Rd, Z+
LD
Rd, -Z
LDD
Rd, Z+q
LDS
Rd, k
ST
X, Rr
ST
X+, Rr
ST
- X, Rr
ST
Y, Rr
ST
Y+, Rr
ST
- Y, Rr
STD
Y+q,Rr
ST
Z, Rr
ST
Z+, Rr
ST
-Z, Rr
STD
Z+q,Rr
STS
k, Rr
LPM
IN
Rd, P
OUT
P, Rr
PUSH
Rr
POP
Rd
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
CBI
P,b
LSL
Rd
LSR
Rd
ROL
Rd
ROR
Rd
ASR
Rd
SWAP
Rd
BSET
s
BCLR
s
BST
Rr, b
BLD
Rd, b
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
100
Description
Operation
Flags
#Clocks
Move Between Registers
Load Immediate
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
In Port
Out Port
Push Register on Stack
Pop Register from Stack
Rd ← Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
(X) ← Rr
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
(k) ← Rr
R0 ← (Z)
Rd ← P
P ← Rr
STACK ← Rr
Rd ← STACK
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
No Operation
Sleep
Watchdog Reset
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Rd(n) ← Rd(n+1), n=0..6
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C←1
C←0
N←1
N←0
Z←1
Z←0
I←1
I←0
S←1
S←0
V←1
V←0
T←1
T←0
H←1
H←0
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
AT90S/LS2333 and AT90S/LS4433
AT90S/LS2333 and AT90S/LS4433
Ordering Information
Power Supply
Speed (MHz)
2.7 - 6.0V
4
4.0 - 6.0V
2.7 - 6.0V
4.0 - 6.0V
8
4
8
Ordering Code
Package
Operation Range
AT90LS2333-4AC
AT90LS2333-4PC
32A
28P3
Commercial
(0°C to 70°C)
AT90LS2333-4AI
AT90LS2333-4PI
32A
28P3
Industrial
(-40°C to 85°C)
AT90S2333-8AC
AT90S2333-8PC
32A
28P3
Commercial
(0°C to 70°C)
AT90S2333-8AI
AT90S2333-8PI
32A
28P3
Industrial
(-40°C to 85°C)
AT90LS4433-4AC
AT90LS4433-4PC
32A
28P3
Commercial
(0°C to 70°C)
AT90LS4433-4AI
AT90LS4433-4PI
32A
28P3
Industrial
(-40°C to 85°C)
AT90S4433-8AC
AT90S4433-8PC
32A
28P3
Commercial
(0°C to 70°C)
AT90S4433-8AI
AT90S4433-8PI
32A
28P3
Industrial
(-40°C to 85°C)
Package Type
28P3
28-lead, 0.300” Wide, Plastic Dual in Line Package (PDIP)
32A
32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
101
Packaging Information
28P3, 28-lead, 0.300” Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flat Package (TQFP)
Dimensions in Millimeters and (Inches)
PIN 1 ID
9.00 (0.354) BSC
0.45 (0.018)
0.30 (0.012)
0.80 (0.031) BSC
9.00 (0.354) BSC
7.00 (0.276) BSC
0.20 (0.008)
0.10 (0.004)
0˚
7˚
0.75 (0.030)
0.45 (0.018)
102
1.20 (0.047) MAX
AT90S/LS2333 and AT90S/LS4433
0.15 (0.006)
0.05 (0.002)
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Atmel Colorado Springs
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Europe
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Atmel Rousset
Atmel U.K., Ltd.
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL (44) 1276-686-677
FAX (44) 1276-686-697
Zone Industrielle
13106 Rousset Cedex
France
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life suppor t devices or systems.
Marks bearing
®
and/or
™
are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
1042D–04/99/xM
工商网监
湘ICP备2023018690号
