Features
• Core
•
•
•
•
•
•
•
– ARM® Cortex®-M3 revision 2.0 running at up to 64 MHz
– Memory Protection Unit (MPU)
– Thumb®-2 instruction set
Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1
products
Memories
– 512 Kbytes Single Plane (SAM3S8) embedded Flash, 128-bit wide access, memory
accelerator
– 512 Kbytes Dual Plane (SAM3SD8) embedded Flash, 128-bit wide access, memory
accelerator
– 64 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash
support
System
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low-power 32.768 kHz for RTC or device clock
– RTC with Gregorian and Persian Calendar mode, waveform generation in lowpower modes
– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
frequency for device startup. In-application trimming access for frequency
adjustment
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– Two PLLs up to 130 MHz for device clock and for USB
– Temperature Sensor
– Up to 24 peripheral DMA (PDC) channels
Low Power Modes
– Sleep and Backup modes, down to 1 µA in Backup mode
– Ultra low-power RTC
Peripherals
– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip
Transceiver
– Up to 3 USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode
– Two 2-wire UARTs
– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller
(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)
– 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM
mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper
Motor
– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time
Generator Counter for Motor Control
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 15-channel, 1Msps ADC with differential input mode and programmable gain
stage and auto calibration
– One 2-channel 12-bit 1Msps DAC
– One Analog Comparator with flexible input selection, Selectable input hysteresis
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
I/O
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel
Capture Mode
Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
AT91SAM
ARM-based
Flash MCU
SAM3S8/SD8
Series
Summary
11090BS–ATARM–22-Oct-13
1.
Description
The Atmel SAM3S8/SD8 series is a member of a family of Flash microcontrollers based on the
high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of
64 MHz and features up to 512 Kbytes of Flash (dual plane on SAM3SD8) and up to 64 Kbytes
of SRAM. The peripheral set includes a Full Speed USB Device port with embedded transceiver,
a High Speed MCI for SDIO/SD/MMC, an External Bus Interface featuring a Static Memory Controller providing connection to SRAM, PSRAM, NOR Flash, LCD Module and NAND Flash, 2(3)x
USARTs, (3 on SAM3SD8C) 2x UARTs, 2x TWIs, 3x SPI, an I2S, as well as 1 PWM timer, 6x
general-purpose 16-bit timers (with stepper motor and quadrature decoder logic support), an
RTC, a 12-bit ADC, a 12-bit DAC and an analog comparator.
The SAM3S8/SD8 series is ready for capacitive touch thanks to the QTouch® library, offering an
easy way to implement buttons, wheels and sliders.
The SAM3S8/SD8 device is a medium range general purpose microcontroller with the best ratio
in terms of reduced power consumption, processing power and peripheral set. This enables the
SAM3S8/SD8 to sustain a wide range of applications including consumer, industrial control, and
PC peripherals.
It operates from 1.62V to 3.6V and is available in 64- and 100-pin QFP, 64-pin QFN, and 100-pin
BGA packages.
The SAM3S8/SD8 series is the ideal migration path from the SAM7S series for applications that
require more performance. The SAM3S8/SD8 series is pin-to-pin compatible with the SAM7S
series.
1.1
Configuration Summary
The SAM3S8/SD8 series devices differ in memory size, package and features. Table 1-1 summarizes the configurations of the device family.
Table 1-1.
Configuration Summary
Feature
SAM3S8B
SAM3S8C
SAM3SD8B
SAM3SD8C
Flash
512 Kbytes
512 Kbytes
512 Kbytes
512 Kbytes
SRAM
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
Package
LQFP64
QFN64
LQFP100
BGA100
LQFP64
QFN64
LQFP100
BGA100
Number of PIOs
47
79
(2)
47
(2)
79
(2)
16 channels(2)
12-bit ADC
11 channels
16 channels
11 channels
12-bit DAC
2 channels
2 channels
2 channels
2 channels
Timer Counter
Channels
6
6
6
6
PDC Channels
22
22
24
24
USART/UART
HSMCI
(1)
1 port/4 bits
-
(1)
2/2
2/2
External Bus
Interface
Notes:
(1)
1 port/4 bits
2/2
1 port/4 bits
8-bit data,
4 chip selects,
24-bit address
-
3/2(1)
1 port/4 bits
8-bit data,
4 chip selects,
24-bit address
1. Full Modem support on USART1.
2. One channel is reserved for internal temperature sensor.
2
SAM3S8/SD8 Summary
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
2. Block Diagram
TST
System Controller
UT
VD
DO
VD
DI
N
JT
AG
SE
L
SAM3S8/SD8 100-pin version Block Diagram
TD
TDI
TMO
TC S/S
K/ WD
SW IO
CL
K
Figure 2-1.
Voltage
Regulator
PCK0-PCK2
PLLA
PLLB
PMC
RC Osc
12/8/4 MHz
XIN
XOUT
JTAG & Serial Wire
In-Circuit Emulator
3-20 MHz
Osc
Cortex M-3 Processor
Fmax 64 MHz
SUPC
24-Bit
N
SysTick Counter V
I
C
MPU
XIN32
XOUT32
Osc 32 kHz
ERASE
RC 32 kHz
VDDIO
8 GPBREG
I/D
Flash
Unique
Identifier
512 KBytes FLASH
SRAM
ROM
SAM3S8 Single Bank 64 KBytes 16 KBytes
SAM3SD8 Dual Bank
S
3-layer AHB Bus Matrix Fmax 64 MHz
VDDCORE
RTT
VDDPLL
RTCOUT0
POR
RSTC
WDT
Peripheral
Bridge
SM
2668 USB 2.0
Bytes
Full
FIFO Speed
PIOA / PIOB / PIOC
TWCK0
TWD0
TWCK1
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
RXD2
TXD2
SCK2
RTS2
CTS2
TWI0
PDC
TWI1
PDC
UART0
PDC
UART1
DDP
DDM
External Bus
Interface
NAND Flash
Logic
PDC
PIO
NRST
Transceiver
RTC
RTCOUT1
Static Memory
Controller
USART0
PDC
PDC
PIODC[7:0]
PIODCEN1
PIODCEN2
PIODCCLK
USART1
PIO
PDC
USART2
(SAM3SD8 Only)
Timer Counter B
TIOA[0:2]
TIOB[0:2]
TC[0..2]
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
TF
TK
TD
RD
RK
RF
PDC
PDC
TCLK[0:2]
SPI
PDC
SSC
TCLK[3:5]
Timer Counter B
TIOA[3:5]
TIOB[3:5]
PDC
ADVREF
DAC0
DAC1
DATRG
MCCK
MCCDA
MCDA[0..3]
TC[3..5]
High Speed MCI
PWMH[0:3]
PWML[0:3]
PWMFI0
ADTRG
AD[0..14]
D[7:0]
A[0:23]
A21/NANDALE
A22/NANDCLE
NCS0
NCS1
NCS2
NCS3
NRD
NWE
NANDOE
NANDWE
NWAIT
PWM
PDC
Temp. Sensor
12-bit ADC
Analog
Comparator
ADVREF
ADC Ch.
CRC Unit
PDC
12-bit DAC
PDC
3
11090BS–ATARM–22-Oct-13
TST
System Controller
DO
VD
DI
N
VD
JT
AG
SE
L
UT
SAM3S8/SD8 64-pin version Block Diagram
TD
TDI
TMO
TC S/S
K/ W D
SW IO
CL
K
Figure 2-2.
Voltage
Regulator
PCK0-PCK2
PLLA
PLLB
PMC
RC Osc
12/8/4 MHz
XIN
XOUT
JTAG & Serial Wire
In-Circuit Emulator
3-20 MHz
Osc
Cortex M-3 Processor
Fmax 64 MHz
SUPC
24-Bit
N
SysTick Counter V
I
C
MPU
XIN32
XOUT32
Osc 32 kHz
ERASE
RC 32 kHz
VDDIO
8 GPBREG
I/D
Flash
Unique
Identifier
512 KBytes FLASH
SRAM
ROM
SAM3S8 Single Bank 64 KBytes 16 KBytes
SAM3SD8 Dual Bank
S
3-layer AHB Bus Matrix Fmax 64 MHz
VDDCORE
RTT
VDDPLL
RTCOUT0
POR
RSTC
NRST
WDT
Peripheral
Bridge
SM
2668 USB 2.0
Bytes
Full
FIFO Speed
PIOA / PIOB
TWCK0
TWD0
TWI0
TWCK1
TWD1
TWI1
URXD0
UTXD0
UART0
URXD1
UTXD1
UART1
RXD0
TXD0
SCK0
RTS0
CTS0
DDP
DDM
PDC
PDC
PDC
PDC
PIODC[7:0]
PIODCEN1
PIODCEN2
PIODCCLK
PIO
PDC
USART0
PDC
PDC
SPI
PIO
USART1
PIO
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
Transceiver
RTC
RTCOUT1
PDC
PDC
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
ADTRG
AD[0..14]
SSC
TC[0..2]
PDC
PWM
PDC
4
MCCK
MCCDA
MCDA[0..3]
High Speed MCI
Temp. Sensor
12-bit ADC
ADVREF
DAC0
DAC1
DATRG
TF
TK
TD
RD
RK
RF
Timer Counter A
PWMH[0:3]
PWML[0:3]
PWMFI0
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
PDC
Analog
Comparator
PDC
CRC Unit
12-bit DAC
ADVREF
ADC Ch.
SAM3S8/SD8 Summary
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
3. Signal Description
Table 3-1 gives details on signal names classified by peripheral.
Table 3-1.
Signal Description List
Signal Name
Function
Type
Active
Level
Voltage
reference
Comments
Power Supplies
VDDIO
Peripherals I/O Lines and USB transceiver
Power Supply
Power
1.62V to 3.6V
VDDIN
Voltage Regulator Input, ADC, DAC and
Analog Comparator Power Supply
Power
1.8V to 3.6V(4)
VDDOUT
Voltage Regulator Output
Power
1.8V Output
VDDPLL
Oscillator and PLL Power Supply
Power
1.62 V to 1.95V
VDDCORE
Power the core, the embedded memories
and the peripherals
Power
GND
Ground
Ground
1.62V to 1.95V
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
PCK0 - PCK2
Input
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
Output
Input
Output
Programmable Clock Output
VDDIO
Reset State:
- PIO Input
- Internal Pull-up enabled
- Schmitt Trigger enabled(1)
Output
Real Time Clock
RTCOUT0
Programmable RTC waveform output
Output
RTCOUT1
Programmable RTC waveform output
Output
VDDIO
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
Serial Wire/JTAG Debug Port - SWJ-DP
TCK/SWCLK
Test Clock/Serial Wire Clock
Input
TDI
Test Data In
Input
TDO/TRACESWO
Test Data Out / Trace Asynchronous Data
Out
Output
TMS/SWDIO
Test Mode Select /Serial Wire Input/Output
Input / I/O
JTAGSEL
JTAG Selection
Input
VDDIO
High
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled(5)
- Schmitt Trigger enabled(1)
Permanent Internal
pull-down
5
11090BS–ATARM–22-Oct-13
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Voltage
reference
Comments
Flash Memory
Flash and NVM Configuration Bits Erase
Command
ERASE
Input
High
VDDIO
Reset State:
- Erase Input
- Internal pull-down enabled
- Schmitt Trigger enabled(1)
Reset/Test
NRST
Synchronous Microcontroller Reset
I/O
Low
VDDIO
TST
Test Select
Permanent Internal
pull-up
Permanent Internal
pull-down
Input
Universal Asynchronous Receiver Transceiver - UARTx
URXDx
UART Receive Data
Input
UTXDx
UART Transmit Data
Output
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31
Parallel IO Controller A
I/O
PB0 - PB14
Parallel IO Controller B
I/O
PC0 - PC31
Parallel IO Controller C
I/O
VDDIO
Reset State:
- PIO or System IOs(2)
- Internal pull-up enabled
- Schmitt Trigger enabled(1)
PIO Controller - Parallel Capture Mode
PIODC0-PIODC7
Parallel Capture Mode Data
Input
PIODCCLK
Parallel Capture Mode Clock
Input
PIODCEN1-2
Parallel Capture Mode Enable
Input
VDDIO
External Bus Interface
D0 - D7
Data Bus
I/O
A0 - A23
Address Bus
NWAIT
External Wait Signal
Output
Input
Low
Static Memory Controller - SMC
NCS0 - NCS3
Chip Select Lines
Output
Low
NRD
Read Signal
Output
Low
NWE
Write Enable
Output
Low
NAND Flash Logic
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
High Speed Multimedia Card Interface - HSMCI
MCCK
Multimedia Card Clock
I/O
MCCDA
Multimedia Card Slot A Command
I/O
MCDA0 - MCDA3
Multimedia Card Slot A Data
I/O
6
SAM3S8/SD8 Summary
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Voltage
reference
Comments
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
CTSx
USARTx Clear To Send
DTR1
USART1 Data Terminal Ready
DSR1
USART1 Data Set Ready
DCD1
USART1 Data Carrier Detect
RI1
USART1 Ring Indicator
Output
Input
I/O
Input
Output
Input
Synchronous Serial Controller - SSC
TD
SSC Transmit Data
Output
RD
SSC Receive Data
Input
TK
SSC Transmit Clock
I/O
RK
SSC Receive Clock
I/O
TF
SSC Transmit Frame Sync
I/O
RF
SSC Receive Frame Sync
I/O
Timer/Counter - TC
TCLKx
TC Channel x External Clock Input
Input
TIOAx
TC Channel x I/O Line A
I/O
TIOBx
TC Channel x I/O Line B
I/O
Pulse Width Modulation Controller- PWMC
PWMHx
PWM Waveform Output High for channel x
PWMLx
PWM Waveform Output Low for channel x
PWMFI0
PWM Fault Input
Output
only output in
complementary mode
when dead time insertion
is enabled.
Output
Input
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
I/O
MOSI
Master Out Slave In
I/O
SPCK
SPI Serial Clock
I/O
SPI_NPCS0
SPI Peripheral Chip Select 0
I/O
Low
SPI_NPCS1 SPI_NPCS3
SPI Peripheral Chip Select
Output
Low
7
11090BS–ATARM–22-Oct-13
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Voltage
reference
Comments
Two-Wire Interface- TWI
TWDx
TWIx Two-wire Serial Data
I/O
TWCKx
TWIx Two-wire Serial Clock
I/O
Analog
ADC, DAC and Analog Comparator
Reference
ADVREF
Analog
12-bit Analog-to-Digital Converter - ADC
AD0-AD14
Analog Inputs
Analog,
Digital
ADTRG
ADC Trigger
Input
VDDIO
12-bit Digital-to-Analog Converter - DAC
DAC0 - DAC1
Analog output
DACTRG
DAC Trigger
Analog,
Digital
Input
VDDIO
Fast Flash Programming Interface - FFPI
PGMEN0PGMEN2
Programming Enabling
Input
PGMM0-PGMM3
Programming Mode
Input
PGMD0-PGMD15
Programming Data
I/O
PGMRDY
Programming Ready
Output
High
PGMNVALID
Data Direction
Output
Low
PGMNOE
Programming Read
Input
Low
PGMCK
Programming Clock
Input
PGMNCMD
Programming Command
Input
VDDIO
VDDIO
Low
USB Full Speed Device
DDM
DDP
Note:
USB Full Speed Data USB Full Speed Data +
Analog,
Digital
VDDIO
Reset State:
- USB Mode
- Internal Pull-down(3)
1. Schmitt Triggers can be disabled through PIO registers.
2. Some PIO lines are shared with System I/Os.
3. Refer to USB Section of the product Electrical Characteristics for information on Pull-down value in USB Mode.
4. See “Typical Powering Schematics” Section for restrictions on voltage range of Analog Cells.
5. TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up corresponding to this
PIO line must be enabled to avoid current consumption due to floating input.
8
SAM3S8/SD8 Summary
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
4. Package and Pinout
SAM3S8/SD8 devices are pin-to-pin compatible with AT91SAM7S legacy products for 64-pin
version. Furthermore, SAM3S8/SD8 products have new functionalities referenced in italic in
Table 4-1, Table 4-3.
4.1
4.1.1
SAM3S8C/8DC Package and Pinout
100-Lead LQFP Package Outline
Figure 4-1.
Orientation of the 100-lead LQFP Package
75
51
76
50
100
26
1
4.1.2
25
100-ball TFBGA Package Outline
The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its
dimensions are 9 x 9 x 1.1 mm. Figure 4-2 shows the orientation of the 100-ball TFBGA
Package.
Figure 4-2.
Orientation of the 100-ball TFBGA Package
TOP VIEW
10
9
8
7
6
5
4
3
2
1
BALL A1
A
B
C
D
E
F
G
H
J
K
9
11090BS–ATARM–22-Oct-13
4.1.3
100-Lead LQFP Pinout
Table 4-1.
SAM3S8C/SD8C 100-lead LQFP pinout
1
ADVREF
26
GND
51
TDI/PB4
76
TDO/TRACESWO/
PB5
2
GND
27
VDDIO
52
PA6/PGMNOE
77
JTAGSEL
3
PB0/AD4
28
PA16/PGMD4
53
PA5/PGMRDY
78
PC18
4
PC29/AD13
29
PC7
54
PC28
79
TMS/SWDIO/PB6
5
PB1/AD5
30
PA15/PGMD3
55
PA4/PGMNCMD
80
PC19
6
PC30/AD14
31
PA14/PGMD2
56
VDDCORE
81
PA31
7
PB2/AD6
32
PC6
57
PA27/PGMD15
82
PC20
8
PC31
33
PA13/PGMD1
58
PC8
83
TCK/SWCLK/PB7
9
PB3/AD7
34
PA24/PGMD12
59
PA28
84
PC21
10
VDDIN
35
PC5
60
NRST
85
VDDCORE
11
VDDOUT
36
VDDCORE
61
TST
86
PC22
12
PA17/PGMD5/AD0
37
PC4
62
PC9
87
ERASE/PB12
13
PC26
38
PA25/PGMD13
63
PA29
88
DDM/PB10
14
PA18/PGMD6/AD1
39
PA26/PGMD14
64
PA30
89
DDP/PB11
15
PA21/PGMD9/AD8
40
PC3
65
PC10
90
PC23
16
VDDCORE
41
PA12/PGMD0
66
PA3
91
VDDIO
17
PC27
42
PA11/PGMM3
67
PA2/PGMEN2
92
PC24
18
PA19/PGMD7/AD2
43
PC2
68
PC11
93
PB13/DAC0
19
PC15/AD11
44
PA10/PGMM2
69
VDDIO
94
PC25
20
PA22/PGMD10/AD
9
45
GND
70
GND
95
GND
21
PC13/AD10
46
PA9/PGMM1
71
PC14
96
PB8/XOUT
22
PA23/PGMD11
47
PC1
72
PA1/PGMEN1
97
PB9/PGMCK/XIN
23
PC12/AD12
48
PA8/XOUT32/
PGMM0
73
PC16
98
VDDIO
24
PA20/PGMD8/AD3
49
PA7/XIN32/
PGMNVALID
74
PA0/PGMEN0
99
PB14/DAC1
25
PC0
50
VDDIO
75
PC17
100
VDDPLL
10
SAM3S8/SD8 Summary
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
4.1.4
100-Ball TFBGA Pinout
Table 4-2.
SAM3S8C/SD8C 100-ball TFBGA pinout
A1
PB1/AD5
C6
TCK/SWCLK/PB7
F1
PA18/PGMD6/AD1
H6
PC4
A2
PC29
C7
PC16
F2
PC26
H7
PA11/PGMM3
A3
VDDIO
C8
PA1/PGMEN1
F3
VDDOUT
H8
PC1
A4
PB9/PGMCK/XIN
C9
PC17
F4
GND
H9
PA6/PGMNOE
A5
PB8/XOUT
C10
PA0/PGMEN0
F5
VDDIO
H10
TDI/PB4
A6
PB13/DAC0
D1
PB3/AD7
F6
PA27/PGMD15
J1
PC15/AD11
A7
DDP/PB11
D2
PB0/AD4
F7
PC8
J2
PC0
A8
DDM/PB10
D3
PC24
F8
PA28
J3
PA16/PGMD4
A9
TMS/SWDIO/PB6
D4
PC22
F9
TST
J4
PC6
A10
JTAGSEL
D5
GND
F10
PC9
J5
PA24/PGMD12
B1
PC30
D6
GND
G1
PA21/PGMD9/AD8
J6
PA25/PGMD13
B2
ADVREF
D7
VDDCORE
G2
PC27
J7
PA10/PGMM2
B3
GNDANA
D8
PA2/PGMEN2
G3
PA15/PGMD3
J8
GND
B4
PB14/DAC1
D9
PC11
G4
VDDCORE
J9
VDDCORE
B5
PC21
D10
PC14
G5
VDDCORE
J10
VDDIO
B6
PC20
E1
PA17/PGMD5/AD
0
G6
PA26/PGMD14
K1
PA22/PGMD10/AD
9
B7
PA31
E2
PC31
G7
PA12/PGMD0
K2
PC13/AD10
B8
PC19
E3
VDDIN
G8
PC28
K3
PC12/AD12
B9
PC18
E4
GND
G9
PA4/PGMNCMD
K4
PA20/PGMD8/AD3
B10
TDO/TRACESWO/
PB5
E5
GND
G10
PA5/PGMRDY
K5
PC5
C1
PB2/AD6
E6
NRST
H1
PA19/PGMD7/AD2
K6
PC3
C2
VDDPLL
E7
PA29/AD13
H2
PA23/PGMD11
K7
PC2
C3
PC25
E8
PA30/AD14
H3
PC7
K8
PA9/PGMM1
C4
PC23
E9
PC10
H4
PA14/PGMD2
K9
PA8/XOUT32/PGM
M0
C5
ERASE/PB12
E10
PA3
H5
PA13/PGMD1
K10
PA7/XIN32/
PGMNVALID
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11090BS–ATARM–22-Oct-13
4.2
4.2.1
SAM3S8B/D8B Package and Pinout
64-Lead LQFP Package Outline
Figure 4-3.
Orientation of the 64-lead LQFP Package
33
48
49
32
64
17
16
1
4.2.2
64-lead QFN Package Outline
Figure 4-4.
Orientation of the 64-lead QFN Package
64
1
48
16
33
17
12
49
TOP VIEW
32
SAM3S8/SD8 Summary
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
4.2.3
64-Lead LQFP and QFN Pinout
Table 4-3.
64-pin SAM3S8B/D8B pinout
1
ADVREF
17
GND
33
TDI/PB4
49
TDO/TRACESWO/
PB5
2
GND
18
VDDIO
34
PA6/PGMNOE
50
JTAGSEL
3
PB0/AD4
19
PA16/PGMD4
35
PA5/PGMRDY
51
TMS/SWDIO/PB6
4
PB1/AD5
20
PA15/PGMD3
36
PA4/PGMNCMD
52
PA31
5
PB2/AD6
21
PA14/PGMD2
37
PA27/PGMD15
53
TCK/SWCLK/PB7
6
PB3/AD7
22
PA13/PGMD1
38
PA28
54
VDDCORE
7
VDDIN
23
PA24/PGMD12
39
NRST
55
ERASE/PB12
8
VDDOUT
24
VDDCORE
40
TST
56
DDM/PB10
9
PA17/PGMD5/
AD0
25
PA25/PGMD13
41
PA29
57
DDP/PB11
10
PA18/PGMD6/
AD1
26
PA26/PGMD14
42
PA30
58
VDDIO
11
PA21/PGMD9/
AD8
27
PA12/PGMD0
43
PA3
59
PB13/DAC0
12
VDDCORE
28
PA11/PGMM3
44
PA2/PGMEN2
60
GND
13
PA19/PGMD7/
AD2
29
PA10/PGMM2
45
VDDIO
61
XOUT/PB8
14
PA22/PGMD10/
AD9
30
PA9/PGMM1
46
GND
62
XIN/PGMCK/PB9
15
PA23/PGMD11
31
PA8/XOUT32/
PGMM0
47
PA1/PGMEN1
63
PB14/DAC1
16
PA20/PGMD8/
AD3
32
PA7/XIN32/
PGMNVALID
48
PA0/PGMEN0
64
VDDPLL
Note:
The bottom pad of the QFN package must be connected to ground.
13
11090BS–ATARM–22-Oct-13
5. Power Considerations
5.1
Power Supplies
The SAM3S8/SD8 has several types of power supply pins:
• VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage
ranges from 1.62V to 1.95V.
• VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), USB transceiver, Backup
part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V.
• VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply.
Voltage ranges from 1.8V to 3.6V.
• VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator. Voltage
ranges from 1.62V to 1.95V.
5.2
Voltage Regulator
The SAM3S8/SD8 embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is designed to supply the internal core of SAM3S8/SD8. It features two
operating modes:
• In Normal mode, the voltage regulator consumes less than 700 µA static current and draws
80 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current
depending on the required load current. In Wait Mode quiescent current is only 7 µA.
• In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT)
is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach
Normal mode is less than 100 µs.
For adequate input and output power supply decoupling/bypassing, refer to the “Voltage Regulator” section in the “Electrical Characteristics” section of the datasheet.
5.3
Typical Powering Schematics
The SAM3S8/SD8 supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. Figure 5-1 below shows the power
schematics.
As VDDIN powers the voltage regulator, the ADC, DAC and the analog comparator, when the
user does not want to use the embedded voltage regulator, it can be disabled by software via
the SUPC (note that this is different from Backup mode).
14
SAM3S8/SD8 Summary
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
Figure 5-1.
Single Supply
VDDIO
Main Supply
(1.8V-3.6V)
USB
Transceivers.
ADC, DAC
Analog Comp.
VDDIN
VDDOUT
Voltage
Regulator
VDDCORE
VDDPLL
Note:
Restrictions
With Main Supply < 2.0 V, USB and ADC/DAC and Analog comparator are not usable.
With Main Supply ≥ 2.0V and < 3V, USB is not usable.
With Main Supply ≥ 3V, all peripherals are usable.
Figure 5-2.
Core Externally Supplied
VDDIO
Main Supply
(1.62V-3.6V)
USB
Transceivers.
Can be the
same supply
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
ADC, DAC
Analog Comp.
VDDIN
VDDOUT
VDDCORE Supply
(1.62V-1.95V)
Voltage
Regulator
VDDCORE
VDDPLL
Note:
Restrictions
With Main Supply < 2.0V, USB is not usable.
With VDDIN < 2.0V, ADC, DAC and Analog comparator are not usable.
With Main Supply ≥ 2.0V and < 3V, USB is not usable.
With Main Supply and VDDIN ≥ 3V, all peripherals are usable.
Figure 5-3 below provides an example of the powering scheme when using a backup battery.
Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch
off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after
backup reset). External wake-up of the system can be from a push button or any signal. See
Section 5.6 “Wake-up Sources” for further details.
15
11090BS–ATARM–22-Oct-13
Figure 5-3.
Backup Battery
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
Backup
Battery
VDDIO
USB
Transceivers.
+
ADC, DAC
Analog Comp.
VDDIN
Main Supply
IN
OUT
3.3V
LDO
VDDOUT
Voltage
Regulator
VDDCORE
ON/OFF
VDDPLL
PIOx (Output)
WAKEUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
5.4
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator,
the main crystal oscillator or the PLLA. The power management controller can be used to adapt
the frequency and to disable the peripheral clocks.
5.5
Low-power Modes
The various low-power modes of the SAM3S8/SD8 are described below:
5.5.1
Backup Mode
The purpose of backup mode is to achieve the lowest power consumption possible in a system
which is performing periodic wake-ups to perform tasks but not requiring fast startup time
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