SAM D21/DA1 Family
Low-Power, 32-bit Cortex-M0+ MCU with Advanced Analog
and PWM
Features
•
•
•
•
•
Processor
®
®
– Arm Cortex -M0+ CPU running at up to 48 MHz
• Single-cycle hardware multiplier
• Micro Trace Buffer (MTB)
Memories
– 4/2/1/0.5 KB Read-While-Write (RWWEE) Flash section (not available on 256 KB devices)
– 256/128/64/32/16 KB in-system self-programmable Flash
– 32/16/8/4 KB SRAM Memory
System
– Power-on Reset (POR) and Brown-out Detection (BOD)
– Internal and external clock options with 48 MHz Digital Frequency-Locked Loop (DFLL48M) and 48 MHz to
96 MHz Fractional Digital Phase-Locked Loop (FDPLL96M)
– External Interrupt Controller (EIC)
– 16 external interrupts
– One Non-maskable Interrupt (NMI)
– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
Low Power
– Idle and Standby Sleep modes
– SleepWalking peripherals
Peripherals
– 12-channel Direct Memory Access Controller (DMAC)
– 12-channel Event System
– Up to five 16-bit Timer/Counters (TC), configurable as either:
• One 16-bit TC with two compare/capture channels
• One 8-bit TC with two compare/capture channels
• One 32-bit TC with two compare/capture channels, by using two TCs
– Up to four 24-bit Timer/Counters for Control (TCC), with extended functions:
• Up to four compare channels with optional complementary output
• Generation of synchronized pulse width modulation (PWM) pattern across port pins
• Deterministic fault protection, fast decay and configurable dead-time between complementary output
• Dithering that increase resolution with up to 5 bit and reduce quantization error
– PWM Channels using TC and TCC peripherals:
• Up to eight PWM channels on each 24-bit TCC
• Up to two PWM channels on each 16-bit TCC
• Up to two PWM channels on each 16-bit TC
– 32-bit Real Time Counter (RTC) with clock/calendar function
– Watchdog Timer (WDT)
– CRC-32 generator
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and its subsidiaries
Complete Datasheet
DS40001882H-page 1
SAM D21/DA1 Family
•
•
•
•
•
– One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
• Embedded host and device function
• Eight endpoints
– Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:
• USART with full-duplex and single-wire half-duplex configuration
• I2C up to 3.4 MHz
• SPI
• LIN client
– One two-channel Inter-IC Sound (I2S) interface
– One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
• Differential and single-ended input
• 1/2x to 16x programmable gain stage
• Automatic offset and gain error compensation
• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
– 10-bit, 350 ksps Digital-to-Analog Converter (DAC)
– Up to four Analog Comparators (AC) with Window Compare function
– Peripheral Touch Controller (PTC)
• Up to 256-Channel capacitive touch and proximity sensing
I/O
– Up to 52 programmable I/O pins
Qualification
– SAM D21 AEC-Q100 Grade 1 (-40°C to 125°C)
– SAM DA1 AEC-Q100 Grade 2 (-40C to 105C)
Drop-in compatible with SAM D20
Packages
– 64-pin TQFP, QFN, UFBGA
– 48-pin TQFP, QFN
– 45-pin WLCSP
– 35-pin WLCSP
– 32-pin TQFP, QFN
Operating Voltage
– SAM D21: 1.62V – 3.63V
– SAM DA1: 2.7V - 3.63V
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 2
SAM D21/DA1 Family
Table of Contents
Features......................................................................................................................................................... 1
1.
Description............................................................................................................................................ 13
2.
Configuration Summary........................................................................................................................ 14
3.
SAM D21 Ordering Information(1)..........................................................................................................16
3.1.
SAM DA1 Ordering Information..................................................................................................17
4.
Block Diagram.......................................................................................................................................18
5.
Pinout.................................................................................................................................................... 19
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
SAM D21J and SAM DA1J.........................................................................................................19
SAM D21GxxA/B/D and SAM DA1GxxA/B................................................................................ 21
SAM D21GxxA........................................................................................................................... 22
SAM D21GxxL............................................................................................................................23
SAM D21ExxA/B/D and SAM DA1ExxA/B................................................................................. 24
SAM D21ExxB/C/D.................................................................................................................... 25
SAM D21ExxL............................................................................................................................ 26
6.
Signal Descriptions List.........................................................................................................................27
7.
I/O Multiplexing and Considerations..................................................................................................... 29
7.1.
7.2.
8.
Power Supply and Start-Up Considerations..........................................................................................35
8.1.
8.2.
8.3.
8.4.
9.
Multiplexed Signals.................................................................................................................... 29
Other Functions..........................................................................................................................32
Power Domain Overview............................................................................................................35
Power Supply Considerations.................................................................................................... 35
Power-Up................................................................................................................................... 37
Power-On Reset and Brown-Out Detector................................................................................. 37
Product Mapping................................................................................................................................... 39
10. Memories.............................................................................................................................................. 41
10.1. Embedded Memories................................................................................................................. 41
10.2. Physical Memory Map................................................................................................................ 41
10.3. NVM Calibration and Auxiliary Space........................................................................................ 42
11. Processor And Architecture.................................................................................................................. 46
11.1.
11.2.
11.3.
11.4.
11.5.
11.6.
11.7.
Cortex M0+ Processor............................................................................................................... 46
Nested Vector Interrupt Controller..............................................................................................47
Micro Trace Buffer...................................................................................................................... 49
High-Speed Bus System............................................................................................................ 49
AHB-APB Bridge........................................................................................................................ 51
Peripheral Access Controller (PAC)........................................................................................... 52
Register Access and Behavior................................................................................................... 65
12. Peripherals Configuration Summary..................................................................................................... 66
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and its subsidiaries
Complete Datasheet
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SAM D21/DA1 Family
13. DSU - Device Service Unit.................................................................................................................... 68
13.1. Overview.................................................................................................................................... 68
13.2. Features..................................................................................................................................... 68
13.3. Block Diagram............................................................................................................................ 68
13.4. Signal Description...................................................................................................................... 69
13.5. Product Dependencies............................................................................................................... 69
13.6. Debug Operation........................................................................................................................ 70
13.7. Chip Erase..................................................................................................................................71
13.8. Programming..............................................................................................................................72
13.9. Intellectual Property Protection.................................................................................................. 72
13.10. Device Identification................................................................................................................... 73
13.11. Functional Description................................................................................................................74
13.12. Register Summary..................................................................................................................... 79
13.13. Register Description...................................................................................................................80
14. Clock System...................................................................................................................................... 103
14.1.
14.2.
14.3.
14.4.
14.5.
14.6.
14.7.
14.8.
Clock Distribution..................................................................................................................... 103
Synchronous and Asynchronous Clocks..................................................................................104
Register Synchronization......................................................................................................... 104
Enabling a Peripheral............................................................................................................... 108
Disabling a Peripheral.............................................................................................................. 108
On-demand, Clock Requests................................................................................................... 109
Power Consumption vs. Speed................................................................................................ 109
Clocks after Reset.................................................................................................................... 109
15. GCLK - Generic Clock Controller.........................................................................................................111
15.1.
15.2.
15.3.
15.4.
15.5.
15.6.
15.7.
15.8.
Overview...................................................................................................................................111
Features....................................................................................................................................111
Block Diagram...........................................................................................................................111
Signal Description.....................................................................................................................112
Product Dependencies............................................................................................................. 112
Functional Description.............................................................................................................. 113
Register Summary....................................................................................................................119
Register Description................................................................................................................. 119
16. PM – Power Manager......................................................................................................................... 130
16.1.
16.2.
16.3.
16.4.
16.5.
16.6.
16.7.
16.8.
Overview.................................................................................................................................. 130
Features................................................................................................................................... 130
Block Diagram.......................................................................................................................... 131
Signal Description.................................................................................................................... 131
Product Dependencies............................................................................................................. 131
Functional Description..............................................................................................................133
Register Summary....................................................................................................................139
Register Description................................................................................................................. 139
17. SYSCTRL – System Controller........................................................................................................... 158
17.1. Overview.................................................................................................................................. 158
17.2. Features................................................................................................................................... 158
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and its subsidiaries
Complete Datasheet
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SAM D21/DA1 Family
17.3.
17.4.
17.5.
17.6.
17.7.
17.8.
Block Diagram.......................................................................................................................... 159
Signal Description.................................................................................................................... 159
Product Dependencies............................................................................................................. 160
Functional Description..............................................................................................................161
Register Summary....................................................................................................................175
Register Description................................................................................................................. 176
18. WDT – Watchdog Timer...................................................................................................................... 211
18.1.
18.2.
18.3.
18.4.
18.5.
18.6.
18.7.
18.8.
Overview...................................................................................................................................211
Features................................................................................................................................... 211
Block Diagram.......................................................................................................................... 211
Signal Description.................................................................................................................... 212
Product Dependencies............................................................................................................. 212
Functional Description..............................................................................................................213
Register Summary....................................................................................................................218
Register Description................................................................................................................. 218
19. RTC – Real-Time Counter...................................................................................................................227
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
19.8.
Overview.................................................................................................................................. 227
Features................................................................................................................................... 227
Block Diagram.......................................................................................................................... 227
Signal Description.................................................................................................................... 228
Product Dependencies............................................................................................................. 228
Functional Description..............................................................................................................230
Register Summary....................................................................................................................234
Register Description................................................................................................................. 236
20. DMAC – Direct Memory Access Controller......................................................................................... 268
20.1. Overview.................................................................................................................................. 268
20.2. Features................................................................................................................................... 268
20.3. Block Diagram.......................................................................................................................... 269
20.4. Signal Description.................................................................................................................... 270
20.5. Product Dependencies............................................................................................................. 270
20.6. Functional Description..............................................................................................................271
20.7. Register Summary....................................................................................................................289
20.8. Register Description................................................................................................................. 290
20.9. Register Summary - SRAM...................................................................................................... 317
20.10. Register Description - SRAM................................................................................................... 317
21. EIC – External Interrupt Controller...................................................................................................... 324
21.1.
21.2.
21.3.
21.4.
21.5.
21.6.
21.7.
21.8.
Overview.................................................................................................................................. 324
Features................................................................................................................................... 324
Block Diagram.......................................................................................................................... 324
Signal Description.................................................................................................................... 324
Product Dependencies............................................................................................................. 325
Functional Description..............................................................................................................326
Register Summary....................................................................................................................330
Register Description................................................................................................................. 330
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 5
SAM D21/DA1 Family
22. Nonvolatile Memory Controller (NVMCTRL)....................................................................................... 341
22.1.
22.2.
22.3.
22.4.
22.5.
22.6.
22.7.
22.8.
Overview.................................................................................................................................. 341
Features................................................................................................................................... 341
Block Diagram.......................................................................................................................... 341
Signal Description.................................................................................................................... 342
Product Dependencies............................................................................................................. 342
Functional Description..............................................................................................................343
Register Summary....................................................................................................................350
Register Description................................................................................................................. 350
23. PORT - I/O Pin Controller....................................................................................................................363
23.1.
23.2.
23.3.
23.4.
23.5.
23.6.
23.7.
23.8.
Overview.................................................................................................................................. 363
Features................................................................................................................................... 363
Block Diagram.......................................................................................................................... 364
Signal Description.................................................................................................................... 364
Product Dependencies............................................................................................................. 364
Functional Description..............................................................................................................366
Register Summary....................................................................................................................371
Register Description................................................................................................................. 372
24. EVSYS – Event System...................................................................................................................... 388
24.1.
24.2.
24.3.
24.4.
24.5.
24.6.
24.7.
24.8.
Overview.................................................................................................................................. 388
Features................................................................................................................................... 388
Block Diagram.......................................................................................................................... 388
Signal Description.................................................................................................................... 388
Product Dependencies............................................................................................................. 389
Functional Description..............................................................................................................390
Register Summary....................................................................................................................394
Register Description................................................................................................................. 395
25. SERCOM – Serial Communication Interface...................................................................................... 408
25.1.
25.2.
25.3.
25.4.
25.5.
25.6.
Overview.................................................................................................................................. 408
Features................................................................................................................................... 408
Block Diagram.......................................................................................................................... 409
Signal Description.................................................................................................................... 409
Product Dependencies............................................................................................................. 409
Functional Description.............................................................................................................. 411
26. SERCOM USART............................................................................................................................... 416
26.1.
26.2.
26.3.
26.4.
26.5.
26.6.
26.7.
26.8.
Overview.................................................................................................................................. 416
USART Features...................................................................................................................... 416
Block Diagram.......................................................................................................................... 417
Signal Description.................................................................................................................... 417
Product Dependencies............................................................................................................. 417
Functional Description..............................................................................................................419
Register Summary....................................................................................................................430
Register Description................................................................................................................. 430
27. SERCOM SPI – SERCOM Serial Peripheral Interface....................................................................... 448
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Complete Datasheet
DS40001882H-page 6
SAM D21/DA1 Family
27.1.
27.2.
27.3.
27.4.
27.5.
27.6.
27.7.
27.8.
Overview.................................................................................................................................. 448
Features................................................................................................................................... 448
Block Diagram.......................................................................................................................... 449
Signal Description.................................................................................................................... 449
Product Dependencies............................................................................................................. 449
Functional Description..............................................................................................................451
Register Summary....................................................................................................................459
Register Description................................................................................................................. 459
28. SERCOM I2C – Inter-Integrated Circuit...............................................................................................475
28.1. Overview.................................................................................................................................. 475
28.2. Features................................................................................................................................... 475
28.3. Block Diagram.......................................................................................................................... 476
28.4. Signal Description.................................................................................................................... 476
28.5. Product Dependencies............................................................................................................. 476
28.6. Functional Description..............................................................................................................478
28.7. Register Summary - I2C Client.................................................................................................494
28.8. Register Description - I2C Client.............................................................................................. 494
28.9. Register Summary - I2C Host.................................................................................................. 507
28.10. Register Description - I2C Host................................................................................................ 507
29. I2S - Inter-IC Sound Controller............................................................................................................525
29.1.
29.2.
29.3.
29.4.
29.5.
29.6.
29.7.
29.8.
29.9.
Overview.................................................................................................................................. 525
Features................................................................................................................................... 525
Block Diagram.......................................................................................................................... 526
Signal Description.................................................................................................................... 526
Product Dependencies............................................................................................................. 527
Functional Description..............................................................................................................528
I2S Application Examples......................................................................................................... 538
Register Summary....................................................................................................................541
Register Description................................................................................................................. 542
30. TC – Timer/Counter.............................................................................................................................555
30.1. Overview.................................................................................................................................. 555
30.2. Features................................................................................................................................... 555
30.3. Block Diagram.......................................................................................................................... 556
30.4. Signal Description.................................................................................................................... 556
30.5. Product Dependencies............................................................................................................. 557
30.6. Functional Description..............................................................................................................558
30.7. Register Summary for 8-bit Registers...................................................................................... 570
30.8. Register Description for 8-bit Registers....................................................................................570
30.9. Register Summary for 16-bit Registers.................................................................................... 586
30.10. Register Description for 16-bit Registers................................................................................. 586
30.11. Register Summary for 32-bit Registers.................................................................................... 601
30.12. Register Description for 32-bit Registers................................................................................. 601
31. TCC – Timer/Counter for Control Applications....................................................................................616
31.1. Overview.................................................................................................................................. 616
31.2. Features................................................................................................................................... 616
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Complete Datasheet
DS40001882H-page 7
SAM D21/DA1 Family
31.3.
31.4.
31.5.
31.6.
31.7.
31.8.
Block Diagram.......................................................................................................................... 617
Signal Description.................................................................................................................... 617
Product Dependencies............................................................................................................. 618
Functional Description..............................................................................................................619
Register Summary....................................................................................................................650
Register Description................................................................................................................. 652
32. USB – Universal Serial Bus................................................................................................................ 691
32.1. Overview.................................................................................................................................. 691
32.2. Features................................................................................................................................... 691
32.3. USB Block Diagram..................................................................................................................692
32.4. Signal Description.................................................................................................................... 692
32.5. Product Dependencies............................................................................................................. 692
32.6. Functional Description..............................................................................................................694
32.7. Communication Device Host Register Summary..................................................................... 710
32.8. Communication Device Host Register Description...................................................................710
32.9. Device Registers - Common -Register Summary.................................................................... 717
32.10. Device Registers - Common.................................................................................................... 717
32.11. Device Endpoint Register Summary........................................................................................ 730
32.12. Device Endpoint Register Description......................................................................................730
32.13. Endpoint Descriptor Structure.................................................................................................. 739
32.14. Device Endpoint RAM Register Summary............................................................................... 740
32.15. Device Endpoint RAM Register Description.............................................................................740
32.16. Host Registers - Common - Register Summary.......................................................................746
32.17. Host Registers - Common - Register Description.................................................................... 746
32.18. Host Registers - Pipe - Register Summary.............................................................................. 760
32.19. Host Registers - Pipe - Register Description............................................................................760
32.20. Pipe Descriptor Structure......................................................................................................... 771
32.21. Host Registers - Pipe RAM - Register Summary..................................................................... 772
32.22. Host Registers - Pipe RAM - Register Description...................................................................772
33. ADC – Analog-to-Digital Converter..................................................................................................... 780
33.1.
33.2.
33.3.
33.4.
33.5.
33.6.
33.7.
33.8.
Overview.................................................................................................................................. 780
Features................................................................................................................................... 780
Block Diagram.......................................................................................................................... 781
Signal Description.................................................................................................................... 781
Product Dependencies............................................................................................................. 781
Functional Description..............................................................................................................783
Register Summary....................................................................................................................792
Register Description................................................................................................................. 792
34. AC – Analog Comparators.................................................................................................................. 816
34.1.
34.2.
34.3.
34.4.
34.5.
34.6.
Overview.................................................................................................................................. 816
Features................................................................................................................................... 816
Block Diagram.......................................................................................................................... 817
Signal Description.................................................................................................................... 818
Product Dependencies............................................................................................................. 818
Functional Description..............................................................................................................819
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and its subsidiaries
Complete Datasheet
DS40001882H-page 8
SAM D21/DA1 Family
34.7. Register Summary....................................................................................................................828
34.8. Register Description................................................................................................................. 828
35. DAC – Digital-to-Analog Converter..................................................................................................... 843
35.1.
35.2.
35.3.
35.4.
35.5.
35.6.
35.7.
35.8.
Overview.................................................................................................................................. 843
Features................................................................................................................................... 843
Block Diagram.......................................................................................................................... 843
Signal Description.................................................................................................................... 843
Product Dependencies............................................................................................................. 843
Functional Description..............................................................................................................845
Register Summary....................................................................................................................849
Register Description................................................................................................................. 849
36. Peripheral Touch Controller (PTC)...................................................................................................... 859
36.1.
36.2.
36.3.
36.4.
36.5.
36.6.
Overview.................................................................................................................................. 859
Features................................................................................................................................... 859
Block Diagram.......................................................................................................................... 860
Signal Description.................................................................................................................... 861
System Dependencies............................................................................................................. 861
Functional Description..............................................................................................................862
37. Electrical Characteristics at 85℃........................................................................................................ 863
37.1. Disclaimer.................................................................................................................................863
37.2. Thermal Considerations........................................................................................................... 863
37.3. Absolute Maximum Ratings......................................................................................................864
37.4. General Operating Ratings.......................................................................................................864
37.5. Supply Characteristics..............................................................................................................865
37.6. Maximum Clock Frequencies................................................................................................... 865
37.7. Power Consumption................................................................................................................. 867
37.8. Peripheral Power Consumption................................................................................................871
37.9. I/O Pin Characteristics..............................................................................................................874
37.10. Injection Current.......................................................................................................................876
37.11. Analog Characteristics............................................................................................................. 877
37.12. NVM Characteristics................................................................................................................ 890
37.13. Oscillators Characteristics........................................................................................................891
37.14. PTC Typical Characteristics..................................................................................................... 898
37.15. USB Characteristics................................................................................................................. 906
37.16. Timing Characteristics..............................................................................................................907
38. Electrical Characteristics at 105°C......................................................................................................916
38.1.
38.2.
38.3.
38.4.
38.5.
38.6.
38.7.
38.8.
38.9.
Disclaimer.................................................................................................................................916
Absolute Maximum Ratings......................................................................................................916
General Operating Ratings.......................................................................................................916
Maximum Clock Frequencies................................................................................................... 917
Power Consumption................................................................................................................. 918
Analog Characteristics............................................................................................................. 921
NVM Characteristics.................................................................................................................928
Oscillators Characteristics........................................................................................................929
PTC Characteristics at 105°C.................................................................................................. 934
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and its subsidiaries
Complete Datasheet
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SAM D21/DA1 Family
38.10. USB Characteristics................................................................................................................. 935
39. Electrical Characteristics at 125°C......................................................................................................936
39.1.
39.2.
39.3.
39.4.
39.5.
39.6.
39.7.
39.8.
Disclaimer.................................................................................................................................936
Absolute Maximum Ratings......................................................................................................936
General Operating Ratings.......................................................................................................936
Maximum Clock Frequencies................................................................................................... 937
Power Consumption................................................................................................................. 940
Analog Characteristics............................................................................................................. 943
NVM Characteristics.................................................................................................................954
Oscillators Characteristics........................................................................................................955
40. AEC-Q100 125°C Specifications.........................................................................................................965
40.1. Disclaimer.................................................................................................................................965
40.2. Thermal Considerations........................................................................................................... 965
40.3. Absolute Maximum Ratings......................................................................................................965
40.4. General Operating Ratings.......................................................................................................966
40.5. Supply Characteristics..............................................................................................................966
40.6. Maximum Clock Frequencies................................................................................................... 967
40.7. Power Consumption................................................................................................................. 970
40.8. I/O Pin Characteristics..............................................................................................................974
40.9. Analog Characteristics............................................................................................................. 977
40.10. NVM Characteristics................................................................................................................ 988
40.11. Oscillator Characteristics..........................................................................................................989
40.12. PTC Characteristics................................................................................................................. 997
41. SAM DA1 Electrical Characteristics.................................................................................................. 1000
41.1. Disclaimer...............................................................................................................................1000
41.2. Thermal Considerations......................................................................................................... 1000
41.3. Absolute Maximum Ratings....................................................................................................1000
41.4. Supply Characteristics............................................................................................................1001
41.5. Maximum Clock Frequencies................................................................................................. 1002
41.6. Power Consumption............................................................................................................... 1003
41.7. Peripheral Power Consumption..............................................................................................1006
41.8. I/O Pin Characteristics............................................................................................................1009
41.9. Injection Current..................................................................................................................... 1012
41.10. Analog Characteristics........................................................................................................... 1013
41.11. NVM Characteristics...............................................................................................................1022
41.12. Oscillators Characteristics......................................................................................................1022
41.13. PTC Typical Characteristics................................................................................................... 1032
41.14. USB Characteristics............................................................................................................... 1040
41.15. Timing Characteristics............................................................................................................1041
42. Appendix A........................................................................................................................................1049
42.1. SIL 2 Enabled Functional Safety Devices.............................................................................. 1049
43. Appendix B........................................................................................................................................1050
43.1. ISELED FULL License Enabled Functional Devices..............................................................1050
43.2. Ordering Information.............................................................................................................. 1050
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Complete Datasheet
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SAM D21/DA1 Family
44. Packaging Information...................................................................................................................... 1051
44.1. Package Drawings................................................................................................................. 1051
44.2. Soldering Profile......................................................................................................................1111
44.3. Package Markings...................................................................................................................1111
45. Schematic Checklist.......................................................................................................................... 1112
45.1.
45.2.
45.3.
45.4.
45.5.
45.6.
45.7.
45.8.
Introduction............................................................................................................................. 1112
Power Supply..........................................................................................................................1112
External Analog Reference Connections................................................................................1113
External Reset Circuit............................................................................................................. 1114
Clocks and Crystal Oscillators................................................................................................ 1116
Unused or Unconnected Pins................................................................................................. 1118
Programming and Debug Ports.............................................................................................. 1118
USB Interface......................................................................................................................... 1121
46. Conventions.......................................................................................................................................1123
46.1.
46.2.
46.3.
46.4.
Numerical Notation................................................................................................................. 1123
Memory Size and Type...........................................................................................................1123
Frequency and Time...............................................................................................................1123
Registers and Bits.................................................................................................................. 1124
47. Acronyms and Abbreviations.............................................................................................................1125
48. Data Sheet Revision History..............................................................................................................1128
48.1. Revision H - September 2021................................................................................................ 1128
48.2. Revision G - April 2021...........................................................................................................1128
48.3. Revision F - March 2020........................................................................................................ 1133
48.4. Revision E - January 2020..................................................................................................... 1134
48.5. Rev D - 9/2018....................................................................................................................... 1135
48.6. Rev. C – 06/2018....................................................................................................................1136
48.7. Rev. B – 04/2018.................................................................................................................... 1136
48.8. Rev. A – 01/2017.................................................................................................................... 1137
48.9. Rev. O – 12/2016....................................................................................................................1137
48.10. Rev. N – 10/2016....................................................................................................................1137
48.11. Rev. M – 09/2016....................................................................................................................1138
48.12. Rev. L – 09/2016.................................................................................................................... 1138
48.13. Rev. K – 09/2016....................................................................................................................1139
48.14. Rev. J – 07/2016.................................................................................................................... 1140
48.15. Rev. I – 03/2016..................................................................................................................... 1140
48.16. Rev. H – 01/2016....................................................................................................................1141
48.17. Rev. G – 09/2015................................................................................................................... 1142
48.18. Rev. F – 07/2015.................................................................................................................... 1142
48.19. Rev. E – 02/2015....................................................................................................................1143
48.20. Rev. D – 09/2014....................................................................................................................1145
48.21. Rev. C – 07/2014....................................................................................................................1145
48.22. Rev. B – 07/2014....................................................................................................................1145
48.23. Rev. A - 02/2014.....................................................................................................................1149
The Microchip Web Site............................................................................................................................1150
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and its subsidiaries
Complete Datasheet
DS40001882H-page 11
SAM D21/DA1 Family
Customer Change Notification Service.....................................................................................................1150
Customer Support.................................................................................................................................... 1150
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© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 12
SAM D21/DA1 Family
Description
1.
Description
The SAM D21/DA1 is a series of low-power microcontrollers using the 32-bit Arm® Cortex®-M0+ processor, and
ranging from 32-pins to 64-pins with up to 256 KB Flash and 32 KB of SRAM. The SAM D21/DA1 operates at a
maximum frequency of 48 MHz and reach 2.46 CoreMark/MHz. They are designed for simple and intuitive migration
with identical peripheral modules, hex compatible code, identical linear address map, and pin compatible migration
paths between all devices in the product series. All devices include intelligent and flexible peripherals, Event System
for inter-peripheral signaling, and support for capacitive touch button, slider, and wheel user interfaces.
The SAM D21/DA1 provides the following features: In-system programmable Flash, 12-channel Direct Memory
Access Controller (DMAC), 12-channel Event System, programmable Interrupt Controller, up to 52 programmable
I/O pins, 32-bit Real-Time Clock and Calendar (RTC), up to five 16-bit Timer/Counters (TC) and up to four 24-bit
Timer/Counters for Control (TCC), where each TC can be configured to perform frequency and waveform generation,
accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs
can operate in 8-bit or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and three timer/counters
have extended functions optimized for motor, lighting, and other control applications. The series provide one fullspeed USB 2.0 embedded host and device interface; up to six Serial Communication Modules (SERCOM) that each
can be configured to act as an USART, UART, SPI, I2C up to 3.4 MHz, SMBus, PMBus, and LIN client; two-channel
I2S interface; up to twenty-channel 350 ksps 12-bit ADC with programmable gain and optional oversampling and
decimation supporting up to 16-bit resolution, one 10-bit 350 ksps DAC, up to four analog comparators with Window
mode, Peripheral Touch Controller (PTG) supporting up to 256 buttons, sliders, wheels, and proximity sensing;
programmable Watchdog Timer (WDT), brown-out detector and power-on Reset and two-pin Serial Wire Debug
(SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for
the system clock. Different clock domains can be independently configured to run at different frequencies, enabling
power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency
while reducing power consumption.
The SAM D21/DA1 have two software-selectable sleep modes, Idle and Stand-by. In Idle mode, the CPU is stopped
while all other functions can be kept running. In Stand-by mode, all clocks and functions are stopped, expect those
selected to continue running. The device supports SleepWalking. This feature allows the peripheral to wake up from
sleep based on predefined conditions, and thus allows the CPU to wake up only when needed, for example, when
a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events,
allowing peripherals to receive, react to and send events even in Stand-by mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can
be used for non-intrusive on-chip debug of application code. A boot loader running in the device can use any
communication interface to download and upgrade the application program in the Flash memory.
The SAM D21/DA1 microcontrollers are supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 13
SAM D21/DA1 Family
Configuration Summary
2.
Configuration Summary
Table 2-1. SAM D21 E/G/J and SAM D21 EL/GL Product Family Features
38
14
PTC (Mutual/Self-capacitance Channels)"
10
DAC
ADC Channels
26
Analog Comparator
I/O Pins
External Interrupt Lines
Y
Event System (Channels)
12
WDT
Waveform /PWM Output
Channels per TCCx Instance
TCC
TC-Waveform /PWM Output/Capture
Input Channels per TCx Instance
SERCOM
USB
External
Internal
Packages
Pins
RTC
32
Analog
DMA Channels
ATSAMD21E15A
Data Memory (KB)
Program Memory (KB)
Device
I2S
Peripherals
Oscillators
4
ATSAMD21E16A
64
8
ATSAMD21E17A
128
16
ATSAMD21E18A
256
32
ATSAMD21E15B
32
4
OSC32K,
32
TQFP,
QFN
OSCULP32K,
OSC8M,
3
4
DFLL48M,
8/4/2
60/6
FDPLL96M
ATSAMD21E16B
64
8
ATSAMD21E15C
32
4
ATSAMD21E16C
64
8
ATSAMD21G15A
32
4
ATSAMD21G16A
64
8
ATSAMD21G17A
128
16
35
3-2
48
256
Y
12
16
OSC32K,
(1)
ATSAMD21G18A
WLCSP
32
OSCULP32K,
XOSC32K,
TQFP,
OSC8M,
XOSC,
QFN
DFLL48M,
Y
Y
3
12
2
Y
120/10
FDPLL96M
( 1)
ATSAMD21G15B
32
4
ATSAMD21G16B
64
8
ATSAMD21J15A
32
4
ATSAMD21J16A
64
8
ATSAMD21J17A
128
16
ATSAMD21J18A
256
32
ATSAMD21J15B
32
4
ATSAMD21J16B
64
8
ATSAMD21E15L
32
4
ATSAMD21E16L
ATSAMD21G16L
Y
6
TQFP,
QFN
OSC32K,
64
TQFP,
QFN,
UFBGA
32
QFN
64
8
48
QFN
128
16
TQFP,
32
QFN
WLCSP
128
OSC8M,
20
26
14
256/16
3
FDPLL96M
12
16
N
4
3-2
Y
Y
12
16
6/4/2
XOSC
N
6
5-2
8/4/2
Y
4
3-2
4
6/4/2/6
Y
Y
6
3-2
4
8/4/2/8
Y
4
N
30/6
38
18
26
10
2
38
14
2
OSC32K,
OSCULP32K,
OSC8M,
XOSC32K,
XOSC
DFLL48M,
OSC32K,
OSCULP32K,
ATSAMD21G17D
52
DFLL48M,
TQFP,
32
ATSAMD21E17D
5-2
OSCULP32K,
8
64
8/4/2
48
QFN,
TQFP
OSC8M,
DFLL48M,
XOSC32K,
XOSC,
12
Y
Y
12
16
Y
FDPLL96M
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DS40001882H-page 14
120/10
SAM D21/DA1 Family
Configuration Summary
...........continued
Peripherals
TC-Waveform /PWM Output/Capture
Input Channels per TCx Instance
TCC
Waveform /PWM Output
Channels per TCCx Instance
I2S
DMA Channels
RTC
WDT
Event System (Channels)
External Interrupt Lines
I/O Pins
ADC Channels
Analog Comparator
DAC
PTC (Mutual/Self-capacitance Channels)"
Y
6
5-2
4
8/4/2/8
Y
12
Y
Y
12
16
52
20
2
Y
256/16
XOSC
N
4
3-2
4
6/4/2/6
N
12
Y
Y
12
16
26
14
4
Y
N
XOSC
N
6
5-2
4
8/4/2/8
N
12
Y
Y
12
16
38
18
4
Y
N
External
SERCOM
Analog
USB
ATSAMD21J17D
Internal
16
Packages
128
Pins
Data Memory (KB)
Device
Program Memory (KB)
Oscillators
OSC32K,
64
QFN,
TQFP
OSCULP32K,
UFBGA
DFLL48M,
OSC8M,
XOSC32K,
XOSC,
FDPLL96M
128
16
OSC32K,
OSCULP32K,
ATSAMD21E17L
32
QFN,
TQFP
OSC8M,
DFLL48M,
FDPLL96M
128
16
OSC32K,
OSCULP32K,
ATSAMD21G17L
48
OSC8M,
QFN
DFLL48M,
FDPLL96M
Note:
1. This part number is also available in a 45-Ball WLCSP package with a total of five TC instances and 15 ADC
Channels.
38
14
52
20
PTC (Mutual/Selfcapacitance Channels)
10
DAC
ADC Channels
26
Analog Comparator
I/O Pins
External Interrupt Lines
Event System (Channels)
WDT
RTC
DMA Channels
I2S
Waveform/PWM Output
Channels per TCCx Instance
32
TCC
ATSAMDA1G15B
TC-Waveform/PWM Output/Capture
Input Channels per TCx Instance
16
USB
ATSAMDA1G14B
SERCOM
64
External
ATSAMDA1E16B
Internal
32
Packages
16
ATSAMDA1E15B
Pins
ATSAMDA1E14B
Data Memory (KB)
Device
Program Memory (KB)
Table 2-2. SAM DA1 E/G/J Product Family Features
4
32
8
4
TQFP,
QFN
4
ATSAMDA1G16B
64
ATSAMDA1J14B
16
ATSAMDA1J15B
32
ATSAMDA1J16B
64
OSC32K,
OSCULP32K,
OSC8M,
48
DFLL48M,
8
FDPLL96M
6/4/2
60/6
3-2
XOSC32K,
XOSC
1
3
6
1
12
Y
Y
12
16
2
1
120/10
8/4/2
4
64
TQFP
5-2
256/16
8
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Complete Datasheet
DS40001882H-page 15
SAM D21/DA1 Family
SAM D21 Ordering Information(1)
3.
SAM D21 Ordering Information(1)
ATSAMD 21 E 15 A - M U T
Product Family
Package Carrier
SAMD = General Purpose Microcontroller
No character = Tray (Default)
T = Tape and Reel
Product Series
21 = Cortex M0 + CPU, Basic Feature Set
+ DMA + USB
Package Grade
Pin Count
U = -40 - 85°C Matte Sn Plating
N = -40 - 105°C Matte Sn Plating
F = -40 - 125°C Matte Sn Plating
Z = -40 - 125°C Matte Sn Plating
(AEC-Q100 Qualified)
E = 32 Pins (35 Pins for WLCSP)
G = 48 Pins (45 Pins for WLCSP)
J = 64 Pins
Flash Memory Density
Package Type
18 = 256 KB
17 = 128 KB
16 = 64 KB
15 = 32 KB
A = TQFP(4)
M = VQFN(4)
MM = 64-Lead VQFN (5LX)
U = WLCSP (2,3)
Device Variant
A = Default Variant
B = Added RWWEE support for 32 KB and 64 KB memory options
C = Silicon revision F for WLCSP45 package option
L = Pinout optimized for Analog and PWM
D = Silicon Revision G with RWWEE Support in 128KB memory options
C = UFBGA
Notes:
1. Not all combinations are valid. The available ordering numbers are listed in the Configuration Summary.
2. WLCSP package is available in -40C to 85C operating temperature range.
3. WLCSP parts are programmed with a specific SPI/I2C bootloader. Refer to "Application Note AT09002" for
additional information. Contact Microchip sales office for additional information on availability.
4. The AEC-Q100 grade 1 qualified version is only offered in the TQFP and QFN packages. The QFN will have
wettable flanks, and both packages will be assembled with gold bond wires.
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 16
SAM D21/DA1 Family
SAM D21 Ordering Information(1)
3.1
SAM DA1 Ordering Information
Figure 3-1. SAM DA1 Ordering Information
SAM D A1 E 14 A - A B T
Product Family
Package Carrier
SAM D = Baseline Cortex-M0+ MCU
T = Tape and Reel
Product Series
A1 = Automotive basic feature set + DMA,
Adv Timers, USB, I2S, PTC
Pin Count
Package Grade
B = -40 C - 105 C Matte Sn Plating (only DA1)
O
E = 32 Pins
G = 48 Pins
J = 64 Pins
O
Package Type
Flash Memory Density
A = TQFP
M = QFN Wettable Flanks
16 = 64KB
15 = 32KB
14 = 16KB
Device Variant
A = Silicon revision E (Initial revision)
B = Silicon revision F
Note:
1. Not all combinations are valid. The available ordering numbers are listed in the Configuration Summary.
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Complete Datasheet
DS40001882H-page 17
SAM D21/DA1 Family
Block Diagram
Block Diagram
SERIAL
WIRE
SWDIO
DEVICE
SERVICE
UNIT
M
256/128/64/32KB
NVM
32/16/8/4KB
RAM
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
M
S
S
M
HIGH-SPEED
BUS MATRIX
PERIPHERAL
ACCESS CONTROLLER
S
AHB-APB
BRIDGE B
S
USB FS
DEVICE
MINI-HOST
S
AHB-APB
BRIDGE A
DMA
66xxSERCOM
SERCOM
VREF
OSC32K
DMA
OSC8M
5 x TIMER / COUNTER
8 x Timer Counter
DFLL48M
XOSC
FDPLL96M
POWER MANAGER
CLOCK
CONTROLLER
RESET
CONTROLLER
SLEEP
CONTROLLER
EVENT SYSTEM
DMA
RESET
PAD0
PAD1
PAD2
PAD3
OSCULP32K
XOSC32K
XIN
XOUT
SOF 1KHZ
PERIPHERAL
ACCESS CONTROLLER
SYSTEM CONTROLLER
XIN32
XOUT32
DP
DM
AHB-APB
BRIDGE C
PERIPHERAL
ACCESS CONTROLLER
BOD33
DMA
4x TIMER / COUNTER
FOR CONTROL
WO0
WO1
WO0
WO1
PORT
SWCLK
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
MICRO
TRACE BUFFER
IOBUS
PORT
4.
(2)
WOn
AIN[19..0]
DMA
20-CHANNEL
12-bit ADC 350KSPS
VREFA
VREFB
CMP[1..0]
GCLK_IO[7..0]
Up to 4 ANALOG
COMPARATORS
GENERIC CLOCK
CONTROLLER
REAL TIME
COUNTER
DMA
EXTINT[15..0]
NMI
VOUT
10-bit DAC
WATCHDOG
TIMER
EXTERNAL INTERRUPT
CONTROLLER
PERIPHERAL
TOUCH
CONTROLLER
DMA
INTER-IC
SOUND
CONTROLLER
1.
2.
AIN[3..0]
VREFA
X[15..0]
Y[15..0]
MCK[1..0]
SCK[1..0]
SD[1..0]
FS[1..0]
Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC
signals. Refer to the Configuration Summary for details.
The TCC instances have different configurations, including the number of Waveform Output (WO) lines. Refer
to the TCC Configuration for details.
Related Links
2. Configuration Summary
7.2.5 TCC Configurations
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Complete Datasheet
DS40001882H-page 18
SAM D21/DA1 Family
Pinout
Pinout
5.1
SAM D21J and SAM DA1J
5.1.1
QFN64 / TQFP64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB03
PB02
PB01
PB00
PB31
PB30
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
5.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PB12
PB13
PB14
PB15
PA12
PA13
PA14
PA15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA00
PA01
PA02
PA03
PB04
PB05
GNDANA
VDDANA
PB06
PB07
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
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Complete Datasheet
DS40001882H-page 19
SAM D21/DA1 Family
Pinout
5.1.2
UFBGA64
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Complete Datasheet
DS40001882H-page 20
SAM D21/DA1 Family
Pinout
SAM D21GxxA/B/D and SAM DA1GxxA/B
5.2.1
QFN48 / TQFP48
48
47
46
45
44
43
42
41
40
39
38
37
PB03
PB02
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
5.2
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PA12
PA13
PA14
PA15
13
14
15
16
17
18
19
20
21
22
23
24
PA00
PA01
PA02
PA03
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
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Complete Datasheet
DS40001882H-page 21
SAM D21/DA1 Family
Pinout
5.3
SAM D21GxxA
5.3.1
WLCSP45
A
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DS40001882H-page 22
SAM D21/DA1 Family
Pinout
SAM D21GxxL
5.4.1
QFN48
48
47
46
45
44
43
42
41
40
39
38
37
PB03
PB02
PB01
PB00
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
5.4
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PA12
PA13
PA14
PA15
13
14
15
16
17
18
19
20
21
22
23
24
PA02
PA03
PB04
PB05
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
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Complete Datasheet
DS40001882H-page 23
SAM D21/DA1 Family
Pinout
SAM D21ExxA/B/D and SAM DA1ExxA/B
5.5.1
QFN32 / TQFP32
32
31
30
29
28
27
26
25
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
5.5
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
VDDANA
GND
PA08
PA09
PA10
PA11
PA14
PA15
9
10
11
12
13
14
15
16
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
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DS40001882H-page 24
SAM D21/DA1 Family
Pinout
5.6
SAM D21ExxB/C/D
5.6.1
WLCSP35
A
B
1
00
PA
30
PA
2
0
PA
4
VD
RE
2
PA
7
2
PA
D
2
PA
2
2
PA
5
11
PA
1
PA
7
1
PA
9
1
PA
6
1
PA
D
1
PA
4
1
PA
03
PA
GN
NA
04
PA
0
PA
6
0
PA
7
0
PA
8
0
PA
10
PA
GN
0
PA
6
VD
O
DI
© 2021 Microchip Technology Inc.
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5
8
IN
2
5
T
2
PA
0
PA
DA
F
SE
RE
GN
2
PA
AN
E
D
CO
D
VD
D
VD
3
PA
A
D
GN
D
1
1
3
C
Complete Datasheet
4
3
9
8
5
DS40001882H-page 25
SAM D21/DA1 Family
Pinout
SAM D21ExxL
5.7.1
QFN32 / TQFP32
32
31
30
29
28
27
26
25
PB03
PB02
PA31
PA30
VDDIO
VDDCORE
GND
RESET
5.7
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
VDDIO/ANA
GND
PA08
PA09
PA10
PA11
PA14
PA15
9
10
11
12
13
14
15
16
PA02
PA03
PB04
PB05
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR PIN
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
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and its subsidiaries
Complete Datasheet
DS40001882H-page 26
SAM D21/DA1 Family
Signal Descriptions List
6.
Signal Descriptions List
The following table gives details on signal names classified by peripheral.
Signal Name
Function
Type
Active Level
Analog Comparators - AC
AIN[3:0]
AC Analog Inputs
Analog
CMP[:0]
AC Comparator Outputs
Digital
Analog Digital Converter - ADC
AIN[19:0]
ADC Analog Inputs
Analog
VREFA
ADC Voltage External Reference A
Analog
VREFB
ADC Voltage External Reference B
Analog
Digital Analog Converter - DAC
VOUT
DAC Voltage output
Analog
VREFA
DAC Voltage External Reference
Analog
External Interrupt Controller
EXTINT[15:0]
External Interrupts
Input
NMI
External Non-Maskable Interrupt
Input
Generic Clock Generator - GCLK
GCLK_IO[7:0]
Generic Clock (source clock or generic clock generator output)
I/O
Inter-IC Sound Controller - I2S
MCK[1:0]
Host Clock
I/O
SCK[1:0]
Serial Clock
I/O
FS[1:0]
I2S Word Select or TDM Frame Sync
I/O
SD[1:0]
Serial Data Input or Output
I/O
Power Manager - PM
RESET
Reset
Input
Low
Serial Communication Interface - SERCOMx
PAD[3:0]
SERCOM I/O Pads
I/O
System Control - SYSCTRL
XIN
Crystal Input
Analog/ Digital
XIN32
32kHz Crystal Input
Analog/ Digital
XOUT
Crystal Output
Analog
XOUT32
32kHz Crystal Output
Analog
Timer Counter - TCx
WO[1:0]
Waveform/PWM Outputs/ Capture Inputs
Output
Timer Counter - TCCx
WO[7:0]
Waveform/PWM Outputs
© 2021 Microchip Technology Inc.
and its subsidiaries
Output
Complete Datasheet
DS40001882H-page 27
SAM D21/DA1 Family
Signal Descriptions List
...........continued
Signal Name
Function
Type
Active Level
Peripheral Touch Controller - PTC
X[15:0]
PTC Input
Analog
Y[15:0]
PTC Input
Analog
General Purpose I/O - PORT
PA25 - PA00
Parallel I/O Controller I/O Port A
I/O
PA28 - PA27
Parallel I/O Controller I/O Port A
I/O
PA31 - PA30
Parallel I/O Controller I/O Port A
I/O
PB17 - PB00
Parallel I/O Controller I/O Port B
I/O
PB23 - PB22
Parallel I/O Controller I/O Port B
I/O
PB31 - PB30
Parallel I/O Controller I/O Port B
I/O
Universal Serial Bus - USB
DP
DP for USB
I/O
DM
DM for USB
I/O
SOF 1kHz
USB Start of Frame
I/O
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 28
SAM D21/DA1 Family
I/O Multiplexing and Considerations
7.
I/O Multiplexing and Considerations
7.1
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of
the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer
Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT
must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing
Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
This table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 7-1. PORT Function Multiplexing for SAM D21 A/B/C/D Variant Devices and SAM DA1 A/B Variant Devices
Pin(1)
SAMD2xE
SAMD2xG
I/O Pin
Supply
B(2)(3)
A
SAMD2xJ
EIC
REF
ADC
AC
PTC
DAC
C
D
E
F
G
H
SERCOM(2)(3)
SERCOM-ALT
TC(4)
TCC
COM
AC/
/TCC
1
1
1
PA00
VDDANA
EXTINT[0]
SERCOM1/
PAD[0]
TCC2/WO[0]
2
2
2
PA01
VDDANA
EXTINT[1]
SERCOM1/
PAD[1]
TCC2/WO[1]
3
3
3
PA02
VDDANA
EXTINT[2]
4
4
4
PA03
VDDANA
EXTINT[3]
AIN[0]
Y[0]
AIN[1]
Y[1]
VOUT
GCLK
TCC3/
WO[0]
ADC/VREFA
DAC/VREFA
TCC3/
WO[1]
5
PB04
VDDANA
EXTINT[4]
AIN[12]
6
PB05
VDDANA
EXTINT[5]
AIN[13]
Y[11]
9
PB06
VDDANA
EXTINT[6]
AIN[14]
Y[12]
10
PB07
VDDANA
EXTINT[7]
AIN[15]
Y[13]
7
11
PB08
VDDANA
EXTINT[8]
AIN[2]
Y[14]
SERCOM4/
PAD[0]
TC4/WO[0]
TCC3/
8
12
PB09
VDDANA
EXTINT[9]
AIN[3]
Y[15]
SERCOM4/
PAD[1]
TC4/WO[1]
TCC3/
5
9
13
PA04
VDDANA
EXTINT[4]
6
10
14
PA05
VDDANA
7
11
15
PA06
8
12
16
PA07
ADC/VREFB
Y[10]
WO[6]
WO[7]
AIN[4]
AIN[0]
Y[2]
SERCOM0/
PAD[0]
TCC0/WO[0]
TCC3/
EXTINT[5]
AIN[5]
AIN[1]
Y[3]
SERCOM0/
PAD[1]
TCC0/WO[1]
TCC3/
VDDANA
EXTINT[6]
AIN[6]
AIN[2]
Y[4]
SERCOM0/
PAD[2]
TCC1/WO[0]
TCC3/
VDDANA
EXTINT[7]
AIN[7]
AIN[3]
Y[5]
SERCOM0/
PAD[3]
TCC1/WO[1]
TCC3/
WO[2]
WO[3]
WO[4]
I2S/SD[0]
WO[5]
11
13
17
PA08
VDDIO
NMI
AIN[16]
X[0]
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/WO[0]
TCC1/
WO[2]
I2S/SD[1]
12
14
18
PA09
VDDIO
EXTINT[9]
AIN[17]
X[1]
SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TCC0/WO[1]
TCC1/
WO[3]
I2S/
MCK[0]
13
15
19
PA10
VDDIO
EXTINT[10]
AIN[18]
X[2]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC1/WO[0]
TCC0/
WO[2]
I2S/
SCK[0]
GCLK_IO[4]
14
16
20
PA11
VDDIO
EXTINT[11]
AIN[19]
X[3]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC1/WO[1]
TCC0/
WO[3]
I2S/FS[0]
GCLK_IO[5]
19
23
PB10
VDDIO
EXTINT[10]
SERCOM4/
PAD[2]
TC5/WO[0]
TCC0/
WO[4]
I2S/
MCK[1]
GCLK_IO[4]
20
24
PB11
VDDIO
EXTINT[11]
SERCOM4/
PAD[3]
TC5/WO[1]
TCC0/
WO[5]
I2S/
SCK[1]
GCLK_IO[5]
25
PB12
VDDIO
EXTINT[12]
X[12]
SERCOM4/
PAD[0]
TC4/WO[0]
TCC0/
WO[6]
I2S/FS[1]
GCLK_IO[6]
26
PB13
VDDIO
EXTINT[13]
X[13]
SERCOM4/
PAD[1]
TC4/WO[1]
TCC0/
WO[7]
27
PB14
VDDIO
EXTINT[14]
X[14]
SERCOM4/
PAD[2]
TC5/WO[0]
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
GCLK_IO[7]
GCLK_IO[0]
DS40001882H-page 29
SAM D21/DA1 Family
I/O Multiplexing and Considerations
...........continued
Pin(1)
SAMD2xE
SAMD2xG
I/O Pin
Supply
B(2)(3)
A
SAMD2xJ
EIC
REF
ADC
AC
PTC
C
D
E
F
G
H
SERCOM(2)(3)
SERCOM-ALT
TC(4)
TCC
COM
AC/
/TCC
GCLK
GCLK_IO[1]
PB15
VDDIO
EXTINT[15]
21
29
PA12
VDDIO
EXTINT[12]
SERCOM2/
PAD[0]
SERCOM4/
PAD[0]
TCC2/WO[0]
TCC0/
WO[6]
AC/CMP[0]
22
30
PA13
VDDIO
EXTINT[13]
SERCOM2/
PAD[1]
SERCOM4/
PAD[1]
TCC2/WO[1]
TCC0/
WO[7]
AC/CMP[1]
15
23
31
PA14
VDDIO
EXTINT[14]
SERCOM2/
PAD[2]
SERCOM4/
PAD[2]
TC3/WO[0]
TCC0/
WO[4]
GCLK_IO[0]
16
24
32
PA15
VDDIO
EXTINT[15]
SERCOM2/
PAD[3]
SERCOM4/
PAD[3]
TC3/WO[1]
TCC0/
WO[5]
GCLK_IO[1]
17
25
35
PA16
VDDIO
EXTINT[0]
X[4]
SERCOM1/
PAD[0]
SERCOM3/
PAD[0]
TCC2/WO[0]
TCC0/WO[6]
GCLK_IO[2]
18
26
36
PA17
VDDIO
EXTINT[1]
X[5]
SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
TCC2/WO[1]
TCC0/WO[7]
GCLK_IO[3]
19
27
37
PA18
VDDIO
EXTINT[2]
X[6]
SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TC3/WO[0]
TCC0/
WO[2]
AC/CMP[0]
20
28
38
PA19
VDDIO
EXTINT[3]
X[7]
SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TC3/WO[1]
TCC0/
WO[3]
I2S/SD[0]
AC/CMP[1]
39
PB16
VDDIO
EXTINT[0]
SERCOM5/
PAD[0]
TC6/WO[0]
TCC0/
WO[4]
I2S/SD[1]
GCLK_IO[2]
40
PB17
VDDIO
EXTINT[1]
SERCOM5/
PAD[1]
TC6/WO[1]
TCC0/
WO[5]
I2S/
MCK[0]
GCLK_IO[3]
29
41
PA20
VDDIO
EXTINT[4]
X[8]
SERCOM5/
PAD[2]
SERCOM3/
PAD[2]
TC7/WO[0]
TCC0/
WO[6]
I2S/
SCK[0]
GCLK_IO[4]
30
42
PA21
VDDIO
EXTINT[5]
X[9]
SERCOM5/
PAD[3]
SERCOM3/
PAD[3]
TC7/WO[1]
TCC0/
WO[7]
I2S/FS[0]
GCLK_IO[5]
21
31
43
PA22
VDDIO
EXTINT[6]
X[10]
SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TC4/WO[0]
TCC0/
WO[4]
22
32
44
PA23
VDDIO
EXTINT[7]
X[11]
SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TC4/WO[1]
TCC0/
WO[5]
USB/SOF 1kHz
23
33
45
PA24(6)
VDDIO
EXTINT[12]
SERCOM3/
PAD[2]
SERCOM5/
PAD[2]
TC5/WO[0]
TCC1/
WO[2]
USB/DM
24
34
46
PA25(6)
VDDIO
EXTINT[13]
SERCOM3/
PAD[3]
SERCOM5/
PAD[3]
TC5/WO[1]
TCC1/
WO[3]
USB/DP
37
49
PB22
VDDIO
EXTINT[6]
SERCOM5/
PAD[2]
TC7/WO[0]
TCC3/
SERCOM5/
PAD[3]
TC7/WO[1]
25
39
50
51
PB23
PA27
VDDIO
VDDIO
SERCOM4/
PAD[3]
TC5/WO[1]
28
38
X[15]
DAC
EXTINT[7]
GCLK_IO[6]
GCLK_IO[7]
GCLK_IO[0]
WO[0]
TCC3/
GCLK_IO[1]
WO[1]
EXTINT[15]
TCC3/
GCLK_IO[0]
WO[6]
27
41
53
PA28
VDDIO
EXTINT[8]
TCC3/
GCLK_IO[0]
WO[7]
31
32
45
46
57
58
PA30
PA31
VDDIO
VDDIO
EXTINT[10]
EXTINT[11]
SERCOM1/
PAD[2]
TCC1/WO[0]
SERCOM1/
PAD[3]
TCC1/WO[1]
TCC3/
TCC3/
PB30
VDDIO
EXTINT[14]
SERCOM5/
PAD[0]
TCC0/WO[0]
TCC1/
WO[2]
60
PB31
VDDIO
EXTINT[15]
SERCOM5/
PAD[1]
TCC0/WO[1]
TCC1/
WO[3]
61
PB00
VDDANA
EXTINT[0]
AIN[8]
Y[6]
SERCOM5/
PAD[2]
TC7/WO[0]
62
PB01
VDDANA
EXTINT[1]
AIN[9]
Y[7]
SERCOM5/
PAD[3]
TC7/WO[1]
47
63
PB02
VDDANA
EXTINT[2]
AIN[10]
Y[8]
SERCOM5/
PAD[0]
TC6/WO[0]
TCC3/
48
64
PB03
VDDANA
EXTINT[3]
AIN[11]
Y[9]
SERCOM5/
PAD[1]
TC6/WO[1]
TCC3/
and its subsidiaries
Complete Datasheet
GCLK_IO[0]
SWDIO(5)
WO[5]
59
© 2021 Microchip Technology Inc.
SWCLK
WO[4]
WO[2]
WO[3]
DS40001882H-page 30
SAM D21/DA1 Family
I/O Multiplexing and Considerations
1.
2.
3.
4.
5.
6.
7.
8.
Use the SAMD21J pinout muxing for WLCSP45 package.
All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the
digital control of the pin.
Only some pins can be used in SERCOM I2C mode. Refer to 7.2.3 SERCOM I2C Pins.
TC6 and TC7 are not supported on the SAM D21E. Refer to 2. Configuration Summary for details.
This function is only activated in the presence of a debugger.
If the PA24 and PA25 pins are not connected, it is recommended to enable a pull-up on PA24 and PA25
through input GPIO mode. The aim is to avoid an eventually extract power consumption ( 0
FCTRLA.BLANKVAL > 0
-
-
x
xxx
FaultA Input
WO[0]
Fault
Qualification
This is enabled by writing a '1' to the Fault n Qualification bit in the Recoverable Fault n
Configuration register (FCTRLn.QUAL). When the recoverable fault qualification is enabled
(FCTRLn.QUAL=1), the fault input is disabled all the time the corresponding channel output
has an inactive level, as shown in the figures below.
Figure 31-23. Fault Qualification in RAMP1 Operation
MAX
"clear" update
TOP
"match"
COUNT
CC0
"Fault input enabled"
- "Fault input disabled"
CC1
x
"Fault discarded"
ZERO
Fault A Input Qual
-
-
-
-
-
x x x
x x x x x x
Fault Input A
Fault B Input Qual
-
x x x
-
-
x x x x x
x x x x x x x
-
-
x x x x
Fault Input B
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Complete Datasheet
DS40001882H-page 637
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-24. Fault Qualification in RAMP2 Operation with Inverted Polarity
Cycle
"clear" update
MAX
"match"
TOP
"Fault input enabled"
COUNT
CC0
- "Fault input disabled"
x
CC1
"Fault discarded"
ZERO
Fault A Input Qual
-
-
x
x
-
x
x
x
x
x
x
x
x
x
x
Fault Input A
-
Fault B Input Qual
x
x
x
x
-
x
x
x
x
-
x
x
x
x
x
x
x
Fault Input B
Fault Actions
Different fault actions can be configured individually for Fault A and Fault B. Most fault actions are not mutually
exclusive; hence two or more actions can be enabled at the same time to achieve a result that is a combination of
fault actions.
Keep
Action
This is enabled by writing the Fault n Keeper bit in the Recoverable Fault n Configuration register
(FCTRLn.KEEP) to '1'. When enabled, the corresponding channel output will be clamped to zero as
long as the fault condition is present. The clamp will be released on the start of the first cycle after the
fault condition is no longer present, see next Figure.
Figure 31-25. Waveform Generation with Fault Qualification and Keep Action
MAX
"clear" update
TOP
"match"
"Fault input enabled"
CC0
COUNT
- "Fault input disabled"
x
"Fault discarded"
ZERO
Fault A Input Qual
-
-
-
-
x
-
x
x
x
Fault Input A
WO[0]
Restart
Action
KEEP
KEEP
This is enabled by writing the Fault n Restart bit in Recoverable Fault n Configuration register
(FCTRLn.RESTART) to '1'. When enabled, the timer/counter will be restarted as soon as the
corresponding fault condition is present. The ongoing cycle is stopped and the timer/counter starts a
new cycle, see Figure 31-26. In Ramp 1 mode, when the new cycle starts, the compare outputs will be
clamped to inactive level as long as the fault condition is present.
Note: For RAMP2 operation, when a new timer/counter cycle starts the cycle index will change
automatically, see Figure 31-27. Fault A and Fault B are qualified only during the cycle A and cycle
B respectively: Fault A is disabled during cycle B, and Fault B is disabled during cycle A.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 638
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-26. Waveform Generation in RAMP1 mode with Restart Action
MAX
"clear" update
"match"
TOP
CC0
COUNT
CC1
ZERO
Restart
Restart
Fault Input A
WO[0]
WO[1]
Figure 31-27. Waveform Generation in RAMP2 mode with Restart Action
Cycle
CCx=ZERO
CCx=TOP
"clear" update
"match"
MAX
TOP
COUNT
CC0/CC1
ZERO
No fault A action
in cycle B
Restart
Fault Input A
WO[0]
WO[1]
Capture
Action
Several capture actions can be selected by writing the Fault n Capture Action bits in the Fault n Control
register (FCTRLn.CAPTURE). When one of the capture operations is selected, the counter value is
captured when the fault occurs. These capture operations are available:
• CAPT - the equivalent to a standard capture operation, for further details refer to 31.6.2.7 Capture
Operations
• CAPTMIN - gets the minimum time stamped value: on each new local minimum captured value, an
event or interrupt is issued.
• CAPTMAX - gets the maximum time stamped value: on each new local maximum captured value,
an event or interrupt (IT) is issued, see Figure 31-28.
• LOCMIN - notifies by event or interrupt when a local minimum captured value is detected.
• LOCMAX - notifies by event or interrupt when a local maximum captured value is detected.
• DERIV0 - notifies by event or interrupt when a local extreme captured value is detected, see Figure
31-29.
CCx Content:
In CAPTMIN and CAPTMAX operations, CCx keeps the respective extremum captured values, see
Figure 31-28. In LOCMIN, LOCMAX or DERIV0 operation, CCx follows the counter value at fault time,
see Figure 31-29.
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Complete Datasheet
DS40001882H-page 639
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Before enabling CAPTMIN or CAPTMAX mode of capture, the user must initialize the corresponding
CCx register value to a value different from zero (for CAPTMIN) top (for CAPTMAX). If the CCx
register initial value is zero (for CAPTMIN) top (for CAPTMAX), no captures will be performed using the
corresponding channel.
MCx Behaviour:
In LOCMIN and LOCMAX operation, capture is performed on each capture event. The MCx interrupt
flag is set only when the captured value is above or equal (for LOCMIN) or below or equal (for
LOCMAX) to the previous captured value. So interrupt flag is set when a new relative local Minimum
(for CAPTMIN) or Maximum (for CAPTMAX) value has been detected. DERIV0 is equivalent to an OR
function of (LOCMIN, LOCMAX).
In CAPT operation, capture is performed on each capture event. The MCx interrupt flag is set on each
new capture.
In CAPTMIN and CAPTMAX operation, capture is performed only when on capture event time, the
counter value is lower (for CAPTMIN) or higher (for CAPMAX) than the last captured value. The MCx
interrupt flag is set only when on capture event time, the counter value is higher or equal (for CAPTMIN)
or lower or equal (for CAPTMAX) to the value captured on the previous event. So interrupt flag is
set when a new absolute local Minimum (for CAPTMIN) or Maximum (for CAPTMAX) value has been
detected.
Interrupt Generation
In CAPT mode, an interrupt is generated on each filtered Fault n and each dedicated CCx channel
capture counter value. In other modes, an interrupt is only generated on an extreme captured value.
Figure 31-28. Capture Action “CAPTMAX”
TOP
"clear" update
COUNT
CC0
ZERO
FaultA Input
CC0 Event/
Interrupt
Figure 31-29. Capture Action “DERIV0”
TOP
COUNT
"update"
"match"
CC0
ZERO
WO[0]
FaultA Input
CC0 Event/
Interrupt
Hardware
Halt Action
This is configured by writing 0x1 to the Fault n Halt mode bits in the Recoverable Fault n
Configuration register (FCTRLn.HALT). When enabled, the timer/counter is halted and the cycle is
extended as long as the corresponding fault is present.
The next figure ('Waveform Generation with Halt and Restart Actions') shows an example where
both restart action and hardware halt action are enabled for Fault A. The compare channel 0 output
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 640
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
is clamped to inactive level as long as the timer/counter is halted. The timer/counter resumes the
counting operation as soon as the fault condition is no longer present. As the restart action is enabled
in this example, the timer/counter is restarted after the fault condition is no longer present.
The figure after that ('Waveform Generation with Fault Qualification, Halt, and Restart Actions') shows
a similar example, but with additionally enabled fault qualification. Here, counting is resumed after the
fault condition is no longer present.
Note that in RAMP2 and RAMP2A operations, when a new timer/counter cycle starts, the cycle index
will automatically change.
Figure 31-30. Waveform Generation with Halt and Restart Actions
MAX
"clear" update
"match"
TOP
COUNT
CC0
HALT
ZERO
Restart
Restart
Fault Input A
WO[0]
Figure 31-31. Waveform Generation with Fault Qualification, Halt, and Restart Actions
MAX
"update"
"match"
TOP
COUNT
CC0
HALT
ZERO
Resume
Fault A Input Qual
-
-
-
-
x
x
-
x
Fault Input A
WO[0]
Software
Halt Action
KEEP
This is configured by writing 0x2 to the Fault n Halt mode bits in the Recoverable Fault n
configuration register (FCTRLn.HALT). Software halt action is similar to hardware halt action, but
in order to restart the timer/counter, the corresponding fault condition must not be present anymore,
and the corresponding FAULT n bit in the STATUS register must be cleared by software.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 641
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-32. Waveform Generation with Software Halt, Fault Qualification, Keep and Restart Actions
MAX
"update"
"match"
TOP
COUNT
CC0
HALT
ZERO
Restart
Fault A Input Qual
-
-
Restart
x
-
x
Fault Input A
Software Clear
WO[0]
KEEP
FCTRLA.KEEP = 1
NO
KEEP
FCTRLA.KEEP = 0
31.6.3.6 Non-Recoverable Faults
The non-recoverable fault action will force all the compare outputs to a pre-defined level programmed into the Driver
Control register (DRVCTRL.NRE and DRVCTRL.NRV). The non-recoverable fault input (EV0 and EV1) actions are
enabled in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1).
To avoid false fault detection on external events (e.g. a glitch on an I/O port) a digital filter can be enabled using
Non-Recoverable Fault Input x Filter Value bits in the Driver Control register (DRVCTRL.FILTERVALn). Therefore, the
event detection is synchronous, and event action is delayed by the selected digital filter value clock cycles.
When the Fault Detection on Debug Break Detection bit in Debug Control register (DGBCTRL.FDDBD) is written
to '1', a non-recoverable Debug Faults State and an interrupt (DFS) is generated when the system goes in debug
operation.
In RAMP2, RAMP2A, or DSBOTH operation, when the Lock Update bit in the Control B register is set by writing
CTRLBSET.LUPD=1 and the ramp index or counter direction changes, a non-recoverable Update Fault State and the
respective interrupt (UFS) are generated.
31.6.3.7 Waveform Extension
Figure 31-33 shows a schematic diagram of actions of the four optional units that follow the recoverable fault stage
on a port pin pair: Output Matrix (OTMX), Dead-Time Insertion (DTI), SWAP and Pattern Generation. The DTI and
SWAP units can be seen as a four port pair slices:
• Slice 0 DTI0 / SWAP0 acting on port pins (WO[0], WO[WO_NUM/2 +0])
• Slice 1 DTI1 / SWAP1 acting on port pins (WO[1], WO[WO_NUM/2 +1])
And more generally:
• Slice n DTIx / SWAPx acting on port pins (WO[x], WO[WO_NUM/2 +x])
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-33. Waveform Extension Stage Details
WEX
OTMX
PORTS
DTI
SWAP
PATTERN
OTMX[x+WO_NUM/2]
PGV[x+WO_NUM/2]
P[x+WO_NUM/2]
LS
OTMX
DTIx
PGO[x+WO_NUM/2]
DTIxEN
INV[x+WO_NUM/2]
SWAPx
PGO[x]
HS
INV[x]
P[x]
OTMX[x]
PGV[x]
The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations in Table
31-4.
Table 31-4. Output Matrix Channel Pin Routing Configuration
Value
OTMX[x]
0x0
CC3
CC2
CC1
CC0
CC3
CC2
CC1
CC0
0x1
CC1
CC0
CC1
CC0
CC1
CC0
CC1
CC0
0x2
CC0
CC0
CC0
CC0
CC0
CC0
CC0
CC0
0x3
CC1
CC1
CC1
CC1
CC1
CC1
CC1
CC0
Notes on Table 31-4:
•
Configuration 0x0 is the default configuration. The channel location is the default one, and channels are
distributed on outputs modulo the number of channels. Channel 0 is routed to the Output matrix output
OTMX[0], and Channel 1 to OTMX[1]. If there are more outputs than channels, then channel 0 is duplicated
to the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and so on.
• Configuration 0x1 distributes the channels on output modulo half the number of channels. This assigns twice the
number of output locations to the lower channels than the default configuration. This can be used, for example,
to control the four transistors of a full bridge using only two compare channels.
Using pattern generation, some of these four outputs can be overwritten by a constant level, enabling flexible
drive of a full bridge in all quadrant configurations.
• Configuration 0x2 distributes compare channel 0 (CC0) to all port pins. With pattern generation, this
configuration can control a stepper motor.
• Configuration 0x3 distributes the compare channel CC0 to the first output, and the channel CC1 to all other
outputs. Together with pattern generation and the fault extension, this configuration can control up to seven LED
strings, with a boost stage.
Table
•
31-5. Example: four compare channels on four outputs
Value
OTMX[3]
OTMX[2]
OTMX[1]
OTMX[0]
0x0
CC3
CC2
CC1
CC0
0x1
CC1
CC0
CC1
CC0
0x2
CC0
CC0
CC0
CC0
0x3
CC1
CC1
CC1
CC0
The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted high side
(HS) of the wave generator output forced at low level. This OFF time is called dead time. Dead-time insertion ensures
that the LS and HS will never switch simultaneously.
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TCC – Timer/Counter for Control Applications
The DTI stage consists of four equal dead-time insertion generators; one for each of the first four compare channels.
Figure 31-34 shows the block diagram of one DTI generator. The four channels have a common register which
controls the dead time, which is independent of high side and low side setting.
Figure 31-34. Dead-Time Generator Block Diagram
DTHS
DTLS
Dead Time Generator
LOAD
EN
Counter
=0
OTMX output
D
"DTLS"
Q
(To PORT)
"DTHS"
Edge Detect
(To PORT)
As shown in Figure 31-35, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle until it
reaches zero. A non-zero counter value will force both the low side and high side outputs into their OFF state. When
the output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input.
When the output changes from low to high (positive edge) it initiates a counter reload of the DTLS register. When the
output changes from high to low (negative edge) it reloads the DTHS register.
Figure 31-35. Dead-Time Generator Timing Diagram
"dti_cnt"
T
tP
tDTILS
t DTIHS
"OTMX output"
"DTLS"
"DTHS"
The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern
generation features are primarily intended for handling the commutation sequence in brushless DC motors (BLDC),
stepper motors, and full bridge control. See also Figure 31-36.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-36. Pattern Generator Block Diagram
COUNT
UPDATE
BV
PGEB[7:0]
EN
BV
PGE[7:0]
PGVB[7:0]
EN
SWAP output
PGV[7:0]
WOx[7:0]
As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE condition
set by the timer/counter waveform generation operation. If synchronization is not required by the application, the
software can simply access directly the PATT.PGE, PATT.PGV bits registers.
31.6.4
DMA, Interrupts, and Events
Table 31-6. Module Requests for TCC
Condition
Interrupt
request
Event
output
Overflow / Underflow
Yes
Yes
Channel Compare Match or Yes
Capture
Yes
Retrigger
Yes
Yes
Count
Yes
Yes
Capture Overflow Error
Yes
Debug Fault State
Yes
Recoverable Faults
Yes
Non-Recoverable Faults
Yes
Event input DMA
request
Yes(2)
TCCx Event 0 input
Yes(4)
TCCx Event 1 input
Yes(5)
DMA request is cleared
Yes(1)
On DMA acknowledge
Yes(3)
For circular buffering: on
DMA acknowledge
For capture channel:
when CCx register is
read
Notes:
1. DMA request set on overflow, underflow or re-trigger conditions.
2. Can perform capture or generate recoverable fault on an event input.
3. In capture or circular modes.
4. On event input, either action can be executed:
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
5.
– re-trigger counter
– control counter direction
– stop the counter
– decrement the counter
– perform period and pulse width capture
– generate non-recoverable fault
On event input, either action can be executed:
– re-trigger counter
– increment or decrement counter depending on direction
– start the counter
– increment or decrement counter based on direction
– increment counter regardless of direction
– generate non-recoverable fault
31.6.4.1 DMA Operation
The TCC can generate the following DMA requests:
Counter overflow
(OVF)
The TCC generates a DMA request on each cycle when an update condition (Overflow,
Underflow or Re-trigger) is detected.
In both cases, the request is cleared by hardware on DMA acknowledge.
Channel Match
(MCx)
A DMA request is set only on a compare match . The request is cleared by hardware on DMA
acknowledge.
Channel Capture
(MCx)
For a capture channel, the request is set when valid data is present in the CCx register, and
cleared once the CCx register is read.
DMA Operation with Circular Buffer
When circular buffer operation is enabled, the Buffer registers must be written in a correct order and synchronized to
the update times of the timer. The DMA triggers of the TCC provide a way to ensure a safe and correct update of
circular buffers.
Note: Circular buffer are intended to be used with RAMP2, RAMP2A and DSBOTH operation only.
DMA Operation with Circular Buffer in RAMP2 and RAMP2A Mode
When a CCx channel is selected as a circular buffer, the related DMA request is not set on a compare match
detection, but on start of ramp B.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of ramp A with an
effective DMA transfer on previous ramp B (DMA acknowledge).
The update of all circular buffer values for ramp A can be done through a DMA channel triggered on a MC trigger.
The update of all circular buffer values for ramp B, can be done through a second DMA channel triggered by the
overflow DMA request.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Figure 31-37. DMA Triggers in RAMP and RAMP2 Operation Mode and Circular Buffer Enabled
Ramp
Cycle
A
B
A
B
A
B
N-1
N-2
N
"update"
COUNT
ZERO
STATUS.IDX
DMA_CCx_req
DMA Channel i
Update ramp A
DMA_OVF_req
DMA Channel j
Update ramp B
DMA Operation with Circular Buffer in DSBOTH Mode
When a CC channel is selected as a circular buffer, the related DMA request is not set on a compare match
detection, but on start of down-counting phase.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of up-counting phase
with an effective DMA transfer on previous down-counting phase (DMA acknowledge).
When up-counting, all circular buffer values can be updated through a DMA channel triggered by MC trigger. When
down-counting, all circular buffer values can be updated through a second DMA channel, triggered by the OVF DMA
request.
Figure 31-38. DMA Triggers in DSBOTH Operation Mode and Circular Buffer Enabled
Cycle
N-2
N
N-1
New Parameter Set
Old Parameter Set
"update"
COUNT
ZERO
CTRLB.DIR
DMA_CCx_req
DMA Channel i
Update Rising
DMA_OVF_req
DMA Channel j
Update Rising
31.6.4.2 Interrupts
The TCC has the following interrupt sources:
•
•
•
•
•
Overflow/Underflow (OVF)
Retrigger (TRG)
Count (CNT) - refer also to description of EVCTRL.CNTSEL.
Capture Overflow Error (ERR)
Non-Recoverable Update Fault (UFS)
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
•
•
•
•
Debug Fault State (DFS)
Recoverable Faults (FAULTn)
Non-recoverable Faults (FAULTx)
Compare Match or Capture Channels (MCx)
These interrupts are asynchronous wake-up sources. See Sleep Mode Entry and Exit Table in PM/Sleep Mode
Controller section for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled, or the TCC is reset. See 31.8.12 INTFLAG for details on how to clear
interrupt flags. The TCC has one common interrupt request line for all the interrupt sources. The user must read the
INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
16.6.2.8 Sleep Mode Controller
16.6.2.8.1 IDLE Mode
16.6.2.8.2 STANDBY Mode
31.6.4.3 Events
The TCC can generate the following output events:
• Overflow/Underflow (OVF)
• Trigger (TRG)
• Counter (CNT) For further details, refer to EVCTRL.CNTSEL description.
• Compare Match or Capture on compare/capture channels: MCx
Writing a '1' ('0') to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables (disables) the
corresponding output event. Refer also to EVSYS – Event System.
The TCC can take the following actions on a channel input event (MCx):
• Capture event
• Generate a recoverable or non-recoverable fault
The TCC can take the following actions on counter Event 1 (TCCx EV1):
• Counter re-trigger
• Counter direction control
• Stop the counter
• Decrement the counter on event
• Period and pulse width capture
• Non-recoverable fault
The TCC can take the following actions on counter Event 0 (TCCx EV0):
• Counter re-trigger
• Count on event (increment or decrement, depending on counter direction)
• Counter start - start counting on the event rising edge. Further events will not restart the counter; the counter will
keep on counting using prescaled GCLK_TCCx, until it reaches TOP or ZERO, depending on the direction.
• Counter increment on event. This will increment the counter, irrespective of the counter direction.
• Count during active state of an asynchronous event (increment or decrement, depending on counter direction).
In this case, the counter will be incremented or decremented on each cycle of the prescaled clock, as long as
the event is active.
• Non-recoverable fault
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TCC – Timer/Counter for Control Applications
The counter Event Actions are available in the Event Control registers (EVCTRL.EVACT0 and EVCTRL.EVACT1).
For further details, refer to EVCTRL.
Writing a '1' ('0') to an Event Input bit in the Event Control register (EVCTRL.MCEIx or EVCTRL.TCEIx) enables
(disables) the corresponding action on input event.
Note: When several events are connected to the TCC, the enabled action will apply for each of the incoming events.
Refer to EVSYS – Event System for details on how to configure the event system.
Related Links
24. EVSYS – Event System
31.6.5
Sleep Mode Operation
The TCC can be configured to operate in any sleep mode. To be able to run in standby the RUNSTDBY bit in the
Control A register (CTRLA.RUNSTDBY) must be '1'. The MODULE can in any sleep mode wake up the device using
interrupts or perform actions through the Event System.
31.6.6
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE)
The following registers are synchronized when written:
•
•
•
•
•
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Status register (STATUS)
Pattern and Pattern Buffer registers (PATT and PATTB)
Waveform register (WAVE)
Count Value register (COUNT)
Period Value and Period Buffer Value registers (PER and PERB)
Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBx)
The following registers are synchronized when read:
•
•
•
•
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Count Value register (COUNT): synchronization is done on demand through READSYNC command
(CTRLBSET.CMD)
Pattern and Pattern Buffer registers (PATT and PATTB)
Waveform register (WAVE)
Period Value and Period Buffer Value registers (PER and PERB)
Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBx)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.7
Register Summary
Offset
Name
0x00
CTRLA
0x04
0x05
0x06
...
0x07
CTRLBCLR
CTRLBSET
0x08
0x0C
0x10
0x14
0x18
0x1C
...
0x1D
0x1E
0x1F
SYNCBUSY
FCTRLA
FCTRLB
WEXCTRL
DRVCTRL
DBGCTRL
Reserved
0x24
INTENCLR
0x30
7:0
15:8
23:16
31:24
7:0
7:0
6
5
4
3
RESOLUTION[1:0]
ALOCK
PRESCYNC[1:0]
1
0
ENABLE
SWRST
PRESCALER[2:0]
RUNSTDBY
CPTEN3
IDXCMD[1:0]
IDXCMD[1:0]
CMD[2:0]
CMD[2:0]
2
CPTEN2
ONESHOT
ONESHOT
CPTEN1
LUPD
LUPD
CPTEN0
DIR
DIR
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
PER
WAVE
PATT
COUNT
CCB3
CCB2
CCB1
RESTART
BLANK[1:0]
CAPTURE[2:0]
QUAL
RESTART
BLANK[1:0]
CAPTURE[2:0]
QUAL
STATUS
CC3
CCB0
CTRLB
CC2
PERB
ENABLE
CC1
WAVEB
SWRST
CC0
PATTB
KEEP
CHSEL[1:0]
BLANKVAL[7:0]
SRC[1:0]
HALT[1:0]
FILTERVAL[3:0]
KEEP
CHSEL[1:0]
BLANKVAL[7:0]
SRC[1:0]
HALT[1:0]
FILTERVAL[3:0]
NRE7
NRV7
INVEN7
NRE6
NRE5
NRV6
NRV5
INVEN6
INVEN5
FILTERVAL1[3:0]
DTIEN3
DTLS[7:0]
DTHS[7:0]
NRE4
NRE3
NRV4
NRV3
INVEN4
INVEN3
DTIEN2
OTMX[1:0]
DTIEN1
DTIEN0
NRE2
NRE1
NRV2
NRV1
INVEN2
INVEN1
FILTERVAL0[3:0]
NRE0
NRV0
INVEN0
Reserved
EVCTRL
0x2C
7
Reserved
0x20
0x28
Bit Pos.
INTENSET
INTFLAG
STATUS
7:0
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
FDDBD
CNTSEL[1:0]
TCEI1
TCEI0
FAULT1
FAULT1
FAULT1
PERBV
FAULT1
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FAULT0
FAULT0
FAULT0
WAVEBV
FAULT0
TCINV1
FAULTB
FAULTB
FAULTB
PATTBV
FAULTB
EVACT1[2:0]
TCINV0
EVACT0[2:0]
TRGEO
MCEI1
MCEO1
TRG
OVFEO
MCEI0
MCEO0
OVF
MC1
MC0
MCEI3
MCEO3
ERR
DFS
MC3
CNTEO
MCEI2
MCEO2
CNT
UFS
MC2
ERR
DFS
MC3
CNT
UFS
MC2
TRG
OVF
MC1
MC0
ERR
DFS
MC3
CNT
UFS
MC2
TRG
OVF
MC1
MC0
DFS
FAULT1IN
CCBV3
CMP3
UFS
FAULT0IN
CCBV2
CMP2
IDX
FAULTBIN
CCBV1
CMP1
STOP
FAULTAIN
CCBV0
CMP0
FAULTA
FAULTA
FAULTA
FAULTA
DBGRUN
Complete Datasheet
DS40001882H-page 650
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
...........continued
Offset
Name
0x34
COUNT
0x38
PATT
0x3A
...
0x3B
Reserved
0x3C
0x40
0x44
0x48
0x4C
WAVE
PER
CC0
CC1
CC2
0x50
CC3
0x54
...
0x63
Reserved
0x64
PATTB
0x66
...
0x67
Reserved
0x68
0x6C
0x70
0x74
WAVEB
PERB
CCB0
CCB1
Bit Pos.
7
6
5
4
3
7:0
15:8
COUNT[7:0]
COUNT[15:8]
23:16
31:24
7:0
15:8
COUNT[23:16]
PGE7
PGV7
PGE6
PGV6
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CIPEREN
7:0
15:8
PGEB7
PGVB7
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CIPERENB
PGE5
PGV5
PGE4
PGV4
PGE3
PGV3
2
1
0
PGE2
PGV2
PGE1
PGV1
PGE0
PGV0
RAMP[1:0]
CICCEN3
CICCEN2
POL3
POL2
SWAP3
SWAP2
DITHER[5:0]
PER[9:2]
PER[17:10]
PER[1:0]
CC[1:0]
WAVEGEN[2:0]
CICCEN1
CICCEN0
POL1
POL0
SWAP1
SWAP0
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[1:0]
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[1:0]
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[1:0]
DITHER[5:0]
CC[9:2]
CC[17:10]
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PGEB6
PGVB6
PERB[1:0]
PGEB5
PGVB5
PGEB4
PGVB4
PGEB3
PGVB3
PGEB2
PGVB2
RAMPB[1:0]
CICCENB3
CICCENB2
POLB3
POLB2
SWAPB 3
SWAPB 2
DITHERB[5:0]
PERB[9:2]
PERB[17:10]
CCB[1:0]
PGEB1
PGVB1
PGEB0
PGVB0
WAVEGENB[2:0]
CICCENB1
CICCENB0
POLB1
POLB0
SWAPB 1
SWAPB 0
DITHERB[5:0]
CCB[9:2]
CCB[17:10]
CCB[1:0]
DITHERB[5:0]
CCB[9:2]
CCB[17:10]
Complete Datasheet
DS40001882H-page 651
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
...........continued
Offset
Name
0x78
CCB2
0x7C
31.8
CCB3
Bit Pos.
7
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
6
5
4
3
CCB[1:0]
2
1
0
DITHERB[5:0]
CCB[9:2]
CCB[17:10]
CCB[1:0]
DITHERB[5:0]
CCB[9:2]
CCB[17:10]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Enable-Protected, Write-Synchronized (ENABLE, SWRST)
31
30
29
28
27
CPTEN3
R/W
0
26
CPTEN2
R/W
0
25
CPTEN1
R/W
0
24
CPTEN0
R/W
0
23
22
21
20
19
18
17
16
15
14
ALOCK
R/W
0
11
RUNSTDBY
R/W
0
10
8
R/W
0
9
PRESCALER[2:0]
R/W
0
R/W
0
3
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
Access
Reset
13
12
PRESCYNC[1:0]
R/W
R/W
0
0
6
5
RESOLUTION[1:0]
R/W
R/W
0
0
4
Bits 24, 25, 26, 27 – CPTEN Capture Channel x Enable
These bits are used to select the capture or compare operation on channel x.
Writing a '1' to CPTENx enables capture on channel x.
Writing a '0' to CPTENx disables capture on channel x.
Bit 14 – ALOCK Auto Lock
This bit is not synchronized.
Value
Description
0
The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/underflow, and
re-trigger events
1
CTRLB.LUPD is set to '1' on each overflow/underflow or re-trigger event.
Bits 13:12 – PRESCYNC[1:0] Prescaler and Counter Synchronization
These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock, or on
the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on re-trigger event.
These bits are not synchronized.
Value
Name
0x0
0x1
GCLK
PRESC
0x2
0x3
RESYNC
Reserved
Description
Counter Reloaded
Prescaler
Reload or reset Counter on next GCLK
Reload or reset Counter on next
prescaler clock
Reload or reset Counter on next GCLK
Reset prescaler counter
Bit 11 – RUNSTDBY Run in Standby
This bit is used to keep the TCC running in standby mode.
This bit is not synchronized.
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Complete Datasheet
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
0
1
Description
The TCC is halted in standby.
The TCC continues to run in standby.
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the Counter prescaler factor.
These bits are not synchronized.
Value
Name
Description
0x0
DIV1
Prescaler: GCLK_TCC
0x1
DIV2
Prescaler: GCLK_TCC/2
0x2
DIV4
Prescaler: GCLK_TCC/4
0x3
DIV8
Prescaler: GCLK_TCC/8
0x4
DIV16
Prescaler: GCLK_TCC/16
0x5
DIV64
Prescaler: GCLK_TCC/64
0x6
DIV256
Prescaler: GCLK_TCC/256
0x7
DIV1024
Prescaler: GCLK_TCC/1024
Bits 6:5 – RESOLUTION[1:0] Dithering Resolution
These bits increase the TCC resolution by enabling the dithering options.
These bits are not synchronized.
Table 31-7. Dithering
Value
Name
Description
0x0
0x1
NONE
DITH4
0x2
DITH5
0x3
DITH6
The dithering is disabled.
Dithering is done every 16 PWM frames. PER[3:0] and
CCx[3:0] contain dithering pattern selection.
Dithering is done every 32 PWM frames. PER[4:0] and
CCx[4:0] contain dithering pattern selection.
Dithering is done every 64 PWM frames. PER[5:0] and
CCx[5:0] contain dithering pattern selection.
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TCC (except DBGCTRL) to their initial state, and the TCC will be
disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.2
Control B Clear
Name:
Offset:
Reset:
Property:
CTRLBCLR
0x04
0x00
PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBSET) register.
Bit
Access
Reset
7
R/W
0
6
CMD[2:0]
R/W
0
5
R/W
0
4
3
IDXCMD[1:0]
R/W
R/W
0
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] TCC Command
Writing zero to this bit group has no effect.
Writing a '1' to any of these bits will clear the pending command.
Value
Name
Description
0x0
NONE
No action
0x1
RETRIGGER
Clear start, restart or retrigger
0x2
STOP
Force stop
0x3
UPDATE
Force update of double buffered registers
0x4
READSYNC
Force COUNT read synchronization
Bits 4:3 – IDXCMD[1:0] Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter
update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command
is cleared.
Writing zero to these bits has no effect.
Writing a '1' to any of these bits will clear the pending command.
Value
Name
Description
0x0
DISABLE
DISABLE Command disabled: IDX toggles between cycles A and B
0x1
SET
Set IDX: cycle B will be forced in the next cycle
0x2
CLEAR
Clear IDX: cycle A will be forced in next cycle
0x3
HOLD
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting on
the next overflow/underflow condition or on a stop command.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable the one-shot operation.
Value
Description
0
The TCC will update the counter value on overflow/underflow condition and continue operation.
1
The TCC will stop counting on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is cleared, the hardware UPDATE registers with value from their buffered registers is enabled.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the registers updates on hardware UPDATE condition.
Value
Description
0
The CCBx, PERB, PGVB, and PGEB buffer registers values are copied into the corresponding CCx,
PER, PGV, and PGE registers on hardware update condition.
1
The CCBx, PERB, PGVB, and PGEB buffer registers values are not copied into the corresponding
CCx, PER, PGV, and PGE registers on hardware update condition.
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Complete Datasheet
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.3
Control B Set
Name:
Offset:
Reset:
Property:
CTRLBSET
0x05
0x00
PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBCLR) register.
Bit
Access
Reset
7
R/W
0
6
CMD[2:0]
R/W
0
5
R/W
0
4
3
IDXCMD[1:0]
R/W
R/W
0
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command has
been executed, the CMD bit field will be read back as zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing zero to this bit group has no effect
Writing a valid value to this bit group will set the associated command.
Value
Name
Description
0x0
NONE
No action
0x1
RETRIGGER
Force start, restart or retrigger
0x2
STOP
Force stop
0x3
UPDATE
Force update of double buffered registers
0x4
READSYNC
Force a read synchronization of COUNT
Bits 4:3 – IDXCMD[1:0] Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter
update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command
is cleared.
Writing a zero to these bits has no effect.
Writing a valid value to these bits will set a command.
Value
Name
Description
0x0
DISABLE
Command disabled: IDX toggles between cycles A and B
0x1
SET
Set IDX: cycle B will be forced in the next cycle
0x2
CLEAR
Clear IDX: cycle A will be forced in next cycle
0x3
HOLD
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next
overflow/underflow condition or a stop command.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the one-shot operation.
Value
Description
0
The TCC will count continuously.
1
The TCC will stop counting on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is set, the hardware UPDATE registers with value from their buffered registers is disabled.
Disabling the update ensures that all buffer registers are valid before an hardware update is performed. After all the
buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will disable the registers updates on hardware UPDATE condition.
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 657
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
0
1
Description
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into CCx, PER,
PGV, PGO and SWAPx registers on hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
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Complete Datasheet
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.4
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x08
0x00000000
-
31
30
29
28
27
26
25
24
23
22
CCB3
R
0
21
CCB2
R
0
20
CCB1
R
0
19
CCB0
R
0
18
PERB
R
0
17
WAVEB
R
0
16
PATTB
R
0
15
14
13
12
11
CC3
R
0
10
CC2
R
0
9
CC1
R
0
8
CC0
R
0
7
PER
R
0
6
WAVE
R
0
5
PATT
R
0
4
COUNT
R
0
3
STATUS
R
0
2
CTRLB
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 19, 20, 21, 22 – CCB Compare/Capture Buffer Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare/Capture Buffer Channel x register between the clock
domains is complete.
This bit is set when the synchronization of Compare/Capture Buffer Channel x register between clock domains is
started.
CCBx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each
TCC feature list.
Bit 18 – PERB PER Buffer Synchronization Busy
This bit is cleared when the synchronization of PERB register between the clock domains is complete.
This bit is set when the synchronization of PERB register between clock domains is started.
Bit 17 – WAVEB WAVE Buffer Synchronization Busy
This bit is cleared when the synchronization of WAVEB register between the clock domains is complete.
This bit is set when the synchronization of WAVEB register between clock domains is started.
Bit 16 – PATTB PATT Buffer Synchronization Busy
This bit is cleared when the synchronization of PATTB register between the clock domains is complete.
This bit is set when the synchronization of PATTB register between clock domains is started.
Bits 8, 9, 10, 11 – CC Compare/Capture Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock domains is
complete.
This bit is set when the synchronization of Compare/Capture Channel x register between clock domains is started.
CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each
TCC feature list.
This bit is set when the synchronization of CCx register between clock domains is started.
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Complete Datasheet
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Bit 7 – PER PER Synchronization Busy
This bit is cleared when the synchronization of PER register between the clock domains is complete.
This bit is set when the synchronization of PER register between clock domains is started.
Bit 6 – WAVE WAVE Synchronization Busy
This bit is cleared when the synchronization of WAVE register between the clock domains is complete.
This bit is set when the synchronization of WAVE register between clock domains is started.
Bit 5 – PATT PATT Synchronization Busy
This bit is cleared when the synchronization of PATTERN register between the clock domains is complete.
This bit is set when the synchronization of PATTERN register between clock domains is started.
Bit 4 – COUNT COUNT Synchronization Busy
This bit is cleared when the synchronization of COUNT register between the clock domains is complete.
This bit is set when the synchronization of COUNT register between clock domains is started.
Bit 3 – STATUS STATUS Synchronization Busy
This bit is cleared when the synchronization of STATUS register between the clock domains is complete.
This bit is set when the synchronization of STATUS register between clock domains is started.
Bit 2 – CTRLB CTRLB Synchronization Busy
This bit is cleared when the synchronization of CTRLB register between the clock domains is complete.
This bit is set when the synchronization of CTRLB register between clock domains is started.
Bit 1 – ENABLE ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE bit between clock domains is started.
Bit 0 – SWRST SWRST Synchronization Busy
This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.
This bit is set when the synchronization of SWRST bit between clock domains is started.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.5
Fault Control A and B
Name:
Offset:
Reset:
Property:
Bit
FCTRLn
0x0C + n*0x04 [n=0..1]
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
Access
Reset
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
CAPTURE[2:0]
R/W
0
Bit
Access
Reset
Bit
Access
Reset
26
25
FILTERVAL[3:0]
R/W
R/W
0
0
R/W
0
Bit
Access
Reset
27
R/W
0
7
RESTART
R/W
0
6
5
BLANK[1:0]
R/W
0
R/W
0
20
19
BLANKVAL[7:0]
R/W
R/W
0
0
12
11
24
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
CHSEL[1:0]
HALT[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
QUAL
R/W
0
3
KEEP
R/W
0
2
1
R/W
0
0
SRC[1:0]
R/W
0
R/W
0
Bits 27:24 – FILTERVAL[3:0] Recoverable Fault n Filter Value
These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero when MCEx
event is used as synchronous event.
Bits 23:16 – BLANKVAL[7:0] Recoverable Fault n Blanking Value
These bits determine the duration of the blanking of the fault input source. Activation and edge selection of the blank
filtering are done by the BLANK bits (FCTRLn.BLANK).
When enabled, the fault input source is internally disabled for BLANKVAL* prescaled GCLK_TCC periods after the
detection of the waveform edge.
Bits 14:12 – CAPTURE[2:0] Recoverable Fault n Capture Action
These bits select the capture and Fault n interrupt/event conditions.
Table 31-8. Fault n Capture Action
Value
Name
0x0
0x1
DISABLE
CAPT
0x2
CAPTMIN
0x3
CAPTMAX
0x4
LOCMIN
0x5
LOCMAX
Description
Capture on valid recoverable Fault n is disabled
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each new captured value.
On rising edge of a valid recoverable Fault n, capture counter value on channel selected
by CHSEL[1:0], if COUNT value is lower than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local minimum detection.
On rising edge of a valid recoverable Fault n, capture counter value on channel selected
by CHSEL[1:0], if COUNT value is higher than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local maximun detection.
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local minimum value detection.
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun detection.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
...........continued
Value
Name
0x6
DERIV0
0x7
Description
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun or minimum detection.
CAPTMARK Capture with ramp index as MSB value.
Bits 11:10 – CHSEL[1:0] Recoverable Fault n Capture Channel
These bits select the channel for capture operation triggered by recoverable Fault n.
Value
Name
Description
0x0
CC0
Capture value stored into CC0
0x1
CC1
Capture value stored into CC1
0x2
CC2
Capture value stored into CC2
0x3
CC3
Capture value stored into CC3
Bits 9:8 – HALT[1:0] Recoverable Fault n Halt Operation
These bits select the halt action for recoverable Fault n.
Value
Name
Description
0x0
DISABLE
Halt action disabled
0x1
HW
Hardware halt action
0x2
SW
Software halt action
0x3
NR
Non-recoverable fault
Bit 7 – RESTART Recoverable Fault n Restart
Setting this bit enables restart action for Fault n.
Value
Description
0
Fault n restart action is disabled.
1
Fault n restart action is enabled.
Bits 6:5 – BLANK[1:0] Recoverable Fault n Blanking Operation
These bits, select the blanking start point for recoverable Fault n.
Value
Name
Description
0x0
START
Blanking applied from start of the Ramp period
0x1
RISE
Blanking applied from rising edge of the waveform output
0x2
FALL
Blanking applied from falling edge of the waveform output
0x3
BOTH
Blanking applied from each toggle of the waveform output
Bit 4 – QUAL Recoverable Fault n Qualification
Setting this bit enables the recoverable Fault n input qualification.
Value
Description
0
The recoverable Fault n input is not disabled on CMPx value condition.
1
The recoverable Fault n input is disabled when output signal is at inactive level (CMPx == 0).
Bit 3 – KEEP Recoverable Fault n Keep
Setting this bit enables the Fault n keep action.
Value
Description
0
The Fault n state is released as soon as the recoverable Fault n is released.
1
The Fault n state is released at the end of TCC cycle.
Bits 1:0 – SRC[1:0] Recoverable Fault n Source
These bits select the TCC event input for recoverable Fault n.
Event system channel connected to MCEx event input, must be configured to route the event asynchronously, when
used as a recoverable Fault n input.
Value
Name
Description
0x0
DISABLE
Fault input disabled
0x1
ENABLE
MCEx (x=0,1) event input
0x2
INVERT
Inverted MCEx (x=0,1) event input
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
0x3
Name
ALTFAULT
© 2021 Microchip Technology Inc.
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Description
Alternate fault (A or B) state at the end of the previous period.
Complete Datasheet
DS40001882H-page 663
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.6
Waveform Extension Control
Name:
Offset:
Reset:
Property:
Bit
31
WEXCTRL
0x14
0x00000000
PAC Write-Protection, Enable-Protected
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
DTHS[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
DTLS[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
DTIEN3
R/W
0
10
DTIEN2
R/W
0
9
DTIEN1
R/W
0
8
DTIEN0
R/W
0
7
6
5
4
3
2
1
0
Access
Reset
Bit
OTMX[1:0]
Access
Reset
R/W
0
R/W
0
Bits 31:24 – DTHS[7:0] Dead-Time High Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time high side.
Bits 23:16 – DTLS[7:0] Dead-time Low Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time low side.
Bits 8, 9, 10, 11 – DTIENx Dead-time Insertion Generator x Enable
Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will
override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively.
Value
Description
0
No dead-time insertion override.
1
Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal.
Bits 1:0 – OTMX[1:0] Output Matrix
These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according to
31.6.3.7 Waveform Extension.
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Complete Datasheet
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.7
Driver Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
R/W
0
DRVCTRL
0x18
0x00000000
PAC Write-Protection, Enable-Protected
30
29
FILTERVAL1[3:0]
R/W
R/W
0
0
28
27
R/W
0
R/W
0
26
25
FILTERVAL0[3:0]
R/W
R/W
0
0
24
R/W
0
23
INVEN7
R/W
0
22
INVEN6
R/W
0
21
INVEN5
R/W
0
20
INVEN4
R/W
0
19
INVEN3
R/W
0
18
INVEN2
R/W
0
17
INVEN1
R/W
0
16
INVEN0
R/W
0
15
NRV7
R/W
0
14
NRV6
R/W
0
13
NRV5
R/W
0
12
NRV4
R/W
0
11
NRV3
R/W
0
10
NRV2
R/W
0
9
NRV1
R/W
0
8
NRV0
R/W
0
7
NRE7
R/W
0
6
NRE6
R/W
0
5
NRE5
R/W
0
4
NRE4
R/W
0
3
NRE3
R/W
0
2
NRE2
R/W
0
1
NRE1
R/W
0
0
NRE0
R/W
0
Bits 31:28 – FILTERVAL1[3:0] Non-Recoverable Fault Input 1 Filter Value
These bits define the filter value applied on TCE1 event input line. When the TCE1 event input line is configured as a
synchronous event, this value must be 0x0.
Bits 27:24 – FILTERVAL0[3:0] Non-Recoverable Fault Input 0 Filter Value
These bits define the filter value applied on TCE0 event input line. When the TCE0 event input line is configured as a
synchronous event, this value must be 0x0.
Bits 16, 17, 18, 19, 20, 21, 22, 23 – INVENx Waveform Output x Inversion
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
Bits 8, 9, 10, 11, 12, 13, 14, 15 – NRVx NRVx Non-Recoverable State x Output Value
These bits define the value of the enabled override outputs, under non-recoverable fault condition.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – NREx Non-Recoverable State x Output Enable
These bits enable the override of individual outputs by NRVx value, under non-recoverable fault condition.
Value
Description
0
Non-recoverable fault tri-state the output.
1
Non-recoverable faults set the output to NRVx level.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.8
Debug control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x1E
0x00
PAC Write-Protection
6
5
4
3
Access
Reset
2
FDDBD
R/W
0
1
0
DBGRUN
R/W
0
Bit 2 – FDDBD Fault Detection on Debug Break Detection
This bit is not affected by software Reset and should not be changed by software while the TCC is enabled.
By default this bit is zero, and the on-chip debug (OCD) fault protection is disabled.
Value
Description
0
No faults are generated when TCC is halted in Debug mode.
1
A non recoverable fault is generated and FAULTD flag is set when TCC is halted in Debug mode.
Bit 0 – DBGRUN Debug Running State
This bit is not affected by software Reset and should not be changed by software while the TCC is enabled.
Value
Description
0
The TCC is halted when the device is halted in Debug mode.
1
The TCC continues normal operation when the device is halted in Debug mode.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.9
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x20
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
MCEO3
R/W
0
26
MCEO2
R/W
0
25
MCEO1
R/W
0
24
MCEO0
R/W
0
23
22
21
20
19
MCEI3
R/W
0
18
MCEI2
R/W
0
17
MCEI1
R/W
0
16
MCEI0
R/W
0
15
TCEI1
R/W
0
14
TCEI0
R/W
0
13
TCINV1
R/W
0
12
TCINV0
R/W
0
11
10
CNTEO
R/W
0
9
TRGEO
R/W
0
8
OVFEO
R/W
0
5
4
EVACT1[2:0]
R/W
0
3
2
0
R/W
0
R/W
0
1
EVACT0[2:0]
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
CNTSEL[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bits 24, 25, 26, 27 – MCEOx Match or Capture Channel x Event Output Enable
These bits control if the match/capture event on channel x is enabled and will be generated for every match or
capture.
Value
Description
0
Match/capture x event is disabled and will not be generated.
1
Match/capture x event is enabled and will be generated for every compare/capture on channel x.
Bits 16, 17, 18, 19 – MCEIx Match or Capture Channel x Event Input Enable
These bits indicate if the match/capture x incoming event is enabled
These bits are used to enable match or capture input events to the CCx channel of TCC.
Value
Description
0
Incoming events are disabled.
1
Incoming events are enabled.
Bits 14, 15 – TCEIx Timer/Counter Event Input x Enable
This bit is used to enable input event x to the TCC.
Value
Description
0
Incoming event x is disabled.
1
Incoming event x is enabled.
Bits 12, 13 – TCINVx Timer/Counter Event x Invert Enable
This bit inverts the event x input.
Value
Description
0
Input event source x is not inverted.
1
Input event source x is inverted.
Bit 10 – CNTEO Timer/Counter Event Output Enable
This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of
counter cycle depending of CNTSEL[1:0] settings.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
0
1
Description
Counter cycle output event is disabled and will not be generated.
Counter cycle output event is enabled and will be generated depend of CNTSEL[1:0] value.
Bit 9 – TRGEO Retrigger Event Output Enable
This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter
retriggers operation.
Value
Description
0
Counter retrigger event is disabled and will not be generated.
1
Counter retrigger event is enabled and will be generated for every counter retrigger.
Bit 8 – OVFEO Overflow/Underflow Event Output Enable
This bit is used to enable the overflow/underflow event. When enabled an event will be generated when the counter
reaches the TOP or the ZERO value.
Value
Description
0
Overflow/underflow counter event is disabled and will not be generated.
1
Overflow/underflow counter event is enabled and will be generated for every counter overflow/
underflow.
Bits 7:6 – CNTSEL[1:0] Timer/Counter Interrupt and Event Output Selection
These bits define on which part of the counter cycle the counter event output is generated.
Value
Name
Description
0x0
BEGIN
An interrupt/event is generated at begin of each counter cycle
0x1
END
An interrupt/event is generated at end of each counter cycle
0x2
BETWEEN An interrupt/event is generated between each counter cycle.
0x3
BOUNDARY An interrupt/event is generated at begin of first counter cycle, and end of last counter
cycle.
Bits 5:3 – EVACT1[2:0] Timer/Counter Event Input 1 Action
These bits define the action the TCC will perform on TCE1 event input.
Value
Name
Description
0x0
OFF
Event action disabled.
0x1
RETRIGGER
Start, restart or re-trigger TC on event
0x2
DIR (asynch)
Direction control
0x3
STOP
Stop TC on event
0x4
DEC
Decrement TC on event
0x5
PPW
Period captured into CC0 Pulse Width on CC1
0x6
PWP
Period captured into CC1 Pulse Width on CC0
0x7
FAULT
Non-recoverable Fault
Bits 2:0 – EVACT0[2:0] Timer/Counter Event Input 0 Action
These bits define the action the TCC will perform on TCE0 event input 0.
Value
Name
Description
0x0
OFF
Event action disabled.
0x1
RETRIGGER
Start, restart or re-trigger TC on event
0x2
COUNTEV
Count on event.
0x3
START
Start TC on event
0x4
INC
Increment TC on EVENT
0x5
COUNT (async)
Count on active state of asynchronous event
0x6
Reserved
0x7
FAULT
Non-recoverable Fault
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.10 Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x24
0x00000000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
7
6
5
4
3
ERR
R/W
0
2
CNT
R/W
0
1
TRG
R/W
0
0
OVF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19 – MCx Match or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTB Recoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Writing a '1' to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the Recoverable
Fault B interrupt.
Value
Description
0
The Recoverable Fault B interrupt is disabled.
1
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTA Recoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Recoverable Fault A Interrupt Disable/Enable bit, which disables the Recoverable
Fault A interrupt.
Value
Description
0
The Recoverable Fault A interrupt is disabled.
1
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFS Non-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Debug Fault State Interrupt Disable/Enable bit, which disables the Debug Fault
State interrupt.
Value
Description
0
The Debug Fault State interrupt is disabled.
1
The Debug Fault State interrupt is enabled.
Bit 10 – UFS Non-Recoverable Update Fault Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which disables the
Non-Recoverable Update Fault interrupt.
Note: This bit is only available on variant L devices. Refer to the Configuration Summary for more information.
Value
0
1
Description
The Non-Recoverable Update Fault interrupt is disabled.
The Non-Recoverable Update Fault interrupt is enabled.
Bit 3 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Compare interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 2 – CNT Counter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter interrupt.
Value
Description
0
The Counter interrupt is disabled.
1
The Counter interrupt is enabled.
Bit 1 – TRG Retrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Retrigger Interrupt Disable/Enable bit, which disables the Retrigger interrupt.
Value
Description
0
The Retrigger interrupt is disabled.
1
The Retrigger interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt
request.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
0
1
Description
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.11 Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x28
0x00000000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
7
6
5
4
3
ERR
R/W
0
2
CNT
R/W
0
1
TRG
R/W
0
0
OVF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19 – MCx Match or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Non-Recoverable Fault x Interrupt Disable/Enable bit, which enables the NonRecoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTB Recoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Writing a '1' to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recoverable
Fault B interrupt.
Value
Description
0
The Recoverable Fault B interrupt is disabled.
1
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTA Recoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the Recoverable
Fault A interrupt.
Value
Description
0
The Recoverable Fault A interrupt is disabled.
1
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFS Non-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault
State interrupt.
Value
Description
0
The Debug Fault State interrupt is disabled.
1
The Debug Fault State interrupt is enabled.
Bit 10 – UFS Non-Recoverable Update Fault Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which enables the
Non-Recoverable Update Fault interrupt.
Note: This bit is only available on variant L devices. Refer to the Configuration Summary for more information.
Value
0
1
Description
The Non-Recoverable Update Fault interrupt is disabled.
The Non-Recoverable Update Fault interrupt is enabled.
Bit 3 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Disable/Enable bit, which enables the Compare interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 2 – CNT Counter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter interrupt.
Value
Description
0
The Counter interrupt is disabled.
1
The Counter interrupt is enabled.
Bit 1 – TRG Retrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt.
Value
Description
0
The Retrigger interrupt is disabled.
1
The Retrigger interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Disable/Enable bit, which enables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
1
Description
The Overflow interrupt is enabled.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.12 Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x2C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
7
6
5
4
3
ERR
R/W
0
2
CNT
R/W
0
1
TRG
R/W
0
0
OVF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19 – MCx Match or Capture Channel x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once CCx register
contain a valid capture value.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In Capture operation, this flag is automatically cleared when CCx register is read.
Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault x occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Non-Recoverable Fault 1 interrupt flag.
Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Flag
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Non-Recoverable Fault 0 interrupt flag.
Bit 13 – FAULTB Recoverable Fault B Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
Bit 12 – FAULTA Recoverable Fault A Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
Bit 11 – DFS Non-Recoverable Debug Fault State Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an Debug Fault State occurs.
Writing a '0' to this bit has no effect.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Writing a '1' to this bit clears the Debug Fault State interrupt flag.
Bit 10 – UFS Non-Recoverable Update Fault
This flag is set when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD).
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Non-Recoverable Update Fault interrupt flag.
Note: This bit is only available on variant L devices. Refer to the Configuration Summary for more information.
Bit 3 – ERR Error Interrupt Flag
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one. In which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the error interrupt flag.
Bit 2 – CNT Counter Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CNT interrupt flag.
Bit 1 – TRG Retrigger Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the re-trigger interrupt flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.13 Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x30
0x00000001
-
31
30
29
28
27
CMP3
R/W
0
26
CMP2
R/W
0
25
CMP1
R/W
0
24
CMP0
R/W
0
23
22
21
20
19
CCBV3
R/W
0
18
CCBV2
R/W
0
17
CCBV1
R/W
0
16
CCBV0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
FAULT1IN
R
0
10
FAULT0IN
R
0
9
FAULTBIN
R
0
8
FAULTAIN
R
0
7
PERBV
R/W
0
6
WAVEBV
R/W
0
5
PATTBV
R/W
0
4
3
DFS
R/W
0
2
UFS
R/W
0
1
IDX
R
0
0
STOP
R
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 24, 25, 26, 27 – CMPx Channel x Compare Value
This bit reflects the channel x output compare value.
Value
Description
0
Channel compare output value is 0.
1
Channel compare output value is 1.
Bits 16, 17, 18, 19 – CCBVx Channel x Compare or Capture Buffer Valid
For a compare channel, this bit is set when a new value is written to the corresponding CCBx register. The bit
is cleared either by writing a '1' to the corresponding location when CTRLB.LUPD is set, or automatically on an
UPDATE condition.
For a capture channel, the bit is set when a valid capture value is stored in the CCBx register. The bit is automatically
cleared when the CCx register is read.
Bits 14, 15 – FAULTx Non-recoverable Fault x State
This bit is set by hardware as soon as non-recoverable Fault x condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULTxIN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from
BOTTOM, the timer/counter restart command must be executed before clearing the corresponding STATEx bit. For
further details on timer/counter commands, refer to available commands description (31.8.3 CTRLBSET.CMD).
Bit 13 – FAULTB Recoverable Fault B State
This bit is set by hardware as soon as recoverable Fault B condition occurs.
This bit can be clear by hardware when Fault B action is resumed, or by writing a '1' to this bit when the
corresponding FAULTBIN bit is low. If software halt command is enabled (FAULTB.HALT=SW), clearing this bit will
release the timer/counter.
Bit 12 – FAULTA Recoverable Fault A State
This bit is set by hardware as soon as recoverable Fault A condition occurs.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
This bit can be clear by hardware when Fault A action is resumed, or by writing a '1' to this bit when the
corresponding FAULTAIN bit is low. If software halt command is enabled (FAULTA.HALT=SW), clearing this bit will
release the timer/counter.
Bit 11 – FAULT1IN Non-Recoverable Fault 1 Input
This bit is set while an active Non-Recoverable Fault 1 input is present.
Bit 10 – FAULT0IN Non-Recoverable Fault 0 Input
This bit is set while an active Non-Recoverable Fault 0 input is present.
Bit 9 – FAULTBIN Recoverable Fault B Input
This bit is set while an active Recoverable Fault B input is present.
Bit 8 – FAULTAIN Recoverable Fault A Input
This bit is set while an active Recoverable Fault A input is present.
Bit 7 – PERBV Period Buffer Valid
This bit is set when a new value is written to the PERB register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 6 – WAVEBV Waveform Control Buffer Valid
This bit is set when a new value is written to the WAVEB register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 5 – PATTBV Pattern Generator Value Buffer Valid
This bit is set when a new value is written to the PATTB register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 3 – DFS Debug Fault State
This bit is set by hardware in Debug mode when DDBGCTRL.FDDBD bit is set. The bit is cleared by writing a '1' to
this bit and when the TCC is not in Debug mode.
When the bit is set, the counter is halted and the Waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV
registers.
Bit 2 – UFS Non-recoverable Update Fault State
This bit is set by hardware when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD). The bit
is cleared by writing a one to this bit.
When the bit is set, the waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV registers.
Bit 1 – IDX Ramp Index
In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1
operation, the bit always reads zero. For details on ramp operations, refer to 31.6.3.4 Ramp Operations.
Bit 0 – STOP Stop
This bit is set when the TCC is disabled either on a STOP command or on an UPDATE condition when One-Shot
operation mode is enabled (CTRLBSET.ONESHOT=1).
This bit is clear on the next incoming counter increment or decrement.
Value
Description
0
Counter is running.
1
Counter is stopped.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.14 Counter Value
Name:
Offset:
Reset:
Property:
COUNT
0x34
0x00000000
PAC Write-Protection, Write-Synchronized, Read-Synchronized
Note: Prior to any read access, this register must be synchronized by user by writing the according TCC Command
value to the Control B Set register (CTRLBSET.CMD=READSYNC).
Bit
31
30
29
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
26
25
24
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
20
19
COUNT[23:16]
R/W
R/W
0
0
12
11
COUNT[15:8]
R/W
R/W
0
0
4
3
COUNT[7:0]
R/W
R/W
0
0
Bits 23:0 – COUNT[23:0] Counter Value
These bits hold the value of the counter register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0 (depicted)
23:4
23:5
23:6
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.15 Pattern
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
PATT
0x38
0x0000
Write-Synchronized
15
PGV7
R/W
0
14
PGV6
R/W
0
13
PGV5
R/W
0
12
PGV4
R/W
0
11
PGV3
R/W
0
10
PGV2
R/W
0
9
PGV1
R/W
0
8
PGV0
R/W
0
7
PGE7
R/W
0
6
PGE6
R/W
0
5
PGE5
R/W
0
4
PGE4
R/W
0
3
PGE3
R/W
0
2
PGE2
R/W
0
1
PGE1
R/W
0
0
PGE0
R/W
0
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGV Pattern Generation Output Value
This register holds the values of pattern for each waveform output.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGE Pattern Generation Output Enable
This register holds the enable status of pattern generation for each waveform output. A bit written to '1' will override
the corresponding SWAP output with the corresponding PGVn value.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.16 Waveform
Name:
Offset:
Reset:
Property:
Bit
WAVE
0x3C
0x00000000
Write-Synchronized
31
30
29
28
27
SWAP3
R/W
0
26
SWAP2
R/W
0
25
SWAP1
R/W
0
24
SWAP0
R/W
0
23
22
21
20
19
POL3
R/W
0
18
POL2
R/W
0
17
POL1
R/W
0
16
POL0
R/W
0
15
14
13
12
11
CICCEN3
R/W
0
10
CICCEN2
R/W
0
9
CICCEN1
R/W
0
8
CICCEN0
R/W
0
7
CIPEREN
R/W
0
6
5
4
3
2
1
WAVEGEN[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
RAMP[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
Bits 24, 25, 26, 27 – SWAP Swap DTI Output Pair x
Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not
affect the swap operation.
Bits 16, 17, 18, 19 – POL Channel Polarity x
Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.
Value
Name
Description
0
(single-slope PWM waveform
Compare output is initialized to ~DIR and set to DIR when TCC
generation)
counter matches CCx value
1
(single-slope PWM waveform
Compare output is initialized to DIR and set to ~DIR when TCC
generation)
counter matches CCx value.
0
(dual-slope PWM waveform
Compare output is set to ~DIR when TCC counter matches CCx
generation)
value
1
(dual-slope PWM waveform
Compare output is set to DIR when TCC counter matches CCx
generation)
value.
Bits 8, 9, 10, 11 – CICCEN Circular CC Enable x
Setting this bits enables the compare circular buffer option on channel. When the bit is set, CCx register value is
copied-back into the CCx register on UPDATE condition.
Bit 7 – CIPEREN Circular Period Enable
Setting this bits enable the period circular buffer option. When the bit is set, the PER register value is copied-back
into the PERB register on UPDATE condition.
Bits 5:4 – RAMP[1:0] Ramp Operation
These bits select Ramp operation (RAMP). These bits are not synchronized.
Value
Name
0x0
RAMP1
0x1
RAMP2A
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Description
RAMP1 operation
Alternative RAMP2 operation
DS40001882H-page 681
SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Value
0x2
0x3
0x4
Name
RAMP2
RAMP2C. This bit is only available in variant L devices. Refer to
Configuration Summary for more information.
-
Description
RAMP2 operation
Critical RAMP2 operation
Reserved
Bits 2:0 – WAVEGEN[2:0] Waveform Generation Operation
These bits select the waveform generation operation. The settings impact the top value and control if frequency or
PWM waveform generation should be used. These bits are not synchronized.
Value
Name
Description
Operation
Top
Update
Waveform Output
On Match
Waveform Output
On Update
OVFIF/Event
Up Down
0x0
NFRQ
Normal Frequency
PER
TOP/Zero
Toggle
Stable
TOP
Zero
0x1
MFRQ
Match Frequency
CC0
TOP/Zero
Toggle
Stable
TOP
Zero
0x2
NPWM
Normal PWM
PER
TOP/Zero
Set
Clear
TOP
Zero
0x3
Reserved
-
-
-
-
-
-
-
0x4
DSCRITICAL
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x5
DSBOTTOM
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x6
DSBOTH
Dual-slope PWM
PER
TOP & Zero
~DIR
Stable
TOP
Zero
0x7
DSTOP
Dual-slope PWM
PER
Zero
~DIR
Stable
TOP
–
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.17 Period Value
Name:
Offset:
Reset:
Property:
Bit
PER
0x40
0xFFFFFFFF
Write-Synchronized
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
11
10
9
8
R/W
1
R/W
1
R/W
1
1
0
R/W
1
R/W
1
Access
Reset
Bit
PER[17:10]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
PER[9:2]
Access
Reset
Bit
R/W
1
7
R/W
1
R/W
1
R/W
1
R/W
1
6
5
4
3
R/W
1
R/W
1
R/W
1
PER[1:0]
Access
Reset
R/W
1
2
DITHER[5:0]
R/W
R/W
1
1
Bits 23:6 – PER[17:0] Period Value
These bits hold the value of the period buffer register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHER[5:0] Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse period every 64 PWM frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.18 Compare/Capture Channel x
Name:
Offset:
Reset:
Property:
CC
0x44 + n*0x04 [n=0..3]
0x00000000
Write-Synchronized, Read-Synchronized
The CCx register represents the 16-, 24- bit value, CCx. The register has two functions, depending of the mode of
operation.
For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
For compare operation, this register is continuously compared to the counter value. Normally, the output form the
comparator is then used for generating waveforms.
CCx register is updated with the buffer value from their corresponding CCBx register when an UPDATE condition
occurs.
In addition, in match frequency operation, the CC0 register controls the counter period.
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Access
Reset
Bit
CC[17:10]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
CC[9:2]
Access
Reset
Bit
R/W
0
7
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
R/W
0
R/W
0
R/W
0
CC[1:0]
Access
Reset
R/W
0
2
DITHER[5:0]
R/W
R/W
0
0
Bits 23:6 – CC[17:0] Channel x Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the m MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHER[5:0] Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM frames.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
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TCC – Timer/Counter for Control Applications
31.8.19 Pattern Buffer
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
PATTB
0x64
0x0000
Write-Synchronized, Read-Synchronized
15
PGVB7
R/W
0
14
PGVB6
R/W
0
13
PGVB5
R/W
0
12
PGVB4
R/W
0
11
PGVB3
R/W
0
10
PGVB2
R/W
0
9
PGVB1
R/W
0
8
PGVB0
R/W
0
7
PGEB7
R/W
0
6
PGEB6
R/W
0
5
PGEB5
R/W
0
4
PGEB4
R/W
0
3
PGEB3
R/W
0
2
PGEB2
R/W
0
1
PGEB1
R/W
0
0
PGEB0
R/W
0
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGVB Pattern Generation Output Value Buffer
This register is the buffer for the PGV register. If double buffering is used, valid content in this register is copied to the
PGV register on an UPDATE condition.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGEB Pattern Generation Output Enable Buffer
This register is the buffer of the PGE register. If double buffering is used, valid content in this register is copied into
the PGE register at an UPDATE condition.
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.20 Waveform Buffer
Name:
Offset:
Reset:
Property:
Bit
WAVEB
0x68
0x00000000
Write-Synchronized, Read-Synchronized
31
30
29
28
27
SWAPB 3
R/W
0
26
SWAPB 2
R/W
0
25
SWAPB 1
R/W
0
24
SWAPB 0
R/W
0
23
22
21
20
19
POLB3
R/W
0
18
POLB2
R/W
0
17
POLB1
R/W
0
16
POLB0
R/W
0
15
14
13
12
11
CICCENB3
R/W
0
10
CICCENB2
R/W
0
9
CICCENB1
R/W
0
8
CICCENB0
R/W
0
7
CIPERENB
R/W
0
6
5
3
2
1
WAVEGENB[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
4
RAMPB[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bits 24, 25, 26, 27 – SWAPB Swap DTI output pair x Buffer
These register bits are the buffer bits for the SWAP register bits. If double buffering is used, valid content in these bits
is copied to the corresponding SWAPx bits on an UPDATE condition.
Bits 16, 17, 18, 19 – POLB Channel Polarity x Buffer
These register bits are the buffer bits for POLx register bits. If double buffering is used, valid content in these bits is
copied to the corresponding POBx bits on an UPDATE condition.
Bits 8, 9, 10, 11 – CICCENB Circular CCx Buffer Enable
These register bits are the buffer bits for CICCENx register bits. If double buffering is used, valid content in these bits
is copied to the corresponding CICCENx bits on a UPDATE condition.
Bit 7 – CIPERENB Circular Period Enable Buffer
This register bit is the buffer bit for CIPEREN register bit. If double buffering is used, valid content in this bit is copied
to the corresponding CIPEREN bit on a UPDATE condition.
Bits 5:4 – RAMPB[1:0] Ramp Operation Buffer
These register bits are the buffer bits for RAMP register bits. If double buffering is used, valid content in these bits is
copied to the corresponding RAMP bits on a UPDATE condition.
Value
Name
Description
0x0
RAMP1
RAMP1 operation
0x1
RAMP2A
Alternative RAMP2 operation
0x2
RAMP2
RAMP2 operation
0x3
RAMP2C. This bit is only available in variant L devices. Refer to
Critical RAMP2 operation
Configuration Summary for more information.
0x4
Reserved
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
Bits 2:0 – WAVEGENB[2:0] Waveform Generation Operation Buffer
These register bits are the buffer bits for WAVEGEN register bits. If double buffering is used, valid content in these
bits is copied to the corresponding WAVEGEN bits on a UPDATE condition.
Value
Name
Description
Operation
Top
Update
Waveform Output
On Match
Waveform Output
On Update
OVFIF/Event
Up Down
0x0
NFRQ
Normal Frequency
PER
TOP/Zero
Toggle
Stable
TOP
Zero
0x1
MFRQ
Match Frequency
CC0
TOP/Zero
Toggle
Stable
TOP
Zero
0x2
NPWM
Normal PWM
PER
TOP/Zero
Set
Clear
TOP
Zero
0x3
Reserved
-
-
-
-
-
-
-
0x4
DSCRITICAL
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x5
DSBOTTOM
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x6
DSBOTH
Dual-slope PWM
PER
TOP & Zero
~DIR
Stable
TOP
Zero
0x7
DSTOP
Dual-slope PWM
PER
Zero
~DIR
Stable
TOP
–
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.21 Period Buffer Value
Name:
Offset:
Reset:
Property:
Bit
PERB
0x6C
0xFFFFFFFF
Write-Synchronized, Read-Synchronized
31
30
29
28
23
22
21
20
R/W
1
R/W
1
R/W
1
15
14
13
27
26
25
24
18
17
16
R/W
1
R/W
1
R/W
1
11
10
9
8
R/W
1
R/W
1
R/W
1
1
0
R/W
1
R/W
1
Access
Reset
Bit
Access
Reset
Bit
19
PERB[17:10]
R/W
R/W
1
1
12
PERB[9:2]
Access
Reset
Bit
R/W
1
7
R/W
1
R/W
1
R/W
1
R/W
1
6
5
4
3
R/W
1
R/W
1
R/W
1
PERB[1:0]
Access
Reset
R/W
1
2
DITHERB[5:0]
R/W
R/W
1
1
Bits 23:6 – PERB[17:0] Period Buffer Value
These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHERB[5:0] Dithering Buffer Cycle Number
These bits represent the PER.DITHER bits buffer. When the double buffering is enabled, the value of this bit field is
copied to the PER.DITHER bits on an UPDATE condition.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
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SAM D21/DA1 Family
TCC – Timer/Counter for Control Applications
31.8.22 Channel x Compare/Capture Buffer Value
Name:
Offset:
Reset:
Property:
CCB
0x70 + n*0x04 [n=0..3]
0x00000000
Write-Synchronized, Read-Synchronized
CCBx is copied into CCx at TCC update time
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Access
Reset
Bit
CCB[17:10]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
CCB[9:2]
Access
Reset
Bit
R/W
0
7
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
R/W
0
R/W
0
R/W
0
CCB[1:0]
Access
Reset
R/W
0
2
DITHERB[5:0]
R/W
R/W
0
0
Bits 23:6 – CCB[17:0] Channel x Compare/Capture Buffer Value
These bits hold the value of the Channel x Compare/Capture Buffer Value register. The register serves as the buffer
for the associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the
corresponding CCBVx status bit.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 5:0 – DITHERB[5:0] Dithering Buffer Cycle Number
These bits represent the CCx.DITHER bits buffer. When the double buffering is enable, DITHERBUF bits value is
copied to the CCx.DITHER bits on an UPDATE condition.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
© 2021 Microchip Technology Inc.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.
USB – Universal Serial Bus
32.1
Overview
The Universal Serial Bus interface (USB) module complies with the Universal Serial Bus (USB) 2.1 specification
supporting both device and embedded host modes.
The USB device mode supports 8 endpoint addresses. All endpoint addresses have one input and one output
endpoint, for a total of 16 endpoints. Each endpoint is fully configurable in any of the four transfer types: control,
interrupt, bulk or isochronous. The USB host mode supports up to 8 pipes. The maximum data payload size is
selectable up to 1023 bytes.
Internal SRAM is used to keep the configuration and data buffer for each endpoint. The memory locations used
for the endpoint configurations and data buffers is fully configurable. The amount of memory allocated is dynamic
according to the number of endpoints in use, and the configuration of these. The USB module has a built-in Direct
Memory Access (DMA) and will read/write data from/to the system RAM when a USB transaction takes place. No
CPU or DMA Controller resources are required.
To maximize throughput, an endpoint can be configured for ping-pong operation. When this is done the input and
output endpoint with the same address are used in the same direction. The CPU or DMA Controller can then
read/write one data buffer while the USB module writes/reads from the other buffer. This gives double buffered
communication.
Multi-packet transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without any software intervention. This reduces the number of interrupts and software intervention
needed for USB transfers.
For low power operation the USB module can put the microcontroller in any sleep mode when the USB bus is idle
and a suspend condition is given. Upon bus resume, the USB module can wake the microcontroller from any sleep
mode.
32.2
Features
•
•
•
•
•
•
•
•
•
Compatible with the USB 2.1 specification
USB Embedded Host and Device mode
Supports full (12Mbit/s) and low (1.5Mbit/s) speed communication
Supports Link Power Management (LPM-L1) protocol
On-chip transceivers with built-in pull-ups and pull-downs
On-Chip USB serial resistors
1kHz SOF clock available on external pin
Device mode
– Supports 8 IN endpoints and 8 OUT endpoints
– No endpoint size limitations
– Built-in DMA with multi-packet and dual bank for all endpoints
– Supports feedback endpoint
– Supports crystal less clock
Host mode
– Supports 8 physical pipes
– No pipe size limitations
– Supports multiplexed virtual pipe on one physical pipe to allow an unlimited USB tree
– Built-in DMA with multi-packet support and dual bank for all pipes
– Supports feedback endpoint
– Supports the USB 2.0 Phase-locked SOFs feature
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.3
USB Block Diagram
Figure 32-1. LS/FS Implementation: USB Block Diagram
USB
SRAM Controller
AHB Client
dedicated bus
APB
device-wide bus
AHB Host
User
Interface
DP
USB interrupts
NVIC
SOF 1kHz
GCLK_USB
GCLK
System clock domain
32.4
DM
USB 2.0
Core
USB clock domain
Signal Description
Pin Name
Pin Description
Type
DM
Data -: Differential Data Line - Port
Input/Output
DP
Data +: Differential Data Line + Port
Input/Output
SOF 1kHZ
SOF Output
Output
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
32.5
Product Dependencies
In order to use this peripheral module, other parts of the system must be configured correctly, as described below.
32.5.1
I/O Lines
The USB pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O Controller to
assign the USB pins to their peripheral functions.
A 1kHz SOF clock is available on an external pin. The user must first configure the I/O Controller to assign the 1kHz
SOF clock to the peripheral function. The SOF clock is available for device and host mode.
32.5.2
Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake
up the device from sleep modes. Events connected to the event system can trigger other operations in the system
without exiting sleep modes.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
Related Links
16. PM – Power Manager
32.5.3
Clocks
The USB bus clock (CLK_USB_AHB) can be enabled and disabled in the Main Clock module, MCLK, and the default
state of CLK_USB_AHB can be found in the Peripheral Clock Masking.
A generic clock (GCLK_USB) is required to clock the USB. This clock must be configured and enabled in the Generic
Clock Controller before using the USB.
This generic clock is asynchronous to the bus clock (CLK_USB_AHB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains.
The USB module requires a GCLK_USB of 48 MHz ± 0.25% clock for low speed and full speed operation. To follow
the USB data rate at 12 Mbit/s in full-speed mode, the CLK_USB_AHB clock should be at minimum 8 MHz.
Clock recovery is achieved by a digital phase-locked loop in the USB module, which complies with the USB jitter
specifications. If crystal-less operation is used in USB device mode, refer to USB Clock Recovery Module.
Related Links
15. GCLK - Generic Clock Controller
16.6.2.6 Peripheral Clock Masking
15.6.6 Synchronization
32.5.4
DMA
The USB has a built-in Direct Memory Access (DMA) and will read/write data to/from the system RAM when a USB
transaction takes place. No CPU or DMA Controller resources are required.
32.5.5
Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral,
the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
32.5.6
Events
Not applicable.
32.5.7
Debug Operation
When the CPU is halted in debug mode the USB peripheral continues normal operation. If the USB peripheral is
configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
32.5.8
Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
•
•
•
Device Interrupt Flag (INTFLAG) register
Endpoint Interrupt Flag (EPINTFLAG) register
Host Interrupt Flag (INTFLAG) register
Pipe Interrupt Flag (PINTFLAG) register
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
Write-protection does not apply for accesses through an external debugger.
32.5.9
Analog Connections
Not applicable.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.5.10 Calibration
The output drivers for the DP/DM USB line interface can be fine tuned with calibration values from production
tests. The calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration
register (PADCAL) by software, before enabling the USB, to achieve the specified accuracy. Refer to NVM Software
Calibration Area Mapping for further details.
For additional information on Pad Calibration, refer to the Pad Calibration (PADCAL) register.
Related Links
10.3.2 NVM Software Calibration Area Mapping
32.6
Functional Description
32.6.1
USB General Operation
32.6.1.1 Initialization
After a hardware reset, the USB is disabled. The user should first enable the USB (CTRLA.ENABLE) in either device
mode or host mode (CTRLA.MODE).
Figure 32-2. General States
HW RESET | CTRLA.SWRST
Any state
Idle
CTRLA.ENABLE = 1
CTRLA.MODE
=0
CTRLA.ENABLE = 0
CTRLA.ENABLE = 1
CTRLA.MODE
=1
CTRLA.ENABLE = 0
Device
Host
After a hardware reset, the USB is in the idle state. In this state:
•
•
•
•
The module is disabled. The USB Enable bit in the Control A register (CTRLA.ENABLE) is reset.
The module clock is stopped in order to minimize power consumption.
The USB pad is in suspend mode.
The internal states and registers of the device and host are reset.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Before using the USB, the Pad Calibration register (PADCAL) must be loaded with production calibration values from
the NVM Software Calibration Area.
The USB is enabled by writing a '1' to CTRLA.ENABLE. The USB is disabled by writing a '0' to CTRLA.ENABLE.
The USB is reset by writing a '1' to the Software Reset bit in CTRLA (CTRLA.SWRST). All registers in the USB will
be reset to their initial state, and the USB will be disabled. Refer to the CTRLA register for details.
The user can configure pads and speed before enabling the USB by writing to the Operating Mode bit in the Control
A register (CTRLA.MODE) and the Speed Configuration field in the Control B register (CTRLB.SPDCONF). These
values are taken into account once the USB has been enabled by writing a '1' to CTRLA.ENABLE.
After writing a '1' to CTRLA.ENABLE, the USB enters device mode or host mode (according to CTRLA.MODE).
The USB can be disabled at any time by writing a '0' to CTRLA.ENABLE.
Refer to 32.6.2 USB Device Operations for the basic operation of the device mode.
Refer to 32.6.3 Host Operations for the basic operation of the host mode.
Related Links
10.3.2 NVM Software Calibration Area Mapping
32.6.2
USB Device Operations
This section gives an overview of the USB module device operation during normal transactions. For more details on
general USB and USB protocol, refer to the Universal Serial Bus specification revision 2.1.
32.6.2.1 Initialization
To attach the USB device to start the USB communications from the USB host, a zero should be written to the Detach
bit in the Device Control B register (CTRLB.DETACH). To detach the device from the USB host, a one must be
written to the CTRLB.DETACH.
After the device is attached, the host will request the USB device descriptor using the default device address zero.
On successful transmission, it will send a USB reset. After that, it sends an address to be configured for the device.
All further transactions will be directed to this device address. This address should be configured in the Device
Address field in the Device Address register (DADD.DADD) and the Address Enable bit in DADD (DADD.ADDEN)
should be written to one to accept communications directed to this address. DADD.ADDEN is automatically cleared
on receiving a USB reset.
32.6.2.2 Endpoint Configuration
Endpoint data can be placed anywhere in the device RAM. The USB controller accesses these endpoints directly
through the AHB host (built-in DMA) with the help of the endpoint descriptors. The base address of the endpoint
descriptors needs to be written in the Descriptor Address register (DESCADD) by the user. For additional information,
refer to Endpoint Description Structure.
Before using an endpoint, the user should configure the direction and type of the endpoint in Type of Endpoint field
in the Device Endpoint Configuration register (EPCFG.EPTYPE0/1). The endpoint descriptor registers should be
initialized to known values before using the endpoint, so that the USB controller does not read random values from
the RAM.
The Endpoint Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported
to the host for that endpoint. The Address of Data Buffer register (ADDR) should be set to the data buffer used for
endpoint transfers.
The RAM Access Interrupt bit in Device Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access
underflow error occurs during IN data stage.
When an endpoint is disabled, the following registers are cleared for that endpoint:
•
•
•
•
Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
Device Endpoint Interrupt Flag (EPINTFLAG) register
Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.6.2.3 Multi-Packet Transfers
Multi-packet transfer enables a data payload exceeding the endpoint maximum transfer size to be transferred as
multiple packets without software intervention. This reduces the number of interrupts and software intervention
required to manage higher level USB transfers. Multi-packet transfer is identical to the IN and OUT transactions
described below unless otherwise noted in this section.
The application software provides the size and address of the RAM buffer to be proceeded by the USB module for
a specific endpoint, and the USB module will split the buffer in the required USB data transfers without any software
intervention.
Figure 32-3. Multi-Packet Feature - Reduction of CPU Overhead
Data Payload
Without Multi-packet support
Transfer Complete Interrupt
&
Data Processing
Maximum Endpoint size
With Multi-packet support
32.6.2.4 USB Reset
The USB bus reset is initiated by a connected host and managed by hardware.
During USB reset the following registers are cleared:
•
•
•
•
•
•
•
•
•
Device Endpoint Configuration (EPCFG) register - except for Endpoint 0
Device Frame Number (FNUM) register
Device Address (DADD) register
Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
Device Endpoint Interrupt Flag (EPINTFLAG) register
Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
Endpoint Interrupt Summary (EPINTSMRY) register
Upstream resume bit in the Control B register (CTRLB.UPRSM)
At the end of the reset process, the End of Reset bit is set in the Interrupt Flag register (INTFLAG.EORST).
32.6.2.5 Start-of-Frame
When a Start-of-Frame (SOF) token is detected, the frame number from the token is stored in the Frame Number
field in the Device Frame Number register (FNUM.FNUM), and the Start-of-Frame interrupt bit in the Device Interrupt
Flag register (INTFLAG.SOF) is set. If there is a CRC or bit-stuff error, the Frame Number Error status flag
(FNUM.FNCERR) in the FNUM register is set.
32.6.2.6 Management of SETUP Transactions
When a SETUP token is detected and the device address of the token packet does not match DADD.DADD, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
When the address matches, the USB module checks if the endpoint is enabled in EPCFG. If the addressed endpoint
is disabled, the packet is discarded and the USB module returns to idle and waits for the next token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed endpoint. If the
EPCFG.EPTYPE0 is not set to control, the USB module returns to idle and waits for the next token packet.
When the EPCFG.EPTYPE0 matches, the USB module then fetches the Data Buffer Address (ADDR) from the
addressed endpoint's descriptor and waits for a DATA0 packet. If a PID error or any other PID than DATA0 is
detected, the USB module returns to idle and waits for the next token packet.
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SAM D21/DA1 Family
USB – Universal Serial Bus
When the data PID matches and if the Received Setup Complete interrupt bit in the Device Endpoint Interrupt
Flag register (EPINTFLAG.RXSTP) is equal to zero, ignoring the Bank 0 Ready bit in the Device Endpoint Status
register (EPSTATUS.BK0RDY), the incoming data is written to the data buffer pointed to by the Data Buffer Address
(ADDR). If the number of received data bytes exceeds the endpoint's maximum data payload size as specified by the
PCKSIZE.SIZE, the remainders of the received data bytes are discarded. The packet will still be checked for bit-stuff
and CRC errors. Software must never report a endpoint size to the host that is greater than the value configured in
PCKSIZE.SIZE. If a bit-stuff or CRC error is detected in the packet, the USB module returns to idle and waits for the
next token packet.
If data is successfully received, an ACK handshake is returned to the host, and the number of received data bytes,
excluding the CRC, is written to the Byte Count (PCKSIZE.BYTE_COUNT). If the number of received data bytes is
the maximum data payload specified by PCKSIZE.SIZE, no CRC data is written to the data buffer. If the number
of received data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC
data is written to the data buffer. If the number of received data is equal or less than the data payload specified by
PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
Finally the EPSTATUS is updated. Data Toggle OUT bit (EPSTATUS.DTGLOUT), the Data Toggle IN bit
(EPSTATUS.DTGLIN), the current bank bit (EPSTATUS.CURRBK) and the Bank Ready 0 bit (EPSTATUS.BK0RDY)
are set. Bank Ready 1 bit (EPSTATUS.BK1RDY) and the Stall Bank 0/1 bit (EPSTATUS.STALLQR0/1) are cleared on
receiving the SETUP request. The RXSTP bit is set and triggers an interrupt if the Received Setup Interrupt Enable
bit is set in Endpoint Interrupt Enable Set/Clear register (EPINTENSET/CLR.RXSTP).
32.6.2.7 Management of OUT Transactions
Figure 32-4. OUT Transfer: Data Packet Host to USB Device
Memory Map
HOST
I/O Register
USB I/O Registers
BULK OUT
EPT 2
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
BULK OUT
EPT 3
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
BULK OUT
EPT 1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
Internal RAM
USB Module
USB Endpoints
Descriptor Table
D
A
T
A
0
DESCADD
ENDPOINT 1 DATA
ENDPOINT 3 DATA
DP
DM
USB Buffers
time
ENDPOINT 2 DATA
When an OUT token is detected, and the device address of the token packet does not match DADD.DADD, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
If the address matches, the USB module checks if the endpoint number received is enabled in the EPCFG of the
addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to
idle and waits for the next token packet.
When the endpoint is enabled, the USB module then checks the Endpoint Configuration register (EPCFG) of the
addressed output endpoint. If the type of the endpoint (EPCFG.EPTYPE0) is not set to OUT, the USB module returns
to idle and waits for the next token packet.
The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor, and waits
for a DATA0 or DATA1 packet. If a PID error or any other PID than DATA0 or DATA1 is detected, the USB module
returns to idle and waits for the next token packet.
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SAM D21/DA1 Family
USB – Universal Serial Bus
If EPSTATUS.STALLRQ0 in EPSTATUS is set, the incoming data is discarded. If the endpoint is not isochronous,
a STALL handshake is returned to the host and the Transmit Stall Bank 0 interrupt bit in EPINTFLAG
(EPINTFLAG.STALL0) is set.
For isochronous endpoints, data from both a DATA0 and DATA1 packet will be accepted. For other endpoint types
the PID is checked against EPSTATUS.DTGLOUT. If a PID mismatch occurs, the incoming data is discarded, and an
ACK handshake is returned to the host.
If EPSTATUS.BK0RDY is set, the incoming data is discarded, the bit Transmit Fail 0 interrupt bit in EPINTFLAG
(EPINTFLAG.TRFAIL0) and the status bit STATUS_BK.ERRORFLOW are set. If the endpoint is not isochronous, a
NAK handshake is returned to the host.
The incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR). If the number of
received data bytes exceeds the maximum data payload specified as PCKSIZE.SIZE, the remainders of the received
data bytes are discarded. The packet will still be checked for bit-stuff and CRC errors. If a bit-stuff or CRC error is
detected in the packet, the USB module returns to idle and waits for the next token packet.
If the endpoint is isochronous and a bit-stuff or CRC error in the incoming data, the number of received data bytes,
excluding CRC, is written to PCKSIZE.BYTE_COUNT. Finally the EPINTFLAG.TRFAIL0 and CRC Error bit in the
Device Bank Status register (STATUS_BK.CRCERR) is set for the addressed endpoint.
If data was successfully received, an ACK handshake is returned to the host if the endpoint is not isochronous, and
the number of received data bytes, excluding CRC, is written to PCKSIZE.BYTE_COUNT. If the number of received
data bytes is the maximum data payload specified by PCKSIZE.SIZE no CRC data bytes are written to the data
buffer. If the number of received data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one,
only the first CRC data byte is written to the data buffer If the number of received data is equal or less than the data
payload specified by PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
Finally in EPSTATUS for the addressed output endpoint, EPSTATUS.BK0RDY is set and EPSTATUS.DTGLOUT
is toggled if the endpoint is not isochronous. The flag Transmit Complete 0 interrupt bit in EPINTFLAG
(EPINTFLAG.TRCPT0) is set for the addressed endpoint.
32.6.2.8 Multi-Packet Transfers for OUT Endpoint
The number of data bytes received is stored in endpoint PCKSIZE.BYTE_COUNT as for normal operation. Since
PCKSIZE.BYTE_COUNT is updated after each transaction, it must be set to zero when setting up a new transfer.
The total number of bytes to be received must be written to PCKSIZE.MULTI_PACKET_SIZE. This value must be
a multiple of PCKSIZE.SIZE, otherwise excess data may be written to SRAM locations used by other parts of the
application.
EPSTATUS.DTGLOUT management for non-isochronous packets and EPINTFLAG.BK1RDY/BK0RDY management
are as for normal operation.
If a maximum payload size packet is received, PCKSIZE.BYTE_COUNT will be incremented by PCKSIZE.SIZE
after the transaction has completed, and EPSTATUS.DTGLOUT will be toggled if the endpoint is not isochronous.
If the updated PCKSIZE.BYTE_COUNT is equal to PCKSIZE.MULTI_PACKET_SIZE (i.e. the last transaction),
EPSTATUS.BK1RDY/BK0RDY, and EPINTFLAG.TRCPT0/TRCPT1 will be set.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.6.2.9 Management of IN Transactions
Figure 32-5. IN Transfer: Data Packet USB Device to Host After Request from Host
Memory Map
I/O Register
HOST
CPU
USB I/O Registers
Internal RAM
EPT 2
D
A
T
A
0
D
A
T
A
1
EPT 3
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
USB Module
EPT 1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
DP
DM
ENDPOINT 2 DATA
DESCADD
USB Endpoints
Descriptor Table
D
A
T
A
0
ENDPOINT 3 DATA
USB Buffers
EPT 2
I
N
T
O
K
E
N
I
N
EPT 3 T
O
K
E
N
I
N
EPT 1 T
O
K
E
N
ENDPOINT 1 DATA
time
When an IN token is detected, and if the device address of the token packet does not match DADD.DADD, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
When the address matches, the USB module checks if the endpoint received is enabled in the EPCFG of the
addressed endpoint and if not, the packet is discarded and the USB module returns to idle and waits for the next
token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed input endpoint. If the
EPCFG.EPTYPE1 is not set to IN, the USB module returns to idle and waits for the next token packet.
If EPSTATUS.STALLRQ1 in EPSTATUS is set, and the endpoint is not isochronous, a STALL handshake is returned
to the host and EPINTFLAG.STALL1 is set.
If EPSTATUS.BK1RDY is cleared, the flag EPINTFLAG.TRFAIL1 is set. If the endpoint is not isochronous, a NAK
handshake is returned to the host.
The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor. The data
pointed to by the Data Buffer Address (ADDR) is sent to the host in a DATA0 packet if the endpoint is isochronous.
For non-isochronous endpoints a DATA0 or DATA1 packet is sent depending on the state of EPSTATUS.DTGLIN.
When the number of data bytes specified in endpoint PCKSIZE.BYTE_COUNT is sent, the CRC is appended and
sent to the host.
For isochronous endpoints, EPSTATUS.BK1RDY is cleared and EPINTFLAG.TRCPT1 is set.
For all non-isochronous endpoints the USB module waits for an ACK handshake from the host. If an ACK
handshake is not received within 16 bit times, the USB module returns to idle and waits for the next token packet.
If an ACK handshake is successfully received EPSTATUS.BK1RDY is cleared, EPINTFLAG.TRCPT1 is set and
EPSTATUS.DTGLIN is toggled.
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USB – Universal Serial Bus
32.6.2.10 Multi-Packet Transfers for IN Endpoint
The total number of data bytes to be sent is written to PCKSIZE.BYTE_COUNT as for normal operation. The
Multi-packet size register (PCKSIZE.MULTI_PACKET_SIZE) is used to store the number of bytes that are sent, and
must be written to zero when setting up a new transfer.
When an IN token is received, PCKSIZE.BYTE_COUNT and PCKSIZE.MULTI_PACKET_SIZE are fetched. If
PCKSIZE.BYTE_COUNT minus PCKSIZE.MULTI_PACKET_SIZE is less than the endpoint PCKSIZE.SIZE, endpoint
BYTE_COUNT minus endpoint PCKSIZE.MULTI_PACKET_SIZE bytes are transmitted, otherwise PCKSIZE.SIZE
number of bytes are transmitted. If endpoint PCKSIZE.BYTE_COUNT is a multiple of PCKSIZE.SIZE, the last packet
sent will be zero-length if the AUTOZLP bit is set.
If a maximum payload size packet was sent (i.e. not the last transaction), MULTI_PACKET_SIZE will be incremented
by the PCKSIZE.SIZE. If the endpoint is not isochronous the EPSTATUS.DTLGIN bit will be toggled when
the transaction has completed. If a short packet was sent (i.e. the last transaction), MULTI_PACKET_SIZE is
incremented by the data payload. EPSTATUS.BK0/1RDY will be cleared and EPINTFLAG.TRCPT0/1 will be set.
32.6.2.11 Ping-Pong Operation
When an endpoint is configured for ping-pong operation, it uses both the input and output data buffers (banks)
for a given endpoint in a single direction. The direction is selected by enabling one of the IN or OUT direction in
EPCFG.EPTYPE0/1 and configuring the opposite direction in EPCFG.EPTYPE1/0 as Dual Bank.
When ping-pong operation is enabled for an endpoint, the endpoint in the opposite direction must be configured as
dual bank. The data buffer, data address pointer and byte counter from the enabled endpoint are used as Bank 0,
while the matching registers from the disabled endpoint are used as Bank 1.
Figure 32-6. Ping-Pong Overview
Endpoint
single bank
Without Ping Pong
t
Endpoint
dual bank
Bank0
With Ping Pong
t
Bank1
USB data packet
Available time for data processing by CPU
to avoid NACK
The Bank Select flag in EPSTATUS.CURBK indicates which bank data will be used in the next transaction, and
is updated after each transaction. According to EPSTATUS.CURBK, EPINTFLAG.TRCPT0 or EPINTFLAG.TRFAIL0
or EPINTFLAG.TRCPT1 or EPINTFLAG.TRFAIL1 in EPINTFLAG and Data Buffer 0/1 ready (EPSTATUS.BK0RDY
and EPSTATUS.BK1RDY) are set. The EPSTATUS.DTGLOUT and EPSTATUS.DTGLIN are updated for the enabled
endpoint direction only.
32.6.2.12 Feedback Operation
Feedback endpoints are endpoints with same the address but in different directions. This is usually used in explicit
feedback mechanism in USB Audio, where a feedback endpoint is associated to one or more isochronous data
endpoints to which it provides feedback service. The feedback endpoint always has the opposite direction from the
data endpoint.
The feedback endpoint always has the opposite direction from the data endpoint(s). The feedback endpoint has the
same endpoint number as the first (lower) data endpoint. A feedback endpoint can be created by configuring an
endpoint with different endpoint size (PCKSIZE.SIZE) and different endpoint type (EPCFG.EPTYPE0/1) for the IN
and OUT direction.
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USB – Universal Serial Bus
Example Configuration for Feedback Operation:
• Endpoint n / IN: EPCFG.EPTYPE1 = Interrupt IN, PCKSIZE.SIZE = 64.
• Endpoint n / OUT: EPCFG.EPTYPE0= Isochronous OUT, PCKSIZE.SIZE = 512.
32.6.2.13 Suspend State and Pad Behavior
The following figure, Pad Behavior, illustrates the behavior of the USB pad in Device mode.
Figure 32-7. Pad Behavior
Idle
CTRLA.ENABLE = 1
|
CTRLB.DETACH = 0
| INTFLAG.SUSPEND = 0
CTRLA.ENABLE = 0
|
CTRLB.DETACH = 1
| INTFLAG.SUSPEND = 1
Active
In Idle state, the pad is in Low Power Consumption mode.
In Active state, the pad is active.
The following figure, Pad Events, illustrates the pad events leading to a PAD state change.
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USB – Universal Serial Bus
Figure 32-8. Pad Events
Suspend detected
Cleared on Wakeup
Wakeup detected
Active
Cleared by software to acknowledge the interrupt
Idle
Active
The Suspend Interrupt bit in the Device Interrupt Flag register (INTFLAG.SUSPEND) is set when a USB Suspend
state has been detected on the USB bus. The USB pad is then automatically put in the Idle state. The detection of a
non-idle state sets the Wake Up Interrupt bit (INTFLAG.WAKEUP) and wakes the USB pad.
The pad goes to the Idle state if the USB module is disabled or if CTRLB.DETACH is written to one. It returns to the
Active state when CTRLA.ENABLE is written to one and CTRLB.DETACH is written to zero.
32.6.2.14 Remote Wakeup
The remote wakeup request (also known as upstream resume) is the only request the device may send on its own
initiative. This should be preceded by a DEVICE_REMOTE_WAKEUP request from the host.
First, the USB must have detected a “Suspend” state on the bus, i.e. the remote wakeup request can only be sent
after INTFLAG.SUSPEND has been set.
The user may then write a one to the Remote Wakeup bit (CTRLB.UPRSM) to send an Upstream Resume to the host
initiating the wakeup. This will automatically be done by the controller after 5 ms of inactivity on the USB bus.
When the controller sends the Upstream Resume INTFLAG.WAKEUP is set and INTFLAG.SUSPEND is cleared.
The CTRLB.UPRSM is cleared at the end of the transmitting Upstream Resume.
In case of a rebroadcast resume initiated by the host, the End of Resume bit (INTFLAG.EORSM) flag is set when the
rebroadcast resume is completed.
In the case where the CTRLB.UPRSM bit is set while a host initiated downstream resume is already started, the
CTRLB.UPRSM is cleared and the upstream resume request is ignored.
32.6.2.15 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device
The LPM Handshake bit in CTRLB.LPMHDSK should be configured to accept the LPM transaction.
When a LPM transaction is received on any enabled endpoint n and a handshake has been sent in response
by the controller according to CTRLB.LPMHDSK, the Device Link Power Manager (EXTREG) register is updated
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USB – Universal Serial Bus
in the bank 0 of the addressed endpoint's descriptor. It contains information such as the Best Effort Service
Latency (BESL), the Remote Wake bit (bRemoteWake), and the Link State parameter (bLinkState). Usually, the
LPM transaction uses only the endpoint number 0.
If the LPM transaction was positively acknowledged (ACK handshake), USB sets the Link Power Management
Interrupt bit (INTFLAG.LPMSUSP) bit which indicates that the USB transceiver is suspended, reducing power
consumption. This suspend occurs 9 microseconds after the LPM transaction according to the specification.
To further reduce consumption, it is recommended to stop the USB clock while the device is suspended.
The MCU can also enter in one of the available sleep modes if the wakeup time latency of the selected sleep mode
complies with the host latency constraint, refer to the BESL parameter in EXTREG register.
Recovering from this LPM-L1 suspend state is exactly the same as the Suspend state (see Section
32.6.2.13 Suspend State and Pad Behavior) except that the remote wakeup duration initiated by USB is shorter
to comply with the Link Power Management specification.
If the LPM transaction is responded with a NYET, the Link Power Management Not Yet Interrupt Flag
(INTFLAG.LPMNYET) is set. This generates an interrupt if the Link Power Management Not Yet Interrupt Enable
bit (INTENCLR/SET.LPMNYET) is set.
If the LPM transaction is responded with a STALL or no handshake, no flag is set, and the transaction is ignored.
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USB – Universal Serial Bus
32.6.2.16 USB Device Interrupt
Figure 32-9. Device Interrupt
EPINTFLAG7.STALL
EPINTENSET7.STALL0/STALL1
EPINTFLAG7.TRFAIL1
EPINTENSET7.TRFAIL1
EPINTFLAG7.TRFAIL0
EPINTENSET7.TRFAIL0
ENDPOINT7
EPINTFLAG7.RXSTP
EPINTSMRY
EPINT7
EPINTENSET7.RXSTP
EPINT6
EPINTFLAG7.TRCPT1
EPINTENSET7.TRCPT1
EPINTFLAG7.TRCPT0
EPINTENSET7.TRCPT0
USB EndPoint
Interrupt
EPINTFLAG0.STALL
EPINTENSET0.STALL0/STALL1
EPINTFLAG0.TRFAIL1
EPINTENSET0.TRFAIL1
EPINTFLAG0.TRFAIL0
EPINTENSET0.TRFAIL0
EPINTFLAG0.RXSTP
ENDPOINT0
EPINT1
EPINT0
EPINTENSET0.RXSTP
EPINTFLAG0.TRCPT1
EPINTENSET0.TRCPT1
EPINTFLAG0.TRCPT0
USB
Interrupt
EPINTENSET0.TRCPT0
INTFLAG.LPMSUSP
INTENSET.LPMSUSP
INTFLAG.LPMNYET
INTENSET.DDISC
INTFLAG.RAMACER
INTENSET.RAMACER
INTFLAG.UPRSM
INTFLAG
INTENSET.UPRSM
INTFLAG.EORSM
USB Device Interrupt
INTENSET.EORSM
INTFLAG.WAKEUP
*
INTENSET.WAKEUP
INTFLAG.EORST
INTENSET.EORST
INTFLAG.SOF
INTENSET.SOF
INTFLAGA.MSOF
INTENSET.MSOF
INTFLAG.SUSPEND
INTENSET.SUSPEND
* Asynchronous interrupt
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
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USB – Universal Serial Bus
32.6.3
Host Operations
This section gives an overview of the USB module Host operation during normal transactions. For more details on
general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1.
32.6.3.1 Device Detection and Disconnection
Prior to device detection the software must set the VBUS is OK bit (CTRLB.VBUSOK) register when the VBUS is
available. This notifies the USB host that USB operations can be started. When the bit CTRLB.VBUSOK is zero and
even if the USB HOST is configured and enabled, host operation is halted. Setting the bit CTRLB.VBUSOK will allow
host operation when the USB is configured.
The Device detection is managed by the software using the Line State field in the Host Status (STATUS.LINESTATE)
register. The device connection is detected by the host controller when DP or DM is pulled high, depending of the
speed of the device.
The device disconnection is detected by the host controller when both DP and DM are pulled down using the
STATUS.LINESTATE registers.
The Device Connection Interrupt bit (INTFLAG.DCONN) is set if a device connection is detected.
The Device Disconnection Interrupt bit (INTFLAG.DDISC) is set if a device disconnection is detected.
32.6.3.2 Host Terminology
In host mode, the term pipe is used instead of endpoint. A host pipe corresponds to a device endpoint, refer to
"Universal Serial Bus Specification revision 2.1." for more information.
32.6.3.3 USB Reset
The USB sends a USB reset signal when the user writes a one to the USB Reset bit (CTRLB.BUSRESET). When the
USB reset has been sent, the USB Reset Sent Interrupt bit in the INTFLAG (INTFLAG.RST) is set and all pipes will
be disabled.
If the bus was previously in a suspended state (i.e., the Start of Frame Generation Enable bit (CTRLB.SOFE) is
zero), the USB will switch it to the Resume state, causing the bus to asynchronously set the Host Wakeup Interrupt
flag (INTFLAG.WAKEUP). The CTRLB.SOFE bit will be set in order to generate SOFs immediately after the USB
reset.
During USB reset the following registers are cleared:
•
•
•
•
•
•
•
All Host Pipe Configuration register (PCFG)
Host Frame Number register (FNUM)
Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
Host Start-of-Frame Control register (HSOFC)
Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
Pipe Interrupt Flag register (PINTFLAG)
Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
After the reset the user should check the Speed Status field in the Status register (STATUS.SPEED) to find out the
current speed according to the capability of the peripheral.
32.6.3.4 Pipe Configuration
Pipe data can be placed anywhere in the RAM. The USB controller accesses these pipes directly through the AHB
host (built-in DMA) with the help of the pipe descriptors. The base address of the pipe descriptors needs to be written
in the Descriptor Address register (DESCADD) by the user. Refer to Pipe Description Structure.
Before using a pipe, the user should configure the direction and type of the pipe in Type of Pipe field in the Host
Pipe Configuration register (PCFG.PTYPE). The pipe descriptor registers should be initialized to known values before
using the pipe, so that the USB controller does not read the random values from the RAM.
The Pipe Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported by the
device for the endpoint associated with this pipe. The Address of Data Buffer register (ADDR) should be set to the
data buffer used for pipe transfers.
The Pipe Bank bit (PCFG.BK) should be set to one if dual banking is desired. Dual bank is not supported for Control
pipes.
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The Ram Access Interrupt bit in Host Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access
underflow error occurs during an OUT stage.
When a pipe is disabled, the following registers are cleared for that pipe:
•
•
•
•
Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
Pipe Interrupt Flag register (PINTFLAG)
Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
32.6.3.5 Pipe Activation
A disabled pipe is inactive, and will be reset along with its context registers (pipe registers for the pipe n). Pipes are
enabled by writing the Type of the Pipe bit (PCFG.PTYPE) to a value different than 0x0 (disabled).
When a pipe is enabled, the Pipe Freeze bit in the Pipe Status register (PSTATUS.FREEZE) is set. This allows the
user to complete the configuration of the pipe, without starting a USB transfer.
When starting an enumeration, the user retrieves the device descriptor by sending a GET_DESCRIPTOR USB
request. This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0),
which the user should use to reconfigure the size of the default control pipe.
32.6.3.6 Pipe Address Setup
Once the device has answered the first host requests with the default device address 0, the host assigns a new
address to the device. The host controller has to send a USB reset to the device and a SET_ADDRESS(addr)
SETUP request with the new address to be used by the device. Once this SETUP transaction is complete, the user
writes the new address to the Pipe Device Address field in the Host Control Pipe register (CTRL_PIPE.PDADDR) in
Pipe descriptor. All following requests by this pipe will be performed using this new address.
32.6.3.7 Suspend and Wakeup
Setting CTRLB.SOFE to zero when in host mode will cause the USB to cease sending Start-of-Frames on the USB
bus and enter the Suspend state. The USB device will enter the Suspend state 3ms later.
Before entering suspend by writing CTRLB.SOFE to zero, the user must freeze the active pipes by setting their
PSTATUS.FREEZE bit. Any current on-going pipe will complete its transaction, and then all pipes will be inactive. The
user should wait at least 1 complete frame before entering the suspend mode to avoid any data loss.
The device can awaken the host by sending an Upstream Resume (Remote Wakeup feature). When the host detects
a non-idle state on the USB bus, it sets the INTFLAG.WAKEUP. If the non-idle bus state corresponds to an Upstream
Resume (K state), the Upstream Resume Received Interrupt bit in INTFLAG (INTFLAG.UPRSM) is set and the
user must generate a Downstream Resume within 1 ms and for at least 20 ms. It is required to first write a one
to the Send USB Resume bit in CTRLB (CTRLB.RESUME) to respond to the upstream resume with a downstream
resume. Alternatively, the host can resume from a suspend state by sending a Downstream Resume on the USB
bus (CTRLB.RESUME set to 1). In both cases, when the downstream resume is completed, the CTRLB.SOFE bit is
automatically set and the host enters again the active state.
32.6.3.8 Phase-locked SOFs
To support the Synchronous Endpoints capability, the period of the emitted Start-of-Frame is maintained while the
USB connection is not in the active state. This does not apply for the disconnected/connected/reset states. It applies
for active/idle/suspend/resume states. The period of Start-of-Frame will be 1ms when the USB connection is in active
state and an integer number of milli-seconds across idle/suspend/resume states.
To ensure the Synchronous Endpoints capability, the GCLK_USB clock must be kept running. If the GCLK_USB is
interrupted, the period of the emitted Start-of-Frame will be erratic.
32.6.3.9 Management of Control Pipes
A control transaction is composed of three stages:
•
•
•
SETUP
Data (IN or OUT)
Status (IN or OUT)
The user has to change the pipe token according to each stage using the Pipe Token field in PCFG
(PCFG.PTOKEN).
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For control pipes only, the token is assigned a specific initial data toggle sequence:
•
•
•
SETUP: Data0
IN: Data1
OUT: Data1
32.6.3.10 Management of IN Pipes
IN packets are sent by the USB device controller upon IN request reception from the host. All the received data from
the device to the host will be stored in the bank provided the bank is empty. The pipe and its descriptor in RAM must
be configured.
The host indicates it is able to receive data from the device by clearing the Bank 0/1 Ready bit in PSTATUS
(PSTATUS.BK0/1RDY), which means that the memory for the bank is available for new USB transfer.
The USB will perform IN requests as long as the pipe is not frozen by the user.
The generation of IN requests starts when the pipe is unfrozen (PSTATUS.PFREEZE is set to zero).
When the current bank is full, the Transmit Complete 0/1 bit in PINTFLAG (PINTFLAG.TRCPT0/1) will be set and
trigger an interrupt if enabled and the PSTATUS.BK0/1RDY bit will be set.
PINTFLAG.TRCPT0/1 must be cleared by software to acknowledge the interrupt. This is done by writing a one to the
PINTFLAG.TRCPT0/1 of the addressed pipe.
The user reads the PCKSIZE.BYTE_COUNT to know how many bytes should be read.
To free the bank the user must read the IN data from the address ADDR in the pipe descriptor and clear the
PKSTATUS.BK0/1RDY bit. When the IN pipe is composed of multiple banks, a successful IN transaction will switch to
the next bank. Another IN request will be performed by the host as long as the PSTATUS.BK0/1RDY bit for that bank
is set. The PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1RDY will be updated accordingly.
The user can follow the current bank looking at Current Bank bit in PSTATUS (PSTATUS.CURBK) and by looking at
Data Toggle for IN pipe bit in PSTATUS (PSTATUS.DTGLIN).
When the pipe is configured as single bank (Pipe Bank bit in PCFG (PCFG.BK) is 0), only PINTFLAG.TRCPT0 and
PSTATUS.BK0 are used. When the pipe is configured as dual bank (PCFG.BK is 1), both PINTFLAG.TRCPT0/1 and
PSTATUS.BK0/1 are used.
32.6.3.11 Management of OUT Pipes
OUT packets are sent by the host. All the data stored in the bank will be sent to the device provided the bank is filled.
The pipe and its descriptor in RAM must be configured.
The host can send data to the device by writing to the data bank 0 in single bank or the data bank 0/1 in dual bank.
The generation of OUT packet starts when the pipe is unfrozen (PSTATUS.PFREEZE is zero).
The user writes the OUT data to the data buffer pointer by ADDR in the pipe descriptor and allows the USB to send
the data by writing a one to the PSTATUS.BK0/1RDY. This will also cause a switch to the next bank if the OUT pipe is
part of a dual bank configuration.
PINTFLAGn.TRCPT0/1 must be cleared before setting PSTATUS.BK0/1RDY to avoid missing an
PINTFLAGn.TRCPT0/1 event.
32.6.3.12 Alternate Pipe
The user has the possibility to run sequentially several logical pipes on the same physical pipe. It allows addressing
of any device endpoint of any attached device on the bus.
Before switching pipe, the user should save the pipe context (Pipe registers and descriptor for pipe n).
After switching pipe, the user should restore the pipe context (Pipe registers and descriptor for pipe n) and in
particular PCFG, and PSTATUS.
32.6.3.13 Data Flow Error
This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets the Transmit
Fail bit in PINTFLAG (PINTFLAG.TRFAIL), which triggers an interrupt if the Transmit Fail bit in PINTENCLR/
SET(PINTENCLR/SET.TRFAIL) is set. The user must check the Pipe Interrupt Summary register (PINTSMRY) to
find out the pipe which triggered the interrupt. Then the user must check the origin of the interrupt’s bank by
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looking at the Pipe Bank Status register (STATUS_BK) for each bank. If the Error Flow bit in the STATUS_BK
(STATUS_BK.ERRORFLOW) is set then the user is able to determine the origin of the data flow error. As the user
knows that the endpoint is an IN or OUT the error flow can be deduced as OUT underflow or as an IN overflow.
An underflow can occur during an OUT stage if the host attempts to send data from an empty bank. If a new
transaction is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
An overflow can occur during an IN stage if the device tries to send a packet while the bank is full. Typically this
occurs when a CPU is not fast enough. The packet data is not written to the bank and is lost. If a new transaction is
successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
32.6.3.14 CRC Error
This error exists only for isochronous IN pipes. It sets the PINTFLAG.TRFAIL, which triggers an interrupt if
PINTENCLR/SET.TRFAIL is set. The user must check the PINTSMRY to find out the pipe which triggered the
interrupt. Then the user must check the origin of the interrupt’s bank by looking at the bank descriptor STATUS_BK
for each bank and if the CRC Error bit in STATUS_BK (STATUS_BK.CRCERR) is set then the user is able to
determine the origin of the CRC error. A CRC error can occur during the IN stage if the USB detects a corrupted
packet. The IN packet will remain stored in the bank and PINTFLAG.TRCPT0/1 will be set.
32.6.3.15 PERR Error
This error exists for all pipes. It sets the PINTFLAG.PERR Interrupt, which triggers an interrupt if PINTFLAG.PERR is
set. The user must check the PINTSMRY register to find out the pipe which can cause an interrupt.
A PERR error occurs if one of the error field in the STATUS_PIPE register in the Host pipe descriptor is set and the
Error Count field in STATUS_PIPE (STATUS_PIPE.ERCNT) exceeds the maximum allowed number of Pipe error(s)
as defined in Pipe Error Max Number field in CTRL_PIPE (CTRL_PIPE.PERMAX). Refer to Host Control Pipe and
Host Status Pipe registers.
If one of the error field in the STATUS_PIPE register from the Host Pipe Descriptor is set and the
STATUS_PIPE.ERCNT is less than the CTRL_PIPE.PERMAX, the STATUS_PIPE.ERCNT is incremented.
32.6.3.16 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host.
An EXTENDED LPM transaction can be transmitted by any enabled pipe. The PCFGn.PTYPE should be set to
EXTENDED. Other fields as PCFG.PTOKEN, PCFG.BK and PCKSIZE.SIZE are irrelevant in this configuration. The
user should also set the EXTREG.VARIABLE in the descriptor as described in the EXTREG Register.
When the pipe is configured and enabled, an EXTENDED TOKEN followed by a LPM TOKEN are transmitted. The
device responds with a valid HANDSHAKE, corrupted HANDSHAKE or no HANDSHAKE (TIME-OUT).
If the valid HANDSHAKE is an ACK, the host will immediately proceed to L1 SLEEP and the PINTFLAG.TRCT0 is
set. The minimum duration of the L1 SLEEP state will be the TL1RetryAndResidency as defined in the reference
document "ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". When entering the L1
SLEEP state, the CTRLB.SOFE is cleared, avoiding Start-of-Frame generation.
If the valid HANDSHAKE is a NYET PINTFLAG.TRFAIL is set.
If the valid HANDSHAKE is a STALL the PINTFLAG.STALL is set.
If there is no HANDSHAKE or corrupted HANDSHAKE, the EXTENDED/LPM pair of TOKENS will be transmitted
again until reaching the maximum number of retries as defined by the CTRL_PIPE.PERMAX in the pipe descriptor.
If the last retry returns no valid HANDSHAKE, the PINTFLAGn.PERR is set, and the STATUS_BK is updated in the
pipe descriptor.
All LPM transactions, should they end up with a ACK, a NYET, a STALL or a PERR, will set the PSTATUS.PFREEZE
bit, freezing the pipe before a succeeding operation. The user should unfreeze the pipe to start a new LPM
transaction.
To exit the L1 STATE, the user initiate a DOWNSTREAM RESUME by setting the bit CTRLB.RESUME or a L1
RESUME by setting the Send L1 Resume bit in CTRLB (CTRLB.L1RESUME). In the case of a L1 RESUME, the K
STATE duration is given by the BESL bit field in the EXTREG.VARIABLE field. Refer to the EXTREG Register.
When the host is in the L1 SLEEP state after a successful LPM transmitted, the device can initiate an UPSTREAM
RESUME. This will set the Upstream Resume Interrupt bit in INTFLAG (INTFLAG.UPRSM). The host should proceed
then to a L1 RESUME as described above.
After resuming from the L1 SLEEP state, the bit CTRLB.SOFE is set, allowing Start-of-Frame generation.
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USB – Universal Serial Bus
32.6.3.17 Host Interrupt
Figure 32-10. Host Interrupt
PINTFLAG7.STALL
PINTENSET.STALL
PINTFLAG7.PERR
PINTENSET.PERR
PINTFLAG7.TRFAIL
PINTENSET.TRFAIL
PIPE7
PINTFLAG7.TXSTP
PINTSMRY
PINT7
PINTENSET.TXSTP
PINT6
PINTFLAG7.TRCPT1
PINTENSET.TRCPT1
PINTFLAG7.TRCPT0
PINTENSET.TRCPT0
USB PIPE
Interrupt
PINTFLAG0.STALL
PINTENSET.STALL
PINTFLAG0.PERR
PINTENSET.PERR
PINTFLAG0.TRFAIL
PINTENSET.TRFAIL
PINTFLAG0.TXSTP
PIPE0
PINT1
PINT0
PINTENSET.TXSTP
PINTFLAG0.TRCPT1
PINTENSET.TRCPT1
PINTFLAG0.TRCPT0
USB
Interrupt
PINTENSET.TRCPT0
INTFLAG.DDISC *
INTENSET.DDISC
INTFLAG.DCONN *
INTENSET.DCONN
INTFLAG.RAMACER
INTFLAGA
INTENSET.RAMACER
INTFLAG.UPRSM
USB Host Interrupt
INTENSET.UPRSM
INTFLAG.DNRSM
INTENSET.DNRSM
INTFLAG.WAKEUP *
INTENSET.WAKEUP
INTFLAG.RST
INTENSET.RST
INTFLAG.HSOF
INTENSET.HSOF
* Asynchronous interrupt
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.7
Communication Device Host Register Summary
Offset
Name
Bit Pos.
7
0x00
0x01
0x02
0x03
0x04
...
0x0C
0x0D
0x0E
...
0x23
CTRLA
Reserved
SYNCBUSY
QOSCTRL
7:0
MODE
5
4
3
7:0
7:0
2
1
0
RUNSTDBY
ENABLE
SWRST
DQOS[1:0]
ENABLE
SWRST
CQOS[1:0]
Reserved
FSMSTATUS
7:0
FSMSTATE[6:0]
Reserved
0x24
DESCADD
0x28
PADCAL
32.8
6
7:0
15:8
23:16
31:24
7:0
15:8
DESCADD[7:0]
DESCADD[15:8]
DESCADD[23:16]
DESCADD[31:24]
TRANSN[1:0]
TRANSP[4:0]
TRIM[2:0]
TRANSN[4:2]
Communication Device Host Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronised
7
MODE
R/W
0
6
5
4
3
2
RUNSTDBY
R/W
0
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 7 – MODE Operating Mode
This bit defines the operating mode of the USB.
Value
Description
0
USB Device mode
1
USB Host mode
Bit 2 – RUNSTDBY Run in Standby Mode
This bit is Enable-Protected.
Value
Description
0
USB clock is stopped in standby mode.
1
USB clock is running in standby mode
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Synchronization status enable bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the
operation is complete.
This bit is Write-Synchronized.
Value
Description
0
The peripheral is disabled or being disabled.
1
The peripheral is enabled or being enabled.
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a '1' to this bit resets all registers in the USB, to their initial state, and the USB will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is Write-Synchronized.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.2
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
7
SYNCBUSY
0x02
0x00
-
6
5
4
3
Access
Reset
2
1
ENABLE
R
0
0
SWRST
R
0
Bit 1 – ENABLE Synchronization Enable status bit
This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.
This bit is set when the synchronization of ENABLE register between clock domains is started.
Bit 0 – SWRST Synchronization Software Reset status bit
This bit is cleared when the synchronization of SWRST register between the clock domains is complete.
This bit is set when the synchronization of SWRST register between clock domains is started.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.3
QOS Control
Name:
Offset:
Reset:
Property:
Bit
QOSCTRL
0x03
0x000x0F
PAC Write-Protection
7
6
5
4
3
2
1
0
DQOS[1:0]
Access
Reset
R/W
0
CQOS[1:0]
R/W
0
R/W
0
R/W
0
Bits 3:2 – DQOS[1:0] Data Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write data operation. Refer to SRAM
Quality of Service.
Bits 1:0 – CQOS[1:0] Configuration Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write configuration operation. Refer to
SRAM Quality of Service.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.4
Finite State Machine Status
Name:
Offset:
Reset:
Property:
Bit
FSMSTATUS
0x0D
0xXXXX
Read only
7
Access
Reset
6
5
4
R
0
R
0
R
0
3
FSMSTATE[6:0]
R
0
2
1
0
R
0
R
0
R
1
Bits 6:0 – FSMSTATE[6:0] Fine State Machine Status
These bits indicate the state of the finite state machine of the USB controller.
Value
Name
Description
0x01
OFF (L3)
Corresponds to the powered-off, disconnected, and disabled state.
0x02
ON (L0)
Corresponds to the Idle and Active states.
0x04
SUSPEND (L2)
0x08
SLEEP (L1)
0x10
DNRESUME
Down Stream Resume.
0x20
UPRESUME
Up Stream Resume.
0x40
RESET
USB lines Reset.
Others
Reserved
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.5
Descriptor Address
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
DESCADD
0x24
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
DESCADD[31:24]
R/W
R/W
0
0
20
19
DESCADD[23:16]
R/W
R/W
0
0
12
11
DESCADD[15:8]
R/W
R/W
0
0
4
3
DESCADD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DESCADD[31:0] Descriptor Address Value
These bits define the base address of the main USB descriptor in RAM. The two least significant bits must be written
to zero.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.8.6
Pad Calibration
Name:
Offset:
Reset:
Property:
PADCAL
0x28
0x0000
PAC Write-Protection
The Pad Calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration
register by software, before enabling the USB, to achieve the specified accuracy.
Refer to NVM Software Calibration Area Mapping for further details.
Refer to for further details.
Bit
15
Access
Reset
Bit
Access
Reset
14
R/W
0
7
6
TRANSN[1:0]
R/W
R/W
0
0
13
TRIM[2:0]
R/W
0
12
11
R/W
0
5
4
3
R/W
0
R/W
0
10
R/W
0
2
TRANSP[4:0]
R/W
0
9
TRANSN[4:2]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
Bits 14:12 – TRIM[2:0] Trim bits for DP/DM
These bits calibrate the matching of rise/fall of DP/DM.
Bits 10:6 – TRANSN[4:0] Trimmable Output Driver Impedance N
These bits calibrate the NMOS output impedance of DP/DM drivers.
Bits 4:0 – TRANSP[4:0] Trimmable Output Driver Impedance P
These bits calibrate the PMOS output impedance of DP/DM drivers.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.9
Device Registers - Common -Register Summary
Offset
Name
0x00
...
0x07
Reserved
0x08
CTRLB
0x0A
0x0B
0x0C
0x0D
...
0x0F
DADD
Reserved
STATUS
7
6
5
4
7:0
15:8
7:0
TSTPCKT
TSTK
TSTJ
NREPLY
7:0
ADDEN
3
2
SPDCONF[1:0]
LPMHDSK[1:0]
DADD[6:0]
LINESTATE[1:0]
1
0
UPRSM
GNAK
DETACH
OPMODE2
SPEED[1:0]
Reserved
0x10
FNUM
0x12
...
0x13
Reserved
0x14
INTENCLR
0x16
...
0x17
Reserved
0x18
INTENSET
0x1A
...
0x1B
Reserved
0x1C
INTFLAG
0x1E
...
0x1F
Reserved
0x20
EPINTSMRY
32.10
Bit Pos.
7:0
15:8
FNUM[4:0]
MFNUM[2:0]
FNCERR
FNUM[10:5]
7:0
15:8
RAMACER
UPRSM
EORSM
WAKEUP
EORST
SOF
MSOF
LPMSUSP
SUSPEND
LPMNYET
7:0
15:8
RAMACER
UPRSM
EORSM
WAKEUP
EORST
SOF
MSOF
LPMSUSP
SUSPEND
LPMNYET
7:0
15:8
RAMACER
UPRSM
EORSM
WAKEUP
EORST
SOF
MSOF
LPMSUSP
SUSPEND
LPMNYET
7:0
15:8
EPINT7
EPINT6
EPINT5
EPINT4
EPINT3
EPINT2
EPINT1
EPINT0
Device Registers - Common
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
© 2021 Microchip Technology Inc.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.1 Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x08
0x0000
PAC Write-Protection
15
14
13
12
11
10
LPMHDSK[1:0]
R/W
R/W
0
0
9
GNAK
R/W
0
8
OPMODE2
R/W
0
7
TSTPCKT
R/W
0
6
TSTK
R/W
0
5
TSTJ
R/W
0
4
NREPLY
R
0
3
2
SPDCONF[1:0]
R/W
R/W
0
0
1
UPRSM
R/W
0
0
DETACH
R/W
0
Access
Reset
Bit
Access
Reset
Bits 11:10 – LPMHDSK[1:0] Link Power Management Handshake
These bits select the Link Power Management Handshake configuration.
Value
Description
0x0
No handshake. LPM is not supported.
0x1
ACK
0x2
NYET
0x3
Reserved
Bit 9 – GNAK Global NAK
This bit configures the operating mode of the NAK.
This bit is not synchronized.
Value
Description
0
The handshake packet reports the status of the USB transaction
1
A NAK handshake is answered for each USB transaction regardless of the current endpoint memory
bank status
Bit 8 – OPMODE2 Specific Operational Mode
Value
Description
0
The UTMI transceiver is in normal operation Mode.
1
The UTMI transceiver is in the “disabled bit stuffing and NRZI encoding” operational mode for test
purpose.
Bit 7 – TSTPCKT Test Packet Mode
Value
Description
0
The UTMI transceiver is in normal operation Mode.
1
The UTMI transceiver generates test packets for test purpose.
Bit 6 – TSTK Test Mode K
Value
Description
0
The UTMI transceiver is in normal operation Mode.
1
The UTMI transceiver generates high speed K state for test purpose.
Bit 5 – TSTJ Test Mode J
Value
Description
0
The UTMI transceiver is in normal operation Mode.
1
The UTMI transceiver generates high speed J state for test purpose.
Bit 4 – NREPLY No reply excepted SETUP Token
This bit is cleared by hardware when receiving a SETUP packet.
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SAM D21/DA1 Family
USB – Universal Serial Bus
This bit has no effect for any other endpoint but endpoint 0.
Value
Description
0
Disable the “NO_REPLY” feature: Any transaction to endpoint 0 will be handled according to the
USB2.0 standard.
1
Enable the “NO_REPLY” feature: Any transaction to endpoint 0 will be ignored except SETUP.
Bits 3:2 – SPDCONF[1:0] Speed Configuration
These bits select the speed configuration.
Value
Description
0x0
FS: Full-speed
0x1
LS: Low-speed
0x2
HS: High-speed capable
0x3
HSTM: High-speed Test Mode (force High-speed mode for test mode)
Bit 1 – UPRSM Upstream Resume
This bit is cleared when the USB receives a USB reset or once the upstream resume has been sent.
Value
Description
0
Writing a zero to this bit has no effect.
1
Writing a one to this bit will generate an upstream resume to the host for a remote wakeup.
Bit 0 – DETACH Detach
Value
Description
0
The device is attached to the USB bus so that communications may occur.
1
It is the default value at reset. The internal device pull-ups are disabled, removing the device from the
USB bus.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.2 Device Address
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
ADDEN
R/W
0
DADD
0x0A
0x00
PAC Write-Protection
6
5
4
R/W
0
R/W
0
R/W
0
3
DADD[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 7 – ADDEN Device Address Enable
This bit is cleared when a USB reset is received.
Value
Description
0
Writing a zero will deactivate the DADD field (USB device address) and return the device to default
address 0.
1
Writing a one will activate the DADD field (USB device address).
Bits 6:0 – DADD[6:0] Device Address
These bits define the device address. The DADD register is reset when a USB reset is received.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.3 Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x0C
0x40
-
7
6
LINESTATE[1:0]
R
R
0
1
Access
Reset
5
4
3
2
1
0
SPEED[1:0]
R/W
0
R/W
1
Bits 7:6 – LINESTATE[1:0] USB Line State Status
These bits define the current line state DP/DM.
LINESTATE[1:0]
USB Line Status
0x0
0x1
0x2
SE0/RESET
FS-J or LS-K State
FS-K or LS-J State
Bits 3:2 – SPEED[1:0] Speed Status
These bits define the current speed used of the device.
SPEED[1:0]
SPEED STATUS
0x0
0x1
0x2
0x3
Full-speed mode
Low-speed mode
High-speed mode
Reserved
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.4 Device Frame Number
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
FNUM
0x10
0x0000
Read only
15
FNCERR
R/W
0
14
7
6
R/W
0
R/W
0
13
12
11
10
FNUM[10:5]
R/W
R/W
0
0
R/W
0
R/W
0
5
FNUM[4:0]
R/W
0
4
3
2
R/W
0
R/W
0
R/W
0
9
8
R/W
0
R/W
0
1
MFNUM[2:0]
R/W
0
0
R/W
0
Bit 15 – FNCERR Frame Number CRC Error
This bit is cleared upon receiving a USB reset.
This bit is set when a corrupted frame number (or micro-frame number) is received.
This bit and the SOF (or MSOF) interrupt bit are updated at the same time.
Bits 13:3 – FNUM[10:0] Frame Number
These bits are cleared upon receiving a USB reset.
These bits are updated with the frame number information as provided from the last SOF packet even if a corrupted
SOF is received.
Bits 2:0 – MFNUM[2:0] Micro Frame Number
These bits are cleared upon receiving a USB reset or at the beginning of each Start-of-Frame (SOF interrupt).
These bits are updated with the micro-frame number information as provided from the last MSOF packet even if a
corrupted MSOF is received.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.5 Device Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x14
0x0000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
15
14
13
12
11
10
9
LPMSUSP
R/W
0
8
LPMNYET
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
EORSM
R/W
0
4
WAKEUP
R/W
0
3
EORST
R/W
0
2
SOF
R/W
0
1
MSOF
R/W
0
0
SUSPEND
R/W
0
Access
Reset
Bit
Access
Reset
Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable the
corresponding interrupt request.
Value
Description
0
The Link Power Management Suspend interrupt is disabled.
1
The Link Power Management Suspend interrupt is enabled and an interrupt request will be generated
when the Link Power Management Suspend interrupt Flag is set.
Bit 8 – LPMNYET Link Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the
corresponding interrupt request.
Value
Description
0
The Link Power Management Not Yet interrupt is disabled.
1
The Link Power Management Not Yet interrupt is enabled and an interrupt request will be generated
when the Link Power Management Not Yet interrupt Flag is set.
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access
interrupt Flag is set.
Bit 6 – UPRSM Upstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Upstream Resume interrupt is disabled.
1
The Upstream Resume interrupt is enabled and an interrupt request will be generated when the
Upstream Resume interrupt Flag is set.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Bit 5 – EORSM End Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The End Of Resume interrupt is disabled.
1
The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of
Resume interrupt Flag is set.
Bit 4 – WAKEUP Wake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Wake Up interrupt is disabled.
1
The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up
interrupt Flag is set.
Bit 3 – EORST End of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The End of Reset interrupt is disabled.
1
The End of Reset interrupt is enabled and an interrupt request will be generated when the End of
Reset interrupt Flag is set.
Bit 2 – SOF Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Start-of-Frame interrupt is disabled.
1
The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Start-ofFrame interrupt Flag is set.
Bit 1 – MSOF Micro Start-of-Frame Interrupt Enable in High Speed Mode
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Micro Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Micro Start-of-Frame interrupt is disabled.
1
The Micro Start-of-Frame interrupt is enabled and an interrupt request will be generated when the
Micro Start-of-Frame Access interrupt Flag is set.
Bit 0 – SUSPEND Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Suspend interrupt is disabled.
1
The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend
interrupt Flag is set.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.6 Device Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x18
0x0000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
15
14
13
12
11
10
9
LPMSUSP
R/W
0
8
LPMNYET
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
EORSM
R/W
0
4
WAKEUP
R/W
0
3
EORST
R/W
0
2
SOF
R/W
0
1
MSOF
R/W
0
0
SUSPEND
R/W
0
Access
Reset
Bit
Access
Reset
Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Suspend Enable bit and enable the corresponding
interrupt request.
Value
Description
0
The Link Power Management Suspend interrupt is disabled.
1
The Link Power Management Suspend interrupt is enabled.
Bit 8 – LPMNYET Link Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Not Yet interrupt bit and enable the corresponding
interrupt request.
Value
Description
0
The Link Power Management Not Yet interrupt is disabled.
1
The Link Power Management Not Yet interrupt is enabled.
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access Enable bit and enable the corresponding interrupt request.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled.
Bit 6 – UPRSM Upstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume Enable bit and enable the corresponding interrupt request.
Value
Description
0
The Upstream Resume interrupt is disabled.
1
The Upstream Resume interrupt is enabled.
Bit 5 – EORSM End Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End Of Resume interrupt Enable bit and enable the corresponding interrupt
request.
Value
Description
0
The End Of Resume interrupt is disabled.
1
The End Of Resume interrupt is enabled.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Bit 4 – WAKEUP Wake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
The Wake Up interrupt is disabled.
1
The Wake Up interrupt is enabled.
Bit 3 – EORST End of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End of Reset interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
The End of Reset interrupt is disabled.
1
The End of Reset interrupt is enabled.
Bit 2 – SOF Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Start-of-Frame interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
The Start-of-Frame interrupt is disabled.
1
The Start-of-Frame interrupt is enabled.
Bit 1 – MSOF Micro Start-of-Frame Interrupt Enable in High Speed Mode
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Micro Start-of-Frame interrupt Enable bit and enable the corresponding interrupt
request.
Value
Description
0
The Micro Start-of-Frame interrupt is disabled.
1
The Micro Start-of-Frame interrupt is enabled
Bit 0 – SUSPEND Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Suspend interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
The Suspend interrupt is disabled.
1
The Suspend interrupt is enabled.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.7 Device Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x01C
0x0000
-
15
14
13
12
11
10
9
LPMSUSP
R/W
0
8
LPMNYET
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
EORSM
R/W
0
4
WAKEUP
R/W
0
3
EORST
R/W
0
2
SOF
R/W
0
1
MSOF
R/W
0
0
SUSPEND
R/W
0
Access
Reset
Bit
Access
Reset
Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledge a Link Power Management Transaction (ACK handshake) and
has entered the Suspended state and will generate an interrupt if INTENCLR/SET.LPMSUSP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMSUSP Interrupt Flag.
Bit 8 – LPMNYET Link Power Management Not Yet Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledges a Link Power Management Transaction (handshake is NYET)
and will generate an interrupt if INTENCLR/SET.LPMNYET is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMNYET Interrupt Flag.
Bit 7 – RAMACER RAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a RAM access underflow error occurs during IN data stage. This bit will generate an interrupt if
INTENCLR/SET.RAMACER is one.
Writing a zero to this bit has no effect.
Bit 6 – UPRSM Upstream Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB sends a resume signal called “Upstream Resume” and will generate an interrupt if
INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
Bit 5 – EORSM End Of Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB detects a valid “End of Resume” signal initiated by the host and will generate an
interrupt if INTENCLR/SET.EORSM is one.
Writing a zero to this bit has no effect.
Bit 4 – WAKEUP Wake Up Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB is reactivated by a filtered non-idle signal from the lines and will generate an interrupt if
INTENCLR/SET.WAKEUP is one.
Writing a zero to this bit has no effect.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Bit 3 – EORST End of Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “End of Reset” has been detected and will generate an interrupt if INTENCLR/
SET.EORST is one.
Writing a zero to this bit has no effect.
Bit 2 – SOF Start-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Start-of-Frame” has been detected (every 1 ms) and will generate an interrupt if
INTENCLR/SET.SOF is one.
The FNUM is updated.
Writing a zero to this bit has no effect.
Bit 1 – MSOF Micro Start-of-Frame Interrupt Flag in High Speed Mode
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Micro Start-of-Frame” has been detected (every 125 us) and will generate an interrupt if
INTENCLR/SET.MSOF is one.
The MFNUM register is updated.The FNUM register is unchanged.
Writing a zero to this bit has no effect.
Bit 0 – SUSPEND Suspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Suspend” idle state has been detected for 3 frame periods (J state for 3 ms) and will
generate an interrupt if INTENCLR/SET.SUSPEND is one.
Writing a zero to this bit has no effect.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.10.8 Endpoint Interrupt Summary
Name:
Offset:
Reset:
Property:
Bit
EPINTSMRY
0x20
0x0000
-
15
14
13
12
11
10
9
8
7
EPINT7
R
0
6
EPINT6
R
0
5
EPINT5
R
0
4
EPINT4
R
0
3
EPINT3
R
0
2
EPINT2
R
0
1
EPINT1
R
0
0
EPINT0
R
0
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – EPINT EndPoint Interrupt
The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. Refer to the EPINTFLAGn register in the
Device EndPoint section.
This bit will be cleared when no interrupts are pending for EndPoint n.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.11
Offset
0x00
...
0xFF
0x0100
0x0101
...
0x0103
0x0104
0x0105
0x0106
0x0107
0x0108
0x0109
32.12
Device Endpoint Register Summary
Name
Bit Pos.
7
7:0
NYETDIS
7:0
7:0
7:0
7:0
7:0
7:0
BK1RDY
BK1RDY
BK1RDY
6
5
4
3
2
1
0
Reserved
EPCFGn
EPTYPE1[2:0]
EPTYPE0[2:0]
Reserved
EPSTATUSCLRn
EPSTATUSSETn
EPSTATUSn
EPINTFLAGn
EPINTENCLRn
EPINTENSETn
BK0RDY
BK0RDY
BK0RDY
STALL1
STALL1
STALL1
STALLRQ1
STALLRQ1
STALLRQ1
STALL0
STALL0
STALL0
STALLRQ0
STALLRQ0
STALLRQ0
RXSTP
RXSTP
RXSTP
TRFAIL1
TRFAIL1
TRFAIL1
CURBK
CURBK
CURBK
TRFAIL0
TRFAIL0
TRFAIL0
DTGLIN
DTGLIN
DTGLIN
TRCPT1
TRCPT1
TRCPT1
DTGLOUT
DTGLOUT
DTGLOUT
TRCPT0
TRCPT0
TRCPT0
Device Endpoint Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
© 2021 Microchip Technology Inc.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.1 Device Endpoint Configuration register n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
EPCFGn
0x100
0x00
PAC Write-Protection
7
NYETDIS
R/W
0
6
R/W
0
5
EPTYPE1[2:0]
R/W
0
4
3
R/W
0
2
R/W
0
1
EPTYPE0[2:0]
R/W
0
0
R/W
0
Bit 7 – NYETDIS NYET token disable
Value
Description
0
Disable the “NYETDIS” feature: In high-speed, handshake will be handled according to the USB2.0
standard.
1
Enable the “NYETDIS” feature: An ack handshake will be sent instead of an NYET handshake in
high-speed mode.
Bits 6:4 – EPTYPE1[2:0] Endpoint Type for IN direction
These bits contains the endpoint type for IN direction.
Upon receiving a USB reset EPCFGn.EPTYPE1 is cleared except for endpoint 0 which is unchanged.
Value
Description
0x0
Bank1 is disabled.
0x1
Bank1 is enabled and configured as Control IN.
0x2
Bank1 is enabled and configured as Isochronous IN.
0x3
Bank1 is enabled and configured as Bulk IN.
0x4
Bank1 is enabled and configured as Interrupt IN.
0x5
Bank1 is enabled and configured as Dual-Bank OUT
0x6-0x7
(Endpoint type is the same as the one defined in EPTYPE0)
Reserved
Bits 2:0 – EPTYPE0[2:0] Endpoint Type for OUT direction
These bits contains the endpoint type for OUT direction.
Upon receiving a USB reset EPCFGn.EPTYPE0 is cleared except for endpoint 0 which is unchanged.
Value
Description
0x0
Bank0 is disabled.
0x1
Bank0 is enabled and configured as Control SETUP / Control OUT.
0x2
Bank0 is enabled and configured as Isochronous OUT.
0x3
Bank0 is enabled and configured as Bulk OUT.
0x4
Bank0 is enabled and configured as Interrupt OUT.
0x5
Bank0 is enabled and configured as Dual Bank IN
0x6-0x7
(Endpoint type is the same as the one defined in EPTYPE1)
Reserved
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.2 EndPoint Status Clear n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
EPSTATUSCLRn
0x104
0x00
PAC Write-Protection
7
BK1RDY
W
0
6
BK0RDY
W
0
5
STALLRQ1
W
0
4
STALLRQ0
W
0
3
2
CURBK
W
0
1
DTGLIN
W
0
0
DTGLOUT
W
0
Bit 7 – BK1RDY Bank 1 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK1RDY bit.
Bit 6 – BK0RDY Bank 0 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK0RDY bit.
Bit 5 – STALLRQ1 STALL bank 1 Request Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ1 bit.
Bit 4 – STALLRQ0 STALL bank 0 Request Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ0 bit.
Bit 2 – CURBK Current Bank Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.CURBK bit.
Bit 1 – DTGLIN Data Toggle IN Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.DTGLIN bit.
Bit 0 – DTGLOUT Data Toggle OUT Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the EPSTATUS.DTGLOUT bit.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.3 EndPoint Status Set n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
EPSTATUSSETn
0x105
0x00
PAC Write-Protection
7
BK1RDY
W
0
6
BK0RDY
W
0
5
STALLRQ1
W
0
4
STALLRQ0
W
0
3
2
CURBK
W
0
1
DTGLIN
W
0
0
DTGLOUT
W
0
Bit 7 – BK1RDY Bank 1 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK1RDY bit.
Bit 6 – BK0RDY Bank 0 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK0RDY bit.
Bit 5 – STALLRQ1 STALL Request bank 1 Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ1 bit.
Bit 4 – STALLRQ0 STALL Request bank 0 Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ0 bit.
Bit 2 – CURBK Current Bank Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.CURBK bit.
Bit 1 – DTGLIN Data Toggle IN Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.DTGLIN bit.
Bit 0 – DTGLOUT Data Toggle OUT Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the EPSTATUS.DTGLOUT bit.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.4 EndPoint Status n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BK1RDY
R
0
EPSTATUSn
0x106
0x00
PAC Write-Protection
6
BK0RDY
R
0
5
STALLRQ1
R
0
4
STALLRQ0
R
2
3
2
CURBK
R
0
1
DTGLIN
R
0
0
DTGLOUT
R
0
Bit 7 – BK1RDY Bank 1 is ready
For Control/OUT direction Endpoints, the bank is empty.
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
Value
Description
0
The bank number 1 is not ready : For IN direction Endpoints, the bank is not yet filled in.
1
The bank number 1 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction
Endpoints, the bank is full.
Bit 6 – BK0RDY Bank 0 is ready
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
Value
Description
0
The bank number 0 is not ready : For IN direction Endpoints, the bank is not yet filled in. For
Control/OUT direction Endpoints, the bank is empty.
1
The bank number 0 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction
Endpoints, the bank is full.
Bits 4, 5 – STALLRQ STALL bank x request
Writing a zero to the bit EPSTATUSCLR.STALLRQ will clear this bit.
Writing a one to the bit EPSTATUSSET.STALLRQ will set this bit.
This bit is cleared by hardware when receiving a SETUP packet.
Value
Description
0
Disable STALLRQx feature.
1
Enable STALLRQx feature: a STALL handshake will be sent to the host in regards to bank x.
Bit 2 – CURBK Current Bank
Writing a zero to the bit EPSTATUSCLR.CURBK will clear this bit.
Writing a one to the bit EPSTATUSSET.CURBK will set this bit.
Value
Description
0
The bank0 is the bank that will be used in the next single/multi USB packet.
1
The bank1 is the bank that will be used in the next single/multi USB packet.
Bit 1 – DTGLIN Data Toggle IN Sequence
Writing a zero to the bit EPSTATUSCLR.DTGLINCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLINSET will set this bit.
Value
Description
0
The PID of the next expected IN transaction will be zero: data 0.
1
The PID of the next expected IN transaction will be one: data 1.
Bit 0 – DTGLOUT Data Toggle OUT Sequence
Writing a zero to the bit EPSTATUSCLR.DTGLOUTCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLOUTSET will set this bit.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Value
0
1
Description
The PID of the next expected OUT transaction will be zero: data 0.
The PID of the next expected OUR transaction will be one: data 1.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.5 Device EndPoint Interrupt Flag n
Name:
Offset:
Reset:
Property:
Bit
EPINTFLAGn
0x107
0x00
-
7
Access
Reset
6
STALL1
R/W
0
5
STALL0
R/W
2
4
RXSTP
R/W
0
3
TRFAIL1
R/W
0
2
TRFAIL0
R/W
2
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bits 5, 6 – STALL Transmit Stall x Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL is one.
EPINTFLAG.STALL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL Interrupt Flag.
Bit 4 – RXSTP Received Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Received Setup occurs and will generate an interrupt if EPINTENCLR/SET.RXSTP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the RXSTP Interrupt Flag.
Bits 2, 3 – TRFAIL Transfer Fail x Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL is one.
EPINTFLAG.TRFAIL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is
"0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL Interrupt Flag.
Bits 0, 1 – TRCPT Transfer Complete x interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer complete occurs and will generate an interrupt if EPINTENCLR/SET.TRCPT is one.
EPINTFLAG.TRCPT is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT0 Interrupt Flag.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.6 Device EndPoint Interrupt Enable n
Name:
Offset:
Reset:
Property:
EPINTENCLRn
0x108
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
Bit
7
Access
Reset
6
STALL1
R/W
0
5
STALL0
R/W
2
4
RXSTP
R/W
0
3
TRFAIL1
R/W
0
2
TRFAIL0
R/W
2
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bits 5, 6 – STALL Transmit STALL x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall x Interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transmit Stall x interrupt is disabled.
1
The Transmit Stall x interrupt is enabled and an interrupt request will be generated when the Transmit
Stall x Interrupt Flag is set.
Bit 4 – RXSTP Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Received Setup interrupt is disabled.
1
The Received Setup interrupt is enabled and an interrupt request will be generated when the Received
Setup Interrupt Flag is set.
Bits 2, 3 – TRFAIL Transfer Fail x Interrupt Enable
The user should look into the descriptor table status located in ram to be informed about the error condition :
ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail x Interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Fail bank x interrupt is disabled.
1
The Transfer Fail bank x interrupt is enabled and an interrupt request will be generated when the
Transfer Fail x Interrupt Flag is set.
Bits 0, 1 – TRCPT Transfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete x interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Complete bank x interrupt is disabled.
1
The Transfer Complete bank x interrupt is enabled and an interrupt request will be generated when the
Transfer Complete x Interrupt Flag is set.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.12.7 Device Interrupt EndPoint Set n
Name:
Offset:
Reset:
Property:
EPINTENSETn
0x109
0x0000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register. This register is cleared by
USB reset or when EPEN[n] is zero.
Bit
7
Access
Reset
6
STALL1
R/W
0
5
STALL0
R/W
2
4
RXSTP
R/W
0
3
TRFAIL1
R/W
0
2
TRFAIL0
R/W
2
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bits 5, 6 – STALL Transmit Stall x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank x Stall interrupt.
Value
Description
0
The Transmit Stall x interrupt is disabled.
1
The Transmit Stall x interrupt is enabled.
Bit 4 – RXSTP Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Received Setup interrupt.
Value
Description
0
The Received Setup interrupt is disabled.
1
The Received Setup interrupt is enabled.
Bits 2, 3 – TRFAIL Transfer Fail bank x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value
Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled.
Bits 0, 1 – TRCPT Transfer Complete bank x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete x interrupt.
0.2.4 Device Registers - Endpoint RAM
Value
Description
0
The Transfer Complete bank x interrupt is disabled.
1
The Transfer Complete bank x interrupt is enabled.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Endpoint Descriptor Structure
Data Buffers
EPn BK1
EPn BK0
Endpoint
descriptors
Reserved
Bank1
Reserved
PCKSIZE
ADDR
(2 x 0xn0) + 0x10
Reserved
STATUS_BK
Bank0
EXTREG
PCKSIZE
ADDR
2 x 0xn0
Reserved
+0x01B
+0x01A
+0x018
+0x014
+0x010
+0x00B
+0x00A
+0x008
+0x004
+0x000
STATUS_BK
Bank1
Reserved
PCKSIZE
ADDR
Bank0
Reserved
STATUS_BK
EXTREG
PCKSIZE
ADDR
© 2021 Microchip Technology Inc.
and its subsidiaries
Growing Memory Addresses
Descriptor En
STATUS_BK
Descriptor E0
32.13
DESCADD
Complete Datasheet
DS40001882H-page 739
SAM D21/DA1 Family
USB – Universal Serial Bus
32.14
Device Endpoint RAM Register Summary
Offset
Name
0x00
ADDR
0x04
PCKSIZE
0x08
EXTREG
0x0A
STATUS_BK
32.15
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
7:0
7
6
5
MULTI_PACKET_SIZE[1:0]
AUTO_ZLP
SIZE[2:0]
VARIABLE[3:0]
4
3
2
1
ADDR[7:0]
ADDR[15:8]
ADDR[23:16]
ADDR[31:24]
BYTE_COUNT[7:0]
BYTE_COUNT[13:8]
MULTI_PACKET_SIZE[9:2]
MULTI_PACKET_SIZE[13:10]
SUBPID[3:0]
VARIABLE[10:4]
ERRORFLOW
0
CRCERR
Device Endpoint RAM Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description.
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 740
SAM D21/DA1 Family
USB – Universal Serial Bus
32.15.1 Address of Data Buffer
Name:
Offset:
Reset:
Property:
ADDR
0x00
0xXXXXXXX
NA
Old address offset 0x00 and 0x10
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
R/W
x
R/W
x
R/W
x
23
22
21
R/W
x
R/W
x
R/W
x
15
14
13
28
27
ADDR[31:24]
R/W
R/W
x
x
26
25
24
R/W
x
R/W
x
R/W
x
18
17
16
R/W
x
R/W
x
R/W
x
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
20
19
ADDR[23:16]
R/W
R/W
x
x
12
ADDR[15:8]
Access
Reset
Bit
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
ADDR[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 31:0 – ADDR[31:0] Data Pointer Address Value
These bits define the data pointer address as an absolute word address in RAM. The two least significant bits must
be zero to ensure the start address is 32-bit aligned.
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 741
SAM D21/DA1 Family
USB – Universal Serial Bus
32.15.2 Packet Size
Name:
Offset:
Reset:
Property:
PCKSIZE
0x04
0xXXXXXXXX
NA
Original offset 0x04 & 0x14
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
AUTO_ZLP
R/W
x
R/W
0
29
SIZE[2:0]
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
MULTI_PACKET_SIZE[1:0]
R/W
R/W
0
x
Bit
Access
Reset
30
28
27
R/W
x
R/W
0
20
19
MULTI_PACKET_SIZE[9:2]
R/W
R/W
0
0
13
12
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
26
25
MULTI_PACKET_SIZE[13:10]
R/W
R/W
0
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
x
11
10
BYTE_COUNT[13:8]
R/W
R/W
0
0
4
3
BYTE_COUNT[7:0]
R/W
R/W
0
0
24
Bit 31 – AUTO_ZLP Automatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the endpoint.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for IN endpoints only. When
disabled the handshake should be managed by firmware.
Value
Description
0
Automatic Zero Length Packet is disabled.
1
Automatic Zero Length Packet is enabled.
Bits 30:28 – SIZE[2:0] Endpoint size
These bits contains the maximum packet size of the endpoint.
Value
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Note: 1. For isochronous endpoint only.
8 Byte
16 Byte
32 Byte
64 Byte
128 Byte(1)
256 Byte(1)
512 Byte(1)
1023 Byte(1)
Bits 27:14 – MULTI_PACKET_SIZE[13:0] Multiple Packet Size
These bits define the 14-bit value that is used for multi-packet transfers.
For IN endpoints, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be
written to zero when setting up a new transfer.
For OUT endpoints, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be a
multiple of the maximum packet size.
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 742
SAM D21/DA1 Family
USB – Universal Serial Bus
Bits 13:0 – BYTE_COUNT[13:0] Byte Count
These bits define the 14-bit value that is used for the byte count.
For IN endpoints, BYTE_COUNT holds the number of bytes to be sent in the next IN transaction.
For OUT endpoint or SETUP endpoints, BYTE_COUNT holds the number of bytes received upon the last OUT or
SETUP transaction.
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 743
SAM D21/DA1 Family
USB – Universal Serial Bus
32.15.3 Extended Register
Name:
Offset:
Reset:
Property:
Bit
EXTREG
0x08
0xXXXXXXX
NA
15
Access
Reset
Bit
7
Access
Reset
R/W
0
14
13
12
R/W
0
R/W
0
6
5
VARIABLE[3:0]
R/W
R/W
0
0
10
9
8
R/W
0
11
VARIABLE[10:4]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
2
R/W
x
R/W
0
1
SUBPID[3:0]
R/W
R/W
0
0
0
R/W
x
Bits 14:4 – VARIABLE[10:0] Variable field send with extended token
These bits define the VARIABLE field of a received extended token. These bits are updated when the USB has
answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the
reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
To support the USB2.0 Link Power Management addition the VARIABLE field should be read as described below.
VARIABLES
Description
VARIABLE[3:0]
VARIABLE[7:4]
VARIABLE[8]
VARIABLE[10:9]
bLinkState (1)
BESL (2)
bRemoteWake (1)
Reserved
1.
2.
For a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference
document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum".
For a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING
CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0
Link Power Management.
Bits 3:0 – SUBPID[3:0] SUBPID field send with extended token
These bits define the SUBPID field of a received extended token. These bits are updated when the USB has
answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the
reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 744
SAM D21/DA1 Family
USB – Universal Serial Bus
32.15.4 Device Status Bank
Name:
Offset:
Reset:
Property:
STATUS_BK
0x0A
0xXXXXXXX
NA
Original offset 0x0A & 0x1A
Bit
7
6
5
4
3
Access
Reset
2
1
ERRORFLOW
R/W
x
0
CRCERR
R/W
x
Bit 1 – ERRORFLOW Error Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For OUT transfer, a NAK handshake has been sent.
For Isochronous OUT transfer, an overrun condition has occurred.
For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow errors.
Value
Description
0
No Error Flow detected.
1
A Error Flow has been detected.
Bit 0 – CRCERR CRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank.
0.2.5 Host Registers - Common
Value
Description
0
No CRC Error.
1
CRC Error detected.
© 2021 Microchip Technology Inc.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.16
Host Registers - Common - Register Summary
Offset
Name
0x00
...
0x07
Reserved
0x08
CTRLB
0x0A
0x0B
0x0C
0x0D
...
0x0F
HSOFC
Reserved
STATUS
0x10
FNUM
0x12
0x13
FLENHIGH
Reserved
0x14
INTENCLR
0x16
...
0x17
Reserved
0x18
INTENSET
0x1A
...
0x1B
Reserved
0x1C
INTFLAG
0x1E
...
0x1F
Reserved
0x20
PINTSMRY
32.17
Bit Pos.
7
7:0
15:8
7:0
7:0
6
5
4
TSTK
TSTJ
AUTORESUM
E
3
2
SPDCONF[1:0]
L1RESUME
FLENCE
LINESTATE[1:0]
1
0
RESUME
VBUSOK
BUSRESET
FLENC[3:0]
SOFE
SPEED[1:0]
Reserved
7:0
15:8
7:0
FNUM[4:0]
MFNUM[2:0]
FNUM[10:5]
FLENHIGH[7:0]
7:0
15:8
RAMACER
7:0
15:8
RAMACER
7:0
15:8
RAMACER
7:0
15:8
EPINT7
UPRSM
UPRSM
UPRSM
EPINT6
DNRSM
DNRSM
DNRSM
EPINT5
WAKEUP
WAKEUP
WAKEUP
EPINT4
RST
RST
RST
EPINT3
HSOF
DDISC
DCONN
DDISC
DCONN
DDISC
DCONN
EPINT1
EPINT0
HSOF
HSOF
EPINT2
Host Registers - Common - Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 746
SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.1 Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x08
0x0000
PAC Write-Protection
15
14
13
12
7
6
TSTK
R/W
0
5
TSTJ
R/W
0
4
AUTORESUME
R/W
0
Access
Reset
Bit
Access
Reset
11
L1RESUME
R/W
0
10
VBUSOK
R/W
0
3
2
SPDCONF[1:0]
R/W
R/W
0
0
9
BUSRESET
R/W
0
8
SOFE
R/W
0
1
RESUME
R/W
0
0
Bit 11 – L1RESUME Send USB L1 Resume
Writing 0 to this bit has no effect.
1: Generates a USB L1 Resume on the USB bus. This bit should only be set when the Start-of-Frame generation is
enabled (SOFE bit set). The duration of the USB L1 Resume is defined by the EXTREG.VARIABLE[7:4] bits field also
known as BESL (See LPM ECN).See the EXTREG Register.
This bit is cleared when the USB L1 Resume has been sent or when a USB reset is requested.
Bit 10 – VBUSOK VBUS is OK
This notifies the USB HOST that USB operations can be started. When this bit is zero and even if the USB HOST
is configured and enabled, HOST operation is halted. Setting this bit will allow HOST operation when the USB is
configured and enabled.
Value
Description
0
The USB module is notified that the VBUS on the USB line is not powered.
1
The USB module is notified that the VBUS on the USB line is powered.
Bit 9 – BUSRESET Send USB Reset
Value
Description
0
Reset generation is disabled. It is written to zero when the USB reset is completed or when a device
disconnection is detected. Writing zero has no effect.
1
Generates a USB Reset on the USB bus.
Bit 8 – SOFE Start-of-Frame Generation Enable
Value
Description
0
The SOF generation is disabled and the USB bus is in suspend state.
1
Generates SOF on the USB bus in full speed and keep it alive in low speed mode. This bit is
automatically set at the end of a USB reset (INTFLAG.RST) or at the end of a downstream resume
(INTFLAG.DNRSM) or at the end of L1 resume.
Bit 6 – TSTK Test mode K
Value
Description
0
The UTMI transceiver is in normal operation Mode
1
The UTMI transceiver generates high speed K state for test purposes.
Bit 5 – TSTJ Test mode J
Value
Description
0
The UTMI transceiver is in normal operation Mode
1
The UTMI transceiver generates high speed J state for test purposes.
Bit 4 – AUTORESUME Auto Resume Enable
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SAM D21/DA1 Family
USB – Universal Serial Bus
Value
0
1
Description
The Auto Resume is disabled.
Enable Auto Resume
Bits 3:2 – SPDCONF[1:0] Speed Configuration for Host
These bits select the host speed configuration as shown below
Value
Description
0x0
Low, Full and High Speed capable
0x1
Reserved
0x2
Reserved
0x3
Low and Full Speed capable
Bit 1 – RESUME Send USB Resume
Writing 0 to this bit has no effect.
1: Generates a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.2 Host Start-of-Frame Control
Name:
Offset:
Reset:
Property:
HSOFC
0x0A
0x00
PAC Write-Protection
During a very short period just before transmitting a Start-of-Frame, this register is locked. Thus, after writing, it is
recommended to check the register value, and write this register again if necessary. This register is cleared upon a
USB reset.
Bit
7
FLENCE
R/W
0
Access
Reset
6
5
4
3
2
1
0
R/W
0
R/W
0
FLENC[3:0]
R/W
0
R/W
0
Bit 7 – FLENCE Frame Length Control Enable
When this bit is '1', the time between Start-of-Frames can be tuned by up to +/-0.06% using FLENC[3:0].
Note: In Low Speed mode, FLENCE must be '0'.
FLENCE Frame Timing
Internal Frame Length Down-Counter Load Value
0
0
11999 (1ms frame rate at 12MHz)
59999 (1ms frame rate at 60MHz)
7499 (0.125ms micro-frame rate at 60MHz)
FLENC[3:0]
11999 + FLENC[3:0] at all speeds.
1
Value
0
1
Internal Frame Length (Full Speed)
Internal Frame Length in Low and Full speed
Internal Frame Length in High speed
Beginning of Frame
Internal Frame Length with Frame correction
Description
Start-of-Frame is generated every 1ms.
Start-of-Frame generation depends on the signed value of FLENC[3:0].
USB Start-of-Frame period equals 1ms + (FLENC[3:0]/12000)ms
Bits 3:0 – FLENC[3:0] Frame Length Control
These bits define the signed value of the 4-bit FLENC that is added to the Internal Frame Length when FLENCE is
'1'. The internal Frame length is the top value of the frame counter when FLENCE is zero.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.3 Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x0C
0x00
Read only
7
6
LINESTATE[1:0]
R
R
0
0
Access
Reset
5
4
3
2
1
0
SPEED[1:0]
R/W
0
R/W
0
Bits 7:6 – LINESTATE[1:0] USB Line State Status
These bits define the current line state DP/DM.
LINESTATE[1:0]
USB Line Status
0x0
0x1
0x2
SE0/RESET
FS-J or LS-K State
FS-K or LS-J State
Bits 3:2 – SPEED[1:0] Speed Status
These bits define the current speed used by the host.
SPEED[1:0]
Speed Status
0x0
0x1
0x2
0x3
Full-speed mode
Low-speed mode High-speed mode
Low-speed mode
Reserved
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Complete Datasheet
DS40001882H-page 750
SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.4 Host Frame Number
Name:
Offset:
Reset:
Property:
Bit
FNUM
0x10
0x0000
PAC Write-Protection
15
14
Access
Reset
Bit
Access
Reset
7
6
R/W
0
R/W
0
13
12
11
10
FNUM[10:5]
R/W
R/W
0
0
R/W
0
R/W
0
5
FNUM[4:0]
R/W
0
4
3
2
R/W
0
R/W
0
R/W
0
9
8
R/W
0
R/W
0
1
MFNUM[2:0]
R/W
0
0
R/W
0
Bits 13:3 – FNUM[10:0] Frame Number
These bits contains the current SOF number.
These bits can be written by software to initialize a new frame number value. In this case, at the next SOF, the FNUM
field takes its new value and the MFNUM bits are cleared.
As the FNUM register lies across two consecutive byte addresses, writing byte-wise (8-bits) to the FNUM register
may produce incorrect frame number generation. It is recommended to write FNUM register word-wise (32-bits) or
half-word-wise (16-bits).
Bits 2:0 – MFNUM[2:0] Micro Frame Number
These bits are tied to zero when operating in full-speed mode.
These bits contains the current Micro Frame number (can vary from 0 to 7) updated every 125 us.
© 2021 Microchip Technology Inc.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.5 Host Frame Length
Name:
Offset:
Reset:
Property:
FLENHIGH
0x12
0x00
Read-Only
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
4
3
FLENHIGH[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 7:0 – FLENHIGH[7:0] Frame Length
These bits contains the 8 high-order bits of the internal frame counter.
Table 32-1. Counter Description vs. Speed
Host Register
Description
STATUS.SPEED
Full Speed
Full Speed
High Speed
With a USB clock running at 12MHz, counter length is 12000 to ensure a SOF generation every
1 ms.
With a USB clock running at 60MHz, counter length is 60000 to ensure a SOF generation every
1 ms.
With a USB clock running at 60MHz, counter length is 7500 to ensure a SOF generation every
125 μs.
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Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.6 Host Interrupt Enable Register Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x14
0x0000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
15
14
13
12
11
10
9
DDISC
R/W
0
8
DCONN
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
DNRSM
R/W
0
4
WAKEUP
R/W
0
3
RST
R/W
0
2
HSOF
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bit 9 – DDISC Device Disconnection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the corresponding
interrupt request.
Value
Description
0
The Device Disconnection interrupt is disabled.
1
The Device Disconnection interrupt is enabled and an interrupt request will be generated when the
Device Disconnection interrupt Flag is set.
Bit 8 – DCONN Device Connection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Device Connection interrupt is disabled.
1
The Device Connection interrupt is enabled and an interrupt request will be generated when the Device
Connection interrupt Flag is set.
Bit 7 – RAMACER RAM Access Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access
interrupt Flag is set.
Bit 6 – UPRSM Upstream Resume from Device Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Upstream Resume interrupt is disabled.
1
The Upstream Resume interrupt is enabled and an interrupt request will be generated when the
Upstream Resume interrupt Flag is set.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Bit 5 – DNRSM Down Resume Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Down Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Down Resume interrupt is disabled.
1
The Down Resume interrupt is enabled and an interrupt request will be generated when the Down
Resume interrupt Flag is set.
Bit 4 – WAKEUP Wake Up Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Wake Up interrupt is disabled.
1
The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up
interrupt Flag is set.
Bit 3 – RST BUS Reset Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Bus Reset interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Bus Reset interrupt is disabled.
1
The Bus Reset interrupt is enabled and an interrupt request will be generated when the Bus Reset
interrupt Flag is set.
Bit 2 – HSOF Host Start-of-Frame Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Host Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Host Start-of-Frame interrupt is disabled.
1
The Host Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Host
Start-of-Frame interrupt Flag is set.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.7 Host Interrupt Enable Register Set
Name:
Offset:
Reset:
Property:
INTENSET
0x18
0x0000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
15
14
13
12
11
10
9
DDISC
R/W
0
8
DCONN
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
DNRSM
R/W
0
4
WAKEUP
R/W
0
3
RST
R/W
0
2
HSOF
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bit 9 – DDISC Device Disconnection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Disconnection interrupt bit and enable the DDSIC interrupt.
Value
Description
0
The Device Disconnection interrupt is disabled.
1
The Device Disconnection interrupt is enabled.
Bit 8 – DCONN Device Connection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Connection interrupt bit and enable the DCONN interrupt.
Value
Description
0
The Device Connection interrupt is disabled.
1
The Device Connection interrupt is enabled.
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access interrupt bit and enable the RAMACER interrupt.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled.
Bit 6 – UPRSM Upstream Resume from the device Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume interrupt bit and enable the UPRSM interrupt.
Value
Description
0
The Upstream Resume interrupt is disabled.
1
The Upstream Resume interrupt is enabled.
Bit 5 – DNRSM Down Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Down Resume interrupt Enable bit and enable the DNRSM interrupt.
Value
Description
0
The Down Resume interrupt is disabled.
1
The Down Resume interrupt is enabled.
Bit 4 – WAKEUP Wake Up Interrupt Enable
Writing a zero to this bit has no effect.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the WAKEUP interrupt request.
Value
Description
0
The WakeUp interrupt is disabled.
1
The WakeUp interrupt is enabled.
Bit 3 – RST Bus Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Bus Reset interrupt Enable bit and enable the Bus RST interrupt.
Value
Description
0
The Bus Reset interrupt is disabled.
1
The Bus Reset interrupt is enabled.
Bit 2 – HSOF Host Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Host Start-of-Frame interrupt Enable bit and enable the HSOF interrupt.
Value
Description
0
The Host Start-of-Frame interrupt is disabled.
1
The Host Start-of-Frame interrupt is enabled.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.8 Host Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x1C
0x0000
-
15
14
13
12
11
10
9
DDISC
R/W
0
8
DCONN
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
DNRSM
R/W
0
4
WAKEUP
R/W
0
3
RST
R/W
0
2
HSOF
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bit 9 – DDISC Device Disconnection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the device has been removed from the USB Bus and will generate an interrupt if INTENCLR/
SET.DDISC is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DDISC Interrupt Flag.
Bit 8 – DCONN Device Connection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a new device has been connected to the USB BUS and will generate an interrupt if INTENCLR/
SET.DCONN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DCONN Interrupt Flag.
Bit 7 – RAMACER RAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a RAM access error occurs during an OUT stage and will generate an interrupt if INTENCLR/
SET.RAMACER is one.
Writing a zero to this bit has no effect.
Bit 6 – UPRSM Upstream Resume from the Device Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has received an Upstream Resume signal from the Device and will generate an
interrupt if INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
Bit 5 – DNRSM Down Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has sent a Down Resume and will generate an interrupt if INTENCLR/SET.DRSM is
one.
Writing a zero to this bit has no effect.
Bit 4 – WAKEUP Wake Up Interrupt Flag
This flag is cleared by writing a one.
This flag is set when:
l The host controller is in suspend mode (SOFE is zero) and an upstream resume from the device is detected.
l The host controller is in suspend mode (SOFE is zero) and an device disconnection is detected.
l The host controller is in operational state (VBUSOK is one) and an device connection is detected.
In all cases it will generate an interrupt if INTENCLR/SET.WAKEUP is one.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Writing a zero to this bit has no effect.
Bit 3 – RST Bus Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Bus “Reset” has been sent to the Device and will generate an interrupt if INTENCLR/SET.RST
is one.
Writing a zero to this bit has no effect.
Bit 2 – HSOF Host Start-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Host Start-of-Frame” in Full Speed or a keep-alive in Low Speed has been sent (every 1
ms) and will generate an interrupt if INTENCLR/SET.HSOF is one.
The value of the FNUM register is updated.
Writing a zero to this bit has no effect.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.17.9 Pipe Interrupt Summary
Name:
Offset:
Reset:
Property:
Bit
PINTSMRY
0x20
0x0000
Read-only
15
14
13
12
11
10
9
8
7
EPINT7
R
0
6
EPINT6
R
0
5
EPINT5
R
0
4
EPINT4
R
0
3
EPINT3
R
0
2
EPINT2
R
0
1
EPINT1
R
0
0
EPINT0
R
0
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – EPINT
The flag EPINTn is set when an interrupt is triggered by the pipe n. See the PINTFLAG register in the Host Pipe
Register section.
This bit will be cleared when there are no interrupts pending for Pipe n.
Writing to this bit has no effect.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.18
Offset
0x00
...
0xFF
0x0100
0x0101
...
0x0102
0x0103
0x0104
0x0105
0x0106
0x0107
0x0108
0x0109
32.19
Host Registers - Pipe - Register Summary
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
PCFGn
7:0
PTYPE[2:0]
BK
PTOKEN[1:0]
Reserved
BINTERVAL
PSTATUSCLR
PSTATUSSET
PSTATUS
PINTFLAG
PINTENCLR
PINTENSET
7:0
7:0
7:0
7:0
7:0
7:0
7:0
BK1RDY
BK1RDY
BK1RDY
BK0RDY
BK0RDY
BK0RDY
STALL
STALL
STALL
BINTERVAL[7:0]
PFREEZE
PFREEZE
PFREEZE
TXSTP
PERR
TXSTP
PERR
TXSTP
PERR
CURBK
CURBK
CURBK
TRFAIL
TRFAIL
TRFAIL
TRCPT1
TRCPT1
TRCPT1
DTGL
DTGL
DTGL
TRCPT0
TRCPT0
TRCPT0
Host Registers - Pipe - Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.19.1 Host Pipe n Configuration
Name:
Offset:
Reset:
Property:
Bit
PCFGn
0x100
0x00
PAC Write-Protection
7
6
5
Access
Reset
R/W
0
4
PTYPE[2:0]
R/W
0
3
R/W
0
2
BK
R/W
0
1
0
PTOKEN[1:0]
R/W
R/W
0
0
Bits 5:3 – PTYPE[2:0] Type of the Pipe
These bits contains the pipe type.
PTYPE[2:0]
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x06-0x7
Pipe is disabled
Pipe is enabled and configured as CONTROL
Pipe is enabled and configured as ISO
Pipe is enabled and configured as BULK
Pipe is enabled and configured as INTERRUPT
Pipe is enabled and configured as EXTENDED
Reserved
These bits are cleared upon sending a USB reset.
Bit 2 – BK Pipe Bank
This bit selects the number of banks for the pipe.
For control endpoints writing a zero to this bit is required as only Bank0 is used for Setup/In/Out transactions.
This bit is cleared when a USB reset is sent.
BK (1)
Description
0x0
0x1
Single-bank endpoint
Dual-bank endpoint
1.
Value
0
1
Bank field is ignored when PTYPE is configured as EXTENDED.
Description
A single bank is used for the pipe.
A dual bank is used for the pipe.
Bits 1:0 – PTOKEN[1:0] Pipe Token
These bits contains the pipe token.
PTOKEN[1:0](1)
Description
0x0
0x1
0x2
0x3
SETUP(2)
IN
OUT
Reserved
1.
2.
PTOKEN field is ignored when PTYPE is configured as EXTENDED.
Available only when PTYPE is configured as CONTROL
Theses bits are cleared upon sending a USB reset.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.19.2 Interval for the Bulk-Out/Ping Transaction
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
BINTERVAL
0x103
0x00
PAC Write-Protection
7
6
5
R/W
0
R/W
0
R/W
0
4
3
BINTERVAL[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BINTERVAL[7:0] BINTERVAL
These bits contains the Ping/Bulk-out period.
These bits are cleared when a USB reset is sent or when PEN[n] is zero.
BINTERVAL
Description
=0
>0
Multiple consecutive OUT token is sent in the same frame until it is acked by the peripheral
One OUT token is sent every BINTERVAL frame until it is acked by the peripheral
PCFGn.PINGEN BINTERVAL Description
0
=0
0
>0
1
=0
1
>0
Multiple consecutive OUT token is sent in the same frame until it is acked by the
peripheral
One OUT token is sent every BINTERVAL micro frame until it is acked by the
peripheral
Multiple consecutive PING token is sent in the same frame until it is acked by the
peripheral
One PING token is sent every BINTERVAL frame until it is acked by the peripheral
Depending from the type of pipe the desired period is defined as:
PTYPE
Description
Interrupt
Isochronous
Bulk or control
EXT LPM
1 ms to 255 ms
2^(Binterval) * 1 ms
1 ms to 255 ms
bInterval ignored. Always 1 ms when a NYET is received.
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SAM D21/DA1 Family
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32.19.3 Pipe Status Clear n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
PSTATUSCLR
0x104
0x00
PAC Write-Protection
7
BK1RDY
W
0
6
BK0RDY
W
0
5
4
PFREEZE
W
0
3
2
CURBK
W
0
1
0
DTGL
W
0
Bit 7 – BK1RDY Bank 1 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK1RDY bit.
Bit 6 – BK0RDY Bank 0 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK0RDY bit.
Bit 4 – PFREEZE Pipe Freeze Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.PFREEZE bit.
Bit 2 – CURBK Current Bank Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.CURBK bit.
Bit 0 – DTGL Data Toggle Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.DTGL bit.
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SAM D21/DA1 Family
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32.19.4 Pipe Status Set Register n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BK1RDY
W
0
PSTATUSSET
0x105
0x00
PAC Write-Protection
6
BK0RDY
W
0
5
4
PFREEZE
W
0
3
2
CURBK
W
0
1
0
DTGL
W
0
Bit 7 – BK1RDY Bank 1 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK1RDY.
Bit 6 – BK0RDY Bank 0 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK0RDY.
Bit 4 – PFREEZE Pipe Freeze Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.PFREEZE bit.
Bit 2 – CURBK Current Bank Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.CURBK bit.
Bit 0 – DTGL Data Toggle Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.DTGL bit.
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SAM D21/DA1 Family
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32.19.5 Pipe Status Register n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
PSTATUS
0x106
0x00
PAC Write-Protection
7
BK1RDY
R
0
6
BK0RDY
R
0
5
4
PFREEZE
R
0
3
2
CURBK
R
0
1
0
DTGL
R
0
Bit 7 – BK1RDY Bank 1 is ready
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
This bank is not used for Control pipe.
Value
Description
0
The bank number 1 is not ready: For IN the bank is empty. For Control/OUT the bank is not yet fill in.
1
The bank number 1 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Bit 6 – BK0RDY Bank 0 is ready
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
This bank is the only one used for Control pipe.
Value
Description
0
The bank number 0 is not ready: For IN the bank is not empty. For Control/OUT the bank is not yet fill
in.
1
The bank number 0 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Bit 4 – PFREEZE Pipe Freeze
Writing a one to the bit EPSTATUSCLR.PFREEZE will clear this bit.
Writing a one to the bit EPSTATUSSET.PFREEZE will set this bit.
This bit is also set by the hardware:
• When a STALL handshake has been received.
• After a PIPE has been enabled (rising of bit PEN.N).
• When an LPM transaction has completed whatever handshake is returned or the transaction was timed-out.
• When a pipe transfer was completed with a pipe error. See the PINTFLAG register.
When PFREEZE bit is set while a transaction is in progress on the USB bus, this transaction will be properly
completed. PFREEZE bit will be read as “1” only when the ongoing transaction will have been completed.
Value
Description
0
The Pipe operates in normal operation.
1
The Pipe is frozen and no additional requests will be sent to the device on this pipe address.
Bit 2 – CURBK Current Bank
Value
Description
0
The bank0 is the bank that will be used in the next single/multi USB packet.
1
The bank1 is the bank that will be used in the next single/multi USB packet.
Bit 0 – DTGL Data Toggle Sequence
Writing a one to the bit EPSTATUSCLR.DTGL will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGL will set this bit.
This bit is toggled automatically by hardware after a data transaction.
This bit will reflect the data toggle in regards of the token type (IN/OUT/SETUP).
Value
Description
0
The PID of the next expected transaction will be zero: data 0.
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Value
1
Description
The PID of the next expected transaction will be one: data 1.
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SAM D21/DA1 Family
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32.19.6 Host Pipe Interrupt Flag Register
Name:
Offset:
Reset:
Property:
Bit
PINTFLAG
0x107
0x00
-
7
6
Access
Reset
5
STALL
R/W
0
4
TXSTP
R/W
0
3
PERR
R/W
0
2
TRFAIL
R/W
0
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bit 5 – STALL STALL Received Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a stall occurs and will generate an interrupt if PINTENCLR/SET.STALL is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL Interrupt Flag.
Bit 4 – TXSTP Transmitted Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Complete occurs and will generate an interrupt if PINTENCLR/SET.TXSTP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TXSTP Interrupt Flag.
Bit 3 – PERR Pipe Error Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a pipe error occurs and will generate an interrupt if PINTENCLR/SET.PERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the PERR Interrupt Flag.
Bit 2 – TRFAIL Transfer Fail Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Fail occurs and will generate an interrupt if PINTENCLR/SET.TRFAIL is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL Interrupt Flag.
Bits 0, 1 – TRCPT Transfer Complete x interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer complete occurs and will generate an interrupt if PINTENCLR/SET.TRCPT is one.
PINTFLAG.TRCPT is set for a single bank IN/OUT pipe or a double bank IN/OUT pipe when current bank is 0.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT Interrupt Flag.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.19.7 Host Pipe Interrupt Clear Register
Name:
Offset:
Reset:
Property:
PINTENCLR
0x108
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register.
This register is cleared by USB reset or when PEN[n] is zero.
Bit
7
6
Access
Reset
5
STALL
R/W
0
4
TXSTP
R/W
0
3
PERR
R/W
0
2
TRFAIL
R/W
0
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bit 5 – STALL Received Stall Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Stall interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The received Stall interrupt is disabled.
1
The received Stall interrupt is enabled and an interrupt request will be generated when the received
Stall interrupt Flag is set.
Bit 4 – TXSTP Transmitted Setup Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmitted Setup interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transmitted Setup interrupt is disabled.
1
The Transmitted Setup interrupt is enabled and an interrupt request will be generated when the
Transmitted Setup interrupt Flag is set.
Bit 3 – PERR Pipe Error Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Pipe Error interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Pipe Error interrupt is disabled.
1
The Pipe Error interrupt is enabled and an interrupt request will be generated when the Pipe Error
interrupt Flag is set.
Bit 2 – TRFAIL Transfer Fail Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail
interrupt Flag is set.
Bits 0, 1 – TRCPT Transfer Complete Bank x interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt Enable bit x and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Complete Bank x interrupt is disabled.
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SAM D21/DA1 Family
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Value
1
Description
The Transfer Complete Bank x interrupt is enabled and an interrupt request will be generated when the
Transfer Complete interrupt x Flag is set.
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32.19.8 Host Interrupt Pipe Set Register
Name:
Offset:
Reset:
Property:
PINTENSET
0x109
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.
This register is cleared by USB reset or when PEN[n] is zero.
Bit
7
6
Access
Reset
5
STALL
R/W
0
4
TXSTP
R/W
0
3
PERR
R/W
0
2
TRFAIL
R/W
0
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bit 5 – STALL Stall Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Stall interrupt.
Value
Description
0
The Stall interrupt is disabled.
1
The Stall interrupt is enabled.
Bit 4 – TXSTP Transmitted Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmitted Setup interrupt.
Value
Description
0
The Transmitted Setup interrupt is disabled.
1
The Transmitted Setup interrupt is enabled.
Bit 3 – PERR Pipe Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Pipe Error interrupt.
Value
Description
0
The Pipe Error interrupt is disabled.
1
The Pipe Error interrupt is enabled.
Bit 2 – TRFAIL Transfer Fail Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value
Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled.
Bits 0, 1 – TRCPT Transfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete interrupt Enable bit x.
0.2.7 Host Registers - Pipe RAM
Value
Description
0
The Transfer Complete x interrupt is disabled.
1
The Transfer Complete x interrupt is enabled.
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SAM D21/DA1 Family
USB – Universal Serial Bus
Pipe Descriptor Structure
Data Buffers
Pn BK1
Pn BK0
Pipe descriptors
Reserved
STATUS _PIPE
Bank1
CTRL_BK
Reserved
Descriptor Pn
Reserved
PCKSIZE
ADDR
(2 x 0xn0) + 0x10
Reserved
STATUS _PIPE
Bank0
CTRL_PIPE
STATUS_BK
EXTREG
PCKSIZE
Reserved
STATUS _PIPE
Bank1
CTRL_BK
Reserved
Reserved
PCKSIZE
ADDR
Reserved
STATUS _PIPE
Bank0
CTRL_PIPE
STATUS_BK
EXTREG
PCKSIZE
ADDR
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2 x 0xn0
+0x01F
+0x01E
+0x01C
+0x01A
+0x018
+0x014
+0x010
+0x00F
+0x00E
+0x00C
+0x00A
+0x008
+0x004
+0x000
Growing Memory Addresses
ADDR
Descriptor P0
32.20
DESCADD
Complete Datasheet
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.21
Host Registers - Pipe RAM - Register Summary
Offset
Name
0x00
ADDR
0x04
PCKSIZE
0x08
EXTREG
0x0A
0x0B
STATUS_BK
Reserved
0x0C
CTRL_PIPE
0x0E
32.22
Bit Pos.
STATUS_PIPE
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
7:0
7
6
5
4
3
2
1
0
ADDR[7:0]
ADDR[15:8]
ADDR[23:16]
ADDR[31:24]
MULTI_PACKET_SIZE[1:0]
AUTO_ZLP
7:0
15:8
7:0
15:8
SIZE[2:0]
VARIABLE[3:0]
BYTE_COUNT[5:0]
MULTI_PACKET_SIZE[9:2]
MULTI_PACKET_SIZE[13:10]
SUBPID[3:0]
VARIABLE[10:4]
ERRORFLOW
CRCERR
PDADDR[6:0]
PERMAX[3:0]
ERCNT[2:0]
CRC16ER
TOUTER
PEPNUM[3:0]
PIDER
DAPIDER
DTGLER
Host Registers - Pipe RAM - Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.1 Address of the Data Buffer
Name:
Offset:
Reset:
Property:
ADDR
0x00
0xxxxxxxx
NA
Original offset 0x00 & 0x10
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
ADDR[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
x
20
19
ADDR[23:16]
R/W
R/W
0
0
12
ADDR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – ADDR[31:0] Data Pointer Address Value
These bits define the data pointer address as an absolute double word address in RAM. The two least significant bits
must be zero to ensure the descriptor is 32-bit aligned.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.2 Packet Size
Name:
Offset:
Reset:
Property:
PCKSIZE
0x04
0xXXXXXXX
NA
Original offset 0x04 & 0x14
Bit
Access
Reset
31
AUTO_ZLP
R/W
x
R/W
0
29
SIZE[2:0]
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
Bit
Access
Reset
Bit
Access
Reset
30
15
14
MULTI_PACKET_SIZE[1:0]
R/W
R/W
0
x
Bit
7
6
28
27
R/W
x
R/W
0
20
19
MULTI_PACKET_SIZE[9:2]
R/W
R/W
0
0
13
12
R/W
0
R/W
0
5
4
26
25
MULTI_PACKET_SIZE[13:10]
R/W
R/W
0
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
9
8
R/W
0
R/W
x
1
0
11
10
BYTE_COUNT[5:0]
R/W
R/W
0
0
3
24
2
Access
Reset
Bit 31 – AUTO_ZLP Automatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the pipe.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for OUT pipes only. When
disabled the handshake should be managed by firmware.
Value
Description
0
Automatic Zero Length Packet is disabled.
1
Automatic Zero Length Packet is enabled.
Bits 30:28 – SIZE[2:0] Pipe size
These bits contains the size of the pipe.
Theses bits are cleared upon sending a USB reset.
SIZE[2:0]
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
8 Byte
16 Byte
32 Byte
64 Byte
128 Byte(1)
256 Byte(1)
512 Byte(1)
1024 Byte in HS mode(1)
1023 Byte in FS mode(1)
Note:
1. For Isochronous pipe only.
Bits 27:14 – MULTI_PACKET_SIZE[13:0] Multi Packet IN or OUT size
These bits define the 14-bit value that is used for multi-packet transfers.
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SAM D21/DA1 Family
USB – Universal Serial Bus
For IN pipes, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be written
to zero when setting up a new transfer.
For OUT pipes, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be a
multiple of the maximum packet size.
Bits 13:8 – BYTE_COUNT[5:0] Byte Count
These bits define the 14-bit value that contains number of bytes sent in the last OUT or SETUP transaction for an
OUT pipe, or of the number of bytes to be received in the next IN transaction for an input pipe.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.3 Extended Register
Name:
Offset:
Reset:
Property:
Bit
EXTREG
0x08
0xXXXXXXX
NA
15
Access
Reset
Bit
Access
Reset
7
R/W
0
14
13
12
R/W
0
R/W
0
6
5
VARIABLE[3:0]
R/W
R/W
0
0
10
9
8
R/W
0
11
VARIABLE[10:4]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
2
R/W
x
R/W
0
1
SUBPID[3:0]
R/W
R/W
0
0
0
R/W
x
Bits 14:4 – VARIABLE[10:0] Variable field send with extended token
These bits define the VARIABLE field sent with extended token. See “Section 2.1.1 Protocol Extension Token in the
reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum.”
To support the USB2.0 Link Power Management addition the VARIABLE field should be set as described below.
VARIABLE
Description
VARIABLE[3:0]
VARIABLE[7:4]
VARIABLE[8]
VARIABLE[10:9]
bLinkState(1)
BESL (See LPM ECN)(2)
bRemoteWake(1)
Reserved
Notes:
1. For a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference
document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum".
2. For a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING
CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0
Link Power Management.
Bits 3:0 – SUBPID[3:0] SUBPID field send with extended token
These bits define the SUBPID field sent with extended token. See “Section 2.1.1 Protocol Extension Token in the
reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
To support the USB2.0 Link Power Management addition the SUBPID field should be set as described in “Table
2.2 SubPID Types in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management
Addendum”.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.4 Host Status Bank
Name:
Offset:
Reset:
Property:
STATUS_BK
0x0A
0xXXXXXXX
NA
Original offset 0x0A & 0x1A
Bit
7
6
5
4
3
2
Access
Reset
1
ERRORFLOW
R/W
x
0
CRCERR
R/W
x
Bit 1 – ERRORFLOW Error Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received. For
Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer, an underflow condition
has occurred.
Value
Description
0
No Error Flow detected.
1
A Error Flow has been detected.
Bit 0 – CRCERR CRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous IN endpoint bank.
Value
Description
0
No CRC Error.
1
CRC Error detected.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.5 Host Control Pipe
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
CTRL_PIPE
0x0C
0xXXXX
PAC Write-Protection, Write-Synchronized, Read-Synchronized
15
R/W
0
7
Access
Reset
14
13
PERMAX[3:0]
R/W
R/W
0
0
12
11
R/W
x
R/W
0
3
PDADDR[6:0]
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
10
9
PEPNUM[3:0]
R/W
R/W
0
0
8
R/W
x
2
1
0
R/W
0
R/W
0
R/W
x
Bits 15:12 – PERMAX[3:0] Pipe Error Max Number
These bits define the maximum number of error for this Pipe before freezing the pipe automatically.
Bits 11:8 – PEPNUM[3:0] Pipe EndPoint Number
These bits define the number of endpoint for this Pipe.
Bits 6:0 – PDADDR[6:0] Pipe Device Address
These bits define the Device Address for this pipe.
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SAM D21/DA1 Family
USB – Universal Serial Bus
32.22.6 Host Status Pipe
Name:
Offset:
Reset:
Property:
STATUS_PIPE
0x0E
0xXXXXXXX
PAC Write-Protection, Write-Synchronized, Read-Synchronized
Original offset 0x0E & 0x1E
Bit
15
14
13
12
11
10
9
8
7
6
ERCNT[2:0]
R/W
0
5
4
CRC16ER
R/W
x
3
TOUTER
R/W
x
2
PIDER
R/W
x
1
DAPIDER
R/W
x
0
DTGLER
R/W
x
Access
Reset
Bit
Access
Reset
R/W
0
R/W
x
Bits 7:5 – ERCNT[2:0] Pipe Error Counter
These bits define the number of errors detected on the pipe.
Bit 4 – CRC16ER CRC16 ERROR
This bit defines the CRC16 Error Status.
This bit is set when a CRC 16 error has been detected during a IN transactions.
Value
Description
0
No CRC 16 Error detected.
1
A CRC 16 error has been detected.
Bit 3 – TOUTER TIME OUT ERROR
This bit defines the Time Out Error Status.
This bit is set when a Time Out error has been detected during a USB transaction.
Value
Description
0
No Time Out Error detected.
1
A Time Out error has been detected.
Bit 2 – PIDER PID ERROR
This bit defines the PID Error Status.
This bit is set when a PID error has been detected during a USB transaction.
Value
Description
0
No PID Error detected.
1
A PID error has been detected.
Bit 1 – DAPIDER Data PID ERROR
This bit defines the PID Error Status.
This bit is set when a Data PID error has been detected during a USB transaction.
Value
Description
0
No Data PID Error detected.
1
A Data PID error has been detected.
Bit 0 – DTGLER Data Toggle Error
This bit defines the Data Toggle Error Status.
This bit is set when a Data Toggle Error has been detected.
Value
Description
0
No Data Toggle Error.
1
Data Toggle Error detected.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.
33.1
ADC – Analog-to-Digital Converter
Overview
The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has 12-bit resolution,
and is capable of converting up to 350ksps. The input selection is flexible, and both differential and single-ended
measurements can be performed. An optional gain stage is available to increase the dynamic range. In addition,
several internal signal inputs are available. The ADC can provide both signed and unsigned results.
ADC measurements can be started by either application software or an incoming event from another peripheral in the
device. ADC measurements can be started with predictable timing, and without software intervention.
Both internal and external reference voltages can be used.
An integrated temperature sensor is available for use with the ADC. The bandgap voltage as well as the scaled I/O
and core voltages can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user-defined thresholds, with minimum software
intervention required.
The ADC may be configured for 8-, 10- or 12-bit results, reducing the conversion time. ADC conversion results
are provided left- or right-adjusted, which eases calculation when the result is represented as a signed value. It is
possible to use DMA to move ADC results directly to memory or peripherals when conversions are done.
33.2
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-, 10- or 12-bit resolution
Up to 350,000 samples per second (350ksps)
Differential and single-ended inputs
– Up to 32 analog input
– 25 positive and 10 negative, including internal and external
Five internal inputs
– Bandgap
– Temperature sensor
– DAC
– Scaled core supply
– Scaled I/O supply
1/2x to 16x gain
Single, continuous and pin-scan conversion options
Windowing monitor with selectable channel
Conversion range:
– Vref [1v to VDDANA - 0.6V]
– ADCx * GAIN [0V to -Vref ]
Built-in internal reference and external reference options
– Four bits for reference selection
Event-triggered conversion for accurate timing (one event input)
Optional DMA transfer of conversion result
Hardware gain and offset compensation
Averaging and oversampling with decimation to support, up to 16-bit result
Selectable sampling time
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.3
Block Diagram
Figure 33-1. ADC Block Diagram
CTRLA
WINCTRL
AVGCTRL
WINLT
SAMPCTRL
WINUT
EVCTRL
OFFSETCORR
SWTRIG
GAINCORR
INPUTCTRL
ADC0
...
ADCn
INT.SIG
ADC
POST
PROCESSING
RESULT
ADC0
...
ADCn
INT.SIG
INT1V
CTRLB
INTVCC0/1
VREFA
VREFB
PRESCALER
REFCTRL
Note: INT1V is the buffered internal reference of 1.0V, derived from the internal 1.1V bandgap reference.
33.4
Signal Description
Signal Name
Type
Description
VREFA
Analog input
External reference voltage A
VREFB
Analog input
External reference voltage B
ADC[19..0](1)
Analog input
Analog input channels
Note: Refer to Configuration Summary for details on exact number of analog input channels.
Note: Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can
be mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
2. Configuration Summary
33.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.5.1
I/O Lines
Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT).
Related Links
23. PORT - I/O Pin Controller
33.5.2
Power Management
The ADC will continue to operate in any Sleep mode where the selected source clock is running. The ADC’s
interrupts, except the OVERRUN interrupt, can be used to wake up the device from sleep modes. Events connected
to the event system can trigger other operations in the system without exiting sleep modes.
Related Links
16. PM – Power Manager
33.5.3
Clocks
The ADC bus clock (CLK_APB_ADCx) can be enabled in the Main Clock, which also defines the default state.
The ADC requires a generic clock (GCLK_ADC). This clock must be configured and enabled in the Generic Clock
Controller (GCLK) before using the ADC.
A generic clock is asynchronous to the bus clock. Due to this asynchronicity, writes to certain registers will require
synchronization between the clock domains. Refer to Synchronization for further details.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
33.5.4
DMA
The DMA request line is connected to the DMA Controller (DMAC). Using the ADC DMA requests requires the DMA
Controller to be configured first.
Related Links
20. DMAC – Direct Memory Access Controller
33.5.5
Interrupts
The interrupt request line is connected to the interrupt controller. Using the ADC interrupt requires the interrupt
controller to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
33.5.6
Events
The events are connected to the Event System.
Related Links
24. EVSYS – Event System
33.5.7
Debug Operation
When the CPU is halted in debug mode the ADC will halt normal operation. The ADC can be forced to continue
operation during debugging.
33.5.8
Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following register:
•
Interrupt Flag Status and Clear (INTFLAG) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
PAC write-protection does not apply to accesses through an external debugger.
Related Links
11.6 Peripheral Access Controller (PAC)
33.5.9
Analog Connections
I/O-pins AIN0 to AIN19 as well as the VREFA/VREFB reference voltage pin are analog inputs to the ADC.
33.5.10 Calibration
The BIAS and LINEARITY calibration values from the production test must be loaded from the NVM Software
Calibration Area into the ADC Calibration register (CALIB) by software to achieve specified accuracy.
Related Links
10.3.2 NVM Software Calibration Area Mapping
33.6
Functional Description
33.6.1
Principle of Operation
By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order to reduce
the conversion time.
The ADC has an oversampling with decimation option that can extend the resolution to 16 bits. The input values can
be either internal (e.g., internal temperature sensor) or external (connected I/O pins). The user can also configure
whether the conversion should be single-ended or differential.
33.6.2
Basic Operation
33.6.2.1 Initialization
Before enabling the ADC, the asynchronous clock source must be selected and enabled, and the ADC reference
must be configured. The first conversion after the reference is changed must not be used. All other configuration
registers must be stable during the conversion. The source for GCLK_ADC is selected and enabled in the System
Controller (SYSCTRL). Refer to SYSCTRL – System Controller for more details.
When GCLK_ADC is enabled, the ADC can be enabled by writing a one to the Enable bit in the Control Register A
(CTRLA.ENABLE).
Related Links
17. SYSCTRL – System Controller
33.6.2.2 Enabling, Disabling and Reset
The ADC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The ADC is disabled
by writing CTRLA.ENABLE=0. The ADC is reset by writing a '1' to the Software Reset bit in the Control A register
(CTRLA.SWRST). All registers in the ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be
disabled.
The ADC must be disabled before it is reset.
33.6.2.3 Operation
In the most basic configuration, the ADC samples values from the configured internal or external sources
(INPUTCTRL register). The rate of the conversion depends on the combination of the GCLK_ADCx frequency and
the clock prescaler.
To convert analog values to digital values, the ADC needs to be initialized first, as described in 33.6.2.1 Initialization.
Data conversion can be started either manually by setting the Start bit in the Software Trigger register
(SWTRIG.START=1), or automatically by configuring an automatic trigger to initiate the conversions. A free-running
mode can be used to continuously convert an input channel. When using free-running mode the first conversion must
be started, while subsequent conversions will start automatically at the end of previous conversions.
The automatic trigger can be configured to trigger on many different conditions.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
The result of the conversion is stored in the Result register (RESULT) overwriting the result from the previous
conversion.
To avoid data loss if more than one channel is enabled, the conversion result must be read as soon as it is available
(INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the OVERRUN bit in the
Interrupt Flag Status and Clear register (INTFLAG.OVERRUN). When the RESRDY interrupt flag is set, the new
result has been synchronized to the RESULT register.
To enable one of the available interrupts sources, the corresponding bit in the Interrupt Enable Set register
(INTENSET) must be written to '1'.
Prescaler
The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower clock rates.
Refer to CTRLB for additional information on prescaler settings.
Figure 33-2. ADC Prescaler
DIV512
DIV256
DIV128
DIV64
DIV32
DIV16
9-BIT PRESCALER
DIV8
GCLK_ADC
DIV4
33.6.3
CTRLB.PRESCALER[2:0]
CLK_ADC
The propagation delay of an ADC measurement depends on the selected mode and is given as follows:
• Single-shot mode:
•
PropagationDelay =
Free-running mode:
PropagationDelay =
Table 33-1. Delay Gain
+ DelayGain
1 + Resolution
2
fCLK_ADC
Resolution
+ DelayGain
2
fCLK_ADC
Delay Gain (in CLK_ADC Period)
INTPUTCTRL.GAIN[3:0]
Name
Free-running mode
Single-shot mode
Differential mode
Single-Ended
mode
Differential mode
Single-Ended
mode
1X
0x0
0
0
0
1
2X
0x1
0
1
0.5
1.5
4X
0x2
1
1
1
2
8X
0x3
1
2
1.5
2.5
16X
0x4
2
2
2
3
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
...........continued
Delay Gain (in CLK_ADC Period)
INTPUTCTRL.GAIN[3:0]
Name
33.6.4
Free-running mode
Single-shot mode
Differential mode
Single-Ended
mode
Differential mode
Single-Ended
mode
Reserved
0x5 ... 0xE
Reserved
Reserved
Reserved
Reserved
DIV2
0xF
0
1
0.5
1.5
ADC Resolution
The ADC supports 8-bit, 10-bit or 12-bit resolution. Resolution can be changed by writing the Resolution bit group in
the Control B register (CTRLB.RESSEL). By default, the ADC resolution is set to 12 bits.
33.6.5
Differential and Single-Ended Conversions
The ADC has two conversion options: differential and single-ended:
• If the positive input may go below the negative input, the differential mode should be used in order to get
correct results.
• If the positive input is always positive, the single-ended conversion should be used in order to have full 12-bit
resolution in the conversion.
The negative input must be connected to ground. This ground could be the internal GND, IOGND or an external
ground connected to a pin. Refer to the Control B (CTRLB) register for selection details.
If the positive input may go below the negative input, creating some negative results, the differential mode should
be used in order to get correct results. The differential mode is enabled by setting DIFFMODE bit in the Control B
register (CTRLB.DIFFMODE). Both conversion types could be run in single mode or in free-running mode. When the
free-running mode is selected, an ADC input will continuously sample the input and performs a new conversion. The
INTFLAG.RESRDY bit will be set at the end of each conversion.
Related Links
33.8.5 CTRLB
33.6.5.1 Conversion Timing
The following figure shows the ADC timing for one single conversion. A conversion starts after the software or event
start are synchronized with the GCLK_ADC clock. The input channel is sampled in the first half CLK_ADC period.
Figure 33-3. ADC Timing for One Conversion in Differential Mode without Gain
1
2
3
4
5
6
7
8
CLK_ ADC
START
SAMPLE
INT
Converting Bit
MS B
10
9
8
7
6
5
4
3
2
1
LS B
The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control
register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
Figure 33-4. ADC Timing for One Conversion in Differential Mode without Gain, but with Increased Sampling
Time
1
2
3
4
5
6
7
8
9
10
11
CLK_ ADC
START
SAMPLE
INT
Converting Bit
MS B
10
9
8
7
6
5
4
3
2
1
LS B
Figure 33-5. ADC Timing for Free Running in Differential Mode without Gain
2
1
3
4
5
6
7
9
8
10
11
12
13
6
4
2
0
14
15
16
8
6
CLK_ ADC
START
SAMPLE
INT
Converting Bit
11
10
9
8
7
6
5
4
3
2
1
0
11
10
9
8
7
5
3
1
11
10
9
7
5
Figure 33-6. ADC Timing for One Conversion in Single-Ended Mode without Gain
1
2
3
4
5
6
7
8
9
10
11
CLK_ADC
START
SAMPLE
AMPLIFY
INT
Converting Bit
MS B
10
9
8
7
6
5
4
3
2
1
LS B
Figure 33-7. ADC Timing for Free Running in Single-Ended Mode without Gain
2
1
3
4
5
6
7
9
8
10
11
12
13
14
9
7
5
3
1
15
16
CLK_ADC
START
SAMPLE
AMPLIFY
INT
Converting Bit
11
10
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9
8
7
6
5
4
3
2
1
0
11
10
Complete Datasheet
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6
4
2
0
11
10
DS40001882H-page 786
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.6.6
Accumulation
The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is
specified by the Number of Samples to be Collected field in the Average Control register (AVGCTRL.SAMPLENUM).
When accumulating more than 16 samples, the result will be too large to match the 16-bit RESULT register size. To
avoid overflow, the result is right shifted automatically to fit within the available register size. The number of automatic
right shifts is specified in the table below.
Note: To perform the accumulation of two or more samples, the Conversion Result Resolution field in the Control B
register (CTRLB.RESSEL) must be set.
Table 33-2. Accumulation
33.6.7
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result Precision
Number of
Automatic
Right Shifts
Final Result
Precision
Automatic
Division
Factor
1
0x0
12 bits
0
12 bits
0
2
0x1
13 bits
0
13 bits
0
4
0x2
14 bits
0
14 bits
0
8
0x3
15 bits
0
15 bits
0
16
0x4
16 bits
0
16 bits
0
32
0x5
17 bits
1
16 bits
2
64
0x6
18 bits
2
16 bits
4
128
0x7
19 bits
3
16 bits
8
256
0x8
20 bits
4
16 bits
16
512
0x9
21 bits
5
16 bits
32
1024
0xA
22 bits
6
16 bits
64
Reserved
0xB - 0xF
12 bits
12 bits
0
Averaging
Averaging is a feature that increases the sample accuracy, at the cost of a reduced sampling rate. This feature is
suitable when operating in noisy conditions.
Averaging is done by accumulating m samples, as described in 33.6.6 Accumulation, and dividing the result by m.
The averaged result is available in the RESULT register. The number of samples to be accumulated is specified by
writing to AVGCTRL.SAMPLENUM.
The division is obtained by a combination of the automatic right shift described above, and an additional right shift
that must be specified by writing to the Adjusting Result/Division Coefficient field in AVGCTRL (AVGCTRL.ADJRES).
Note: To perform the averaging of two or more samples, the Conversion Result Resolution field in the Control B
register (CTRLB.RESSEL) must be set to '1'.
Averaging AVGCTRL.SAMPLENUM samples will reduce the un-averaged sampling rate by a factor
1
.
AVGCTRL.SAMPLENUM
When the averaged result is available, the INTFLAG.RESRDY bit will be set.
Table 33-3. Averaging
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result
Precision
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.ADJRES
1
0x0
12 bits
0
1
0x0
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Total
Number of
Right
Shifts
Final Result
Precision
Automatic
Division
Factor
12 bits
0
DS40001882H-page 787
SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
...........continued
33.6.8
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result
Precision
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.ADJRES
Total
Number of
Right
Shifts
Final Result
Precision
Automatic
Division
Factor
2
0x1
13
0
2
0x1
1
12 bits
0
4
0x2
14
0
4
0x2
2
12 bits
0
8
0x3
15
0
8
0x3
3
12 bits
0
16
0x4
16
0
16
0x4
4
12 bits
0
32
0x5
17
1
16
0x4
5
12 bits
2
64
0x6
18
2
16
0x4
6
12 bits
4
128
0x7
19
3
16
0x4
7
12 bits
8
256
0x8
20
4
16
0x4
8
12 bits
16
512
0x9
21
5
16
0x4
9
12 bits
32
1024
0xA
22
6
16
0x4
10
12 bits
64
Reserved
0xB-0xF
12 bits
0
0x0
Oversampling and Decimation
By using oversampling and decimation, the ADC resolution can be increased from 12 bits up to 16 bits, for the cost of
reduced effective sampling rate.
To increase the resolution by n bits, 4n samples must be accumulated. The result must then be right-shifted by n bits.
This right-shift is a combination of the automatic right-shift and the value written to AVGCTRL.ADJRES. To obtain the
correct resolution, the ADJRES must be configured as described in the table below. This method will result in n bit
extra LSB resolution.
Table 33-4. Configuration Required for Oversampling and Decimation
33.6.9
Result
Resolution
Number of
Samples to
Average
AVGCTRL.SAMPLENUM[3:0]
Number of
Automatic
Right Shifts
AVGCTRL.ADJRES[2:0]
13 bits
41 = 4
0x2
0
0x1
14 bits
42 = 16
0x4
0
0x2
15 bits
43 = 64
0x6
2
0x1
16 bits
44
0x8
4
0x0
= 256
Window Monitor
The window monitor feature allows the conversion result in the RESULT register to be compared to predefined
threshold values. The window mode is selected by setting the Window Monitor Mode bits in the Window Monitor
Control register (WINCTRL.WINMODE[2:0]). Threshold values must be written in the Window Monitor Lower
Threshold register (WINLT) and Window Monitor Upper Threshold register (WINUT).
If differential input is selected, the WINLT and WINUT are evaluated as signed values. Otherwise they are evaluated
as unsigned values. The significant WINLT and WINUT bits are given by the precision selected in the Conversion
Result Resolution bit group in the Control B register (CTRLB.RESSEL). This means that e.g. in 8-bit mode, only the
eight lower bits will be considered. In addition, in differential mode, the eighth bit will be considered as the sign bit,
even if the ninth bit is zero.
The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor condition.
33.6.10 Offset and Gain Correction
Inherent gain and offset errors affect the absolute accuracy of the ADC.
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ADC – Analog-to-Digital Converter
The offset error is defined as the deviation of the actual ADC transfer function from an ideal straight line at zero
input voltage. The offset error cancellation is handled by the Offset Correction register (OFFSETCORR). The offset
correction value is subtracted from the converted data before writing to the Result register (RESULT).
The gain error is defined as the deviation of the last output step’s midpoint from the ideal straight line, after
compensating for offset error. The gain error cancellation is handled by the Gain Correction register (GAINCORR).
To correct these two errors, the Digital Correction Logic Enabled bit in the Control B register (CTRLB.CORREN) must
be set.
Offset and gain error compensation results are both calculated according to:
Result = Conversion value+ − OFFSETCORR ⋅ GAINCORR
The correction will introduce a latency of 13 CLK_ADC clock cycles. In Free-running mode this latency is introduced
on the first conversion only because the duration is always less than the propagation delay. In Single Conversion
mode this latency is introduced for each conversion.
Figure 33-8. ADC Timing Correction Enabled
START
CONV0
CONV1
CORR0
CONV2
CORR1
CONV3
CORR2
CORR3
33.6.11 DMA Operation
The ADC generates the following DMA request:
•
Result Conversion Ready (RESRDY): the request is set when a conversion result is available and cleared
when the RESULT register is read. When the averaging operation is enabled, the DMA request is set when the
averaging is completed and result is available.
33.6.12 Interrupts
The ADC has the following interrupt sources:
• Result Conversion Ready: RESRDY
• Window Monitor: WINMON
• Overrun: OVERRUN
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to
the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled, or the ADC is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or
one common interrupt request line for all the interrupt sources. This is device dependent.
Refer to Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to determine which
interrupt condition is present.
Related Links
11.2 Nested Vector Interrupt Controller
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.6.13 Events
The ADC can generate the following output events:
• Result Ready (RESRDY): Generated when the conversion is complete and the result is available.
• Window Monitor (WINMON): Generated when the window monitor condition match.
Setting an Event Output bit in the Event Control Register (EVCTRL.xxEO=1) enables the corresponding output event.
Clearing this bit disables the corresponding output event. Refer to the Event System chapter for details on configuring
the event system.
The peripheral can take the following actions on an input event:
• Start conversion (START): Start a conversion.
• Conversion flush (FLUSH): Flush the conversion.
Setting an Event Input bit in the Event Control register (EVCTRL.xxEI=1) enables the corresponding action on input
event. Clearing this bit disables the corresponding action on input event.
Note: If several events are connected to the ADC, the enabled action will be taken on any of the incoming events.
The events must be correctly routed in the Event System.
Related Links
24. EVSYS – Event System
33.6.14 Sleep Mode Operation
The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the ADC
during standby sleep mode. When CTRLA.RUNSTDBY=0, the ADC is disabled during sleep, but maintains its
current configuration. When CTRLA.RUNSTDBY=1, the ADC continues to operate during sleep. Note that when
CTRLA.RUNSTDBY=0, the analog blocks are powered off for the lowest power consumption. This necessitates a
start-up time delay when the system returns from sleep.
When CTRLA.RUNSTDBY=1, any enabled ADC interrupt source can wake up the CPU, except the OVERRUN
interrupt.. While the CPU is sleeping, ADC conversion can only be triggered by events.
33.6.15 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY=1, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits are synchronized when written:
•
•
Software Reset bit in the Control A register (CTRLA.SWRST)
Enable bit in the Control A register (CTRLA.ENABLE)
The following registers are synchronized when written:
•
•
•
•
•
Control B (CTRLB)
Software Trigger (SWTRIG)
Window Monitor Control (WINCTRL)
Input Control (INPUTCTRL)
Window Upper/Lower Threshold (WINUT/WINLT)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
The following registers are synchronized when read:
•
•
Software Trigger (SWTRIG)
Input Control (INPUTCTRL)
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ADC – Analog-to-Digital Converter
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
Related Links
14.3 Register Synchronization
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ADC – Analog-to-Digital Converter
33.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
CTRLA
REFCTRL
AVGCTRL
SAMPCTRL
0x04
CTRLB
7:0
7:0
7:0
7:0
7:0
15:8
0x06
...
0x07
0x08
0x09
...
0x0B
0x0C
0x0D
...
0x0F
6
5
4
3
2
1
0
RUNSTDBY
ENABLE
SWRST
REFSEL[3:0]
SAMPLENUM[3:0]
SAMPLEN[5:0]
CORREN
FREERUN
LEFTADJ
DIFFMODE
PRESCALER[2:0]
REFCOMP
ADJRES[2:0]
RESSEL[1:0]
Reserved
WINCTRL
7:0
WINMODE[2:0]
7:0
START
Reserved
SWTRIG
FLUSH
Reserved
0x10
INPUTCTRL
0x14
0x15
0x16
0x17
0x18
0x19
EVCTRL
Reserved
INTENCLR
INTENSET
INTFLAG
STATUS
0x1A
RESULT
0x1C
WINLT
0x1E
...
0x1F
Reserved
0x20
WINUT
0x22
...
0x23
Reserved
0x24
GAINCORR
0x26
OFFSETCORR
0x28
CALIB
0x2A
DBGCTRL
33.8
7
7:0
15:8
23:16
31:24
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
MUXPOS[4:0]
MUXNEG[4:0]
INPUTSCAN[3:0]
GAIN[3:0]
SYNCEI
INPUTOFFSET[3:0]
WINMONEO RESRDYEO
SYNCRDY
SYNCRDY
SYNCRDY
WINMON
WINMON
WINMON
OVERRUN
OVERRUN
OVERRUN
STARTEI
RESRDY
RESRDY
RESRDY
SYNCBUSY
RESULT[7:0]
RESULT[15:8]
WINLT[7:0]
WINLT[15:8]
7:0
15:8
WINUT[7:0]
WINUT[15:8]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
GAINCORR[7:0]
GAINCORR[11:8]
OFFSETCORR[7:0]
OFFSETCORR[11:8]
LINEARITY_CAL[7:0]
BIAS_CAL[2:0]
DBGRUN
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted
by the Write-Protected property in each individual register description.
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ADC – Analog-to-Digital Converter
Some registers require synchronization when read and/or written. Synchronization is denoted by the WriteSynchronized or the Read-Synchronized property in each individual register description.
Some registers are enable-protected, meaning they can be written only when the ADC is disabled. Enable-protection
is denoted by the Enable-Protected property in each individual register description.
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ADC – Analog-to-Digital Converter
33.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00
Write-Protected
7
6
5
4
3
Access
Reset
2
RUNSTDBY
R/W
0
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 2 – RUNSTDBY Run in Standby
This bit indicates whether the ADC will continue running in standby sleep mode or not:
Value
Description
0
The ADC is halted during standby sleep mode.
1
The ADC continues normal operation during standby sleep mode.
Bit 1 – ENABLE Enable
Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
Value
Description
0
The ADC is disabled.
1
The ADC is enabled.
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
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ADC – Analog-to-Digital Converter
33.8.2
Reference Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
REFCTRL
0x01
0x00
Write-Protected
7
REFCOMP
R/W
0
6
5
4
3
R/W
0
2
1
REFSEL[3:0]
R/W
R/W
0
0
0
R/W
0
Bit 7 – REFCOMP Reference Buffer Offset Compensation Enable
The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will
decrease the input impedance and thus increase the start-up time of the reference.
Value
Description
0
Reference buffer offset compensation is disabled.
1
Reference buffer offset compensation is enabled.
Bits 3:0 – REFSEL[3:0] Reference Selection
These bits select the reference for the ADC.
Table 33-5. Reference Selection
REFSEL[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5-0xF
INT1V
INTVCC0
INTVCC1
VREFA
VREFB
1.0V voltage reference
1/1.48 VDDANA
1/2 VDDANA (only for VDDANA > 2.0V)
External reference
External reference
Reserved
Note: INT1V is the buffered internal reference of 1.0V, derived from the internal 1.1V bandgap reference.
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ADC – Analog-to-Digital Converter
33.8.3
Average Control
Name:
Offset:
Reset:
Property:
Bit
AVGCTRL
0x02
0x00
Write-Protected
7
Access
Reset
6
R/W
0
5
ADJRES[2:0]
R/W
0
4
3
R/W
0
R/W
0
2
1
SAMPLENUM[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 6:4 – ADJRES[2:0] Adjusting Result / Division Coefficient
These bits define the division coefficient in 2n steps.
Bits 3:0 – SAMPLENUM[3:0] Number of Samples to be Collected
These bits define how many samples should be added together.The result will be available in the Result register
(RESULT). Note: if the result width increases, CTRLB.RESSEL must be changed.
SAMPLENUM[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB-0xF
1
2
4
8
16
32
64
128
256
512
1024
1 sample
2 samples
4 samples
8 samples
16 samples
32 samples
64 samples
128 samples
256 samples
512 samples
1024 samples
Reserved
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ADC – Analog-to-Digital Converter
33.8.4
Sampling Time Control
Name:
Offset:
Reset:
Property:
Bit
7
SAMPCTRL
0x03
0x00
Write-Protected
6
Access
Reset
5
4
R/W
0
R/W
0
3
2
SAMPLEN[5:0]
R/W
R/W
0
0
1
0
R/W
0
R/W
0
Bits 5:0 – SAMPLEN[5:0] Sampling Time Length
These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus
controlling the ADC input impedance. Sampling time is set according to the equation:
CLKADC
Sampling time = SAMPLEN+1 ⋅
2
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ADC – Analog-to-Digital Converter
33.8.5
Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x04
0x0000
Write-Protected, Write-Synchronized
15
14
13
12
11
Access
Reset
Bit
7
6
Access
Reset
5
4
RESSEL[1:0]
R/W
R/W
0
0
3
CORREN
R/W
0
10
R/W
0
9
PRESCALER[2:0]
R/W
0
8
R/W
0
2
FREERUN
R/W
0
1
LEFTADJ
R/W
0
0
DIFFMODE
R/W
0
Bits 10:8 – PRESCALER[2:0] Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock.
PRESCALER[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
DIV256
DIV512
Peripheral clock divided by 4
Peripheral clock divided by 8
Peripheral clock divided by 16
Peripheral clock divided by 32
Peripheral clock divided by 64
Peripheral clock divided by 128
Peripheral clock divided by 256
Peripheral clock divided by 512
Bits 5:4 – RESSEL[1:0] Conversion Result Resolution
These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution.
RESSEL[1:0]
Name
Description
0x0
0x1
0x2
0x3
12BIT
16BIT
10BIT
8BIT
12-bit result
For averaging mode output
10-bit result
8-bit result
Bit 3 – CORREN Digital Correction Logic Enabled
Value
Description
0
Disable the digital result correction.
1
Enable the digital result correction. The ADC conversion result in the RESULT register is then
corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers.
Conversion time will be increased by X cycles according to the value in the Offset Correction Value bit
group in the Offset Correction register.
Bit 2 – FREERUN Free Running Mode
Value
Description
0
The ADC run is single conversion mode.
1
The ADC is in free running mode and a new conversion will be initiated when a previous conversion
completes.
Bit 1 – LEFTADJ Left-Adjusted Result
Value
Description
0
The ADC conversion result is right-adjusted in the RESULT register.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
Value
1
Description
The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result
will be present in the upper part of the result register. Writing this bit to zero (default) will right-adjust
the value in the RESULT register.
Bit 0 – DIFFMODE Differential Mode
Value
Description
0
The ADC is running in singled-ended mode.
1
The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS
and MUXNEG inputs will be converted by the ADC.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.6
Window Monitor Control
Name:
Offset:
Reset:
Property:
Bit
WINCTRL
0x08
0x00
Write-Protected, Write-Synchronized
7
6
5
4
3
Access
Reset
2
R/W
0
1
WINMODE[2:0]
R/W
0
0
R/W
0
Bits 2:0 – WINMODE[2:0] Window Monitor Mode
These bits enable and define the window monitor mode.
WINMODE[2:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5-0x7
DISABLE
MODE1
MODE2
MODE3
MODE4
No window mode (default)
Mode 1: RESULT > WINLT
Mode 2: RESULT < WINUT
Mode 3: WINLT < RESULT < WINUT
Mode 4: !(WINLT < RESULT < WINUT)
Reserved
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.7
Software Trigger
Name:
Offset:
Reset:
Property:
Bit
SWTRIG
0x0C
0x00
Write-Protected, Write-Synchronized
7
6
5
4
3
Access
Reset
2
1
START
R/W
0
0
FLUSH
R/W
0
Bit 1 – START ADC Start Conversion
Writing this bit to zero will have no effect.
Value
Description
0
The ADC will not start a conversion.
1
The ADC will start a conversion. The bit is cleared by hardware when the conversion has started.
Setting this bit when it is already set has no effect.
Bit 0 – FLUSH ADC Conversion Flush
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a new
conversion.
Writing this bit to zero will have no effect.
Value
Description
0
No flush action.
1
"Writing a '1' to this bit will flush the ADC pipeline. A flush will restart the ADC clock on the next
peripheral clock edge, and all conversions in progress will be aborted and lost. This bit will be cleared
after the ADC has been flushed.
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start
a new conversion.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.8
Input Control
Name:
Offset:
Reset:
Property:
Bit
INPUTCTRL
0x10
0x00000000
Write-Protected, Write-Synchronized
31
30
29
28
27
26
25
24
R/W
0
R/W
0
GAIN[3:0]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
23
22
21
INPUTOFFSET[3:0]
R/W
R/W
0
0
R/W
0
15
14
13
Access
Reset
Bit
7
6
Access
Reset
5
20
19
R/W
0
R/W
0
12
11
R/W
0
R/W
0
4
3
R/W
0
R/W
0
R/W
0
18
17
INPUTSCAN[3:0]
R/W
R/W
0
0
10
MUXNEG[4:0]
R/W
0
2
MUXPOS[4:0]
R/W
0
16
R/W
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bits 27:24 – GAIN[3:0] Gain Factor Selection
These bits set the gain factor of the ADC gain stage.
GAIN[3:0]
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5-0xE
0xF
1X
2X
4X
8X
16X
DIV2
1x
2x
4x
8x
16x
Reserved
1/2x
Bits 23:20 – INPUTOFFSET[3:0] Positive Mux Setting Offset
The pin scan is enabled when INPUTSCAN != 0. Writing these bits to a value other than zero causes the first
conversion triggered to be converted using a positive input equal to MUXPOS + INPUTOFFSET. Setting this register
to zero causes the first conversion to use a positive input equal to MUXPOS.
After a conversion, the INPUTOFFSET register will be incremented by one, causing the next conversion to be done
with the positive input equal to MUXPOS + INPUTOFFSET. The sum of MUXPOS and INPUTOFFSET gives the
input that is actually converted.
Bits 19:16 – INPUTSCAN[3:0] Number of Input Channels Included in Scan
This register gives the number of input sources included in the pin scan. The number of input sources included is
INPUTSCAN + 1. The input channels included are in the range from MUXPOS + INPUTOFFSET to MUXPOS +
INPUTOFFSET + INPUTSCAN.
The range of the scan mode must not exceed the number of input channels available on the device.
Bits 12:8 – MUXNEG[4:0] Negative Mux Input Selection
These bits define the Mux selection for the negative ADC input. selections.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08-0x1
7
0x18
0x19
0x1A-0x1
F
Name
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
Description
ADC AIN0 pin
ADC AIN1 pin
ADC AIN2 pin
ADC AIN3 pin
ADC AIN4 pin
ADC AIN5 pin
ADC AIN6 pin
ADC AIN7 pin
Reserved
GND
IOGND
Internal ground
I/O ground
Reserved
Note: 1. Only available in SAM R21G.
Bits 4:0 – MUXPOS[4:0] Positive Mux Input Selection
These bits define the Mux selection for the positive ADC input. The following table shows the possible input
selections. If the internal bandgap voltage channel is selected, then the Sampling Time Length bit group in the
Sampling Control register must be written.
MUXPOS[4:0]
Group configuration
Description
0x00
PIN0
ADC AIN0 pin
0x01
PIN1
ADC AIN1 pin
0x02
PIN2
ADC AIN2 pin
0x03
PIN3
ADC AIN3 pin
0x04
PIN4
ADC AIN4 pin
0x05
PIN5
ADC AIN5 pin
0x06
PIN6
ADC AIN6 pin
0x07
PIN7
ADC AIN7 pin
0x08
PIN8
ADC AIN8 pin
0x09
PIN9
ADC AIN9 pin
0x0A
PIN10
ADC AIN10 pin
0x0B
PIN11
ADC AIN11 pin
0x0C
PIN12
ADC AIN12 pin
0x0D
PIN13
ADC AIN13 pin
0x0E
PIN14
ADC AIN14 pin
0x0F
PIN15
ADC AIN15 pin
0x10
PIN16
ADC AIN16 pin
0x11
PIN17
ADC AIN17 pin
0x12
PIN18
ADC AIN18 pin
0x13
PIN19
ADC AIN19 pin
0x14-0x17
Reserved
0x18
TEMP
Temperature reference
0x19
BANDGAP
Bandgap voltage
0x1A
SCALEDCOREVCC
1/4 scaled core supply
0x1B
SCALEDIOVCC
1/4 scaled I/O supply
0x1C
DAC
DAC output (1)
0x1D-0x1F
Reserved
Note:
1. When using the internal DAC connection to the positive input of the ADC, the DAC CTRLB.EOEN must be
set.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.9
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x14
0x00
Write-Protected
7
6
Access
Reset
5
WINMONEO
R/W
0
4
RESRDYEO
R/W
0
3
2
1
SYNCEI
R/W
0
0
STARTEI
R/W
0
Bit 5 – WINMONEO Window Monitor Event Out
This bit indicates whether the Window Monitor event output is enabled or not and an output event will be generated
when the window monitor detects something.
Value
Description
0
Window Monitor event output is disabled and an event will not be generated.
1
Window Monitor event output is enabled and an event will be generated.
Bit 4 – RESRDYEO Result Ready Event Out
This bit indicates whether the Result Ready event output is enabled or not and an output event will be generated
when the conversion result is available.
Value
Description
0
Result Ready event output is disabled and an event will not be generated.
1
Result Ready event output is enabled and an event will be generated.
Bit 1 – SYNCEI Synchronization Event In
Value
Description
0
A flush and new conversion will not be triggered on any incoming event.
1
A flush and new conversion will be triggered on any incoming event.
Bit 0 – STARTEI Start Conversion Event In
Value
Description
0
A new conversion will not be triggered on any incoming event.
1
A new conversion will be triggered on any incoming event.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.10 Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
Bit
INTENCLR
0x16
0x00
Write-Protected
7
6
Access
Reset
5
4
3
SYNCRDY
R/W
0
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding interrupt
request.
Value
Description
0
The Synchronization Ready interrupt is disabled.
1
The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the
Synchronization Ready interrupt flag is set.
Bit 2 – WINMON Window Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The window monitor interrupt is disabled.
1
The window monitor interrupt is enabled, and an interrupt request will be generated when the Window
Monitor interrupt flag is set.
Bit 1 – OVERRUN Overrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt
flag is set.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result
Ready interrupt flag is set.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.11 Interrupt Enable Set
Name:
Offset:
Reset:
Property:
Bit
INTENSET
0x17
0x00
Write-Protected
7
6
Access
Reset
5
4
3
SYNCRDY
R/W
0
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization
Ready interrupt.
Value
Description
0
The Synchronization Ready interrupt is disabled.
1
The Synchronization Ready interrupt is enabled.
Bit 2 – WINMON Window Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Window Monitor Interrupt bit and enable the Window Monitor interrupt.
Value
Description
0
The Window Monitor interrupt is disabled.
1
The Window Monitor interrupt is enabled.
Bit 1 – OVERRUN Overrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Interrupt bit and enable the Overrun interrupt.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Result Ready Interrupt bit and enable the Result Ready interrupt.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.12 Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x18
0x00
-
7
6
Access
Reset
5
4
3
SYNCRDY
R/W
0
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 3 – SYNCRDY Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a one-to-zero transition of the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY), except when caused by an enable or software reset, and will generate an interrupt request if
INTENCLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
Bit 2 – WINMON Window Monitor
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an interrupt
request will be generated if INTENCLR/SET.WINMON is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Window Monitor interrupt flag.
Bit 1 – OVERRUN Overrun
This flag is cleared by writing a one to the flag.
This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt request will be
generated if INTENCLR/SET.OVERRUN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overrun interrupt flag.
Bit 0 – RESRDY Result Ready
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/SET.RESRDY
is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Result Ready interrupt flag.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.13 Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
STATUS
0x19
0x00
-
7
SYNCBUSY
R
0
6
5
4
3
2
1
0
Bit 7 – SYNCBUSY Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.14 Result
Name:
Offset:
Reset:
Property:
RESULT
0x1A
0x0000
Read-Synchronized
Bit
15
14
13
10
9
8
R
0
12
11
RESULT[15:8]
R
R
0
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
RESULT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – RESULT[15:0] Result Conversion Value
These bits will hold up to a 16-bit ADC result, depending on the configuration.
In single conversion mode without averaging, the ADC conversion will produce a 12-bit result, which can be left- or
right-shifted, depending on the setting of CTRLB.LEFTADJ.
If the result is left-adjusted (CTRLB.LEFTADJ), the high byte of the result will be in bit position [15:8], while the
remaining 4 bits of the result will be placed in bit locations [7:4]. This can be used only if an 8-bit result is required;
i.e., one can read only the high byte of the entire 16-bit register.
If the result is not left-adjusted (CTRLB.LEFTADJ) and no oversampling is used, the result will be available in bit
locations [11:0], and the result is then 12 bits long.
If oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the Average
Control register (AVGCTRL).
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.15 Window Monitor Lower Threshold
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
WINLT
0x1C
0x0000
Write-Protected, Write-Synchronized
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINLT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINLT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WINLT[15:0] Window Lower Threshold
If the window monitor is enabled, these bits define the lower threshold value.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.16 Window Monitor Upper Threshold
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
WINUT
0x20
0x0000
Write-Protected, Write-Synchronized
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINUT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WINUT[15:0] Window Upper Threshold
If the window monitor is enabled, these bits define the upper threshold value.
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SAM D21/DA1 Family
ADC – Analog-to-Digital Converter
33.8.17 Gain Correction
Name:
Offset:
Reset:
Property:
Bit
15
GAINCORR
0x24
0x0000
Write-Protected
14
13
Access
Reset
Bit
Access
Reset
12
11
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
4
3
GAINCORR[7:0]
R/W
R/W
0
0
10
9
GAINCORR[11:8]
R/W
R/W
0
0
8
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – GAINCORR[11:0] Gain Correction Value
If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for gain error
before being written to the result register. The gain-correction is a fractional value, a 1-bit integer plusan 11-bit
fraction, and therefore 1/2 1.6V, IOL maxI
-
0.1*VDD 0.2*VDD
VOH
Output high-level
voltage
VDD>1.6V, IOH maxII
0.8*VDD
0.9*VDD -
VIH
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
IOL
VDD=1.62V-3V,
PORT.PINCFG.DRVSTR=0
-
-
1
mA
VDD=3V-3.63V,
PORT.PINCFG.DRVSTR=0
-
-
2.5
VDD=1.62V-3V,
PORT.PINCFG.DRVSTR=1
-
-
3
VDD=3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
-
10
VDD=1.62V-3V,
PORT.PINCFG.DRVSTR=0
-
-
0.70
VDD=3V-3.63V,
PORT.PINCFG.DRVSTR=0
-
-
2
VDD=1.62V-3V,
PORT.PINCFG.DRVSTR=1
-
-
2
VDD=3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
-
7
PORT.PINCFG.DRVSTR=0load = 5pF,
VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=1load = 20pF,
VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=0load = 5pF,
VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=1load = 20pF,
VDD = 3.3V
-
-
15
Pull-up resistors disabled
-1
+/-0.015 1
IOH
tRISE
tFALL
ILEAK
Output low-level
current
Output high-level
current
Rise time(1)
Fall time(1)
Input leakage current
ns
ns
μA
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
37.9.2
I2C Pins
Refer to I/O Multiplexing and Considerations to get the list of I2C pins.
Table 37-16. I2C Pins Characteristics in I2C configuration
Symbol Parameter
Condition
Min.
Typ. Max.
VIL
VDD=1.62V-2.7V
-
-
0.25*VDD V
VDD=2.7V-3.63V
-
-
0.3*VDD
VDD=1.62V-2.7V
0.7*VDD
-
-
VDD=2.7V-3.63V
0.55*VDD -
-
0.08*VDD -
-
VDD> 2.0V,
IOL=3mA
-
-
0.4
VDD≤2.0V
, IOL=2mA
-
-
0.2*VDD
VIH
Input low-level voltage
Input high-level voltage
VHYS
Hysteresis of Schmitt trigger inputs
VOL
Output low-level voltage
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Units
DS40001882H-page 875
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Condition
Min.
IOL
VOL =0.4V
Standard, Fast and HS Modes
3
VOL =0.4V
Fast Mode +
20
-
-
VOL =0.6V
6
-
-
-
-
3.4
Output low-level current
fSCL
SCL clock frequency
Typ. Max.
Units
mA
MHz
I2C pins timing characteristics can be found in 37.16.3 SERCOM in I2C Mode Timing.
37.9.3
XOSC Pin
XOSC pins behave as normal pins when used as normal I/Os. Refer to table 37.9.1 Normal I/O Pins.
37.9.4
XOSC32 Pin
XOSC32 pins behave as normal pins when used as normal I/Os. Refer to table 37.9.1 Normal I/O Pins.
37.9.5
External Reset Pin
Reset pin has the same electrical characteristics as normal I/O pins. Refer to table 37.9.1 Normal I/O Pins.
37.10
Injection Current
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 37-17. Injection Current(1)
Symbol
Description
min
max
Unit
Iinj1 (2)
IO pin injection current
-1
+1
mA
(3)
IO pin injection current
-15
+15
mA
Sum of IO pins injection current
-45
+45
mA
Iinj2
Iinjtotal
1.
2.
Injecting current may have an effect on the accuracy of Analog blocks
Conditions for Vpin: Vpin < GND-0.6V or 3.6V VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (Vref/GAIN)
37.11.4.1 Performance with the Averaging Digital Feature
Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of
multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samplesto-be-collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is
available in the Result register (RESULT).
Table 37-29. Averaging Feature (Device Variant A)
Average
Number
Conditions
SNR (dB) SINAD (dB) SFDR (dB) ENOB (bits)
1
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
66.0
65.0
72.8
9.75
67.6
65.8
75.1
10.62
32
69.7
67.1
75.3
10.85
128
70.4
67.5
75.5
10.91
8
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-30. Averaging Feature (Device Variant B,C, D and L)
Average
Number
Conditions
SNR (dB) SINAD (dB) SFDR (dB) ENOB (bits)
1
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
66.0
65.0
72.8
10.5
67.6
65.8
75.1
10.62
32
69.7
67.1
75.3
10.85
128
70.4
67.5
75.5
10.91
8
37.11.4.2 Performance with the hardware offset and gain correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled
by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register
(GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result
register (RESULT).
Table 37-31. Offset and Gain correction feature
Gain Factor Conditions
Offset Error
(mV)
Gain Error
(mV)
Total Unadjusted
Error (LSB)
0.5x
0.25
1.0
2.4
0.20
0.10
1.5
2x
0.15
-0.15
2.7
8x
-0.05
0.05
3.2
16x
0.10
-0.05
6.1
1x
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
37.11.4.3 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order
to achieve maximum accuracy. Seen externally, the ADC input consists of a resistor (RSAMPLE) and a capacitor
(CSAMPLE). In addition, the source resistance (RSOURCE) must be taken into account when calculating the required
sample and hold time. The next figure shows the ADC input channel equivalent circuit.
Figure 37-5. ADC Input
VDDANA/2
Analog Input
AINx
RSOURCE
CSAMPLE
RSAMPLE
VIN
To achieve n bits of accuracy, the CSAMPLE capacitor must be charged at least to a voltage of
VCSAMPLE ≥ VIN × 1 + − 2− n + 1
The minimum sampling time tSAMPLEHOLD for a given RSOURCEcan be found using this formula:
tSAMPLEHOLD ≥ RSAMPLE + RSOURCE × CSAMPLE × n + 1 × ln 2
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
for a 12 bits accuracy: tSAMPLEHOLD ≥ RSAMPLE + RSOURCE × CSAMPLE × 9.02
37.11.5 Digital to Analog Converter (DAC) Characteristics
Table 37-32. Operating Conditions(1)
Symbol
Parameter
VDDANA
AVREF
IDD
Conditions
Min.
Typ.
Max.
Units
Analog supply voltage
-
1.62
-
3.63
V
External reference voltage
-
1.0
-
VDDANA-0.6
V
INT1V(3)
-
-
1
-
V
VDDANA
-
-
VDDANA
-
V
Linear output voltage range
-
0.05
-
VDDANA-0.05
V
Minimum resistive load
-
5
-
-
kΩ
Maximum capacitance load
-
-
-
100
pF
Voltage pump disabled
-
160
230
μA
DC supply current(2)
Notes:
1. These values are based on specifications otherwise noted.
2. These values are based on characterization, and are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 37-33. Clock and Timing(1)
Symbol
Parameter
Conditions
Conversion rate
Cload = 100 pF
Rload > 5 kΩ
Startup time
Min.
Typ.
Max.
Units
Normal mode
-
-
350
ksps
For ΔDATA = +/-1
-
-
1000
VDDNA > 2.6V
-
-
2.85
μs
VDDNA < 2.6V
-
-
10
μs
Note:
1. These values are based on simulation, and are not covered by test limits in production or characterization.
Table 37-34. Accuracy Characteristics(1) (Device Variant A)
Symbol
Parameter
RES
Input resolution
INL
Integral non-linearity
Conditions
Min.
Typ.
Max.
Units
-
-
-
10
Bits
VDD = 1.6V
0.75
1.1
2.5
LSB
VDD = 3.6V
0.6
1.2
1.5
VDD = 1.6V
1.4
2.2
2.5
VDD = 3.6V
0.9
1.4
1.5
VDD = 1.6V
0.75
1.3
1.5
VDD = 3.6V
0.8
1.2
1.5
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol
Parameter
DNL
Differential non-linearity
Conditions
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
Min.
Typ.
Max.
Units
VDD = 1.6V
+/-0.9
+/-1.2
+/-1.5
LSB
VDD = 3.6V
+/-0.9
+/-1.1
+/-1.2
VDD = 1.6V
+/-1.1
+/-1.5
+/-1.7
VDD = 3.6V
+/-1.0
+/-1.1
+/-1.2
VDD = 1.6V
+/-1.1
+/-1.4
+/-1.5
VDD = 3.6V
+/-1.0
+/-1.5
+/-1.6
GE
Gain error
Ext. VREF
+/-1.5
+/-5
+/-10
mV
OE
Offset error
Ext. VREF
+/-2
+/-3
+/-6
mV
Table 37-35. Accuracy Characteristics(1) (Device Variant B,C, D and L)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RES
Input resolution
-
-
-
10
Bits
INL
Integral non-linearity
VREF = Ext 1.0V
VDD = 1.6V
0.7
0.75
2
LSB
VDD = 3.6V
0.6
0.65
1.5
VDD = 1.6V
0.6
0.85
2
VDD = 3.6V
0.5
0.8
1.5
VDD = 1.6V
0.5
0.75
1.5
VDD = 3.6V
0.7
0.8
1.5
VDD = 1.6V
+/-0.3
+/-0.4
+/-1.0
VDD = 3.6V
+/-0.25
+/-0.4
+/-0.75
VDD = 1.6V
+/-0.4
+/-0.55
+/-1.5
VDD = 3.6V
+/-0.2
+/-0.3
+/-0.75
VDD = 1.6V
+/-0.5
+/-0.7
+/-1.5
VDD = 3.6V
+/-0.4
+/-0.7
+/-1.5
VREF = VDDANA
VREF = INT1V
DNL
Differential non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
LSB
GE
Gain error
Ext. VREF
+/-0.5
+/-5
+/-10
mV
OE
Offset error
Ext. VREF
+/-2
+/-1.5
+/-8
mV
Note:
1. All values measured using a conversion rate of 35 ksps.
37.11.6 Analog Comparator Characteristics
Table 37-36. Electrical and Timing (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Positive input voltage range
-
0
-
VDDANA
V
Negative input voltage range
-
0
-
VDDANA
Hysteresis = 0, Fast mode
-15
0.0
+15
mV
Hysteresis = 0, Low-power mode
-25
0.0
+25
mV
Offset
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Hysteresis
Hysteresis = 1, Fast mode
20
50
80
mV
Hysteresis = 1, Low-power mode
15
40
75
mV
Changes for VACM = VDDANA/2
100 mV overdrive, Fast mode
-
60
116
ns
Changes for VACM = VDDANA/2
100 mV overdrive, Low-power mode
-
225
370
ns
Enable to ready delay
Fast mode
-
1
2
μs
Enable to ready delay
Low power mode
-
12
19
μs
INL(3)
-
-1.4
0.75
+1.4
LSB
DNL(3)
-
-0.9
0.25
+0.9
LSB
+0.920
LSB
Propagation delay
tSTARTUP
VSCALE
Startup time
Offset Error (1)(2)
Gain Error
(1)(2)
-
-0.200 0.260
-
-0.89
0.215
0.89
LSB
Min.
Typ.
Max.
Units
V
Table 37-37. Electrical and Timing (Device Variant B,C, D and L)
Symbol
Parameter
Conditions
Positive input voltage range
-
0
-
VDDANA
Negative input voltage range
-
0
-
VDDANA
Offset
Hysteresis = 0, Fast mode
-15
0.0
+15
mV
Hysteresis = 0, Low-power mode
-25
0.0
+25
mV
Hysteresis = 1, Fast mode
20
50
85
mV
Hysteresis = 1, Low-power mode
15
40
75
mV
Changes for VACM = VDDANA/2
100 mV overdrive, Fast mode
-
90
180
ns
Changes for VACM = VDDANA/2
100 mV overdrive, Low-power mode
-
282
520
ns
Enable to ready delay
,Fast mode
-
1
2.6
μs
Enable to ready delay
, Low-power mode
-
14
22
μs
-
-1.4
0.75
+1.4
LSB
-
-0.9
0.25
+0.9
LSB
+0.920
LSB
0.89
LSB
Hysteresis
Propagation delay
tSTARTUP
VSCALE
Startup time
INL(3)
DNL(3)
Offset Error
(1)(2)
Gain Error (1)(2)
-
-0.200 0.260
-
-0.89
0.215
Notes:
1. According to the standard equation V(X) = VLSB*(X+1); VLSB = VDDANA/64.
2. Data computed with the Best Fit method.
3. Data computed using histogram.
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.11.7 Bandgap and Internal 1.0V Reference Characteristics
Table 37-38. Bandgap and Internal 1.0V Reference Characteristics
Symbol
Parameter
BANDGAP Internal 1.1V Bandgap
reference
INT1V
Conditions
Min. Typ. Max. Units
After calibration at T = 25°C,
over [-40℃, +85℃],VDD = 3.3V
1.08
1.1
1.12
V
Over voltage at 25°C
1.09
1.1
1.11
V
1
1.02
V
1
1.01
V
Internal 1.0V reference voltage After calibration at T = 25°C,
0.98
(1)
over voltage and [-40°C, +85°C],VDD = 3.3V
Over voltage at 25°C
0.99
Note:
1. These values are simulation based and are not covered by production test limits.
37.11.8 Temperature Sensor Characteristics
37.11.8.1 Temperature Sensor Characteristics
Table 37-39. Temperature Sensor Characteristics(1) (Device Variant A)
Symbol Parameter
Temperature sensor
output voltage
Conditions
Min. Typ.
T= 25°C, VDDANA = 3.3V
-
0.667 -
V
2.3
2.4
2.5
mV/°C
Temperature sensor
slope
Max. Units
Variation over VDDANA
voltage
VDDANA=1.62V to 3.6V
-1.7 1
3.7
mV/V
Temperature Sensor
accuracy
Using the method described in the
37.11.8.2 Software-based Refinement of the
Actual Temperature
-10
10
°C
-
Table 37-40. Temperature Sensor Characteristics(1) (Device Variant B,C, D and L)
Symbol Parameter
Temperature sensor
output voltage
Conditions
Min. Typ.
T= 25°C, VDDANA = 3.3V
-
Temperature sensor
slope
Max. Units
0.688 -
V
2.06 2.16
2.26 mV/°C
Variation over VDDANA
voltage
VDDANA=1.62V to 3.6V
-0.4 1.4
3
mV/V
Temperature Sensor
accuracy
Using the method described in the
37.11.8.2 Software-based Refinement of the
Actual Temperature
-10
10
°C
-
Note: 1. These values are based on characterization. These values are not covered by test limits in production.
Temperature sensor values are not guaranteed for Automotive parts.
37.11.8.2 Software-based Refinement of the Actual Temperature
The temperature sensor behavior is linear but depends on several parameters such as the internal voltage reference,
which itself depends on the temperature. To take this into account, each device contains a Temperature Log row with
data measured and written during the production tests. These calibration values should be read by software to infer
the most accurate temperature readings possible.
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
This Software Temperature Log row can be read at address 0x00806030
This section specifies the Temperature Log row content and explains how to refine the temperature sensor output
using the values in the Temperature Log row.
37.11.8.2.1 Temperature Log Row
All values in this row were measured in the following conditions:
• VDDIN = VDDIO = VDDANA = 3.3V
• ADC Clock speed = 1MHz
• ADC mode: Free running mode, ADC averaging mode with 4 averaged samples
• ADC voltage reference = 1.0V internal buffered reference (INT1V)
• ADC input = Temperature sensor
Table 37-41. Temperature Log Row Content
Bit position Name
Description
7:0
ROOM_TEMP_VAL_INT
Integer part of room temperature in °C
11:8
ROOM_TEMP_VAL_DEC Decimal part of room temperature
19:12
HOT_TEMP_VAL_INT
Integer part of hot temperature in °C
23:20
HOT_TEMP_VAL_DEC
Decimal part of hot temperature
31:24
ROOM_INT1V_VAL
2’s complement of the internal 1V reference drift at room temperature
(versus a 1.0 centered value)
39:32
HOT_INT1V_VAL
2’s complement of the internal 1V reference drift at hot temperature
(versus a 1.0 centered value)
51:40
ROOM_ADC_VAL
12-bit ADC conversion at room temperature
63:52
HOT_ADC_VAL
12-bit ADC conversion at hot temperature
The temperature sensor values are logged during test production flow for Room and Hot insertions:
•
•
ROOM_TEMP_VAL_INT and ROOM_TEMP_VAL_DEC contains the measured temperature at room insertion
(e.g. for ROOM_TEMP_VAL_INT=25 and ROOM_TEMP_VAL_DEC=2, the measured temperature at room
insertion is 25.2°C).
HOT_TEMP_VAL_INT and HOT_TEMP_VAL_DEC contains the measured temperature at hot insertion (e.g.
for HOT_TEMP_VAL_INT=83 and HOT_TEMP_VAL_DEC=3, the measured temperature at room insertion is
83.3°C).
The temperature log row also contains the corresponding 12-bit ADC conversions of both Room and Hot
temperatures:
•
•
ROOM_ADC_VAL contains the 12-bit ADC value corresponding to (ROOM_TEMP_VAL_INT,
ROOM_TEMP_VAL_DEC)
HOT_ADC_VAL contains the 12-bit ADC value corresponding to (HOT_TEMP_VAL_INT,
HOT_TEMP_VAL_DEC)
The temperature log row also contains the corresponding 1V internal reference of both Room and Hot temperatures:
•
•
•
ROOM_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to
(ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC)
HOT_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to
(HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC)
ROOM_INT1V_VAL and HOT_INT1V_VAL values are centered around 1V with a 0.001V step. In other words,
the range of values [0,127] corresponds to [1V, 0.873V] and the range of values [-1, -127] corresponds to
[1.001V, 1.127V]. INT1V == 1 - (VAL/1000) is valid for both ranges.
37.11.8.2.2 Using Linear Interpolation
For concise equations, we will use the following notations:
• (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) is denoted tempR
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
•
•
•
•
•
(HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) is denoted tempH
ROOM_ADC_VAL is denoted ADCR, its conversion to Volt is denoted VADCR
HOT_ADC_VAL is denoted ADCH, its conversion to Volt is denoted VADCH
ROOM_INT1V_VAL is denoted INT1VR
HOT_INT1V_VAL is denoted INT1VH
Using the (tempR, ADCR) and (tempH, ADCH) points, using a linear interpolation we have the following equation:
VADC + − VADCR
VADCH + − VADCR
temp+ − tempR = tempH + − tempR
Given a temperature sensor ADC conversion value ADCm, we can infer a coarse value of the temperature tempC as:
tempC = tempR +
ADCm ⋅
1
212 + − 1
ADCH ⋅
[Equation 1]
+ − ADCR ⋅
INT1VH
212 + − 1
INT1VR
12
2 + −1
+ − ADCR ⋅
⋅ tempH + − tempR
INT1VR
12
2 + −1
Notes:
1. In the previous expression, we have added the conversion of the ADC register value to be expressed in V.
2. This is a coarse value because we assume INT1V=1V for this ADC conversion.
Using the (tempR, INT1VR) and (tempH, INT1VH) points, using a linear interpolation we have the following equation:
INT1V + − INT1VR
INT1V + − INT1V
= tempH + − temp R
temp+ − tempR
H
R
Then using the coarse temperature value, we can infer a closer to reality INT1V value during the ADC conversion as:
INT1Vm = INT1VR +
INT1VH + − INT1VR ⋅ tempC + − tempR
tempH + − tempR
Back to [Equation 1], if we replace INT1V=1V by INT1V = INT1Vm, we can deduce a finer temperature value as:
tempf = tempR +
ADCm ⋅
ADCH ⋅
[Equation 1bis]
37.12
INT1Vm
212 + − 1
+ − ADCR ⋅
INT1VH
212 + − 1
INT1VR
212 + − 1
+ − ADCR ⋅
⋅ tempH ⋅ tempR
INT1VR
212 + − 1
NVM Characteristics
Table 37-42. Maximum Operating Frequency
VDD range
NVM Wait States
Maximum Operating Frequency
Units
1.62V to 2.7V
0
14
MHz
1
28
2
42
3
48
0
24
1
48
2.7V to 3.63V
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 37-43. Flash Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
-40°C < Ta < 85°C
25k
150k
-
Cycles
CycNVM
Cycling
Endurance(1)
1. An endurance cycle is a write and an erase operation.
Table 37-44. EEPROM Emulation(1) Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetEEPROM100k
Retention after up to 100k
Average ambient 55°C
10
50
-
Years
RetEEPROM10k
Retention after up to 10k
Average ambient 55°C
20
100
-
Years
CycEEPROM
Cycling Endurance(2)
-40°C < Ta < 85°C
100k
600k
-
Cycles
1. The EEPROM emulation is a software emulation described in the App note AT03265.
2. An endurance cycle is a write and an erase operation.
Table 37-45. NVM Characteristics (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
tFPP
Page programming time
-
-
-
2.5
ms
tFRE
Row erase time
-
-
-
6
ms
tFCE
DSU chip erase time (CHIP_ERASE)
-
-
-
240
ms
Table 37-46. NVM Characteristics (Device Variant B,C, D and L)
37.13
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
tFPP
Page programming time
-
-
-
2.5
ms
tFRE
Row erase time
-
-
1.2
6
ms
tFCE
DSU chip erase time (CHIP_ERASE)
-
-
-
240
ms
Oscillators Characteristics
37.13.1 Crystal Oscillator (XOSC) Characteristics
37.13.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 37-47. Digital Clock Characteristics
Symbol
Parameter
fCPXIN
XIN clock frequency
© 2021 Microchip Technology Inc.
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Conditions
Complete Datasheet
Min.
Typ.
Max.
Units
-
-
32
MHz
DS40001882H-page 891
SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.13.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT . The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in
the table. The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T= 113 μm)
Table 37-48. Crystal Oscillator Characteristics
Symbol Parameter
fOUT
Crystal oscillator frequency
ESR
Crystal Equivalent Series Resistance
Safety Factor = 3
The AGC doesn’t have any noticeable
impact on these measurements.
Conditions
Min. Typ.
Max.
Units
0.4
-
32
MHz
f = 0.455 MHz, CL = 100pF
XOSC.GAIN = 0
-
-
5.6K
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
-
-
416
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
-
-
243
f = 8 MHz, CL = 20pF
XOSC.GAIN = 2
-
-
138
f = 16 MHz, CL = 20pF
XOSC.GAIN = 3
-
-
66
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
-
-
56
CXIN
Parasitic capacitor load
-
5.9
-
pF
CXOUT
Parasitic capacitor load
-
3.2
-
pF
f = 2MHz, CL = 20pF, AGC off
27
65
85
μA
f = 2MHz, CL = 20pF, AGC on
14
52
73
f = 4MHz, CL = 20pF, AGC off
61
117
150
f = 4MHz, CL = 20pF, AGC on
23
74
100
f = 8MHz, CL = 20pF, AGC off
131
226
296
f = 8MHz, CL = 20pF, AGC on
56
128
172
f = 16MHz, CL = 20pF, AGC off 305
502
687
f = 16MHz, CL = 20pF, AGC on 116
307
552
Current Consumption
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f = 32MHz, CL = 18pF, AGC off 1031 1622
2200
f = 32MHz, CL = 18pF, AGC on 278
1200
Complete Datasheet
615
DS40001882H-page 892
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Conditions
Min. Typ.
Max.
Units
tSTARTUP Start-up time
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
-
14K
48K
cycles
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
-
6.8K
19.5K
f = 8 MHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
-
5.55K 13K
f = 16 MHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
-
6.75K 14.5K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
-
5.3K
9.6K
Figure 37-6. Oscillator Connection
Xin
C LEXT
Crystal
LM
C SHUNT
RM
C STRAY
CM
Xout
C LEXT
37.13.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
37.13.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 37-49. Digital Clock Characteristics
Symbol
Parameter
fCPXIN32
Conditions
Min.
Typ.
Max.
Units
XIN32 clock frequency
-
32.768
-
kHz
XIN32 clock duty cycle
-
50
-
%
37.13.2.1.1 Crystal Oscillator Characteristics
Figure 37-6 and the equation in also applies to the 32 kHz oscillator connection. The user must choose a crystal
oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be
found in the crystal data sheet.
Table 37-50. 32kHz Crystal Oscillator Characteristics (Device Variant A)
Symbol Parameter
fOUT
Conditions
Crystal oscillator frequency
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Min. Typ.
-
Complete Datasheet
Max. Units
32768 -
Hz
DS40001882H-page 893
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol Parameter
Conditions
Min. Typ.
Max. Units
tSTARTUP Startup time
ESRXTAL = 39.9 kΩ, CL =
12.5 pF
-
28K
30K
cycles
CL
Crystal load capacitance
-
-
12.5 pF
CSHUNT
Crystal shunt capacitance
-
0.1
-
CXIN32
Parasitic capacitor load
-
3.1
-
CXOUT32 Parasitic capacitor load
-
3.3
-
IXOSC32K Current consumption
-
1.22
2.19 µA
-
-
141
ESR
Crystal equivalent series resistance
f=32.768kHz
, Safety Factor = 3
CL=12.5pF
kΩ
Table 37-51. 32kHz Crystal Oscillator Characteristics (Device Variant B,C, D, and L)
Symbol Parameter
fOUT
Conditions
Crystal oscillator frequency
tSTARTUP Startup time
ESRXTAL = 39.9 kΩ, CL =
12.5 pF
Min. Typ.
Max. Units
-
32768 -
Hz
-
28K
30K
cycles
CL
Crystal load capacitance
-
-
12.5 pF
CSHUNT
Crystal shunt capacitance
-
0.1
-
CXIN32
Parasitic capacitor load
-
3.2
-
CXOUT32 Parasitic capacitor load
-
3.7
-
IXOSC32K Current consumption
-
1.22
2.19 µA
-
-
100
ESR
Crystal equivalent series resistance
f=32.768kHz
, Safety Factor = 3
CL=12.5pF
kΩ
37.13.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 37-52. DFLL48M Characteristics - Open Loop Mode(1)
Symbol Parameter
Conditions
Min. Typ. Max. Units
fOUT
Output frequency
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
47
IDFLL
Power consumption on VDDIN IDFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512
tSTARTUP Start-up time
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
-
48
49
MHz
403
453
μA
8
9
μs
fOUT within 90 % of final value
Note: 1. DFLL48M in Open loop after calibration at room temperature.
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-53. DFLL48M Characteristics - Closed Loop Mode(1) (Device Variant A)
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Average Output
frequency
fREF = XTAL, 32 .768kHz, 100ppm DFLLMUL =
1464
47.963 47.972 47.981 MHz
fREF
Reference frequency
Jitter
Cycle to Cycle jitter
IDFLL
tLOCK
0.732
32.768 33
kHz
fREF = XTAL, 32 .768kHz, 100ppm DFLLMUL =
1464
-
-
0.42
ns
Power consumption
on VDDIN
fREF = XTAL, 32 .768kHz, 100ppm DFLLMUL =
1464
-
425
482
μA
Lock time
fREF = XTAL, 32 .768kHz, 100ppm DFLLMUL =
1464
DFLLVAL.COARSE = DFLL48M COARSE CAL
100
200
500
μs
Max.
Units
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Table 37-54. DFLL48M Characteristics - Closed Loop Mode(1) (Device Variant B, C, D, and L)
Symbol Parameter
Conditions
Min.
Typ.
fOUT
Average Output
frequency
fREF = 32 .768kHz
47.963 47.972 47.981 MHz
fREF
Reference frequency
Jitter
Cycle to Cycle jitter
IDFLL
tLOCK
0.732
32.768 33
kHz
fREF = 32 .768kHz
-
-
0.42
ns
Power consumption on
VDDIN
fREF =32 .768kHz
-
403
453
μA
Lock time
fREF = 32 .768kHz
DFLLVAL.COARSE = DFLL48M COARSE CAL
200
500
μs
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
1.
To insure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in
close loop must be within a 2% error accuracy.
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.13.4 32.768kHz Internal oscillator (OSC32K) Characteristics
Table 37-55. 32kHz RC Oscillator Characteristics
Symbol Parameter
Conditions
Min.
fOUT
Calibrated against a 32.768kHz reference at
25°C, over [-40, +85]C, over [1.62, 3.63]V
28.508 32.768 34.734 kHz
Calibrated against a 32.768kHz reference at
25°C, at VDD=3.3V
32.276 32.768 33.260
Calibrated against a 32.768kHz reference at
25°C, over [1.62, 3.63]V
31.457 32.768 34.079
IOSC32K
Output frequency
Current consumption
Typ.
Max.
Units
-
0.67
1.31
μA
tSTARTUP Start-up time
-
1
2
cycle
Duty
-
50
-
%
Typ.
Max.
Units
Duty Cycle
37.13.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Table 37-56. Ultra Low Power Internal 32kHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min.
fOUT
Output frequency Calibrated against a 32.768kHz reference at
25°C, over [-40, +85]C, over [1.62, 3.63]V
25.559 32.768 38.011 kHz
Calibrated against a 32.768kHz reference at
25°C, at VDD=3.3V
31.293 32.768 34.570
Calibrated against a 32.768kHz reference at
25°C, over [1.62, 3.63]V
31.293 32.768 34.570
iOSCULP32K(1)(2)
-
-
125
nA
tSTARTUP
Start-up time
-
10
-
cycles
Duty
Duty Cycle
-
50
-
%
Notes: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
2. This oscillator is always on.
37.13.6 8MHz RC Oscillator (OSC8M) Characteristics
Table 37-57. Internal 8MHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min. Typ. Max. Units
fOUT
Output frequency
Calibrated against a 8MHz reference at 25°C,
over [-40, +85]C, over [1.62, 3.63]V
7.8
Calibrated against a 8MHz reference at 25°C,
at VDD=3.3V
7.94 8
8.06
Calibrated against a 8MHz reference at 25°C,
over [1.62, 3.63]V
7.92 8
8.08
-1.2
1
%
-2
2
%
TempCo
Frequency vs. Temperature
drift
SupplyCo Frequency vs. Supply drift
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8.16 MHz
DS40001882H-page 896
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Symbol
Parameter
Conditions
IOSC8M
Current consumption
IDLE2 on OSC32K versus IDLE2 on
calibrated OSC8M enabled at 8MHz
(FRANGE=1, PRESC=0)
tSTARTUP
Startup time
Duty
Duty cycle
Min. Typ. Max. Units
64
96
μA
-
2.4
3.3
μs
-
50
-
%
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 37-58. FDPLL96M Characteristics(1) (Device Variant A)
Symbol
Parameter
fIN
Min.
Typ.
Max.
Units
Input frequency
32
-
2000
KHz
fOUT
Output frequency
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
-
500
700
μA
fIN= 32 kHz, fOUT= 96 MHz
-
900
1200
fIN= 32 kHz, fOUT= 48 MHz
-
1.5
2.0
fIN= 32 kHz, fOUT= 96 MHz
-
3.0
10.0
fIN= 2 MHz, fOUT= 48 MHz
-
1.3
2.0
fIN= 2 MHz, fOUT= 96 MHz
-
3.0
7.0
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
1.3
2
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
μs
40
50
60
%
Jp
tLOCK
Duty
Period jitter
Lock Time
Conditions
Duty cycle
%
Table 37-59. FDPLL96M Characteristics(1) (Device Variant B and L with Silicon Revision E)
Symbol
Parameter
fIN
Min.
Typ.
Max.
Units
Input frequency
32
-
2000
KHz
fOUT
Output frequency
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
-
500
700
μA
fIN= 32 kHz, fOUT= 96 MHz
-
900
1200
fIN= 32 kHz, fOUT= 48 MHz
-
1.5
2.1
fIN= 32 kHz, fOUT= 96 MHz
-
4.0
10.0
fIN= 2 MHz, fOUT= 48 MHz
-
1.6
2.2
fIN= 2 MHz, fOUT= 96 MHz
-
4.6
10.2
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
1.2
2
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
μs
40
50
60
%
Jp
tLOCK
Duty
Period jitter
Lock Time
Conditions
Duty cycle
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DS40001882H-page 897
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-60. FDPLL96M Characteristics(1) (Silicon Revision F and G)
Symbol
Parameter
fIN
Min.
Typ.
Max.
Units
Input frequency
32
-
2000
KHz
fOUT
Output frequency
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
-
500
-
μA
fIN= 32 kHz, fOUT= 96 MHz
-
900
-
fIN= 32 kHz, fOUT= 48 MHz
-
2.2
3.0
fIN= 32 kHz, fOUT= 96 MHz
-
3.7
9.0
fIN= 2 MHz, fOUT= 48 MHz
-
2.2
3.0
fIN= 2 MHz, fOUT= 96 MHz
-
4.4
9.7
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
1.0
2
ms
fIN= 2 MHz, fOUT= 96 MHz
-
22
50
μs
40
50
60
%
Jp
Conditions
Period jitter
tLOCK
Lock Time
Duty
Duty cycle
%
Note: All values have been characterized with FILTSEL[1/0] as the default value.
37.14
PTC Typical Characteristics
37.14.1 Device Variant A
Figure 37-7. Power Consumption [μA]
1 sensor, noise countermeasures disabled, f=48MHz, Vcc=3.3V
140
120
100
80
Scan rate 10ms
60
Scan rate 50ms
40
Scan rate 100ms
Scan rate 200ms
20
0
1
2
4
8
16
32
64
Sample averaging
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-8. Power Consumption [μA]
1 sensor, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
200
180
160
140
120
Scan rate 10ms
100
80
Scan rate 50ms
60
Scan rate 100ms
40
Scan rate 200ms
20
0
1
2
4
8
16
32
64
Sample averaging
Figure 37-9. Power Consumption [μA]
10 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
1200
1000
800
Scan rate 10ms
600
Scan rate 50ms
Scan rate 100ms
400
Scan rate 200ms
200
Linear (Scan rate 50ms)
0
1
2
4
8
16
32
64
Sample averaging
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-10. Power Consumption [μA]
10 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
900
800
700
600
500
Scan rate 10ms
400
Scan rate 50ms
300
Scan rate 100ms
200
Scan rate 200ms
100
0
1
2
4
8
16
32
64
Sample averaging
Figure 37-11. Power Consumption [μA]
100 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
5000
4500
4000
3500
3000
Scan rate 10ms
2500
2000
Scan rate 50ms
1500
Scan rate 100ms
1000
Scan rate 200ms
500
0
1
2
4
8
16
32
64
Sample averaging
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Complete Datasheet
DS40001882H-page 900
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-12. Power Consumption [μA]
100 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
1800
1600
1400
1200
1000
Scan rate 10ms
800
Scan rate 50ms
600
Scan rate 100ms
400
Scan rate 200ms
200
0
1
2
4
8
16
32
64
Sample averaging
Figure 37-13. CPU Utilization
80 %
70 %
60 %
50 %
Channel count 1
40 %
Channel count 10
30 %
Channel count 100
20 %
10 %
0%
10
50
100
200
37.14.2 Device Variant B,C and D
VCC = 3.3C and fCPU = 48 MHz for the following PTC measurements.
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
1Key / PTC_GCLK
= 4MHz / FREQ_MODE_NONE
Figure 37-14. 1 Sensor / PTC_GCLK = 4 MHz
/ FREQ_MODE_NONE
1
2
4
8
16
32
64
32
64
Sample Averaging
1Key / PTC_GCLK = 2MHz / FREQ_MODE_HOP
Figure 37-15. 1 Sensor / PTC_GCLK = 2 MHz
/ FREQ_MODE_HOP
1
2
4
8
16
Sample Averaging
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
= 4MHz / FREQ_MODE_NONE
Figure 37-16. 10 Sensor / PTC_GCLK = 410Keys
MHz/ PTC_GCLK
/ FREQ_MODE_NONE
1
2
4
8
16
32
64
32
64
Sample Averaging
= 2MHz / FREQ_MODE_HOP
Figure 37-17. 10 Sensor / PTC_GCLK = 210Keys
MHz/ PTC_GCLK
/ FREQ_MODE_HOP
1
2
4
8
16
Sample Averaging
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Keys / PTC_GCLK
= 4MHz / FREQ_MODE_NONE
Figure 37-18. 100 Sensor / PTC_GCLK = 100
4 MHz
/ FREQ_MODE_NONE
1
2
4
8
16
32
64
32
64
Sample Averaging
Figure 37-19. 100 Sensor / PTC_GCLK = 100
2 MHz
/ FREQ_MODE_HOP
Keys / PTC_GCLK
= 2MHz / FREQ_MODE_HOP
1
2
4
8
16
Sample Averaging
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-61. Sensor Load Capacitance
Symbol
Mode
PTC channel
Max Sensor Load (1)
Y0
16
Y1
23
Y2
19
Units
Y3
Y4
Y5
Y6
Self-capacitance
Cload
23
Y7
Y8
pF
Y9
Y10
19
Y11
Y12
Y13
23
Y14
Y15
Mutual-capacitance
All
30
Note:
1. Capacitance load that the PTC circuitry can compensate for each channel.
Table 37-62. Analog Gain Settings
Symbol
Gain
Setting
Average
GAIN_1
1.0
GAIN_2
2.0
GAIN_4
3.8
GAIN_8
8.0
GAIN_16
12.4
GAIN_32
-
Notes:
1. Analog Gain is a parameter of the QTouch Library. Refer to the QTouch Library Peripheral Touch Controller
User Guide.
2. GAIN_16 and GAIN_32 settings are not recommended, otherwise the PTC measurements might get unstable.
The values in the Power Consumption table below are measured values of power consumption under the following
conditions:
Operating conditions
VDD = 3.3 V
Clocks
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
OSC8M used as main clock source, running undivided at 8MHz
CPU is running on flash with 0 wait states, at 8MHz
PTC running at 4MHz
PTC configuration
Mutual-capacitance mode
One touch channel
System configuration
Standby sleep mode enabled
RTC running on OSCULP32K: used to define the PTC scan rate, through the event system
Drift Calibration disabled: no interrupts, PTC scans are performed in standby mode
Drift Calibration enabled: RTC interrupts (wakeup) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
Table 37-63.
Symbol
Parameters
Drift
Calibration
PTC scan
Oversamples
rate (msec)
10
50
Disabled
100
200
IDD
Current
Consumption
10
50
Enabled
100
200
37.15
Ta
Typ. Max Units
4
9
107
16
17
117
4
5
102
16
6
104
4
4
102
16
5
103
4
4
102
4
102
15
114
16
23
124
4
7
105
16
8
108
4
5
103
16
6
105
4
6
103
16
6
104
16
4
Max 85°C Typ
25°C
µA
USB Characteristics
The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to
these buffers can be found within the USB 2.0 electrical specifications.
The USB interface is USB-IF certified:
- TID 40001583 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks
- TID 120000272 - Embedded Hosts > Full Speed
Electrical configuration required to be USB compliance:
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
- The CPU frequency must be higher 8MHz when USB is active (No constraint for USB suspend mode)
- The operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V).
- The GCLK_USB frequency accuracy source must be less than:
- In USB device mode, 48MHz +/-0.25%
- In USB host mode, 48MHz +/-0.05%
Table 37-64. GCLK_USB Clock Setup Recommendations
Clock setup
DFLL48M
FDPLL96M
USB Device
USB Host
Open loop
No
No
Closed loop, any internal OSC source
No
No
Closed loop, any external XOSC source
Yes
No
Closed loop, USB SOF source (USB recovery mode)(1)
Yes(2)
N/A
Any internal OSC source (32K, 8M, ... )
No
No
Any external XOSC source (< 1MHz)
Yes
No
Any external XOSC source (> 1MHz)
Yes(3)
Yes
Notes: 1. When using DFLL48M in USB recovery mode, the Fine Step value must be Ah to guarantee a USB clock at
+/-0.25% before 11ms after a resume.
2. Very high signal quality and crystal less. It is the best setup for USB Device mode.
3. FDPLL lock time is short when the clock frequency source is high (> 1MHz). Thus, FDPLL and external OSC can
be stopped during USB suspend mode to reduce consumption and guarantee a USB wake-up time (See TDRSMDN
in USB specification).
37.16
Timing Characteristics
37.16.1 External Reset
Table 37-65. External Reset Characteristics
Symbol
Parameter
tEXT
Minimum reset pulse width
Condition
Min.
Typ.
Max.
Units
10
-
-
ns
Min.
Typ.
Max.
Units
1000
-
-
ns
Table 37-66. External Reset Characteristics (Silicon Revision G)
Symbol
Parameter
tEXT
Minimum reset pulse width
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Complete Datasheet
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.16.2 SERCOM in SPI Mode Timing
Figure 37-20. SPI Timing Requirements in Host Mode
tSCKR
tMOS
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data Input)
tMIH
tSCK
MSB
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Figure 37-21. SPI Timing Requirements in Client Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data Input)
tSIH
MSB
tSOSSS
MISO
(Data Output)
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tSSCK
LSB
tSOS
tSOSSH
MSB
LSB
Complete Datasheet
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-67. SPI Timing Characteristics and Requirements(1)
Symbol
Parameter
Conditions
tSCK
SCK period
Host
tSCKW
SCK high/low width
Host
-
0.5*tSCK
-
tSCKR
SCK rise time(2)
Host
-
-
-
Host
-
-
-
time(2)
Min.
Typ.
Max.
84
ns
tSCKF
SCK fall
tMIS
MISO setup to SCK
Host
-
21
-
tMIH
MISO hold after SCK
Host
-
13
-
tMOS
MOSI setup SCK
Host
-
tSCK/2 - 3
-
tMOH
MOSI hold after SCK
Host
-
3
-
tSSCK
Client SCK Period
Client
1*tCLK_APB
-
-
tSSCKW
SCK high/low width
Client
0.5*tSSCK
-
-
tSSCKR
SCK rise time(2)
Client
-
-
-
Client
-
-
-
time(2)
Units
tSSCKF
SCK fall
tSIS
MOSI setup to SCK
Client
tSSCK/2 - 9
-
-
tSIH
MOSI hold after SCK
Client
tSSCK/2 - 3
-
-
tSSS
SS setup to SCK
Client
PRELOADEN=1 2*tCLK_APB
+ tSOS
-
-
PRELOADEN=0 tSOS+7
-
-
tSSH
SS hold after SCK
Client
tSIH - 4
-
-
tSOS
MISO setup SCK
Client
-
tSSCK/2 18
-
tSOH
MISO hold after SCK
Client
-
18
-
tSOSS
MISO setup after SS
low
Client
-
18
-
tSOSH
MISO hold after SS
high
Client
-
10
-
Notes:
1. These values are based on simulation. These values are not covered by test limits in production.
2. See 37.9 I/O Pin Characteristics.
37.16.3 SERCOM in I2C Mode Timing
This section describes the requirements for devices connected to the I2C Interface Bus.
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-22. I2C Interface Bus Timing
tOF
tHIGH
tR
tLOW
tLOW
SCL
tSU;STA
tHD;STA
tHD;DAT
tSU;DAT
tSU;STO
SDA
tBUF
Table 37-68.
I2C
Interface Timing (Device Variant A)
Symbol Parameter
tR
tOF
Rise time for both SDA and SCL
Output fall time from VIHmin to
VILmax
Conditions
Min.
Typ. Max. Units
Standard / Fast
Mode
ICb(2) = 400pF
-
215
300
Fast
Mode +
ICb(2) = 550pF
60
100
High Speed
Mode
ICb(2) = 100pF
20
40
Standard / Fast
Mode
10pF < Cb(2) < 400pF
20.0 50.0
Fast
Mode +
10pF < Cb(2) < 550pF
15.0 50.0
High Speed
Mode
10pF < Cb(2)< 100pF
10.0 40.0
tHD;STA
Hold time (repeated) START
condition
fSCL > 100 kHz, Host
tLOW-9 -
-
tLOW
Low period of SCL Clock
fSCL > 100 kHz
113
-
-
tBUF
Bus free time between a STOP
and a START condition
fSCL > 100 kHz
tLOW
-
-
tSU;STA
Setup time for a repeated START
condition
fSCL > 100 kHz, Host
tLOW+7 -
-
tHD;DAT
Data hold time
fSCL > 100 kHz, Host
9
-
12
tSU;DAT
Data setup time
fSCL > 100 kHz, Host
104
-
-
tSU;STO
Setup time for STOP condition
fSCL > 100 kHz, Host
tLOW+9 -
-
tSU;DAT;rx Data setup time (receive mode)
fSCL > 100 kHz, Client 51
-
56
tHD;DAT;tx Data hold time (send mode)
fSCL > 100 kHz, Client 71
90
138
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DS40001882H-page 910
SAM D21/DA1 Family
Electrical Characteristics at 85℃
Table 37-69. I2C Interface Timing (Device Variant B,C and D)
Symbol Parameter
tR
tOF
Rise time for both SDA and SCL
Output fall time from VIHmin to
VILmax
Conditions
(2)
= 400pF
Min.
Typ. Max. Units
-
230
350
Standard / Fast
Mode
Cb
Fast
Mode +
Cb(2) = 550pF
60
100
High Speed
Mode
Cb(2) = 100pF
30
60
Standard / Fast
Mode
10pF < Cb(2) < 400pF
25
50
Fast
Mode +
10pF < Cb(2) < 550pF
20
30
High Speed
Mode
10pF < Cb(2) < 100pF
10
20
tHD;STA
Hold time (repeated) START
condition
fSCL > 100 kHz, Host
tLOW-9 -
-
tLOW
Low period of SCL Clock
fSCL > 100 kHz
113
-
-
tBUF
Bus free time between a STOP
and a START condition
fSCL > 100 kHz
tLOW
-
-
tSU;STA
Setup time for a repeated START
condition
fSCL > 100 kHz, Host
tLOW+7 -
-
tHD;DAT
Data hold time
fSCL > 100 kHz, Host
9
-
12
tSU;DAT
Data setup time
fSCL > 100 kHz, Host
104
-
-
tSU;STO
Setup time for STOP condition
fSCL > 100 kHz, Host
tLOW+9 -
-
tSU;DAT;rx Data setup time (receive mode)
fSCL > 100 kHz, Client 51
-
56
tHD;DAT;tx Data hold time (send mode)
fSCL > 100 kHz, Client 71
90
138
ns
Notes:
1. These values are based on simulation. These values are not covered by test limits in production.
2. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF.
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
37.16.4 SWD Timing
Figure 37-23. SWD Interface Signals
Read Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Thigh
Tos
Data
Data
Parity
Start
Tlow
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Tri State
Write Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Tis
Start
Tih
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Data
Data
Parity
Tri State
Table 37-70. SWD Timings(1)
Symbol Parameter
Conditions
Min. Max.
Units
Thigh
SWDCLK High period
10
500000 ns
Tlow
SWDCLK Low period
VVDDIO from 3.0 V to 3.6 V, maximum external
capacitor = 40 pF
10
500000
Tos
SWDIO output skew to falling
edge SWDCLK
-5
5
Tis
Input Setup time required
between SWDIO
4
-
Tih
Input Hold time required
between SWDIO and rising
edge SWDCLK
1
-
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
37.16.5 I2S Timing
Figure 37-24. I2S Timing Host Mode
MCK output
tM_SCKOR
SCK output
FS output
SD output
tM_FSOH
tM_SDIS
tM_SDIH
tM_SCKOF
tM_SCKO
tM_SDOH
tM_FSOV
tM_SDOV
LSB right ch.
MSB left ch.
SD input
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SAM D21/DA1 Family
Electrical Characteristics at 85℃
Figure 37-25. I2S Timing Client Mode
tS_FSIH
SCK input
tS_SCKI
tS_FSIS
FS input
tS_SDIS
tS_SDOH
tS_SDIH
tS_SDOV
SD output
LSB rignt ch.
MSB left ch.
SD input
Figure 37-26. I2S Timing PDM2 Mode
PDM2 mode
tPDM2RS tPDM2RH
tPDM2LS
tPDM2LH
SCK input
SD input
Left
Right
Left
Right
Left
Right
Table 37-71. I2S Timing Characteristics and Requirements (Device Variant A)
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max Min. Typ. Max.
tM_MCKOR
I2S MCK rise time(3)
Host mode / Capacitive load
CL = 15 pF
9.2
4.7
ns
tM_MCKOF
I2S MCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
11.5
5.3
ns
dM_MCKO
I2S MCK duty cycle
Host mode
50
%
dM_MCKI
I2S MCK duty cycle
Host mode, pin is input (1b)
tM_SCKOR
I2S SCK rise time(3)
Host mode / Capacitive load
CL = 15 pF
9
4.6
ns
tM_SCKOF
I2S SCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
9.7
4.5
ns
dM_SCKO
I2S SCK duty cycle
Host mode
50
%
fM_SCKO,1/
tM_SCKO
I2S SCK frequency
Host mode,Supposing external
device response delay is 30ns
8
9.5
MHz
fS_SCKI,1/
tS_SCKI
I2S SCK frequency
Client mode,Supposing
external device response
delay is 30ns
14.4
14.8
MHz
dS_SCKO
I2S SCK duty cycle
Client mode
tM_FSOV
FS valid time
Host mode
tM_FSOH
FS hold time
Host mode
-0.9
-0.9
ns
tS_FSIS
FS setup time
Client mode
2.3
1.5
ns
tS_FSIH
FS hold time
Client mode
0
0
ns
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50
45.4
50
45.6
50
50
45.6
50
%
50
4.1
%
4
ns
DS40001882H-page 913
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max Min. Typ. Max.
tM_SDIS
Data input setup time Host mode
34.7
24.5
ns
tM_SDIH
Data input hold time
-8.2
-8.2
ns
tS_SDIS
Data input setup time Client mode
4.6
3.9
ns
tS_SDIH
Data input hold time
1.2
1.2
ns
tM_SDOV
Data output valid time Host transmitter
tM_SDOH
Data output hold time Host transmitter
tS_SDOV
Data output valid time Client transmitter
tS_SDOH
Data output hold time Client transmitter
tPDM2LS
Host mode
Client mode
5.6
-0.5
4.8
-0.5
ns
ns
36.2
25.9
ns
36
25.7
ns
Data input setup time Host mode PDM2 Left
34.7
24.5
ns
tPDM2LH
Data input hold time
-8.2
-8.2
ns
tPDM2RS
Data input setup time Host mode PDM2 Right
30.5
20.9
ns
tPDM2RH
Data input hold time
-6.7
-6.7
ns
Host mode PDM2 Left
Host mode PDM2 Right
Table 37-72. I2S Timing Characteristics and Requirements (Device Variant B, C and D)
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tM_MCKOR
I2S MCK rise time(3)
Host mode / Capacitive load
CL = 15 pF
9.2
4.7
ns
tM_MCKOF
I2S MCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
11.6
5.4
ns
dM_MCKO
I2S MCK duty cycle
Host mode
50
%
dM_MCKI
I2S MCK duty cycle
Host mode, pin is input (1b)
tM_SCKOR
I2S SCK rise time(3)
Host mode / Capacitive load
CL = 15 pF
9
4.6
ns
tM_SCKOF
I2S SCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
9.7
4.6
ns
dM_SCKO
I2S SCK duty cycle
Host mode
50
%
fM_SCKO, 1/
tM_SCKO
I2S SCK frequency
Host mode, Supposing
external device response
delay is 30ns
7.8
9.2
MHz
fS_SCKI, 1/tS_SCKI I2S SCK frequency
Client mode, Supposing
external device response
delay is 30ns
12.8
13
MHz
dS_SCKO
I2S SCK duty cycle
Client mode
tM_FSOV
FS valid time
Host mode
tM_FSOH
FS hold time
Host mode
-0.1
-0.1
ns
tS_FSIS
FS setup time
Client mode
6
5.3
ns
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50
47.3
50
47
50
50
47.2
50
50
2.4
Complete Datasheet
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%
1.9
ns
DS40001882H-page 914
SAM D21/DA1 Family
Electrical Characteristics at 85℃
...........continued
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tS_FSIH
FS hold time
Client mode
0
0
ns
tM_SDIS
Data input setup time Host mode
36
25.9
ns
tM_SDIH
Data input hold time
-8.2
-8.2
ns
tS_SDIS
Data input setup time Client mode
9.1
8.3
ns
tS_SDIH
Data input hold time
3.8
3.7
ns
tM_SDOV
Data output valid time Host transmitter
tM_SDOH
Data output hold time Host transmitter
tS_SDOV
Data output valid time Client transmitter
tS_SDOH
Data output hold time Client transmitter
29.1
18.9
ns
tPDM2LS
Data input setup time Host mode PDM2 Left
35.5
25.3
ns
tPDM2LH
Data input hold time
-8.2
-8.2
ns
tPDM2RS
Data input setup time Host mode PDM2 Right
30.6
21.1
ns
tPDM2RH
Data input hold time
-7
-7
ns
Host mode
Client mode
Host mode PDM2 Left
2.5
-0.1
1.9
-0.1
29.8
Host mode PDM2 Right
ns
ns
19.7
ns
Notes:
1. All timing characteristics given for 15pF capacitive load.
2. These values are based on simulations and not covered by test limits in production.
3. See 37.9 I/O Pin Characteristics
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SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.
Electrical Characteristics at 105°C
38.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
38.2
Absolute Maximum Ratings
Stresses beyond those listed in table below may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 38-1. Absolute Maximum Ratings
Symbol
Parameter
VDD
Min.
Max.
Units
Power supply voltage
0
3.8
V
IDD
Current into a VDD pin
-
92(1)
mA
IGND
Current out of a GND pin
-
130(1)
mA
VPIN
Pin voltage with respect to GND and VDD
GND-0.3V
VDD+0.3V
V
Tstorgae
Storage temperature
-60
150
°C
1.
Condition
Maximum source current is 46mA and maximum sink current is 65mA per cluster. A cluster is a group of
GPIOs. Also note that each VDD/GND pair is connected to two clusters so current consumption through the
pair will be a sum of the clusters source/sink currents.
Related Links
7.2.4 GPIO Clusters
38.3
General Operating Ratings
The device must operate within the ratings listed in the table below in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 38-2. General Operating Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Units
Power supply voltage
1.62(1)
3.3
3.63
V
VDDANA
Analog supply voltage
1.62(1)
3.3
3.63
V
TA
Temperature range
-40
25
105
°C
TJ
Junction temperature
-
-
125
°C
1.
Condition
With BOD33 disabled. If the BOD33 is enabled, refer to the BOD33 characteristics.
Related Links
38.6.2.1 BOD33 Characteristics
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SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.4
Maximum Clock Frequencies
Table 38-3. Maximum GCLK Generator Output Frequencies
Symbol
Description
Conditions
Max.
Units
fGCLKGEN0 / fGCLK_MAIN
GCLK Generator Output Frequency
Undivided
96
MHz
Divided
48
MHz
fGCLKGEN1
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
Table 38-4. Maximum Peripheral Clock Frequencies
Symbol
Description
Max.
Units
fCPU
CPU clock frequency
48
MHz
fAHB
AHB clock frequency
48
MHz
fAPBA
APBA clock frequency
48
MHz
fAPBB
APBB clock frequency
48
MHz
fAPBC
APBC clock frequency
48
MHz
fGCLK_DFLL48M_REF
DFLL48M Reference clock frequency
33
KHz
fGCLK_DPLL
FDPLL96M Reference clock frequency
2
MHz
fGCLK_DPLL_32K
FDPLL96M 32k Reference clock frequency
32
KHz
fGCLK_WDT
WDT input clock frequency
48
MHz
fGCLK_RTC
RTC input clock frequency
48
MHz
fGCLK_EIC
EIC input clock frequency
48
MHz
fGCLK_USB
USB input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_0
EVSYS channel 0 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_1
EVSYS channel 1 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_2
EVSYS channel 2 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_3
EVSYS channel 3 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_4
EVSYS channel 4 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_5
EVSYS channel 5 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_6
EVSYS channel 6 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_7
EVSYS channel 7 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_8
EVSYS channel 8 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_9
EVSYS channel 9 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_10
EVSYS channel 10 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_11
EVSYS channel 11 input clock frequency
48
MHz
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SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
38.5
Symbol
Description
Max.
Units
fGCLK_SERCOMx_SLOW
Common SERCOM slow input clock frequency
48
MHz
fGCLK_SERCOM0_CORE
SERCOM0 input clock frequency
48
MHz
fGCLK_SERCOM1_CORE
SERCOM1 input clock frequency
48
MHz
fGCLK_SERCOM2_CORE
SERCOM2 input clock frequency
48
MHz
fGCLK_SERCOM3_CORE
SERCOM3 input clock frequency
48
MHz
fGCLK_SERCOM4_CORE
SERCOM4 input clock frequency
48
MHz
fGCLK_SERCOM5_CORE
SERCOM5 input clock frequency
48
MHz
fGCLK_TCC0, fGCLK_TCC1
TCC0, TCC1 input clock frequency
96
MHz
fGCLK_TCC2, fGCLK_TCC3, fGCLK_TC3
TCC2, TCC3, TC3 input clock frequency
96
MHz
fGCLK_TC4, fGCLK_TC5
TC4, TC5 input clock frequency
48
MHz
fGCLK_TC6, fGCLK_TC7
TC6, TC7 input clock frequency
48
MHz
fGCLK_ADC
ADC input clock frequency
48
MHz
fGCLK_AC_DIG
AC digital input clock frequency
48
MHz
fGCLK_AC_ANA
AC analog input clock frequency
64
KHz
fGCLK_AC1_DIG
AC1 digital input clock frequency
48
MHz
fGCLK_AC1_ANA
AC1 analog input clock frequency
64
KHz
fGCLK_DAC
DAC input clock frequency
48
MHz
fGCLK_PTC
PTC input clock frequency
48
MHz
fGCLK_I2S_0
I2S serial 0 input clock frequency
13
MHz
fGCLK_I2S_1
I2S serial 1 input clock frequency
13
MHz
Power Consumption
The values in the below table are measured values of power consumption under the following conditions, except
where noted:
•
•
•
•
•
Operating conditions
– VVDDIN = 3.3 V
Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
Oscillators
– XOSC32K (32 kHz crystal oscillator) stopped
– XOSC (crystal oscillator) running with external 32MHz clock on XIN
– DFLL48M stopped
Clocks
– XOSC used as main clock source, except otherwise specified
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
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SAM D21/DA1 Family
Electrical Characteristics at 105°C
•
•
•
•
•
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
CPU is running on flash with 1 wait states
Cache enabled
BOD33 disabled
Table 38-5. Current Consumption (Silicon Revisions A, B, C, D, E, and F)
Mode
Conditions
TA
Max.
Units
ACTIVE
CPU running a While(1) algorithm
105°C -
2.55
2.75
mA
CPU running a While(1) algorithm
VDDIN=1.8V,
CPU is running on Flash with 3 wait
states
-
2.56
2.82
CPU running a While(1) algorithm, CPU
is
running on Flash with 3 wait states with
GCLKIN as reference
-
42*freq +318 42*freq +432 μA
(with freq in
MHz)
CPU running a Fibonacci algorithm
-
4.21
4.59
CPU running a Fibonacci algorithm
VDDIN=1.8V, CPU is running on flash with
3
wait states
-
4.23
4.57
CPU running a Fibonacci algorithm, CPU
is
running on Flash with 3 wait states with
GCLKIN as reference
-
80*freq +320 82*freq +432 μA
(with freq in
MHz)
CPU running a CoreMark algorithm
-
6.02
6.54
CPU running a CoreMark algorithm
VDDIN=1.8V, CPU is running on flash with
3
wait states
-
5.21
5.57
CPU running a CoreMark algorithm, CPU
is
running on Flash with 3 wait states with
GCLKIN as reference
-
96*freq +322 98*freq +432 μA
(with freq in
MHz)
IDLE0
-
1.55
1.62
IDLE1
-
1.13
1.18
IDLE2
-
0.96
1.01
XOSC32K running
/ RTC running at 1kHz(1)
105°C -
214
627
XOSC32K and RTC stopped (1)
105°C -
212
624
XOSC32K running
/ RTC running at 1kHz (1)
105°C -
175
452
XOSC32K and RTC stopped (1)
105°C -
173
450
STANDBY
(rev. E silicon)
STANDBY
(rev. F silicon)
© 2021 Microchip Technology Inc.
and its subsidiaries
Min. Typ.
Complete Datasheet
mA
mA
mA
μA
μA
DS40001882H-page 919
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Note:
1. Measurements were done with SYSCTRL->VREG.bit.RUNSTDBY = 1
Table 38-6. Current Consumption (Silicon Revision G)
Mode
conditions
Ta
ACTIVE
CPU running a While 1 algorithm
Vcc
Typ.
Max.
Units
105°C 3.3V 3.3
3.6
mA
105°C 1.8V 3.3
3.6
CPU running a While 1 algorithm, with GCLKIN as
reference
105°C 3.3V 56*Freq+254 55*Freq+596
CPU running a Fibonacci algorithm
105°C 3.3V 4.2
4.6
105°C 1.8V 4.3
4.7
CPU running a Fibonacci algorithm, with GCLKIN as 105°C 3.3V 75*Freq+254 73*Freq+594
reference
CPU running a CoreMark algorithm
CPU running a CoreMark algorithm, with GCLKIN
as reference
105°C 3.3V 4.9
5.4
105°C 1.8V 4.7
5.1
105°C 3.3V 87*Freq+257 86*Freq+597
IDLE0
105°C 3.3V 1.8
2.1
IDLE1
105°C 3.3V 1.2
1.5
IDLE2
105°C 3.3V 1.0
1.2
STANDBY XOSC32K running, RTC running at 1kHz RTC
running at 1kHz (1)
105°C 3.3V 175.0
452.0
105°C 3.3V 173.0
450.0
XOSC32K and RTC stopped (1)
µA
Note: Measurements done with VREG.bit.RUNSTDBY = 1.
Table 38-7. Wake-up Time
Mode
Conditions
TA
Min.
Typ.
Max.
Units
IDLE0
OSC8M used as main clock source, Cache disabled
105°C
3.8
4
4.1
μs
IDLE1
OSC8M used as main clock source, Cache disabled
12.8
14.3
15.7
IDLE2
OSC8M used as main clock source, Cache disabled
13.7
15.2
16.6
STANDBY
OSC8M used as main clock source, Cache disabled
18.7
20.1
21.6
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 920
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Figure 38-1. Measurement Schematic
VDDIN
VDDANA
VDDIO
Amp 0
VDDCORE
38.6
Analog Characteristics
38.6.1
Power-On Reset (POR) Characteristics
Table 38-8. POR Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VPOT+
Voltage threshold on VDD rising
IVDD falls at 1V/ms or slower
1.27
1.45
1.58
V
VPOT-
Voltage threshold on VDD falling
0.72
0.99
1.32
V
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 921
SAM D21/DA1 Family
Electrical Characteristics at 105°C
VDD
Figure 38-2. POR Operating Principle
VPOT+
VPOT-
38.6.2
RESET
Internal
Time
Brown-Out Detectors Characteristics
38.6.2.1 BOD33 Characteristics
Table 38-9. BOD33 Characteristics
Symbol
Parameter
I
Step size, between
adjacent values in
BOD33.LEVEL
VHYST
VBOD+ - VBOD-
tDET
Detection time
IIdleBOD33 Current consumption om Active/Idle
mode
Conditions
Min. Typ.
Max. Units
-
34
-
mV
Hysteresis ON
35
-
170
mV
Time with
VDDANA < VTH
necessary to generate a
reset signal
-
0.9(1) -
μs
-
25
48
μA
-40- to 105°C -
-
51
25°C
0.034 0.21
Continuous mode
Sampling mode
ISbyBOD33 Current consumption in Standby
mode
tSTARTUP
1.
Sampling mode
Temp.
25°C
-
-40- to 105°C -
-
25°C
0.132 0.38 μA
-40- to 105°C
Startup time
-40- to 105°C -
2.44
1.5
2.2(1)
-
μs
These values are based on simulation. These values are not covered by test limits in production or
characterization.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 922
SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.6.3
Analog-to-Digital Converter (ADC) Characteristics
Table 38-10. Operating Conditions
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDDANA
Power supply voltage
T > 85°C
2.7
-
3.6
V
RES
Resolution
-
8
-
12
bits
fCLK_ADC
ADC Clock frequency
-
30
-
2100
kHz
rate(1)
Single shot
5
-
300
ksps
Sample
Free running
5
-
350
ksps
time(1)
-
250
-
-
ns
Sampling time with DAC as
input(2)
-
3
-
-
µs
Sampling time with Temp
sens as input(2)
-
10
-
-
µs
Sampling time with
Bandgap as input(2)
-
10
-
-
µs
Conversion time(1)
1x Gain
6
-
-
cycles
Sampling
VREF
Voltage reference range
(VREFA or VREFB)
-
1.0
-
VDDANA-0.6
V
INT1V
Internal 1V reference (2,4)
-
-
1.0
-
V
INTVCC0
Internal ratiometric
reference 0(2)
-
-
VDDANA/1.48
-
V
2.0V < VDDANA2.0V
-
VDDANA/2
-
V
2.0V < VDDANA VREF/4
• VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
• VCM_IN > VREF/4 -0.05*VDDANA -0.1V
b. If |VIN| < VREF/4
• VCM_IN < 1.2*VDDANA - 0.75V
• VCM_IN > 0.2*VDDANA - 0.1V
The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (2*Vref/GAIN)
Table 38-12. Single-Ended Mode
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ENOB
Effective Number of Bits
With gain compensation
-
9.7
10.1
Bits
TUE
Total Unadjusted Error
1x gain
-
7.9
30.0
LSB
INL
Integral Non-Linearity
1x gain
1.4
2.6
5.0
LSB
DNL
Differential Non-Linearity
1x gain
+/-0.6
+/-0.7
+/-0.95
LSB
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DS40001882H-page 924
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
GE
Gain Error
Ext. Ref. 1x
-5.0
0.6
5.0
mV
Ext. Ref. 0.5x
+/-0.1
+/-0.37
+/-0.5
%
Ext. Ref. 2x to 16X
+/-0.01
+/-0.1
+/-0.2
%
Gain
Accuracy(4)
OE
Offset Error
Ext. Ref. 1x
-5.0
0.6
10.0
mV
SFDR
Spurious Free Dynamic Range
63.0
68.0
70.1
dB
SINAD
Signal-to-Noise and Distortion
1x Gain
FCLK_ADC = 2.1 MHz
55.0
60.1
62.5
dB
SNR
Signal-to-Noise Ratio
54.0
61.0
64.0
dB
THD
Total Harmonic Distortion
-70.0
-68.0
-65.0
dB
-
1.0
-
mV
Noise RMS
1.
2.
3.
4.
FIN = 40 kHz
AIN = 95% FSR
T = 25°C
Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input
voltage range.
Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage) for all VIN:
– VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (Vref/GAIN)
38.6.3.1 Performance with the Averaging Digital Feature
Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of
multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samplesto-be-collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is
available in the Result register (RESULT).
Table 38-13. Averaging Feature
Average
Number
Condition
SNR(dB) SINAD(dB) SFDR(dB) ENOB(bits)
1
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
66
65
72.8
10.5
67.6
65.8
75.1
10.62
32
69.7
67.1
75.3
10.85
128
70.4
67.5
75.5
10.91
8
38.6.3.2 Performance with the hardware offset and gain correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled
by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register
(GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result
register (RESULT).
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 925
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Table 38-14. Offset and Gain Correction Feature
Gain Factor Conditions
Offset Error
(mV)
Gain Error
(mV)
Total Unadjusted
Error (LSB)
0.25
1
2.4
0.2
0.1
1.5
2x
0.15
-0.15
2.7
8x
-0.05
0.05
3.2
16x
0.1
-0.05
6.1
0.5x
1x
In differential mode, 1x gain, VDDANA=3.0V,
VREF=1.0V, 350kSps at 25°C
38.6.3.3 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order
to achieve maximum accuracy. Seen externally the ADC input consists of a resistor (RSAMPLE) and a capacitor
(CSAMPLE). In addition, the source resistance (RSOURCE) must be taken into account when calculating the required
sample and hold time. The figure below shows the ADC input channel equivalent circuit.
Figure 38-3. ADC Input
VDDANA/2
Analog Input
AINx
RSOURCE
CSAMPLE
RSAMPLE
VIN
To achieve n bits of accuracy, the CSAMPLE capacitor must be charged at least to a voltage of
VCSAMPLE ≥ VIN × 1 − 2− n + 1
The minimum sampling time tSAMPLEHOLD for a given RSOURCEcan be found using this formula:
tSAMPLEHOLD ≥ RSAMPLE + RSOURCE × CSAMPLE × n + 1 × ln 2
38.6.4
for a 12 bits accuracy: tSAMPLEHOLD ≥ RSAMPLE + RSOURCE × CSAMPLE × 9.02
Digital to Analog Converter (DAC) Characteristics
Table 38-15. Operating Conditions
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDDANA
Analog supply voltage
-
1.62
-
3.63
V
AVREF
External reference voltage
-
1.0
-
VDDANA-0.6
V
INT1V(3)
-
-
1
-
V
VDDANA
-
-
VDDANA
-
V
Linear output voltage range
-
0.05
-
VDDANA-0.05
V
Minimum resistive load
-
5
-
-
kΩ
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Complete Datasheet
DS40001882H-page 926
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol
IDD
Parameter
Conditions
Maximum capacitance load
DC supply
current(2)
Min.
Typ.
Max.
Units
-
-
-
100
pF
Voltage pump disabled
-
160
245
μA
Notes:
1. These values are based on specifications otherwise noted.
2. These values are based on characterization, and are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 38-16. Clock and Timing
Symbol
Parameter
Conditions
Conversion rate
Cload = 100 pF
Rload > 5 kΩ
Startup time
Min.
Typ.
Max.
Units
Normal mode
-
-
350
ksps
For ΔDATA = +/-1
-
-
1000
VDDNA > 2.6V
-
-
2.85
μs
VDDNA < 2.6V
-
-
10
μs
Note:
1. These values are based on simulation, and are not covered by test limits in production or characterization.
Table 38-17. Accuracy Characteristics
Symbol
Parameter
Conditions
RES
Input resolution
-
INL
Integral non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
DNL
Differential non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
Min.
Typ.
Max.
Units
-
-
10
Bits
VDD = 1.6V
0.7
0.75
2.0
LSB
VDD = 3.6V
0.6
0.65
1.5
VDD = 1.6V
0.6
0.85
2.0
VDD = 3.6V
0.5
0.8
1.5
VDD = 1.6V
0.5
0.75
1.5
VDD = 3.6V
0.7
0.8
1.5
VDD = 1.6V
+/-0.3
+/-0.4
+/-1.0
VDD = 3.6V
+/-0.25
+/-0.4
+/-0.75
VDD = 1.6V
+/-0.4
+/-0.55
+/-1.5
VDD = 3.6V
+/-0.2
+/-0.3
+/-0.75
VDD = 1.6V
+/-0.5
+/-0.7
+/-1.5
VDD = 3.6V
+/-0.4
+/-0.7
+/-1.5
LSB
GE
Gain error
Ext. VREF
+/-0.5
+/-5
+/-12
mV
OE
Offset error
Ext. VREF
+/-2
+/-1.5
+/-8
mV
Note:
1. All values measured using a conversion rate of 35 ksps.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 927
SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.6.5
Analog Comparator Characteristics
Table 38-18. Electrical and Timing Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Units
Positive input voltage range
0
-
VDDANA
V
Negative input voltage range
0
-
VDDANA
Hysteresis = 0, Fast mode
-15
0.0
+15
mV
Hysteresis = 0, Low power mode
-25
0.0
+25
mV
Hysteresis = 1, Fast mode
20
50
85
mV
Hysteresis = 1, Low power mode
15
40
75
mV
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
-
90
180
ns
Changes for VACM=VDDANA/2
100mV overdrive, Low power mode
-
282
520
ns
Enable to ready delay
Fast mode
-
1
2.6
μs
Enable to ready delay
Low power mode
-
14
22
μs
INL(3)
-1.4
0.75
1.4
LSB
DNL(3)
-0.9
0.25
0.9
LSB
-0.20 0.26
+0.92
LSB
-0.89 0.215
0.89
LSB
Offset
Hysteresis
Propagation delay
tSTARTUP
VSCALE
Startup time
Conditions
Offset Error (1)(2)
Gain Error
1.
2.
3.
38.7
(1)(2)
According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
Data computed with the Best Fit method
Data computed using histogram
NVM Characteristics
Note that on this flash technology, a max number of four consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 38-19. Flash Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
CycNVM
Cycling Endurance(1)
-40°C < Ta < 105°C
25k
150k
-
Cycles
1.
An endurance cycle is a write and an erase operation.
Table 38-20. EEPROM Emulation(1), Endurance and Data Retention
Symbol
RetEEPROM100k
Parameter
Conditions
Retention after up to 100k
Average ambient 55°C
© 2021 Microchip Technology Inc.
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Complete Datasheet
Min.
Typ.
Max.
Units
10
50
-
Years
DS40001882H-page 928
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol
RetEEPROM10k
CycEEPROM
1.
2.
Parameter
Conditions
Retention after up to 10k
Average ambient 55°C
Cycling
Endurance(2)
-40°C < Ta < 105°C
Min.
Typ.
Max.
Units
20
100
-
Years
100k
600k
-
Cycles
The EEPROM emulation is a software emulation described in the App note AT03265.
An endurance cycle is a write and an erase operation.
38.8
Oscillators Characteristics
38.8.1
Crystal Oscillator (XOSC) Characteristics
38.8.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 38-21. Digital Clock Characteristics
Symbol
Parameter
fCPXIN
XIN clock frequency
Conditions
Min.
Typ.
Max.
Units
-
-
32
MHz
38.8.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT as shown in Figure 38-4. The user must choose a crystal oscillator where the crystal load capacitance CL is
within the range given in the table. The exact value of CL can be found in the crystal data sheet. The capacitance of
the external capacitors (CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
Table 38-22. Crystal Oscillator Characteristics
Symbol Parameter
fOUT
Conditions
Crystal oscillator frequency
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Complete Datasheet
Min. Typ. Max.
Units
0.4
MHz
-
32
DS40001882H-page 929
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol Parameter
Conditions
Min. Typ. Max.
Units
ESR
f = 0.455 MHz, CL = 100pF
XOSC.GAIN = 0
-
-
5.6K
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
-
-
416
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
-
-
243
f = 8 MHz, CL = 20pF
XOSC.GAIN = 2
-
-
138
f = 16 MHz, CL = 20pF
XOSC.GAIN = 3
-
-
66
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
-
-
56
Crystal Equivalent Series Resistance
Safety Factor = 3
The AGC doesn’t have any noticeable
impact on these measurements.
CXIN
Parasitic capacitor load
-
5.9
-
pF
CXOUT
Parasitic capacitor load
-
3.2
-
pF
IXOSC
Current Consumption
f = 2MHz, CL = 20pF, AGC off
65
87
μA
f = 2MHz, CL = 20pF, AGC on
52
76
f = 4MHz, CL = 20pF, AGC off
117
155
f = 4MHz, CL = 20pF, AGC on
74
104
f = 8MHz, CL = 20pF, AGC off
226
308
f = 8MHz, CL = 20pF, AGC on
128
180
f = 16MHz, CL = 20pF, AGC off
502
714
f = 16MHz, CL = 20pF, AGC on
307
590
f = 32MHz, CL = 18pF, AGC off
1622 2257
f = 32MHz, CL = 18pF, AGC on
615
1280
48K
tSTARTUP Startup time
© 2021 Microchip Technology Inc.
and its subsidiaries
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
-
14K
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
-
6800 19.5K
f = 8 MHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
-
5550 13K
f = 16 MHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
-
6750 14.5K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
-
5.3K 9.6K
Complete Datasheet
cycles
DS40001882H-page 930
SAM D21/DA1 Family
Electrical Characteristics at 105°C
Figure 38-4. Crystal Oscillator Connection
Xin
C LEXT
Crystal
LM
C SHUNT
RM
C STRAY
CM
Xout
C LEXT
38.8.2
External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
38.8.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 38-23. Digital Clock Characteristics
Symbol
Parameter
fCPXIN32
Conditions
Min.
Typ.
Max.
Units
XIN32 clock frequency
-
32.768
-
kHz
XIN32 clock duty cycle
-
50
-
%
38.8.2.2 Crystal Oscillator Characteristics
Figure 38-4 and the equation in 38.8.1.2 Crystal Oscillator Characteristics also applies to the 32 kHz oscillator
connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given
in the table. The exact value of CL can be found in the crystal datasheet.
Table 38-24. 32kHz Crystal Oscillator Characteristics
Symbol Parameter
Conditions
Min. Typ.
fOUT
I
-
Crystal oscillator frequency
Max. Units
32768 -
Hz
cycles
tSTARTUP Startup time
ESRXTAL = 39.9 kΩ, CL = 12.5 pF
28K
30K
CL
Crystal load capacitance
I
-
-
12.5 pF
CSHUNT
Crystal shunt capacitance
I
-
0.1
-
CXIN32
Parasitic capacitor load
-
3.2
-
CXOUT32 Parasitic capacitor load
-
3.7
-
IXOSC32K Current consumption
-
1.22
2.2
μA
-
-
100
kΩ
ESR
Crystal equivalent series resistance
f=32.768kHz
Safety Factor = 3
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CL=12.5pF
Complete Datasheet
DS40001882H-page 931
SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.8.3
Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 38-25. DFLL48M Characteristics - Open Loop Mode
Symbol Parameter
Conditions
fOUT
Output frequency
IDFLLVAL.COARSE = DFLL48M COARSE CAL 47
DFLLVAL.FINE = 512
IDFLL
Power consumption on VDDIN IDFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512
tSTARTUP Startup time
Min. Typ. Max. Units
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
48
49
MHz
403
453
μA
8
9
μs
Max.
Units
fOUT within 90 % of final value
Note: 1. DFLL48M in Open loop after calibration at room temperature.
Table 38-26. DFLL48M Characteristics - Closed Loop Mode
Symbol Parameter
Conditions
Min.
Typ.
fOUT
Average Output frequency fREF = 32.768kHz
47.76 48
48.24 MHz
fREF
Reference frequency
I
0.732 32.768 33
kHz
Jitter
Period Jitter
fREF = 32.768kHz
-
-
0.42
ns
IDFLL
Power consumption on
VDDIN
fREF = 32.768kHz
-
403
453
μA
tLOCK
Lock time
fREF = 32.768kHz
DFLLVAL.COARSE = DFLL48M COARSE CAL
200
500
μs
Typ.
Max.
Units
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
38.8.4
32.768 kHz Internal oscillator (OSC32K) Characteristics
Table 38-27. 32 kHz RC Oscillator Characteristics
Symbol Parameter
Conditions
fOUT
Calibrated against a 32.768 kHz reference at
25°C, over [-40, +105]°C, over [1.62, 3.63]V
28.508 32.768 35.132
Calibrated against a 32.768 kHz reference at
25°C, at VDD = 3.3V
32.276 32.768 33.260
Calibrated against a 32.768 kHz reference at
25°C, over [1.62, 3.63]V
31.457 32.768 34.079
IOSC32K
Output frequency
Min.
Current consumption I
kHz
-
0.67
1.9
μA
tSTARTUP Startup time
I
-
1
2
cycle
Duty
I
-
50
-
%
Duty Cycle
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SAM D21/DA1 Family
Electrical Characteristics at 105°C
38.8.5
Ultra Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Characteristics
Table 38-28. Ultra Low-Power Internal 32 kHz RC Oscillator Characteristics
Symbol Parameter
fOUT
Conditions
Min.
Output frequency Calibrated against a 32.768 kHz reference at 25°C,
over [-40, +105]°C, over [1.62, 3.63]V
Typ.
Max.
25.559 32.768 40.305
Units
kHz
Calibrated against a 32.768 kHz reference at 25°C, at 31.293 32.768 34.570
VDD = 3.3V
Calibrated against a 32.768 kHz reference at 25°C,
over [1.62, 3.63]V
Duty
1.
2.
38.8.6
31.293 32.768 34.570
Duty cycle
-
50
-
%
These values are based on simulation, and not covered by test limits in production or characterization.
This oscillator is always on.
8 MHz RC Oscillator (OSC8M) Characteristics
Table 38-29. Internal 8 MHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min. Typ. Max. Units
fOUT
Output frequency
ICalibrated against a 8 MHz reference at 25°C,
over [-40, +105]°C, over [1.62, 3.63]V
7.65
8
8.17
Calibrated against a 8 MHz reference at 25°C, at 7.94
VDD = 3.3V
8
8.06
Calibrated against a 8 MHz reference at 25°C,
over [1.62, 3.63]V
8
8.08
TempCo
Frequency vs. temperature
drift
SupplyCo Frequency vs. supply drift
38.8.7
7.92
-1.2
1
-2
2
MHz
IOSC8M
Current consumption
IIDLEIDLE2 on OSC32K versus IDLE2 on
calibrated OSC8M enabled at 8 MHz (FRANGE
= 1, PRESC = 0)
-
64
96
μA
tSTARTUP
Startup time
I
-
2.4
3.3
μs
Duty
Duty cycle
I
-
50
-
%
Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 38-30. FDPLL96M Characteristics (Variant B and L With Silicon Revision E)
Symbol
Parameter
fIN
Min.
Typ.
Max.
Units
Input frequency
32
-
2000
KHz
fOUT
Output frequency
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
500
733
μA
fIN= 32 kHz, fOUT= 96 MHz
900
1235
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Conditions
Complete Datasheet
DS40001882H-page 933
SAM D21/DA1 Family
Electrical Characteristics at 105°C
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Jp
Period jitter
fIN= 32 kHz, fOUT= 48 MHz
-
2.1
3.2
%
fIN= 32 kHz, fOUT= 96 MHz
4.0
6.9
fIN= 2 MHz, fOUT= 48 MHz
2.2
3.6
fIN= 2 MHz, fOUT= 96 MHz
4.7
8.2
After startup, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
1.2
2
ms
fIN= 2 MHz, fOUT= 96 MHz
25
50
μs
40
50
60
%
tLOCK
Duty
Lock Time
Duty cycle
Table 38-31. FDPLL96M Characteristics(1) (Silicon Revision F and G)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fIN
Input frequency
-
32
-
2000
KHz
fOUT
Output frequency
-
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
-
500
-
μA
fIN= 32 kHz, fOUT= 96 MHz
-
900
-
fIN= 32 kHz, fOUT= 48 MHz
-
2.1
3.0
fIN= 32 kHz, fOUT= 96 MHz
-
3.8
9.2
fIN= 2 MHz, fOUT= 48 MHz
-
2.2
3.2
fIN= 2 MHz, fOUT= 96 MHz
-
4.4
10.0
After startup, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
1.2
2
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
μs
-
40
50
60
%
Jp
tLOCK
Duty
Period jitter
Lock Time
Duty cycle
%
Note: 1. All values have been characterized with FILTSEL[1/0] as default value.
38.9
PTC Characteristics at 105°C
The values in the Power Consumption table below are measured values of power consumption under the following
conditions:
Operating Conditions
VDD = 3.3V
Clocks
OSC8M used as main clock source, running undivided at 8MHz
CPU is running on flash with 0 wait states, at 8MHz
PTC running at 4MHz
PTC Configuration
Mutual-capacitance mode
One touch channel
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SAM D21/DA1 Family
Electrical Characteristics at 105°C
System Configuration
Standby sleep mode enabled
RTC running on OSCULP32K: used to define the PTC scan rate, through the event system
Drift Calibration disabled: no interrupts, PTC scans are performed in standby mode
Drift Calibration enabled: RTC interrupts (wakeup) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
Table 38-32. Power Consumption
Symbol
Parameters
Drift
Calibration
PTC scan
rate
(msec)
Oversamples
10
50
Disabled
100
200
IDD
Current
Consumption
10
50
Enabled
100
200
38.10
Ta
Typ. Max Units
4
9
458
16
17
467
4
5
452
16
6
454
4
4
452
16
5
453
4
4
452
4
452
15
466
16
23
476
4
7
456
16
8
459
4
5
455
16
6
455
4
6
453
16
6
454
16
4
Max 105°C Typ
25°C
µA
USB Characteristics
The USB shares the same characteristics as in the -40°C to 85°C.
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SAM D21/DA1 Family
Electrical Characteristics at 125°C
39.
Electrical Characteristics at 125°C
39.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
39.2
Absolute Maximum Ratings
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 39-1. Absolute Maximum Ratings
Symbol
Parameter
VDD
Condition
Min.
Max.
Units
Power supply voltage
0
3.8
V
IVDD
Current into a VDD pin
-
28(1)
mA
IGND
Current out of a GND pin
-
39(1)
mA
VPIN
Pin voltage with respect to GND and VDD
GND-0.6V
VDD+0.6V
V
Tstorage
Storage temperature
-60
150
°C
Note:
1. Maximum source current is 14mA and maximum sink current is 19.5mA per cluster. A cluster is a group
of GPIOs, see related links. Also note that each VDD/GND pair is connected to 2 clusters so current
consumption through the pair will be a sum of the clusters source/sink currents.
Related Links
7.2.4 GPIO Clusters
39.3
General Operating Ratings
The device must operate within the ratings in order for all other electrical characteristics and typical characteristics of
the device to be valid.
Table 39-2. General Operating Conditions
Symbol
Parameter
VDD
Condition
Min.
Typ.
Max.
Units
Power supply voltage
1.62(1)
3.3
3.63
V
VDDANA
Analog supply voltage
1.62(1)
3.3
3.63
V
TA
Temperature range
-40
25
125
°C
TJ
Junction temperature
-
-
145
°C
Note:
Notes: 1. With BOD33 disabled. If the BOD33 is enabled, check Table 37-21.
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SAM D21/DA1 Family
Electrical Characteristics at 125°C
39.4
Maximum Clock Frequencies
Table 39-3. Maximum GCLK Generator Output Frequencies (Device Variant A)
Symbol
Description
Conditions
Max.
Units
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
GCLK Generator Output Frequency
Undivided
96
MHz
Divided
32
MHz
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
fGCLKGEN6
fGCLKGEN7
fGCLKGEN8
Table 39-4. Maximum Peripheral Clock Frequencies (Device Variant A)
Symbol
Description
Max.
Units
fCPU
CPU clock frequency
32
MHz
fAHB
AHB clock frequency
32
MHz
fAPBA
APBA clock frequency
32
MHz
fAPBB
APBB clock frequency
32
MHz
fAPBC
APBC clock frequency
32
MHz
fGCLK_DFLL48M_REF
DFLL48M Reference clock frequency
33
KHz
fGCLK_DPLL
FDPLL96M Reference clock frequency
2
MHz
fGCLK_DPLL_32K
FDPLL96M 32k Reference clock frequency
32
KHz
fGCLK_WDT
WDT input clock frequency
48
MHz
fGCLK_RTC
RTC input clock frequency
48
MHz
fGCLK_EIC
EIC input clock frequency
48
MHz
fGCLK_USB
USB input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_0
EVSYS channel 0 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_1
EVSYS channel 1 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_2
EVSYS channel 2 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_3
EVSYS channel 3 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_4
EVSYS channel 4 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_5
EVSYS channel 5 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_6
EVSYS channel 6 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_7
EVSYS channel 7 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_8
EVSYS channel 8 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_9
EVSYS channel 9 input clock frequency
48
MHz
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SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Description
Max.
Units
fGCLK_EVSYS_CHANNEL_10
EVSYS channel 10 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_11
EVSYS channel 11 input clock frequency
48
MHz
fGCLK_SERCOMx_SLOW
Common SERCOM slow input clock frequency
48
MHz
fGCLK_SERCOM0_CORE
SERCOM0 input clock frequency
48
MHz
fGCLK_SERCOM1_CORE
SERCOM1 input clock frequency
48
MHz
fGCLK_SERCOM2_CORE
SERCOM2 input clock frequency
48
MHz
fGCLK_SERCOM3_CORE
SERCOM3 input clock frequency
48
MHz
fGCLK_SERCOM4_CORE
SERCOM4 input clock frequency
48
MHz
fGCLK_SERCOM5_CORE
SERCOM5 input clock frequency
48
MHz
fGCLK_TCC0, fGCLK_TCC1
TCC0, TCC1 input clock frequency
96
MHz
fGCLK_TCC2, fGCLK_TC3
TCC2, TC3 input clock frequency
96
MHz
fGCLK_TC4, fGCLK_TC5
TC4, TC5 input clock frequency
48
MHz
fGCLK_TC6, fGCLK_TC7
TC6, TC7 input clock frequency
48
MHz
fGCLK_ADC
ADC input clock frequency
48
MHz
fGCLK_AC_DIG
AC digital input clock frequency
48
MHz
fGCLK_AC_ANA
AC analog input clock frequency
64
KHz
fGCLK_DAC
DAC input clock frequency
48
MHz
fGCLK_PTC
PTC input clock frequency
48
MHz
fGCLK_I2S_0
I2S serializer 0 input clock frequency
13
MHz
fGCLK_I2S_1
I2S serializer 1 input clock frequency
13
MHz
Table 39-5. Maximum GCLK Generator Output Frequencies (Device Variant B, C, D, and L)
Symbol
Description
Conditions
Max.
Units
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
GCLK Generator Output Frequency
Undivided
96
MHz
Divided
48
MHz
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
fGCLKGEN6
fGCLKGEN7
fGCLKGEN8
Table 39-6. Maximum Peripheral Clock Frequencies (Device Variant B, C, D, and L)
Symbol
Description
Max.
Units
fCPU
CPU clock frequency
48
MHz
fAHB
AHB clock frequency
48
MHz
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SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Description
Max.
Units
fAPBA
APBA clock frequency
48
MHz
fAPBB
APBB clock frequency
48
MHz
fAPBC
APBC clock frequency
48
MHz
fGCLK_DFLL48M_REF
DFLL48M Reference clock frequency
33
KHz
fGCLK_DPLL
FDPLL96M Reference clock frequency
2
MHz
fGCLK_DPLL_32K
FDPLL96M 32k Reference clock frequency
32
KHz
fGCLK_WDT
WDT input clock frequency
48
MHz
fGCLK_RTC
RTC input clock frequency
48
MHz
fGCLK_EIC
EIC input clock frequency
48
MHz
fGCLK_USB
USB input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_0
EVSYS channel 0 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_1
EVSYS channel 1 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_2
EVSYS channel 2 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_3
EVSYS channel 3 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_4
EVSYS channel 4 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_5
EVSYS channel 5 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_6
EVSYS channel 6 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_7
EVSYS channel 7 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_8
EVSYS channel 8 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_9
EVSYS channel 9 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_10
EVSYS channel 10 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_11
EVSYS channel 11 input clock frequency
48
MHz
fGCLK_SERCOMx_SLOW
Common SERCOM slow input clock frequency
48
MHz
fGCLK_SERCOM0_CORE
SERCOM0 input clock frequency
48
MHz
fGCLK_SERCOM1_CORE
SERCOM1 input clock frequency
48
MHz
fGCLK_SERCOM2_CORE
SERCOM2 input clock frequency
48
MHz
fGCLK_SERCOM3_CORE
SERCOM3 input clock frequency
48
MHz
fGCLK_SERCOM4_CORE
SERCOM4 input clock frequency
48
MHz
fGCLK_SERCOM5_CORE
SERCOM5 input clock frequency
48
MHz
fGCLK_TCC0, fGCLK_TCC1
TCC0, TCC1 input clock frequency
96
MHz
fGCLK_TCC2, fGCLK_TCC3, fGCLK_TC3
TCC2, TCC3,TC3 input clock frequency
96
MHz
fGCLK_TC4, fGCLK_TC5
TC4, TC5 input clock frequency
48
MHz
fGCLK_TC6, fGCLK_TC7
TC6, TC7 input clock frequency
48
MHz
fGCLK_ADC
ADC input clock frequency
48
MHz
fGCLK_AC_DIG
AC digital input clock frequency
48
MHz
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SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
39.5
Symbol
Description
Max.
Units
fGCLK_AC_ANA
AC analog input clock frequency
64
KHz
fGCLK_AC1_DIG
AC1 digital input clock frequency
48
MHz
fGCLK_AC1_ANA
AC1 analog input clock frequency
64
KHz
fGCLK_DAC
DAC input clock frequency
48
MHz
fGCLK_PTC
PTC input clock frequency
48
MHz
fGCLK_I2S_0
I2S serializer 0 input clock frequency
13
MHz
fGCLK_I2S_1
I2S serializer 1 input clock frequency
13
MHz
Power Consumption
The values in this section are measured values of power consumption under the following conditions, except where
noted:
•
•
•
•
•
•
•
•
•
•
Operating conditions
– VVDDIN = 3.3 V
Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
Oscillators
– XOSC (crystal oscillator) stopped
– XOSC32K (32 kHz crystal oscillator) running with external 32kHz crystal
– DFLL48M using XOSC32K as reference and running at 48 MHz
Clocks
– DFLL48M used as main clock source, except otherwise specified
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
CPU is running on flash with 1 wait states
Cache enabled
BOD33 disabled
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SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table
•
39-7. Current Consumption (Device Variant A, B, C and L. Silicon Revision F)
Mode
ACTIVE
Conditions
CPU running a
TA
While(1)
algorithm
CPU running a While(1) algorithm
VDDIN=1.8V,
CPU is running on Flash with 3 wait
states
Typ.
Max.
Units
125°C 3.75
4.12
mA
125°C 3.77
4.13
CPU running a While(1) algorithm, CPU 125°C 62*freq + 228 62*freq + 302 μA
is
(with freq in
running on Flash with 3 wait states with
MHz)
GCLKIN as reference
CPU running a Fibonacci algorithm
125°C 4.85
5.29
CPU running a Fibonacci algorithm
VDDIN=1.8V, CPU is running on flash
with 3
wait states
125°C 4.87
5.29
mA
CPU running a Fibonacci algorithm,
125°C 88*freq + 424 88*freq + 486 μA
CPU is
(with freq in
running on Flash with 3 wait states with
MHz)
GCLKIN as reference
CPU running a CoreMark algorithm
125°C 6.70
7.30
CPU running a CoreMark algorithm
VDDIN=1.8V, CPU is running on flash
with 3
wait states
125°C 5.98
6.41
mA
CPU running a CoreMark algorithm,
125°C 108*freq +
CPU is
426
running on Flash with 3 wait states with
GCLKIN as reference
108*freq +
492
μA
(with freq in
MHz)
IDLE0
Default operating conditions
125°C 2.40
2.69
mA
IDLE1
Default operating conditions
125°C 1.79
2.05
IDLE2
Default operating conditions
125°C 1.50
1.76
STANDBY
XOSC32K running
, RTC running at 1kHz(1)
125°C 348.0
850.0
XOSC32K and RTC stopped(1)
125°C 346.0
848.0
XOSC32K running
, RTC running at 1kHz(1)
125°C 294.0
782.0
125°C 292.0
780.0
(Device Variant B,
Die Revision E)
STANDBY
(Device Variant B
and C, Die Revision XOSC32K and RTC stopped(1)
F)
μA
μA
Note:
1. Measurements were done with SYSCTRL->VREG.bit.RUNSTDBY = 1
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Complete Datasheet
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SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-8. Current Consumption (Silicon Revision G)
Mode
conditions
ACTIVE
Ta
CPU running a While 1 algorithm
CPU running a While 1 algorithm, with GCLKIN as
reference
Typ.
Max.
3,3V
3.5
4.0
1,8V
3.5
4.0
CPU running a Fibonacci algorithm, with GCLKIN
as reference
3,3V
4.5
5.0
1,8V
4.5
5.0
3,3V 75*Freq+397 72*Freq+1076
125°C
CPU running a CoreMark algorithm, with GCLKIN
as reference
3,3V
5.1
5.7
1,8V
4.9
5.5
3,3V
2.0
2.5
IDLE1
3,3V
1.4
1.9
IDLE2
3,3V
1.1
1.7
3,3V
294.0
782.0
3,3V
292.0
780.0
XOSC32K running, RTC running at 1kHz RTC
running at 1kHz (1)
XOSC32K and RTC stopped (1)
mA
3,3V 88*Freq+399 85*Freq+1075
IDLE0
STANDBY
Units
3,3V 57*Freq+395 55*Freq+1076
CPU running a Fibonacci algorithm
CPU running a CoreMark algorithm
Vcc
µA
Note:
1. Measurements done with VREG.bit.RUNSTDBY = 1.
Table 39-9. Wake-up Time (SAMD21)
Mode
Conditions
TA
Min.
Typ.
Max.
Units
IDLE0
OSC8M used as main clock source, Cache disabled
125°C
3.9
4.0
4.1
μs
IDLE1
OSC8M used as main clock source, Cache disabled
125°C
13.5
14.9
16.4
IDLE2
OSC8M used as main clock source, Cache disabled
125°C
14.4
15.8
17.2
STANDBY
OSC8M used as main clock source, Cache disabled
125°C
19.2
20.6
22.1
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 942
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Figure 39-1. Measurement Schematic
VDDIN
VDDANA
VDDIO
Amp 0
VDDCORE
39.6
Analog Characteristics
39.6.1
Power-On Reset (POR) Characteristics
Table 39-10. POR Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VPOT+
Voltage threshold on VDD rising
VDD falls at 1V/ms or slower
1.27
1.45
1.58
V
VPOT-
Voltage threshold on VDD falling
0.72
0.99
1.32
V
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 943
SAM D21/DA1 Family
Electrical Characteristics at 125°C
VDD
Figure 39-2. POR Operating Principle
VPOT+
VPOT-
39.6.2
RESET
Internal
Time
Brown-Out Detectors Characteristics
39.6.2.1 BOD33
Table 39-11. BOD33 Characteristics (Device Variant A)
Symbol
Parameter
Conditions
Temp.
Step size, between
adjacent values in
BOD33.LEVEL
Min. Typ.
Max. Units
-
34
-
mV
170
mV
VHYST
VBOD+ - VBOD-
Hysteresis ON
35
-
tDET
Detection time
Time with VDDANA < VTH
necessary to generate a
reset signal
-
0.9(1) -
μs
IBOD33
Current consumption
Continuous mode
-
25
48
μA
-40 to 125°C -
-
50
25°C
0.034 0.21
Sampling mode
ISbyBOD33 Current consumption in Standby
mode
tSTARTUP
Sampling mode
and its subsidiaries
-
-40 to 125°C --
-
25°C
0.132 0.38 μA
-
-40 to 125°C -
Start-up time
© 2021 Microchip Technology Inc.
25°C
-
Complete Datasheet
-
2.29
1.62
1.2(1) -
μs
DS40001882H-page 944
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-12. BOD33 Characteristics (Device Variant B, C, D and L)
Symbol
Parameter
Conditions
Temp.
Step size, between
adjacent values in
BOD33.LEVEL
Min. Typ.
Max. Units
-
34
-
mV
170
mV
VHYST
VBOD+ - VBOD-
Hysteresis ON
35
-
tDET
Detection time
Time with VDDANA < VTH
necessary to generate a
reset signal
-
0.9(1) -
μs
IBOD33
Current consumption
Continuous mode
-
25
48
μA
-40 to 125°C -
-
52
25°C
0.03
0.21
-40 to 125°C --
-
2.91
25°C
0.13
0.38 μA
-
1.7
25°C
Sampling mode
ISbyBOD33 Current consumption in Standby
mode
tSTARTUP
Sampling mode
-
-
-40 to 125°C -
Start-up time
-
2.2(1) -
μs
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
39.6.3
Analog-to-Digital (ADC) characteristics
Table 39-13. Operating Conditions (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDDANA
Power Supply Voltage
T>105°C
3
-
3.6
V
RES
Resolution
-
8
-
12
bits
fCLK_ADC
ADC Clock frequency
-
30
-
2100
kHz
Sample rate(1)
Single shot (with
VDDANA > 3.0V)(4)
5
-
300
ksps
Free running
5
-
350
ksps
250
-
-
ns
Sampling time with DAC as input(2)
3
-
-
µs
Sampling time with Temp
sens as input(2)
-
10
-
-
µs
Sampling time with
Bandgap as input(2)
-
10
-
-
µs
Conversion time(1)
1x Gain
6
-
-
cycles
VREF
Voltage reference range
(VREFA or VREFB)
-
1.0
-
VDDANA-0.6
V
INT1V
Internal 1V reference (2,5)
-
-
1.0
-
V
INTVCC0
Internal ratiometric
reference 0(2)
-
-
VDDANA/1.48
-
V
Sampling time(1)
© 2021 Microchip Technology Inc.
and its subsidiaries
-
Complete Datasheet
DS40001882H-page 945
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
INTVCC0
Internal ratiometric
Voltage Error reference 0(2) error
2.0V < VDDANA2.0V
-
VDDANA/2
-
V
-1.0
-
+1.0
%
-VREF/
GAIN
-
+VREF/GAIN
V
0.0
-
+VREF/GAIN
V
Internal ratiometric
reference 1(2)
INTVCC1
Internal ratiometric
Voltage Error reference 1(2) error
Conversion range(1)
2.0V < VDDANA105°C
3
-
3.6
V
RES
Resolution
-
8
-
12
bits
fCLK_ADC
ADC Clock frequency
-
30
-
2100
kHz
Conversion speed
-
10
-
1000
ksps
Single shot
5
-
300
ksps
Free running
5
-
350
ksps
Sampling time(1)
-
250
-
-
ns
Sampling time with DAC as
input(2)
-
3
-
-
µs
Sampling time with Temp
sens as input(2)
-
10
-
-
µs
Sampling time with
Bandgap as input(2)
-
10
-
-
µs
Conversion time(1)
1x Gain
6
-
-
cycles
VREF
Voltage reference range
(VREFA or VREFB)
-
1.0
-
VDDANA-0.6
V
INTV1
Internal 1V reference (2,4)
-
-
1.0
-
V
INTVCC0
Internal ratiometric
reference 0(2)
-
-
VDDANA/1.48 -
V
INTVCC0
Internal ratiometric
Voltage Error reference 0(2) error
2.0V <
VDDANA2.0V
-
VDDANA/2
-
V
Sample
rate(1)
Internal ratiometric
reference 1(2)
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Complete Datasheet
DS40001882H-page 946
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
INTVCC1
Internal ratiometric
Voltage Error reference 1(2) error
Conversion range(1)
Conditions
Min.
Typ.
Max.
Units
2.0V <
VDDANA VREF/4
– VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 -0.05*VDDANA -0.1V
ii. If |VIN| < VREF/4
– VCM_IN < 1.2*VDDANA - 0.75V
– VCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (2*Vref/GAIN)
Table 39-17. Single-Ended Mode (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ENOB
Effective Number of Bits
With gain compensation
-
9.5
9.8
Bits
TUE
Total Unadjusted Error
1x gain
-
10.5
14.0
LSB
INL
Integral Non-Linearity
1x gain
1.0
1.6
7.5
LSB
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 948
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
DNL
Differential Non-Linearity
1x gain
+/-0.5
+/-0.6
+/-0.95
LSB
GE
Gain Error
Ext. Ref. 1x
-10.0
0.7
+10.0
mV
Gain Accuracy(4)
Ext. Ref. 0.5x
+/-0.1
+/-0.34
+/-0.4
%
Ext. Ref. 2x to 16X
+/-0.01
+/-0.1
+/-0.15
%
OE
Offset Error
Ext. Ref. 1x
-5.0
1.5
+10.0
mV
SFDR
Spurious Free Dynamic Range
63.1
65.0
66.5
dB
SINAD
Signal-to-Noise and Distortion
1x Gain
FCLK_ADC = 2.1 MHz
50.7
59.5
61.0
dB
SNR
Signal-to-Noise Ratio
49.9
60.0
64.0
dB
THD
Total Harmonic Distortion
-65.4
-63.0
-62.1
dB
-
1.0
-
mV
Noise RMS
FIN = 40 kHz
AIN = 95% FSR
T = 25°C
Table 39-18. Single-Ended Mode (Device Variant B, C, D and L)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ENOB
Effective Number of Bits
With gain compensation
-
9.7
10.1
Bits
TUE
Total Unadjusted Error
1x gain
-
7.9
40.0
LSB
INL
Integral Non-Linearity
1x gain
1.4
2.6
6.0
LSB
DNL
Differential Non-Linearity
1x gain
+/-0.6
+/-0.7
+/-0.95
LSB
GE
Gain Error
Ext. Ref. 1x
-5.0
0.6
+5.0
mV
Gain Accuracy(4)
Ext. Ref. 0.5x
+/-0.1
+/-0.37
+/-0.55
%
Ext. Ref. 2x to 16X
+/-0.01
+/-0.1
+/-0.2
%
OE
Offset Error
Ext. Ref. 1x
-5.0
0.6
+10.0
mV
SFDR
Spurious Free Dynamic Range
63.0
68.0
68.7
dB
SINAD
Signal-to-Noise and Distortion
1x Gain
FCLK_ADC = 2.1 MHz
55.0
60.1
62.5
dB
SNR
Signal-to-Noise Ratio
54.0
61.0
64.0
dB
THD
Total Harmonic Distortion
-69.0
-68.0
-65.0
dB
-
1.0
-
mV
Noise RMS
FIN = 40 kHz
AIN = 95%FSR
T = 25°C
Notes:
1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input
voltage range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage) for all VIN:
– VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC
performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (Vref/GAIN)
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 949
SAM D21/DA1 Family
Electrical Characteristics at 125°C
39.6.4
Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order
to achieve maximum accuracy. Seen externally the ADC input consists of a resistor (RSAMPLE) and a capacitor
(CSAMPLE). In addition, the source resistance (RSOURCE) must be taken into account when calculating the required
sample and hold time. The next figure shows the ADC input channel equivalent circuit.
Figure 39-3. ADC Input
VDDANA/2
Analog Input
AINx
CSAMPLE
RSOURCE
RSAMPLE
VIN
To achieve n bits of accuracy, the CSAMPLE capacitor must be charged at least to a voltage of
VCSAMPLE ≥ VIN × 1 + − 2− n + 1
The minimum sampling time tSAMPLEHOLD for a given RSOURCEcan be found using this formula:
tSAMPLEHOLD ≥ RSAMPLE + RSOURCE × CSAMPLE × n + 1 × ln 2
39.6.5
for a 12 bits accuracy: tSAMPLEHOLD ≥ RSAMPLE + RSOURCE × CSAMPLE × 9.02
Digital to Analog Converter (DAC) Characteristics
Table 39-19. Operating Conditions(1)(Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDDANA
Analog supply voltage
-
1.62
-
3.63
V
AVREF
External reference voltage
-
1.0
-
VDDANA-0.6
V
INT1V(3)
-
-
1
-
V
VDDANA
-
-
VDDANA
-
V
Linear output voltage range
-
0.05
-
VDDANA-0.05
V
Minimum resistive load
-
5
-
-
kΩ
Maximum capacitance load
-
-
-
100
pF
DC supply current(2)
Voltage pump disabled
-
160
242
μA
Conditions
Min.
Typ.
Max.
Units
-
1.62
-
3.63
V
IDD
Table 39-20. Operating Conditions(1)(Device Variant B, C, D and L)
Symbol
Parameter
VDDANA
Analog supply voltage
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Complete Datasheet
DS40001882H-page 950
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
AVREF
IDD
Conditions
Min.
Typ.
Max.
Units
External reference voltage
-
1.0
-
VDDANA-0.6
V
INT1V(3)
-
-
1
-
V
VDDANA
-
-
VDDANA
-
V
Linear output voltage range
-
0.05
-
VDDANA-0.05
V
Minimum resistive load
-
5
-
-
kΩ
Maximum capacitance load
-
-
-
100
pF
Voltage pump disabled
-
160
283
μA
DC supply current(2)
Notes:
1. These values are based on specifications otherwise noted.
2. These values are based on characterization, and are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 39-21. Clock and Timing(1)
Symbol
Parameter
Conditions
Conversion rate
Cload = 100 pF
Rload > 5 kΩ
Startup time
Min.
Typ.
Max.
Units
Normal mode
-
-
350
ksps
For ΔDATA = +/-1
-
-
1000
VDDNA > 2.6V
-
-
2.85
μs
VDDNA < 2.6V
-
-
10
μs
Note:
1. These values are based on simulation, and are not covered by test limits in production or characterization.
Table 39-22. Accuracy Characteristics(1)(Device Variant A)
Symbol
Parameter
Conditions
RES
Input resolution
-
INL
Integral non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
DNL
Differential non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
GE
Gain error
© 2021 Microchip Technology Inc.
and its subsidiaries
Min.
Typ.
Max.
Units
-
-
10
Bits
VDD = 1.6V
0.75
1.1
2.0
LSB
VDD = 3.6V
0.6
1.2
2.5
VDD = 1.6V
1.4
2.2
3.5
VDD = 3.6V
0.9
1.4
1.5
VDD = 1.6V
0.75
1.3
2.5
VDD = 3.6V
0.8
1.2
1.5
VDD = 1.6V
+/-0.9
+/-1.2
+/-2.0
VDD = 3.6V
+/-0.9
+/-1.1
+/-1.5
VDD = 1.6V
+/-1.1
+/-1.7
+/-3.0
VDD = 3.6V
+/-1.0
+/-1.1
+/-1.6
VDD = 1.6V
+/-1.1
+/-1.4
+/-2.5
VDD = 3.6V
+/-1.0
+/-1.5
+/-1.8
+/-1.0
+/-5
+/-10
Ext. VREF
Complete Datasheet
LSB
mV
DS40001882H-page 951
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
OE
Offset error
Ext. VREF
+/-2
+/-3
+/-8
mV
Table 39-23. Accuracy Characteristics(1)(Device Variant B, C, D and L)
Symbol
Parameter
Conditions
RES
Input resolution
-
INL
Integral non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
DNL
Differential non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
Min.
Typ.
Max.
Units
-
-
10
Bits
VDD = 1.6V
0.7
0.75
2.0
LSB
VDD = 3.6V
0.6
0.65
1.5
VDD = 1.6V
0.6
0.85
2.0
VDD = 3.6V
0.5
0.8
1.5
VDD = 1.6V
0.5
0.75
1.5
VDD = 3.6V
0.7
0.8
1.5
VDD = 1.6V
+/-0.3
+/-0.4
+/-1.0
VDD = 3.6V
+/-0.25
+/-0.4
+/-0.75
VDD = 1.6V
+/-0.4
+/-0.55
+/-1.5
VDD = 3.6V
+/-0.2
+/-0.3
+/-0.75
VDD = 1.6V
+/-0.5
+/-0.7
+/-1.5
VDD = 3.6V
+/-0.4
+/-0.7
+/-1.5
LSB
GE
Gain error
Ext. VREF
+/-0.5
+/-5
+/-12
mV
OE
Offset error
Ext. VREF
+/-2
+/-1.5
+/-8
mV
Note:
1. All values measured using a conversion rate of 35 ksps.
39.6.6
Analog Comparator Characteristics
Table 39-24. Electrical and Timing (Device Variant A)
Symbol
Parameter
Min.
Typ.
Max.
Units
Positive input voltage range
0
-
VDDANA
V
Negative input voltage range
0
-
VDDANA
Hysteresis = 0, Fast mode
-15
0.0
+15
mV
Hysteresis = 0, Low power mode
-25
0.0
+25
mV
Hysteresis = 1, Fast mode
20
50
83
mV
Hysteresis = 1, Low power mode
15
40
75
mV
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
-
60
116
ns
Changes for VACM=VDDANA/2
100mV overdrive, Low power mode
-
225
370
ns
Offset
Hysteresis
Propagation delay
© 2021 Microchip Technology Inc.
and its subsidiaries
Conditions
Complete Datasheet
DS40001882H-page 952
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
tSTARTUP
Startup time
Enable to ready delay
Fast mode
-
1
2
μs
Enable to ready delay
Low power mode
-
12
19
μs
INL(3)
-
0.75
+1.58
LSB
DNL(3)
-
0.25
+0.95
LSB
VSCALE
Offset Error (1)(2)
-0.200 0.260 +1.035
LSB
0.55
1.2
2.0
LSB
Min.
Typ.
Max.
Units
Positive input voltage range
0
-
VDDANA
V
Negative input voltage range
0
-
VDDANA
Hysteresis = 0, Fast mode
-15
0.0
+15
mV
Hysteresis = 0, Low power mode
-25
0.0
+25
mV
Hysteresis = 1, Fast mode
20
50
90
mV
Hysteresis = 1, Low power mode
15
40
75
mV
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
-
90
180
ns
Changes for VACM=VDDANA/2
100mV overdrive, Low power mode
-
282
520
ns
Enable to ready delay
Fast mode
-
1
2.6
μs
Enable to ready delay
Low power mode
-
14
22
μs
-
0.75
+1.58
LSB
-
0.25
+0.95
LSB
Gain Error
(1)(2)
Table 39-25. Electrical and Timing (Device Variant B, C, D and L)
Symbol
Parameter
Conditions
Offset
Hysteresis
Propagation delay
tSTARTUP
VSCALE
Startup time
INL(3)
DNL(3)
Offset Error
(1)(2)
Gain Error (1)(2)
-0.200 0.260 +1.035
LSB
0.55
LSB
1.2
2.0
Notes:
1. According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2. Data computed with the Best Fit method
3. Data computed using histogram
39.6.7
Temperature Sensor Characteristics
Table 39-26. Temperature Sensor Characteristics(1)(Device Variant A)
Symbol Parameter
Temperature sensor
output voltage
© 2021 Microchip Technology Inc.
and its subsidiaries
Conditions
Min.
Typ.
T= 25°C, VDDANA = 3.3V
-
0.667 -
Complete Datasheet
Max. Units
V
DS40001882H-page 953
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Temperature sensor
slope
Min.
Typ.
Max. Units
2.2
2.4
2.7
mV/°C
1
14
mV/V
Variation over VDDANA
voltage
VDDANA=1.62V to 3.6V
-9
Temperature Sensor
accuracy
Using the method described in the
37.11.8.2 Software-based Refinement of the
Actual Temperature
-13.0 -
13.0 °C
Conditions
Min.
Typ.
Max. Units
T= 25°C, VDDANA = 3.3V
-
0.688 -
2.06
2.16
2.26 mV/°C
1.4
3
Table 39-27. Temperature Sensor Characteristics(1)(Device Variant B, C, D and L)
Symbol Parameter
Temperature sensor
output voltage
Temperature sensor
slope
Variation over VDDANA
voltage
VDDANA=1.62V to 3.6V
-0.4
Temperature Sensor
accuracy
Using the method described in the
37.11.8.2 Software-based Refinement of the
Actual Temperature
-13.0 -
V
mV/V
13.0 °C
Note: 1. These values are based on characterization. These values are not covered by test limits in production.
39.7
NVM Characteristics
Table 39-28. Maximum Operating Frequency
VDD range
NVM Wait States
Maximum Operating Frequency
Units
1.62V to 2.7V
0
14
MHz
1
28
2
40
0
24
1
40
2.7V to 3.63V
Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 39-29. Flash Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
CycNVM
Cycling Endurance(1)
-40°C < Ta < 125°C
25k
150k
-
Cycles
Note: 1. An endurance cycle is a write and an erase operation.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 954
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-30. EEPROM Emulation(1) Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetEEPROM100k
Retention after up to 100k
Average ambient 55°C
10
50
-
Years
RetEEPROM10k
Retention after up to 10k
Average ambient 55°C
20
100
-
Years
CycEEPROM
Cycling Endurance(2)
-40°C < Ta < 125°C
100k
600k
-
Cycles
Notes: 1. The EEPROM emulation is a software emulation described in the App note AT03265.
2. An endurance cycle is a write and an erase operation.
39.8
Oscillators Characteristics
39.8.1
Crystal Oscillator (XOSC) Characteristics
39.8.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 39-31. Digital Clock Characteristics
Symbol
Parameter
fCPXIN
XIN clock frequency
Conditions
Min.
Typ.
Max.
Units
-
-
32
MHz
39.8.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT . The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in
the table. The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
Table 39-32. Crystal Oscillator Characteristics (Device Variant A)
Symbol Parameter
fOUT
Conditions
Crystal oscillator frequency
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
Min. Typ. Max.
Units
0.4
MHz
-
32
DS40001882H-page 955
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Min. Typ. Max.
Units
ESR
f = 0.455 MHz, CL = 100pF
XOSC.GAIN = 0
-
-
5.6K
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
-
-
416
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
-
-
243
f = 8 MHz, CL = 20pF
XOSC.GAIN = 2
-
-
138
f = 16 MHz, CL = 20pF
XOSC.GAIN = 3
-
-
66
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
-
-
56
Crystal Equivalent Series Resistance
Safety Factor = 3
The AGC doesn’t have any noticeable
impact on these measurements.
CXIN
Parasitic capacitor load
-
5.9
-
pF
CXOUT
Parasitic capacitor load
-
3.2
-
pF
f = 2MHz, CL = 20pF, AGC off
27
65
90
μA
f = 2MHz, CL = 20pF, AGC on
14
52
79
f = 4MHz, CL = 20pF, AGC off
61
117
161
f = 4MHz, CL = 20pF, AGC on
23
74
110
f = 8MHz, CL = 20pF, AGC off
131
226
319
f = 8MHz, CL = 20pF, AGC on
56
128
193
f = 16MHz, CL = 20pF, AGC off 305
502
742
f = 16MHz, CL = 20pF, AGC on 116
307
627
Current Consumption
f = 32MHz, CL = 18pF, AGC off 1031 1622 2344
tSTARTUP Start-up time
f = 32MHz, CL = 18pF, AGC on 278
615
1422
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
-
14K
48K
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
-
6800 19.5K
f = 8 MHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
-
5550 13K
f = 16 MHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
-
6750 14.5K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
-
5.3K 9.6K
cycles
Table 39-33. Crystal Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
fOUT
Conditions
Crystal oscillator frequency
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
Min. Typ. Max.
Units
0.4
MHz
-
32
DS40001882H-page 956
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Min. Typ. Max.
Units
ESR
f = 0.455 MHz, CL = 100pF
XOSC.GAIN = 0
-
-
5.6K
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
-
-
416
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
-
-
243
f = 8 MHz, CL = 20pF
XOSC.GAIN = 2
-
-
138
f = 16 MHz, CL = 20pF
XOSC.GAIN = 3
-
-
66
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
-
-
56
Crystal Equivalent Series Resistance
Safety Factor = 3
The AGC doesn’t have any noticeable
impact on these measurements.
CXIN
Parasitic capacitor load
-
5.9
-
pF
CXOUT
Parasitic capacitor load
-
3.2
-
pF
f = 2MHz, CL = 20pF, AGC off
27
65
90
μA
f = 2MHz, CL = 20pF, AGC on
14
52
79
f = 4MHz, CL = 20pF, AGC off
61
117
160
f = 4MHz, CL = 20pF, AGC on
23
74
110
f = 8MHz, CL = 20pF, AGC off
131
226
319
f = 8MHz, CL = 20pF, AGC on
56
128
193
f = 16MHz, CL = 20pF, AGC off 305
502
741
f = 16MHz, CL = 20pF, AGC on 116
307
626
Current Consumption
f = 32MHz, CL = 18pF, AGC off 1031 1622 2344
tSTARTUP Start-up time
© 2021 Microchip Technology Inc.
and its subsidiaries
f = 32MHz, CL = 18pF, AGC on 278
615
1400
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
-
14K
48K
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
-
6800 19.5K
f = 8 MHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
-
5550 13K
f = 16 MHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
-
6750 14.5K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
-
5.3K 9.6K
Complete Datasheet
cycles
DS40001882H-page 957
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Figure 39-4. Oscillator Connection
Xin
C LEXT
Crystal
LM
C SHUNT
RM
C STRAY
CM
Xout
C LEXT
39.8.2
External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
39.8.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 39-34. Digital Clock Characteristics
Symbol
Parameter
fCPXIN32
Conditions
Min.
Typ.
Max.
Units
XIN32 clock frequency
-
32.768
-
kHz
XIN32 clock duty cycle
-
50
-
%
39.8.2.2 Crystal Oscillator Characteristics
Figure 37-6 and the equation in also applies to the 32 kHz oscillator connection. The user must choose a crystal
oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be
found in the crystal data sheet.
Table 39-35. 32kHz Crystal Oscillator Characteristics (Device Variant A)
Symbol Parameter
fOUT
Conditions
Crystal oscillator frequency
tSTARTUP Startup time
ESRXTAL = 39.9 kΩ, CL = 12.5
pF
Min. Typ.
Max. Units
-
32768 -
Hz
-
28K
31K
cycles
CL
Crystal load capacitance
-
-
12.5 pF
CSHUNT
Crystal shunt capacitance
-
0.1
-
CXIN32
Parasitic capacitor load
-
3.1
-
CXOUT32 Parasitic capacitor load
-
3.3
-
IXOSC32K Current consumption
-
1.22
2.44 µA
-
-
141
ESR
Crystal equivalent series resistance
f=32.768kHz
, Safety Factor = 3
© 2021 Microchip Technology Inc.
and its subsidiaries
TQFP64/48/32 packages
CL=12.5pF
Complete Datasheet
kΩ
DS40001882H-page 958
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-36. 32kHz Crystal Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
fOUT
Conditions
Crystal oscillator frequency
tSTARTUP Startup time
ESRXTAL = 39.9 kΩ, CL = 12.5
pF
Max. Units
-
32768 -
Hz
-
28K
30K
cycles
CL
Crystal load capacitance
-
-
12.5 pF
CSHUNT
Crystal shunt capacitance
-
0.1
-
CXIN32
Parasitic capacitor load
-
3.2
-
CXOUT32 Parasitic capacitor load
-
3.7
-
IXOSC32K Current consumption
-
1.22
2.2
µA
-
-
100
kΩ
ESR
39.8.3
Min. Typ.
TQFP64/48/32 packages
Crystal equivalent series resistance
f=32.768kHz
, Safety Factor = 3
CL=12.5pF
Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 39-37. DFLL48M Characteristics - Open Loop Mode(1)(Device Variant A)
Symbol Parameter
Conditions
fOUT
Output frequency
IDFLLVAL.COARSE = DFLL48M COARSE CAL 47
DFLLVAL.FINE = 512
IDFLL
Power consumption on VDDIN IDFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512
tSTARTUP Start-up time
Min. Typ. Max. Units
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
7
48
49
MHz
403
457
μA
8
9
μs
fOUT within 90 % of final value
Table 39-38. DFLL48M Characteristics - Open Loop Mode(1)(Device Variant B, C, D and L)
Symbol Parameter
Conditions
fOUT
Output frequency
IDFLLVAL.COARSE = DFLL48M COARSE CAL 47
DFLLVAL.FINE = 512
IDFLL
Power consumption on VDDIN IDFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512
tSTARTUP Start-up time
Min. Typ. Max. Units
48
49
MHz
403
453
μA
-
8
9
μs
Min.
Typ.
Max.
Units
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
fOUT within 90 % of final value
Note: 1. DFLL48M in Open loop after calibration at room temperature.
Table 39-39. DFLL48M Characteristics - Closed Loop Mode(1)(Device Variant A)
Symbol Parameter
Conditions
fOUT
Average Output frequency fREF = 32 .768kHz
47.76 48
fREF
Reference frequency
0.732 32.768 33
kHz
Jitter
Cycle to Cycle jitter
-
ns
© 2021 Microchip Technology Inc.
and its subsidiaries
fREF = 32 .768kHz
Complete Datasheet
-
48.24 MHz
1.04
DS40001882H-page 959
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
IDFLL
Power consumption on
VDDIN
fREF = 32 .768kHz
-
425
482
μA
tLOCK
Lock time
fREF = 32 .768kHz
100
DFLLVAL.COARSE = DFLL48M COARSE CAL
200
500
μs
Max.
Units
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Table 39-40. DFLL48M Characteristics - Closed Loop Mode(1)(Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min.
Typ.
fOUT
Average Output frequency fREF = 32 .768kHz
47.76 48
48.24 MHz
fREF
Reference frequency
0.732 32.768 33
kHz
Jitter
Cycle to Cycle jitter
fREF = 32 .768kHz
-
-
0.42
ns
IDFLL
Power consumption on
VDDIN
fREF = 32 .768kHz
-
403
453
μA
tLOCK
Lock time
fREF = 32 .768kHz
DFLLVAL.COARSE = DFLL48M COARSE CAL
200
500
μs
Typ.
Max.
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
39.8.4
32.768 kHz Internal oscillator (OSC32K) Characteristics
Table 39-41. 32 kHz RC Oscillator Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min.
fOUT
Calibrated against a 32.768 kHz reference at
25°C, over [-40, +125]°C, over [1.62, 3.63]V
28.508 32.768 35.389 kHz
Calibrated against a 32.768 kHz reference at
25°C, at VDD = 3.3V
32.276 32.768 33.260
Calibrated against a 32.768 kHz reference at
25°C, over [1.62, 3.63]V
31.457 32.768 34.079
IOSC32K
Output frequency
Current consumption
Units
-
0.79
1.80
μA
tSTARTUP Start-up time
-
1
2
cycle
Duty
-
50
-
%
Duty Cycle
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and its subsidiaries
Complete Datasheet
DS40001882H-page 960
SAM D21/DA1 Family
Electrical Characteristics at 125°C
Table 39-42. 32 kHz RC Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min.
fOUT
Calibrated against a 32.768 kHz reference at
25°C, over [-40, +125]°C, over [1.62, 3.63]V
28.508 32.768 35.389 kHz
Calibrated against a 32.768 kHz reference at
25°C, at VDD = 3.3V
32.276 32.768 33.260
Calibrated against a 32.768 kHz reference at
25°C, over [1.62, 3.63]V
31.457 32.768 34.079
IOSC32K
39.8.5
Output frequency
Current consumption
Typ.
Max.
Units
-
0.67
2.80
μA
tSTARTUP Start-up time
-
1
2
cycle
Duty
-
50
-
%
Max.
Units
Duty Cycle
Ultra Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Characteristics
Table 39-43. Ultra Low-Power Internal 32 kHz RC Oscillator Characteristics (Device Variant A)
Symbol
Parameter
Conditions
Min.
fOUT
Output frequency Calibrated against a 32.768 kHz reference at
25°C, over [-40, +125]°C, over [1.62, 3.63]V
Typ.
25.559 32.768 40.305 kHz
Calibrated against a 32.768 kHz reference at
25°C, at VDD = 3.3V
31.293 32.768 34.570
Calibrated against a 32.768 kHz reference at
25°C, over [1.62, 3.63]V
31.293 32.768 34.570
iOSCULP32K(1)(2)
-
-
180
nA
tSTARTUP
Start-up time
-
10
-
cycles
Duty
Duty Cycle
-
50
-
%
Table 39-44. Ultra Low-Power Internal 32 kHz RC Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
fOUT
Conditions
Min.
Output frequency Calibrated against a 32.768 kHz reference at 25°C,
over [-40, +125]°C, over [1.62, 3.63]V
Typ.
Max.
Units
25.559 32.768 40.305 kHz
Calibrated against a 32.768 kHz reference at 25°C, at 31.293 32.768 34.570
VDD = 3.3V
Calibrated against a 32.768 kHz reference at 25°C,
over [1.62, 3.63]V
Duty
Duty Cycle
31.293 32.768 34.570
-
50
-
%
Notes:
1. These values are based on simulation, and are not covered by test limits in production or characterization.
2. This oscillator is always on.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 961
SAM D21/DA1 Family
Electrical Characteristics at 125°C
39.8.6
8MHz RC Oscillator (OSC8M) Characteristics
Table 39-45. Internal 8MHz RC Oscillator Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min. Typ. Max. Units
fOUT
Calibrated against a 8MHz reference at 25°C, over [-40,
+125]°C, over [1.62, 3.63]V
7.54 8
8.19 MHz
Calibrated against a 8MHz reference at 25°C, at
VDD=3.3V
7.94 8
8.06
Calibrated against a 8MHz reference at 25°C, over
[1.62, 3.63]V
7.92 8
8.08
IOSC8M
Output frequency
Current consumption IIDLEIDLE2 on OSC32K versus IDLE2 on calibrated
OSC8M enabled at 8MHz (FRANGE=1, PRESC=0)
64
100
μA
tSTARTUP Startup time
-
2.1
3
μs
Duty
-
50
-
%
Duty cycle
Table 39-46. Internal 8MHz RC Oscillator Characteristics (Device Variant B, C, D and L)
Symbol Parameter
Conditions
Min. Typ. Max. Units
fOUT
Calibrated against a 8MHz reference at 25°C, over [-40,
+125]°C, over [1.62, 3.63]V
7.54 8
8.19 MHz
Calibrated against a 8MHz reference at 25°C, at
VDD=3.3V
7.94 8
8.06
Calibrated against a 8MHz reference at 25°C, over
[1.62, 3.63]V
7.92 8
8.06
IOSC8M
39.8.7
Output frequency
Current consumption IIDLEIDLE2 on OSC32K versus IDLE2 on calibrated
OSC8M enabled at 8MHz (FRANGE=1, PRESC=0)
64
96
μA
tSTARTUP Startup time
-
2.4
3.3
μs
Duty
-
50
-
%
Duty cycle
Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 39-47. FDPLL96M Characteristics(1) (Device Variant A)
Symbol
Parameter
fIN
Min.
Typ.
Max.
Units
Input frequency
32
-
2000
KHz
fOUT
Output frequency
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
-
500
700
μA
fIN= 32 kHz, fOUT= 96 MHz
-
900
1200
fIN= 32 kHz, fOUT= 48 MHz
-
1.5
2.0
fIN= 32 kHz, fOUT= 96 MHz
-
3.0
10.0
fIN= 2 MHz, fOUT= 48 MHz
-
1.3
2.0
fIN= 2 MHz, fOUT= 96 MHz
-
3.0
7.0
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
1.3
2
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
μs
Jp
tLOCK
Period jitter
Lock Time
© 2021 Microchip Technology Inc.
and its subsidiaries
Conditions
Complete Datasheet
%
DS40001882H-page 962
SAM D21/DA1 Family
Electrical Characteristics at 125°C
...........continued
Symbol
Parameter
Duty
Duty cycle
Conditions
Min.
Typ.
Max.
Units
40
50
60
%
Table 39-48. FDPLL96M Characteristics(1) (Device Variant B and L with Silicon Revision E)
Symbol
Parameter
fIN
Min.
Typ.
Max.
Units
Input frequency
32
-
2000
KHz
fOUT
Output frequency
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
-
500
740
μA
fIN= 32 kHz, fOUT= 96 MHz
-
900
1262
fIN= 32 kHz, fOUT= 48 MHz
-
1.5
2.5
fIN= 32 kHz, fOUT= 96 MHz
-
4.0
10.5
fIN= 2 MHz, fOUT= 48 MHz
-
1.6
2.5
fIN= 2 MHz, fOUT= 96 MHz
-
4.6
11.0
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
1.2
2
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
μs
40
50
60
%
Jp
tLOCK
Duty
Period jitter
Lock Time
Conditions
Duty cycle
%
Table 39-49. FDPLL96M Characteristics(1) (Device Variant B, C, D and L with Silicon Revision F and G)
Symbol
Parameter
fIN
Min.
Typ.
Max.
Units
Input frequency
32
-
2000
KHz
fOUT
Output frequency
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
-
500
-
μA
fIN= 32 kHz, fOUT= 96 MHz
-
900
-
fIN= 32 kHz, fOUT= 48 MHz
-
2.1
3.2
fIN= 32 kHz, fOUT= 96 MHz
-
3.8
9.2
fIN= 2 MHz, fOUT= 48 MHz
-
2.2
3.4
fIN= 2 MHz, fOUT= 96 MHz
-
5.0
10.5
After start-up, time to get lock signal.
fIN= 32 kHz, fOUT= 96 MHz
-
1.2
2
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
μs
40
50
60
%
Jp
tLOCK
Duty
Period jitter
Lock Time
Conditions
Duty cycle
%
Note:
1. All values have been characterized with FILTSEL[1/0] as default value.
39.8.8
PTC Characteristics at 125°C
The values in the Power Consumption table below are measured values of power consumption under the following
conditions:
Operating Conditions
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 963
SAM D21/DA1 Family
Electrical Characteristics at 125°C
VDD = 3.3V
Clocks
OSC8M used as main clock source, running undivided at 8MHz
CPU is running on flash with 0 wait states, at 8MHz
PTC is running at 4MHz
PTC Configuration
Mutual-capacitance mode
One touch channel
System Configuration
Standby sleep mode enabled
RTC running on OSCULP32K: used to define the PTC scan rate, through the event system
Drift Calibration disabled: no interrupts, PTC scans are performed in standby mode
Drift Calibration enabled: RTC interrupts (wakeup) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
Table 39-50. Power Consumption (1)
Symbol
Parameters
Drift
Calibration
PTC scan
rate
(msec)
Oversamples
10
50
Disabled
100
200
IDD (2)
Current
Consumption
10
50
Enabled
100
200
Ta
Typ. Max Units
4
66
791
16
75
803
4
61
787
16
63
791
4
61
788
16
62
790
4
60
788
61
789
71
802
16
80
813
4
63
792
16
65
795
4
62
791
16
63
793
4
62
790
16
63
791
16
4
Max 125°C Typ
25°C
µA
Notes:
1. These are based on characterization.
2. On this table, the LDO Voltage Regulator is enabled in Standby mode (SYSCTRL.VREG.RUNSTDBY = 1).
39.8.9
USB Characteristics
The USB shares the same characteristics as in the -40°C to 85°C.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 964
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
40.
AEC-Q100 125°C Specifications
40.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
40.2
Thermal Considerations
40.2.1
Thermal Resistance Data
The following Table summarizes the thermal resistance data depending on the package.
Table 40-1. Thermal Resistance Data
40.2.2
Package Type
θJA
θJC
32-pin QFN (Wettable Flanks)
40.5°C/W
16.0°C/W
48-pin QFN (Wettable Flanks)
31.9°C/W
11.7°C/W
64-pin QFN (Wettable Flanks)
32.5°C/W
11.3°C/W
32-pin TQFP
64.7°C/W
23.1°C/W
48-pin TQFP
63.6°C/W
12.2°C/W
64-pin TQFP
60.9°C/W
12.2°C/W
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
TJ = TA + (PD x θJA)
TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is
necessary or not. If a cooling device has to be fitted on the chip, the second equation should be used to compute the
resulting average chip-junction temperature TJ in °C.
40.3
Absolute Maximum Ratings
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 965
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-2. Absolute Maximum Ratings
Symbol
Description
VDD
Conditions
Min.
Max.
Units
Power Supply Voltage
0
3.8
V
IVDD
Current into a VDD pin
-
28 (1)
mA
IGND
Current out of a GND pin
-
39 (1)
mA
VPIN
Pin voltage with respect to GND and VDD
GND-0.3V
VDD+0.3V
V
TSTORAGE
Storage temperature
-60
150
°C
Note:
1. Maximum source current is 14mA and maximum sink current is 19.5mA per cluster. A cluster is a group
of GPIOs, see related links. Also note that each VDD/GND pair is connected to 2 clusters so current
consumption through the pair will be a sum of the clusters source/sink currents.
Related Links
GPIO Clusters
40.4
General Operating Ratings
The device must operate within the ratings listed in the following table in order for all other electrical characteristics
and typical characteristics of the device to be valid.
Table 40-3. General Operating Conditions
40.5
Symbol
Description
VDD
Conditions
Min.
Typ.
Max.
Units
Power Supply Voltage
2.7
3.3
3.63
V
VDDANA
Analog supply voltage
2.7
3.3
3.63
V
TA
Temperature range
-40
25
125
°C
TJ
Junction Temperature
-
-
145
°C
Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 125°C, unless
otherwise specified and are valid for a junction temperature up to TJ = 145°C.
Table 40-4. Supply Characteristics
Symbol
Conditions
Voltage
Min
Units
Max
VDDIO
VDDIN
Full Voltage Range
2.7
3.63
V
VDDANA
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and its subsidiaries
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-5. Supply Rates
Fall Rate Rise Rate
Symbol Conditions
Max
Max
Units
VDDIO
VDDIN
DC supply peripheral I/Os, internal regulator and analog supply voltage
0.05
0.1
V/μs
VDDANA
Note: To secure power up and power down sequence, enabling BOD33 is recommended.
Related Links
Power Supply and Start-Up Considerations
40.6
Maximum Clock Frequencies
Table 40-6. Maximum GCLK Generator Output Frequencies (Device Variant A)
Symbol
Description
Conditions
Max
Units
fGCLKGEN0 / fGCLK_MAIN
GCLK Generator Output Frequency
Undivided
64
MHz
Divided
32
MHz
fGCLKGEN1
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
Table 40-7. Maximum Peripheral Clock Frequencies (Device Variant A)
Symbol
Description
Max.
Units
fCPU
CPU clock frequency
32
MHz
fAHB
AHB clock frequency
32
MHz
fAPBA
APBA clock frequency
32
MHz
fAPBB
APBB clock frequency
32
MHz
fAPBC
APBC clock frequency
32
MHz
fGCLK_DFLL48M_REF
DFLL48M Reference clock frequency
33
kHz
fGCLK_DPLL
FDPLL96M Reference clock frequency
2
MHz
fGCLK_DPLL_32K
FDPLL96M 32k Reference clock frequency
32
kHz
fGCLK_WDT
WDT input clock frequency
48
MHz
fGCLK_RTC
RTC input clock frequency
48
MHz
fGCLK_EIC
EIC input clock frequency
48
MHz
fGCLK_USB
USB input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_0
EVSYS channel 0 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_1
EVSYS channel 1 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_2
EVSYS channel 2 input clock frequency
48
MHz
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Description
Max.
Units
fGCLK_EVSYS_CHANNEL_3
EVSYS channel 3 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_4
EVSYS channel 4 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_5
EVSYS channel 5 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_6
EVSYS channel 6 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_7
EVSYS channel 7 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_8
EVSYS channel 8 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_9
EVSYS channel 9 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_10
EVSYS channel 10 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_11
EVSYS channel 11 input clock frequency
48
MHz
fGCLK_SERCOMx_SLOW
Common SERCOM slow input clock frequency
48
MHz
fGCLK_SERCOM0_CORE
SERCOM0 input clock frequency
48
MHz
fGCLK_SERCOM1_CORE
SERCOM1 input clock frequency
48
MHz
fGCLK_SERCOM2_CORE
SERCOM2 input clock frequency
48
MHz
fGCLK_SERCOM3_CORE
SERCOM3 input clock frequency
48
MHz
fGCLK_SERCOM4_CORE
SERCOM4 input clock frequency
48
MHz
fGCLK_SERCOM5_CORE
SERCOM5 input clock frequency
48
MHz
fGCLK_TCC0, fGCLK_TCC1
TCC0, TCC1 input clock frequency
80
MHz
fGCLK_TCC2, fGCLK_TC3
TCC2,TC3 input clock frequency
80
MHz
fGCLK_TC4, fGCLK_TC5
TC4, TC5 input clock frequency
48
MHz
fGCLK_TC6, fGCLK_TC7
TC6,TC7 input clock frequency
48
MHz
fGCLK_ADC
ADC input clock frequency
48
MHz
fGCLK_AC_DIG
AC digital input clock frequency
48
MHz
fGCLK_AC_ANA
AC analog input clock frequency
64
kHz
fGCLK_DAC
DAC input clock frequency
48
MHz
fGCLK_PTC
PTC input clock frequency
48
MHz
fGCLK_I2S_0
I2S serial 0 input clock frequency
13
MHz
fGCLK_I2S_1
I2S serial 1 input clock frequency
13
MHz
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-8. Maximum GCLK Generator Output Frequencies (Device Variant B, D)
Symbol
Description
Conditions
Max
Units
fGCLKGEN0 /
fGCLK_MAIN
GCLK Generator
Output Frequency
Undivided
96
MHz
Divided
48
MHz
fGCLKGEN1
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
Table 40-9. Maximum Peripheral Clock Frequencies (Device Variant B, D)
Symbol
Description
Max.
Units
fCPU
CPU clock frequency
48
MHz
fAHB
AHB clock frequency
48
MHz
fAPBA
APBA clock frequency
48
MHz
fAPBB
APBB clock frequency
48
MHz
fAPBC
APBC clock frequency
48
MHz
fGCLK_DFLL48M_REF
DFLL48M Reference clock frequency
33
KHz
fGCLK_DPLL
FDPLL96M Reference clock frequency
2
MHz
fGCLK_DPLL_32K
FDPLL96M 32k Reference clock frequency
32
KHz
fGCLK_WDT
WDT input clock frequency
48
MHz
fGCLK_RTC
RTC input clock frequency
48
MHz
fGCLK_EIC
EIC input clock frequency
48
MHz
fGCLK_USB
USB input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_0
EVSYS channel 0 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_1
EVSYS channel 1 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_2
EVSYS channel 2 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_3
EVSYS channel 3 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_4
EVSYS channel 4 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_5
EVSYS channel 5 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_6
EVSYS channel 6 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_7
EVSYS channel 7 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_8
EVSYS channel 8 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_9
EVSYS channel 9 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_10
EVSYS channel 10 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_11
EVSYS channel 11 input clock frequency
48
MHz
fGCLK_SERCOMx_SLOW
Common SERCOM slow input clock frequency
48
MHz
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 969
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
40.7
Symbol
Description
Max.
Units
fGCLK_SERCOM0_CORE
SERCOM0 input clock frequency
48
MHz
fGCLK_SERCOM1_CORE
SERCOM1 input clock frequency
48
MHz
fGCLK_SERCOM2_CORE
SERCOM2 input clock frequency
48
MHz
fGCLK_SERCOM3_CORE
SERCOM3 input clock frequency
48
MHz
fGCLK_SERCOM4_CORE
SERCOM4 input clock frequency
48
MHz
fGCLK_SERCOM5_CORE
SERCOM5 input clock frequency
48
MHz
fGCLK_TCC0, GCLK_TCC1
TCC0, TCC1 input clock frequency
96
MHz
fGCLK_TCC2,fGCLK_TCC3, GCLK_TC3
TCC2, TCC3, TC3 input clock frequency
96
MHz
fGCLK_TC4, GCLK_TC5
TC4, TC5 input clock frequency
48
MHz
fGCLK_TC6, GCLK_TC7
TC6,TC7 input clock frequency
48
MHz
fGCLK_ADC
ADC input clock frequency
48
MHz
fGCLK_AC_DIG
AC digital input clock frequency
48
MHz
fGCLK_AC_ANA
AC analog input clock frequency
64
kHz
fGCLK_DAC
DAC input clock frequency
48
MHz
fGCLK_PTC
PTC input clock frequency
48
MHz
fGCLK_I2S_0
I2S
serial 0 input clock frequency
13
MHz
fGCLK_I2S_1
I2S serial 1 input clock frequency
13
MHz
Power Consumption
The values provided in the following table are measured values of power consumption, which are valid under the
following conditions, except where noted:
•
•
•
•
•
•
•
•
Operating conditions:
– VDDIN = 3.3V
Wake up time from Sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in Flash.
Oscillators:
– XOSC (Crystal scillator) stopped
– XOSC32K (32 kHz Crystal Oscillator) running with external 32 kHz crystal
– DFLL48M using XOSC32K as reference and running at 48 MHz
Clocks:
– DFLL48M used as main clock source, except otherwise specified.
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
CPU is running on Flash with 1 wait states
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
•
•
NVMCTRL cache enabled
BOD33 disabled
Table 40-10. Current Consumption (Device Variant A)
Mode
Conditions
TA
VCC Typ.
Max.
Units
ACTIVE
CPU running a While 1 algorithm
25°C
3.3V 3.4
3.9
mA
125°C
3.3V 3.8
6.1
CPU running a While 1 algorithm, 25°C
with
125°C
GCLKIN as reference
3.3V 60*Freq+136
81*Freq+126
µA
3.3V 62*Freq+498
70*Freq+1780
(with freq. in
MHz)
CPU running a Fibonacci
algorithm
25°C
3.3V 4.6
5.0
mA
125°C
3.3V 5.0
7.3
CPU running a Fibonacci
algorithm, with
25°C
3.3V 92*Freq+113
99*Freq+141
µA
125°C
3.3V 92*Freq+503
91*Freq+1794
(with freq. in
MHz)
CPU running a CoreMark
algorithm
25°C
3.3V 6.3
6.8
mA
125°C
3.3V 6.7
8.6
CPU running a CoreMark
algorithm, with
25°C
3.3V 118*Freq+116 131*Freq+141
125°C
3.3V 121*Freq+506 122*Freq+1792 (with freq. in
MHz)
25°C
3.3V 2.0
2.2
125°C
3.3V 2.4
4.0
25°C
3.3V 1.5
1.6
125°C
3.3V 1.8
3.3
25°C
3.3V 1.2
1.3
125°C
3.3V 1.5
3.0
25°C
3.3V 4.2
13.3
GCLKIN as reference
GCLKIN as reference
IDLE0
IDLE1
IDLE2
Default operating conditions
Default operating conditions
Default operating conditions
STANDBY (1) XOSC32K running
RTC running at 1kHz
125°C (1) 3.3V 430.6
1128.0
XOSC32K and RTC stopped
25°C
3.3V 2.9
12.2
125°C(1)
3.3V 428.6
1126.0
µA
mA
µA
Note:
1. Measurements done with VREG.bit.RUNSTDBY = 1.
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Complete Datasheet
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-11. Current Consumption (Device Variant B)
Mode
Conditions
TA
Vcc
ACTIVE
CPU running a While 1 algorithm
25°C
CPU running a While 1 algorithm,
with
STANDBY
mA
125°C 3.3V 3.0
3.5
3.3V 52*Freq+108 60*Freq+124
µA
25°C
3.3V 3.3
3.6
125°C 3.3V 3.6
4.1
25°C
mA
3.3V 66*Freq+108 71*Freq+126
µA
GCLKIN as reference
125°C 3.3V 66*Freq+375 62*Freq+1113 (with freq. in
MHz)
CPU running a CoreMark algorithm
25°C
3.3V 4.5
5.0
125°C 3.3V 4.9
5.4
25°C
mA
3.3V 90*Freq+109 97*Freq+125
µA
GCLKIN as reference
125°C 3.3V 92*Freq+376 89*Freq+1103 (with freq. in
MHz)
Default operating conditions
25°C
3.3V 1.5
1.6
125°C 3.3V 1.8
2.4
25°C
3.3V 1.0
1.0
125°C 3.3V 1.2
1.8
25°C
3.3V 0.8
0.8
125°C 3.3V 1.0
1.6
XOSC32K running
25°C
83.0
RTC running at 1kHz
125°C 3,3V 294.0
782.0
XOSC32K and RTC stopped
25°C
82.0
Default operating conditions
(1)
3.1
CPU running a Fibonacci algorithm
Default operating conditions
IDLE2
3.3V 2.7
125°C 3.3V 53*Freq+377 48*Freq+1104 (with freq. in
MHz)
CPU running a CoreMark algorithm,
with
IDLE1
Units
GCLKIN as reference
CPU running a Fibonacci algorithm,
with
IDLE0
Max.
25°C
Typ.
3,3V 61.0
3,3V 60.0
125°C 3,3V 292.0
mA
µA
780.0
Note:
1. Measurements done with VREG.bit.RUNSTDBY = 1.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 972
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-12. Current Consumption (Variant D)
Mode
Conditions
CPU running a While 1 algorithm
CPU running a While 1 algorithm, with
GCLKIN as reference
CPU running a Fibonacci algorithm
ACTIVE
Ta
Vcc
Typ.
Max
25°C
3.3V
2.8
3.1
125°C 3.3V
3.5
4.1
25°C
3.3V 56*Freq+116
Units
mA
60*Freq+131
125°C 3.3V 57*Freq+395 55*Freq+1232
25°C
3.3V
3.7
4.1
125°C 3.3V
4.5
5.1
µA (with freq
in MHz)
mA
CPU running a Fibonacci algorithm, with 25°C 3.3V 74*Freq+116 80*Freq+125 µA (with freq
GCLKIN as reference
in MHz)
125°C 3.3V 75*Freq+397 72*Freq+1231
CPU running a CoreMark algorithm
25°C
3.3V
4.2
4.7
125°C 3.3V
5.1
5.9
mA
CPU running a CoreMark algorithm, with 25°C 3.3V 86*Freq+117 92*Freq+127 µA (with freq
GCLKIN as reference
in MHz)
125°C 3.3V 88*Freq+399 85*Freq+1230
25°C
IDLE0
IDLE1
IDLE2
XOSC32K running RTC running at 1kHz
STANDBY (1)
XOSC32K and RTC stopped
3.3V
1.5
1.7
125°C 3.3V
2.0
2.7
25°C
3.3V
1.0
1.1
125°C 3.3V
1.4
2.1
25°C
3.3V
0.8
0.9
125°C 3.3V
1.1
1.8
25°C
3,3V
61.0
83.0
125°C 3,3V
294.0
782.0
25°C
3,3V
60.0
82.0
125°C 3,3V
292.0
780.0
mA
µA
Note:
1. Measurements done with VREG.bit.RUNSTDBY = 1.
Table 40-13. Wake-Up Time
Mode
Conditions
TA
IDLE0
OSC8M used as main clock source, Cache disabled
IDLE1
OSC8M used as main clock source, Cache disabled
IDLE2
OSC8M used as main clock source, Cache disabled
STANDBY
OSC8M used as main clock source, Cache disabled
125°C
Min.
Typ.
Max.
-
4
-
-
14.9
-
-
15.8
-
-
20.6
-
Units
µs
For Measurement Schematics, refer to Power Supply Schematic.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 973
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
40.8
I/O Pin Characteristics
Table 40-14. Normal I/O Pin Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VIL
Input low-level voltage
VDD=2.7V-3.63V
-
-
0.3*VDD
V
VIH
Input high-level voltage
VDD=2.7V-3.63V
0.55*VDD
-
-
VOL
Output low-level voltage
VDD>2.7V, IOL max.
-
0.1*VDD
0.2*VDD
VOH
Output high-level voltage
VDD>2.7V, IOH max.
0.8*VDD
0.9*VDD
-
IOL
Output low-level current
VDD=2.7V-3V,
-
-
-
PORT.PINCFG.DRVSTR=0
-
-
1
VDD=3V-3.63V,
-
-
-
PORT.PINCFG.DRVSTR=0
-
-
2.5
VDD=2.7V-3V,
-
-
-
PORT.PINCFG.DRVSTR=1
-
-
3
VDD = 3V-3.63V,
-
-
-
PORT.PINCFG.DRVSTR=1
-
-
10
VDD=2.7V-3V,
-
-
-
PORT.PINCFG.DRVSTR=0
-
-
0.7
VDD=3V-3.63V,
-
-
-
PORT.PINCFG.DRVSTR=0
-
-
2
VDD=2.7V-3V,
-
-
-
PORT.PINCFG.DRVSTR=1
-
-
2
VDD=3V-3.63V,
-
-
-
PORT.PINCFG.DRVSTR=1
-
-
7
Load = 20pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=1
-
-
-
Load = 5pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=0
-
-
-
Load = 20pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=1
-
-
-
Load = 5pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=0
-
-
-
Pull-up resistors disabled
-1
+/-0.015
1
IOH
tRISE
tFALL
ILEAK
Output high-level current
Rise time(1)
Fall time(1)
Input leakage current
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
mA
ns
µA
DS40001882H-page 974
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-15. I2C Pins Characteristics in I2C Configuration
Symbol Parameter
Condition
Min.
Typ. Max.
VIL
Input low-level voltage
VDD = 2.7V-3.63V
-
-
VIH
Input high-level voltage
VDD = 2.7V-3.63VI
0.55*VDD -
-
VHYS
Hysteresis of Schmitt trigger inputs
-
0.08*VDD -
-
VOL
Output low-level voltage
VDD> 2.0V
-
-
-
IOL = 3 mA
-
-
0.4
VDD≤2.0V
-
-
-
IOL = 2 mA
-
-
0.2*VDD
Units
0.3*VDD V
CI
Capacitance for each I/O Pin
-
-
-
-
pF
IOL
Output low-level current
VOL = 0.4V
-
-
-
mA
Standard, Fast and HS Modes
3
-
-
VOL = 0.4V
-
-
-
Fast Mode +
20
-
-
VOL = 0.6V
6
-
-
fSCL
SCL clock frequency
-
-
-
3.4
MHz
RP
Value of pull-up resistor
fSCL ≤ 100 kHz
-
-
-
ohms
fSCL > 100 kHz
-
-
-
-
Table 40-16. I2C Pin Characteristics in I/O Configuration
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
RPULL
Pull-up - Pull-down resistance
-
20
40
60
kΩ
VIL
Input low-level voltage
VDD = 2.7V-3.63V
-
-
0.3*VDD V
VIH
Input high-level voltage
VDD = 2.7V-3.63V
0.55*VDD -
VOL
Output low-level voltage
VDD>2.7V, IOL max
-
0.1*VDD 0.2*VDD
VOH
Output high-level voltage
VDD>2.7V, IOH max
0.8*VDD
0.9*VDD -
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
-
DS40001882H-page 975
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
IOL
VDD = 2.7V-3V,
-
-
-
mA
PORT.PINCFG.DRVSTR=0
-
-
1
VDD = 3V-3.63V,
-
-
-
PORT.PINCFG.DRVSTR=0
-
-
2.5
VDD = 2.7V-3V,
-
-
-
PORT.PINCFG.DRVSTR=1
-
-
3
VDD = 3V-3.63V,
-
-
-
PORT.PINCFG.DRVSTR=1
-
-
10
VDD = 2.7V-3V,
-
-
-
PORT.PINCFG.DRVSTR=0
-
-
0.7
VDD = 3V-3.63V,
-
-
-
PORT.PINCFG.DRVSTR=0
-
-
2
VDD = 2.7V-3V,
-
-
-
PORT.PINCFG.DRVSTR = 1
-
-
2
VDD = 3V-3.63V,
-
-
-
PORT.PINCFG.DRVSTR = 1
-
-
7
load = 20 pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=1
-
-
-
Load = 5 pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=0
-
-
-
load = 20 pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR = 1
-
-
-
load = 5 pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR = 0
-
-
-
Pull-up resistors disabled
-1
+/-0.015
1
IOH
tRISE
tFALL
ILEAK
Output low-level current
Output high-level current
Rise time(1)
Fall
time(1)
Input leakage current
ns
µA
Table 40-17. PA24/PA25 Pins Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RPULL
Pull-up - Pull-down resistance
-
20
40
60
kΩ
VIL
Input low-level voltage
VDD = 2.7V-3.63V
-
-
0.29*VDD
V
VIH
Input high-level voltage
VDD = 2.7V-3.63V
0.55*VDD
-
-
VOL
Output low-level voltage
VDD>2.7V, IOL max
-
0.1*VDD
0.2*VDD
VOH
Output high-level voltage
VDD>2.7V, IOH max
0.8*VDD
0.9*VDD
-
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 976
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
IOL
Output low-level current
VDD = 2.7V-3V,
-
-
3
mA
VDD=3V-3.63V,
-
-
8
VDD=2.7V-3V,
-
-
2
VDD = 3V-3.63V,
-
-
7
Load = 5pF, VDD = 3.3V
-
-
15
-
-
15
-1
+/-0.015
1
IOH
tRISE
Output high-level current
Rise
time(1)
ns
Load = 20pF, VDD = 3.3V
tFALL
Fall time(1)
Load = 5pF, VDD = 3.3V
Load = 20pF, VDD = 3.3V
ILEAK
Input leakage current
Pull-up resistors disabled
µA
Notes:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. The I2C pins have faster fall-time in I2C Fast Plus mode (Fm+) and High Speed mode (HS). The fall-time can
be in 7 ns range in Fm+ mode, and in 5 ns range in HS mode.
3. USB pads PA24, PA25 compliant with USB standard in USB mode.
40.9
Analog Characteristics
40.9.1
Power-On Reset (POR) Characteristics
Table 40-18. POR Characteristics (Device Variant A)
Symbol
Parameters
Conditions
VPOT+
Voltage threshold Level on VDDIN rising
VPOT-
Voltage threshold Level on VDDIN falling
VDD falls at 1V/ms or slower
Min. Typ. Max. Unit
1.27
1.44
1.62
V
0.72
1.07
1.37
V
Table 40-19. POR Characteristics (Device Variant B and D)
Symbol
Parameters
VPOT+
Voltage threshold Level on VDDIN rising
VPOT-
Voltage threshold Level on VDDIN falling
© 2021 Microchip Technology Inc.
and its subsidiaries
Conditions
VDD falls at 1V/ms or slower
Complete Datasheet
Min. Typ. Max. Unit
1.27
1.45
1.62
V
0.53
0.99
1.32
V
DS40001882H-page 977
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
VDD
Figure 40-1. POR Operating Principle
VPOT+
VPOT-
40.9.2
RESET
Internal
Time
Brown-Out Detectors (BOD) Characteristics
Table 40-20. BOD33 Level Value (Device Variant A and B)
Symbol
BOD33.LEVEL
Conditions
Min.
Typ.
Max.
VBOD+
34
Hysteresis ON
-
2.68
2.74
VBOD- or VBOD
34
Hysteresis ON or Hysteresis OFF
2.51
2.59
2.65
Units
V
Table 40-21. BOD33 Level Value (Device Variant D)
Symbol
BOD33.LEVEL
Conditions
Min.
Typ.
Max.
VBOD+
34
Hysteresis ON
-
2.69
2.76
VBOD- or VBOD
34
Hysteresis ON or OFF
2.51
2.59
2.66
Units
V
Note: Refer to the Memories table NVM User Row Mapping for the BOD33 default value settings.
Table 40-22. BOD33 Characteristics (Device Variant A)
Symbol
Parameter
Conditions
Step size, between adjacent
values in BOD33.LEVEL
Min. Typ. Max. Units
-
34
-
mV
VHYST
VBOD+ - VBOD-
Hysteresis ON
35
-
170
mV
tDET(1)
Detection time
Time with VDDANA < VTH
necessary to generate a reset
signal
-
0.9
-
µs
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 978
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
IBOD33
Current Consumption
IDLE2, Mode CONT
Min. Typ. Max. Units
25°C
IDLE2, Mode SAMPL
STDBY, Mode SAMPL
-
33
48
-40 to 125 -
-
53.0
25°C
0.03 0.50
-
-40 to 125 -
-
25°C
0.13 0.50
-
-40 to 125 tSTARTUP(1) Start-up time
-
µA
2.3
-
1.7
1.2
-
µs
Table 40-23. BOD33 Characteristics (Device Variant B and D)
Symbol
Parameter
Conditions
Step size, between adjacent
values in BOD33.LEVEL
Min. Typ.
Max. Units
-
34
-
mV
170
mV
VHYST
VBOD+ - VBOD-
Hysteresis ON
35
-
tDET(1)
Detection time
Time with VDDANA < VTH
necessary to generate a reset
signal
-
0.9(1) -
µs
IBOD33
Current Consumption
IDLE2, Mode CONT
-
33
48
µA
-40 to 125 -
-
53.0
25°C
0.03
0.50
-40 to 125 -
-
3
25°C
0.13
0.50
-
1.7
2.2(1)
-
25°C
IDLE2, Mode SAMPL
STDBY, Mode SAMPL
-
-
-40 to 125 (1)
tSTARTUP
Start-up time
-
µs
Note:
1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
40.9.3
Analog-to-Digital (ADC) Characteristics
Table 40-24. Operating Conditions (Device Variant A)
Symbol
Parameters
VDDANA
Min
Typ
Max
Unit
Power supply voltage
2.7
-
3.6
V
Res
Resolution
8
-
12
bits
fCLK_ADC
ADC Clock frequency
30
-
2100
kHz
5
-
300
ksps
5
-
350
250
-
-
Sampling
rate(2)
Conditions
Single shot (with
VDDANA >
3.0V)(4)
Free running
Sampling time(2)
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
ns
DS40001882H-page 979
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameters
Min
Typ
Max
Unit
Sampling time with DAC as
input(2)
3
-
-
µs
Sampling time with Temp
sens as input(2)
10
-
-
µs
Sampling time with
Bandgap as input(2)
10
-
-
µs
6
-
-
Cycles
Conversion time(2)
Conditions
1x Gain
VREF
Voltage reference range
(VREFA or VREFB)
1
-
VDDANA-0.6
V
INT1V
Internal 1V reference (2,5)
-
1
-
V
INTVCC0
Internal ratiometric
reference 0(2)
-
VDDANA/1.48 -
V
INTVCC0
Internal ratiometric
Voltage Error reference 0(2) error
2.0V <
VDDANA2.0V
-
VDDANA/2
-
V
2.0V <
VDDANA VREF/4
– VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 -0.05*VDDANA -0.1V
ii. If |VIN| < VREF/4
– VCM_IN < 1.2*VDDANA - 0.75V
– VCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09, PA10, and PA11 are powered from the VDDIO power supply. The
ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (2*VREF/GAIN).
Table 40-28. Single Ended Mode FCLK_ADC = 2.1MHz (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ENOB
Effective Number of Bits
With gain compensation
-
9.5
9.8
Bits
TUE
Total Unadjusted Error
1x gain
-
8.4
14.7
LSB
INL
Integral Non-Linearity
1x gain
1.6
2.6
7.5
LSB
DNL
Differential Non-Linearity
1x gain
+/-0.5
+/-0.6
+/-0.95
LSB
GE
Gain Error
Ext. Ref. 1x
-10
0.7
10
mV
Gain Accuracy(4)
Ext. Ref. 0.5x
+/-0.1
+/-0.3
+/-0.4
%
Ext. Ref. 2x to 16X
+/-0.01
+/-0.1
+/-0,65
%
OE
Offset Error
Ext. Ref. 1x
-17
0.2
1
mV
SFDR
Spurious Free Dynamic Range
1x Gain
63
65
66.5
dB
SINAD
Signal-to-Noise and Distortion
FIN = 40kHz
50.7
59.5
61
dB
SNR
Signal-to-Noise Ratio
AIN = 95%FSR
57.6
60
64
dB
THD
Total Harmonic Distortion
-64.4
-63
-57.9
dB
-
Noise RMS
-
1
-
mV
T = 25°C
Table 40-29. Single Ended Mode FCLK_ADC = 2.1MHz (Device Variant B and D)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ENOB
Effective Number of Bits
With gain compensation
-
9.5
10.1
Bits
TUE
Total Unadjusted Error
1x gain
-
7.8
40
LSB
INL
Integral Non-Linearity
1x gain
1.4
2.6
6
LSB
DNL
Differential Non-Linearity
1x gain
+/-0.6
+/-0.7
+/-0.95
LSB
GE
Gain Error
Ext. Ref. 1x
-6.6
0.6
6.6
mV
Gain Accuracy(4)
Ext. Ref. 0.5x
+/-0.1
+/-0.37
+/-0.55
%
Ext. Ref. 2x to 16X
+/-0.01
+/-0.1
+/-0.3
%
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 983
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
OE
Offset Error
Ext. Ref. 1x
-5
3.2
12
mV
SFDR
Spurious Free Dynamic Range
1x Gain
61.7
66.6
66.6
dB
SINAD
Signal-to-Noise and Distortion
FIN = 40kHz
53.9
58.8
60.7
dB
SNR
Signal-to-Noise Ratio
AIN = 95%FSR
52.9
59.7
62.7
dB
THD
Total Harmonic Distortion
-67.6
-66.6
-63.7
dB
-
Noise RMS
-
1
6
mV
T = 25°C
Notes:
1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input
voltage range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel
common mode voltage) for all VIN:
– VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09, PA10, and PA11 are powered from the VDDIO power supply. The
ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x
100) / (VREF/GAIN).
40.9.4
Digital to Analog Converter (DAC) Characteristics
Table 40-30. Operating Conditions(1)
Symbol
Parameters
Conditions
Min.
Typ.
Max.
Unit
VDDANA
Analog supply voltage
-
2.7
-
3.63
V
AVREF
External reference voltage
-
1
-
VDDANA-0.6
V
INT1V(3)
-
-
1
-
V
VDDANA
-
-
VDDANA
-
V
Linear output voltage range
-
0.05
-
VDDANA-0.05
V
Minimum resistive load
-
5
-
-
kW
Maximum capacitance load
-
-
-
100
pF
DC supply current(2)
Voltage pump disabled
-
160
290
µA
IDD
Notes:
1. These values are based on specifications otherwise noted.
2. These values are based on characterization. These values are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 40-31. Clock and Timing (1)
Parameter
Conditions
Conversion rate
CLOAD=100pF
RLOAD > 5kΩ
© 2021 Microchip Technology Inc.
and its subsidiaries
Min.
Typ.
Max.
Units
Normal mode
-
-
350
ksps
For ΔDATA=+/-1
-
-
1000
Complete Datasheet
DS40001882H-page 984
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Parameter
Conditions
Min.
Typ.
Max.
Units
Startup time
VDDNA > 2.6V
-
-
2.85
µs
VDDNA < 2.6V
-
-
10
µs
Note:
1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
Table 40-32. Accuracy Characteristics(1) (Device Variant A)
Symbol
Parameter
Conditions
RES
Input resolution
-
INL
Integral non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
DNL
Differential non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
Min.
Typ.
Max.
Units
-
-
-
10
Bits
VDD = 2.7V
-
1.2
1.5
LSB
VDD = 3.6V
-
1.2
1.5
VDD = 2.7V
-
1.4
1.5
VDD = 3.6V
-
1.4
1.5
VDD = 2.7V
-
1.2
2
VDD = 3.6V
-
1.2
2
VDD = 2.7V
-
+/-1.2
+/-1.6
VDD = 3.6V
-
+/-1.1
+/-1.5
VDD = 2.7V
-
+-1.3
+/-1.9
VDD = 3.6V
-
+/-1.1
+/-1.6
VDD = 2.7V
-
+/-1.4
+/-3
VDD = 3.6V
-
+/-1,5
+/-3
LSB
GE
Gain error
Ext. VREF
-
-
+/-5
+/-28
mV
OE
Offset error
Ext. VREF
-
-
+/-3
+/-14
mV
Table 40-33. Accuracy Characteristics(1) (Device Variant B and D)
Symbol
Parameter
Conditions
RES
Input resolution
-
© 2021 Microchip Technology Inc.
and its subsidiaries
-
Complete Datasheet
Min.
Typ.
Max.
Units
-
-
10
Bits
DS40001882H-page 985
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
INL
Integral non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
DNL
Differential non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
Min.
Typ.
Max.
Units
VDD = 2.7V
-
0.75
1.5
LSB
VDD = 3.6V
-
0.65
1.5
VDD = 2.7V
-
0.85
1.5
VDD = 3.6V
-
0.8
1.5
VDD = 2.7V
-
0.8
2
VDD = 3.6V
-
0.8
3
VDD = 2.7V
-
+/-0.4
+/-1
VDD = 3.6V
-
+/-0.4
+/-1
VDD = 2.7V
-
+/-0.55
+/-1.0
VDD = 3.6V
-
+/-0.3
+/-0.75
VDD = 2.7V
-
+/-0.7
+/-3
VDD = 3.6V
-
+/-0.7
+/-3
GE
Gain error
Ext. VREF
-
-
+/-4
+/-16
mV
OE
Offset error
Ext. VREF
-
-
+/-1
+/-13
mV
Note:
1. All values measured using a conversion rate of 35ksps.
40.9.5
Analog Comparator Characteristics
Table 40-34. Electrical and Timing (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ. Max.
Units
Positive input voltage range
-
0
-
VDDANA
V
Negative input voltage range
-
0
-
VDDANA
Offset
Hysteresis = 0, Fast mode
-26
0
26
mV
Hysteresis = 0, Low power mode
-43
0
43
mV
Hysteresis = 1, Fast mode
8
50
102
mV
Hysteresis = 1, Low power mode
14
40
85
mV
Changes for VACM=VDDANA/2
-
60
126
ns
-
225
402
ns
-
1
2
µs
-
12
20
µs
-1.6
0.8
1.6
LSB
Hysteresis
Propagation delay
100mV overdrive, Fast mode
Changes for VACM=VDDANA/2
100mV overdrive, Low power mode
tSTARTUP
Startup time
Enable to ready delay
Fast mode
Enable to ready delay
Low power mode
VSCALE
INL(3)
© 2021 Microchip Technology Inc.
and its subsidiaries
-
Complete Datasheet
DS40001882H-page 986
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
DNL(3)
Offset Error
(1)(2)
Gain Error (1)(2)
Conditions
Min.
Typ. Max.
Units
-
-0.95
0.3
0.95
LSB
-
-0.2
0.3
1.04
LSB
-
-0.89
0.2
2
LSB
Table 40-35. Electrical and Timing (Device Variant B and D)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Positive input voltage range
-
0
-
VDDANA
Negative input voltage range
-
0
-
VDDANA
Offset
Hysteresis = 0, Fast mode
-26
0
26
Hysteresis = 0, Low power mode
-28
0
28
Hysteresis = 1, Fast mode
8
50
102
Hysteresis = 1, Low power mode
14
40
75
Changes for VACM=VDDANA/2
-
90
180
-
282
534
-
1
3
-
14
23
-
-1.6
0.75
1.6
-
-0.95
0.25
0.95
-
-0.2
0.26
1.04
-
-0.89
0.215
2
Hysteresis
Propagation delay
100mV overdrive, Fast mode
Changes for VACM=VDDANA/2
100mV overdrive, Low power mode
tSTARTUP
Startup time
Enable to ready delay
Fast mode
Enable to ready delay
Low power mode
VSCALE
INL(3)
DNL(3)
Offset Error
(1)(2)
Gain Error (1)(2)
Notes:
1. According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2. Data computed with the Best Fit method.
3. Data computed using histogram.
40.9.6
Bandgap and Internal 1.0V Reference Characteristics
Table 40-36. Bandgap and Internal 1.0V Reference Characteristics
Symbol
Parameter
BANDGAP Internal 1.1V Bandgap
reference
© 2021 Microchip Technology Inc.
and its subsidiaries
Conditions
Min. Typ. Max. Units
After calibration at T= 25°C, over [-40°C,
+125°C], Vdd 3.3V
1.06 1.1
1.12 V
Over voltage at 25°C
1.07 1.1
1.12 V
Complete Datasheet
DS40001882H-page 987
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
Min. Typ. Max. Units
INT1V
Internal 1.0V reference voltage
After calibration at T= 25°C, over [-40°C,
+125°C], Vdd 3.3V
0.96 1.00 1.02 V
Over voltage at 25°C
0.97 1.00 1.02 V
(1)
Note:
1. These values are simulation based and are not covered by production test limits.
40.10
NVM Characteristics
Table 40-37. Maximum Operating Frequency (Device Variant A)
VDD range
NVM Wait States
Maximum Operating Frequency
Units
2.7V to 3.63V
0
24
MHz
1
40
Table 40-38. Maximum Operating Frequency (Device Variant B and D)
VDD range
NVM Wait States
Maximum Operating Frequency
Units
2.7V to 3.63V
0
24
MHz
1
48
Note: With on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 40-39. Flash Endurance and Data Retention (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
CycNVM
Cycling Endurance(1)
-40°C < Ta < 125°C
10K
-
-
Cycles
Table 40-40. Flash Endurance and Data Retention (Device Variant B and D)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
CycNVM
Cycling Endurance(1)
-40°C < Ta < 125°C
25k
-
-
Cycles
Note:
1. An endurance cycle is a write and an erase operation.
Table 40-41. EEPROM Emulation(1) Endurance and Data Retention (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetEEPROM100k
Retention after up to 100k
Average ambient 55°C
10
50
-
Years
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and its subsidiaries
Complete Datasheet
DS40001882H-page 988
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetEEPROM10k
Retention after up to 10k
Average ambient 55°C
20
100
-
Years
-40°C < Ta < 125°C
40K
-
-
Cycles
CycEEPROM
Cycling
Endurance(2)
Table 40-42. EEPROM Emulation(1) Endurance and Data Retention (Device Variant B and D)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetEEPROM100k
Retention after up to 100k
Average ambient 55°C
10
50
-
Years
RetEEPROM10k
Retention after up to 10k
Average ambient 55°C
20
100
-
Years
-40°C < Ta < 125°C
100k
-
-
Cycles
CycEEPROM
Cycling
Endurance(2)
Notes:
1. The EEPROM emulation is a software emulation described in the Application Note AT03265: SAM
D10/D11/D20/D21/R/L/C EEPROM Emulator (EEPROM) Service.
2. An endurance cycle is a write and an erase operation.
Table 40-43. NVM Characteristics
40.11
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
tFPP
Page programming time
-
-
-
2.5
ms
tFRE
Row erase time
-
-
-
6
ms
tFCE
DSU chip erase time (CHIP_ERASE)
-
-
-
240
ms
Oscillator Characteristics
40.11.1 Crystal Oscillator (XOSC) Characteristics
Table 40-44. Digital Clock Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
fCPXIN
XIN clock frequency
digital mode
-
-
32
MHz
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in
the table. The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-45. Crystal Oscillator Characteristics
Symbol Parameter
Conditions
Min. Typ.
Max.
Units
fOUT
Crystal oscillator frequency
-
0.4
-
32
MHz
ESR
Crystal Equivalent Series
Resistance - SF = 3
f = 0.455 MHz, CL = 100pF, XOSC.GAIN = 0
-
-
5.6K
Ω
f = 2MHz, CL=20 pF XOSC.GAIN=0
-
-
330
f = 4MHz, CL=20 pF XOSC.GAIN=1
-
-
240
f = 8MHz, CL=20 pF XOSC.GAIN=2
-
-
105
f = 16MHz, CL=20 pF XOSC.GAIN=3
-
-
60
f = 32MHz, CL=18 pF XOSC,GAIN=4
-
-
55
-
-
5.9
-
pF
-
-
3.2
-
pF
f = 2MHz, CL=20 pF XOSC.GAIN=0, AGC off -
65
240
uA
f = 2MHz, CL=20 pF XOSC.GAIN=0, AGC on -
52
240
f = 4MHz, CL=20 pF XOSC.GAIN=1, AGC off -
117
309
f = 4MHz, CL=20 pF XOSC.GAIN=1, AGC on -
74
281
f = 8MHz, CL=20 pF XOSC.GAIN=2, AGC off -
226
435
f = 8MHz, CL=20 pF XOSC.GAIN=2, AGC on -
128
356
f = 16MHz, CL=20 pF XOSC.GAIN=3, AGC
off
-
502
748
f = 16MHz, CL=20 pF XOSC.GAIN=3, AGC
on
-
307
627
f = 32MHz, CL=18 pF XOSC.GAIN=4, AGC
off
-
1622
2344
f = 32MHz, CL=18 pF XOSC.GAIN=4, AGC
on
-
615
1422
f = 2MHz, CL=20 pF XOSC,GAIN=0,
ESR=600 Ohms
-
15.6K 51.0K Cycles
f = 4MHz, CL=20 pF XOSC,GAIN=1,
ESR=100 Ohms
-
6.3K
20.1K
f = 8MHz, CL=20 pF XOSC,GAIN=2,
ESR=35 Ohms
-
6.2K
20.3K
f = 16MHz, CL=20 pF XOSC,GAIN=3,
ESR=25 Ohms
-
7.7K
21.2K
f = 32MHz, CL=18 pF XOSC,GAIN=4,
ESR=40 Ohms
-
6.0K
14.2K
CXIN
Parasitic load capacitor
CXOUT
IXOSC
tSTART
Current consumption
Startup time
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Figure 40-2. Oscillator Connection
40.11.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 40-46. Digital Clock Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
fCPXIN32
XIN32 clock frequency
digital mode
-
32.768
-
kHz
-
XIN32 clock duty cycle
digital mode
-
50
-
%
Crystal Oscillator Characteristics
The figure, Oscillator Connection and the equation in Crystal Oscillator Characteristics also applies to the 32 kHz
oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the
range given in the table. The exact value of CL can be found in the crystal data sheet.
Table 40-47. 32 kHz Crystal Oscillator Electrical Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min. Typ.
fOUT
-
-
Crystal oscillator frequency
tSTARTUP Startup time
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ESRXTAL = 39.9 kΩ, CL = 12.5 pF -
Complete Datasheet
Max Units
32768 28K
Hz
31K cycles
DS40001882H-page 991
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol Parameter
Conditions
Min. Typ.
Max Units
CL
Crystal load capacitance
-
-
-
12.5 pF
CSHUNT
Crystal shunt capacitance
-
-
0.1
-
pF
CXIN32
Parasitic capacitor load
TQFP64/48/32 packages
-
3.1
-
pF
-
3.3
-
pF
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
-
-
1.2
2.5
µA
ESR
CL=12.5pF
-
-
141
kΩ
Crystal equivalent series resistance
f=32.768kHz
Safety Factor = 3
Table 40-48. 32 kHz Crystal Oscillator Electrical Characteristics (Device Variant B and D)
Symbol Parameter
Conditions
Min. Typ.
fOUT
-
-
Crystal oscillator frequency
Max Units
32768 -
Hz
tSTARTUP Startup time
ESRXTAL = 39.9 kW, CL = 12.5 pF -
28K
31K cycles
CL
Crystal load capacitance
-
-
-
12.5 pF
CSHUNT
Crystal shunt capacitance
-
-
0.1
-
-
CXIN32
Parasitic capacitor load
TQFP64/48/32 packages
-
3.2
-
-
-
3.7
-
-
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
-
-
1.2
2.2
µA
ESR
CL=12.5pF
-
-
100
kΩ
Crystal equivalent series resistance
f=32.768kHz
Safety Factor = 3
40.11.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 40-49. DFLL48M Characteristics - Open Loop Mode (Device Variant A)
Symbol Parameter
Conditions
fOUT
DFLLVAL.COARSE = DFLL48M COARSE CAL 45
Output frequency
Min. Typ. Max. Units
48
49
MHz
DFLLVAL.COARSE = DFLL48M COARSE CAL 46.5 48
49
MHz
403
457
µA
8
12
µs
DFLLVAL.FINE = 512
over [-40°, +125°]C, over [2.7, 3.6]V
fOUT
Output frequency
DFLLVAL.FINE = 512
at 25°C, over [2.7, 3.6]V
IDFLL
Power consumption on VDDIN DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512
tSTARTUP Startup time
DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512
fOUT within 90 % of final value
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-50. DFLL48M Characteristics - Open Loop Mode (Device Variant B and D)
Symbol Parameter
Conditions
fOUT
DFLLVAL.COARSE = DFLL48M COARSE CAL 44.75 48
Output frequency
Min.
Typ. Max. Units
49
MHz
48
49
MHz
48
49
MHz
403
457
µA
8
12
µs
Max.
Units
DFLLVAL.FINE = 512
over [-10°, +125°]C, over [2.7, 3.6]V
fOUT
Output frequency
DFLLVAL.COARSE = DFLL48M COARSE CAL 43.5
DFLLVAL.FINE = 512
over [-40°, +125°]C, over [2.7, 3.6]V
fOUT
Output frequency
DFLLVAL.COARSE = DFLL48M COARSE CAL 45.5
DFLLVAL.FINE = 512
at 25°C, over [2.7, 3.6]V
IDFLL
Power consumption on VDDIN DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512
tSTARTUP Startup time
DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512
fOUT within 90 % of final value
Table 40-51. DFLL48M Characteristics - Close Loop Mode (Device Variant A)
Symbol Parameter
Conditions
Min.
fOUT
fREF = XTAL, 32 .768kHz, 100ppm
47.76 48
Average Output frequency
Typ.
48.24 MHz
DFLLMUL = 1464
fREF
Reference frequency
-
0.732 32.768 33
kHz
Jitter
Cycle to Cycle jitter
fREF = XTAL, 32 .768kHz, 100ppm
-
-
0.42
ns
DFLLMUL = 1464
IDFLL
Power consumption on
VDDIN
fREF = XTAL, 32 .768kHz, 100ppm
-
403
457
µA
tLOCK
Lock time
fREF = XTAL, 32 .768kHz, 100ppm
-
350
1500
µs
DFLLMUL = 1464
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-52. DFLL48M Characteristics - Close Loop Mode (Device Variant B and D)
Symbol Parameter
fOUT
Conditions
Min.
Average Output frequency fREF = XTAL, 32 .768kHz, 100ppm
Typ.
Max.
47.76 48
Units
48.24 MHz
DFLLMUL = 1464
fREF
Reference frequency
-
0.732 32.768 33
kHz
Jitter
Cycle to Cycle jitter
fREF = XTAL, 32 .768kHz, 100ppm
-
-
0.42
ns
DFLLMUL = 1464
IDFLL
Power consumption on
VDDIN
fREF = XTAL, 32 .768kHz, 100ppm
-
403
457
µA
tLOCK
Lock time
fREF = XTAL, 32 .768kHz, 100ppm
-
350
1500
µs
DFLLMUL = 1464
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Note: All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL closed loop
mode with an external OSC reference or the internal OSC8M.
40.11.4 32.768 kHz Internal Oscillator (OSC32K) Characteristics
Table 40-53. 32 kHz RC Oscillator Electrical Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min.
fOUT
Calibrated against a 32.768kHz
28.508 32.768 35.389 kHz
Output frequency
Typ.
Max
Units
reference at 25°C, over [-40, +125]C,
over [2.7, 3.63]V
Calibrated against a 32.768kHz reference at
25°C, at VDD=3.3V
31.621 32.768 33.423
Calibrated against a 32.768kHz
31.457 32.768 34.079
reference at 25°C, over [2.7, 3.63]V
IOSC32K
Current consumption -
-
0.79
3.7
uA
tSTARTUP Startup time
-
-
1
2
cycles
Duty
-
-
50
-
%
Duty Cycle
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-54. 32 kHz RC Oscillator Electrical Characteristics (Device Variant B and D)
Symbol Parameter
Conditions
Min.
fOUT
Calibrated against a 32.768kHz
26.214 32.768 39.321 kHz
Output frequency
Typ.
Max
Units
reference at 25°C, over [-40, +125]C,
over [2.7, 3.63]V
Calibrated against a 32.768kHz reference at
25°C, at VDD=3.3V
32.113 32.768 33.423 kHz
Calibrated against a 32.768kHz
31.457 32.768 34.079 kHz
reference at 25°C, over [2.7, 3.63]V
IOSC32K
Current consumption -
-
0.67
5
uA
tSTARTUP Startup time
-
-
1
2
cycles
Duty
-
-
50
-
%
Typ.
Max
Units
Duty Cycle
40.11.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Table 40-55. Ultra Low Power Internal 32 kHz RC Oscillator Electrical Characteristics
Symbol Parameter
fOUT
Conditions
Min.
Output frequency Calibrated against a 32.768kHz
24.248 32.768 40.96
kHz
reference at 25°C, over [-40, +125]C,
over [2.7, 3.63]V
-
-
Calibrated against a 32.768kHz reference at 25°C, at
VDD=3.3V
30.474 32.768 35.061 kHz
-
-
Calibrated against a 32.768kHz
30.146 32.768 35.389 kHz
reference at 25°C, over [2.7, 3.63]V
Duty
Duty Cycle
-
-
50
-
%
Notes:
1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
2. This oscillator is always on.
40.11.6 8MHz RC Oscillator (OSC8M) Characteristics
Table 40-56. Internal RC Oscillator Electrical Characteristics (Device Variant A)
Symbol Parameter
Conditions
Min. Typ. Max Units
fOUT
Calibrated against a 8MHz reference at 25°C, over [-10,
+70]C, over [2.7, 3.6]V
7.84 8
8.16 MHz
Calibrated against a 8MHz reference at 25°C, over [-10,
+125]C, over [2.7, 3.6]V
7.8
8
8.2
Calibrated against a 8MHz reference at 25°C, over [-40,
+125]C, over [2.7, 3.6]V
7.7
8
8.3
Calibrated against a 8MHz reference at 25°C, over [2.7,
3.6]V
7.88 8
Output frequency
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8.12
DS40001882H-page 995
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
...........continued
Symbol Parameter
IOSC8M
Conditions
Min. Typ. Max Units
Current consumption IDLE2 on OSC32K versus IDLE2 on calibrated OSC8M
enabled at 8MHz (FRANGE=1, PRESC=0)
-
64
100
uA
tSTARTUP Startup time
-
-
2.4
3.9
us
Duty
-
-
50
-
%
Duty Cycle
Table 40-57. Internal RC Oscillator Electrical Characteristics (Device Variant B and D)
Symbol Parameter
Conditions
Min. Typ. Max Units
fOUT
Calibrated against a 8MHz reference at 25°C, over [-10,
+70]C, over [2.7, 3.6]V
7.84 8
8.16 MHz
Calibrated against a 8MHz reference at 25°C, over [-10,
+125]C, over [2.7, 3.6]V
7.8
8.2
Calibrated against a 8MHz reference at 25°C, over [-40,
+125]C, over [2.7, 3.6]V
7.66 8
8.34
Calibrated against a 8MHz reference at 25°C, over [2.7,
3.6]V
7.88 8
8.12
-
64
96
uA
IOSC8M
Output frequency
Current consumption IDLE2 on OSC32K versus IDLE2 on calibrated OSC8M
enabled at 8MHz (FRANGE=1, PRESC=0)
8
tSTARTUP Startup time
-
-
2.4
3.9
us
Duty
-
-
50
-
%
Duty Cycle
40.11.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 40-58. FDPLL96M Characteristics(1) (Device Variant A)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fIN
Input frequency
-
32
-
2000
kHz
fOUT
Output frequency
-
48
-
64
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
-
500
700
µA
fIN= 32 kHz, fOUT= 64 MHz
-
900
1200
fIN= 32 kHz, fOUT= 48 MHz
-
1.5
4
fIN= 32 kHz, fOUT= 64 MHz
-
2.8
7
fIN= 2 MHz, fOUT= 48 MHz
-
1.3
5
fIN= 2 MHz, fOUT= 64 MHz
-
3.3
8
After startup, time to get lock signal.
-
1.3
2
ms
-
25
50
µs
40
50
60
%
JP
tLOCK
Period jitter peak
Lock Time
%
fIN= 32 kHz, fOUT= 64 MHz
After startup, time to get lock signal
fIN= 2MHz, fOUT= 64MHz
Duty
Duty cycle
© 2021 Microchip Technology Inc.
and its subsidiaries
-
Complete Datasheet
DS40001882H-page 996
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-59. FDPLL96M Characteristics(1) (Device Variant B and D)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fIN
Input frequency
-
32
-
2000
kHz
fOUT
Output frequency
-
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
-
500
740
µA
fIN= 32 kHz, fOUT= 96 MHz
-
900
1262
fIN= 32 kHz, fOUT= 48 MHz
-
2.1
4
fIN= 32 kHz, fOUT= 96 MHz
-
3.8
11
fIN= 2 MHz, fOUT= 48 MHz
-
2.2
4
fIN= 2 MHz, fOUT= 96 MHz
-
5
12
After startup, time to get lock signal.
-
1.2
2
ms
fIN= 2 MHz, fOUT= 96 MHz
-
25
50
µs
-
40
50
60
%
JP
tLOCK
Period jitter peak
Lock Time
%
fIN= 32 kHz, fOUT= 96 MHz
Duty
Duty cycle
Note:
1. All values have been characterized with FILTSEL[1/0] as default value.
40.12
PTC Characteristics
The values given in the Power Consumption table below are measured values of power consumption, which are valid
under the following conditions:
Operating conditions
VDD = 3.3 V
Clocks
OSC8M used as main clock source, running undivided at 8 MHz.
CPU is running on Flash with '0' wait states, at 8 MHz.
PTC running at 4 MHz.
PTC configuration
Mutual-Capacitance mode.
One-touch channel.
System configuration
Standby Sleep mode enabled.
RTC running on OSCULP32K: Used to define the PTC scan rate through the event system.
Drift Calibration disabled: No interrupts, PTC scans are performed in Standby mode.
Drift Calibration enabled: RTC interrupts (wake-up) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
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Complete Datasheet
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SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-60. Power Consumption (1)(2) (Variant A)
Symbol Parameters
IDD(2)
Drift Calibration
Current Consumption Disabled
PTC scan
rate (msec)
Oversamples Ta
10
4
Max. 125°C 72
1151 µA
16
Typ. 25°C
84
1167
4
65
1148
16
68
1154
4
64
1148
16
65
1151
4
64
1151
16
64
1150
4
77
1152
16
88
1181
4
67
1156
16
70
1160
4
66
1154
16
67
1158
4
65
1155
16
66
1157
50
100
200
Enabled
10
50
100
200
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Complete Datasheet
Typ. Max. Units
DS40001882H-page 998
SAM D21/DA1 Family
AEC-Q100 125°C Specifications
Table 40-61. Power Consumption (1)(2) (Variant B and D)
Symbol Parameters
IDD(2)
Drift Calibration
Current Consumption Disabled
PTC scan
rate (msec)
Oversamples Ta
10
4
Max. 125°C 66
791
16
Typ. 25°C
75
803
4
61
787
16
63
791
4
61
788
16
62
790
4
60
788
16
61
789
4
71
802
16
80
813
4
63
792
16
65
795
4
62
791
16
63
793
4
62
790
16
63
791
50
100
200
Enabled
10
50
100
200
Typ. Max. Units
µA
Notes:
1. These are based on characterization.
2. On this table, the LDO voltage regulator is enabled in Standby mode (SYSCTRL.VREG.RUNSTDBY = 1).
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Complete Datasheet
DS40001882H-page 999
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.
SAM DA1 Electrical Characteristics
41.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
41.2
41.2.1
Thermal Considerations
Thermal Resistance Data
The following Table summarizes the thermal resistance data depending on the package.
Table 41-1. Thermal Resistance Data
41.2.2
Package Type
θJA
θJC
32-pin VQFN
40.9°C/W
15.2°C/W
48-pin VQFN
32.0°C/W
10.9°C/W
64-pin VQFN (TMB)
32.5°C/W
10.7°C/W
64-lead VQFN (5LX)
23.9°C/W
8.9°C/W
32-pin TQFP
64.7°C/W
23.1°C/W
48-pin TQFP
63.6°C/W
12.2°C/W
64-pin TQFP
60.9°C/W
12.2°C/W
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
TJ = TA + (PD x θJA)
TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is
necessary or not. If a cooling device has to be fitted on the chip, the second equation should be used to compute the
resulting average chip-junction temperature TJ in °C.
41.3
Absolute Maximum Ratings
Stresses beyond those listed in this section may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-2. Absolute Maximum Ratings
Symbol
Description
Min.
Max.
Units
VDD
Power supply voltage
0
3.8
V
IVDD
Current into a VDD pin
-
92(1)
mA
IGND
Current out of a GND pin
-
130(1)
mA
VPIN
Pin voltage with respect to GND and VDD
GND-0.6V
VDD+0.6V
V
Tstorage
Storage temperature
-60
150
°C
1.
Maximum source current is 46mA and maximum sink current is 65mA per cluster. A cluster is a group of
GPIOs as shown in the table below. Also note that each VDD/GND pair is connected to two clusters so current
consumption through the pair will be a sum of the clusters source/sink currents.
CAUTION
CAUTION
This device is sensitive to electrostatic discharges (ESD). Improper handling may lead to permanent
performance degradation or malfunctioning.
Handle the device following best practice ESD protection rules: Be aware that the human body can
accumulate charges large enough to impair functionality or destroy the device.
In debugger cold-plugging mode, NVM erase operations are not protected by the BOD33 and BOD12.
NVM erase operation at supply voltages below specified minimum can cause corruption of NVM areas that
are mandatory for correct device behavior.
Related Links
7.2.4 GPIO Clusters
7.2.4 GPIO Clusters
41.4
Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 105°C, unless
otherwise specified and are valid for a junction temperature up to TJ = 125°C. Refer to Power Supply and Start-Up
Considerations.
Table 41-3. Supply Characteristics
Voltage
Conditions
Symbol
Min.
Max.
Unit
Full Voltage Range
VDDIO
VDDIN
VDDANA
2.7
3.63
V
Table 41-4. Supply Rates
Fall Rate Rise Rate
Conditions
Symbol
Max.
Max.
Unit
DC supply peripheral I/Os, internal regulator and analog supply voltage
VDDIO
, VDDIN
, VDDANA
0.05
0.1
V/μs
Related Links
8. Power Supply and Start-Up Considerations
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and its subsidiaries
Complete Datasheet
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.5
Maximum Clock Frequencies
Table 41-5. Maximum GCLK Generator Output Frequencies
Description
Conditions
Symbol
Max.
Unit
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
96
MHz
48
MHz
Symbol
Max.
Unit
CPU clock frequency
fCPU
48
MHz
AHB clock frequency
fAHB
48
MHz
APBA clock frequency
fAPBA
48
MHz
APBB clock frequency
fAPBB
48
MHz
APBC clock frequency
fAPBC
48
MHz
fGCLK_DFLL48M_REF
33
kHz
fGCLK_DPLL
2
MHz
fGCLK_DPLL_32K
32
kHz
WDT input clock frequency
fGCLK_WDT
48
MHz
RTC input clock frequency
fGCLK_RTC
48
MHz
EIC input clock frequency
fGCLK_EIC
48
MHz
USB input clock frequency
fGCLK_USB
48
MHz
EVSYS channel 0 input clock frequency
fGCLK_EVSYS_CHANNEL_0
48
MHz
EVSYS channel 1 input clock frequency
fGCLK_EVSYS_CHANNEL_1
48
MHz
EVSYS channel 2 input clock frequency
fGCLK_EVSYS_CHANNEL_2
48
MHz
EVSYS channel 3 input clock frequency
fGCLK_EVSYS_CHANNEL_3
48
MHz
EVSYS channel 4 input clock frequency
fGCLK_EVSYS_CHANNEL_4
48
MHz
EVSYS channel 5 input clock frequency
fGCLK_EVSYS_CHANNEL_5
48
MHz
EVSYS channel 6 input clock frequency
fGCLK_EVSYS_CHANNEL_6
48
MHz
EVSYS channel 7 input clock frequency
fGCLK_EVSYS_CHANNEL_7
48
MHz
EVSYS channel 8 input clock frequency
fGCLK_EVSYS_CHANNEL_8
48
MHz
EVSYS channel 9 input clock frequency
fGCLK_EVSYS_CHANNEL_9
48
MHz
EVSYS channel 10 input clock frequency
fGCLK_EVSYS_CHANNEL_10
48
MHz
EVSYS channel 11 input clock frequency
fGCLK_EVSYS_CHANNEL_11
48
MHz
fGCLK_SERCOMx_SLOW
48
MHz
Undivided
fGCLKGEN2
GCLK Generator Output Frequency
fGCLKGEN3
fGCLKGEN4
Divided
fGCLKGEN5
Table 41-6. Maximum Peripheral Clock Frequencies
Description
DFLL48M Reference clock frequency
FDPLL96M Reference clock frequency
FDPLL96M 32k Reference clock frequency
Common SERCOM slow input clock frequency
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Description
Symbol
Max.
Unit
SERCOM0 input clock frequency
fGCLK_SERCOM0_CORE
48
MHz
SERCOM1 input clock frequency
fGCLK_SERCOM1_CORE
48
MHz
SERCOM2 input clock frequency
fGCLK_SERCOM2_CORE
48
MHz
SERCOM3 input clock frequency
fGCLK_SERCOM3_CORE
48
MHz
SERCOM4 input clock frequency
fGCLK_SERCOM4_CORE
48
MHz
SERCOM5 input clock frequency
fGCLK_SERCOM5_CORE
48
MHz
TCC0, TCC1 input clock frequency
fGCLK_TCC0, GCLK_TCC1
96
MHz
TCC2,TC3 input clock frequency
fGCLK_TCC2, GCLK_TC3
48
MHz
TC4, TC5 input clock frequency
fGCLK_TC4, GCLK_TC5
96
MHz
TC6,TC7 input clock frequency
fGCLK_TC6, GCLK_TC7
48
MHz
fGCLK_ADC
48
MHz
AC digital input clock frequency
fGCLK_AC_DIG
48
MHz
AC analog input clock frequency
fGCLK_AC_ANA
64
kHz
DAC input clock frequency
fGCLK_DAC
48
MHz
PTC input clock frequency
fGCLK_PTC
48
MHz
I2S serial 0 input clock frequency
fGCLK_I2S_0
13
MHz
I2S serial 1 input clock frequency
fGCLK_I2S_1
13
MHz
ADC input clock frequency
41.6
Power Consumption
The values in this section are measured values of power consumption under the following conditions, except where
noted:
•
•
•
•
•
•
•
Operating conditions
– VVDDIN = 3.3 V
– VVDDIN = 2.7V, CPU is running on Flash with 1 wait state
Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
Oscillators
– XOSC (crystal oscillator) stopped
– XOSC32K (32 kHz crystal oscillator) running with external 32kHz crystal
– DFLL48M using XOSC32K as reference and running at 48 MHz
Clocks
– DFLL48M used as main clock source, except otherwise specified
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
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Complete Datasheet
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
•
•
•
CPU is running on flash with 1 wait states
Cache enabled
BOD33 disabled
Table 41-7. Current Consumption
Mode
Conditions
CPU running a While(1) algorithm
CPU running a While(1) algorithm,
with GCLKIN as reference
CPU running a Fibonacci algorithm
ACTIVE
CPU running a Fibonacci algorithm,
with GCLKIN as reference
CPU running a CoreMark algorithm
CPU running a CoreMark algorithm,
with GCLKIN as reference
IDLE0
Default operating conditions
IDLE1
Default operating conditions
IDLE2
Default operating conditions
STANDBY
(Device
Variant A / Die rev. E)
XOSC32K running
RTC running at 1kHz
XOSC32K and RTC stopped
© 2021 Microchip Technology Inc.
and its subsidiaries
TA
VCC
Typ.
Max.
25°C
3.3V
3.32
3.63
105°C 3.3V
3.57
3.98
3.3V
64 × Freq +
110
70 × Freq +
131
105°C 3.3V
65 × Freq +
342
65 × Freq +
764
3.3V
4.03
4.35
105°C 3.3V
4.29
4.76
3.3V
79 × Freq +
110
85 × Freq +
133
105°C 3.3V
80 × Freq +
346
81 × Freq +
771
3.3V
5.08
5.63
105°C 3.3V
5.41
5.95
3.3V
101 × Freq +
113
110 × Freq +
132
105°C 3.3V
103 × Freq +
347
104 × Freq +
748
3.3V
2.24
2.41
105°C 3.3V
2.49
2.92
25°C
3.3V
1.69
1.82
105°C 3.3V
1,91
2.33
25°C
3.3V
1.23
1.32
105°C 3.3V
1.44
1.85
25°C
3.3V
4.2
12.8
70°C
3.3V
26.7
100.0
105°C 3.3V
146
627
25°C
3.3V
3.1
12.2
70°C
3.3V
25.6
100.0
105°C 3.3V
145
624
25°C
25°C
25°C
25°C
25°C
25°C
Complete Datasheet
Unit
mA
μA (with freq
in MHz)
mA
μA (with freq
in MHz)
mA
μA (with freq
in MHz)
mA
μA
DS40001882H-page 1004
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Mode
Conditions
TA
VCC
Typ.
Max.
25°C
3.3V
4.6
15.0
70°C
3.3V
23
96
105°C 3.3V
95.0
390.0
25°C
3.3V
3.4
14.0
70°C
3.3V
22
95
105°C 3.3V
94.0
388.0
XOSC32K running
25°C
3.3V
61.0
72.0
RTC running at 1kHz
70°C
3.3V
87
176
105°C 3.3V
174.0
452.0
25°C
3.3V
60.0
71.0
70°C
3.3V
86
175
173.0
450.0
XOSC32K running
RTC running at 1kHz
STANDBY(1)
(Device Variant B / Die rev. F)
XOSC32K and RTC stopped
STANDBY(2)
(Device Variant B / Die rev. F) XOSC32K and RTC stopped
105°C 3.3V
1.
2.
Unit
μA
μA
Measurements done with SYSCTRL.VREG.RUNSTDBY=0 (low power configuration).
Measurements done with SYSCTRL.VREG.RUNSTDBY=1 (normal configuration).
Table 41-8. Wake-up Time(1)
Mode
TA
IDLE0
IDLE1
IDLE2
25°C
21.1
22.0
29.6
IDLE0
2.3
IDLE2
Unit
2.3
STANDBY
IDLE1
105°C
STANDBY
1.
Typ.
22.9
23.8
μs
μs
29.8
OSC8M used as main clock source, cache disabled.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-1. Measurement Schematic
VDDIN
VDDANA
VDDIO
Amp 0
VDDCORE
41.7
Peripheral Power Consumption
41.7.1
All peripheral except USB
Default conditions, except where noted:
•
•
•
•
•
•
•
•
•
Operating conditions
– VVDDIN = 3.3 V
Oscillators
– XOSC (crystal oscillator) stopped
– XOSC32K (32 kHz crystal oscillator) running with external 32kHz crystal
– OSC8M at 8MHz
Clocks
– OSC8M used as main clock source
– CPU, AHB and APBn clocks undivided
The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
CPU in IDLE0 mode
Cache enabled
BOD33 disabled
In this default conditions, the power consumption Idefault is measured.
Operating mode for each peripheral in turn:
•
•
Configure and enable the peripheral GCLK (When relevant, see conditions)
Unmask the peripheral clock
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
•
•
•
•
•
•
•
Enable the peripheral (when relevant)
Set CPU in IDLE0 mode
Measurement Iperiph
Wake-up CPU via EIC (async: level detection, filtering disabled)
Disable the peripheral (when relevant)
Mask the peripheral clock
Disable the peripheral GCLK (when relevant, see conditions)
Each peripheral power consumption provided in table x.y is the value (Iperiph - Idefault), using the same measurement
method as for global power consumption measurement
Table 41-9. Typical Peripheral Current Consumption
Peripheral
Conditions
Typ.
Unit
RTC
fGCLK_RTC = 32kHz, 32bit counter mode
7.4
μA
WDT
fGCLK_WDT = 32kHz, normal mode with EW
5.5
μA
Both fGCLK = 8MHz, Enable both COMP
31.3
μA
50
μA
AC
TCx(1)
fGCLK = 8MHz, Enable + COUNTER in 8bit mode
TCC2
fGCLK = 8MHz, Enable + COUNTER
95.5
μA
TCC1
fGCLK = 8MHz, Enable + COUNTER
167.5
μA
TCC0
fGCLK = 8MHz, Enable + COUNTER
180.3
μA
SERCOMx.I2CM(2)
fGCLK = 8MHz, Enable
69.7
μA
SERCOMx.I2CS
fGCLK = 8MHz, Enable
29.2
μA
SERCOMx.SPI
fGCLK = 8MHz, Enable
64.6
μA
SERCOMx.USART
fGCLK = 8MHz, Enable
65.5
μA
fGCLK_I2S_0 = 12.288MHz with source FDPLL with fFDPLL = 49.152MHz
26.4
μA
RAM to RAM transfer
399.5
μA
I2S(3)
DMAC(4)
1.
2.
3.
4.
41.7.2
All TCs from 4 to 7 share the same power consumption values.
All SERCOMs from 0 to 5 share the same power consumption values.
The value includes the power consumption of the FDPLL.
The value includes the power consumption of the R/W access to the RAM.
USB Peripheral Power Consumption
Default conditions, except where noted:
•
•
•
•
•
Operating conditions
– VVDDIN = 3.3 V
Oscillators
– XOSC32K (32 kHz crystal oscillator) running with external 32kHz crystal in USB Host mode
Clocks
– USB Device mode: DFLL48M in USB recovery mode (Crystal less)
– USB Host mode: DFLL48M in closed loop with XOSC32K (32 kHz crystal oscillator) running with external
32kHz crystal
– CPU, AHB and APBn clocks undivided
The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge
– All other AHB clocks stopped
I/Os are inactive with internal pull-up
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
•
•
•
CPU in IDLE0 mode
Cache enabled
BOD33 disabled
In this default conditions, the power consumption Idefault is measured.
Measurements do not include consumption of clock source (ex: DFLL48M or FDPLL96M) and CPU. However no
CPU activity is required during all states (Suspend, IDLE, Data transfer).
Measurements have been done with an USB cable of 1.5m.
For USB Device mode, measurements include the maximum consumption (200μA) through pull-up resistor on the D+
line for USB attach. This value depends on USB Host characteristic.
Operating modes:
•
Run the USB Device/Host states in regards of the Universal Serial Bus (USB) v2.0 standard.
USB power consumption is provided in the following tables.
Table 41-10. Typical USB Device Full Speed mode Current Consumption
USB Device state
Conditions
Typ.
Units
Suspend
GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus in suspend mode.
201
μA
Suspend
GCLK_USB is on.
USB bus in suspend mode.
0.83
mA
IDLE
Start Of Frame is running.
No packet transferred.
1.17
mA
Active OUT
Start Of Frame is running.
Bulk OUT on 100% bandwidth.
2.17
mA
Active IN
Start Of Frame is running.
Bulk IN on 100% bandwidth.
10.3
mA
Table 41-11. Typical USB Host Full Speed mode Current Consumption
USB Device state
Conditions
Typ.
Units
Wait connection
GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus not connected.
0.10
μA
Wait connection
GCLK_USB is on.
USB bus not connected.
0.19
mA
Suspend
GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus in suspend mode.
201
μA
Suspend
GCLK_USB is on.
USB bus in suspend mode.
0.83
mA
IDLE
Start Of Frame is running.
No packet transferred.
1.17
mA
Active OUT
Start Of Frame is running.
Bulk OUT on 100% bandwidth.
2.17
mA
Active IN
Start Of Frame is running.
Bulk IN on 100% bandwidth.
10.3
mA
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.8
I/O Pin Characteristics
41.8.1
Normal I/O Pins
Table 41-12. Normal I/O Pins Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Pull-up - Pull-down
resistance
All pins excepted PA24, PA25
RPULL
20
40
60
kΩ
Input low-level voltage
VDD = 2.7V-3.63V
VIL
-
-
0.3 × VDD
Input high-level voltage
VDD = 2.7V-3.63V
VIH
0.55 × VDD
-
-
Output low-level voltage
VDD > 2.7V, IOL maxI
VOL
-
Output high-level voltage
VDD > 2.7V, IOH maxII
VOH
0.8 × VDD
0.9 × VDD
-
-
-
1
-
-
2.5
-
-
3
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
-
10
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=0
-
-
0.70
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=0
-
-
2
-
-
2
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
-
7
PORT.PINCFG.DRVSTR = 0load = 5pF, VDD = 3.3V
-
-
15
-
-
15
-
-
15
-
-
15
–1
±0.015
1
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=0
Output low-level current
Output high-level current
Rise
time(1)
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=0
0.1 × VDD 0.2 × VDD
IOL
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=1
mA
IOH
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=1
PORT.PINCFG.DRVSTR = 1load = 20pF, VDD =
3.3V
tRISE
PORT.PINCFG.DRVSTR = 0load = 5pF, VDD = 3.3V
Fall time(1)
PORT.PINCFG.DRVSTR = 1load = 20pF, VDD =
3.3V
tFALL
Input leakage current
Pull-up resistors disabled
ILEAK
Note: These values are based on simulation. These values are not covered by test limits in production or
characterization.
41.8.2
I2C Pins
Refer to the SERCOM I2C Pins section to get the list of I2C pins.
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Complete Datasheet
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ns
ns
μA
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-13. I2C Pins Characteristics in I2C Configuration
Parameter
Condition
Symbol
Min.
Typ.
Max.
Input low-level voltage
Input high-level voltage
VDD = 2.7V-3.63V
VIL
-
-
0.3 × VDD
VDD = 2.7V-3.63V
VIH
0.55 × VDD
-
-
VHYS
0.08 × VDD
-
-
-
-
0.4
-
-
0.2 × VDD
20
-
-
6
-
-
-
-
3.4
MHz
Hysteresis of Schmitt trigger inputs
VDD > 2.0V,
IOL = 3mA
Output low-level voltage
Unit
V
VOL
VDD ≤ 2.0V
,
IOL = 2mA
VOL = 0.4V
Standard, Fast and HS Modes
3
VOL = 0.4V
Fast Mode +
Output low-level current
IOL
VOL = 0.6V
SCL clock frequency
fSCL
mA
I2C pins timing characteristics can be found in the SERCOM in I2C Mode Timing section.
Table 41-14. I2C Pins Characteristics in I/O Configuration
Parameter
Conditions
Pull-up - Pull-down resistance
Symbol
Min.
Typ.
Max.
Unit
RPULL
20
40
60
kΩ
Input low-level voltage
VDD = 2.7V-3.63V
VIL
-
-
0.3 × VDD
Input high-level voltage
VDD = 2.7V-3.63V
VIH
0.55 × VDD
-
-
Output low-level voltage
VDD > 2.7V, IOL max
VOL
-
0.1 × VDD
0.2 × VDD
Output high-level voltage
VDD > 2.7V, IOH max
VOH
0.8*VDD
0.9 × VDD
-
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol
Min.
Typ.
Max.
-
-
1
-
-
2.5
-
-
3
-
-
10
Unit
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=0
VDD = 3V-3.63V,
Output low-level current
PORT.PINCFG.
DRVSTR=0
IOL
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=1
VDD = 3V-3.63V,
PORT.PINCFG.
DRVSTR=1
mA
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=0
-
-
0.70
-
-
2
-
-
2
-
-
7
VDD = 3V-3.63V,
Output high-level current
PORT.PINCFG.
DRVSTR=0
IOH
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=1
VDD = 3V-3.63V,
PORT.PINCFG.
DRVSTR=1
load = 20pF,
VDD = 3.3V
Rise time
15
PORT.PINCFG.
DRVSTR=1
tRISE
ns
load = 5pF, VDD = 3.3V
15
PORT.PINCFG.
DRVSTR=0
load = 20pF,
VDD = 3.3V
15
PORT.PINCFG.
DRVSTR=1
Fall time
tFALL
ns
load = 5pF, VDD = 3.3V
15
PORT.PINCFG.
DRVSTR=0
Input leakage current
Pull-up resistors disabled
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Related Links
7.2.3 SERCOM I2C Pins
37.16.3 SERCOM in I2C Mode Timing
41.8.3
USB Pins
Table 41-15. USB Pins Characteristics in I/O Configuration
Parameter
Conditions
Pull-up - Pull-down resistance
Symbol
Min.
Typ.
Max.
Unit
RPULL
20
40
60
kΩ
Input low-level voltage
VDD = 2.7V-3.63V
VIL
-
-
0.29 × VDD
Input high-level voltage
VDD = 2.7V-3.63V
VIH
0.55 × VDD
-
-
Output low-level voltage
VDD > 2.7V, IOL max
VOL
-
0.1 × VDD
0.2 × VDD
Output high-level voltage
VDD > 2.7V, IOH max
VOH
0.8 × VDD
0.9 × VDD
-
-
-
3
-
-
9
-
-
2
-
-
7
VDD = 2.7V-3V
Output low-level current
VDD = 3V-3.63V
VDD = 2.7V-3V
Output high-level current
IOH
VDD = 3V-3.63V
load = 5pF, VDD = 3.3V
Rise time
load = 20pF, VDD = 3.3V
load = 5pF, VDD = 3.3V
Fall time
load = 20pF, VDD = 3.3V
Input leakage current
41.8.4
IOL
Pull-up resistors disabled
tRISE
ns
tFALL
ILEAK
15
–1
±0.015
1
XOSC Pin
XOSC32 Pin
XOSC32 pins behave as normal pins when used as normal I/Os. Refer to table “Normal I/O Pins Characteristics”.
41.8.6
External Reset Pin
Reset pin has the same electrical characteristics as normal I/O pins. Refer to table “Normal I/O Pins Characteristics”.
41.9
Injection Current
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 41-16. Injection Current(1)
Symbol
Description
min
max
Unit
Iinj1 (2)
IO pin injection current
-1
+1
mA
Iinj2 (3)
IO pin injection current
-15
+15
mA
Iinjtotal
Sum of IO pins injection current
-45
+45
mA
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mA
15
XOSC pins behave as normal pins when used as normal I/Os. Refer to table “Normal I/O Pins Characteristics”.
41.8.5
V
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
1.
2.
Injecting current may have an effect on the accuracy of Analog blocks
Conditions for Vpin: Vpin < GND-0.6V or 3.6V 0.2 × VDDANA – 0.1V
The ADC channels on the pins, PA08, PA09, PA10, PA11, are powered from the VDDIO power supply. The
ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
The gain accuracy represents the gain error expressed in percent.
Gain accuracy (%) = (Gain Error in V × 100) / (2 × Vref/GAIN)
Table 41-25. Single-Ended Mode
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Effective Number of Bits
With gain compensation
ENOB
-
9.6
10.1
Bits
Total Unadjusted Error
1x gain
TUE
3
11
74
LSB
Integral Non-linearity
1x gain
INL
1
4
11
LSB
Differential Non-linearity
1x gain
DNL
-
±0.5
±0.95
LSB
Gain Error
Ext. Ref. 1x
-
±0.9
±10
mV
-
±0.2
±0.5
%
-
±0.15
±0.3
%
OE
-
±3
±40
mV
SFDR
63
68
70.1
dB
SINAD
55
60.1
62.5
dB
Gain Accuracy(4)
Ext. Ref. 0.5x
GE
Ext. Ref. 2x to 16X
Offset Error
Ext. Ref. 1x
Spurious Free Dynamic Range
Signal-to-Noise and Distortion
1x Gain
FCLK_ADC = 2.1 MHz
Signal-to-Noise Ratio
FIN = 40 kHz
SNR
54
61
64
dB
Total Harmonic Distortion
AIN = 95%FSR
THD
–70
–68
–65
dB
Noise RMS
T = 25°C
-
1
5
mV
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Notes:
1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input
voltage range.
2. Respect the input common mode voltage through the following equations, where VCM_IN is the Input Channel
Common mode voltage for all VIN:
VCM_IN < 0.7 × VDDANA + VREF/4 – 0.75V
3.
4.
VCM_IN > VREF/4 – 0.3 × VDDANA – 0.1V
The ADC channels on the pins, PA08, PA09, PA10, PA11, are powered from the VDDIO power supply. The
ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the
VDDANA power supply.
The gain accuracy represents the gain error expressed in percent.
Gain accuracy (%) = (Gain Error in V × 100) / (Vref/GAIN).
41.10.4.1 Performance with the Averaging Digital Feature
Averaging is a feature that increases the sample accuracy. ADC automatically computes an average value of
multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samplesto-be-Collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is
available in the Result register (RESULT).
Table 41-26. Averaging Feature
Average Number
Conditions
SNR (dB)
SINAD (dB)
SFDR (dB)
ENOB (bits)
66.0
65.0
72.8
10.5
67.6
65.8
75.1
10.62
69.7
67.1
75.3
10.85
70.4
67.5
75.5
10.91
1
8
32
In differential mode, 1x gain,
VDDANA = 3.0V, VREF = 1.0V, 350kSps at 25°C
128
41.10.4.2 Performance with the Hardware Offset and Gain Correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled
by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register
(GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result
register (RESULT).
Table 41-27. Offset and Gain Correction Feature
Offset Error
(mV)
Gain Error
(mV)
Total Unadjusted
Error (LSB)
0.25
1.0
2.4
0.20
0.10
1.5
0.15
–0.15
2.7
8x
–0.05
0.05
3.2
16x
0.10
–0.05
6.1
Gain Factor Conditions
0.5x
1x
2x
In differential mode, 1x gain, VDDANA = 3.0V, VREF = 1.0V,
350kSps at 25°C
41.10.4.3 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order
to achieve maximum accuracy. Seen externally, the ADC input consists of a resistor (RSAMPLE) and a capacitor
(CSAMPLE). In addition, the source resistance (RSOURCE) must be taken into account when calculating the required
sample and hold time. The next figure shows the ADC input channel equivalent circuit.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-5. ADC Input
VDDANA/2
Analog Input
AINx
RSOURCE
CSAMPLE
RSAMPLE
VIN
To achieve n bits of accuracy, the CSAMPLE capacitor must be charged at least to a voltage of
VCSAMPLE ≥ VIN × 1 + − 2− n + 1
The minimum sampling time tSAMPLEHOLD for a given RSOURCEcan be found using this formula:
tSAMPLEHOLD ≥ RSAMPLE + RSOURCE × CSAMPLE × n + 1 × ln 2
for a 12 bits accuracy: tSAMPLEHOLD ≥ RSAMPLE + RSOURCE × CSAMPLE × 9.02
41.10.5 Digital-to-Analog Converter (DAC) Characteristics
Table 41-28. Operating Conditions(1)
Symbol
Parameter
VDDANA
AVREF
Conditions
Min.
Typ.
Max.
Unit
Analog supply voltage
2.7
-
3.63
V
External reference voltage
1.0
-
VDDANA – 0.6
V
INT1V(3)
-
1
-
V
VDDANA
-
VDDANA
-
V
0.05
-
VDDANA – 0.05
V
Minimum resistive load
5
-
-
kΩ
Maximum capacitance load
-
-
100
pF
-
175
256
μA
Linear output voltage range
DC supply current(2)
IDD
Voltage pump disabled
Notes:
1. These values are based on specifications otherwise noted.
2. These values are based on characterization. These values are not covered by test limits in production.
3. It is the buffered internal reference of 1.0V derived from the internal 1.1V bandgap reference.
Table 41-29. Clock and Timing(1)
Parameter
Conditions
Conversion rate
Cload = 100pF
Rload > 5kΩ
Startup time
Min.
Typ.
Max.
Normal mode
-
-
350
For ΔDATA = ±1
-
-
1000
VDDNA > 2.6V
-
-
2.85
μs
VDDNA < 2.6V
-
-
10
μs
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Unit
ksps
DS40001882H-page 1019
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
1.
These values are based on simulation. These values are not covered by test limits in production or
characterization.
Table 41-30. Accuracy Characteristics(1)
Symbol
Min.
Typ.
Max.
Unit
-
-
10
Bits
VDD = 2.7V
±0.2
±0.5
±1
VDD = 3.6V
±0.2
±0.4
±1.2
VDD = 2.7V
±0.2
±0.6
±1.2
VDD = 3.6V
±0.2
±0.5
±1.3
VDD = 2.7V
±0.4
±0.7
±2
VDD = 3.6V
±0.4
±0.8
±6
VDD = 2.7V
±0.1
±0.3
±0.8
VDD = 3.6V
±0.1
±0.3
±0.8
VDD = 2.7V
±0.1
±0.2
±0.5
VDD = 3.6V
±0.1
±0.2
±1
VDD = 2.7V
±0.3
±0.6
±3
VDD = 3.6V
±0.3
±0.8
±7
VREF = Ext. VREF
-
±4
±16
mV
VREF = VDDANA
-
±12
±60
mV
VREF = INT1V
-
±1
±22
mV
VREF = Ext. VREF
-
±1
±13
mV
VREF = VDDANA
-
±2.5
±21
mV
VREF = INT1V
-
±1.5
±20
mV
Min.
Typ.
Max.
Unit
Positive input voltage range
0
-
VDDANA
Negative input voltage range
0
-
VDDANA
Hysteresis = 0, Fast mode
–26
0
26
mV
Hysteresis = 0, Low-power mode
–28
0
28
mV
Hysteresis = 1, Fast mode
8
50
102
mV
Hysteresis = 1, Low-power mode
14
50
75
mV
RES
Parameter
Conditions
Input resolution
VREF = Ext 1.0V
INL
Integral nonlinearity
VREF = VDDANA
VREF = INT1V
VREF = Ext 1.0V
DNL
VREF = VDDANA
Differential nonlinearity
VREF = INT1V
GE
Gain error
OE
Offset error
LSB
LSB
Note:
1. All values measured using a conversion rate of 35ksps.
41.10.6 Analog Comparator Characteristics
Table 41-31. Electrical and Timing
Parameter
Offset
Hysteresis
Conditions
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Complete Datasheet
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Propagation delay
Symbol
Typ.
Max.
Unit
Changes for VACM = VDDANA/2
100mV overdrive, Fast mode
90
180
ns
Changes for VACM = VDDANA/2
100mV overdrive, Low-power mode
302
534
ns
1
2
μs
-
14
23
μs
–1.4
0.201
1.4
LSB
–0.9
0.022
0.9
LSB
–0.2
0.056
0.92
LSB
–0.89
0.079
0.89
LSB
Enable to ready delay
Fast mode
Start-up time
tSTARTUP
Enable to ready delay
Low-power mode
INL(3)
DNL(3)
VSCALE
Offset Error (1)(2)
Gain Error
(1)(2)
1.
2.
3.
Min.
According to the standard equation V(X) = VLSB × (X + 1); VLSB = VDDANA/64
Data computed with the Best Fit method
Data computed using histogram
41.10.7 Bandgap and Internal 1.0V Reference Characteristics
Table 41-32. Bandgap and Internal 1.0V Reference Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
1.07
1.1
1.12
V
1.08
1.1
1.11
V
0.97
1.00
1.02
V
0.98
1.00
1.01
V
After calibration
at T= 25°C,
BANDGAP
Internal 1.1V
Bandgap
reference
over [–40°C,
+105°C],
VDD = 3.3V
Over voltage at
25°C
INT1V
After calibration
at T= 25°C, over
Internal 1.0V
[-40°C,+105°C],
reference voltage Vdd 3.3V
(1)
Over voltage at
25°C
Note:
1. These values are simulation based and are not covered by production test limits.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.11
NVM Characteristics
Table 41-33. Maximum Operating Frequency
VDD range
NVM Wait States
Maximum Operating Frequency
Unit
0
24
MHz
1
48
MHz
2.7V to 3.63V
Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 41-34. Flash Endurance and Data Retention
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Retention after up to 25k
Average ambient 55°C
RetNVM25k
10
50
-
Years
Retention after up to 2.5k
Average ambient 55°C
RetNVM2.5k
20
100
-
Years
Retention after up to 100
Average ambient 55°C
RetNVM100
25
>100
-
Years
Cycling Endurance(1)
–40°C < Ta < 105°C
CycNVM
25k
150k
-
Cycles
An endurance cycle is a write and an erase operation.
Table 41-35. EEPROM Emulation(1) Endurance and Data Retention
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Retention after up to 100k
Average ambient 55°C
RetEEPROM100k
10
50
-
Years
Retention after up to 10k
Average ambient 55°C
RetEEPROM10k
20
100
-
Years
Cycling Endurance(2)
–40°C < Ta
< 105°C
CycEEPROM
100k
600k
-
Cycles
The EEPROM emulation is a software emulation described in the App note AT03265. An endurance cycle is a write
and an erase operation.
Table 41-36. NVM Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Page programming time
-
tFPP
-
-
2.5
ms
Row erase time
-
tFRE
-
-
6
ms
DSU chip erase time (CHIP_ERASE)
-
tFCE
-
-
240
ms
41.12
Oscillators Characteristics
All temperature values are TC unless otherwise stated.
41.12.1 Crystal Oscillator (XOSC) Characteristics
41.12.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-37. Digital Clock Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
XIN clock frequency
Digital mode
Fxin
-
-
32
MHz
XIN clock duty cycle
Digital mode
DCxin
-
-
-
%
41.12.1.2 XOSC Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in
the table. The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
Table 41-38. Crystal Oscillator Characteristics
Parameter
Conditions
Crystal oscillator frequency
Symbol Min. Typ. Max. Unit
fOUT
0.4
-
32
-
-
5.6K
-
-
330
-
-
240
MHz
f = 0.455 MHz,
CL = 100pF
XOSC.GAIN = 0
f = 2 MHz,
CL = 20pF
XOSC.GAIN = 0
f = 4 MHz,
Crystal Equivalent Series Resistance
CL = 20pF
XOSC.GAIN = 1
Safety Factor = 3
The AGC does not have any noticeable impact on these
measurements.
f = 8 MHz,
CL = 20pF
ESR
Ω
-
-
105
-
-
60
-
-
55
XOSC.GAIN = 2
f = 16 MHz,
CL = 20pF
XOSC.GAIN = 3
f = 32 MHz,
CL = 18pF
XOSC.GAIN = 4
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol Min. Typ. Max. Unit
Parasitic capacitor load
CXIN
-
5.9
-
pF
Parasitic capacitor load
CXOUT
-
3.2
-
pF
Parameter
Conditions
Symbol
Min.
Typ.
Max.
-
15.6K
51.0K
-
6.3K
20.1K
-
6.2K
20.3K
-
7.7K
21.2K
-
6.0K
14.2K
Unit
f = 2 MHz,
CL = 20pF,
XOSC.GAIN = 0,
ESR = 600Ω
f = 4 MHz,
CL = 20pF,
XOSC.GAIN = 1,
ESR = 100Ω
f = 8 MHz,
CL = 20pF,
Startup time
XOSC.GAIN = 2,
tSTARTUP
cycles
ESR = 35Ω
f = 16 MHz,
CL = 20pF,
XOSC.GAIN = 3,
ESR = 25Ω
f = 32 MHz,
CL = 18pF,
XOSC.GAIN = 4,
ESR = 40Ω
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
-
89
190
-
82
187
-
140
256
-
102
219
-
243
380
Unit
f = 2 MHz,
CL = 20pF,
XOSC.GAIN = 0,
AGC off
f = 2 MHz,
CL = 20pF,
XOSC.GAIN = 0,
AGC on
f = 4 MHz,
Current Consumption
CL = 20pF,
XOSC.GAIN = 1,
μA
AGC off
f = 4 MHz,
CL = 20pF,
XOSC.GAIN = 1,
AGC on
f = 8 MHz,
CL = 20pF,
XOSC.GAIN = 2,
AGC off
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Conditions
Symbol
Min.
Typ.
Max.
-
166
299
-
493
685
-
293
480
-
1343
1975
-
555
776
Unit
f = 8 MHz,
CL = 20pF,
XOSC.GAIN = 2,
AGC on
f = 16 MHz,
CL = 20pF,
XOSC.GAIN = 3,
AGC off
f = 16 MHz,
Current Consumption
CL = 20pF,
XOSC.GAIN = 3,
μA
AGC on
f = 32 MHz,
CL = 18pF,
XOSC.GAIN = 4,
AGC off
f = 32 MHz,
CL = 18pF,
XOSC.GAIN = 4,
AGC on
Figure 41-6. Oscillator Connection
Xin
C LEXT
Crystal
LM
C SHUNT
RM
C STRAY
CM
C LEXT
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Xout
DS40001882H-page 1026
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.12.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
41.12.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 41-39. Digital Clock Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
XIN32 clock frequency
fCPXIN32
-
32.768
-
kHz
XIN32 clock duty cycle
DCxin
-
50
-
%
41.12.2.2 XOSC32K Characteristics
Figure 41-6 and the equation in 41.12.1.2 XOSC Characteristics also apply to the 32 kHz oscillator connection. The
user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The
exact value of CL can be found in the crystal data sheet.
Table 41-40. 32 kHz Crystal Oscillator Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
fOUT
-
32768
-
Hz
tSTARTUP
-
28K
30K
cycles
Crystal load capacitance
CL
-
-
12.5
pF
Crystal shunt capacitance
CSHUNT
-
0.1
-
pF
Parasitic capacitor load
CXIN32
-
3.2
-
pF
Parasitic capacitor load
CXOUT32
-
3.7
-
pF
Current consumption
IXOSC32K
-
1.22
2.2
μA
ESR
-
-
100
kΩ
Crystal oscillator frequency
ESRXTAL = 39.9 kΩ,
Start-up time
CL = 12.5 pF
Crystal equivalent series resistance
f = 32.768 kHz
CL=12.5pF
Safety Factor = 3
41.12.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 41-41. DFLL48M Characteristics - Open Loop Mode
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
fOUT
44.75
48
49
MHz
fOUT
43.75
48
49
MHz
fOUT
45.5
48
49
MHz
DFLLVAL.COARSE = DFLL48M COARSE CAL
Output frequency
DFLLVAL.FINE = 512
over [–10, +105]C, over [2.7, 3.6]V
DFLLVAL.COARSE = DFLL48M COARSE CAL
Output frequency
DFLLVAL.FINE = 512
over [–40, +105]C, over [2.7, 3.6]V
DFLLVAL.COARSE = DFLL48M COARSE CAL
Output frequency
DFLLVAL.FINE = 512
at 25°C, over [2.7, 3.6]V
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Power consumption on VDDIN
Conditions
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
Symbol
Min.
Typ.
Max.
Unit
IDFLL
-
403
453
μA
tSTARTUP
-
8.6
11.5
μs
DFLLVAL.COARSE = DFLL48M COARSE CAL
Startup time
DFLLVAL.FINE = 512
fOUT within 90 % of final value
Table 41-42. DFLL48M Characteristics - Closed Loop Mode(1)
Parameter
Average Output frequency
Conditions
fREF = XTAL, 32.768kHz, 100ppm
DFLLMUL = 1464
Reference frequency
Symbol
Min.
Typ.
Max.
Unit
fCloseOUT
47.963
47.972
47.981
MHz
fREF
0.732
32.768
33
kHz
Cycle to Cycle jitter
fREF = XTAL, 32.768kHz, 100ppm
DFLLMUL = 1464
Jitter
-
-
0.42
ns
Power consumption on VDDIN
fREF = XTAL, 32.768kHz, 100ppm
IDFLL
-
403
453
μA
tLOCK
-
350
1500
μs
fREF = XTAL, 32.768kHz, 100ppm
DFFLMUL = 1464
DFLLVAL.COARSE = DFLL48M
COARSE CAL
DFLLVAL.FINE = 512
Lock time
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Notes:
1. All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL closed loop
mode with an external OSC reference or the internal OSC8M.
2. To ensure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in
close loop must be within a 2% error accuracy.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.12.4 32.768 kHz Internal oscillator (OSC32K) Characteristics
Table 41-43. 32 kHz RC Oscillator Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
26.214
32.768
39.321
Unit
All temperatures TC
Calibrated against a 32.768 kHz
reference at 25°C,
over [–40, +105]°C,
over [2.7, 3.63]V
Output frequency
Calibrated against a 32.768 kHz
fOUT
reference at 25°C,
kHz
32.113
32.768
33.423
31.457
32.768
34.079
at VDD = 3.3V
Calibrated against a 32.768 kHz
reference at 25°C,
over [2.7, 3.63]V
Current consumption
IOSC32K
0.67
4.06
μA
Startup time
tSTARTUP
1
2
cycle
Duty Cycle
Duty
50
%
41.12.5 Ultra Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Characteristics
Table 41-44. Ultra Low-Power Internal 32 kHz RC Oscillator Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
24.576
32.768
40.960
Unit
All temperatures TC
Calibrated against a 32.768 kHz
reference
at 25°C,
over
[–40, +105]°C,
over [2.7, 3.63]V
Output frequency
Calibrated against a 32.768 kHz
reference
fOUT
at 25°C,
kHz
31.457
32.768
34.078
31.293
32.768
34.570
-
50
-
at VDD = 3.3V
Calibrated against a 32.768 kHz
reference
at 25°C,
over [2.7, 3.63]V
Duty Cycle
Duty
1.
These values are based on simulation. These values are not covered by test limits in production or
characterization.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
2.
This oscillator is always on.
41.12.6 8 MHz RC Oscillator (OSC8M) Characteristics
Table 41-45. Internal 8 MHz RC Oscillator Characteristics
Parameter
Conditions
Symbol Min. Typ. Max. Unit
Calibrated against a 8 MHz reference
at 25°C,
over [–10, +70]°C,
7.84
8
8.16
7.80
8
8.20
over [2.7, 3.6]V
Calibrated against a 8 MHz reference
at 25°C,
over [–10, +105]°C,
Output frequency
over [2.7, 3.6]V
fOUT
MHz
Calibrated against a 8 MHz reference
at 25°C,
7.66
8
8.34
7.88
8
8.12
IOSC8M
-
64
96
μA
tSTARTUP
-
2.3
3.9
μs
Duty
-
50
-
%
over [–40, +105]°C,
over [2.7, 3.6]V
Calibrated against a 8 MHz reference
at 25°C,
over [2.7, 3.6]V
Current consumption
IDLE2 on OSC32K versus IDLE2 on calibrated OSC8M enabled at 8 MHz
(FRANGE = 1, PRESC = 0)
Startup time
Duty cycle
41.12.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 41-46. FDPLL96M Characteristics(1) (Device Variant A / Die revision E)
Parameter
Conditions
Input frequency
Output frequency
Current consumption
fIN = 32kHz, fOUT = 48MHz
fIN = 32kHz, fOUT = 96MHz
Symbol
Min.
Typ.
Max.
Unit
fIN
32
-
2000
kHz
fOUT
48
-
96
MHz
-
500
733
-
900
1235
-
1.3
4
-
3.1
7
-
1.3
4
-
3.6
9
IFDPLL96M
fIN = 32kHz, fOUT = 48MHz
Period jitter
fIN = 32kHz, fOUT = 96MHz
fIN = 2MHz, fOUT = 48MHz
fIN = 2MHz, fOUT = 96MHz
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μA
%
DS40001882H-page 1030
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Parameter
Lock Time
Conditions
Symbol
Min.
Typ.
Max.
Unit
-
1
2
ms
-
25
50
μs
40
50
60
%
Symbol
Min.
Typ.
Max.
Unit
fIN
32
-
2000
kHz
fOUT
48
-
96
MHz
-
500
-
-
900
-
-
2.1
4.0
-
4.0
11.0
-
2.2
4.0
-
4.7
12.0
-
1.2
2
ms
-
25
35
μs
40
50
60
%
After startup, time to get lock signal.
fIN = 32kHz, fOUT = 96MHz
tLOCK
fIN = 2MHz, fOUT = 96MHz
Duty cycle
Duty
Table 41-47. FDPLL96M Characteristics(1) (Device Variant B / Die revision F)
Parameter
Conditions
Input frequency
Output frequency
Current consumption
fIN = 32kHz, fOUT = 48MHz
fIN = 32kHz, fOUT = 96MHz
IFDPLL96M
fIN = 32kHz, fOUT = 48MHz
Period jitter
fIN = 32kHz, fOUT = 96MHz
fIN = 2MHz, fOUT = 48MHz
Jp
fIN = 2MHz, fOUT = 96MHz
Lock Time
After startup, time to get lock signal.
fIN = 32kHz, fOUT = 96MHz
tLOCK
fIN = 2MHz, fOUT = 96MHz
Duty cycle
1.
Duty
μA
%
All values have been characterized with FILTSEL[1/0] as default value.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.13
PTC Typical Characteristics
41.13.1 Device Variant A
Figure 41-7. Power Consumption [μA]
1 sensor, noise countermeasures disabled, f=48MHz, Vcc=3.3V
140
120
100
80
Scan rate 10ms
60
Scan rate 50ms
40
Scan rate 100ms
Scan rate 200ms
20
0
1
2
4
8
16
32
64
Sample averaging
Figure 41-8. Power Consumption [μA]
1 sensor, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
200
180
160
140
120
Scan rate 10ms
100
80
Scan rate 50ms
60
Scan rate 100ms
40
Scan rate 200ms
20
0
1
2
4
8
16
32
64
Sample averaging
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-9. Power Consumption [μA]
10 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
1200
1000
800
Scan rate 10ms
600
Scan rate 50ms
Scan rate 100ms
400
Scan rate 200ms
200
Linear (Scan rate 50ms)
0
1
2
4
8
16
32
64
Sample averaging
Figure 41-10. Power Consumption [μA]
10 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
900
800
700
600
500
Scan rate 10ms
400
Scan rate 50ms
300
Scan rate 100ms
200
Scan rate 200ms
100
0
1
2
4
8
16
32
64
Sample averaging
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-11. Power Consumption [μA]
100 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
5000
4500
4000
3500
3000
Scan rate 10ms
2500
2000
Scan rate 50ms
1500
Scan rate 100ms
1000
Scan rate 200ms
500
0
1
2
4
8
16
32
64
Sample averaging
Figure 41-12. Power Consumption [μA]
100 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
1800
1600
1400
1200
1000
Scan rate 10ms
800
Scan rate 50ms
600
Scan rate 100ms
400
Scan rate 200ms
200
0
1
2
4
8
16
32
64
Sample averaging
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-13. CPU Utilization
80 %
70 %
60 %
50 %
Channel count 1
40 %
Channel count 10
30 %
Channel count 100
20 %
10 %
0%
10
50
100
200
41.13.2 Device Variant B,C and D
VCC = 3.3C and fCPU = 48 MHz for the following PTC measurements.
1Key / PTC_GCLK
= 4MHz / FREQ_MODE_NONE
Figure 41-14. 1 Sensor / PTC_GCLK = 4 MHz
/ FREQ_MODE_NONE
1
2
4
8
16
32
64
Sample Averaging
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
1Key / PTC_GCLK = 2MHz / FREQ_MODE_HOP
Figure 41-15. 1 Sensor / PTC_GCLK = 2 MHz
/ FREQ_MODE_HOP
1
2
4
8
16
32
64
32
64
Sample Averaging
= 4MHz / FREQ_MODE_NONE
Figure 41-16. 10 Sensor / PTC_GCLK = 410Keys
MHz/ PTC_GCLK
/ FREQ_MODE_NONE
1
2
4
8
16
Sample Averaging
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
= 2MHz / FREQ_MODE_HOP
Figure 41-17. 10 Sensor / PTC_GCLK = 210Keys
MHz/ PTC_GCLK
/ FREQ_MODE_HOP
1
2
4
8
16
32
64
32
64
Sample Averaging
Keys / PTC_GCLK
= 4MHz / FREQ_MODE_NONE
Figure 41-18. 100 Sensor / PTC_GCLK = 100
4 MHz
/ FREQ_MODE_NONE
1
2
4
8
16
Sample Averaging
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-19. 100 Sensor / PTC_GCLK = 100
2 MHz
/ FREQ_MODE_HOP
Keys / PTC_GCLK
= 2MHz / FREQ_MODE_HOP
1
2
4
8
16
32
64
Sample Averaging
Table 41-48. Sensor Load Capacitance
Symbol
Mode
PTC channel
Max Sensor Load (1)
Y0
16
Y1
23
Y2
19
Units
Y3
Y4
Y5
Y6
Cload
Self-capacitance
23
Y7
Y8
pF
Y9
Y10
19
Y11
Y12
Y13
23
Y14
Y15
Mutual-capacitance
All
30
Note:
1. Capacitance load that the PTC circuitry can compensate for each channel.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-49. Analog Gain Settings
Symbol
Gain
Setting
Average
GAIN_1
1.0
GAIN_2
2.0
GAIN_4
3.8
GAIN_8
8.0
GAIN_16
12.4
GAIN_32
-
Notes:
1. Analog Gain is a parameter of the QTouch Library. Refer to the QTouch Library Peripheral Touch Controller
User Guide.
2. GAIN_16 and GAIN_32 settings are not recommended, otherwise the PTC measurements might get unstable.
The values in the Power Consumption table below are measured values of power consumption under the following
conditions:
Operating conditions
VDD = 3.3 V
Clocks
OSC8M used as main clock source, running undivided at 8MHz
CPU is running on flash with 0 wait states, at 8MHz
PTC running at 4MHz
PTC configuration
Mutual-capacitance mode
One touch channel
System configuration
Standby sleep mode enabled
RTC running on OSCULP32K: used to define the PTC scan rate, through the event system
Drift Calibration disabled: no interrupts, PTC scans are performed in standby mode
Drift Calibration enabled: RTC interrupts (wakeup) the CPU to perform PTC scans. PTC drift calibration is performed
every 1.5 sec.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-50.
Symbol
Parameters
Drift
Calibration
PTC scan
Oversamples
rate (msec)
10
50
Disabled
100
200
IDD
50
Enabled
100
200
41.14
9
107
16
17
117
4
5
102
16
6
104
4
4
102
16
5
103
4
4
102
4
102
15
114
16
23
124
4
7
105
16
8
108
4
5
103
16
6
105
4
6
103
16
6
104
4
10
Typ. Max Units
4
16
Current
Consumption
Ta
Max 85°C Typ
25°C
µA
USB Characteristics
The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to
these buffers can be found within the USB 2.0 electrical specifications.
The USB interface is USB-IF certified:
- TID 40001583 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks
- TID 120000272 - Embedded Hosts > Full Speed
Electrical configuration required to be USB compliance:
- The CPU frequency must be higher 8MHz when USB is active (No constraint for USB suspend mode)
- The operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V).
- The GCLK_USB frequency accuracy source must be less than:
- In USB device mode, 48MHz +/-0.25%
- In USB host mode, 48MHz +/-0.05%
Table 41-51. GCLK_USB Clock Setup Recommendations
Clock setup
DFLL48M
USB Device
USB Host
Open loop
No
No
Closed loop, any internal OSC source
No
No
Yes
No
Yes(2)
N/A
Closed loop, any external XOSC source
Closed loop, USB SOF source (USB recovery
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Clock setup
FDPLL96M
USB Device
USB Host
Any internal OSC source (32K, 8M, ... )
No
No
Any external XOSC source (< 1MHz)
Yes
No
Any external XOSC source (> 1MHz)
Yes(3)
Yes
Notes: 1. When using DFLL48M in USB recovery mode, the Fine Step value must be Ah to guarantee a USB clock at
+/-0.25% before 11ms after a resume.
2. Very high signal quality and crystal less. It is the best setup for USB Device mode.
3. FDPLL lock time is short when the clock frequency source is high (> 1MHz). Thus, FDPLL and external OSC can
be stopped during USB suspend mode to reduce consumption and guarantee a USB wake-up time (See TDRSMDN
in USB specification).
41.15
Timing Characteristics
41.15.1 External Reset
Table 41-52. External Reset Characteristics
Symbol
Parameter
Condition
tEXT
Minimum reset pulse width
Min.
Typ.
Max.
Units
10
-
-
ns
Min.
Typ.
Max.
Units
1000
-
-
ns
Table 41-53. External Reset Characteristics (Silicon Revision G)
Symbol
Parameter
Condition
tEXT
Minimum reset pulse width
41.15.2 SERCOM in SPI Mode Timing
Figure 41-20. SPI Timing Requirements in Host Mode
tSCKR
tMOS
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data Input)
tMIH
tSCK
MSB
LSB
tMOH
tMOH
MOSI
(Data Output)
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-21. SPI Timing Requirements in Client Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data Input)
tSIH
tSSCK
MSB
LSB
tSOSSS
MISO
(Data Output)
tSOS
tSOSSH
MSB
LSB
Table 41-54. SPI Timing Characteristics and Requirements(1)
Symbol
Parameter
Conditions
tSCK
SCK period
Host
tSCKW
SCK high/low width
Host
-
0.5*tSCK
-
tSCKR
SCK rise time(2)
Host
-
-
-
Host
-
-
-
time(2)
Min.
Typ.
Max. Units
84
ns
tSCKF
SCK fall
tMIS
MISO setup to SCK
Host
-
21
-
tMIH
MISO hold after SCK
Host
-
13
-
tMOS
MOSI setup SCK
Host
-
tSCK/2 - 3
-
tMOH
MOSI hold after SCK
Host
-
3
-
tSSCK
Client SCK Period
Client
1*tCLK_APB
-
-
tSSCKW
SCK high/low width
Client
0.5*tSSCK
-
-
tSSCKR
SCK rise time(2)
Client
-
-
-
Client
-
-
-
time(2)
tSSCKF
SCK fall
tSIS
MOSI setup to SCK
Client
tSSCK/2 - 9
-
-
tSIH
MOSI hold after SCK
Client
tSSCK/2 - 3
-
-
tSSS
SS setup to SCK
Client
PRELOADEN=1
2*tCLK_APB + tSOS
-
-
PRELOADEN=0
tSOS+7
-
-
tSSH
SS hold after SCK
Client
tSIH - 4
-
-
tSOS
MISO setup SCK
Client
-
tSSCK/2 - 18
-
tSOH
MISO hold after SCK
Client
-
18
-
tSOSS
MISO setup after SS low
Client
-
18
-
tSOSH
MISO hold after SS high
Client
-
10
-
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Notes:
1. These values are based on simulation. These values are not covered by test limits in production.
2. See 41.8 I/O Pin Characteristics.
41.15.3 SERCOM in I2C Mode Timing
This section describes the requirements for devices connected to the I2C Interface Bus.
Figure 41-22. I2C Interface Bus Timing
tOF
tHIGH
tR
tLOW
tLOW
SCL
tSU;STA
tHD;STA
tHD;DAT
tSU;DAT
tSU;STO
SDA
tBUF
Table 41-55.
I2C
Interface Timing (Device Variant A)
Symbol Parameter
tR
tOF
Rise time for both SDA and SCL
Output fall time from VIHmin to
VILmax
Conditions
(2)
= 400pF
Min.
Typ. Max. Units
-
215
300
Standard / Fast
Mode
ICb
Fast
Mode +
ICb(2) = 550pF
60
100
High Speed
Mode
ICb(2) = 100pF
20
40
Standard / Fast
Mode
10pF < Cb(2) < 400pF
20.0 50.0
Fast
Mode +
10pF < Cb(2) < 550pF
15.0 50.0
High Speed
Mode
10pF < Cb(2)< 100pF
10.0 40.0
tHD;STA
Hold time (repeated) START
condition
fSCL > 100 kHz, Host
tLOW-9 -
-
tLOW
Low period of SCL Clock
fSCL > 100 kHz
113
-
-
tBUF
Bus free time between a STOP
and a START condition
fSCL > 100 kHz
tLOW
-
-
tSU;STA
Setup time for a repeated START
condition
fSCL > 100 kHz, Host
tLOW+7 -
-
tHD;DAT
Data hold time
fSCL > 100 kHz, Host
9
-
12
tSU;DAT
Data setup time
fSCL > 100 kHz, Host
104
-
-
tSU;STO
Setup time for STOP condition
fSCL > 100 kHz, Host
tLOW+9 -
-
tSU;DAT;rx Data setup time (receive mode)
fSCL > 100 kHz, Client 51
-
56
tHD;DAT;tx Data hold time (send mode)
fSCL > 100 kHz, Client 71
90
138
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Table 41-56. I2C Interface Timing (Device Variant B,C and D)
Symbol Parameter
tR
tOF
Rise time for both SDA and SCL
Output fall time from VIHmin to
VILmax
Conditions
(2)
= 400pF
Min.
Typ. Max. Units
-
230
350
Standard / Fast
Mode
Cb
Fast
Mode +
Cb(2) = 550pF
60
100
High Speed
Mode
Cb(2) = 100pF
30
60
Standard / Fast
Mode
10pF < Cb(2) < 400pF
25
50
Fast
Mode +
10pF < Cb(2) < 550pF
20
30
High Speed
Mode
10pF < Cb(2) < 100pF
10
20
tHD;STA
Hold time (repeated) START
condition
fSCL > 100 kHz, Host
tLOW-9 -
-
tLOW
Low period of SCL Clock
fSCL > 100 kHz
113
-
-
tBUF
Bus free time between a STOP
and a START condition
fSCL > 100 kHz
tLOW
-
-
tSU;STA
Setup time for a repeated START
condition
fSCL > 100 kHz, Host
tLOW+7 -
-
tHD;DAT
Data hold time
fSCL > 100 kHz, Host
9
-
12
tSU;DAT
Data setup time
fSCL > 100 kHz, Host
104
-
-
tSU;STO
Setup time for STOP condition
fSCL > 100 kHz, Host
tLOW+9 -
-
tSU;DAT;rx Data setup time (receive mode)
fSCL > 100 kHz, Client 51
-
56
tHD;DAT;tx Data hold time (send mode)
fSCL > 100 kHz, Client 71
90
138
ns
Notes:
1. These values are based on simulation. These values are not covered by test limits in production.
2. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF.
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SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
41.15.4 SWD Timing
Figure 41-23. SWD Interface Signals
Read Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Thigh
Tos
Data
Data
Parity
Start
Tlow
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Tri State
Write Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Tis
Start
Tih
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Data
Data
Parity
Tri State
Table 41-57. SWD Timings(1)
Symbol Parameter
Conditions
Min. Max.
Units
Thigh
SWDCLK High period
10
500000 ns
Tlow
SWDCLK Low period
VVDDIO from 3.0 V to 3.6 V, maximum external
capacitor = 40 pF
10
500000
Tos
SWDIO output skew to falling
edge SWDCLK
-5
5
Tis
Input Setup time required
between SWDIO
4
-
Tih
Input Hold time required
between SWDIO and rising
edge SWDCLK
1
-
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
41.15.5 I2S Timing
Figure 41-24. I2S Timing Host Mode
MCK output
tM_SCKOR
SCK output
FS output
SD output
tM_FSOH
tM_SDIS
tM_SDIH
tM_SCKOF
tM_SCKO
tM_SDOH
tM_FSOV
tM_SDOV
LSB right ch.
MSB left ch.
SD input
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1045
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
Figure 41-25. I2S Timing Client Mode
tS_FSIH
SCK input
tS_SCKI
tS_FSIS
FS input
tS_SDIS
tS_SDOH
tS_SDIH
tS_SDOV
SD output
LSB rignt ch.
MSB left ch.
SD input
Figure 41-26. I2S Timing PDM2 Mode
PDM2 mode
tPDM2RS tPDM2RH
tPDM2LS
tPDM2LH
SCK input
SD input
Left
Right
Left
Right
Left
Right
Table 41-58. I2S Timing Characteristics and Requirements (Device Variant A)
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max Min. Typ. Max.
tM_MCKOR
I2S MCK rise time(3)
Host mode / Capacitive load
CL = 15 pF
9.2
4.7
ns
tM_MCKOF
I2S MCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
11.5
5.3
ns
dM_MCKO
I2S MCK duty cycle
Host mode
50
%
dM_MCKI
I2S MCK duty cycle
Host mode, pin is input (1b)
tM_SCKOR
I2S SCK rise time(3)
Host mode / Capacitive load
CL = 15 pF
9
4.6
ns
tM_SCKOF
I2S SCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
9.7
4.5
ns
dM_SCKO
I2S SCK duty cycle
Host mode
50
%
fM_SCKO,1/
tM_SCKO
I2S SCK frequency
Host mode,Supposing external
device response delay is 30ns
8
9.5
MHz
fS_SCKI,1/
tS_SCKI
I2S SCK frequency
Client mode,Supposing
external device response
delay is 30ns
14.4
14.8
MHz
dS_SCKO
I2S SCK duty cycle
Client mode
tM_FSOV
FS valid time
Host mode
tM_FSOH
FS hold time
Host mode
-0.9
-0.9
ns
tS_FSIS
FS setup time
Client mode
2.3
1.5
ns
tS_FSIH
FS hold time
Client mode
0
0
ns
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
45.4
50
45.4
50
45.6
50
50
45.6
50
%
50
4.1
%
4
ns
DS40001882H-page 1046
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max Min. Typ. Max.
tM_SDIS
Data input setup time Host mode
34.7
24.5
ns
tM_SDIH
Data input hold time
-8.2
-8.2
ns
tS_SDIS
Data input setup time Client mode
4.6
3.9
ns
tS_SDIH
Data input hold time
1.2
1.2
ns
tM_SDOV
Data output valid time Host transmitter
tM_SDOH
Data output hold time Host transmitter
tS_SDOV
Data output valid time Client transmitter
tS_SDOH
Data output hold time Client transmitter
tPDM2LS
Host mode
Client mode
5.6
-0.5
4.8
-0.5
ns
ns
36.2
25.9
ns
36
25.7
ns
Data input setup time Host mode PDM2 Left
34.7
24.5
ns
tPDM2LH
Data input hold time
-8.2
-8.2
ns
tPDM2RS
Data input setup time Host mode PDM2 Right
30.5
20.9
ns
tPDM2RH
Data input hold time
-6.7
-6.7
ns
Host mode PDM2 Left
Host mode PDM2 Right
Table 41-59. I2S Timing Characteristics and Requirements (Device Variant B and C)
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tM_MCKOR
I2S MCK rise time(3)
Host mode / Capacitive load
CL = 15 pF
9.2
4.7
ns
tM_MCKOF
I2S MCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
11.6
5.4
ns
dM_MCKO
I2S MCK duty cycle
Host mode
50
%
dM_MCKI
I2S MCK duty cycle
Host mode, pin is input (1b)
tM_SCKOR
I2S SCK rise time(3)
Host mode / Capacitive load
CL = 15 pF
9
4.6
ns
tM_SCKOF
I2S SCK fall time(3)
Host mode / Capacitive load
CL = 15 pF
9.7
4.6
ns
dM_SCKO
I2S SCK duty cycle
Host mode
50
%
fM_SCKO, 1/
tM_SCKO
I2S SCK frequency
Host mode, Supposing
external device response
delay is 30ns
7.8
9.2
MHz
fS_SCKI, 1/tS_SCKI I2S SCK frequency
Client mode, Supposing
external device response
delay is 30ns
12.8
13
MHz
dS_SCKO
I2S SCK duty cycle
Client mode
tM_FSOV
FS valid time
Host mode
tM_FSOH
FS hold time
Host mode
-0.1
-0.1
ns
tS_FSIS
FS setup time
Client mode
6
5.3
ns
© 2021 Microchip Technology Inc.
and its subsidiaries
47.1
50
47.3
50
47
50
50
47.2
50
50
2.4
Complete Datasheet
%
%
1.9
ns
DS40001882H-page 1047
SAM D21/DA1 Family
SAM DA1 Electrical Characteristics
...........continued
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tS_FSIH
FS hold time
Client mode
0
0
ns
tM_SDIS
Data input setup time Host mode
36
25.9
ns
tM_SDIH
Data input hold time
-8.2
-8.2
ns
tS_SDIS
Data input setup time Client mode
9.1
8.3
ns
tS_SDIH
Data input hold time
3.8
3.7
ns
tM_SDOV
Data output valid time Host transmitter
tM_SDOH
Data output hold time Host transmitter
tS_SDOV
Data output valid time Client transmitter
tS_SDOH
Data output hold time Client transmitter
29.1
18.9
ns
tPDM2LS
Data input setup time Host mode PDM2 Left
35.5
25.3
ns
tPDM2LH
Data input hold time
-8.2
-8.2
ns
tPDM2RS
Data input setup time Host mode PDM2 Right
30.6
21.1
ns
tPDM2RH
Data input hold time
-7
-7
ns
Host mode
Client mode
Host mode PDM2 Left
2.5
-0.1
1.9
-0.1
29.8
Host mode PDM2 Right
ns
ns
19.7
ns
Notes:
1. All timing characteristics given for 15pF capacitive load.
2. These values are based on simulations and not covered by test limits in production.
3. See I/O Pin Characteristics.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1048
SAM D21/DA1 Family
Appendix A
42.
42.1
Appendix A
SIL 2 Enabled Functional Safety Devices
Microchip offers IEC 61508 SIL 2-enabled devices which can utilize the self-test library available on request from
Microchip Sales Office. The download includes the library binary, library user’s manual, and user’s checklist for
integration of the library. Refer to the “Embex SIL 2 Library User’s Manual” for additional information on using the IEC
61508 SIL 2-enabled Microchip devices.
Contact Microchip Sales Office for additional information on the IEC 61508 SIL 2-enabled devices, or to request a
part number which is not shown in the following Ordering Information.
42.1.1
Ordering Information
The following tables list the IEC 61508 SIL-enabled devices which can utilize the SIL 2 certified self-test library (STL).
Table 42-1. SAM D21J
Ordering Code
FLASH (bytes)
SRAM (bytes)
Temperature Grade
Package
Carrier Type
ATSAMD21J18A-AU-SLL
256K
32K
-40°C to 85°C
TQFP64
Tray
ATSAMD21J18A-MU-SLL
256K
32K
-40°C to 85°C
QFN64
Tray
Ordering Code
FLASH (bytes)
SRAM (bytes)
Temperature Grade
Package
Carrier Type
ATSAMD21G18A-AU-SLL
256K
32K
-40°C to 85°C
TQFP48
Tray
ATSAMD21G18A-MU-SLL
256K
32K
-40°C to 85°C
QFN48
Tray
Table 42-2. SAM D21G
Table 42-3. SAM D21E
Ordering Code
FLASH(bytes)
SRAM (bytes)
Temperature Grade
Package
Carrier Type
ATSAMD21E18A-AU-SLL
256K
32K
-40°C to 85°C
TQFP32
Tray
ATSAMD21E18A-MU-SLL
256K
32K
-40°C to 85°C
QFN32
Tray
ATSAMD21E17D-MUT-SLL
128K
16K
-40°C to 85°C
QFN32
Tape & Reel
ATSAMD21E16B-MU-SLL
64K
8K
-40°C to 85°C
QFN32
Tray
ATSAMD21E16B-MUT-SLL
64K
8K
-40°C to 85°C
QFN32
Tape & Reel
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1049
SAM D21/DA1 Family
Appendix B
43.
Appendix B
43.1
ISELED FULL License Enabled Functional Devices
Microchip offers ISELED full license enabled devices which can utilize the ISELED software stack and library
available for download from the Microchip Website. Included in the download will be the ISELED stack source code
file, header, the library binary, and the library user’s manual. Refer to the Inova data sheet of the INLC10AQ (ISELED
control commands; document AN-INLC_04; ) For more information on Microchip’s ISELED solutions, please visit the
Microchip Website (www.microchip.com/iseled).
Contact the Microchip Sales Office for more details on the ISELED full license enabled devices, or to request a part
number which is not available in the following Ordering Information.
43.2
Ordering Information
The following table lists the ISELED full license enabled devices, which can utilize the ISELED full license software
stack and library.
Table 43-1. D21 ISELED Licensed Devices
Ordering Code
Flash (bytes)
SRAM (bytes)
Temperature Grade
Package
Carrier Type
ATSAMD21J18A-AZT510
256K
32K
-40°C to 125°C
TQFP64
Tape & Reel
ATSAMD21J18A-AZ510
256K
32K
-40°C to 125°C
TQFP64
Tray
ATSAMD21G18A-AZT510
256K
32K
-40°C to 125°C
TQFP48
Tape & Reel
ATSAMD21G18A-AZ510
256K
32K
-40°C to 125°C
TQFP48
Tray
ATSAMD21E18A-AZT510
256K
32K
-40°C to 125°C
TQFP32
Tape & Reel
ATSAMD21E18A-AZ510
256K
32K
-40°C to 125°C
TQFP32
Tray
ATSAMD21E16B-AZT510
64K
8K
-40°C to 125°C
TQFP32
Tape & Reel
ATSAMD21E16B -AZ510
64K
8K
-40°C to 125°C
TQFP32
Tray
D21J:
D21G:
D21E:
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1050
SAM D21/DA1 Family
Packaging Information
44.
Packaging Information
44.1
Package Drawings
Note: For current package drawings, refer to the Microchip Packaging Specification, which is available at http://
www.microchip.com/packaging.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1051
SAM D21/DA1 Family
Packaging Information
44.1.1
64-Pin TQFP
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
A
B
E1/2
E1
A
E
A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D
1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
0.05
C
SEATING
PLANE
0.08 C
64 X b
0.08
e
A1
C A-B D
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1052
SAM D21/DA1 Family
Packaging Information
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
L
(L1)
X=A—B OR D
X
SECTION A-A
e/2
DETAIL 1
Notes:
Units
Dimension Limits
Number of Leads
N
e
Lead Pitch
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
Foot Length
L
Footprint
L1
Foot Angle
Overall Width
E
Overall Length
D
Molded Package Width
E1
Molded Package Length
D1
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
0.95
0.05
0.45
0°
0.09
0.17
11°
11°
MILLIMETERS
NOM
64
0.50 BSC
1.00
0.60
1.00 REF
3.5°
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
0.22
12°
12°
MAX
1.20
1.05
0.15
0.75
7°
0.20
0.27
13°
13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1053
SAM D21/DA1 Family
Packaging Information
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
E
C2
G
Y1
X1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X28)
X1
Contact Pad Length (X28)
Y1
Distance Between Pads
G
MIN
MILLIMETERS
NOM
0.50 BSC
11.40
11.40
MAX
0.30
1.50
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2085B Sheet 1 of 1
Table 44-1. Device and Package Maximum Weight
300
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1054
SAM D21/DA1 Family
Packaging Information
Table 44-2. Package Reference
Package Outline Drawing MCHP reference
C04-085
JESD97 Classification
E3
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1055
SAM D21/DA1 Family
Packaging Information
44.1.2
64-Pin VQFN
64-Lead Very Thin Plastic Quad Flat, No Lead Package (TMB) - 9x9 mm Body [VQFN]
Atmel Legacy Global Package Code ZST
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
64X
0.08 C
D
A
0.10 C
B
N
1
2
NOTE 1
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
A1
TOP VIEW
0.15 C
0.10
(A3)
C A B
D2
A
SEATING
C
PLANE
SIDE VIEW
0.10
C A B
E2
e
2
NOTE 1
K
2
1
N
L
e
BOTTOM VIEW
64X b
0.10
0.05
C A B
C
Microchip Technology Drawing C04-21441-TMB Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1056
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (TMB) - 9x9 mm Body [VQFN]
Atmel Legacy Global Package Code ZST
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Notes:
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
A3
Terminal Thickness
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
E2
Exposed Pad Width
Terminal Width
b
Terminal Length
L
Terminal-to-Exposed-Pad
K
MIN
0.80
0.00
4.60
4.60
0.15
0.30
0.20
MILLIMETERS
NOM
64
0.50 BSC
0.90
0.02
0.203 REF
9.00 BSC
4.70
9.00 BSC
4.70
0.20
0.40
-
MAX
1.00
0.05
4.80
4.80
0.25
0.55
-
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21441-TMB Rev A Sheet 2 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1057
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (TMB) - 9x9 mm Body [VQFN]
Atmel Legacy Global Package Code ZST
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
64
1
2
ØV
G2
C2 Y2
EV
Y1
G1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X64)
X1
Contact Pad Length (X64)
Y1
Contact Pad to Center Pad (X64)
G1
Contact Pad to Contact Pad (X60)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
4.80
4.80
8.90
8.90
0.30
0.90
1.60
0.20
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-21441-TMB Rev A Sheet 1 of 2
Note: The exposed die attach pad is not connected electrically inside the device. It is recommenced to attach
© 2018the
Microchip
Technology
(solder)
exposed
pad to a Inc.
matching perimeter landing beneath the package punctuated with vias to the ground
layer.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1058
SAM D21/DA1 Family
Packaging Information
Table 44-3. Device and Package Maximum Weight
200
mg
Table 44-4. Package Reference
Package Outline Drawing MCHP reference
C04-21441
JESD97 Classification
E3
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1059
SAM D21/DA1 Family
Packaging Information
44.1.3
64-Lead QFN with Sawn Wettable Flanks
64-Lead Very Thin Plastic Quad Flat, No Lead Package (U6B) - 9x9 mm Body [VQFN]
With 4.7 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZRB
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
64X
0.08 C
D
NOTE 1
A
0.10 C
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
TOP VIEW
0.10 C
0.05
0.20
0.10
C A B
0.90
SEATING
C
PLANE
D2
SIDE VIEW
DETAIL A
0.10
C A B
E2
A
e
2
A4
A
(K)
2
1
D3
SECTION A-A
STEPPED
WETTABLE
FLANK
N
L
e
BOTTOM VIEW
64X b
0.10
0.05
C A B
C
Microchip Technology Drawing C04-21497 Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1060
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (U6B) - 9x9 mm Body [VQFN]
With 4.7 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZRB
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Notes:
Units
Dimension Limits
N
Number of Terminals
e
Pitch
Overall Height
A
Standoff
A1
Terminal Thickness
A3
Overall Length
D
Exposed Pad Length
D2
E
Overall Width
Exposed Pad Width
E2
b
Terminal Width
L
Terminal Length
Terminal-to-Exposed-Pad
K
D3
Wettable Flank Step Length
Wettable Flank Step Height
A4
MIN
0.80
0.00
4.60
4.60
0.15
0.35
0.10
MILLIMETERS
NOM
MAX
64
0.50 BSC
0.85
0.90
0.035
0.05
0.203 REF
9.00 BSC
4.70
4.80
9.00 BSC
4.70
4.80
0.20
0.25
0.40
0.45
1.75 REF
0.085
0.19
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21497 Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1061
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (U6B) - 9x9 mm Body [VQFN]
With 4.7 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZRB
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
64
1
2
ØV
G2
C2
Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X64)
X1
Contact Pad Length (X64)
Y1
Contact Pad to Center Pad (X64)
G1
Contact Pad to Contact Pad (X60)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
4.80
4.80
8.90
8.90
0.30
0.85
1.63
0.20
0.33
1.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23497 Rev A
Table 44-5. Device and Package Maximum Weight
© 2018 Microchip Technology Inc.
200
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1062
SAM D21/DA1 Family
Packaging Information
Table 44-6. Package Reference
JEDEC Drawing Reference
C04-21497
JESD97 Classification
E3
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1063
SAM D21/DA1 Family
Packaging Information
44.1.4
64-Pin VQFN
64-Lead Very Thin Plastic Quad Flat, No Lead Package (5LX) - 9x9x1.0 mm Body [VQFN]
With 5.4 mm Exposed Pad and Stepped Wettable Flanks
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
64X
0.08 C
D
NOTE 1
A
0.10 C
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
A1
TOP VIEW
0.10 C
(A3)
0.10
A
C A B
SEATING C
PLANE
D2
SIDE VIEW
(K)
0.10
A
C A B
A
E2
e
2
A4
NOTE 1
2
1
D3
SECTION A-A
N
L
e
BOTTOM VIEW
64X b
0.10
0.05
STEPPED
WETTABLE
FLANK
C A B
C
Microchip Technology Drawing C04-483 Rev E Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1064
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (5LX) - 9x9x1.0 mm Body [VQFN]
With 5.4 mm Exposed Pad and Stepped Wettable Flanks
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
Terminal Thickness
A3
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
Terminal Width
b
Terminal Length
L
Terminal-to-Exposed-Pad
K
D3
Wettable Flank Step Length
Wettable Flank Step Height
A4
MILLIMETERS
MAX
NOM
64
0.50 BSC
0.80
1.00
0.90
0.00
0.02
0.05
0.203 REF
9.00 BSC
5.30
5.40
5.50
9.00 BSC
5.30
5.40
5.50
0.20
0.25
0.30
0.30
0.40
0.50
1.40 REF
0.035
0.060
0.085
0.10
0.19
MIN
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-483 Rev E Sheet 2 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1065
SAM D21/DA1 Family
Packaging Information
64-Lead Very Thin Plastic Quad Flat, No Lead Package (5LX) - 9x9x1.0 mm Body [VQFN]
With 5.4 mm Exposed Pad and Stepped Wettable Flanks
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
64
1
2
ØV
G2
C2
Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X64)
X1
Contact Pad Length (X64)
Y1
Contact Pad to Center Pad (X64)
G1
Contact Pad to Contact Pad (X60)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
5.50
5.50
8.90
8.90
0.30
0.85
1.28
0.20
0.33
1.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2483 Rev E
© 2018
Inc. Maximum Weight
Table
44-7.Microchip
Device Technology
and Package
232.4
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1066
SAM D21/DA1 Family
Packaging Information
Table 44-8. Package Reference
Package Outline Drawing MCHP reference
C04-00483
JESD97 Classification
E3
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1067
SAM D21/DA1 Family
Packaging Information
44.1.5
64-ball UFBGA
64-Ball Ultra Thin Fine-Pitch Ball Grid Array Package (BQB) - 5x5x0.65 mm Body
[UFBGA]; Atmel Legacy Global Package Code CAH
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
64X
0.10 C
D
A
0.10 C
1
2
3
4
5
6
7
8
B
A
B
C
D
E
E
F
G
H
2X
0.10 C
2X
A1
TOP VIEW
0.10 C
(S)
(M)
1
2
3
4
5
6
7
SEATING
PLANE
8
A
C
END VIEW
H
G
e
2
F
E
E2
D
C
B
A
NOTE 1
e
D2
BOTTOM VIEW
64X Øb
0.15
0.05
C A B
C
Microchip Technology Drawing C04-21153 Rev A Sheet 1 of 2
© 2020 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1068
SAM D21/DA1 Family
Packaging Information
64-Ball Ultra Thin Fine-Pitch Ball Grid Array Package (BQB) - 5x5x0.65 mm Body
[UFBGA]; Atmel Legacy Global Package Code CAH
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Ball Height
A1
Mold Thickness
M
Substrate Thickness
S
Overall Length
D
Ball Array Length
D2
Overall Width
E
Ball Array Width
E2
b
Ball Width
MIN
–
0.14
0.20
MILLIMETERS
NOM
64
0.50 BSC
–
0.19
0.25 REF
1.36 REF
5.00 BSC
3.50 BSC
5.00 BSC
3.50 BSC
0.25
MAX
0.65
0.24
0.3
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21153 Rev A Sheet 2 of 2
© 2020 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1069
SAM D21/DA1 Family
Packaging Information
64-Ball Ultra Thin Fine-Pitch Ball Grid Array Package (BQB) - 5x5x0.65 mm Body
[UFBGA]; Atmel Legacy Global Package Code CAH
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1
2
3
4
5
6
7
8
A
B
G
C
D
C2
E
F
G
H
SILK SCREEN
ØX
E
C1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (Xnn)
X
Contact Pad to Contact Pad (Xnn)
G
MIN
MILLIMETERS
NOM
0.50 BSC
3.50 BSC
3.50 BSC
MAX
0.20
0.30
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23153 Rev A
© 2020 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1070
SAM D21/DA1 Family
Packaging Information
Table 44-9. Device and Package Maximum Weight
27.4
mg
Table 44-10. Package Reference
Package Outline Drawing MCHP reference
C04-21153
JESD97 Classification
E8
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1071
SAM D21/DA1 Family
Packaging Information
44.1.6
48-Pin TQFP
48-Lead Plastic Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1
2
D
2
D
E1
2
A
B
E
E1
A
NOTE 1
A
E
2
N
N/4 TIPS
0.20 C A-B D
1
2
3
0.20 C A-B D 4X
e
2
e
TOP VIEW
C
SEATING
PLANE
A A2
48X
A1
48X b
0.08
0.08 C
C A-B D
SIDE VIEW
Microchip Technology Drawing C04-300-Y8 Rev D Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1072
SAM D21/DA1 Family
Packaging Information
48-Lead Plastic Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ϴ2
ϴ1
R2
H
R1
ϴ2
c
ϴ
L
(L1)
SECTION A-A
Notes:
Number of Terminals
Pitch
Overall Height
Standoff
Molded Package Thickness
Overall Length
Molded Package Length
Overall Width
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
Lead Angle
Mold Draft Angle
Units
Dimension Limits
N
e
A
A1
A2
D
D1
E
E1
b
c
L
L1
R1
R2
ϴ
ϴ1
ϴ2
MIN
0.05
0.95
0.17
0.09
0.45
0.08
0.08
0°
0°
11°
MILLIMETERS
NOM
48
0.50 BSC
1.00
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.22
0.60
1.00 REF
3.5°
12°
MAX
1.20
0.15
1.05
0.27
0.16
0.75
0.20
7°
13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-300-Y8 Rev D Sheet 2 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1073
SAM D21/DA1 Family
Packaging Information
48-Lead Plastic Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
G
C2
SILK SCREEN
48
Y1
1 2
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X48)
X1
Contact Pad Length (X48)
Y1
Distance Between Pads
G
MIN
MILLIMETERS
NOM
0.50 BSC
8.40
8.40
MAX
0.30
1.50
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2300-Y8 Rev D
Table
44-11.
Device
and Package
© 2018
Microchip
Technology
Inc. Maximum Weight
140
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1074
SAM D21/DA1 Family
Packaging Information
Table 44-12. Package Reference
Package Outline Drawing MCHP reference
C04-00300
JESD97 Classification
E3
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1075
SAM D21/DA1 Family
Packaging Information
44.1.7
48-Pin VQFN
48-Lead Very Thin Quad Flat Pack No-Leads (T3B) 7x7x0.9 mm [VQFN]
With 5.15x5.15 mm Exposed Pad; Atmel Legacy Global Package Code ZLG
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
A1
48X
0.08 C
D
NOTE 1
A
0.08 C
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
TOP VIEW
0.15 C
(A3)
0.10
C A B
D2
A
SEATING
C
PLANE
SIDE VIEW
E2
e
2
2
1
NOTE 1
0.10
C A B
N
L
e
BOTTOM VIEW
48X b
0.10
0.05
C A B
C
Microchip Technology Drawing C04-21425 Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1076
SAM D21/DA1 Family
Packaging Information
48-Lead Very Thin Quad Flat Pack No-Leads (T3B) 7x7x0.9 mm [VQFN]
With 5.15x5.15 mm Exposed Pad; Atmel Legacy Global Package Code ZLG
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Notes:
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
A3
Terminal Thickness
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
E2
Exposed Pad Width
Terminal Width
b
Terminal Length
L
Terminal-to-Exposed-Pad
K
MIN
0.80
0.00
5.05
5.05
0.18
0.30
0.20
MILLIMETERS
NOM
48
0.50 BSC
0.85
0.02
0.20 REF
7.00 BSC
5.15
7.00 BSC
5.15
0.25
0.40
-
MAX
0.90
0.05
5.25
5.25
0.30
0.50
-
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21425 Rev A Sheet 2 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1077
SAM D21/DA1 Family
Packaging Information
48-Lead Very Thin Quad Flat Pack No-Leads (T3B) 7x7x0.9 mm [VQFN]
With 5.15x5.15 mm Exposed Pad; Atmel Legacy Global Package Code ZLG
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
48
1
2
ØV
C2
Y2
G2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X20)
X1
Contact Pad Length (X20)
Y1
Contact Pad to Center Pad (X48)
G1
Contact Pad to Contact Pad (X44)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
5.15
5.15
6.90
6.90
0.30
0.90
0.20
0.20
0.33
1.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23425 Rev A
Note: The exposed die attach pad is not connected electrically inside the device. It is recommenced to attach
© 2018 Microchip Technology Inc.
(solder) the exposed pad to a matching perimeter landing beneath the package punctuated with vias to the ground
layer.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1078
SAM D21/DA1 Family
Packaging Information
Table 44-13. Device and Package Maximum Weight
140
mg
Table 44-14. Package Reference
Package Outline Drawing MCHP reference
C04-21425
JESD97 Classification
E3
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1079
SAM D21/DA1 Family
Packaging Information
44.1.8
48 lead VQFN with Sawn Wettable Flanks
48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN]
With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
48X
0.08 C
D
A
0.10 C
D
4
B
N
E
4
1
2
NOTE 1
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
TOP VIEW
0.10 C
A1
0.10 C A B
(A3)
D2
A
SEATING
C
PLANE
0.10 C A B
DETAIL A
SIDE VIEW
A
A
E2
A4
e
2
2
1
D3
SECTION A-A
N
(K)
L
e
BOTTOM VIEW
48X b
0.10
0.05
C A B
C
Microchip Technology Drawing C04-21493 Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1080
SAM D21/DA1 Family
Packaging Information
48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN]
With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Notes:
Units
Dimension Limits
N
Number of Terminals
e
Pitch
Overall Height
A
Standoff
A1
Terminal Thickness
A3
Overall Length
D
Exposed Pad Length
D2
E
Overall Width
Exposed Pad Width
E2
b
Terminal Width
L
Terminal Length
Terminal-to-Exposed-Pad
K
D3
Wettable Flank Step Length
Wettable Flank Step Height
A4
MIN
0,80
0.00
5.05
5.05
0.20
0.35
0.10
MILLIMETERS
NOM
MAX
48
0.50 BSC
0.85
0.90
0.02
0.05
0.203 REF
7.00 BSC
5.15
5.25
7.00 BSC
5.15
5.25
0.25
0.30
0.40
0.45
0.53 REF
0.085
0.19
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21493 Rev A Sheet 2 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1081
SAM D21/DA1 Family
Packaging Information
48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN]
With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
48
1
ØV
2
G2
C2 Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X48)
X1
Contact Pad Length (X48)
Y1
Contact Pad to Center Pad (X48)
G1
Contact Pad to Center Pad (X44)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
5.25
5.25
6.90
6.90
0.30
0.85
0.20
0.40
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23493 Rev A
Table
44-15.
Device
and Package
© 2018
Microchip
Technology
Inc. Maximum Weight
140
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1082
SAM D21/DA1 Family
Packaging Information
Table 44-16. Package Reference
JEDEC Drawing Reference
C04-21493
JESD97 Classification
E3
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1083
SAM D21/DA1 Family
Packaging Information
45-ball WLCSP
45-Ball Wafer Level Chip Scale Package (FSB) - 2.944x2.699 mm Body [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
NOTE 1
(DATUM
A)
E
(DATUM
B)
2X
0.03 C
2X
0.03 C
C
SEATING
PLANE
TOP VIEW
SEE DETAIL A
A
SIDE VIEW
D1
45X Øb
0.15
0.05
e
E1
C A B
C
e
44.1.9
NOTE 1
e
2
e
BOTTOM VIEW
Microchip Technology Drawing C04-21247 Rev A Sheet 1 of 2
© 2017 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1084
SAM D21/DA1 Family
Packaging Information
45-Ball Wafer Level Chip Scale Package (FSB) - 2.944x2.699 mm Body [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(A3)
0.10 C
A2
A1
45X
0.075 C
DETAIL A
Number of Terminals
Pitch
Overall Height
Bump Height
Die Thickness
Backside Coating
Overall Length
Overall Bump Pitch
Overall Width
Overall Bump Pitch
Terminal Width
Units
Dimension Limits
N
e
A
A1
A2
A3
D
D1
E
E1
b
MILLIMETERS
NOM
MAX
45
0.40 BSC
0.483
0.17
0.20
0.23
0.178
0.203
0.228
0.04 REF
2.944 BSC
2.40
2.699 BSC
2.079 BSC
0.23
0.26
0.29
MIN
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21247 Rev A Sheet 2 of 2
© 2017 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1085
SAM D21/DA1 Family
Packaging Information
45-Ball Wafer Level Chip Scale Package (FSB) - 2.944x2.699 mm Body [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ØX
E
C1
E
SILK SCREEN
C2
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Diameter (X45)
X
MIN
MILLIMETERS
NOM
0.40 BSC
2.079 BSC
2.40 BSC
0.26
MAX
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23247 Rev A
Table 44-17. Device and Package Maximum Weight
© 2017 Microchip Technology Inc.
7.3
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1086
SAM D21/DA1 Family
Packaging Information
Table 44-18. Package Reference
Package Outline Drawing MCHP reference
C04-21247
JESD97 Classification
E1
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1087
R
SAM D21/DA1 Family
Packaging Information
44.1.10 32-Pin TQFP
32-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
2.00 mm Footprint; Also Atmel Legacy Global Package Code AUT
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D
32X TIPS
0.20 C A-B D
A
B
E1
A
E
A
N
NOTE 1
1
2
4X
0.20 H A-B D
32X b
0.20
e
C A-B D
TOP VIEW
C
SEATING
PLANE
0.10 C
A A2
32X
0.10 C
A1
SIDE VIEW
Microchip Technology Drawing C04-074 Rev C Sheet 1 of 2
© 2017 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1088
SAM D21/DA1 Family
Packaging Information
32-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
2.00 mm Footprint; Also Atmel Legacy Global Package Code AUT
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
L
(L1)
SECTION A-A
Notes:
Units
Dimension Limits
N
Number of Leads
e
Lead Pitch
A
Overall Height
A1
Standoff
Molded Package Thickness
A2
Foot Length
L
Footprint
L1
Foot Angle
E
Overall Width
D
Overall Length
Molded Package Width
E1
Molded Package Length
D1
b
Lead Width
Mold Draft Angle Top
MIN
0.05
0.95
0.45
0°
0.30
11°
MILLIMETERS
NOM
32
0.80 BSC
1.00
0.60
1.00 REF
9.00 BSC
9.00 BSC
7.00 BSC
7.00 BSC
0.37
-
MAX
1.20
0.15
1.05
0.75
7°
0.45
13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-074 Rev C Sheet 2 of 2
© 2017 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1089
SAM D21/DA1 Family
Packaging Information
32-Lead Thin Plastic Quad Flatpack (PT) - 7x7 mm Body [TQFP]
2.00 mm Footprint; Also Atmel Legacy Global Package Code AUT
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
G
C2
Y
X
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (Xnn)
X
Contact Pad Length (Xnn)
Y
Contact Pad to Contact Pad (Xnn)
G
MIN
MILLIMETERS
NOM
0.80 BSC
8.40
8.40
MAX
0.55
1.55
0.25
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2074 Rev C
Table 44-19. Device and Package Maximum Weight
© 2018 Microchip Technology Inc.
100
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1090
SAM D21/DA1 Family
Packaging Information
Table 44-20. Package Reference
Package Outline Drawing MCHP reference
C04-00074
JESD97 Classification
E3
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1091
SAM D21/DA1 Family
Packaging Information
44.1.11 32-Pin VQFN
32-Lead Very Thin Plastic Quad Flat, No Lead Package (S8B) - 5x5 mm Body [VQFN]
With 3.60 mm Exposed Pad; Atmel Legacy Global Package Code ZKV
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
32X
0.08 C
D
NOTE 1
A
0.10 C
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
A1
TOP VIEW
0.15 C
(A3)
0.10
C A B
A
SEATING
C
PLANE
D2
0.10
C A B
SIDE VIEW
E2
e
2
K
2
1
NOTE 1
N
L
e
32X b
0.10
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-21402 Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1092
SAM D21/DA1 Family
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (S8B) - 5x5 mm Body [VQFN]
With 3.60 mm Exposed Pad; Atmel Legacy Global Package Code ZKV
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Notes:
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
A3
Terminal Thickness
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
E2
Exposed Pad Width
Terminal Width
b
Terminal Length
L
Terminal-to-Exposed-Pad
K
MIN
0.80
0.00
3.50
3.50
0.18
0.30
0.20
MILLIMETERS
NOM
32
0.50 BSC
0.90
0.02
0.20 REF
5.00 BSC
3.60
5.00 BSC
3.60
0.25
0.40
-
MAX
1.00
0.05
3.70
3.70
0.30
0.50
-
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21402 Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1093
SAM D21/DA1 Family
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (S8B) - 5x5 mm Body [VQFN]
With 3.60 mm Exposed Pad; Atmel Legacy Global Package Code ZKV
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
32
1
2
C2
Y2
ØV
G2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X32)
X1
Contact Pad Length (X32)
Y1
Contact Pad to Center Pad (X32)
G1
Contact Pad to Contact Pad (X28)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
3.70
3.70
5.00
5.00
0.30
0.85
0.23
0.20
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23402 Rev A
Note:
The exposed die attach pad is connected inside the device to GND and GNDANA.
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1094
SAM D21/DA1 Family
Packaging Information
Table 44-21. Device and Package Maximum Weight
90
mg
Table 44-22. Package Reference
Package Outline Drawing MCHP reference
C04-21402
JESD97 Classification
E3
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1095
SAM D21/DA1 Family
Packaging Information
44.1.12 32 lead VQFN with Sawn Wettable Flanks
32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]
With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
NOTE 1
A
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
TOP VIEW
0.10 C
C
SEATING
PLANE
A1
0.10 C
A
32X
(A3)
0.08 C
SIDE VIEW
0.10
C A B
D2
A4
DETAIL A
D3
A
A E2
e
2
SECTION A–A
PARTIALLY
PLATED
K
2
1
NOTE 1
0.10
C A B
N
L
e
BOTTOM VIEW
32X b
0.10
0.05
C A B
C
Microchip Technology Drawing C04-21391 Rev E Sheet 1 of 2
© 2017 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1096
SAM D21/DA1 Family
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]
With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
A3
Terminal Thickness
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
b
Terminal Width
Terminal Length
L
Terminal-to-Exposed-Pad
K
D3
Wettable Flank Step Cut Width
Wettable Flank Step Cut Depth
A4
MIN
0.80
0.00
3.50
3.50
0.20
0.35
0.20
0.10
MILLIMETERS
NOM
MAX
32
0.50 BSC
0.90
1.00
0.035
0.05
0.203 REF
5.00 BSC
3.60
3.70
5.00 BSC
3.60
3.70
0.25
0.30
0.40
0.45
0.085
0.19
Dimensions D3 and A4 above apply to all new products released after
November 1, and all products shipped after January 1, 2019, and supersede
dimensions D3 and A4 below.
No physical changes are being made to any package; this update is to align
cosmetic and tolerance variations from existing suppliers.
Notes:
Wettable Flank Step Length
Wettable Flank Step Height
D3
A4
0.035
0.10
0.06
-
0.085
0.19
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21391 Rev E Sheet 2 of 2
© 2017 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1097
SAM D21/DA1 Family
Packaging Information
32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]
With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
32
G1
1
ØV
2
CH
C2
G2
Y2
EV
X1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Exposed Pad 45° Corner Chamfer CH
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X32)
X1
Contact Pad Length (X32)
Y1
Contact Pad to Center Pad (X32)
G1
Contact Pad to Contact Pad (X28)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
3.70
3.70
0.25
5.00
5.00
0.30
0.80
0.25
0.20
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23391 Rev. E
Table 44-23. Device and Package Maximum Weight
© 2017 Microchip Technology Inc.
90
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1098
SAM D21/DA1 Family
Packaging Information
Table 44-24. Package Reference
JEDEC Drawing Reference
C04-21391
JESD97 Classification
E3
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1099
SAM D21/DA1 Family
Packaging Information
44.1.13 35 ball WLCSP (Device Variant B)
35-Ball Wafer Level Chip Scale Package (FQB) - 2.821x2.529 mm Body [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
NOTE 1
1
2
3
4
5
6
A
B
C
E
D
(DATUM B)
E
(DATUM A)
2X
0.03 C
F
2X
TOP VIEW
0.03 C
SEE DETAIL A
C
SEATING
PLANE
A
SIDE VIEW
D1
1
2
3
4
5
6
F
e
2
E
D
E1
C
B
A
NOTE 1
e
35X Øb
0.15
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-21245 Rev A Sheet 1 of 2
© 2017 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1100
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chip Scale Package (FQB) - 2.821x2.529 mm Body [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(A3)
0.10 C
A2
A1
35X
0.075 C
DETAIL A
Notes:
Number of Terminals
Pitch
Overall Height
Bump Height
Die Thickness
Backside Coating
Overall Length
Overall Bump Pitch
Overall Width
Overall Bump Pitch
Terminal Width
Units
Dimension Limits
N
e
A
A1
A2
A3
D
D1
E
E1
b
MILLIMETERS
NOM
MAX
35
0.40 BSC
0.483
0.17
0.20
0.23
0.178
0.203
0.228
0.04 REF
2.529 BSC
2.00 BSC
2.821 BSC
2.00 BSC
0.23
0.26
0.29
MIN
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21245 Rev A Sheet 2 of 2
© 2017 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1101
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chip Scale Package (FQB) - 2.821x2.529 mm Body [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1
2
3
4
5
6
A
B
ØX
C
C1
D
E
E
F
E
SILK SCREEN
C2
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Diameter (X35)
X
MIN
MILLIMETERS
NOM
0.40 BSC
2.00 BSC
2.00 BSC
0.26
MAX
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23245 Rev. A
Table 44-25. Device and Package Maximum Weight
© 2017 Microchip Technology Inc.
6.2
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1102
SAM D21/DA1 Family
Packaging Information
Table 44-26. Package Reference
JEDEC Drawing Reference
C04-21245
JESD97 Classification
E1
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1103
SAM D21/DA1 Family
Packaging Information
44.1.14 35 ball WLCSP (Device Variant C)
35-Ball Wafer Level Chip Scale Package (GFB) - 2.78x2.578x0.443 mm Body [WCLSP]
Atmel Global Package Code GJS
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
1
NOTE1
2
3
SEE DETAIL A
A
4
5
B
6
A
B
C
E
(DATUM B)
D
E
(DATUM A)
F
2X
0.03 C
2X
A
SEATING
C
PLANE
TOP VIEW
0.03 C
SIDE VIEW
D1
1
2
3
4
5
6
F
E
D
E1
C
B
A
35X Øb
e
2
e
0.05
0.015
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-21492 Rev A Sheet 1 of 2
© 2021 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1104
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chip Scale Package (GFB) - 2.78x2.578x0.443 mm Body [WCLSP]
Atmel Global Package Code GJS
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(A3)
0.10 C
A2
A1
35X
0.075 C
DETAIL A
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Bump Height
A1
Die Thickness
A2
A3
Backside Coating
Overall Length
D
Overall Bump Pitch
D1
Overall Width
E
Overall Bump Pitch
E1
b
Bump Diameter
MILLIMETERS
NOM
MAX
35
0.40 BSC
0.403
0.443
0.483
0.17
–
0.23
0.178
0.203
0.228
0.04 REF
2.578 BSC
2.00 BSC
2.78 BSC
2.00 BSC
0.23
0.26
0.29
MIN
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21492 Rev A Sheet 2 of 2
© 2021 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1105
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chip Scale Package (GFB) - 2.78x2.578x0.443 mm Body [WCLSP]
Atmel Global Package Code GJS
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1
2
3
4
5
6
A
B
G
C
C2
D
E
F
ØX
SILK SCREEN
E
C1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width
X
Contact Pad to Contact Pad (X35)
G
MILLIMETERS
NOM
0.40 BSC
2.00 BSC
2.00 BSC
MIN
MAX
0.20
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23492 Rev A
© 2021
Microchip
Inc. Maximum Weight
Table
44-27.
DeviceTechnology
and Package
6.22
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1106
SAM D21/DA1 Family
Packaging Information
Table 44-28. Package Reference
JEDEC Drawing Reference
C04-21492
JESD97 Classification
e1
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 1107
SAM D21/DA1 Family
Packaging Information
44.1.15 35 Ball WLCSP (Device Variant D)
35-Ball Wafer Level Chipscale Package (GUB) - 2.916x2.831 mm Body [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
35X
0.05 C
D
NOTE 1
1
3
2
A
4
5
0.06 C
B
6
A
B
C
E
D
(DATUM B)
(DATUM A)
E
F
2X
0.03 C
2X
TOP VIEW
0.03 C
A1
A3
A2
eD
e
2
A
SEATING
C
PLANE
SIDE VIEW
F
e
2
E
D
eE
C
B
A
1
2
3
4
5
6
35X Øb
e
0.015
C A B
BOTTOM VIEW
Microchip Technology Drawing C04-21491 Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1108
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chipscale Package (GUB) - 2.916x2.831 mm Body [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Notes:
Units
Dimension Limits
Number of Terminals
N
e
Pitch
A
Overall Height
Ball Height
A1
Die Thickness
A2
A3
Film Thickness
Overall Length
D
eD
Overall Pitch
E
Overall Width
eE
Overall Pitch
b
Ball Diameter
MILLIMETERS
MAX
NOM
35
0.40 BSC
0.403
0.483
0.443
0.23
0.17
0.20
0.178
0.203
0.228
0.036
0.040
0.044
2.831 BSC
2.00 BSC
2.916 BSC
2.00 BSC
0.24
0.27
0.30
MIN
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21491 Rev A Sheet 2 of 2
© 2018 Microchip Technology Inc.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1109
SAM D21/DA1 Family
Packaging Information
35-Ball Wafer Level Chipscale Package (GUB) - 2.916x2.831 mm Body [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
1
2
3
4
5
6
A
B
C
C2
D
E
F
ØX
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Diameter (X35)
X
MILLIMETERS
NOM
0.40 BSC
2.00
2.00
MIN
MAX
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23491 Rev A
Table 44-29. Device and Package Maximum Weight
© 2018 Microchip Technology Inc.
5.98
© 2021 Microchip Technology Inc.
and its subsidiaries
mg
Complete Datasheet
DS40001882H-page 1110
SAM D21/DA1 Family
Packaging Information
Table 44-30. Package Reference
44.2
JEDEC Drawing Reference
C04-21491
JESD97 Classification
e1
Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
Table 44-31. Recommended Soldering Profile
Profile Feature
Green Package
Average Ramp-up Rate (217°C to peak)
3°C/s max.
Preheat Temperature 175°C ±25°C
150-200°C
Time Maintained Above 217°C
60-150s
Time within 5°C of Actual Peak Temperature
30s
Peak Temperature Range
260°C
Ramp-down Rate
6°C/s max.
Time 25°C to Peak Temperature
8 minutes max.
A maximum of three reflow passes is allowed per component.
44.3
Package Markings
All devices are marked with the Atmel logo and the ordering code.
Additional marking is as follows:
Where:
•
•
•
•
“YY”: Manufacturing year
“WW”: Manufacturing week
“R”: Internal Code
“XXXXXX”: Lot number
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SAM D21/DA1 Family
Schematic Checklist
45.
Schematic Checklist
45.1
Introduction
This chapter describes a common checklist which should be used when starting and reviewing the schematics for a
SAM D21 design. This chapter illustrates a recommended power supply connection, how to connect external analog
references, programmer, debugger, oscillator and crystal.
45.1.1
Operation in Noisy Environment
If the device is operating in an environment with much electromagnetic noise, it must be protected from this noise to
ensure reliable operation. In addition to following best practice EMC design guidelines, the recommendations listed
in the schematic checklist sections must be followed. In particular, placing decoupling capacitors very close to the
power pins, an RC-filter on the RESET pin, and a pull-up resistor on the SWCLK pin is critical for reliable operations.
It is also relevant to eliminate or attenuate noise in order to avoid that it reaches supply pins, I/O pins and crystals.
45.2
Power Supply
The SAM D21 supports a single power supply from 1.62V - 3.63V.
45.2.1
Power Supply Connections
Figure 45-1. Power Supply Schematic(1)
Close to device
(for every pin)
1.62V-3.63V
VDDANA
10µF
100nF
GNDANA
VDDIO
100nF
VDDIN
100nF
VDDCORE
10µF
1µF
GND
Note: 1. It is recommended to use a ceramic or solid tantalum capacitor with low ESR. Refer to table 37-18 in
37.11.1 Voltage Regulator Characteristics for additional details on ESR.
Table 45-1. Power Supply Connections, VDDCORE From Internal Regulator
Signal Name Recommended Pin Connection
Description
VDDIO
Digital supply voltage
1.62V - 3.63V
Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1)
Decoupling/filtering inductor 10μH(1)(3)
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SAM D21/DA1 Family
Schematic Checklist
...........continued
Signal Name Recommended Pin Connection
Description
VDDANA
Analog supply voltage
1.62V - 3.63V
Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1)
Ferrite bead(4) prevents the VDD noise interfering the VDDANA
VDDCORE
1.6V to 1.8V
Decoupling/filtering capacitor 1μF(1)(2)
Core supply voltage / external
decoupling pin
GND
Ground
GNDANA
Ground for the analog power domain
Notes:
1. These values are only given as typical examples.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group, low
ESR caps should be used for better decoupling.
3. An inductor should be added between the external power and the VDD for power filtering.
4. Ferrite bead has better filtering performance than the common inductor at high frequencies. It can be added
between VDD and VDDANA for preventing digital noise from entering the analog power domain. The bead
should provide enough impedance (e.g. 50Ω at 20MHz and 220Ω at 100MHz) for separating the digital power
from the analog power domain. Make sure to select a ferrite bead designed for filtering applications with a low
DC resistance to avoid a large voltage drop across the ferrite bead.
45.3
External Analog Reference Connections
The following schematic checklist is only necessary if the application is using one or more of the external analog
references. If the internal references are used instead, the following circuits are not necessary.
Figure 45-2. External Analog Reference Schematic With Two References
Close to device
(for every pin)
AREFA
EXTERNAL
REFERENCE 1
4.7µF
100nF
GND
AREFB
EXTERNAL
REFERENCE 2
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4.7µF
100nF
GND
Complete Datasheet
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SAM D21/DA1 Family
Schematic Checklist
Figure 45-3. External Analog Reference Schematic With One Reference
Close to device
(for every pin)
AREFA
EXTERNAL
REFERENCE
4.7µF
100nF
GND
AREFB
100nF
GND
Table 45-2. External Analog Reference Connections
Signal Name
Recommended Pin Connection
Description
AREFx
1.0V to VDDANA - 0.6V for ADC
External reference from AREFx pin on
the analog port
1.0V to VDDANA- 0.6V for DAC
Decoupling/filtering capacitors
100nF(1)(2) and 4.7μF(1)
GND
1.
2.
45.4
Ground
These values are given as a typical example.
Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group.
External Reset Circuit
The external Reset circuit is connected to the RESET pin when the external Reset function is used. The circuit is not
necessary when the RESET pin is not driven low externally by the application circuitry.
The reset switch can also be removed, if a manual reset is not desired. The RESET pin itself has an internal pull-up
resistor, hence it is optional to add any external pull-up resistor.
A pull-up resistor makes sure that the reset does not go low and unintentionally cause a device reset. An additional
resistor has been added in series with the switch to safely discharge the filtering capacitor, that is, preventing a
current surge when shorting the filtering capacitor, which again can cause a noise spike that can have a negative
effect on the system.
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SAM D21/DA1 Family
Schematic Checklist
Figure 45-4. External Reset Circuit Schematic
VDD
10k Ω
RESET
330Ω
100nF
GND
Figure 45-5. External Reset Circuit Schematic (EFT Immunity Enhancement)
VDD
2.2kΩ
330Ω
100pF
RESET
GND
Note: This reset circuit is intended to improve EFT immunity, but does not filter low-frequency glitches, which makes
it not suitable as an example for applications requiring debouncing on a reset button.
Table 45-3. Reset Circuit Connections
Signal Name Recommended Pin Connection
Description
RESET
Reset pin
Reset low-level threshold voltage
VDDIO = 1.6V - 2.0V: Below 0.33 * VDDIO
VDDIO = 2.7V - 3.6V: Below 0.36 * VDDIO
Decoupling/filter capacitor 100 pF(1)Pull-up resistor 2.2 kΩ(1)(2)Resistor in series with
the switch 330Ω(1)
1.
These values are given as a typical example.
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SAM D21/DA1 Family
Schematic Checklist
2.
45.5
The SAM D21 features an internal pull-up resistor on the RESET pin, hence an external pull-up is optional.
Clocks and Crystal Oscillators
The SAM D21 can be run from internal or external clock sources, or a mix of internal and external sources. An
example of usage will be to use the internal 8MHz oscillator as source for the system clock, and an external
32.768kHz watch crystal as clock source for the Real-Time counter (RTC).
45.5.1
External Clock Source
Figure 45-6. External Clock Source Example Schematic
External
Clock
XIN
XOUT/GPIO
NC/GPIO
Table 45-4. External Clock Source Connections
45.5.2
Signal Name
Recommended Pin Connection
Description
XIN
XIN is used as input for an external clock signal
Input for inverting oscillator pin
XOUT/GPIO
Can be left unconnected or used as normal GPIO
Crystal Oscillator
Figure 45-7. Crystal Oscillator Example Schematic
XIN
CLEXT
XOUT
CLEXT
The crystal should be located as close to the device as possible. Long signal lines may cause a load too high to
operate the crystal, and cause crosstalk to other parts of the system.
Table 45-5. Crystal Oscillator Checklist
Signal Name
(1)(2)
XIN
Load capacitor CLEXT
XOUT
Load capacitor CLEXT(1)(2)
1.
2.
45.5.3
Recommended Pin Connection
Description
External crystal between 0.4 to 30 MHz
Use the equation in Crystal Oscillator Characteristics to calculate CLEXT.
Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group.
External Real Time Oscillator
The low-frequency crystal oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals,
load capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into consideration. Both values are
specified by the crystal vendor.
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SAM D21/DA1 Family
Schematic Checklist
The SAM D21 oscillator is optimized for very-low-power consumption, so pay close attention when selecting crystals.
See the table below for maximum ESR recommendations on 9pF and 12.5pF crystals.
The low-frequency crystal oscillator provides an internal load capacitance of typical values available in Table , 32 kHz
Crystal Oscillator Characteristics. This internal load capacitance and PCB capacitance can use a crystal inferior to
12.5pF load capacitance without external capacitors as shown in the following figure.
Table 45-6. Maximum ESR Recommendation for 32.768 kHz Crystal
Crystal CL (pF)
Max ESR [kΩ]
12.5
313
Note: Maximum ESR is typical value based on characterization. These values are not covered by test limits in
production.
Figure 45-8. External Real Time Oscillator without Load Capacitor
XIN32
32.768kHz
XOUT32
However, to improve crystal accuracy and safety factor, the data sheet recommends adding external capacitors as
shown in the next figure.
To find suitable load capacitance for a 32.768 kHz crystal, consult the crystal data sheet.
Figure 45-9. External Real Time Oscillator with Load Capacitor
XIN32
CLEXT
32.768kHz
XOUT32
CLEXT
Table 45-7. External Real Time Oscillator Checklist
Signal Name
Recommended Pin Connection
Description
XIN32
Load capacitor CLEXT(1)(2)
Timer oscillator input
XOUT32
1.
2.
Load capacitor
CLEXT(1)(2)
Timer oscillator output
Use the equation in Crystal Oscillator Characteristics to calculate CLEXT.
Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group.
Note:
In order to minimize the cycle-to-cycle jitter of the external oscillator, keep the neighboring pins as steady as possible.
For neighboring pin details, refer to the Oscillator Pinout section.
Related Links
7.2.1 Oscillator Pinout
37.13 Oscillators Characteristics
45.5.4
Calculating the Correct Crystal Decoupling Capacitor
In order to calculate correct load capacitor for a given crystal, refer to Oscillator Characteristics for parasitic load
capacitance values and equation to calculate CLEXT.
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SAM D21/DA1 Family
Schematic Checklist
45.6
Unused or Unconnected Pins
For unused pins, the default state of the pins for the will provide the lowest current leakage. There is no need to do
any configuration of the unused pins in order to lower the power consumption.
45.7
Programming and Debug Ports
For programming and/or debugging the SAM D21 the device should be connected using the Serial Wire Debug,
SWD, interface. Currently the SWD interface is supported by several Microchip and third party programmers
and debuggers, like the JTAGICE3, SAM-ICE, ATMEL_ICE or SAM D21 Xplained Pro ( SAM D21 evaluation kit)
Embedded Debugger.
Refer to the JTAGICE3, SAM-ICE, ATMEL_ICE or SAM D21 Xplained Pro user guides for details on debugging and
programming connections and options. For connecting to any other programming or debugging tool, refer to that
specific programmer or debugger’s user guide.
The SAM D21 Xplained Pro evaluation board for the SAM D21 supports programming and debugging through the
onboard embedded debugger so no external programmer or debugger is needed.
Note that a pull-up resistor on the SWCLK pin is critical for reliable operations. Refer to related link for more
information.
Figure 45-10. SWCLK Circuit Connections
VDD
1kΩ
SWCLK
Table 45-8. SWCLK Circuit Connections
Pin Name
Description
Recommended Pin Connection
SWCLK
Serial wire clock pin
Pull-up resistor 1kΩ
Related Links
45.1.1 Operation in Noisy Environment
45.7.1
Cortex Debug Connector (10-pin)
For debuggers and/or programmers that support the Cortex Debug Connector (10-pin) interface the signals should be
connected as shown in the figure below with details described in the next table.
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SAM D21/DA1 Family
Schematic Checklist
Figure 45-11. Cortex Debug Connector (10-pin)
VDD
Cortex Debug Connector
(10-pin)
VTref
GND
1
SWDIO
SWDCLK
GND
NC
NC
NC
NC
nRESET
RESET
SWCLK
SWDIO
GND
Table 45-9. Cortex Debug Connector (10-pin)
Header Signal Name Description
Recommended Pin
Connection
SWDCLK
Serial wire clock pin
Pull-up resistor 1kΩ
SWDIO
Serial wire bidirectional data pin
RESET
Target device reset pin, active low
Refer to 45.4 External Reset Circuit.
45.7.2
VTref
Target voltage sense, should be connected to the device
VDD
GND
Ground
10-pin JTAGICE3 Compatible Serial Wire Debug Interface
The JTAGICE3 debugger and programmer does not support the Cortex Debug Connector (10-pin) directly, hence a
special pinout is needed to directly connect the SAM D21 to the JTAGICE3, alternatively one can use the JTAGICE3
squid cable and manually match the signals between the JTAGICE3 and SAM D21. The following figure describes
how to connect a 10-pin header that support connecting the JTAGICE3 directly to the SAM D21 without the need for
a squid cable.
To connect the JTAGICE3 programmer and debugger to the SAM D21, one can either use the JTAGICE3 squid
cable, or use a 10-pin connector as shown in the figure below with details given in the next table to connect to the
target using the JTAGICE3 50 mil cable directly.
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SAM D21/DA1 Family
Schematic Checklist
Figure 45-12. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
10-pin JTAGICE3 Compatible
VDD
Serial Wire Debug Header
SWDCLK
GND
1
NC
RESET
VTG
SWDIO
RESET
NC
NC
NC
NC
SWCLK
SWDIO
GND
Table 45-10. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
45.7.3
Header Signal Name
Description
SWDCLK
Serial wire clock pin
SWDIO
Serial wire bidirectional data pin
RESET
Target device reset pin, active low
VTG
Target voltage sense, should be connected to the device VDD
GND
Ground
20-pin IDC JTAG Connector
For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the signals
should be connected as shown in the next figure with details described in the table.
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SAM D21/DA1 Family
Schematic Checklist
Figure 45-13. 20-pin IDC JTAG Connector
VDD
20-pin IDC JTAG Connector
VCC
1
NC
NC
GND
NC
GND
SWDIO
GND
SWDCLK
GND
NC
GND
NC
GND*
nRESET
GND*
NC
GND*
NC
GND*
RESET
SWCLK
SWDIO
GND
Table 45-11. 20-pin IDC JTAG Connector
Header Signal Name Description
45.8
SWDCLK
Serial wire clock pin
SWDIO
Serial wire bidirectional data pin
RESET
Target device reset pin, active low
VCC
Target voltage sense, should be connected to the device VDD
GND
Ground
GND*
These pins are reserved for firmware extension purposes. They can be left open or
connected to GND in normal debug environment. They are not essential for SWD in
general.
USB Interface
The USB interface consists of a differential data pair (D+/D-) and a power supply (VBUS, GND). Refer to the
Electrical Characteristics for operating voltages which will allow USB operation.
Table 45-12. USB Interface Checklist
Signal
Name
D+
Recommended Pin Connection
•
•
D-
•
The impedance of the pair should be matched on the PCB to minimize
reflections.
USB differential tracks should be routed with the same characteristics
(length, width, number of vias, etc.)
Signals should be routed as parallel as possible, with a minimum
number of angles and vias
© 2021 Microchip Technology Inc.
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Description
Complete Datasheet
USB full speed / low
speed positive data
upstream pin
USB full speed / low
speed negative data
upstream pin
DS40001882H-page 1121
SAM D21/DA1 Family
Schematic Checklist
Figure 45-14. Low Cost USB Interface Example Schematic
USB
Connector
VBUS
D+
DGND
VBUS
USB
Differential
Data Line Pair
USB_D+
USB_D-
Shield
GND (Board)
It is recommended to increase ESD protection on the USB D+, D-, and VBUS lines using dedicated transient
suppressors. These protections should be located as close as possible to the USB connector to reduce the potential
discharge path and reduce discharge propagation within the entire system.
The USB FS cable includes a dedicated shield wire that should be connected to the board with caution. Special
attention should be paid to the connection between the board ground plane and the shield from the USB connector
and the cable.
Tying the shield directly to ground would create a direct path from the ground plane to the shield, turning the USB
cable into an antenna. To limit the USB cable antenna effect, it is recommended to connect the shield and ground
through an RC filter.
Figure 45-15. Protected USB Interface Example Schematic
VBUS
USB Transient
protection
USB
Connector
USB
Differential
Data Line Pair
VBUS
D+
DGND
RC Filter
(GND/Shield
Connection)
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USB_D-
4.5nF
1MO
Shield
USB_D+
GND (Board)
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SAM D21/DA1 Family
Conventions
46.
Conventions
46.1
Numerical Notation
Table 46-1. Numerical Notation
46.2
Symbol
Description
165
Decimal number
0b0101
Binary number (example 0b0101 = 5 decimal)
'0101'
Binary numbers are given without prefix if unambiguous
0x3B24
Hexadecimal number
X
Represents an unknown or don't care value
Z
Represents a high-impedance (floating) state for either a
signal or a bus
Memory Size and Type
Table 46-2. Memory Size and Bit Rate
46.3
Symbol
Description
KB (kbyte)
kilobyte (210 = 1024)
MB (Mbyte)
megabyte (220 = 1024*1024)
GB (Gbyte)
gigabyte (230 = 1024*1024*1024)
b
bit (binary '0' or '1')
B
byte (8 bits)
1kbit/s
1,000 bit/s rate (not 1,024 bit/s)
1Mbit/s
1,000,000 bit/s rate
1Gbit/s
1,000,000,000 bit/s rate
word
32 bit
half-word
16 bit
Frequency and Time
Table 46-3. Frequency and Time
Symbol
Description
kHz
1 kHz = 103 Hz = 1,000 Hz
KHz
1 KHz = 1,024 Hz, 32 KHz = 32,768 Hz
MHz
1 MHz = 106 Hz = 1,000,000 Hz
GHz
1 GHz = 109 Hz = 1,000,000,000 Hz
s
second
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SAM D21/DA1 Family
Conventions
...........continued
46.4
Symbol
Description
ms
millisecond
µs
microsecond
ns
nanosecond
Registers and Bits
Table 46-4. Register and Bit Mnemonics
Symbol
Description
R/W
Read/Write accessible register bit. The user can read from and write to this bit.
R
Read-only accessible register bit. The user can only read this bit. Writes will be ignored.
W
Write-only accessible register bit. The user can only write this bit. Reading this bit will return an
undefined value.
BIT
Bit names are shown in uppercase. (Example ENABLE)
FIELD[n:m]
A set of bits from bit n down to m. (Example: PINA[3:0] = {PINA3, PINA2, PINA1, PINA0}
Reserved
Reserved bits are unused and reserved for future use. For compatibility with future devices,
always write reserved bits to zero when the register is written. Reserved bits will always return
zero when read.
Reserved bit field values must not be written to a bit field. A reserved value will not be read from
a read-only bit field.
PERIPHERALi
If several instances of a peripheral exist, the peripheral name is followed by a number to indicate
the number of the instance in the range 0-n. PERIPHERAL0 denotes one specific instance.
Reset
Value of a register after a power Reset. This is also the value of registers in a peripheral after
performing a software Reset of the peripheral, except for the Debug Control registers.
SET/CLR
Registers with SET/CLR suffix allows the user to clear and set bits in a register without doing
a read-modify-write operation. These registers always come in pairs. Writing a ‘1’ to a bit in the
CLR register will clear the corresponding bit in both registers, while writing a ‘1’ to a bit in the
SET register will set the corresponding bit in both registers. Both registers will return the same
value when read. If both registers are written simultaneously, the write to the CLR register will
take precedence.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1124
SAM D21/DA1 Family
Acronyms and Abbreviations
47.
Acronyms and Abbreviations
The below table contains acronyms and abbreviations used in this document.
Table 47-1. Acronyms and Abbreviations
Abbreviation
Description
AC
Analog Comparator
ADC
Analog-to-Digital Converter
ADDR
Address
AES
Advanced Encryption Standard
AHB
Advanced High-performance Bus
AMBA®
Advanced Microcontroller Bus Architecture
APB
AMBA Advanced Peripheral Bus
AREF
Analog reference voltage
BLB
Boot Lock Bit
BOD
Brown-out Detector
CAL
Calibration
CC
Compare/Capture
CCL
Configurable Custom Logic
CLK
Clock
CRC
Cyclic Redundancy Check
CTRL
Control
DAC
Digital-to-Analog Converter
DAP
Debug Access Port
DFLL
Digital Frequency Locked Loop
DPLL
Digital Phase Locked Loop
DMAC
DMA (Direct Memory Access) Controller
DSU
Device Service Unit
EEPROM
Electrically Erasable Programmable Read-Only Memory
EIC
External Interrupt Controller
EVSYS
Event System
FDPLL
Fractional Digital Phase Locked Loop, also DPLL
GCLK
Generic Clock Controller
GND
Ground
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
IF
Interrupt flag
INT
Interrupt
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and its subsidiaries
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DS40001882H-page 1125
SAM D21/DA1 Family
Acronyms and Abbreviations
...........continued
Abbreviation
Description
MBIST
Memory built-in self-test
MEM-AP
Memory Access Port
MTB
Micro Trace Buffer
NMI
Non-maskable interrupt
NVIC
Nested Vector Interrupt Controller
NVM
Non-Volatile Memory
NVMCTRL
Non-Volatile Memory Controller
OSC
Oscillator
PAC
Peripheral Access Controller
PC
Program Counter
PER
Period
PM
Power Manager
POR
Power-on reset
PORT
I/O Pin Controller
PTC
Peripheral Touch Controller
PWM
Pulse Width Modulation
RAM
Random-Access Memory
REF
Reference
RTC
Real-Time Counter
RX
Receiver/Receive
SEEP
SmartEEPROM Page
SERCOM
Serial Communication Interface
SMBus™
System Management Bus
SP
Stack Pointer
SPI
Serial Peripheral Interface
SRAM
Static Random-Access Memory
SUPC
Supply Controller
SWD
Serial Wire Debug
TC
Timer/Counter
TCC
Timer/Counter for Control Applications
TRNG
True Random Number Generator
TX
Transmitter/Transmit
ULP
Ultra low-power
USART
Universal Synchronous and Asynchronous Serial Receiver and Transmitter
USB
Universal Serial Bus
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1126
SAM D21/DA1 Family
Acronyms and Abbreviations
...........continued
Abbreviation
Description
VDD
Common voltage to be applied to VDDIO, VDDIN and VDDANA
VDDIN
Digital supply voltage
VDDIO
Digital supply voltage
VDDANA
Analog supply voltage
VREF
Voltage reference
WDT
Watchdog Timer
XOSC
Crystal Oscillator
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1127
SAM D21/DA1 Family
Data Sheet Revision History
48.
Data Sheet Revision History
Page numbers listed in this section refer to this document. The revision listed in this section refers to the document
revision.
48.1
Revision H - September 2021
Section
Description
SYSCTRL
Removed erroneous text from the DFLLRDY bitfield of the PCLKSR Register.
DMAC
Removed non-applicable text from Burst Transfer in DMA.
TCC
Updated the number of TCC Instances in Overview.
ADC
Updated the Equations in Prescaler for Single-Shot and Free-Running Modes.
AC
Added a new paragraph to Overview for L-Variant devices.
DAC
Updated Synchronization to reflect that no bits need synchronization.
Electrical Characteristics
at 85°C
•
•
•
Updated the POR Operating Principle figure to properly reflect an Internal RESET
in Power-On-Reset (POR) Characteristics
Updated the following figures in BOD33 to properly display the Internal RESET:
– BOD33 Hysteresis OFF
– BOD33 Hysteresis ON
Removed erroneous SS line from the SPI Timing Requirements in Host Mode figure
in SERCOM in SPI Mode Timing
SAM DA1 Electrical
Characteristics at 105°C
Updated the values in the BOD33 LEVEL Value table in BOD33.
Appendix B
Updated Ordering Information with a new table reflecting all ISELED parts.
Packaging Information
Updated the following packages with a new note:
• 64-Pin VQFN
• 48-Pin VQFN
Added the following package:
• 64-Lead VQFN
48.2
Revision G - April 2021
This revision includes the updates as listed in the following table, and numerous typographical corrections throughout
the document.
Section
Description
General
The SPI, I2S, and I2C standards use the terminology "Master" and "Slave". The equivalent
Microchip terminology used in this document is "Host" and "Client" respectively.
These terms have been updated throughout this document for this revision.
Features
Updated RWW to RWWEE for Memories
Ordering
Information
Updated RWW to RWWEE in the Device Variant description
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Complete Datasheet
DS40001882H-page 1128
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Description
Pinout
Updated the following Pinouts to accurately display the RESET pin
• QFN48
• QFN32 / TQFP32
• UFBGA64
• WLCSP45
• WLCSP35
I/O Multiplexing
Product Mapping
•
•
•
Added a new notes to table 7-1 for SERCOM and TCC3 availability
Added a new note to table 7-2 for TCC3 availability
Removed erroneous text from the header of Table 7-5 in SERCOM I2C Pins
Updated RWW to RWWEE in the figure
Memories
•
•
•
Updated EEPROM and RWWEE text in Embedded Memories
Updated RWW to RWWEE in all the tables in Physical Memory Map
Updated Table 10-7 in NVM User Row Mapping to display text for Emulation
Processor and
Architecture
•
•
Updated the Addresses of the bits in SRAM Quality of Service
Updated the following registers, changing clear to set:
– PCA0 Register WPSET
– PCA1 Register WPSET
– PCA2 Register WPSET
DSU
•
•
Added verbiage for RWWEE Emulation to Chip Erase
Updated table 13-3 in 32-bit Cyclic Redundancy Check CRC32 with proper capitalization
on Emulation
Updated table 13-6 in System Services Availability when Accessed Externally and Device
is Protected with the correct RWWEE verbiage
Updated the DEVSEL bit of the DID Register with information for Device identification
•
•
Clock System
Updated Read Request with new verbiage for the READREQ.RCONT and READREQ.RREQ
bits
GCLK
Updated the GENDIV Register with a new Register property, and added a new column for the
Maximum Division Factor to the table for the DIV bit.
SYSCTRL
RTC
DMAC
EIC
•
Updated the following registers:
– XOSC with new verbiage for the AMPGC and GAIN bits
– DFLLCTRL - removed erroneous RUNSTDBY bit
Updated the Overview with new verbiage for clock sources selectable through the GCLK.
•
Updated the following registers:
– BASEADDR with new text for the bitfield BASEADDR
– WRBADDR with new text for the bitfield WRBADDR
– SRCADDR with new text for the bitfield SRCADDR
– DSTADDR with new text for the bitfield DSTADDR
– DESCADDR bitfield was updated for 64 bit alignment in the DESCADDR register
Updated the EXTINTx bit of the INTENCLR register to read “disables the external interrupt.”
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1129
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Description
NVMCTRL
•
•
•
•
Updated the Overview with new text for the EEPROM Emulation array
Updated Memory Organization with new EEPROM Emulation verbiage
Updated NVM User Configuration with new EEPROM Emulation verbiage
Updated the following registers:
– PARAM
– The ADDR bit of the ADDR Register was updated with new verbiage
– The LOCK bit of the LOCK Register was updated with the correct reset value
EVSYS
•
•
Updated Features with new event user verbiage
Updated the CHSTATUS Register with a new Reset value for the USRRDY bitfield
SERCOM I2C
•
•
Updated the Signal Description with a cross reference to the proper I/O Multiplexing table
In DMA, Interrupts and Events, erroneous information referring to the TX FIFO and RX
FIFO was removed from table 28-1 and table 28-2
In Interrupts erroneous information regarding the RX FIFO and TX FIFO was removed
Updated the SYNCBUSY Register to remove the SYSOP bitfield
Updated the DATA Register with a new register Property and added a note to the DATA
Bitfield
•
•
•
I2S
Added new slotsize information to PDM Reception.
TC
Updated the RCONT bit of the READREQ Register with new verbiage for clearing and reading
the RREQ and RCONT bits.
USB
Updated the SPEED Bitfield of the STATUS Register with the proper allocation of low-speed
and full-speed mode.
ADC
DAC
Electrical
Characteristics at
85°C
•
•
Updated the Block Diagram to properly display INTVCC0/1, and updated the note
Updated the Note for the REFSEL bit of the REFCTRL Register
Updated the CTRLB Register with a new note for the REFSEL bitfield.
•
•
•
•
•
In Maximum Clock Frequencies, table 37-7 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 37-24
– 37-25
– 37-26
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 37-32
– 37-34
– 37-35
Updated table 37-38 in Bandgap and Internal 1.0V Reference Characteristics with new
symbol values
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 1130
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
Electrical
Characteristics at
105°C
Description
•
•
•
•
•
Electrical
Specifications at
125°C
•
•
•
•
In Maximum Clock Frequencies, table 38-4 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 38-10
– 38-11
– 38-12
Updated table 38-14 in Performance with the Hardware Offset and Gain Correction by
applying the Conditions value to the whole column
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 38-15
– 38-16
– 38-17
In Maximum Clock Frequencies, table 39-4 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 39-13
– 39-14
– 39-15
– 39-16
– 39-17
– 39-18
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 39-19
– 39-20
– 39-22
– 39-23
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Complete Datasheet
DS40001882H-page 1131
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
AEC-Q100 125°C
Specifications
Description
•
•
•
•
•
SAM DA1
Electrical
Characteristics
•
•
•
•
•
Appendix B
In Maximum Clock Frequencies, table 40-7 and 40-9 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 40-24
– 40-25
– 40-26
– 40-27
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 40-30
– 40-32
– 40-33
Updated table 40-36 in Bandgap and Internal 1.0V Reference Characteristics with new
symbol values
In Maximum Clock Frequencies, table 41-6 was updated with a new maximum
specification and units for the DAC input clock frequency
The POR Operating Principle figure in Power-On Reset (POR) Characteristics was
updated to properly display the RESET designation
Analog-to-Digital (ADC) Characteristics had numerous updates with new symbol values
and new rows added to the following tables:
– 41-23
– 41-24
– 41-25
Digital to Analog Converter (DAC) Characteristics had numerous updates to merge cells,
add new parameter values, and notes to the following tables:
– 41-28
– 41-30
Updated table 41-32 in Bandgap and Internal 1.0V Reference Characteristics with new
symbol values
Added a new Appendix for ISELED Specifications.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1132
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
48.3
Section
Description
Packaging
The following packages were updated with new drawings:
• 64TQFP
• 64 pin QFN
• 64 Lead QFN with Sawn Wettable Flanks
• 64-ball UFBGA
• 48 pin TQFP
• 48 pin QFN
• 48 lead QFN with Sawn Wettable Flanks
• 45-ball WLCSP
• 32 pin TQFP
• 32 pin QFN
• 32 lead QFN with Sawn Wettable Flanks
• 35-ball WLCSP (Device Variant B)
• 35-ball WLCSP (Device Variant C)
• 35-ball WLCSP (Device Variant D)
Revision F - March 2020
This revision includesthe updates as listed in the following table, and several typographical corrections throughout the
document.
Section
Description
Appendix A
Added a new appendix SIL 2 Enabled Functional Safety Devices
Packaging Information
Added ‘35-ball WLCSP (Device variant D)’
DAC
ADC
•
•
Updated the INTENSET register, changed disable to enable for interrupts.
Updated the SYNCRDY bit of the INTENSET Register.
Added information about internal 1.0V buffered reference voltage.
Added information about internal 1.0V buffered reference voltage.
Updated CALIB register description.
SAM DA1 Electrical
Characteristics
Updated I2C Pins Characteristics in I2C Configuration in I2C Pins.
Updated label for internal 1.1V Bandgap Reference
Added information about internal 1.0V buffered reference voltage for ADC and DAC.
SERCOM I2C
Updated the SYSOP bit of the SYNCBUSY Register with the removal of erroneous
text
SERCOM SPI
Updated DOPO description.
EIC
Note added for CONFIGn registers.
DMAC
Updatetd Sleep mode operation description.
SYSCTRL
Removed reference to BOD12 registers. Added ENABLE bit in the VREG register.
DSU
Related linked added in the DID register description.
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SAM D21/DA1 Family
Data Sheet Revision History
48.4
Revision E - January 2020
This revision encompasses changes made to combine the SAM D21 Data Sheet with the SAM DA1 Data Sheet to
improve readability and information access.
Section
Description
Block Diagram
Added arrow between PORT and AHB-APB BRIDGE B.
Pinout
Updated section titles
Product Mapping
Updated the diagram to show the Internal Flash.
PORT I/O Pin Controller
Corrected the WRCONFIG register to show the
DRVSTR bit.
SERCOM
Under Clock Generation - Baud-Rate Generator, the
table was updated with a new information and equations.
SERCOM USART
•
•
•
SERCOM SPI
•
•
•
SERCOM I2C
•
•
•
•
•
•
•
•
Timer Counter (TC)
•
•
© 2021 Microchip Technology Inc.
and its subsidiaries
Information regarding FIFO was removed as it is
not supported on this device
The FIFOCLR bit was removed from the CTRLB
register
The FIFOSPACE and FIFOPTR registers were
removed
Information on FIFO was removed as it is not
supported on this device
The FIFOCLR bit was removed from the CTRLB
register
The FIFOSPACE and FIFOPTR registers were
removed
Information on FIFO was removed as it is not
supported on this device
The FIFOCLR bit was removed from the CTRLB
Slave Register
Bit fields RXFF and TXFE were removed from
the INTENCLR, INTENSET, and INTFLAG Slave
Registers
The LENERR bit was removed from the STATUS
Slave Register
Registers FIFOSPACE and FIFOPTR were
removed from the Slave Registers
The FIFOCLR bit was removed from the CTRLB
Master Register
Bit fields, RXFF and TXFE, were removed from
the INTENCLR, INTENSET, and INTFLAG Master
Registers
Registers FIFOSPACE and FIFOPTR were
removed from the Master Registers
In Counter Mode, Count32 was updated with new
TC numbering
The register summaries for 8-bit Mode, 16-bit
Mode, and 32-bit Mode were updated to correctly
display
Complete Datasheet
DS40001882H-page 1134
SAM D21/DA1 Family
Data Sheet Revision History
...........continued
Section
TCC
Description
•
•
•
•
•
•
•
•
USB
Updated cross references.
ADC
Updated the MUXPOS Bit table in the INPUTCTRL
register.
AC
•
•
•
•
•
•
•
48.5
FCTRLA and FCTRLB had their naming corrected
In the WEXCTRL register the DTIEN bit had the
numbering updated
In the DRVCTRL register the numbering was
updated for the INVENx, NRVx, and NREx bits
In the EVCTRL register the numbering was updated
for the MCEOx, MCEIx, TCEIx, and TCINVx
Registers
In the INTENCLR, INTENSET, and INTFLAG
registers the numbering was updated for the MCx
bit
In the STATUS register the numbering was updated
for the CMPx and FAULTx bits
The PATT register was updated to properly display
the PGVx and PGEx bits
The PATTB register was updated to properly display
the PGVBx and PGEBx bits
Updated the STARTx bit numbering in the CTRLB
register
Updated the bit numbering for the COMPEIx,
COMPEOx, and WINEOx bits in the EVCTRL
register
Updated the bit numbering for the WINx, and
COMPx bits in the INTENCLR, INTENSET, and
INTFLAG registers
Updated the bit numbering for the WSTATEx and
STATEx bits in the STATUSA register
Updated the bit numbering for the READYx bit in
the STATUSB register
Updated the bit numbering for the WSTATEx and
STATEx bits in the STATUSC register
Updated the bit numbering for the WINTSELx and
WENx bits in the WINCTRL register
SAM DA1 Electrical Characteristics
This section was migrated into this data sheet from the
original SAM DA1 data sheet.
Schematic Checklist
Updated External Reset Circuit with changes to the
diagram External Reset Circuit Schematic.
Packaging Information
Updated Package Markings with a new marking
diagram.
Rev D - 9/2018
Configuration Summary
Updated to Add new packages for device variant D.
Product Mapping
Updated diagram.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1135
SAM D21/DA1 Family
Data Sheet Revision History
RTC
Updated READREQ register tables.
DMAC
Updated Channel Control B Register tables.
24. EVSYS – Event System
•
•
DAC
Updated the Channel Register tables
Updated the User Register tables.
Updated the 35.3 Block Diagram to display ADC Input.
Electrical Characteristics at 85°C
•
Updated Decoupling Requirements table.
.
38. Electrical Characteristics at 105°C
39. Electrical Characteristics at 125°C
AEC-Q100 Electrical Characteristics at 125°C
Packaging Information
48.6
48.7
Updated the WLSCP 45-Ball Package diagram.
Rev. C – 06/2018
Features
•
Added Qualification AEC-Q100 Grade 1 (-40C to 125C).
Ordering Information
•
Added: under Package Grade Z = -40 – 125C Matte Sn Plating AEC-Q100
Electrical Characteristics
•
Updated with new chapter for AEC-Q100 Specifications.
Packaging Information
•
Added QFN package drawings with wettable flanks.
Rev. B – 04/2018
General
•
•
This revision was updated to include the SAM D21EL and SAM D21GL Variant
information, which was released separately in DS40001883A. The SAM D21EL/SAM
D21GL Data Sheet (DS40001883A) is superseded by this revision (DS40001882B).
IOBUS start addressed is added which was missing in previous revision
(DS40001882A).
Electrical
Characteristics
•
•
Clarified ESR information for VDDCORE capacitor
Typo addressed for VDDIN capacitor value
DMA
•
RUNSTDBY not supported, typo addressed
AC
•
Continuous Mode SleepWalking figure is updated
ADC
•
Bandgap reference as input was omitted in previous version of the data sheet. It is
added in this version.
Packaging
Information
•
•
WLCSP package drawings updated
Thermal characteristic for 45-ball WLCSP & 64-pin UFBGA is added
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1136
SAM D21/DA1 Family
Data Sheet Revision History
48.8
Rev. A – 01/2017
General
•
•
•
•
Template: Updated from Atmel to Microchip template.
Document number: Changed from the Atmel 42181 to Microchip xxxxx.
Document revision letter reset to A.
ISBN number added.
Electrical
Characteristics
•
•
Die Revision F final characterization added.
37.7 Power Consumption: Added Standby typical numbers for Device Variant C / Die
Revision F.
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added
characterization data for Device Variant C / Die Revision F.
•
Errata
•
New errata added:
– B
– Device Variant A: Errata reverence 15625, 15683, 15753 added.
– Device Variant B: Errata reverence 15625, 15683, 15753 added.
– Device Variant C: Errata reverence 15625, 15683, 15753 added.
39. Electrical
Characteristics at
125°C
•
•
Die Revision F final characterization is preliminary.
39.5 Power Consumption: Added Standby typical numbers for Device Variant C / Die
Revision F.
39.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added
characterization data for Device Variant C / Die Revision F.
•
48.9
Rev. O – 12/2016
General
•
Introduced Device Variant C.
37. Electrical
Characteristics at 85℃
•
•
Die Revision F characterization is preliminary.
37.7 Power Consumption: Added Standby typical numbers for Device Variant C /
Die Revision F.
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added
characterization data for Device Variant C / Die Revision F.
•
39. Electrical
Characteristics at 125°C
•
•
•
48.10
Die Revision F characterization is preliminary.
39.5 Power Consumption: Added Standby typical numbers for Device Variant C /
Die Revision F.
39.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added
characterization data for Device Variant C / Die Revision F.
Rev. N – 10/2016
7. I/O Multiplexing and
Considerations
•
7.1 Multiplexed Signals: Updated table note 6 with information on PA24
and PA25.
10. Memories
•
10.3.1 NVM User Row Mapping: Added BOOTPROT default value for
WLCSP.
30. TC – Timer/Counter
•
•
30.5.3 Clocks: Corrected TC instance numbers.
30.6.2.4 Counter Mode: Corrected TC instance numbers.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1137
SAM D21/DA1 Family
Data Sheet Revision History
37. Electrical Characteristics at 85℃
48.11
37.9.1 Normal I/O Pins: Added condition to Pull-up - Pull-down
resistance.
Rev. M – 09/2016
2. Configuration
Summary
•
Added information on number of pins for the SAM D21G WLCSP pakcage option.
SAM D21G is offered in 48 pin packages, while the WLCSP has 45 pins.
3. SAM D21 Ordering
Information(1)
•
Added information to the pin count explanation. For the The G letter indicates 48 pin
packages, while the WLCSP option is 45 pins.
ATSAMD21E18A-MFUT corrected to ATSAMD21E18A-MFT.
Device Identification:
– Removed C variants.
– Added device identification values for the devices in WLCSP packages. These
have separate device id's compared to the other package options.
•
•
18. WDT – Watchdog
Timer
48.12
•
•
18.5.7 Debug Operation: Removed the sentence "This peripheral can be forced
to continue operation during debugging." The WDT can not be forced to continue
operation in debug mode.
Rev. L – 09/2016
2. Configuration Summary
•
Added information on number of pins for the WLCSP pakcage. SAM D21E is
offered in 32 pin packages, while the WLCSP has 35 pins.
13. DSU - Device Service Unit
•
13.11.5 Testing of On-Board Memories MBIST: Updated description.
14. Clock System
•
14.5 Disabling a Peripheral: New section added.
17. SYSCTRL – System
Controller
•
17.8.5 XOSC.AMPGC bit description updated.
21. EIC – External Interrupt
Controller
•
21.6.6 Interrupts: Added note explaining how it works when the same
external interrupt (EXTINT) is common on sevral pins.
24. EVSYS – Event System
•
24.8.1 CTRL.SWRST: Added recommendation when doing a software reset.
28. SERCOM I2C – InterIntegrated Circuit
•
Corrected cross references in the Master 28.10.1 CTRLA.SCLSM and Slave
28.8.1 CTRLASCLSM bits.
31. TCC – Timer/Counter for
Control Applications
•
Value 0 in CAPTMIN mode is captured only in down-counting mode.
33. ADC – Analog-to-Digital
Converter
•
33.6.5 Differential and Single-Ended Conversions: Corrected register
reference from INPUTCTRL.DIFFMODE to CTRLB.DIFFMODE.
33.8.14 RESULT: Corrected description. Reference to "single-ended mode"
corrected to "single conversion mode".
•
37. Electrical Characteristics at
85℃
•
•
•
© 2021 Microchip Technology Inc.
and its subsidiaries
37.3 Absolute Maximum Ratings: Add ESD warnings.
37.16.5 I2S Timing: fM_SCKO and fM_SCKI values for VDD=1.8V moved from
the minimum to maximum column.
XOSC32K 37.13.2.1.1 Crystal Oscillator Characteristics: Removed
conditions from the parasitic capacitor loads CXIN32 and CXOUT32. The
difference between package types is so small that it can be ingored.
Complete Datasheet
DS40001882H-page 1138
SAM D21/DA1 Family
Data Sheet Revision History
48.13
45. Schematic Checklist
•
45.5.3 External Real Time Oscillator: Added note on how to minimize jitter.
39. Electrical Characteristics at
125°C
•
39.4 Maximum Clock Frequencies: Corrected heading of Table 39-6 say
"Device Variant B".
Rev. K – 09/2016
3. SAM D21 Ordering
Information(1)
•
•
SAM D21E: Added Device Variant C ordering codes.
Device Identification: Added Device Variant C.
7. I/O Multiplexing and
Considerations
•
The section is reorgnaized:
– 7.2.3 SERCOM I2C Pins: Replaces the "Type" column in 7.1 Multiplexed
Signals.
– 7.2.4 GPIO Clusters: Moved from 37.3 Absolute Maximum Ratings.
– 7.2.5 TCC Configurations: Moved from the TCC 31.1 Overview.
16. PM – Power Manager
•
16.8.10 APBCMASK updated.
13. DSU - Device Service
Unit
•
13.11.6 System Services Availability when Accessed Externally and Device is
Protected: MBIST not available when device is operated from external address
range and device is protected.
19. RTC – Real-Time
Counter
•
19.6.3.3 Clock/Calendar (Mode 2): Example added on how the clock counter
works in calendar mode.
30. TC – Timer/Counter
•
30.8.1 CTRLA.WAVEGEN[1:0]: Name column updated.
31. TCC – Timer/Counter
for Control Applications
•
31.6.3.6 Non-Recoverable Faults: Removed references to Update Fault State
(UFS).
Removed the UFS bit from the INTENCLR, INTENSET, INTFLAG and STATUS
registers.
Removed RAMP2C from the 31.8.16 WAVE.WAVE[2:0]=0x3
•
•
37. Electrical
Characteristics at 85℃
•
•
37.3 Absolute Maximum Ratings: Updated VPIN minimum and maximum values.
(Related to the new Injection Current definition section)
37.5 Supply Characteristics: Corrected supply rise rates units from V/s to V/μs.
37.7 Power Consumption: Added power consumption numbers for Device
Variant C.
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics:
Added characterization data for Device Variant C.
Added 37.10 Injection Current section.
44. Packaging Information
•
Added 44.1.14 35 ball WLCSP (Device Variant C) package outline drawing.
Errata
•
Added errata for Device Variant C.
39. Electrical
Characteristics at 125°C
•
39.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics:
Added characterization data for Device Variant C.
39.2 Absolute Maximum Ratings: Updated VPIN minimum and maximum values.
(Related to the new Injection Current definition section)
•
•
•
•
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1139
SAM D21/DA1 Family
Data Sheet Revision History
48.14
Rev. J – 07/2016
3. SAM D21 Ordering
Information(1)
•
SAM D21E: Added ATSAMD21E15B-UUT.
30. TC – Timer/Counter
•
30.8.7 EVCTRL:EVACT[2:0] bit description updated: Time stamp capture
and pulse width capture removed
31. TCC – Timer/Counter for
Control Applications
•
•
31.6.3 Additional Features: Removed "Time-Stamp Capture" section.
31.8.9 EVCTRL:EVACT0[2:0] bit description updated: "Capture Overflow
times (Max value)" option removed (Related to Time-Stamp Capture).
Errata
•
Cleaned up errata section: Split between device variant A and B.
.
48.15
Rev. I – 03/2016
2. Configuration Summary
Updated value for Waveform output channels per TCC to 8/4/2.
7. I/O Multiplexing and Considerations
Added Note.6 for Table 7-1
10. Memories
Table 10-1: Updated start address in Internal RWW section to from 0x00010000 to 0x00400000.
22. Nonvolatile Memory Controller (NVMCTRL)
Updated value from "NVM Base Address + 0x00010000" to "NVM Base Address + 0x00400000"in
Figure 22-3
26. SERCOM USART
Updated equation and added error calculation explained w/example in section
26.6.2.6.4 Asynchronous Operational Range
31. TCC – Timer/Counter for Control Applications:
Register Summary: Remove INTENCLR.SYNCRDY. Add MC0 (located in bit 0) for INTENSET and
INTFLAG, and left shift MC1, MC2 and MC3 for one bit. Therefore, MC0/1/2/3 are located in bit
0/1/2/3.
37. Electrical Characteristics at 85℃
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1140
SAM D21/DA1 Family
Data Sheet Revision History
Updated unit from 's' to 'us' in the following tables:
•
•
•
•
•
•
•
•
•
•
•
•
Table 39-11
Table 39-12
Table 39-24
Table 39-25
Table 39-37
Table 39-38
Table 39-39
Table 39-40
Table 39-45
Table 39-46
Table 39-47
Table 39-48
Update value and condition for Table 39-39 and Table 39-40
44. Packaging Information
Updated section 44.1.11 32-Pin VQFN .
48.16
Rev. H – 01/2016
20. DMAC – Direct Memory Access Controller
Updated bit description of the PRICTRL0.LVLPRIn [n=3..0].
22. Nonvolatile Memory Controller (NVMCTRL)
Updated description in 22.6.4.3 NVM Write: Removed reference to default NWM CTRLB.MANW
default value.
Updated reset value for CTRLB.MANW from 0 to 1. Note that this change is only applicable for
Device Variant B. Device Variant A will continue to have MANW bit reset value 0.
Updated reset value of the CTRLB register from 0x00000000 to 0x00000080.
Note that this change is change is only applicable for Device Variant B. Device Variant A will
continue to have CTRLB register reset value 0x00000000.
13. DSU - Device Service Unit
Bit CTRL.CRC is write-only.
32. USB – Universal Serial Bus:
Register HSOFC.FLENCE description updated.
USB Device Registers - Common: Bit description of CTRLB .SPDCONF[1:0] updated.
44. Packaging Information
Updated values in 37.2.1 Thermal Resistance Data.
Corrected junction temperature equations: TC updated to TJ.
Updated package drawing for 44.1.13 35 ball WLCSP (Device Variant B): GPC corrected from GJP
to GJR. No other changes.
45. Schematic Checklist
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1141
SAM D21/DA1 Family
Data Sheet Revision History
Added 45.1.1 Operation in Noisy Environment.
Updated section 45.7 Programming and Debug Ports.
Updated recommended pin connection in 45.7.2 10-pin JTAGICE3 Compatible Serial Wire Debug
Interface: Pull-up resistor value on SWCLK pin changed from 10kΩ to 1kΩ.
VDDCORE decoupling capacitor value updated from 100nF to 1μF in 45.2.1 Power Supply
Connections
48.17
Rev. G – 09/2015
17. SYSCTRL – System Controller:
Updated description in 17.6.7.1.5 Drift Compensation.
37. Electrical Characteristics at 85℃:
Removed note from Table 37-53 and Table 37-54.
44. Packaging Information:
Package drawing updated 44.1.9 45-ball WLCSP.
39. Electrical Characteristics at 125°C:
Removed note from:Table 39-39 and Table 39-40.
Updated power consumption units in Table 39-7.
48.18
Rev. F – 07/2015
Ordering Information
Added ATSAMD21E15B-UUT and ATSAMD21E16B-UUT ordering codes (WLCSP35 package
option).
4. Block Diagram
Updated system block diagram.
5. Pinout
Added pinout figure for 5.6.1 WLCSP35.
9. Product Mapping
Updated Internal RWW section to start address from 0x00010000 to 0x00400000.
ADC - Analog-to-Digital Converter
References to AREFA and AREFB replaced with VREFA and VREFB respectively.
37. Electrical Characteristics at 85℃
Added GPIO cluster note to '37.3 Absolute Maximum Ratings.
Added 37.16.5 I2S Timing.
Updated BOD33 characteristics.
Added characterization data for Device Variant B.
Packaging Information
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1142
SAM D21/DA1 Family
Data Sheet Revision History
Updated ΘJC value from 3.1 to 15.0 °C/W for 32-pin QFN package in 37.2.1 Thermal Resistance
Data.
Added package drawing for 44.1.13 35 ball WLCSP (Device Variant B).
Schematic Checklist
45.2.1 Power Supply Connections:
VDDCORE decoupling capacitor value updated from 100nF to 1μF.
References to AREFA and AREFB replaced with VREFA and VREFB respectively.
Electrical Characteristics at 125C
Added I2S Timing.
Updated BOD33 characteristics.
Added characterization data for Device Variant B.
48.19
Rev. E – 02/2015
1. Description:
CoreMark score updated from 2.14 to 2.46 CoreMark/MHz.
3. SAM D21 Ordering Information(1):
Added Ordering codes for Device Variant B.
Added 125°C ordering codes for QFN and TQFP package options: SAMD21E, SAM D21E, SAM
D21G, and SAM D21J, and .
Added WLCSP package option for SAM D21G .
Added UFBGA package option for SAM D21J .
5. Pinout:
Added pinout figures for 5.1.2 UFBGA64 and 5.3.1 WLCSP45.
9. Product Mapping:
Updated Product Mapping figure with Internal RWW section block for Device Variant B.
10. Memories:
10.2 Physical Memory Map: Added start address for Internal Read While Write (RWW) section for
Device Variant B.
11. Processor And Architecture:
11.1.1 Cortex M0+ Configuration: Removed green connection dots between DMAC Data and AHBAPB Bridge A and Bridge B.
22. Nonvolatile Memory Controller (NVMCTRL):
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1143
SAM D21/DA1 Family
Data Sheet Revision History
Introducing Read While Write (RWW) feature for Device Variant B.
Updated and New sections:
22.1 Overview
22.2 Features
22.3 Block Diagram
22.6.4.1 NVM Read
22.6.4.2 RWWEE Read
22.6.4.3 NVM Write
22.6.4.5 Erase Row
22.6.2 Memory Organization: Figure 22-2 updated.
Register Summary and 22.8 Register Description: 22.8.3 PARAM: Added RWWEEP[12:0] bits for
Device Variant B.
23. PORT - I/O Pin Controller:
23.6.3 I/O Pin Configuration: Removed reference to “open-drain”.
Access for DRVSTR bit in Pin Configuration n register (PINCFGn.DRVCTR) updated from W to R/W.
17. SYSCTRL – System Controller:
Removed references to XOSC32K and OSC32 1kHz clock output option:
- XOSC32K: 17.6.3 32kHz External Crystal Oscillator (XOSC32K) Operation
- OSC32K: 17.6.4 32 kHz Internal Oscillator (OSC32K) Operation
1kHz Output Enable (EN1K) bit set as reserved bit:
- Bit 4 in 17.8.6 XOSC32K
- Bit 3 in 17.8.7 OSC32K
37. Electrical Characteristics at 85℃:
37.11.3 Brown-out Detectors Characteristics: Added Figure 37-3 and Figure 37-4 and updated
conditions in Table 37-21 and Table 37-23.
44. Packaging Information:
Added 44.1.5 64-ball UFBGA and 44.1.9 45-ball WLCSP package drawings.
45. Schematic Checklist
Updated description in 45.6 Unused or Unconnected Pins.
Errata:
Device Variant A:
- Updated errata for revision A: Added Errata Reference 12291, 13507, 13574.
- Updated errata for revision B: Added Errata Reference 12291, 13507, 13574.
- Updated errata for revision C: Added Errata Reference 12291, 13507, 13574, 13951.
- Added errata for revision D.
Device Variant B:
- Added errata for revision E (Only available for SAMD21x15/16).
39. Electrical Characteristics at 125°C:
Electrical characteristics for 125°C added.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1144
SAM D21/DA1 Family
Data Sheet Revision History
48.20
Rev. D – 09/2014
Block Diagram
NVM Controller bus connection changed from Master to Slave.
Clock System
Register Synchronization updated by splitting the section into Common synchronizer Register
Synchronization and Distributed Synchronizer Register Synchronization.
Electrical Characterstics
ADC
Characteristi
cs
: Added note defining gain accuracy parameter in:
- ADC Differential Mode, Differential Mode (Device Variant)
ADC Single-Ended Mode, Single-Ended Mode (Device Variant A)
Errata
Updated errata for revision A, B and C: Added Errata Reference 13140, 12860.
48.21
Rev. C – 07/2014
37. Electrical Characteristics at 85℃
Updated condition for Rise time for both SDA and SCL (tR) in High Speed Mode: Cb changed from
1000pF to 100pF in Table 37-16.
Errata
Errata for revision C and E added.
48.22
Rev. B – 07/2014
General:
Introduced the new product family name: Atmel | SMART
Removed references to Clock Failure Detection.
Sub sections within chapters might been moved to other location within the chapter.
Typo corrections.
2. Configuration Summary
Added 32KB Flash and 4KB SRAM options to SAM D21J and SAM D21G.
3. SAM D21 Ordering Information(1)
Added Tray to Carrier Type option for SAM D21E, SAMD 21G and SAMD21J ordering codes.
7. I/O Multiplexing and Considerations:
Updated REF function on PA03 and PA04 in Table 7-1:
PA03: DAC/VREFP changed to DAC/VREFA.
PA04: ADC VREFP changed to ADC/VREFB.
Updated COM function on PA30 and PA31:
PA30: CORTEX_M0P/SWCLK changed to SWCKL.
PA31: Added SWDIO.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1145
SAM D21/DA1 Family
Data Sheet Revision History
10. Memories
Added a second note to Table 10-3.
Added Figure 10-1 Calibration and Auxiliary Space.
Added default values for fuses in Table 10-7 NVM User Row Mapping.
11. Processor And Architecture
MTB renamed from “Memory Trace Buffer” to “Micro Trace Buffer”.
13. DSU - Device Service Unit
Updated description of 13.11.3.1 Starting CRC32 Calculation.
Updated title of Table 13-6.
Added Device Selection table to Device Selection bit description the Device Identification register (DID.DEVSEL).
15. GCLK - Generic Clock Controller
Signal names updated in Device Clocking Diagram, 15.3 Block Diagram.
16. PM – Power Manager
Added figure Figure 16-2.
Register Summary:
Removed CFD bit from INTENCLR, INTENSET and INTFLAG.
Added PTC bit to APBCMASK register.
Register Description:
AHB Mask register (AHBMASK): Full bit names updated.
APBC Mask register (APBCMASK.PTC): Added PTC to bit 19.
CFD bit removed from INTENCLR, INTENSET and INTFLAG.
17. SYSCTRL – System Controller
Updated description of 17.6.6 8MHz Internal Oscillator (OSC8M) Operation.
FDPLL96M section reorganized and more integrated in the SYSCTRL chapter: Features, Signal Description and
Product Dependencies sub sections removed and integrated with the corresponding sections in SYSCTRL.
Register Summary: Added VREG register on address 0x3C - 0x3D.
Register Description:
Updated reset values in OSC8M.
Updated CALIB[11:0] bit description in OSC8M.
Updated LBYPASS bit description in DPLLCTRLB.
18. WDT – Watchdog Timer
Updated description in 18.6.1 Principle of Operation: Introducing the bits used in Table 18-1.
Updated description in 18.6.2.1 Initialization.
Updated description in 18.6.2.4 Normal Mode.
Updated description in 18.6.2.5 Window Mode.
Updated description in 18.6.4 Interrupts.
WEN bit description in the Control register (CTRL.WEN) updated with information on enable-protection.
19. RTC – Real-Time Counter
© 2021 Microchip Technology Inc.
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Complete Datasheet
DS40001882H-page 1146
SAM D21/DA1 Family
Data Sheet Revision History
19.6.9.1 Periodic Events: Bit names updated fro, PERx to PEREOx in example, Figure 19-4.
CLOCK.HOUR[4:0]: Updated Table 19-4
Mode 0 and Mode 2: CMPx bit renamed to CMP0 since only one CMP0 is available.
Bit description of CLOCK.HOUR[4:0]: Updated Table 19-4
ALARMn register renamed to ALARM0.
20. DMAC – Direct Memory Access Controller
Updated block diagram, 20.3 Block Diagram.
General updated description.
21. EIC – External Interrupt Controller
Register Summary and Register Description:
EVCTRL register: Added bits EXTINTO17 and EXTINTO16 in bit position 17 and 16 respectively.
INTENCLR, INTENSET, INTENFLAG registers: Added bits EXTINT17 and EXTINT16 in bit position 17 and 16
respectively.
WAKEUP register: Added bits WAKEUPEN17 and WAKEUPEN16 in bit position 17 and 16 respectively.
CONFIG2 register added, CONFIG0 and CONFIG1 registers updated: Added bits FILTEN0...31 and SENSE0...31.
22. Nonvolatile Memory Controller (NVMCTRL)
CTRLB register: Removed table from NVM Read Wait States description (RWS[3:0])
23. PORT - I/O Pin Controller
Instances of the term “pad” replaced with “pin”.
Instances of the term “bundle” replaced with “group” and “interface”.
23.6.2 Basic Operation description updated.
Peripheral Multiplexing n (PMUX0) register: Offset formula updated.
24. EVSYS – Event System
Updated information in 24.2 Features.
24.5.2 Power Management updated: Description of on how event generators can generate an event when the
system clock is stopped moved to 24.6.4 Sleep Mode Operation.
24.5.3 Clocks updated: Renamed EVSYS channel dedicated generic clock from GCLK_EVSYS_x to
GCLK_EVSYS_CHANNELx.
Updated description in 24.6.1 Principle of Operation.
Updated description in sub sections of 24.6.2 Basic Operation.
Updated description in 24.6.3.1 The Overrun Channel n Interrupt.
Channel x Overrun bit description in 24.8.7 INTFLAG updated.
26. SERCOM USART
Updated description in 26.6.3.4 Break Character Detection and Auto-Baud.
Updated description in 26.6.3.7 Start-of-Frame Detection.
29. I2S - Inter-IC Sound Controller
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Complete Datasheet
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SAM D21/DA1 Family
Data Sheet Revision History
Introducing Frame Synch Clock.
29.4 Signal Description: Added separate tables for Master-, Slave- and Controller mode.
Updated description in 29.5.7 Debug Operation and 29.5.8 Register Access Protection.
Updated description in 29.6.1 Principle of Operation.
Updated description in sub sections of 29.6.2 Basic Operation.
Updated formula in 29.6.2.1.3 MCKn Clock Frequency.
Updated formulas in 29.6.2.1.5 Relation Between MCKn, SCKn, and Sampling Frequency fs.
Updated description in 29.6.6 PDM Reception.
Section on MONO removed and information included in 29.6.2 Basic Operation.
Updated property of Control A (CTRLA) register: Added Write-Synchronized
31. TCC – Timer/Counter for Control Applications
Updated description in 31.6.1 Principle of Operation.
Updated description in sub sections of 31.6.2 Basic Operation.
Updated description in sub sections of 31.6.3 Additional Features.
Updated description in 31.6.6 Synchronization.
Lock Update (LUPD) bit description updated in Control B Clear (CTRLBCLR) register.
Compare Channel Buffer x Busy (CCBx) bit description updated in Synchronization Busy (SYNCBUSY) register.
Event Control (EVCTRL) register property updated: Removed Enable-Protected.
Interrupt Enable Clear (INTENCLR), Interrupt Enable Set (INTENSET) and Interrupt Flag Status and Clear
(INTFLAG) registers: Updated bit description of FAULT0, FAULT1, FAULTA and FAULTB.
STATUS register bit descriptions updated.
Wave Control (WAVE) register property updated: Removed Read-Synchronized.
Pattern Buffer (PATTB) register: Updated property and bit description.
Waveform Control Buffer (WAVEB) register: Updated property and bit descriptions.
32. USB – Universal Serial Bus
Removed figures: Setup Transaction Overview, OUT Single Bank Transaction Overview, IN Single Bank
Transaction Overview and USB Host Communication Flow.
Updated description and graphics in sub sections of 32.6.2 USB Device Operations.
Updated description in sub sections of 32.6.3 Host Operations.
Pad Calibration (PADCAL) register: Access updated.
Upgraded bit descriptions.
Pipe Descriptor Structure: Updated register reset values.
33. ADC – Analog-to-Digital Converter
Register Description:
REFCTRL bit selection names updated from AREFA / AREFB to VREFA / VREFB in Table 33-5
35. DAC – Digital-to-Analog Converter
Updated block diagram and signal description: VREFP replaced with VREFB.
37. Electrical Characteristics at 85℃
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1148
SAM D21/DA1 Family
Data Sheet Revision History
Updated VDD max from 3.63V to 3.63V in 37.3 Absolute Maximum Ratings.
Updated VDDIN pin from 57 to 56 in 7.2.4 GPIO Clusters.
37.7 Power Consumption: Updated Max values for STANDBY from 190.6μA and 197.3μA to 100μA in Table 37-8.
Added 37.8 Peripheral Power Consumption.
37.9 I/O Pin Characteristics: tRISE and tFALL updated with different load conditions depending on the DVRSTR
value in .
37.9 I/O Pin Characteristics: Correct typo IOL and IOH Max values inverted between PORT.PINCFG.DRVSTR=0
and 1, tRISE and tFALL updated with different load conditions depending on the DVRSTR value in Table 37-15.
37.11 Analog Characteristics: Removed note from Table 37-19.
37.11.4 Analog-to-Digital (ADC) characteristics: Added Max DC supply current (IDD), RSAMPLE maximum value
changed from 2.8kW to 3.5kW, Conversion time Typ value change to Min Value in Table 37-24.
37.11.5 Digital to Analog Converter (DAC) Characteristics: Added Max DC supply current (IDD) in Table 37-32.
37.11.6 Analog Comparator Characteristics: Added Min and Max values for VSCALE INL, DNL, Offset Error and
Gain Error in Table 37-36.
37.11.7 Bandgap and Internal 1.0V Reference Characteristics: Added Min and Max values, removed accuracy row
in Table 37-38.
37.16.3 SERCOM in I2C Mode Timing: Add Typical values for tR in Table 37-68.
Removed Asynchronous Watchdog Clock Characterization.
37.13.4 32.768kHz Internal oscillator (OSC32K) Characteristics: Added Max current consumption (IOSC32K) in Table
37-55.
Updated Crystal Oscillator Characteristics (XOSC32K) ESR maximum values, 37.13.2.1.1 Crystal Oscillator
Characteristics.
Updated Crystal Oscillator Characteristics (XOSC) ESR maximum value, 37.13.1.2 Crystal Oscillator
Characteristics from 348kΩ to 141kΩ.
37.13.3 Digital Frequency Locked Loop (DFLL48M) Characteristics: Updated presentation, now separating
between Open- and Closed Loop Modes. Added fREF Min and Max values to Table 37-52.
Updated typical Startup time ( tSTARTUP) from 6.1µs to 8µs in Table 37-53.
Updated typical Fine lock time (tLFINE) from 700µs to 600µs in Table 37-53.
37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added Current consumption
(IFDPLL96M), Period Jitter (Jp), Lock time (tLOCK), Duty cycles parameters in Table 37-58.
Added 37.15 USB Characteristics.
37.16 Timing Characteristics: Added SCK period (tSCK) Typ value in Table 37-65.
Errata
Errata for revision B added.
48.23
Rev. A - 02/2014
Initial released version of this data sheet.
© 2021 Microchip Technology Inc.
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Complete Datasheet
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SAM D21/DA1 Family
The Microchip Web Site
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Technical support is available through the web site at: www.microchip.com/support
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SAM D21/DA1 Family
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
ATSAMD 21 E 15 A - M U T
Product Family
Package Carrier
SAMD = General Purpose Microcontroller
No character = Tray (Default)
T = Tape and Reel
Product Series
21 = Cortex M0 + CPU, Basic Feature Set
+ DMA + USB
Package Grade
Pin Count
U = -40 - 85°C Matte Sn Plating
N = -40 - 105°C Matte Sn Plating
F = -40 - 125°C Matte Sn Plating
Z = -40 - 125°C Matte Sn Plating
(AEC-Q100 Qualified)
E = 32 Pins (35 Pins for WLCSP)
G = 48 Pins (45 Pins for WLCSP)
J = 64 Pins
Flash Memory Density
Package Type
18 = 256 KB
17 = 128 KB
16 = 64 KB
15 = 32 KB
A = TQFP(4)
M = VQFN(4)
MM = 64-Lead VQFN (5LX)
U = WLCSP (2,3)
Device Variant
A = Default Variant
B = Added RWWEE support for 32 KB and 64 KB memory options
C = Silicon revision F for WLCSP45 package option
L = Pinout optimized for Analog and PWM
D = Silicon Revision G with RWWEE Support in 128KB memory options
C = UFBGA
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Microchip products meet the specification contained in their particular Microchip Data Sheet.
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There are dishonest and possibly illegal methods used to breach the code protection feature. All of
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you
may have a right to sue for relief under that Act.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS40001882H-page 1151
SAM D21/DA1 Family
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your
convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with
your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER
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INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR
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Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck,
LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower,
PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash,
tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT,
chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified
logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S.,
SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock,
Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2018, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-8898-9
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Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication
facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The
Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ®
code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
© 2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
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