HV2902GA-G

HV2802/HV2902 Low Harmonic Distortion, 32-Channel SPST, High-Voltage Analog Switch Features General Description • 32-Channel SPST (Single-Pole, Single-Throw) High-Voltage Analog Switch • 3.3V or 5.0V CMOS Input Logic Level • 20 MHz Data Shift Clock Frequency • High-Voltage CMOS (HVCMOS) Technology for High Performance • Very Low Quiescent Power Dissipation (10 µA) • Low Parasitic Capacitance • DC to 50 MHz Analog Signal Frequency • -60 dB Typical OFF-Isolation at 5.0 MHz • CMOS Logic Circuitry for Low Power • Excellent Noise Immunity • Cascadable Serial Data Register with Latches • Flexible Operating Supply Voltages • Integrated Bleed Resistors on the Outputs (HV2902 only) The HV2802 and HV2902 are low-charge injection, 32-channel, high-voltage analog switches intended for use in applications requiring high-voltage switching controlled by low-voltage control signals, such as medical ultrasound imaging, driving piezoelectric transducers and printers. The HV2902 has integrated bleed resistors which eliminate voltage build-up on capacitive loads such as piezoelectric transducers. Applications • Medical Ultrasound Imaging • Non-Destructive Testing (NDT) Metal Flaw Detection • Piezoelectric Transducer Drivers • Inkjet Printer Heads • Optical MEMS Modules Input data are shifted into a 32-bit shift register that can then be retained in a 32-bit latch. To reduce any possible clock feedthrough noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using the HVCMOS technology, this device combines high-voltage bilateral DMOS switches and low-power CMOS logic to provide efficient control of high-voltage analog signals. The device is suitable for various combinations of high-voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V and +160V/-40V. Package Type HV2802/HV2902 9x9x1.0 mm VFBGA* Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F G H J K L M N *See Section 2.0 “Package Pin Configurations and Functions Description”  2015 Microchip Technology Inc. DS20005449A-page 1 HV2802/HV2902 Block Diagram Latches Level Shifters Output Switches Bleed Resistors SW0A D LE CLR SW0B SW1A D LE CLR SW1B CLK SW2A D LE CLR 32-Bit Shift Register DIN SW2B DOUT SW30A D LE CLR SW30B SW31A D LE CLR SW31B VDD GND LE CLR VNN VPP RGND HV2902 only DS20005449A-page 2  2015 Microchip Technology Inc. HV2802/HV2902 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VDD Logic Supply Voltage .......................................................................................................................... -0.5V to +6.5V VPP-VNN Differential Supply ......................................................................................................................................220V VPP Positive Supply ...........................................................................................................................-0.5V to VNN +200V VNN Negative Supply ................................................................................................................................ +0.5V to -200V Logic Input Voltage..............................................................................................................................-0.5V to VDD +0.3V Analog Signal Range .......................................................................................................................................VNN to VPP Peak Analog Signal Current/Channel ........................................................................................................................3.0A Power Dissipation .................................................................................................................................................... 1.5W † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Note 1 — 3) Parameter Symbol Value VDD +3.0V to +5.5V Positive Voltage Supply VPP +40V to VNN+200V Negative Voltage Supply VNN -40V to -160V High-Level Input Voltage VIH 0.9VDD to VDD Low-Level Input Voltage VIL 0V to 0.1VDD VSIG VNN +10V to VPP -10V Logic Power Supply Voltage Analog Signal Voltage Peak-to-Peak Note 1: 2: 3: Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. VSIG must be VNN  V SIG  VPP or floating during power up/down transition. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0 ms.  2015 Microchip Technology Inc. DS20005449A-page 3 HV2802/HV2902 DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, VDD = 5.0V, VPP = +100V, VNN = -100V, Specification at 0°C and 70°C based on characterization and not 100% tested. 0°C Parameters +25°C +70°C Symbol Units Conditions Min. Max. Min. Typ. Max. Min. Max. Small Signal Switch ON-Resistance RONS  — 30 — 26 38 — 48 ISIG = 5.0 mA, VPP = +40V, VNN = -160V — 25 — 22 27 — 32 ISIG = 200 mA, VPP = +40V, VNN = -160V — 25 — 22 27 — 30 ISIG = 5.0 mA, VPP = +100V, VNN = -100V — 18 — 18 24 — 27 ISIG = 200 mA, VPP = +100V, VNN = -100V — 23 — 20 25 — 30 ISIG = 5.0 mA, VPP = +160V, VNN = -40V — 22 — 16 25 — 27 ISIG = 200 mA, VPP = +160V, VNN = -40V Small Signal Switch ON-Resistance Matching RONS — 20 — 5 20 — 20 % ISIG = 5.0 mA, VPP = +100V, VNN = -100V Large Signal Switch ON-Resistance (Note 1) RONL — — — 15 — — —  VSIG = VPP -10V, ISIG = 1A Value of Output Bleed Resistor RINT — — 20 35 50 — — k Output switch to RGND IRINT = 0.5 mA Switch off Leakage per Switch ISOL — 5 — 1 10 — 15 µA VSIG = VPP -10V, VNN +10V Switch DC Offset VOS — 300 — 100 300 — 300 mV Switch OFF, RLOAD = 100 kfor HV2802 No load for HV2902 — 500 — 100 500 — 500 Quiescent VPP Supply Current IPPQ — — — 10 50 — — Quiescent VNN Supply Current INNQ — — — 10 50 — — Quiescent VPP Supply Current IPPQ — — — 10 50 — — Quiescent VNN Supply Current INNQ — — — 10 50 — — Switch Output Peak Current (Note 1) ISW — — 2 3 — — Output Switching Frequency (Note 1) fSW — — — — 50 — Note 1: 2: Switch ON RLOAD = 100 kfor HV2802 No load for HV2902 µA All switches off µA All switches on, ISW = 5.0 mA — A VSIG duty cycle < 0.1% — kHz Duty cycle = 50% Specification is obtained by characterization and is not 100% tested. Design guidance only. DS20005449A-page 4  2015 Microchip Technology Inc. HV2802/HV2902 DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, VDD = 5.0V, VPP = +100V, VNN = -100V, Specification at 0°C and 70°C based on characterization and not 100% tested. 0°C Parameters +25°C +70°C Symbol Units Conditions mA VPP = +40V, VNN = -160V All output switches are turning on and off at 50 kHz with no load Min. Max. Min. Typ. Max. Min. Max. Average VPP Supply Current — 14 — — 14 — 14 — 14 — — 14 — 14 VPP = +100V, VNN = -100V All output switches are turning on and off at 50 kHz with no load — 14 — — 14 — 14 VPP = +160V, VNN = -40V All output switches are turning on and off at 50 kHz with no load — 14 — — 14 — 14 — 14 — — 14 — 14 VPP = +100V, VNN = -100V All output switches are turning on and off at 50 kHz with no load — 14 — — 14 — 14 VPP = +160V, VNN = -40V All output switches are turning on and off at 50 kHz with no load IDD — 8 — — 8 — 8 mA fCLK = 5.0 MHz, VDD = 5.0V Quiescent VDD Supply Current IDDQ — 10 — — 10 — 10 µA All logic inputs are static Data Out Source Current ISOR 0.45 — 0.45 0.70 — 0.40 — mA VOUT = VDD -0.7V Data Out Sink Current ISINK 0.45 — 0.45 0.70 — 0.40 — mA VOUT = 0.7V Logic Input Capacitance (Note 2) CIN — 10 10 — 10 pF Average VNN Supply Current Average VDD Supply Current Note 1: 2: IPP INN — — mA VPP = +40V, VNN = -160V All output switches are turning on and off at 50 kHz with no load Specification is obtained by characterization and is not 100% tested. Design guidance only.  2015 Microchip Technology Inc. DS20005449A-page 5 HV2802/HV2902 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, VDD = 5.0V, VPP = +100V, VNN = -100V, Specification at 0°C and 70°C based on characterization and not 100% tested. Parameters 0°C +25°C +70°C Symbol Units Conditions Min. Max. Min. Typ. Max. Min. Max. Set Up Time Before LE Rises (Note 1) tSD 25 — 25 — — 25 — ns Time Width of LE (Note 1) tWLE 56 — 56 — — 56 — ns VDD = 3.0V 12 — 12 — — 12 — Clock Delay Time to Data Out (Note 1) tDO 8 40 8 19 40 8 40 ns VDD = 3.0V 8 30 8 15 30 8 30 Time Width of CLR (Note 1) tWCLR 55 — 55 — — 55 — ns Set Up Time Data to Clock (Note 1) tSU 21 — 21 — — 21 — ns 7 — 7 — — 7 — Hold Time Data from Clock (Note 1) tH Clock Frequency Clock Rise and Fall Times Turn ON Time VDD = 5.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V 5 — 5 — — 5 — 7 — 7 — — 7 — VDD = 5.0V — 8 — — 8 — 8 MHz VDD = 3.0V — 20 — — 20 — 20 VDD = 5.0V tR, tF — 50 — — 50 — 50 ns tON — 5 — — 5 — 5 µs fCLK ns VDD = 3.0V Turn OFF Time tOFF — 5 — — 5 — 5 VSIG = VPP -10V, RLOAD = 10 k Maximum VSIG Slew Rate (Note 1) dv/dt — — — — 20 — — V/ns VPP = +40V, VNN = -160V — — — — 20 — — VPP = +100V, VNN = -100V — — — — 20 — — VPP = +160V, VNN = -40V — — — -33 -30 — — — — — -60 -58 — — KCR — — — -70 -60 — — dB f = 5.0 MHz, 50 load Output Switch Isolation Diode Current (Note 1) IID — — — — 300 — — mA 300 ns pulse width, 2.0% duty cycle Off Capacitance SW to GND (Note 1) CSG(OFF) — — — 10 15 — — pF 0V, f = 1.0 MHz On Capacitance SW to GND (Note 1) CSG(ON) — — — 13 18 — — Output Voltage Spike SWA, SWB (Note 1) +VSPK — — — — +150 — — mV VPP = +40V, VNN = -160V RLOAD = 50 OFF Isolation (Note 1) Switch Crosstalk (Note 1) Charge Injection (per switch) (Note 1) Note 1: KO -VSPK — — -150 — — — — +VSPK — — — — +150 — — -VSPK — — -150 — — — — +VSPK — — — — +150 — — dB f = 5.0 MHz, 1.0 k ǁ 15 pF load f = 5.0 MHz, 50 load VPP = +100V, VNN = -100V RLOAD = 50 VPP = +160V, VNN = -40V RLOAD = 50 -VSPK — — -150 — — — — QC — — — 820 — — — — — — 600 — — — VPP = +100V, VNN = -100V — — — 350 — — — VPP = +160V, VNN = -40V pC VPP = +40V, VNN = -160V Specification is obtained by characterization and is not 100% tested. DS20005449A-page 6  2015 Microchip Technology Inc. HV2802/HV2902 TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Operating Temperature TA 0 — +70 °C Storage Temperature TA -65 — +150 °C JA — 32.2 — °C/W Conditions Temperature Ranges Package Thermal Resistance Thermal Resistance, 78-Ball VFBGA  2015 Microchip Technology Inc. DS20005449A-page 7 HV2802/HV2902 1.1 Logic Timing and Truth Table DN DN+1 DATA IN DN-1 50% 50% 50% LE 50% tWLE tSD 50% CLOCK tSU 50% th tDO DATA OUT 50% tON tOFF OFF VOUT (typical) 10% ON 50% CLR FIGURE 1-1: TABLE 1-1: D0 D1 L 10% 50% tWCL Logic Timing Waveforms. TRUTH TABLE (Notes 1 — 6) D15 D16 — — H — — L — — — — — — — L L — — — L — — L L — — — H — — L L — — — — — L — L L — — — — — H — L L — — — — — — L L — — — — — — L L — — — — — L L — — — — — L L — — — — — — — — — L L L — — — — OFF — — — — H L L — — — — ON X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF Legend: Note 1: 2: 3: 4: 5: 6: ••• D31 LE CLR SW0 SW1 — — L L OFF — — — — — — — L L ON — — — — — — — L L — OFF — — — H — — — L L — ON — — — — — — — L L — — — — — — — — — — OFF — — ••• ••• ••• ••• SW15 SW16 ••• SW31 ON — — OFF — — ON — — — — — — — — — — — — — — — ••• ••• — — X = Do not care; L = Low; H = High. The 32 switches operate independently. Serial data is clocked in on the L to H transition of the CLK. All 32 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the shift register’s data flow through the latch. DOUT is high when data in register 31 is high. Shift register’s clocking has no effect on the switch states if LE is high. The CLR clear input overrides all other inputs. DS20005449A-page 8  2015 Microchip Technology Inc. HV2802/HV2902 2.0 PACKAGE PIN CONFIGURATIONS AND FUNCTIONS DESCRIPTION This section details the pin designation for the 78-Ball VFBGA package (Figure 2-1). The descriptions of the pins are listed in Table 2-1. 1 2 3 A SW2B B SW3A SW2A C SW4A D SW1B 4 5 6 7 SW0B DOUT GND VDD LE SW1A SW0A DIN CLK NC 8 9 CLR 10 11 SW31A SW30A SW31B SW30B 12 13 SW29B SW28B SW29A SW3B SW27B SW28A SW5A SW4B SW26B SW27A E SW6A SW5B SW25B SW26A F SW7A SW6B SW24B SW25A G SW8A SW7B SW23B SW24A H SW9A SW8B SW22B SW23A J SW10A SW9B SW21B SW22A K SW11A SW10B SW20B SW21A L SW12A SW11B SW19B SW20A M SW13A SW12B SW18A SW19A N SW13B VNN VNN SW18B VPP Note: FIGURE 2-1: NC RGND RGND SW14A SW15A SW16A SW17A SW14B SW15B SW16B SW17B NC RGND VPP On pins B6, M10 and N5 the NC pin is available for HV2802 only, while RGND pin is available for HV2902. 78-Ball VFBGA Package - Top View.  2015 Microchip Technology Inc. DS20005449A-page 9 HV2802/HV2902 TABLE 2-1: PIN FUNCTION TABLE Symbol Pin Number Description 9x9x1.0 VFBGA HV2802 HV2902 A1 SW2B SW2B Analog switch 2 terminal B A3 SW1B SW1B Analog switch 1 terminal B A4 SW0B SW0B Analog switch 0 terminal B A5 DOUT DOUT Data out logic output A6 GND GND Ground A7 VDD VDD Logic supply voltage A8 LE LE Latch enable logic input, low active A10 SW31A SW31A Analog switch 31 terminal A A11 SW30A SW30A Analog switch 30 terminal A A13 SW29B SW29B Analog switch 29 terminal B B1 SW3A SW3A Analog switch 3 terminal A B2 SW2A SW2A Analog switch 2 terminal A B4 SW1A SW1A Analog switch 1 terminal A B5 SW0A SW0A Analog switch 0 terminal A B6 NC RGND No connect / Ground for bleed resistor B7 DIN DIN Data in logic input B8 CLK CLK Clock logic input for shift register B9 CLR CLR B10 SW31B SW31B Analog switch 31 terminal B Latch clear logic input B11 SW30B SW30B Analog switch 30 terminal B B12 SW28B SW28B Analog switch 28 terminal B B13 SW29A SW29A Analog switch 29 terminal A C1 SW4A SW4A Analog switch 4 terminal A C2 SW3B SW3B Analog switch 3 terminal B C12 SW27B SW27B Analog switch 27 terminal B C13 SW28A SW28A Analog switch 28 terminal A D1 SW5A SW5A Analog switch 5 terminal A D2 SW4B SW4B Analog switch 4 terminal B D12 SW26B SW26B Analog switch 26 terminal B D13 SW27A SW27A Analog switch 27 terminal A E1 SW6A SW6A Analog switch 6 terminal A E2 SW5B SW5B Analog switch 5 terminal B E12 SW25B SW25B Analog switch 25 terminal B E13 SW26A SW26A Analog switch 26 terminal A F1 SW7A SW7A Analog switch 7 terminal A F2 SW6B SW6B Analog switch 6 terminal B F12 SW24B SW24B Analog switch 24 terminal B F13 SW25A SW25A Analog switch 25 terminal A G1 SW8A SW8A Analog switch 8 terminal A G2 SW7B SW7B Analog switch 7 terminal B G12 SW23B SW23B Analog switch 23 terminal B G13 SW24A SW24A Analog switch 24 terminal A DS20005449A-page 10  2015 Microchip Technology Inc. HV2802/HV2902 TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Symbol Pin Number H1 Description 9x9x1.0 VFBGA HV2802 HV2902 SW9A SW9A Analog switch 9 terminal A H2 SW8B SW8B Analog switch 8 terminal B H12 SW22B SW22B Analog switch 22 terminal B H13 SW23A SW23A Analog switch 23 terminal A J1 SW10A SW10A Analog switch 10 terminal A J2 SW9B SW9B Analog switch 9 terminal B J12 SW21B SW21B Analog switch 21 terminal B J13 SW22A SW22A Analog switch 22 terminal A K1 SW11A SW11A Analog switch 11 terminal A K2 SW10B SW10B Analog switch 10 terminal B K12 SW20B SW20B Analog switch 20 terminal B K13 SW21A SW21A Analog switch 21 terminal A L1 SW12A SW12A Analog switch 12 terminal A L2 SW11B SW11B Analog switch 11 terminal B L12 SW19B SW19B Analog switch 19 terminal B L13 SW20A SW20A Analog switch 20 terminal A M1 SW13A SW13A Analog switch 13 terminal A M2 SW12B SW12B Analog switch 12 terminal B M6 SW14A SW14A Analog switch 14 terminal A M7 SW15A SW15A Analog switch 15 terminal A M8 SW16A SW16A Analog switch 16 terminal A M9 SW17A SW17A Analog switch 17 terminal A M10 NC RGND No connect/Ground for bleed resistor M12 SW18A SW18A Analog switch 18 terminal A M13 SW19A SW19A Analog switch 19 terminal A N1 SW13B SW13B Analog switch 13 terminal B N2 VNN VNN Negative supply voltage N4 VPP VPP Positive supply voltage N5 NC RGND No connect/Ground for bleed resistor N6 SW14B SW14B Analog switch 14 terminal B N7 SW15B SW15B Analog switch 15 terminal B N8 SW16B SW16B Analog switch 16 terminal B N9 SW17B SW17B Analog switch 17 terminal B N10 VPP VPP Positive supply voltage N12 VNN VNN Negative supply voltage N13 SW18B SW18B  2015 Microchip Technology Inc. Analog switch 18 terminal B DS20005449A-page 11 HV2802/HV2902 3.0 TEST CIRCUIT EXAMPLES This section details test circuit examples for a few electrical characteristics. The RGND pins are found only on the HV2902 device. The Switch DC Offset of HV2802 needs 100 k external load. VIN = 10VP-P @5 MHz ISOL VPP-10V VOUT RLOAD Open RGND* RGND* VPP VPP VDD VNN VNN GND Open 5.0V VPP VPP VDD VNN VNN GND 5.0V V OUT K o = 20Log ---------------V IN FIGURE 3-1: Switch Off Leakage per Switch. FIGURE 3-4: Off Isolation. VSIG VOUT IID RLOAD 100k (HV2802 only) VNN VPP VPP VDD VNN VNN GND FIGURE 3-2: RGND* RGND* 5.0V VPP VPP VDD VNN VNN GND FIGURE 3-5: Diode Current. Switch DC Offset. 5.0V Output Switch Isolation VIN = 10VP-P @5 MHz VPP-10V VOUT RLOAD 10k VOUT NC 50 50 RGND* RGND* VPP VPP VDD VNN VNN GND FIGURE 3-3: DS20005449A-page 12 5.0V TON/TOFF Test Circuit. VPP VPP VDD VNN VNN GND 5.0V V OUT K CR = 20Log ---------------V IN FIGURE 3-6: Switch Crosstalk.  2015 Microchip Technology Inc. HV2802/HV2902 VOUT VOUT 1000pF VSIG RGND* VPP VPP VDD VNN VNN GND Q = 1000pF   V FIGURE 3-7: 5.0V OUT Charge Injection. +VSPK VOUT -VSPK RLOAD 50 RGND* 1k VPP VPP VDD VNN VNN GND FIGURE 3-8: 5.0V Output Voltage Spike.  2015 Microchip Technology Inc. DS20005449A-page 13 HV2802/HV2902 4.0 Figure 4-1 shows a typical medical ultrasound image system comprising 64-channels of transmit pulsers, 64-channels of receivers (LNA and ADC) and 64-channels of T/R switches connecting to 192 elements of an ultrasound transducer probe via a high-voltage analog switch array. DETAILED DESCRIPTION AND APPLICATION INFORMATION The high-voltage analog switches are used for multiplexing a piezoelectric transducer array in a probe to multiple channel transmitters (Tx) arrays in a medical ultrasound system. Tx / Rx Array HV 2XXX SW Array PZT Array Tx CH1 T/R Switch Rx ADC E1 Tx E65 CH2 E129 T/R Switch ADC Rx E2 E66 E130 Tx CH64 T/R Switch ADC Rx E64 E128 E192 FPGA Ctrl Logic VIDEO FIGURE 4-1: CPU MEMORY Typical Medical Ultrasound Imaging System. The HV2802/HV2902 devices are comprised of two main circuitries: • A low-power CMOS digital serial interface powered by VDD to control the high-voltage analog switches • High-voltage bilateral analog switch. High-voltage supplies VPP and VNN are needed by the high-voltage level translation circuitry to control the states of the output high-voltage analog switches. In addition, each high-voltage analog switch can be independently controlled because each switch is controlled via a corresponding latch. A 32-bit shift register and 32 latches allow the user to serially load data into the registers, and after completion, to load the data onto the latches that control the states of the high-voltage analog switches. The data is shifted into the shift registers on the rising edge (low-to-high transition) of the clock. The switch configuration bit of SW31 is shifted in first and the switch configuration bit of SW0 is shifted in last. To avoid clock feedthrough, the latch enable input (LE) should remain high while the 32-bit data-in signal is shifted into the 32-bit register. After the valid 32-bit data complete shifting into the shift registers, the high-to-low transition of the LE signal transfers the contents of the shift register into the latches. Finally, setting the LE high again allows all the latches to keep the current state, while new data can now be shifted into the shift registers without upsetting the latches. It is recommended to change all the latch states at the same time through this method to avoid possible clock feedthrough noise. See Figure 4-2 for details. The HV2802/HV2902 have a digital serial interface consisting of logic signals, Data In (DIN), Clock (CLK), Data Out (DOUT), Latch Enable (LE) and Clear (CLR). The digital circuits are supplied by VDD and either a 3.3V or a 5V logic can be used. With a VDD = 5V supply, the serial clock frequency can operate up to 20 MHz. DS20005449A-page 14  2015 Microchip Technology Inc. HV2802/HV2902 tWLE LE tSD CLK tSU tH DN31 DIN DN30 DN29 D N1 DN0 tDO DOUT DN-131 DN-130 DN-129 DN-11 DN-10 DN31 *The previous data input in the shift register are shifted out FIGURE 4-2: Latch Enable Timing Waveforms. When the CLR input is set high, all 32 latches are cleared of the data. Consequently, all the high-voltage switches are set to off state. However, the CLR signal does not affect the contents of the shift register, so the shift register can operate independently of the CLR signal. Hence, after the CLR input is set low, the shift register would still retain the previous data. The serial input interface of the HV2802/HV2902 allows multiple devices to daisy-chain together. In this configuration, DOUT of a HV2802/HV2902 device is connected to the DIN of the subsequent device, and so forth. The last DOUT of the daisy-chained HV2802/HV2902 can either be floating or fed back to an FPGA to check the previously stored shift register data. To control all the high-voltage analog switch states in daisy-chained N devices, N times 32 clocks and N times 32 bits of data are shifted into shift registers, while LE remains high and CLR remains low. After all N times 32 bits of data finish shifting in, the high-to-low transition of the LE transfers the data from all N times 32-bit shift registers to N times 32 latches simultaneously. Consequently, all N times 32 high-voltage analog switches change states simultaneously. The HV2802/HV2902 devices do not have a specific power up/down sequence. During the power up/down period, all the analog switch inputs should be within the VPP and VNN range or floating. The rise time and fall time of the power supplies, VDD, VPP and VNN, should be greater than 1 ms. Violating the rise time or fall time requirement on the power supplies may cause malfunction such as latch-up or even permanent damage of the device. The HV2902 device has 35 k integrated bleed resisters connected from all the analog switch terminals A and B to RGND. These bleed resisters eliminate voltage build-up on capacitive loads such as piezoelectric transducers. The HV2802 device does not have integrated bleed resistors. It is recommended that 0.1 uF ceramic decoupling capacitors, with the appropriate voltage ratings, be connected between GND and the other supplies (VDD, VPP and VNN). These decoupling capacitors should be placed as close as possible to the device.  2015 Microchip Technology Inc. DS20005449A-page 15 HV2802/HV2902 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 78-Ball VFBGA (9x9x1.0) Example HV2802GA 1520256 Legend: XX...X Y YY WW NNN * Note: DS20005449A-page 16 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( can be found on the outer packaging for this package. ) In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2015 Microchip Technology Inc. HV2802/HV2902 78-Ball Very Thin Fine Pitch Ball Grid Array (5G) - 9x9x1.0 mm Body [VFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A D/4 B E/4 E 0.10 C 2X 0.10 C TOP VIEW A3 A SEATING PLANE C SIDE VIEW SEE DETAIL B D1 e E1 DETAIL A BOTTOM VIEW Microchip Technology Drawing C04-371A Sheet 1 of 2  2015 Microchip Technology Inc. DS20005449A-page 17 HV2802/HV2902 78-Ball Very Thin Fine Pitch Ball Grid Array (5G) - 9x9x1.0 mm Body [VFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging NX Øb Ø0.15 Ø0.05 C A B C SOLDER BALL DETAIL A 0.10 C 0.08 C C A1 DETAIL A Units Dimension Limits N Number of Pins e Pitch A Overall Height Standoff A1 A3 Molded Cap Thickness E Overall Width Overall Ball Pitch E1 D Overall Length D1 Overall Ball Pitch Øb Ball Diameter MIN 0.15 0.45 0.25 MILLIMETERS NOM 78 0.65 BSC 0.20 0.50 9.00 BSC 7.80 BSC 9.00 BSC 7.80 BSC 0.30 MAX 1.00 0.25 0.55 0.35 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-371A Sheet 2 of 2 DS20005449A-page 18  2015 Microchip Technology Inc. HV2802/HV2902 78-Ball Very Thin Fine Pitch Ball Grid Array (5G) - 9x9x1.0 mm Body [VFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 ØX C2 E1 E2 RECOMMENDED LAND PATTERN Units Dimension Limits E1 Contact Pitch Contact Pitch E2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Diameter (X78) X MIN MILLIMETERS NOM 0.65 BSC 0.65 BSC 780 7.80 0.25 MAX Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2371A  2015 Microchip Technology Inc. DS20005449A-page 19 HV2802/HV2902 NOTES: DS20005449A-page 20  2015 Microchip Technology Inc. HV2802/HV2902 APPENDIX A: REVISION HISTORY Revision A (October 2015) • Original release of this document.  2015 Microchip Technology Inc. DS20005449A-page 21 HV2802/HV2902 NOTES: DS20005449A-page 22  2015 Microchip Technology Inc. HV2802/HV2902 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX-X Device Package Examples: a) b) Device HV2802: 32-Channel SPST, High-Voltage Analog Switch HV2902: 32-Channel SPST, High-Voltage Analog Switch with Bleed Resistors Package GA-G = HV2802GA-G: HV2902GA-G: 78-Ball VFBGA package 78-Ball VFBGA package Very Thin Fine Pitch Ball Grid Array (5G) 9x9x1.0 mm (VFBGA), 78-Ball  2015 Microchip Technology Inc. DS20005449A-page 23 HV2802/HV2902 NOTES: DS20005449A-page 24  2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-907-6 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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