PIC24FJ128GA310 FAMILY
64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers
with LCD Controller and XLP Technology
Extreme Low-Power Features:
Peripheral Features (Continued):
• Multiple Power Management Options for Extreme
Power Reduction:
- VBAT allows the device to transition to a backup
battery for the lowest power consumption with
RTCC
- Deep Sleep allows near total power-down with the
ability to wake-up on external triggers
- Sleep and Idle modes selectively shut down
peripherals and/or core for substantial power
reduction and fast wake-up
- Doze mode allows CPU to run at a lower clock
speed than peripherals
• Alternate Clock modes Allow On-the-Fly Switching to
a Lower Clock Speed for Selective Power Reduction
• Extreme Low-Power Current Consumption for
Deep Sleep:
- WDT: 270 nA @ 3.3V typical
- RTCC: 400 nA @ 32 kHz, 3.3V typical
- Deep Sleep current, 40 na, 3.3V typical
• Seven Input Capture modules, each with a
Dedicated 16-Bit Timer
• Seven Output Compare/PWM modules, each with a
Dedicated 16-Bit Timer
• Enhanced Parallel Master/Slave Port (EPMP/EPSP)
• Hardware Real-Time Clock/Calendar (RTCC):
- Runs in Deep Sleep and VBAT modes
• Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer
• Two I2C™ modules Support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing
• Four UART modules:
- Support RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA®
- Auto-wake-up on Auto-Baud Detect
- 4-level deep FIFO buffer
• Programmable 32-Bit Cyclic Redundancy Check
(CRC) Generator
• Digital Signal Modulator Provides On-Chip FSK and
PSK Modulation for a Digital Signal Stream
• Configurable Open-Drain Outputs on Digital I/O Pins
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
Peripheral Features:
• LCD Display Controller:
- Up to 60 segments by 8 commons
- Internal charge pump and low-power, internal
resistor biasing
- Operation in Sleep mode
• Up to Five External Interrupt Sources
• Peripheral Pin Select (PPS): Allows Independent I/O
Mapping of Many Peripherals
• Five 16-Bit Timers/Counters with Prescaler:
- Can be paired as 32-bit timers/counters
• Six-Channel DMA supports All Peripheral modules:
- Minimizes CPU overhead and increases data
throughput
Analog Features:
Pins
Flash
Program
(bytes)
Data SRAM
(bytes)
16-Bit Timers
Capture Input
Compare/PWM
Output
UART w/IrDA®
SPI
I2C™
10/12-Bit ADC
(ch)
Comparators
CTMU (ch)
EPMP/EPSP
LCD (pixels)
JTAG
Deep Sleep w/VBAT
• 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter:
- Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit)
- Conversion available during Sleep and Idle
• Three Rail-to-Rail Enhanced Analog Comparators
with Programmable Input/Output Configuration
• On-Chip Programmable Voltage Reference
• Charge Time Measurement Unit (CTMU):
- Used for capacitive touch sensing, up to 24 channels
- Time measurement down to 1 ns resolution
- CTMU temperature sensing
PIC24FJ128GA310
100
128K
8K
5
7
7
4
2
2
24
3
24
Y
480
Y
Y
PIC24FJ128GA308
80
128K
8K
5
7
7
4
2
2
16
3
16
Y
368
Y
Y
PIC24FJ128GA306
64
128K
8K
5
7
7
4
2
2
16
3
16
Y
240
Y
Y
PIC24FJ64GA310
100
64K
8K
5
7
7
4
2
2
24
3
24
Y
480
Y
Y
PIC24FJ64GA308
80
64K
8K
5
7
7
4
2
2
16
3
16
Y
368
Y
Y
PIC24FJ64GA306
64
64K
8K
5
7
7
4
2
2
16
3
16
Y
240
Y
Y
Memory
Device
2010-2014 Microchip Technology Inc.
Remappable Peripherals
DS30009996G-page 1
PIC24FJ128GA310 FAMILY
High-Performance CPU:
Special Microcontroller Features:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator:
- 4x PLL option
- Multiple clock divide options
- Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units for Separate Read
and Write Addressing of Data Memory
• Operating Voltage Range of 2.0V to 3.6V
• Two On-Chip Voltage Regulators (1.8V and 1.2V) for
Regular and Extreme Low-Power Operation
• 20,000 Erase/Write Cycle Endurance Flash Program
Memory, Typical
• Flash Data Retention: 20 Years Minimum
• Self-Programmable under Software Control
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins
• JTAG Boundary Scan Support
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR) with Operation Below VBOR
• High/Low-Voltage Detect (HLVD)
• Flexible Watchdog Timer (WDT) with its Own
RC Oscillator for Reliable Operation
• Standard and Ultra Low-Power Watchdog Timers
(ULPW) for Reliable Operation in Standard and
Deep Sleep modes
DS30009996G-page 2
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Pin Diagrams
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
HLVDIN/CTED8/PMD4/CN62/RE4
COM0/CTED9/PMD3/CN61/RE3
COM1/PMD2/CN60/RE2
COM2/PMD1/CN59/RE1
COM3/PMD0/CN58/RE0
COM4/SEG48/CN69/RF1
SEG27/CN68/RF0
VBAT
VCAP/VDDCORE
C3INA/SEG26/CN16/RD7
C3INB/SEG25/CN15/RD6
RP20/SEG24/PMRD/CN14/RD5
RP25/SEG23/PMWR/CN13/RD4
RP22/SEG22/PMBE0/CN52/RD3
RP23/SEG21/PMACK1/CN51/RD2
RP24/SEG20/CN50/RD1
64-Pin TQFP, QFN(1)
PMD5/CTED4/LCDBIAS2/CN63/RE5
PMD6/LCDBIAS1/CN64/RE6
PMD7/LCDBIAS0/CN65/RE7
C1IND/RP21/SEG0/PMA5/CN8/RG6
VLCAP1/C1INC/RP26/PMA4/CN9/RG7
VLCAP2/C2IND/RP19/PMA3/CN10/RG8
MCLR
C2INC/RP27/SEG1/PMA2/CN11/RG9
VSS
VDD
2
3
4
5
6
7
8
9
10
11
12
PIC24FJXXXGA306
13
14
15
16
43
42
41
40
39
38
37
36
35
34
33
SOSCO/RPI37/SCKLI/RC14
SOSCI/RC13
RP11/SEG17/CN49/RD0
RP12/C3INC/SEG16/PMA14/CS1/CN56/RD11
RP3/SEG15/PMA15/C3IND/CS2/CN55/RD10
RP4/SEG14/PMACK2/CN54/RD9
RP2/SEG13/RTCC/CN53/RD8
VSS
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
VDD
SEG28/CN72/SCL1/RG2
SEG47/CN73/SDA1/RG3
INT0/CN84/RF6
RP30/CN70/RF2
RP16/SEG12/CN71/RF3
TCK/AN12/CTED2/PMA11/SEG18/CN30/RB12
TDI/AN13/SEG19/CTED1/PMA10/CN31/RB13
AN14/RP14/SEG8/CTED5/CTPLS/PMA1/CN32/RB14
AN15/RP29/SEG9/CTED6/REFO/PMA0/CN12/RB15
RP10/SDA2/SEG10/PMA9/CN17/RF4
PMA8/RP17/SCL2/SEG11/CN18/RF5
PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6
PGED2/AN7/RP7/CN25/RB7
AVDD
AVSS
AN8/RP8/SEG31/COM7/CN26/RB8
AN9/RP9/SEG30/COM6/PMA7/CN27/RB9
TMS/CVREF/AN10/SEG29/COM5/PMA13/CN28/RB10
TDO/AN11/PMA12/CN29/RB11
VSS
VDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
AN3/C2INA/SEG4/CN5/RB3
AN2/C2INB/CTCMP/CTED13/RP13/SEG5/CN4/RB2
PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1
PGED1/CVREF+/AN0/RP0/SEG7/PMA6/CN2/RB0
48
47
46
45
44
1
Legend: RPn and RPIn represent remappable pins for the Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Note 1: Refer to Table 4-22 for the list of analog ports.
2010-2014 Microchip Technology Inc.
DS30009996G-page 3
PIC24FJ128GA310 FAMILY
Pin Diagrams (Continued)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
HLVDIN/CTED8/PMD4/CN62/RE4
CTED9/COM0/PMD3/CN61/RE3
COM1/PMD2/CN60/RE2
COM2/PMD1/CN59/RE1
COM3/PMD0/CN58/RE0
SEG50/PMD8/CN77/RG0
SEG46/PMD9/CN78/RG1
COM4/SEG48/PMD10/CN69/RF1
SEG27/PMD11/CN68/RF0
VBAT
VCAP/VDDCORE
C3INA/SEG26/PMD15/CN16/RD7
C3INB/SEG25/PMD14/CN15/RD6
RP20/SEG24/PMRD/CN14/RD5
RP25/SEG23/PMWR/CN13/RD4
SEG45/PMD13/CN19/RD13
RPI42/SEG44/PMD12/CN57/RD12
RP22/SEG22/PMBE0/CN52/RD3
RP23/SEG21/PMACK1/CN51/RD2
RP24/SEG20/CN50/RD1
80-Pin TQFP(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC24FJXXXGA308
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RPI37/SOSCO/SCKLI/RC14
SOSCI/RC13
RP11/SEG17/CN49/RD0
RP12/C3INC/SEG16/PMA14/CS1/CN56/RD11
RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10
RP4/SEG14/PMACK2/CN54/RD9
RP2/SEG13/RTCC/CN53/RD8
RPI35/SEG43/PMBE1/CN44/RA15
RPI36/SEG42/PMA22/CN43/RA14
VSS
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
VDD
SEG28/SCL1/CN72/RG2
SEG47/SDA1/CN73/RG3
INT0/CN84/RF6
CN83/RF7
RP15/SEG41/CN74/RF8
RP30/SEG40/CN70/RF2
RP16/SEG12/CN71/RF3
PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6
PGED2/AN7/RP7/CN25/RB7
VREF-/SEG36/PMA7/CN41/RA9
VREF+/SEG37/PMA6/CN42/RA10
AVDD
AVSS
AN8/RP8/SEG31/COM7/CN26/RB8
AN9/RP9/SEG30/COM6/CN27/RB9
CVREF/AN10/SEG29/COM5/PMA13/CN28/RB10
AN11/PMA12/CN29/RB11
Vss
VDD
TCK/AN12/CTED2/SEG18/PMA11/CN30/RB12
TDI/AN13/CTED1/SEG19/PMA10/CN31/RB13
AN14/RP14/SEG8/CTPLS/CTED5/PMA1/CN32/RB14
AN15/RP29/SEG9/CTED6/REFO/PMA0/CN12/RB15
RPI43/SEG38/CN20/RD14
RP5/SEG39/CN21/RD15
RP10/SEG10/SDA2/PMA9/CN17/RF4
RP17/SEG11/SCL2/PMA8/CN18/RF5
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PMD5/CTED4/LCDBIAS2/CN63/RE5
PMD6/LCDBIAS1/CN64/RE6
PMD7/LCDBIAS0/CN65/RE7
RPI38/SEG32/CN45/RC1
RPI40/SEG33/CN47/RC3
C1IND/RP21/SEG0/PMA5/CN8/RG6
VLCAP1/C1INC/RP26/PMA4/CN9/RG7
VLCAP2/C2IND/RP19/PMA3/CN10/RG8
MCLR
C2INC/RP27/SEG1/PMA2/CN11/RG9
VSS
VDD
TMS/RPI33/SEG34/PMCS1/CN66/RE8
TDO/RPI34/SEG35/PMA19/CN67/RE9
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
AN3/C2INA/SEG4/CN5/RB3
AN2/C2INB/RP13/CTCMP/SEG5/CTED13/CN4/RB2
PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1
PGED1/CVREF+/AN0/RP0/SEG7/CN2/RB0
Legend: RPn and RPIn represent remappable pins for the Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Note 1: Refer to Table 4-22 for the list of analog ports.
DS30009996G-page 4
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Pin Diagrams (Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SEG63/PMD4/HLVDIN/CTED8/CN62/RE4
COM0/PMD3/CTED9/CN61/RE3
COM1/PMD2/CN60/RE2
SEG62/CTED10/CN80/RG13
SEG61/CN79/RG12
SEG60/PMA16/CTED11/CN81/RG14
COM2/PMD1/CN59/RE1
COM3/PMD0/CN58/RE0
AN22/SEG59/PMA17/CN40/RA7
AN23/SEG58/CN39/RA6
SEG50/PMD8/CN77/RG0
SEG46/PMD9/CN78/RG1
COM4/SEG48/PMD10/CN69/RF1
SEG27/PMD11/CN68/RF0
VBAT
VCAP/VDDCORE
C3INA/SEG26/PMD15/CN16/RD7
C3INB/SEG25/PMD14/CN15/RD6
RP20/SEG24/PMRD/CN14/RD5
RP25/SEG23/PMWR/CN13/RD4
SEG45/PMD13/CN19/RD13
RPI42/SEG44/PMD12/CN57/RD12
RP22/SEG22/PMBE0/CN52/RD3
RP23/SEG21/PMACK1/CN51/RD2
RP24/SEG20/CN50/RD1
100-Pin TQFP(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC24FJXXXGA310
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
RPI37/SOSCO/SCLKI/RC14
SOSCI/RC13
RP11/SEG17/CN49/RD0
RP12/SEG16/C3INC/PMA14/CS1/CN56/RD11
RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10
RP4/SEG14/PMACK2/CN54/RD9
RP2/SEG13/RTCC/CN53/RD8
RPI35/SEG43/PMBE1/CN44/RA15
RPI36/SEG42/PMA22/CN43/RA14
VSS
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
VDD
TDO/CN38/RA5
TDI/PMA21/CN37/RA4
SDA2/SEG57/PMA20/CN36/RA3
SCL2/SEG56/CN35/RA2
SCL1/SEG28/CN72/RG2
SDA1/SEG47/CN73/RG3
INT0/CN84/RF6
CN83/RF7
RP15/SEG41/CN74/RF8
RP30/SEG40/CN70/RF2
RP16/SEG12/CN71/RF3
PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6
PGED2/AN7/RP7/CN25/RB7
VREF-/SEG36/PMA7/CN41/RA9
VREF+/SEG37/PMA6/CN42/RA10
AVDD
AVSS
AN8/RP8/SEG31/COM7/CN26/RB8
AN9/RP9/SEG30/COM6/CN27/RB9
CVREF/AN10/SEG29/COM5/PMA13/CN28/RB10
AN11/PMA12/CN29/RB11
VSS
VDD
TCK/CN34/RA1
RP31/SEG54/CN76/RF13
RPI32/SEG55/CTED7/PMA18/CN75/RF12
AN12/CTED2/SEG18/PMA11/CN30/RB12
AN13/CTED1/PMA10/SEG19/CN31/RB13
AN14/RP14/SEG8/CTPLS/CTED5/PMA1/CN32/RB14
AN15/RP29/SEG9/REFO/CTED6/PMA0/CN12/RB15
VSS
VDD
RPI43/SEG38/CN20/RD14
RP5/SEG39/CN21/RD15
RP10/SEG10/PMA9/CN17/RF4
RP17/SEG11/PMA8/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SEG51/CTED3/CN82/RG15
VDD
CTED4/PMD5/LCDBIAS2/CN63/RE5
PMD6/LCDBIAS1/CN64/RE6
PMD7/LCDBIAS0/CN65/RE7
RPI38/SEG32/CN45/RC1
RPI39/SEG52/CN46/RC2
RPI40/SEG33/CN47/RC3
AN16/RPI41/SEG53/PMCS2/CN48/RC4
AN17/C1IND/RP21/SEG0/PMA5/CN8/RG6
VLCAP1/AN18/C1INC/RP26/PMA4/CN9/RG7
VLCAP2/AN19/C2IND/RP19/PMA3/CN10/RG8
MCLR
AN20/C2INC/RP27/SEG1/PMA2/CN11/RG9
VSS
VDD
TMS/CTED0/SEG49/CN33/RA0
RPI33/SEG34/PMCS1/CN66/RE8
AN21/RPI34/SEG35/PMA19/CN67/RE9
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
AN3/C2INA/SEG4/CN5/RB3
AN2/C2INB/RP13/SEG5/CTED13/CTCMP/CN4/RB2
PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1
PGED1/CVREF+/AN0/RP0/SEG7/CN2/RB0
Legend: RPn and RPIn represent remappable pins for the Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Note 1: Refer to Table 4-22 for the list of analog ports.
2010-2014 Microchip Technology Inc.
DS30009996G-page 5
PIC24FJ128GA310 FAMILY
Pin Diagrams (Continued)
121-Pin BGA (Top View)(1,2)
A
B
C
1
2
3
4
5
6
7
8
9
10
11
RE4
RE3
RG13
RE0
RG0
RF1
VBAT
N/C
RD12
RD2
RD1
N/C
RG15
RE2
RE1
RA7
RF0
VCAP/
VDDCORE
RD5
RD3
VSS
RC14
RE6
VDD
RG12
RG14
RA6
N/C
RD7
RD4
N/C
RC13
RD11
RC1
RE7
RE5
N/C
N/C
N/C
RD6
RD13
RD0
N/C
RD10
RC4
RC3
RG6
RC2
N/C
RG1
N/C
RA15
RD8
RD9
RA14
MCLR
RG8
RG9
RG7
VSS
N/C
N/C
VDD
OSCI/
RC12
VSS
OSCO/
RC15
RE8
RE9
RA0
N/C
VDD
VSS
VSS
N/C
RA5
RA3
RA4
RB5
RB4
N/C
N/C
N/C
VDD
N/C
RF7
RF6
RG2
RA2
RB3
RB2
RB7
AVDD
RB11
RA1
RB12
N/C
N/C
RF8
RG3
RB1
RB0
RA10
RB8
N/C
RF12
RB14
VDD
RD15
RF3
RF2
RB6
RA9
AVSS
RB9
RB10
RF13
RB13
RB15
RD14
RF4
RF5
D
E
F
G
H
J
K
L
Legend: Shaded pins indicate pins that are tolerant up to +5.5V.
Note 1: See Table 1 for complete pinout descriptions.
2: Refer to Table 4-22 for the list of analog ports.
DS30009996G-page 6
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES
Pin
Function
Pin
Function
A1
SEG63/PMD4/HLVDIN/CTED8/CN62/RE4
E1
AN16/RPI41/SEG53/PMCS2/CN48/RC4
A2
COM0/PMD3/CTED9/CN61/RE3
E2
RPI40/SEG33/CN47/RC3
A3
SEG62/CTED10/CN80/RG13
E3
AN17/C1IND/RP21/SEG0/PMA5/CN8/RG6
A4
COM3/PMD0/CN58/RE0
E4
RPI39/SEG52/CN46/RC2
A5
SEG50/PMD8/CN77/RG0
E5
N/C
A6
SEG48/COM4/PMD10/CN69/RF1
E6
SEG46/PMD9/CN78/RG1
A7
VBAT
E7
N/C
A8
N/C
E8
RPI35/SEG43/PMBE1/CN44/RA15
A9
RPI42/SEG44/PMD12/CN57/RD12
E9
RP2/SEG13/RTCC/CN53/RD8
A10
RP23/SEG21/PMACK1/CN51/RD2
E10
RP4/SEG14/PMACK2/CN54/RD9
A11
RP24/SEG20/CN50/RD1
E11
RPI36/SEG42/PMA22/CN43/RA14
B1
N/C
F1
MCLR
B2
SEG51/CTED3/CN82/RG15
F2
VLCAP2/AN19/C2IND/RP19/PMA3/CN10/RG8
B3
COM1/PMD2/CN60/RE2
F3
AN20/C2INC/RP27/SEG1/PMA2/CN11/RG9
B4
COM2/PMD1/CN59/RE1
F4
VLCAP1/AN18/C1INC/RP26/PMA4/CN9/RG7
B5
AN22/SEG59/PMA17/CN40/RA7
F5
VSS
B6
SEG27/PMD11/CN68/RF0
F6
N/C
B7
VCAP
F7
N/C
B8
RP20/SEG24/PMRD/CN14/RD5
F8
VDD
B9
RP22/SEG22/PMBE0/CN52/RD3
F9
OSCI/CLKI/CN23/RC12
B10
VSS
F10
VSS
B11
RPI37/SOSCO/SCLKI/RC14
F11
OSCO/CLKO/CN22/RC15
C1
PMD6/LCDBIAS1/CN64/RE6
G1
RPI33/SEG34/PMCS1/CN66/RE8
C2
VDD
G2
AN21/RPI34/SEG35/PMPA19/CN67/RE9
C3
SEG61/CN79/RG12
G3
TMS/SEG49/CTED0/CN33/RA0
C4
SEG60/PMA16/CTED11/CN81/RG14
G4
N/C
VDD
C5
AN23/SEG58/CN39/RA6
G5
C6
N/C
G6
VSS
C7
C3INA/SEG26/PMD15/CN16/RD7
G7
VSS
C8
RP25/SEG23/PMWR/CN13/RD4
G8
N/C
C9
N/C
G9
TDO/CN38/RA5
C10
SOSCI/RC13
G10
SDA2/SEG57/PMA20/CN36/RA3
C11
RP12/SEG16/C3INC/PMA14/CS1/CN56/RD11
G11
TDI/PMA21/CN37/RA4
D1
RPI38/SEG32/CN45/RC1
H1
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
D2
PMD7/LCDBIAS0/CN65/RE7
H2
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
D3
PMD5/CTED4/LCDBIAS2/CN63/RE5
H3
N/C
D4
N/C
H4
N/C
D5
N/C
H5
N/C
D6
N/C
H6
VDD
D7
C3INB/SEG25/PMD14/CN15/RD6
H7
N/C
D8
SEG45/PMD13/CN19/RD13
H8
CN83/RF7
D9
RP11/SEG17/CN49/RD0
H9
INT0/CN84/RF6
D10
N/C
H10
SCL1/SEG28/CN72/RG2
D11
RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10
H11
SCL2/SEG56/CN35/RA2
Legend:
RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
2010-2014 Microchip Technology Inc.
DS30009996G-page 7
PIC24FJ128GA310 FAMILY
TABLE 1:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES (CONTINUED)
Pin
Function
Pin
Function
J1
AN3/C2INA/SEG4/CN5/RB3
K7
J2
AN2/C2INB/RP13/SEG5/CTCMP/CTED13/CN4/RB2
K8
AN14/RP14/SEG8/CTPLS/CTED5/PMA1/CN32/RB14
VDD
J3
PGED2/AN7/RP7/CN25/RB7
K9
RP5/SEG39/CN21/RD15
J4
AVDD
K10
RP16/SEG12/CN71/RF3
J5
AN11/PMA12/CN29/RB11
K11
RP30/SEG40/CN70/RF2
J6
TCK/CN34/RA1
L1
PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6
J7
AN12/SEG18/CTED2/PMA11/CN30/RB12
L2
VREF-/SEG36/PMA7/CN41/RA9
J8
N/C
L3
AVSS
J9
N/C
L4
AN9/RP9/COM6/SEG30/CN27/RB9
J10
RP15/SEG41/CN74/RF8
L5
CVREF/AN10/COM5/SEG29/PMA13/CN28/RB10
J11
SDA1/SEG47/CN73/RG3
L6
RP31/SEG54/CN76/RF13
K1
PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1
L7
AN13/SEG19/CTED1/PMA10/CN31/RB13
K2
PGD1/CVREF+/AN0/RP0/SEG7/CN2/RB0
L8
AN15/RP29/SEG9/CTED6/REFO/PMA0/CN12/RB15
K3
VREF+/SEG37/PMA6/CN42/RA10
L9
RPI43/SEG38/CN20/RD14
K4
AN8/RP8/COM7/SEG31/CN26/RB8
L10
RP10/SEG10/PMA9/CN17/RF4
K5
N/C
L11
RP17/SEG11/PMA8/CN18/RF5
K6
RPI32/SEG55/CTED7/PMA18/CN75/RF12
Legend:
RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
DS30009996G-page 8
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 29
3.0 CPU ........................................................................................................................................................................................... 35
4.0 Memory Organization ................................................................................................................................................................. 41
5.0 Direct Memory Access Controller (DMA) ................................................................................................................................... 75
6.0 Flash Program Memory.............................................................................................................................................................. 83
7.0 Resets ........................................................................................................................................................................................ 89
8.0 Interrupt Controller ..................................................................................................................................................................... 95
9.0 Oscillator Configuration ............................................................................................................................................................ 145
10.0 Power-Saving Features............................................................................................................................................................ 155
11.0 I/O Ports ................................................................................................................................................................................... 167
12.0 Timer1 ...................................................................................................................................................................................... 197
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 199
14.0 Input Capture with Dedicated Timers ....................................................................................................................................... 205
15.0 Output Compare with Dedicated Timers .................................................................................................................................. 211
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 221
17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 233
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 241
19.0 Data Signal Modulator.............................................................................................................................................................. 249
20.0 Enhanced Parallel Master Port (EPMP) ................................................................................................................................... 253
21.0 Liquid Crystal Display (LCD) Controller.................................................................................................................................... 265
22.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 275
23.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 289
24.0 12-Bit A/D Converter (ADC) with Threshold Scan.................................................................................................................... 295
25.0 Triple Comparator Module........................................................................................................................................................ 315
26.0 Comparator Voltage Reference................................................................................................................................................ 321
27.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 323
28.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 331
29.0 Special Features ...................................................................................................................................................................... 333
30.0 Development Support............................................................................................................................................................... 347
31.0 Instruction Set Summary .......................................................................................................................................................... 351
32.0 Electrical Characteristics .......................................................................................................................................................... 359
33.0 Packaging Information.............................................................................................................................................................. 389
Appendix A: Revision History............................................................................................................................................................. 407
Index ................................................................................................................................................................................................. 409
The Microchip Web Site ..................................................................................................................................................................... 415
Customer Change Notification Service .............................................................................................................................................. 415
Customer Support .............................................................................................................................................................................. 415
Product Identification System ............................................................................................................................................................ 417
2010-2014 Microchip Technology Inc.
DS30009996G-page 9
PIC24FJ128GA310 FAMILY
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS30009996G-page 10
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ64GA306
• PIC24FJ128GA306
• PIC24FJ64GA308
• PIC24FJ128GA308
• PIC24FJ64GA310
• PIC24FJ128GA310
The PIC24FJ128GA310 family adds many new features
to Microchip‘s 16-bit microcontrollers, including new
ultra low-power features, Direct Memory Access (DMA)
for peripherals, and a built-in LCD Controller and Driver.
Together, these provide a wide range of powerful
features in one economical and power-saving package.
1.1
1.1.1
Core Features
16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements, such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)
• A 16-element Working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.2
XLP POWER-SAVING
TECHNOLOGY
The PIC24FJ128GA310 family of devices introduces a
greatly expanded range of power-saving operating
modes for the ultimate in power conservation. The new
modes include:
• Retention Sleep with essential circuits being
powered from a separate low-voltage regulator
• Deep Sleep without RTCC for the lowest possible
power consumption under software control
• VBAT mode (with or without RTCC) to continue
limited operation from a backup battery when VDD
is removed
Aside from these new features, PIC24FJ128GA310
family devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
• On-the-Fly Clock Switching, allowing the selection
of a lower power clock during run time
• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick
invocation of Idle and the many Sleep modes.
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ128GA310 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• Two Crystal modes
• Two External Clock modes
• A Phase Lock Loop (PLL) frequency multiplier,
which allows clock speeds of up to 32 MHz
• A Fast Internal Oscillator (FRC) (nominal 8 MHz
output) with multiple frequency divider options
• A separate Low-Power Internal RC Oscillator
(LPRC) (31 kHz nominal) for low-power,
timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the internal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger, or even in jumping from 64-pin to 100-pin
devices.
The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
Many of these new low-power modes also support the
continuous operation of the low-power, on-chip
Real-Time Clock/Calendar (RTCC), making it possible
for an application to keep time while the device is
otherwise asleep.
2010-2014 Microchip Technology Inc.
DS30009996G-page 11
PIC24FJ128GA310 FAMILY
1.2
DMA Controller
PIC24FJ128GA310 family devices also introduce a
new Direct Memory Access Controller (DMA) to the
PIC24F architecture. This module acts in concert with
the CPU, allowing data to move between data memory
and peripherals without the intervention of the CPU,
increasing data throughput and decreasing execution
time overhead. Six independently programmable channels make it possible to service multiple peripherals at
virtually the same time, with each channel peripheral
performing a different operation. Many types of data
transfer operations are supported.
1.3
LCD Controller
With the PIC24FJ128GA310 family of devices,
Microchip introduces its versatile Liquid Crystal Display
(LCD) controller and driver to the PIC24F family. The
on-chip LCD driver includes many features that make
the integration of displays in low-power applications
easier. These include an integrated voltage regulator
with charge pump, and an integrated internal resistor
ladder that allows contrast control in software and
display operation above device VDD.
1.4
Other Special Features
• Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
• Communications: The PIC24FJ128GA310 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are two independent I2C™
modules that support both Master and Slave
modes of operation. Devices also have, through
the PPS feature, four independent UARTs with
built-in IrDA® encoders/decoders and two SPI
modules.
• Analog Features: All members of the
PIC24FJ128GA310 family include the new 12-bit
A/D Converter (ADC) module and a triple comparator module. The ADC module incorporates a
range of new features that allow the converter to
assess and make decisions on incoming data,
reducing CPU overhead for routine ADC conversions. The comparator module includes three
analog comparators that are configurable for a
wide range of operations.
• CTMU Interface: In addition to their other analog
features, members of the PIC24FJ128GA310
family include the CTMU interface module. This
provides a convenient method for precision time
measurement and pulse generation, and can
serve as an interface for capacitive sensors.
DS30009996G-page 12
• Enhanced Parallel Master/Parallel Slave Port:
This module allows rapid and transparent access
to the microcontroller data bus, and enables the
CPU to directly address external data memory. The
parallel port can function in Master or Slave mode,
accommodating data widths of 4, 8 or 16 bits, and
address widths up to 23 bits in Master modes.
• Real-Time Clock and Calendar (RTCC): This
module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.
• Data Signal Modulator (DSM): The Data Signal
Modulator (DSM) allows the user to mix a digital
data stream (the “modulator signal”) with a carrier
signal to produce a modulated output.
1.5
Details on Individual Family
Members
Devices in the PIC24FJ128GA310 family are available
in 64-pin, 80-pin and 100-pin packages. The general
block diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in
six ways:
1.
2.
3.
4.
5.
6.
Flash program memory (64 Kbytes for
PIC24FJ64GA3XX devices and 128 Kbytes for
PIC24FJ128GA3XX devices).
Available I/O pins and ports (53 pins on 6 ports
for 64-pin devices, 69 pins on 7 ports for 80-pin
devices and 85 pins on 7 ports for 100-pin
devices).
Available Interrupt-on-Change Notification (ICN)
inputs (52 on 64-pin devices, 66 on 80-pin
devices and 82 on 100-pin devices).
Available remappable pins (29 pins on 64-pin
devices, 40 on 80-pin devices and 44 pins on
100-pin devices).
Maximum available drivable LCD pixels (272 on
64-pin devices, 368 on 80-pin devices and
480 on 100-pin devices).
Analog input channels (16 channels for 64-pin
and 80-pin devices, and 24 channels for 100-pin
devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1, Table 1-2 and
Table 1-3.
A list of the pin features available on the
PIC24FJ128GA310 family devices, sorted by function,
is shown in Table 1-4. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information is
provided in the pinout diagrams in the beginning of this
data sheet. Multiplexed features are sorted by the priority
given to a feature, with the highest priority peripheral
being listed first.
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 64-PIN
Features
PIC24FJ64GA306
Operating Frequency
Program Memory (bytes)
Program Memory (instructions)
PIC24FJ128GA306
DC – 32 MHz
64K
128K
22,016
Data Memory (bytes)
44,032
8K
Interrupt Sources (soft vectors/
NMI traps)
65 (61/4)
I/O Ports
Ports B, C, D, E, F, G
Total I/O Pins
53
Remappable Pins
30 (29 I/Os, 1 input only)
Timers:
5(1)
Total Number (16-bit)
32-Bit (from paired 16-bit timers)
2
Input Capture Channels
7(1)
Output Compare/PWM Channels
7(1)
Input Change Notification Interrupt
52
Serial Communications:
UART
4(1)
SPI (3-wire/4-wire)
2(1)
I2C™
2
Digital Signal Modulator
Yes
Parallel Communications (EPMP/PSP)
Yes
JTAG Boundary Scan
Yes
12/10-Bit Analog-to-Digital Converter
(ADC) Module (input channels)
16
Analog Comparators
3
CTMU Interface
Yes
LCD Controller (available pixels)
240 (30 SEG x 8 COM)
Resets (and Delays)
Core POR, VDD POR, VBAT POR, BOR, RESET Instruction,
MCLR, WDT, Illegal Opcode, REPEAT Instruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
Instruction Set
76 Base Instructions, Multiple Addressing Mode Variations
Packages
Note 1:
64-Pin TQFP and QFN
Peripherals are accessible through remappable pins.
2010-2014 Microchip Technology Inc.
DS30009996G-page 13
PIC24FJ128GA310 FAMILY
TABLE 1-2:
DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 80-PIN
Features
PIC24FJ64GA308
Operating Frequency
Program Memory (bytes)
Program Memory (instructions)
PIC24FJ128GA308
DC – 32 MHz
64K
128K
22,016
Data Memory (bytes)
44,032
8K
Interrupt Sources (soft vectors/
NMI traps)
65 (61/4)
I/O Ports
Ports A, B, C, D, E, F, G
Total I/O Pins
69
Remappable Pins
40 (31 I/Os, 9 input only)
Timers:
5(1)
Total Number (16-bit)
32-Bit (from paired 16-bit timers)
2
Input Capture Channels
7(1)
Output Compare/PWM Channels
7(1)
Input Change Notification Interrupt
66
Serial Communications:
UART
4(1)
SPI (3-wire/4-wire)
2(1)
I2C™
2
Digital Signal Modulator
Yes
Parallel Communications (EPMP/PSP)
Yes
JTAG Boundary Scan
Yes
12/10-Bit Analog-to-Digital Converter
(ADC) Module (input channels)
16
Analog Comparators
3
CTMU Interface
Yes
LCD Controller (available pixels)
368 (46 SEG x 8 COM)
Resets (and Delays)
Core POR, VDD POR, VBAT POR, BOR, RESET Instruction,
MCLR, WDT, Illegal Opcode, REPEAT Instruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
Instruction Set
76 Base Instructions, Multiple Addressing Mode Variations
Packages
Note 1:
80-Pin TQFP and QFN
Peripherals are accessible through remappable pins.
DS30009996G-page 14
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-3:
DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 100-PIN DEVICES
Features
PIC24FJ64GA310
Operating Frequency
Program Memory (bytes)
Program Memory (instructions)
PIC24FJ128GA310
DC – 32 MHz
64K
128K
22,016
44,032
Data Memory (bytes)
8K
Interrupt Sources (soft vectors/NMI
traps)
66 (62/4)
I/O Ports
Ports A, B, C, D, E, F, G
Total I/O Pins
85
Remappable Pins
44 (32 I/Os, 12 input only)
Timers:
5(1)
Total Number (16-bit)
32-Bit (from paired 16-bit timers)
2
Input Capture Channels
7(1)
Output Compare/PWM Channels
7(1)
Input Change Notification Interrupt
82
Serial Communications:
UART
4(1)
SPI (3-wire/4-wire)
2(1)
I2C™
2
Digital Signal Modulator
Yes
Parallel Communications
(EPMP/PSP)
Yes
JTAG Boundary Scan
Yes
12/10-Bit Analog-to-Digital Converter
(ADC) Module (input channels)
24
Analog Comparators
3
CTMU Interface
Yes
LCD Controller (available pixels)
480 (60 SEG x 8 COM)
Resets (and delays)
Core POR, VDD POR, VBAT POR, BOR, RESET Instruction,
MCLR, WDT, Illegal Opcode, REPEAT Instruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
Instruction Set
76 Base Instructions, Multiple Addressing Mode Variations
Packages
Note 1:
100-Pin TQFP and 121-Pin BGA
Peripherals are accessible through remappable pins.
2010-2014 Microchip Technology Inc.
DS30009996G-page 15
PIC24FJ128GA310 FAMILY
FIGURE 1-1:
PIC24FJ128GA310 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
Interrupt
Controller
PORTA(1)
16
(12 I/O)
16
16
8
Data Latch
EDS and
Table Data
Access Control
23
DMA
Controller
Data RAM
PCH
PCL
Program Counter
Repeat
Stack
Control
Control
Logic
Logic
Address
Latch
PORTB
(16 I/O)
16
23
16
16
Read AGU
Write AGU
Address Latch
Program Memory/
Extended Data
Space
PORTC(1)
(8 I/O)
Data Latch
Address Bus
16
EA MUX
24
Inst Register
Control Signals
REFO
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulators
PORTD(1)
Literal
Data
(16 I/O)
DMA
Data Bus
Instruction
Decode and
Control
Divide
Support
OSCO/CLKO
OSCI/CLKI
Timing
Generation
16
16
Inst Latch
17x17
Multiplier
Power-up
Timer
PORTE(1)
(10 I/O)
16 x 16
W Reg Array
Oscillator
Start-up Timer
PORTF(1)
16-Bit ALU
Power-on
Reset
(10 I/O)
16
Watchdog
Timer
HLVD &
BOR(2)
PORTG(1)
(12 I/O)
VCAP
Timer1
VBAT
Timer2/3(3)
VDD, VSS
Timer4/5(3)
MCLR
RTCC
12-Bit
ADC
Comparators(3)
Digital
Modulator
EPMP/PSP
IC
1-7(3)
Note 1:
2:
3:
OC/PWM
1-7(3)
ICNs(1)
SPI
1/2(3)
I2C™
1/2
UART
1/2/3/4(3)
CTMU
LCD
Driver
Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-4 for specific implementations by pin count.
BOR functionality is provided when the on-board voltage regulator is enabled.
These peripheral I/Os are only accessible through remappable pins.
DS30009996G-page 16
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
AN0
16
20
25
K2
I
ANA
AN1
15
19
24
K1
I
ANA
AN2
14
18
23
J2
I
ANA
AN3
13
17
22
J1
I
ANA
AN4
12
16
21
H2
I
ANA
AN5
11
15
20
H1
I
ANA
AN6
17
21
26
L1
I
ANA
AN7
18
22
27
J3
I
ANA
AN8
21
27
32
K4
I
ANA
AN9
22
28
33
L4
I
ANA
ANA
Description
ADC Analog Inputs.
AN10
23
29
34
L5
I
AN11
24
30
35
J5
I
ANA
AN12
27
33
41
J7
I
ANA
AN13
28
34
42
L7
I
ANA
AN14
29
35
43
K7
I
ANA
AN15
30
36
44
L8
I
ANA
AN16
—
—
9
E1
I
ANA
AN17
—
—
10
E3
I
ANA
AN18
—
—
11
F4
I
ANA
AN19
—
—
12
F2
I
ANA
AN20
—
—
14
F3
I
ANA
AN21
—
—
19
G2
I
ANA
AN22
—
—
92
B5
I
ANA
AN23
—
—
91
C5
I
ANA
AVDD
19
25
30
J4
P
—
Positive Supply for Analog modules.
AVSS
20
26
31
L3
P
—
Ground Reference for Analog modules.
C1INA
11
15
20
H1
I
ANA
Comparator 1 Input A.
C1INB
12
16
21
H2
I
ANA
Comparator 1 Input B.
C1INC
5
7
11
F4
I
ANA
Comparator 1 Input C.
C1IND
4
6
10
E3
I
ANA
Comparator 1 Input D.
C2INA
13
17
22
J1
I
ANA
Comparator 2 Input A.
C2INB
14
18
23
J2
I
ANA
Comparator 2 Input B.
C2INC
8
10
14
F3
I
ANA
Comparator 2 Input C.
C2IND
6
8
12
F2
I
ANA
Comparator 2 Input D.
C3INA
55
69
84
C7
I
ANA
Comparator 3 Input A.
C3INB
54
68
83
D7
I
ANA
Comparator 3 Input B.
C3INC
45
57
71
C11
I
ANA
Comparator 3 Input C.
C3IND
44
56
70
D11
I
ANA
Comparator 3 Input D.
CLKI
39
49
63
F9
I
ANA
CLKO
40
50
64
F11
O
—
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
2010-2014 Microchip Technology Inc.
Main Clock Input Connection.
System Clock Output.
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
DS30009996G-page 17
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
CN2
16
20
25
K2
I
ST
CN3
15
19
24
K1
I
ST
CN4
14
18
23
J2
I
ST
CN5
13
17
22
J1
I
ST
CN6
12
16
21
H2
I
ST
CN7
11
15
20
H1
I
ST
CN8
4
6
10
E3
I
ST
CN9
5
7
11
F4
I
ST
CN10
6
8
12
F2
I
ST
CN11
8
10
14
F3
I
ST
CN12
30
36
44
L8
I
ST
CN13
52
66
81
C8
I
ST
CN14
53
67
82
B8
I
ST
CN15
54
68
83
D7
I
ST
CN16
55
69
84
C7
I
ST
CN17
31
39
49
L10
I
ST
CN18
32
40
50
L11
I
ST
CN19
—
65
80
D8
I
ST
CN20
—
37
47
L9
I
ST
CN21
—
38
48
K9
I
ST
CN22
40
50
64
F11
I
ST
CN23
39
49
63
F9
I
ST
CN24
17
21
26
L1
I
ST
CN25
18
22
27
J3
I
ST
CN26
21
27
32
K4
I
ST
CN27
22
28
33
L4
I
ST
CN28
23
29
34
L5
I
ST
CN29
24
30
35
J5
I
ST
CN30
27
33
41
J7
I
ST
CN31
28
34
42
L7
I
ST
CN32
29
35
43
K7
I
ST
CN33
—
—
17
G3
I
ST
CN34
—
—
38
J6
I
ST
CN35
—
—
58
H11
I
ST
CN36
—
—
59
G10
I
ST
CN37
—
—
60
G11
I
ST
CN38
—
—
61
G9
I
ST
CN39
—
—
91
C5
I
ST
CN40
—
—
92
B5
I
ST
CN41
—
23
28
L2
I
ST
CN42
—
24
29
K3
I
ST
CN43
—
52
66
E11
I
ST
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
DS30009996G-page 18
Description
Interrupt-on-Change Inputs.
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
121-Pin
BGA
I/O
Input
Buffer
67
E8
I
ST
6
D1
I
ST
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
CN44
—
53
CN45
—
4
CN46
—
—
7
E4
I
ST
CN47
—
5
8
E2
I
ST
CN48
—
—
9
E1
I
ST
CN49
46
58
72
D9
I
ST
CN50
49
61
76
A11
I
ST
CN51
50
62
77
A10
I
ST
CN52
51
63
78
B9
I
ST
CN53
42
54
68
E9
I
ST
CN54
43
55
69
E10
I
ST
CN55
44
56
70
D11
I
ST
CN56
45
57
71
C11
I
ST
CN57
—
64
79
A9
I
ST
CN58
60
76
93
A4
I
ST
CN59
61
77
94
B4
I
ST
CN60
62
78
98
119
I
ST
CN61
63
79
99
A2
I
ST
CN62
64
80
100
A1
I
ST
CN63
1
1
3
D3
I
ST
CN64
2
2
4
C1
I
ST
CN65
3
3
5
D2
I
ST
CN66
—
13
18
G1
I
ST
CN67
—
14
19
G2
I
ST
CN68
58
72
87
B6
I
ST
CN69
59
73
88
A6
I
ST
CN70
34
42
52
K11
I
ST
CN71
33
41
51
K10
I
ST
CN72
37
47
57
H10
I
ST
CN73
36
46
56
J11
I
ST
CN74
—
43
53
J10
I
ST
CN75
—
—
40
K6
I
ST
CN76
—
—
39
L6
I
ST
CN77
—
75
90
A5
I
ST
CN78
—
74
89
E6
I
ST
CN79
—
—
96
C3
I
ST
CN80
—
—
97
A3
I
ST
CN81
—
—
95
C4
I
ST
CN82
—
—
1
B2
I
ST
CN83
—
44
54
H8
I
ST
CN84
35
45
55
H9
I
ST
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
2010-2014 Microchip Technology Inc.
Description
Interrupt-on-Change Inputs.
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
DS30009996G-page 19
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
COM0
63
79
99
A2
O
—
COM1
62
78
98
B3
O
—
COM2
61
77
94
B4
O
—
COM3
60
76
93
A4
O
—
COM4
59
73
88
A6
O
—
COM5
23
29
34
L5
O
—
COM6
22
28
33
L4
O
—
COM7
21
27
32
K4
O
—
CS1
45
57
71
C11
I/O
ST/TTL
Parallel Master Port Chip Select 1 Strobe (shared
with PMA14).
CS2
44
56
70
D11
O
—
Parallel Master Port Chip Select 2 Strobe (shared
with PMA15).
CTCMP
14
18
23
J2
I
ANA
CTMU Comparator 2 Input (Pulse mode).
CTED0
—
—
17
G3
I
DIG
CTMU External Edge Inputs.
CTED1
28
34
42
L7
I
DIG
CTED2
27
33
41
J7
I
DIG
CTED3
—
—
1
B2
I
DIG
CTED4
1
1
3
D3
I
DIG
CTED5
29
35
43
K7
I
DIG
CTED6
30
36
44
L8
I
DIG
DIG
Pin
Function
CTED7
—
—
40
47
I
CTED8
64
80
100
A1
I
DIG
CTED9
63
79
99
A2
I
DIG
CTED10
—
—
97
A3
I
DIG
DIG
Description
LCD Driver Common Outputs.
CTED11
—
—
95
C4
I
CTED12
15
19
24
K1
I
DIG
CTED13
14
18
23
J2
I
DIG
CTPLS
29
35
43
K7
O
—
CTMU Pulse Output.
CVREF
23
29
34
L5
O
—
Comparator Voltage Reference Output.
CVREF+
16
20
25
K2
I
ANA
CVREF-
15
19
24
K1
I
ANA
INT0
35
45
55
H9
I
ST
LCDBIAS0
3
3
5
D2
I
ANA
LCDBIAS1
2
2
4
C1
I
ANA
LCDBIAS2
1
1
3
D3
I
ANA
LCDBIAS3
17
21
26
L1
I
ANA
HLVDIN
64
80
100
A1
I
ANA
MCLR
7
9
13
F1
I
ST
OSCI
39
49
63
F9
I
ANA
OSCO
40
50
64
F11
O
—
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
DS30009996G-page 20
Comparator/ADC Reference Voltage (high) Input.
Comparator/ADC Reference Voltage (low) Input.
External Interrupt Input 0.
Bias Inputs for LCD Driver Charge Pump.
High/Low-Voltage Detect Input.
Master Clear (device Reset) Input. This line is
brought low to cause a Reset.
Main Oscillator Input Connection.
Main Oscillator Output Connection.
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
PGEC1
15
19
24
K1
I/O
ST
In-Circuit Debugger/Emulator/ICSP™ Programming
Clock 1.
PGED1
16
20
25
K2
I/O
ST
In-Circuit Debugger/Emulator/ICSP Programming
Data 1.
PGEC2
17
21
26
L1
I/O
ST
In-Circuit Debugger/Emulator/ICSP Programming
Clock 2.
PGED2
18
22
27
J3
I/O
ST
In-Circuit Debugger/Emulator/ICSP Programming
Data 2.
PGEC3
11
15
20
H1
I/O
ST
In-Circuit Debugger/Emulator/ICSP Programming
Clock 3.
PGED3
12
16
21
H2
I/O
ST
In-Circuit Debugger/Emulator/ICSP Programming
Data 3.
PMA0
30
36
44
L8
I/O
ST
Parallel Master Port Address Bit 0 Input (Buffered
Slave modes) and Output (Master modes).
PMA1
29
35
43
K7
I/O
ST
Parallel Master Port Address Bit 1 Input (Buffered
Slave modes) and Output (Master modes).
PMA2
8
10
14
F3
O
—
Parallel Master Port Address (bits).
PMA3
6
8
12
F2
O
—
PMA4
5
7
11
F4
O
—
PMA5
4
6
10
E3
O
—
PMA6
16
24
29
K3
O
—
PMA7
22
23
28
L2
O
—
PMA8
32
40
50
L11
O
—
PMA9
31
39
49
L10
O
—
PMA10
28
34
42
L7
O
—
PMA11
27
33
41
J7
O
—
PMA12
24
30
35
J5
O
—
PMA13
23
29
34
L5
O
—
PMA14
45
57
71
C11
O
—
PMA15
44
56
70
D11
O
—
PMA16
—
—
95
C4
O
—
PMA17
—
—
92
B5
O
—
PMA18
—
—
40
K6
O
—
PMA19
—
14
19
G2
O
—
PMA20
—
—
59
G10
O
—
PMA21
—
—
60
G11
O
—
Description
PMA22
—
52
66
E11
O
—
PMACK1
50
62
77
A10
I
ST/TTL
PMACK2
43
55
69
E10
I
ST/TTL
Parallel Master Port Acknowledge Input 2.
PMBE0
51
63
78
B9
O
—
Parallel Master Port Byte Enable 0 Strobe.
Parallel Master Port Acknowledge Input 1.
PMBE1
—
53
67
E8
O
—
Parallel Master Port Byte Enable 1 Strobe.
PMCS1
—
13
18
G1
I/O
ST/TTL
Parallel Master Port Chip Select 1 Strobe.
—
—
9
E1
O
—
Parallel Master Port Chip Select 2 Strobe.
PMCS2
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
2010-2014 Microchip Technology Inc.
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
DS30009996G-page 21
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
PMD0
60
76
93
A4
I/O
ST/TTL
PMD1
61
77
94
B4
I/O
ST/TTL
PMD2
62
78
98
B3
I/O
ST/TTL
PMD3
63
79
99
A2
I/O
ST/TTL
PMD4
64
80
100
A1
I/O
ST/TTL
PMD5
1
1
3
D3
I/O
ST/TTL
PMD6
2
2
4
C1
I/O
ST/TTL
PMD7
3
3
5
D2
I/O
ST/TTL
PMD8
—
75
90
A5
I/O
ST/TTL
PMD9
—
74
89
E6
I/O
ST/TTL
Description
Parallel Master Port Data (Demultiplexed Master
mode) or Address/Data (Multiplexed Master modes).
PMD10
—
73
88
A6
I/O
ST/TTL
PMD11
—
72
87
B6
I/O
ST/TTL
PMD12
—
64
79
A9
I/O
ST/TTL
PMD13
—
65
80
D8
I/O
ST/TTL
PMD14
—
68
83
D7
I/O
ST/TTL
PMD15
—
69
84
C7
I/O
ST/TTL
PMRD
53
67
82
B8
O
—
Parallel Master Port Read Strobe.
PMWR
52
66
81
C8
O
—
Parallel Master Port Write Strobe.
RA0
—
—
17
G3
I/O
ST
PORTA Digital I/O.
RA1
—
—
38
J6
I/O
ST
RA2
—
—
58
H11
I/O
ST
RA3
—
—
59
G10
I/O
ST
RA4
—
—
60
G11
I/O
ST
RA5
—
—
61
G9
I/O
ST
RA6
—
—
91
C5
I/O
ST
RA7
—
—
92
B5
I/O
ST
RA9
—
23
28
L2
I/O
ST
RA10
—
24
29
K3
I/O
ST
RA14
—
52
66
E11
I/O
ST
RA15
—
53
67
E8
I/O
ST
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
DS30009996G-page 22
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
RB0
16
20
25
K2
I/O
ST
RB1
15
19
24
K1
I/O
ST
RB2
14
18
23
J2
I/O
ST
RB3
13
17
22
J1
I/O
ST
RB4
12
16
21
H2
I/O
ST
RB5
11
15
20
H1
I/O
ST
RB6
17
21
26
L1
I/O
ST
RB7
18
22
27
J3
I/O
ST
RB8
21
27
32
K4
I/O
ST
RB9
22
28
33
L4
I/O
ST
RB10
23
29
34
L5
I/O
ST
RB11
24
30
35
J5
I/O
ST
RB12
27
33
41
J7
I/O
ST
RB13
28
34
42
L7
I/O
ST
RB14
29
35
43
K7
I/O
ST
RB15
30
36
44
L8
I/O
ST
RC1
—
4
6
D1
I/O
ST
RC2
—
—
7
E4
I/O
ST
RC3
—
5
8
E2
I/O
ST
RC4
—
—
9
E1
I/O
ST
RC12
39
49
63
F9
I/O
ST
RC13
47
59
73
C10
I
ST
RC14
48
60
74
B11
I
ST
RC15
40
50
64
F11
I/O
ST
RD0
46
58
72
D9
I/O
ST
RD1
49
61
76
A11
I/O
ST
RD2
50
62
77
A10
I/O
ST
RD3
51
63
78
B9
I/O
ST
RD4
52
66
81
C8
I/O
ST
RD5
53
67
82
B8
I/O
ST
RD6
54
68
83
D7
I/O
ST
RD7
55
69
84
C7
I/O
ST
RD8
42
54
68
E9
I/O
ST
RD9
43
55
69
E10
I/O
ST
RD10
44
56
70
D11
I/O
ST
RD11
45
57
71
C11
I/O
ST
RD12
—
64
79
A9
I/O
ST
RD13
—
65
80
D8
I/O
ST
RD14
—
37
47
L9
I/O
ST
RD15
—
38
48
K9
I/O
ST
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
2010-2014 Microchip Technology Inc.
Description
PORTB Digital I/O.
PORTC Digital I/O.
PORTD Digital I/O.
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
DS30009996G-page 23
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
RE0
60
76
93
A4
I/O
ST
RE1
61
77
94
B4
I/O
ST
RE2
62
78
98
B3
I/O
ST
RE3
63
79
99
A2
I/O
ST
RE4
64
80
100
A1
I/O
ST
RE5
1
1
3
D3
I/O
ST
RE6
2
2
4
C1
I/O
ST
RE7
3
3
5
D2
I/O
ST
RE8
—
13
18
G1
I/O
ST
RE9
—
14
19
G2
I/O
ST
Description
PORTE Digital I/O.
REFO
30
36
44
L8
O
—
Reference Clock Output.
RF0
58
72
87
B6
I/O
ST
PORTF Digital I/O.
RF1
59
73
88
A6
I/O
ST
RF2
34
42
52
K11
I/O
ST
RF3
33
41
51
K10
I/O
ST
RF4
31
39
49
L10
I/O
ST
RF5
32
40
50
L11
I/O
ST
RF6
35
45
55
H9
I/O
ST
ST
RF7
—
44
54
H8
I/O
RF8
—
43
53
J10
I/O
ST
RF12
—
—
40
K6
I/O
ST
RF13
—
—
39
L6
I/O
ST
RG0
—
75
90
A5
I/O
ST
RG1
—
74
89
E6
I/O
ST
RG2
37
47
57
H10
I/O
ST
RG3
36
46
56
J11
I/O
ST
RG6
4
6
10
E3
I/O
ST
RG7
5
7
11
F4
I/O
ST
RG8
6
8
12
F2
I/O
ST
RG9
8
10
14
F3
I/O
ST
ST
RG12
—
—
96
C3
I/O
RG13
—
—
97
A3
I/O
ST
RG14
—
—
95
C4
I/O
ST
RG15
—
—
1
B2
I/O
ST
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
DS30009996G-page 24
PORTG Digital I/O.
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
RP0
16
20
25
K2
I/O
ST
RP1
15
19
24
K1
I/O
ST
RP2
42
54
68
E9
I/O
ST
RP3
44
56
70
D11
I/O
ST
RP4
43
55
69
E10
I/O
ST
RP5
—
38
48
K9
I/O
ST
RP6
17
21
26
L1
I/O
ST
RP7
18
22
27
J3
I/O
ST
RP8
21
27
32
K4
I/O
ST
RP9
22
28
33
L4
I/O
ST
RP10
31
39
49
L10
I/O
ST
RP11
46
58
72
D9
I/O
ST
RP12
45
57
71
C11
I/O
ST
RP13
14
18
23
J2
I/O
ST
RP14
29
35
43
K7
I/O
ST
RP15
—
43
53
J10
I/O
ST
RP16
33
41
51
K10
I/O
ST
RP17
32
40
50
L11
I/O
ST
RP18
11
15
20
H1
I/O
ST
RP19
6
8
12
F2
I/O
ST
RP20
53
67
82
B8
I/O
ST
RP21
4
6
10
E3
I/O
ST
ST
RP22
51
63
78
B9
I/O
RP23
50
62
77
A10
I/O
ST
RP24
49
61
76
A11
I/O
ST
RP25
52
66
81
C8
I/O
ST
RP26
5
7
11
F4
I/O
ST
RP27
8
10
14
F3
I/O
ST
RP28
12
16
21
H2
I/O
ST
RP29
30
36
44
L8
I/O
ST
RP30
34
42
52
K11
I/O
ST
RP31
—
—
39
L6
I/O
ST
RPI32
—
—
40
K6
I
ST
RPI33
—
13
18
G1
I
ST
RPI34
—
14
19
G2
I
ST
RPI35
—
53
67
E8
I
ST
RPI36
—
52
66
E11
I
ST
RPI37
48
60
74
B11
I
ST
RPI38
—
4
6
D1
I
ST
RPI39
—
—
7
E4
I
ST
RPI40
—
5
8
E2
I
ST
RPI41
—
—
9
E1
I
ST
RPI42
—
64
79
A9
I
ST
RPI43
—
37
47
L9
I
ST
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
2010-2014 Microchip Technology Inc.
Description
Remappable Peripheral (input or output).
Remappable Peripheral (input only).
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
DS30009996G-page 25
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
RTCC
42
54
68
E9
O
—
Real-Time Clock/Calendar Alarm/Seconds Pulse
Output.
SCL1
37
47
57
H10
I/O
I2C
I2C1 Synchronous Serial Clock Input/Output.
SCL2
32
40
58
H11
I/O
I2C
I2C2 Synchronous Serial Clock Input/Output.
SCLKI
48
60
74
B11
I
ST
Digital Secondary Clock Input.
I2C1 Data Input/Output.
Description
SDA1
36
46
56
J11
I/O
I2C
SDA2
31
39
59
G10
I/O
I2C
I2C2 Data Input/Output.
SEG0
4
6
10
E3
O
—
LCD Driver Segment Outputs.
SEG1
8
10
14
F3
O
—
—
SEG2
11
15
20
H1
O
SEG3
12
16
21
H2
O
—
SEG4
13
17
22
J1
O
—
SEG5
14
18
23
J2
O
—
SEG6
15
19
24
K1
O
—
SEG7
16
20
25
K2
O
—
SEG8
29
35
43
K7
O
—
SEG9
30
36
44
L8
O
—
SEG10
31
39
49
L10
O
—
SEG11
32
40
50
L11
O
—
SEG12
33
41
51
K10
O
—
SEG13
42
54
68
E9
O
—
SEG14
43
55
69
E10
O
—
SEG15
44
56
70
D11
O
—
SEG16
45
57
71
C11
O
—
SEG17
46
58
72
D9
O
—
SEG18
27
33
41
J7
O
—
SEG19
28
34
42
L7
O
—
SEG20
49
61
76
A11
O
—
SEG21
50
62
77
A10
O
—
SEG22
51
63
78
B9
O
—
SEG23
52
66
81
C8
O
—
SEG24
53
67
82
B8
O
—
SEG25
54
68
83
D7
O
—
SEG26
55
69
84
C7
O
—
SEG27
58
72
87
B6
O
—
SEG28
37
47
57
H10
O
—
SEG29
23
29
34
L5
O
—
SEG30
22
28
33
L4
O
—
SEG31
21
27
32
K4
O
—
SEG32
—
4
6
D1
O
—
SEG33
—
5
8
E2
O
—
—
13
18
G1
O
—
SEG34
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
DS30009996G-page 26
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
SEG35
—
14
19
G2
O
—
SEG36
—
23
28
L2
O
—
SEG37
—
24
29
K3
O
—
SEG38
—
37
47
L9
O
—
SEG39
—
38
48
K9
O
—
SEG40
—
42
52
K11
O
—
SEG41
—
43
53
J10
O
—
SEG42
—
52
66
E11
O
—
SEG43
—
53
67
E8
O
—
SEG44
—
64
79
A9
O
—
SEG45
—
65
80
D8
O
—
SEG46
—
74
89
E6
O
—
SEG47
36
46
56
J11
O
—
SEG48
59
73
88
A6
O
—
SEG49
—
—
17
G3
O
—
SEG50
—
75
90
A5
O
—
SEG51
—
—
1
B2
O
—
SEG52
—
—
7
E4
O
—
SEG53
—
—
9
E1
O
—
SEG54
—
—
39
L6
O
—
SEG55
—
—
40
K6
O
—
SEG56
—
—
58
H11
O
—
SEG57
—
—
59
G10
O
—
SEG58
—
—
91
C5
O
—
SEG59
—
—
92
B5
O
—
SEG60
—
—
95
C4
O
—
—
SEG61
—
—
96
C3
O
SEG62
—
—
97
A3
O
—
SEG63
—
—
100
A1
O
—
SOSCI
47
59
73
C10
I
ANA
Description
LCD Driver Segment Outputs.
Secondary Oscillator/Timer1 Clock Input.
SOSCO
48
60
74
B11
O
ANA
Secondary Oscillator/Timer1 Clock Output.
TCK
27
33
38
J6
I
ST
JTAG Test Clock/Programming Clock Input.
TDI
28
34
60
G11
I
ST
JTAG Test Data/Programming Data Input.
TDO
24
14
61
G9
O
—
JTAG Test Data Output.
23
13
17
G3
I
ST
JTAG Test Mode Select Input.
TMS
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
2010-2014 Microchip Technology Inc.
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
DS30009996G-page 27
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locater
Pin
Function
64-Pin
TQFP
80-Pin
TQFP
100-Pin
TQFP
121-Pin
BGA
I/O
Input
Buffer
VBAT
57
71
86
A7
P
—
Backup Battery.
VCAP
56
70
85
B7
P
—
External Filter Capacitor Connection (regulator
enabled).
VDD
10, 26,
38
12, 32,
48
2, 16,
37, 46,
62
C2, F8,
G5, H6,
K8
P
—
Positive Supply for Peripheral Digital Logic and I/O
Pins.
5
7
11
F4
I
ANA
VLCAP1
Description
LCD Drive Charge Pump Capacitor Inputs.
VLCAP2
6
8
12
F2
I
ANA
VREF+
—
24
29
K3
I
ANA
Comparator/ADC Reference Voltage (low) Input
(default).
VREF-
—
23
28
L2
I
ANA
Comparator/ADC Reference Voltage (high) Input
(default).
9, 25, 41
11, 31,
51
15, 36,
45, 65,
75
B10, F5,
F10, G6,
G7
P
—
Vss
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
DS30009996G-page 28
Ground Reference for Logic and I/O Pins.
ST = Schmitt Trigger input buffer
I2C™ = I2C/SMBus input buffer
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
C2(2)
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• VCAP pin
(see Section 2.4 “Voltage Regulator Pin (VCAP)”)
VSS
VDD
MCLR
VCAP
C1
C7(1)
PIC24FJXXX
VSS
VDD
VDD
VSS
C3(2)
C6(2)
VSS
The following pins must always be connected:
R1
R2
VDD
Getting started with the PIC24FJ128GA310 family
family of 16-bit microcontrollers requires attention to a
minimal set of device pin connections before
proceeding with development.
VDD
AVSS
Basic Connection Requirements
AVDD
2.1
C4(2)
C5(2)
These pins must also be connected if they are being
used in the end application:
Key (all values are recommendations):
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
C7: 10 F, 6.3V or greater, tantalum or ceramic
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for analog modules is implemented
Note:
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
C1 through C6: 0.1 F, 20V ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1:
2:
See Section 2.4 “Voltage Regulator Pin
(VCAP)” for details on selecting the proper
capacitor for Vcap.
The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
The minimum mandatory connections are shown in
Figure 2-1.
2010-2014 Microchip Technology Inc.
DS30009996G-page 29
PIC24FJ128GA310 FAMILY
2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including microcontrollers to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
DS30009996G-page 30
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: device Reset, and device programming
and debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R1
R2
JP
MCLR
PIC24FJXXX
C1
Note 1:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin VIH and VIL specifications are met.
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
2.4
FIGURE 2-3:
Voltage Regulator Pin (VCAP)
A low-ESR (< 5Ω) capacitor is required on the VCAP pin
to stabilize the output voltage of the on-chip voltage
regulator. The VCAP pin must not be connected to VDD
and must use a capacitor of 10 µF connected to ground.
The type can be ceramic or tantalum. Suitable examples
of capacitors are shown in Table 2-1. Capacitors with
equivalent specification can be used.
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
10
ESR ()
1
The placement of this capacitor should be close to
VCAP. It is recommended that the trace length not
exceed 0.25 inch (6 mm). Refer to Section 32.0
“Electrical
Characteristics”
for
additional
information.
0.1
0.01
0.001
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
0.01
0.1
1
10
100
Frequency (MHz)
1000 10,000
Note: Typical data measurement at +25°C, 0V DC bias.
Refer to Section 29.2 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator.
.
TABLE 2-1:
SUITABLE CAPACITOR EQUIVALENTS
Make
Part #
Nominal
Capacitance
Base Tolerance
Rated Voltage
Temp. Range
TDK
C3216X7R1C106K
10 µF
±10%
16V
-55 to +125ºC
TDK
C3216X5R1C106K
10 µF
±10%
16V
-55 to +85ºC
Panasonic
ECJ-3YX1C106K
10 µF
±10%
16V
-55 to +125ºC
Panasonic
ECJ-4YB1C106K
10 µF
±10%
16V
-55 to +85ºC
Murata
GRM32DR71C106KA01L
10 µF
±10%
16V
-55 to +125ºC
Murata
GRM31CR61C106KC31L
10 µF
±10%
16V
-55 to +85ºC
2010-2014 Microchip Technology Inc.
DS30009996G-page 31
PIC24FJ128GA310 FAMILY
CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer’s data
sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 F nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very significant, but is often overlooked or is not always
documented.
Typical DC bias voltage vs. capacitance graph for X7R
type capacitors is shown in Figure 2-4.
FIGURE 2-4:
Capacitance Change (%)
2.4.1
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
10
0
-10
16V Capacitor
-20
-30
-40
10V Capacitor
-50
-60
-70
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DC Bias Voltage (VDC)
When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at
16V for the 2.5V or 1.8V core voltage. Suggested
capacitors are shown in Table 2-1.
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming (ICSP) and debugging purposes.
It is recommended to keep the trace length between
the ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is
recommended, with the value in the range of a few tens
of Ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin Voltage Input High
(VIH) and Voltage Input Low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGECx/PGEDx pins),
programmed into the device, matches the physical
connections for the ICSP to the Microchip
debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 30.0 “Development Support”.
DS30009996G-page 32
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
2.6
External Oscillator Pins
FIGURE 2-5:
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency
secondary
oscillator
(refer to
Section 9.0 “Oscillator Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Single-Sided and In-Line Layouts:
Copper Pour
(tied to ground)
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
Primary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
OSCI
C1
`
OSCO
GND
C2
`
SOSCO
SOSC I
Secondary
Oscillator
Crystal
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times
and other similar noise).
SUGGESTED
PLACEMENT OF THE
OSCILLATOR CIRCUIT
`
Sec Oscillator: C1
Sec Oscillator: C2
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
OSCO
C2
Oscillator
Crystal
GND
C1
OSCI
DEVICE PINS
2010-2014 Microchip Technology Inc.
DS30009996G-page 33
PIC24FJ128GA310 FAMILY
2.7
Configuration of Analog and
Digital Pins During ICSP
Operations
If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the ADC input pins
(ANx) as “digital” pins. Depending on the particular
device, this is done by setting all bits in the ADnPCFG
register(s), or clearing all bit in the ANSx registers.
All PIC24F devices will have either one or more
ADxPCFG registers or several ANSx registers (one for
each port); no device will have both. Refer to
Section 11.2 “Configuring Analog Port Pins
(ANSx)” for more specific information.
The bits in these registers that correspond to the ADC
pins that initialized the emulator must not be changed
by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.
If your application needs to use certain ADC pins as
analog input pins during the debug session, the user
application must modify the appropriate bits during
initialization of the ADC module, as follows:
• For devices with an ADxPCFG register, clear the
bits corresponding to the pin(s) to be configured
as analog. Do not change any other bits, particularly those corresponding to the PGECx/PGEDx
pair, at any time.
• For devices with ANSx registers, set the bits
corresponding to the pin(s) to be configured as
analog. Do not change any other bits, particularly
those corresponding to the PGECx/PGEDx pair,
at any time.
When a Microchip debugger/emulator is used as a
programmer, the user application firmware must
correctly configure the ADxPCFG or ANSx registers.
Automatic initialization of these registers is only done
during debugger operation. Failure to correctly
configure the register(s) will result in all ADC pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
2.8
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
DS30009996G-page 34
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
3.0
Note:
CPU
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“CPU with Extended Data Space (EDS)”
(DS39732) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEAT instructions, which are interruptible
at any point.
PIC24F devices have sixteen, 16-bit Working registers
in the programmer’s model. Each of the Working
registers can act as a data, address or address offset
register. The 16th Working register (W15) operates as
a Software Stack Pointer for interrupts and calls.
The lower 32 Kbytes of the Data Space can be
accessed linearly. The upper 32 Kbytes of the Data
Space are referred to as Extended Data Space (EDS)
to which the extended data RAM, EPMP memory
space or program memory can be mapped.
The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
2010-2014 Microchip Technology Inc.
The core supports Inherent (no operand), Relative,
Literal and Memory Direct Addressing modes, along
with three other groups of addressing modes. All
modes support Register Direct and various Register
Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a Working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported,
allowing trinary operations (that is, A + B = C) to be
executed in a single cycle.
A high-speed, 17-bit x 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
Signed, Unsigned and Mixed mode, 16-bit x 16-bit or
8-bit x 8-bit, integer multiplication. All multiply
instructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEAT instruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or
16-bit), divided by 16-bit, integer signed and unsigned
division. All divide operations require 19 cycles to
complete but are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with up
to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to
one of seven priority levels.
A block diagram of the CPU is shown in Figure 3-1.
3.1
Programmer’s Model
The programmer’s model for the PIC24F is shown in
Figure 3-2. All registers in the programmer’s model are
memory-mapped and can be manipulated directly by
instructions. A description of each register is provided
in Table 3-1. All registers associated with the
programmer’s model are memory-mapped.
DS30009996G-page 35
PIC24FJ128GA310 FAMILY
FIGURE 3-1:
PIC24F CPU CORE BLOCK DIAGRAM
EDS and Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
8
16
16
Data Latch
23
Data RAM
Up to 0x7FFF
PCH
PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
Address
Latch
23
16
RAGU
WAGU
Address Latch
EA MUX
Address Bus
Data Latch
ROM Latch
24
16
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
Hardware
Multiplier
Divide
Support
16
Literal Data
Program Memory/
Extended Data
Space
16
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
TABLE 3-1:
CPU CORE REGISTERS
Register(s) Name
W0 through W15
PC
SR
SPLIM
TBLPAG
RCOUNT
CORCON
DISICNT
DSRPAG
DSWPAG
DS30009996G-page 36
Description
Working Register Array
23-Bit Program Counter
ALU STATUS Register
Stack Pointer Limit Value Register
Table Memory Page Address Register
Repeat Loop Counter Register
CPU Control Register
Disable Interrupt Count Register
Data Space Read Page Register
Data Space Write Page Register
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 3-2:
PROGRAMMER’S MODEL
15
Divider Working Registers
0
W0 (WREG)
W1
W2
Multiplier Registers
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
Frame Pointer
W15
Stack Pointer
0
SPLIM
0
22
0
0
PC
7
0
TBLPAG
9
Program Counter
Table Memory Page
Address Register
0
Data Space Read Page Register
DSRPAG
8
0
Data Space Write Page Register
DSWPAG
15
0
RCOUNT
15
Stack Pointer Limit
Value Register
SRH
SRL
Repeat Loop Counter
Register
0
— — — — — — — DC 2 IPL
1 0 RA N OV Z C
ALU STATUS Register (SR)
0
15
— — — — — — — — — — — — IPL3 ———
CPU Control Register (CORCON)
13
0
DISICNT
Disable Interrupt Count Register
Registers or bits are shadowed for PUSH.S and POP.S instructions.
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3.2
CPU Control Registers
REGISTER 3-1:
SR: ALU STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
DC
bit 15
bit 8
R/W-0(1)
IPL2
R/W-0(1)
(2)
(2)
IPL1
R/W-0(1)
R-0
R/W-0
R/W-0
R/W-0,
R/W-0
IPL0(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
DC: ALU Half Carry/Borrow bit
1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry out from the 4th or 8th low-order bit of the result has occurred
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress
bit 3
N: ALU Negative bit
1 = Result was negative
0 = Result was not negative (zero or positive)
bit 2
OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1
Z: ALU Zero bit
1 = An operation, which affects the Z bit, has set it at some time in the past
0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result)
bit 0
C: ALU Carry/Borrow bit
1 = A carry out from the Most Significant bit of the result occurred
0 = No carry out from the Most Significant bit of the result occurred
Note 1:
2:
The IPL Status bits are read-only when NSTDIS (INTCON1) = 1.
The IPL Status bits are concatenated with the IPL3 (CORCON) bit to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
DS30009996G-page 38
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 3-2:
CORCON: CPU CORE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0
r-1
U-0
U-0
—
—
—
—
IPL3(1)
r
—
—
bit 7
bit 0
Legend:
C = Clearable bit
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
Unimplemented: Read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2
Reserved: Read as ‘1’
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level;
see Register 3-1 for bit description.
2010-2014 Microchip Technology Inc.
DS30009996G-page 39
PIC24FJ128GA310 FAMILY
3.3
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
for 16-bit divisor division.
3.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
1.
2.
3.
4.
5.
6.
7.
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
TABLE 3-2:
3.3.2
DIVIDER
The divide block supports signed and unsigned integer
divide operations with the following data sizes:
1.
2.
3.
4.
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.3.3
MULTI-BIT SHIFT SUPPORT
The PIC24F ALU supports both single bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support Register Direct
Addressing for both the operand source and result
destination.
A full summary of instructions that use the shift
operation is provided in Table 3-2.
INSTRUCTIONS THAT USE THE SINGLE BIT AND MULTI-BIT SHIFT OPERATION
Instruction
Description
ASR
Arithmetic shift right source register by one or more bits.
SL
Shift left source register by one or more bits.
LSR
Logical shift right source register by one or more bits.
DS30009996G-page 40
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
4.0
MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory
spaces and buses. This architecture also allows direct
access of program memory from the Data Space during
code execution.
4.1
Program Memory Space
The program address memory space of the
PIC24FJ128GA310 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
FIGURE 4-1:
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ128GA310 family of
devices are shown in Figure 4-1.
PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES
PIC24FJ64GA3XX
PIC24F128GA3XX
GOTO Instruction
Reset Address
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
Alternate Vector Table
Alternate Vector Table
User Flash
Program Memory
(22K instructions)
Flash Config Words
User Memory Space
from either the 23-bit Program Counter (PC) during program execution, or from table operation or Data Space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User Flash
Program Memory
(44K instructions)
Flash Config Words
Unimplemented
Read ‘0’
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
00ABFEh
00AC00h
0157FEh
015800h
Unimplemented
Read ‘0’
Configuration Memory Space
7FFFFEh
800000h
Reserved
Reserved
Device Config Registers
Device Config Registers
Reserved
Reserved
DEVID (2)
Note:
F7FFFEh
F80000h
F8000Eh
F80010h
FEFFFEh
FF0000h
DEVID (2)
FFFFFEh
Memory areas are not shown to scale.
2010-2014 Microchip Technology Inc.
DS30009996G-page 41
PIC24FJ128GA310 FAMILY
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.3
In PIC24FJ128GA310 family devices, the top four words
of on-chip program memory are reserved for configuration information. On device Reset, the configuration
information is copied into the appropriate Configuration
register. The addresses of the Flash Configuration Word
for devices in the PIC24FJ128GA310 family are shown
in Table 4-1. Their location in the memory map is shown
with the other memory vectors in Figure 4-1.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
The Configuration Words in program memory are a
compact format. The actual Configuration bits are
mapped in several different registers in the configuration
memory space. Their order in the Flash Configuration
Words does not reflect a corresponding arrangement in
the configuration space. Additional details on the device
Configuration Words are provided in Section 29.0
“Special Features”.
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2
HARD MEMORY VECTORS
TABLE 4-1:
All PIC24F devices reserve the addresses between
000000h and 000200h for hard-coded program execution vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h with
the actual address for the start of code at 000002h.
msw
Address
Configuration Word
Addresses
PIC24FJ64GA3XX
22,016
00ABF8h:00ABFEh
PIC24FJ128GA3XX
44,032
0157F8h:0157FEh
least significant word
most significant word
16
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS30009996G-page 42
Program
Memory
(Words)
PROGRAM MEMORY ORGANIZATION
23
0x000001
0x000003
0x000005
0x000007
FLASH CONFIGURATION
WORDS FOR
PIC24FJ128GA310 FAMILY
DEVICES
Device
PIC24F devices also have two interrupt vector tables,
located from 000004h to 0000FFh and 000100h to
0001FFh. These vector tables allow each of the many
device interrupt sources to be handled by separate
ISRs. A more detailed discussion of the interrupt vector
tables is provided in Section 8.1 “Interrupt Vector
Table”.
FIGURE 4-2:
FLASH CONFIGURATION WORDS
Instruction Width
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
4.2
Note:
The upper half of data memory address space (8000h to
FFFFh) is used as a window into the Extended Data
Space (EDS). This allows the microcontroller to directly
access a greater range of data beyond the standard
16-bit address range. EDS is discussed in detail in
Section 4.2.5 “Extended Data Space (EDS)”.
Data Memory Space
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Data Memory with Extended Data
Space (EDS)” (DS39733) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
The lower half of DS is compatible with previous PIC24F
microcontrollers without EDS. All PIC24FJ128GA310
family devices implement 8 Kbytes of data RAM in the
lower half of DS, from 0800h to 27FFh.
The PIC24F core has a 16-bit-wide data memory space,
addressable as a single linear range. The Data Space is
accessed using two Address Generation Units (AGUs),
one each for read and write operations. The Data Space
memory map is shown in Figure 4-3.
The 16-bit wide data addresses in the data memory
space point to bytes within the Data Space (DS). This
gives a DS address range of 64 Kbytes or 32K words.
The lower half (0000h to 7FFFh) is used for
implemented (on-chip) memory addresses.
FIGURE 4-3:
DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned
in data memory and registers as 16-bit words, but all
Data Space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
DATA SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES
MSB
Address
MSB
0001h
1FFFh
2001h
LSB
SFR Space
07FFh
0801h
Lower 32 Kbytes
Data Space
4.2.1
8 Kbytes Data RAM
2801h(1)
LSB
Address
0000h
07FEh
0800h
SFR
Space
Near
Data Space
1FFEh
2000h
2800h
EDS Page 0x1
(32 Kbytes)
Unimplemented
EDS Page 0x2
Internal Extended
Data RAM (66 Kbytes)
(32 Kbytes)
7FFFh
8001h
7FFEh
8000h
EDS Page 0x3 (2 Kbytes)
EDS Page 0x4
EDS Window
Upper 32 Kbytes
Data Space
EDS Page 0x1FF
EDS Page 0x200
EDS Page 0x2FF
FFFFh
FFFEh
EDS Page 0x300
EDS Page 0x3FF
Note:
EPMP Memory Space
Program Space Visibility
Area to Access Lower
Word of Program Memory
Program Space Visibility
Area to Access Upper
Word of Program Memory
Memory areas not shown to scale.
2010-2014 Microchip Technology Inc.
DS30009996G-page 43
PIC24FJ128GA310 FAMILY
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
A Sign-Extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
To maintain backward compatibility with PIC® MCUs and
improve Data Space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
EA calculations are internally scaled to step through
word-aligned memory. For example, the core recognizes
that Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte operations
and Ws + 2 for word operations.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the Data Space is addressable indirectly.
Additionally, the whole Data Space is addressable
using MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.
Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel, byte-wide
entities with shared (word) address decode but
separate write lines. Data byte writes only write to the
corresponding side of the array or register which
matches the byte address.
4.2.4
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine
state prior to execution of the address Fault.
SPECIAL FUNCTION REGISTER
(SFR) SPACE
The first 2 Kbytes of the Near Data Space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
SFRs are distributed among the modules that they control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A diagram of the SFR space,
showing where the SFRs are actually implemented, is
shown in Table 4-2. Each implemented area indicates
a 32-byte region where at least one address is implemented as an SFR. A complete list of implemented
SFRs, including their addresses, is shown in Tables 4-3
through 4-34.
All byte loads into any W register are loaded into the
LSB. The Most Significant Byte (MSB) is not modified.
TABLE 4-2:
NEAR DATA SPACE
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address
xx00
xx20
I2C™
SPI/UART
ADC/CTMU
300h
—
—
xxA0
—
—
500h
—
—
—
—
600h
EPMP
RTC/CMP
CRC
—
700h
—
—
System
NVM/PMD
xxE0
—
Compare
—
—
—
xxC0
Interrupts
—
Capture
UART
xx80
ICN
Timers
100h
400h
xx60
Core
000h
200h
xx40
—
UART
I/O
DMA
—
—
—
LCD
ANA
—
—
LCD
PPS
—
—
—
—
—
Legend: — = No implemented SFRs in this block
DS30009996G-page 44
2010-2014 Microchip Technology Inc.
2010-2014 Microchip Technology Inc.
TABLE 4-3:
File Name
Addr
CPU CORE REGISTERS MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
WREG0
0000
Working Register 0
0000
WREG1
0002
Working Register 1
0000
WREG2
0004
Working Register 2
0000
WREG3
0006
Working Register 3
0000
WREG4
0008
Working Register 4
0000
WREG5
000A
Working Register 5
0000
WREG6
000C
Working Register 6
0000
WREG7
000E
Working Register 7
0000
WREG8
0010
Working Register 8
0000
WREG9
0012
Working Register 9
0000
WREG10
0014
Working Register 10
0000
WREG11
0016
Working Register 11
0000
0018
Working Register 12
0000
001A
Working Register 13
0000
WREG14
001C
Working Register 14
0000
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Value Register
xxxx
PCL
002E
Program Counter Low Word Register
0000
PCH
0030
—
—
—
—
—
—
DSRPAG
0032
—
—
—
—
—
—
DSWPAG
0034
—
—
—
—
—
—
—
—
—
Program Counter High Word Register
0000
Extended Data Space Read Page Address Register
0001
Extended Data Space Write Page Address Register
0001
RCOUNT
0036
SR
0042
—
—
—
—
—
—
—
Repeat Loop Counter Register
DC
IPL2
IPL1
IPL0
RA
N
OV
Z
C
CORCON
0044
—
—
—
—
—
—
—
—
—
—
—
—
IPL3
r
—
—
DISICNT
0052
—
—
TBLPAG
0054
—
—
xxxx
Disable Interrupts Counter Register
—
—
—
—
—
—
Legend: — = unimplemented, read as ‘0’; r = reserved, do not modify. Reset values are shown in hexadecimal.
Table Memory Page Address Register
0000
0004
xxxx
0000
DS30009996G-page 45
PIC24FJ128GA310 FAMILY
WREG12
WREG13
ICN REGISTER MAP
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
CNPD1
0056
CN15PDE
CN14PDE
CN13PDE
CNPD2
0058
CN31PDE
CN30PDE
CN29PDE
CNPD3
005A CN47PDE(1) CN46PDE(2) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(2) CN39PDE(2) CN38PDE(2) CN37PDE(2) CN36PDE(2) CN35PDE(2) CN34PDE(2) CN33PDE(2)
CNPD4
005C
CNPD5
005E CN79PDE(2) CN78PDE(1) CN77PDE(1) CN76PDE(2) CN75PDE(2) CN74PDE(1)
CNPD6
0060
—
—
—
—
—
CNEN1
0062
CN15IE
CN14IE
CN13IE
CN12IE
CNEN2
0064
CN31IE
CN30IE
CN29IE
CNEN3
0066
CN47IE(1)
CN46IE(1)
CNEN4
0068
CN63IE
CNEN5
006A
CNEN6
CN12PDE
CN11PDE
CN10PDE
CN9PDE
CN8PDE
CN7PDE
CN6PDE
CN28PDE
CN27PDE
CN26PDE
CN25PDE
CN24PDE
CN23PDE
CN22PDE
Bit 5
Bit 4
Bit 3
CN5PDE
CN4PDE
CN3PDE
CN21PDE(1) CN20PDE(1) CN19PDE(1)
Bit 1
Bit 0
All
Resets
CN2PDE
—
—
0000
CN18PDE
CN17PDE
CN16PDE
0000
CN32PDE
0000
CN49PDE
CN48PDE(2)
0000
CN65PDE
CN64PDE
0000
CN73PDE
CN72PDE
CN71PDE
CN70PDE
CN69PDE
CN68PDE
CN67PDE(1) CN66PDE(1)
—
—
—
—
—
—
CN84PDE
CN83PDE(1) CN82PDE(2) CN81PDE(2) CN80PDE(2)
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
—
—
0000
CN28IE
CN27IE
CN26IE
CN25IE
CN24IE
CN23IE
CN22IE
CN21IE(1)
CN20IE(1)
CN19IE(1)
CN18IE
CN17IE
CN16IE
0000
CN45IE(1)
CN44IE(1)
CN43IE(1)
CN42IE(1)
CN41IE(1)
CN40IE(2)
CN39IE(2)
CN38IE(2)
CN37IE(2)
CN36IE(2)
CN35IE(2)
CN34IE(2)
CN33IE(2)
CN32IE
0000
CN62IE
CN61IE
CN60IE
CN59IE
CN58IE
CN57IE
CN56IE
CN55IE
CN54IE
CN53IE
CN52IE
CN51IE
CN50IE
CN49IE
CN48IE(2)
0000
CN79IE(2)
CN78IE(1)
CN77IE(1)
CN76IE(2)
CN75IE(2)
CN74IE(1)
CN73IE
CN72IE
CN71IE
CN70IE
CN69IE
CN68IE
CN67IE(1)
CN66IE(1)
CN65IE
CN64IE
0000
006C
—
—
—
—
—
—
—
—
—
—
—
CN84IE
CN83IE(1)
CN82IE(2)
CN81IE(2)
CN80IE(2)
0000
CNPU1
006E
CN15PUE
CN14PUE
CN13PUE
CN12PUE
CN11PUE
CN10PUE
CN9PUE
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
—
—
0000
CNPU2
0070
CN31PUE
CN30PUE
CN29PUE
CN28PUE
CN27PUE
CN26PUE
CN25PUE
CN24PUE
CN23PUE
CN22PUE
CN18PUE
CN17PUE
CN16PUE
0000
CNPU3
0072 CN47PUE(1) CN46PUE(1) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(2) CN39PUE(2) CN38PUE(2) CN37PUE(2) CN36PUE(2) CN35PUE(2) CN34PUE(2) CN33PUE(2)
CN32PUE
0000
CNPU4
0074
CN49PUE
CN48PUE(2)
0000
CNPU5
0076 CN79PUE(2) CN78PUE(1) CN77PUE(1) CN76PUE(2) CN75PUE(2) CN74PUE(1)
CN65PUE
CN64PUE
0000
CNPU6
0078
—
—
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are unimplemented in 64-pin devices, read as ‘0’.
These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
CN58PUE
—
CN51PDE
Bit 2
CN52PDE
CN59PUE
CN58PDE
Bit 6
CN53PDE
CN60PUE
CN59PDE
Bit 7
CN54PDE
CN61PUE
CN60PDE
Bit 8
CN55PDE
CN62PUE
CN61PDE
Bit 9
CN56PDE
CN63PUE
CN62PDE
Bit 10
CN57PDE
Legend:
Note 1:
2:
CN63PDE
Bit 11
CN21PUE(1) CN20PUE(1) CN19PUE(1)
CN51PUE
CN50PDE
CN57PUE
CN56PUE
CN55PUE
CN54PUE
CN53PUE
CN52PUE
CN50PUE
CN73PUE
CN72PUE
CN71PUE
CN70PUE
CN69PUE
CN68PUE
CN67PUE(1) CN66PUE(1)
—
—
—
—
—
CN84PUE
CN83PUE(1) CN82PUE(2) CN81PUE(2) CN80PUE(2)
0000
0000
PIC24FJ128GA310 FAMILY
DS30009996G-page 46
TABLE 4-4:
2010-2014 Microchip Technology Inc.
2010-2014 Microchip Technology Inc.
TABLE 4-5:
File
Name
Addr
INTERRUPT CONTROLLER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
MATHERR ADDRERR
Bit 2
Bit 1
Bit 0
All
Resets
INTCON1 0080
NSTDIS
—
—
—
—
—
—
—
—
—
—
STKERR
OSCFAIL
—
0000
INTCON2 0082
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
0084
—
DMA1IF
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPF1IF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
—
IC7IF
—
INT1IF
CNIF
CMIF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
DMA4IF
PMPIF
—
OC7IF
OC6IF
OC5IF
IC6IF
IC5IF
IC4IF
IC3IF
DMA3IF
—
—
SPI2IF
SPF2IF
0000
IFS3
008A
—
RTCIF
DMA5IF
—
—
—
—
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
CTMUIF
—
—
—
—
HLVDIF
—
—
—
—
CRCIF
U2ERIF
U1ERIF
—
0000
IFS5
008E
—
—
—
—
—
—
U4TXIF
U4RXIF
U4ERIF
—
—
—
U3TXIF
U3RXIF
U3ERIF
—
0000
IFS6
0090
—
—
—
—
—
—
—
—
—
—
—
LCDIF
—
—
—
—
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
JTAGIF
—
—
—
—
—
0000
IEC0
0094
—
DMA1IE
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPF1IE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
—
IC7IE
—
INT1IE
CNIE
CMIE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
DMA4IE
PMPIE
—
OC7IE
OC6IE
OC5IE
IC6IE
IC5IE
IC4IE
IC3IE
DMA3IE
—
—
SPI2IE
SPF2IE
0000
IEC3
009A
—
RTCIE
DMA5IE
—
—
—
—
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
CTMUIE
—
—
—
—
HLVDIE
—
—
—
—
CRCIE
U2ERIE
U1ERIE
—
0000
IEC5
009E
—
—
—
—
—
—
U4TXIE
U4RXIE
U4ERIE
—
—
—
U3TXIE
U3RXIE
U3ERIE
—
0000
IEC6
00A0
—
—
—
—
—
—
—
—
—
—
—
LCDIE
—
—
—
—
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
JTAGIE
—
—
—
—
—
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2
DMA0IP1
DMA0IP0
4444
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPF1IP2
SPF1IP1
SPF1IP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
DMA1IP2
DMA1IP1
DMA1IP0
—
AD1IP2
AD1IP1
AD1IP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0444
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
CMIP2
CMIP1
CMIP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
IC7IP2
IC7IP1
IC7IP0
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0404
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2
DMA2IP1
DMA2IP0
4444
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPF2IP2
SPF2IP1
SPF2IP0
0044
IPC9
00B6
—
IC5IP2
IC5IP1
IC5IP0
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2
DMA3IP1
DMA3IP0
4444
IPC10
00B8
—
OC7IP2
OC7IP1
OC7IP0
—
OC6IP2
OC6IP1
OC6IP0
—
OC5IP2
OC5IP1
OC5IP0
—
IC6IP2
IC6IP1
IC6IP0
4444
IPC11
00BA
—
—
—
—
—
DMA4IP2
DMA4IP1
DMA4IP0
—
PMPIP2
PMPIP1
PMPIP0
—
—
—
—
0440
IPC12
00BC
—
—
—
—
—
MI2C2IP2 MI2C2IP1 MI2C2IP0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC15
00C2
—
—
—
—
—
RTCIP2
RTCIP1
RTCIP0
—
DMA5IP2
DMA5IP1
DMA5IP0
—
—
—
—
0440
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FJ128GA310 FAMILY
DS30009996G-page 47
IFS0
File
Name
INTERRUPT CONTROLLER REGISTER MAP (CONTINUED)
Bit 0
All
Resets
—
—
4440
HLVDIP1
HLVDIP0
0004
—
—
0040
—
—
—
4440
—
—
—
—
4000
U4TXIP0
—
U4RXIP2
U4RXIP1
U4RXIP0
0044
—
—
—
LCDIP2
LCDIP1
LCDIP0
0004
JTAGIP1
JTAGIP0
—
—
—
—
0040
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
IPC16
00C4
—
CRCIP2
CRCIP1
CRCIP0
—
U2ERIP2
U2ERIP1
U2ERIP0
—
U1ERIP2
U1ERIP1
U1ERIP0
—
—
IPC18
00C8
—
—
—
—
—
—
—
—
—
—
—
—
—
HLVDIP2
IPC19
00CA
—
—
—
—
—
—
—
—
—
CTMUIP2
CTMUIP1
CTMUIP0
—
—
IPC20
00CC
—
U3TXIP2
U3TXIP1
U3TXIP0
—
U3RXIP2
U3RXIP1
U3RXIP0
—
U3ERIP2
U3ERIP1
U3ERIP0
—
IPC21
00CE
—
U4ERIP2
U4ERIP1
U4ERIP0
—
—
—
—
—
—
—
—
IPC22
00D0
—
—
—
—
—
—
—
—
—
U4TXIP2
U4TXIP1
IPC25
00D6
—
—
—
—
—
—
—
—
—
—
IPC29
00DE
—
—
—
—
—
—
—
—
—
JTAGIP2
CPUIRQ
—
VHOLD
—
ILR3
ILR2
ILR1
ILR0
—
INTTREG 00E0
Bit 2
Bit 1
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6:
File Name
Addr
TIMER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TMR1
0100
Timer1 Register
PR1
0102
Timer1 Period Register
T1CON
0104
TON
—
TSIDL
—
—
—
TIECS1
TIECS0
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
FFFF
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
0000
TMR2
0106
Timer2 Register
0000
TMR3HLD
0108
Timer3 Holding Register (for 32-bit timer operations only)
0000
2010-2014 Microchip Technology Inc.
TMR3
010A
Timer3 Register
0000
PR2
010C
Timer2 Period Register
FFFF
PR3
010E
Timer3 Period Register
T2CON
0110
TON
—
TSIDL
—
—
—
—
T3CON
0112
TON
—
TSIDL
—
—
—
—
TMR4
0114
Timer4 Register
0000
TMR5HLD
0116
Timer5 Holding Register (for 32-bit operations only)
0000
FFFF
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
TMR5
0118
Timer5 Register
0000
PR4
011A
Timer4 Period Register
FFFF
PR5
011C
Timer5 Period Register
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T45
—
TCS
—
0000
T5CON
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
FFFF
PIC24FJ128GA310 FAMILY
DS30009996G-page 48
TABLE 4-5:
2010-2014 Microchip Technology Inc.
TABLE 4-7:
INPUT CAPTURE REGISTER MAP
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
IC1CON1
0140
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
IC1CON2
0142
—
—
—
—
—
—
—
IC32
IC1BUF
0144
Input Capture 1 Buffer Register
IC1TMR
0146
Timer Value 1 Register
IC2CON1
0148
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
—
ICI1
ICI0
IC2CON2
014A
—
—
—
—
—
—
—
IC32
ICTRIG
TRIGSTAT
—
IC2BUF
014C
Input Capture 2 Buffer Register
IC2TMR
014E
Timer Value 2 Register
IC3CON1
0150
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
—
ICI1
ICI0
IC3CON2
0152
—
—
—
—
—
—
—
IC32
ICTRIG
TRIGSTAT
—
IC3BUF
0154
Input Capture 3 Buffer Register
IC3TMR
0156
Timer Value 3 Register
IC4CON1
0158
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
—
ICI1
ICI0
IC4CON2
015A
—
—
—
—
—
—
—
IC32
ICTRIG
TRIGSTAT
—
IC4BUF
015C
Input Capture 4 Buffer Register
IC4TMR
015E
Timer Value 4 Register
IC5CON1
0160
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
—
ICI1
ICI0
IC5CON2
0162
—
—
—
—
—
—
—
IC32
ICTRIG
TRIGSTAT
—
IC5BUF
0164
Input Capture 5 Buffer Register
IC5TMR
0166
Timer Value 5 Register
IC6CON1
0168
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
—
ICI1
ICI0
IC6CON2
016A
—
—
—
—
—
—
—
IC32
ICTRIG
TRIGSTAT
—
IC6BUF
016C
Input Capture 6 Buffer Register
IC6TMR
016E
Timer Value 6 Register
IC7CON1
0170
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
—
ICI1
ICI0
IC7CON2
0172
—
—
—
—
—
—
—
IC32
ICTRIG
TRIGSTAT
—
IC7BUF
0174
Input Capture 7 Buffer Register
0000
IC7TMR
0176
Timer Value 7 Register
xxxx
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 7
Bit 6
Bit 5
—
ICI1
ICI0
ICTRIG
TRIGSTAT
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
000D
0000
xxxx
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
0000
xxxx
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
0000
xxxx
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
0000
xxxx
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
0000
xxxx
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
0000
xxxx
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
DS30009996G-page 49
PIC24FJ128GA310 FAMILY
Legend:
Bit 8
File Name
Addr
OUTPUT COMPARE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 8
Bit 7
Bit 6
ENFLT2
ENFLT1
ENFLT0
OCFLT2
DCB0
OC32
OCTRIG
TRIGSTAT
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
OCFLT1
OCFLT0
TRIGMODE
OCM2
OCM1
OCM0
0000
OCTRIS
SYNCSEL4
Bit 5
2010-2014 Microchip Technology Inc.
OC1CON1
0190
—
—
OCSIDL
OC1CON2
0192
FLTMD
FLTOUT
FLTTRIEN
OC1RS
0194
Output Compare 1 Secondary Register
0000
OC1R
0196
Output Compare 1 Register
0000
OC1TMR
0198
Timer Value 1 Register
OC2CON1
019A
—
—
OCSIDL
OC2CON2
019C
FLTMD
FLTOUT
FLTTRIEN
OC2RS
019E
Output Compare 2 Secondary Register
0000
OC2R
01A0
Output Compare 2 Register
0000
OC2TMR
01A2
Timer Value 2 Register
OC3CON1
01A4
—
—
OCSIDL
OC3CON2
01A6
FLTMD
FLTOUT
FLTTRIEN
OC3RS
01A8
Output Compare 3 Secondary Register
0000
OC3R
01AA
Output Compare 3 Register
0000
OC3TMR
01AC
Timer Value 3 Register
OC4CON1
01AE
—
—
OCSIDL
OC4CON2
01B0
FLTMD
FLTOUT
FLTTRIEN
OC4RS
01B2
Output Compare 4 Secondary Register
0000
OC4R
01B4
Output Compare 4 Register
0000
OC4TMR
01B6
Timer Value 4 Register
OC5CON1
01B8
—
—
OCSIDL
OC5CON2
01BA
FLTMD
FLTOUT
FLTTRIEN
OC5RS
01BC
Output Compare 5 Secondary Register
0000
OC5R
01BE
Output Compare 5 Register
0000
OC5TMR
01C0
Timer Value 5 Register
OC6CON1
01C2
—
—
OCSIDL
OC6CON2
01C4
FLTMD
FLTOUT
FLTTRIEN
OC6RS
01C6
Output Compare 6 Secondary Register
0000
OC6R
01C8
Output Compare 6 Register
0000
OC6TMR
01CA
Timer Value 6 Register
xxxx
Legend:
OCTSEL2 OCTSEL1 OCTSEL0
Bit 9
OCINV
—
DCB1
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
DCB1
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
DCB1
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
DCB1
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
DCB1
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
DCB1
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
000C
xxxx
ENFLT2
ENFLT1
ENFLT0
OCFLT2
OCFLT1
OCFLT0
DCB0
OC32
OCTRIG
TRIGSTAT
OCTRIS
SYNCSEL4
TRIGMODE
OCM2
OCM1
OCM0
SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
xxxx
ENFLT2
ENFLT1
ENFLT0
OCFLT2
OCFLT1
OCFLT0
DCB0
OC32
OCTRIG
TRIGSTAT
OCTRIS
SYNCSEL4
TRIGMODE
OCM2
OCM1
OCM0
SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
xxxx
ENFLT2
ENFLT1
ENFLT0
OCFLT2
OCFLT1
OCFLT0
DCB0
OC32
OCTRIG
TRIGSTAT
OCTRIS
SYNCSEL4
TRIGMODE
OCM2
OCM1
OCM0
SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
xxxx
ENFLT2
ENFLT1
ENFLT0
OCFLT1
OCFLT1
OCFLT0
DCB0
OC32
OCTRIG
TRIGSTAT
OCTRIS
SYNCSEL4
TRIGMODE
OCM2
OCM1
OCM0
SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
xxxx
ENFLT2
ENFLT1
ENFLT0
OCFLT2
OCFLT1
OCFLT0
DCB0
OC32
OCTRIG
TRIGSTAT
OCTRIS
SYNCSEL4
TRIGMODE
OCM2
OCM1
OCM0
SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
PIC24FJ128GA310 FAMILY
DS30009996G-page 50
TABLE 4-8:
2010-2014 Microchip Technology Inc.
TABLE 4-8:
File Name
OUTPUT COMPARE REGISTER MAP (CONTINUED)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
OC7CON1 01CC
—
—
OCSIDL
OC7CON2 01CE
FLTMD
FLTOUT
FLTTRIEN
Bit 11
Bit 10
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
DCB1
Bit 9
Bit 8
Bit 7
Bit 6
ENFLT2
ENFLT1
ENFLT0
OCFLT2
DCB0
OC32
OCTRIG
TRIGSTAT
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
OCFLT1
OCFLT0
TRIGMODE
OCM2
OCM1
OCM0
0000
OCTRIS
SYNCSEL4
Bit 5
SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
000C
OC7RS
01D0
Output Compare 7 Secondary Register
0000
OC7R
01D2
Output Compare 7 Register
0000
OC7TMR
01D4
Timer Value 7 Register
xxxx
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
I2C™ REGISTER MAP
TABLE 4-9:
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0200
—
—
—
—
—
—
—
—
I2C1 Receive Register
0000
0202
—
—
—
—
—
—
—
—
I2C1 Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
ACKSTAT TRSTAT
Baud Rate Generator Register
0000
I2C1ADD
020A
—
—
—
—
—
—
I2C1 Address Register
I2C1MSK
020C
—
—
—
—
—
—
I2C1 Address Mask Register
I2C2RCV
0210
—
—
—
—
—
—
—
—
I2C2TRN
0212
—
—
—
—
—
—
—
—
I2C2BRG
0214
—
—
—
—
—
—
—
I2C2CON
0216
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C2STAT
0218
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
ACKSTAT TRSTAT
0000
0000
I2C2 Receive Register
0000
I2C2 Transmit Register
00FF
Baud Rate Generator Register
0000
I2C2ADD
021A
—
—
—
—
—
—
I2C2 Address Register
0000
I2C2MSK
021C
—
—
—
—
—
—
I2C2 Address Mask Register
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS30009996G-page 51
PIC24FJ128GA310 FAMILY
I2C1RCV
I2C1TRN
File Name
Addr
UART REGISTER MAPS
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 0
All
Resets
PDSEL0
STSEL
0000
OERR
URXDA
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
RXINV
BRGH
PDSEL1
ADDEN
RIDLE
PERR
FERR
U1MODE
0220
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U1STA
0222
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U1TXREG
0224
—
—
—
—
—
—
—
UART1 Transmit Register
xxxx
U1RXREG
0226
—
—
—
—
—
—
—
UART1 Receive Register
0000
U1BRG
0228
U2MODE
0230
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U2STA
0232
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U2TXREG
0234
—
—
—
—
—
—
—
UART2 Transmit Register
xxxx
U2RXREG
0236
—
—
—
—
—
—
—
UART2 Receive Register
0000
U2BRG
0238
U3MODE
0250
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U3STA
0252
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U3TXREG
0254
—
—
—
—
—
—
—
UART3 Transmit Register
xxxx
U3RXREG
0256
—
—
—
—
—
—
—
UART3 Receive Register
0000
U3BRG
0258
U4MODE
02B0
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U4STA
02B2
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U4TXREG
02B4
—
—
—
—
—
—
—
UART4 Transmit Register
xxxx
U4RXREG
02B6
—
—
—
—
—
—
—
UART4 Receive Register
0000
U4BRG
02B8
URXISEL1 URXISEL0
Baud Rate Generator Prescaler Register
WAKE
LPBACK
URXISEL1 URXISEL0
0000
ABAUD
RXINV
BRGH
PDSEL1
PDSEL0
STSEL
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
Baud Rate Generator Prescaler Register
WAKE
LPBACK
URXISEL1 URXISEL0
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
LPBACK
URXISEL1 URXISEL0
Baud Rate Generator Prescaler Register
0000
0110
0000
ABAUD
RXINV
BRGH
PDSEL1
PDSEL0
STSEL
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
Baud Rate Generator Prescaler Register
WAKE
0110
0000
0110
0000
ABAUD
RXINV
BRGH
PDSEL1
PDSEL0
STSEL
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0000
0110
0000
PIC24FJ128GA310 FAMILY
DS30009996G-page 52
TABLE 4-10:
2010-2014 Microchip Technology Inc.
2010-2014 Microchip Technology Inc.
TABLE 4-11:
File Name
SPI REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
SPIBEC2 SPIBEC1 SPIBEC0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
SPI1CON2
0244
FRMEN
SPIFSD
SPIFPOL
—
—
—
—
—
—
—
—
—
—
—
SPIFE
SPIBEN
0000
SPI1BUF
0248
SPI2STAT
0260
SPIEN
—
SPISIDL
—
—
SPIRBF
0000
SPI1 Transmit and Receive Buffer
SPIBEC2 SPIBEC1 SPIBEC0
0000
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPI2CON1
0262
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
SPI2CON2
0264
FRMEN
SPIFSD
SPIFPOL
—
—
—
—
—
—
—
—
—
—
—
SPIFE
SPIBEN
0000
SPI2BUF
0268
SPI2 Transmit and Receive Buffer
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12:
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7(2)
Bit 6(2)
Bit 5(2)
Bit 4(2)
Bit 3(2)
Bit2(2)
Bit 1(2)
Bit 0(2)
All
Resets
TRISA
02C0
TRISA
—
—
—
TRISA
—
TRISA
C6FF
PORTA
02C2
RA
—
—
—
RA
—
RA
xxxx
LATA
02C4
LATA
—
—
—
LATA
—
LATA
xxxx
ODCA
02C6
ODA
—
—
—
ODA
—
ODA
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: PORTA and all associated bits are unimplemented in 64-pin devices and read as ‘0’.
2: These bits are also unimplemented in 80-pin devices, read as ‘0’.
TABLE 4-13:
File
Name
Addr
PORTB REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
DS30009996G-page 53
TRISB
02C8
TRISB
FFFF
PORTB
02CA
RB
xxxx
LATB
02CC
LATB
xxxx
ODCB
02CE
ODB
0000
Legend: Reset values are shown in hexadecimal.
PIC24FJ128GA310 FAMILY
File
Name
PORTA REGISTER MAP(1)
File
Name
PORTC REGISTER MAP
Addr
Bit 15
TRISC
02D0
TRISC15
PORTC
02D2
LATC
02D4
ODCC
02D6
Legend:
Note 1:
2:
3:
4:
5:
TRISC
—
901E
RC
—
xxxx
—
LATC16;
// Initialize PM Page Boundary SFR
offset = progAddr & 0xFFFF;
// Initialize lower word of address
__builtin_tblwtl(offset, 0x0000);
// Set base address of erase block
// with dummy latch write
NVMCON = 0x4042;
// Initialize NVMCON
asm("DISI #5");
// Block all interrupts with priority 16;
// Initialize PM Page Boundary SFR
offset = progAddr & 0xFFFF;
// Initialize lower word of address
//Perform TBLWT instructions to write latches
__builtin_tblwtl(offset, progDataL);
// Write to address low word
__builtin_tblwth(offset, progDataH);
// Write to upper byte
asm(“DISI #5”);
// Block interrupts with priority Control bits
(OSCCON)
DS30009996G-page 93
PIC24FJ128GA310 FAMILY
TABLE 7-3:
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type
POR
BOR
SYSRST Delay
System Clock
Delay
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
—
TLOCK
TOST
TOST + TLOCK
TFRC
TFRC + TLOCK
TLPRC
—
TLOCK
TOST
TOST + TLOCK
TFRC
TFRC + TLOCK
TLPRC
Clock Source
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
Notes
1, 2, 3
1, 2, 3, 5
1, 2, 3, 4, 8
1, 2, 3, 4, 5, 8
1, 2, 3, 6, 7
1, 2, 3, 5, 6
1, 2, 3, 6
2, 3
2, 3, 5
2, 3, 4, 8
2, 3, 4, 5, 8
2, 3, 6, 7
2, 3, 5, 6
2, 3, 6
Any Clock
TRST
—
3
MCLR
WDT
Any Clock
TRST
—
3
Software
Any clock
TRST
—
3
Illegal Opcode Any Clock
TRST
—
3
Uninitialized W Any Clock
TRST
—
3
Trap Conflict
Any Clock
TRST
—
3
Note 1: TPOR = Power-on Reset delay (10 s nominal).
2: TSTARTUP = TVREG (10 s nominal when VREGS = 1 and when VREGS = 0; depends upon
WDTWIN bits setting).
3: TRST = Internal State Reset time (2 s nominal).
4: TOST = Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing
the oscillator clock to the system.
5: TLOCK = PLL lock time.
6: TFRC and TLPRC = RC oscillator start-up times.
7: If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC
so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid. It switches to the
primary oscillator after its respective clock delay.
8: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
7.4.1
POR AND LONG OSCILLATOR
START-UP TIMES
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
DS30009996G-page 94
The device will not begin to execute code until a valid
clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
7.4.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
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PIC24FJ128GA310 FAMILY
8.0
Note:
INTERRUPT CONTROLLER
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference source. For more information, refer
to “Interrupts” (DS39707) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the PIC24F CPU. It has the following
features:
•
•
•
•
Up to 8 processor exceptions and software traps
Seven user-selectable priority levels
Interrupt Vector Table (IVT) with up to 118 vectors
Unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
8.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 8-1.
The IVT resides in program memory, starting at location,
000004h. The IVT contains 126 vectors, consisting of
8 non-maskable trap vectors, plus up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt vector location is the starting address of the associated
Interrupt Service Routine (ISR).
8.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 8-1. The ALTIVT
(INTCON2) control bit provides access to the
AIVT. If the ALTIVT bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
8.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset, which forces the PC to zero. The microcontroller then begins program execution at location,
000000h. The user programs a GOTO instruction at the
Reset address, which redirects program execution to
the appropriate start-up routine.
Note:
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt associated with Vector 0 will take priority over interrupts at
any other vector address.
PIC24FJ128GA310
family
devices
implement
non-maskable traps and unique interrupts. These are
summarized in Table 8-1 and Table 8-2.
2010-2014 Microchip Technology Inc.
DS30009996G-page 95
PIC24FJ128GA310 FAMILY
FIGURE 8-1:
PIC24F INTERRUPT VECTOR TABLE
Decreasing Natural Order Priority
Reset – GOTO Instruction
Reset – GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
—
—
—
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
—
—
Interrupt Vector 116
Interrupt Vector 117
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
—
—
—
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
—
—
Interrupt Vector 116
Interrupt Vector 117
Start of Code
000014h
00007Ch
00007Eh
000080h
Interrupt Vector Table (IVT)(1)
0000FCh
0000FEh
000100h
000102h
000114h
00017Ch
00017Eh
000180h
Alternate Interrupt Vector Table (AIVT)(1)
0001FEh
000200h
See Table 8-2 for the interrupt vector list.
Note 1:
TABLE 8-1:
000000h
000002h
000004h
TRAP VECTOR DETAILS
Vector Number
IVT Address
AIVT Address
0
1
2
3
4
5
6
7
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000104h
000106h
000108h
00010Ah
00010Ch
00010Eh
000110h
000112h
DS30009996G-page 96
Trap Source
Reserved
Oscillator Failure
Address Error
Stack Error
Math Error
Reserved
Reserved
Reserved
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TABLE 8-2:
IMPLEMENTED INTERRUPT VECTORS
Interrupt Bit Locations
Vector
Number
IVT
Address
AIVT
Address
Flag
Enable
ADC1 Conversion Done
13
00002Eh
00012Eh
IFS0
IEC0
IPC3
Comparator Event
18
000038h
000138h
IFS1
IEC1
IPC4
CRC Generator
67
00009Ah
00019Ah
IFS4
IEC4
IPC16
CTMU Event
77
0000AEh
0001AEh
IFS4
IEC4
IPC19
DMA Channel 0
4
00001Ch
00011Ch
IFS0
IEC0
IPC1
DMA Channel 1
14
000030h
000130h
IFS0
IEC0
IPC3
DMA Channel 2
24
000044h
000144h
IFS1
IEC1
IPC6
DMA Channel 3
36
00005Ch
00015Ch
IFS2
IEC2
IPC9
DMA Channel 4
46
000070h
000170h
IFS2
IEC2
IPC11
DMA Channel 5
61
00008Eh
00018Eh
IFS3
IEC3
IPC15
Interrupt Source
Priority
External Interrupt 0
0
000014h
000114h
IFS0
IEC0
IPC0
External Interrupt 1
20
00003Ch
00013Ch
IFS1
IEC1
IPC5
External Interrupt 2
29
00004Eh
00014Eh
IFS1
IEC1
IPC7
External Interrupt 3
53
00007Eh
00017Eh
IFS3
IEC3
IPC13
External Interrupt 4
54
000080h
000180h
IFS3
IEC3
IPC13
I2C1 Master Event
17
000036h
000136h
IFS1
IEC1
IPC4
I2C1 Slave Event
16
000034h
000134h
IFS1
IEC1
IPC4
I2C2 Master Event
50
000078h
000178h
IFS3
IEC3
IPC12
I2C2 Slave Event
49
000076h
000176h
IFS3
IEC3
IPC12
Input Capture 1
1
000016h
000116h
IFS0
IEC0
IPC0
Input Capture 2
5
00001Eh
00011Eh
IFS0
IEC0
IPC1
Input Capture 3
37
00005Eh
00015Eh
IFS2
IEC2
IPC9
Input Capture 4
38
000060h
000160h
IFS2
IEC2
IPC9
Input Capture 5
39
000062h
000162h
IFS2
IEC2
IPC9
Input Capture 6
40
000064h
000164h
IFS2
IEC2
IPC10
Input Capture 7
22
000040h
000140h
IFS1
IEC1
IPC5
JTAG
117
0000FEh
0001FEh
IFS7
IEC7
IPC29
Input Change Notification (ICN)
19
00003Ah
00013Ah
IFS1
IEC1
IPC4
LCD Controller
100
0000DCh
0001DCh
IFS6
IEC6
IPC25
High/Low-Voltage Detect (HLVD)
72
0000A4h
0001A4h
IFS4
IEC4
IPC18
Output Compare 1
2
000018h
000118h
IFS0
IEC0
IPC0
Output Compare 2
6
000020h
000120h
IFS0
IEC0
IPC1
Output Compare 3
25
000046h
000146h
IFS1
IEC1
IPC6
Output Compare 4
26
000048h
000148h
IFS1
IEC1
IPC6
Output Compare 5
41
000066h
000166h
IFS2
IEC2
IPC10
Output Compare 6
42
000068h
000168h
IFS2
IEC2
IPC10
Output Compare 7
43
00006Ah
00016Ah
IFS2
IEC2
IPC10
Enhanced Parallel Master Port (EPMP)
45
00006Eh
00016Eh
IFS2
IEC2
IPC11
Real-Time Clock and Calendar (RTCC)
62
000090h
000190h
IFS3
IEC3
IPC15
SPI1 Error
9
000026h
000126h
IFS0
IEC0
IPC2
SPI1 Event
10
000028h
000128h
IFS0
IEC0
IPC2
SPI2 Error
32
000054h
000154h
IFS2
IEC2
IPC8
SPI2 Event
33
000056h
000156h
IFS2
IEC2
IPC8
2010-2014 Microchip Technology Inc.
DS30009996G-page 97
PIC24FJ128GA310 FAMILY
TABLE 8-2:
IMPLEMENTED INTERRUPT VECTORS (CONTINUED)
Interrupt Bit Locations
Vector
Number
IVT
Address
AIVT
Address
Flag
Enable
Priority
Timer1
3
00001Ah
00011Ah
IFS0
IEC0
IPC0
Timer2
7
000022h
000122h
IFS0
IEC0
IPC1
Timer3
8
000024h
000124h
IFS0
IEC0
IPC2
Timer4
27
00004Ah
00014Ah
IFS1
IEC1
IPC6
Timer5
28
00004Ch
00014Ch
IFS1
IEC1
IPC7
UART1 Error
65
000096h
000196h
IFS4
IEC4
IPC16
UART1 Receiver
11
00002Ah
00012Ah
IFS0
IEC0
IPC2
UART1 Transmitter
12
00002Ch
00012Ch
IFS0
IEC0
IPC3
UART2 Error
66
000098h
000198h
IFS4
IEC4
IPC16
Interrupt Source
UART2 Receiver
30
000050h
000150h
IFS1
IEC1
IPC7
UART2 Transmitter
31
000052h
000152h
IFS1
IEC1
IPC7
UART3 Error
81
0000B6h
0001B6h
IFS5
IEC5
IPC20
UART3 Receiver
82
0000B8h
0001B8h
IFS5
IEC5
IPC20
UART3 Transmitter
83
0000BAh
0001BAh
IFS5
IEC5
IPC20
UART4 Error
87
0000C2h
0001C2h
IFS5
IEC5
IPC21
UART4 Receiver
88
0000C4h
0001C4h
IFS5
IEC5
IPC22
UART4 Transmitter
89
0000C6h
0001C6h
IFS5
IEC5
IPC22
8.3
Interrupt Control and Status
Registers
The PIC24FJ128GA310 family of devices implements
a total of 43 registers for the interrupt controller:
•
•
•
•
•
INTCON1
INTCON2
IFS0 through IFS7
IEC0 through IEC7
IPC0 through IPC13, ICP15 and ICP16, ICP18
through ICP23, ICP25 and ICP29
• INTTREG
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table (AIVT).
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or an external signal
and is cleared via software.
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
DS30009996G-page 98
The IPCx registers are used to set the Interrupt Priority
Level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector
Number (VECNUM) and the Interrupt Level
(ILR) bit fields in the INTTREG register. The
new Interrupt Priority Level is the priority of the
pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the order of their vector numbers,
as shown in Table 8-2. For example, the INT0 (External
Interrupt 0) is shown as having a vector number and a
natural order priority of 0. Thus, the INT0IF status bit is
found in IFS0, the INT0IE enable bit in IEC0
and the INT0IP priority bits in the first position of
IPC0 (IPC0).
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers contain bits that control interrupt functionality. The ALU
STATUS Register (SR) contains the IPL bits
(SR). These indicate the current CPU Interrupt
Priority Level. The user can change the current CPU
priority level by writing to the IPLx bits.
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The CORCON register contains the IPL3 bit, which
together with the IPL bits, indicate the current
CPU priority level. IPL3 is a read-only bit so that trap
events cannot be masked by the user software.
The interrupt controller has the Interrupt Controller Test
register, INTTREG, which displays the status of the
interrupt controller. When an interrupt request occurs,
it’s associated vector number and the new Interrupt Pri-
REGISTER 8-1:
ority Level are latched into INTTREG. This information
can be used to determine a specific interrupt source if
a generic ISR is used for multiple vectors (such as
when ISR remapping is used in bootloader applications) or to check if another interrupt is pending while in
an ISR.
All interrupt registers are described in Register 8-1
through Register 8-44 in the succeeding pages.
SR: ALU STATUS REGISTER (IN CPU)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
DC(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL2(2,3)
IPL1(2,3)
IPL0(2,3)
RA(1)
N(1)
OV(1)
Z(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-9
Unimplemented: Read as ‘0’
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1:
2:
3:
x = Bit is unknown
See Register 3-1 for the description of the remaining bits (bits 8, 4, 3, 2, 1 and 0) that are not dedicated to
interrupt control functions.
The IPLx bits are concatenated with the IPL3 (CORCON) bit to form the CPU Interrupt Priority Level.
The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.
The IPLx Status bits are read-only when NSTDIS (INTCON1) = 1.
2010-2014 Microchip Technology Inc.
DS30009996G-page 99
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REGISTER 8-2:
CORCON: CPU CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0
r-1
U-0
U-0
—
—
—
—
IPL3(1)
r
—
—
bit 7
bit 0
Legend:
r = Reserved bit
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
Unimplemented: Read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2
Reserved: Read as ‘1’
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level;
see Register 3-2 for bit description.
DS30009996G-page 100
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REGISTER 8-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
NSTDIS
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
MATHERR
ADDRERR
STKERR
OSCFAIL
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14-5
Unimplemented: Read as ‘0’
bit 4
MATHERR: Arithmetic Error Trap Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2
STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1
OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0
Unimplemented: Read as ‘0’
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DS30009996G-page 101
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REGISTER 8-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
R-0, HSC
U-0
U-0
U-0
U-0
U-0
U-0
ALTIVT
DISI
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Use Alternate Interrupt Vector Table
0 = Use standard (default) Interrupt Vector Table
bit 14
DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-5
Unimplemented: Read as ‘0’
bit 4
INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 3
INT3EP: External Interrupt 3 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 2
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
DS30009996G-page 102
x = Bit is unknown
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REGISTER 8-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DMA1IF
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPF1IF
T3IF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0,
R/W-0
R/W-0
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC1IF
IC1IF
INT0IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
DMA1IF: DMA Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13
AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10
SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
SPF1IF: SPI1 Fault Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
DMA0IF: DMA Channel 0 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 103
PIC24FJ128GA310 FAMILY
REGISTER 8-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS30009996G-page 104
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
bit 15
bit 8
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
IC7IF
—
INT1IF
CNIF
CMIF
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14
U2RXIF: UART2 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13
INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12
T5IF: Timer5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11
T4IF: Timer4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10
OC4IF: Output Compare Channel 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
DMA2IF: DMA Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7
Unimplemented: Read as ‘0’
bit 6
IC7IF: Input Capture Channel 7 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
Unimplemented: Read as ‘0’
bit 4
INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 105
PIC24FJ128GA310 FAMILY
REGISTER 8-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED)
bit 2
CMIF: Comparator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
MI2C1IF: Master I2C1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS30009996G-page 106
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DMA4IF
PMPIF
—
OC7IF
OC6IF
OC5IF
IC6IF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
IC5IF
IC4IF
IC3IF
DMA3IF
—
—
SPI2IF
SPF2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
DMA4IF: DMA Channel 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13
PMPIF: Parallel Master Port Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12
Unimplemented: Read as ‘0’
bit 11
OC7IF: Output Compare Channel 7 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10
OC6IF: Output Compare Channel 6 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
OC5IF: Output Compare Channel 5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
IC6IF: Input Capture Channel 6 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7
IC5IF: Input Capture Channel 5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6
IC4IF: Input Capture Channel 4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
DMA3IF: DMA Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3-2
Unimplemented: Read as ‘0’
bit 1
SPI2IF: SPI2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 107
PIC24FJ128GA310 FAMILY
REGISTER 8-7:
bit 0
IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED)
SPF2IF: SPI2 Fault Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
REGISTER 8-8:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
RTCIF
DMA5IF
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13
DMA5IF: DMA Channel 5 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-7
Unimplemented: Read as ‘0’
bit 6
INT4IF: External Interrupt 4 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
INT3IF: External Interrupt 3 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4-3
Unimplemented: Read as ‘0’
bit 2
MI2C2IF: Master I2C2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
DS30009996G-page 108
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
—
—
CTMUIF
—
—
—
—
HLVDIF
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
—
CRCIF
U2ERIF
U1ERIF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
CTMUIF: CTMU Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-9
Unimplemented: Read as ‘0’
bit 8
HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7-4
Unimplemented: Read as ‘0’
bit 3
CRCIF: CRC Generator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
U2ERIF: UART2 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
U1ERIF: UART1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 109
PIC24FJ128GA310 FAMILY
REGISTER 8-10:
IFS5: INTERRUPT FLAG STATUS REGISTER 5
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
U4TXIF
U4RXIF
bit 15
bit 8
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
U4ERIF
—
—
—
U3TXIF
U3RXIF
U3ERIF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
Unimplemented: Read as ‘0’
bit 9
U4TXIF: UART4 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
U4RXIF: UART4 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7
U4ERIF: UART4 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6-4
Unimplemented: Read as ‘0’
bit 3
U3TXIF: UART3 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
U3RXIF: UART3 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
U3ERIF: UART3 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
DS30009996G-page 110
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-11:
IFS6: INTERRUPT FLAG STATUS REGISTER 6
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
LCDIF
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-5
Unimplemented: Read as ‘0’
bit 4
LCDIF: LCD Controller Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 8-12:
x = Bit is unknown
IFS7: INTERRUPT FLAG STATUS REGISTER 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
JTAGIF
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
Unimplemented: Read as ‘0’
bit 5
JTAGIF: JTAG Controller Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4-0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 111
PIC24FJ128GA310 FAMILY
REGISTER 8-13:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DMA1IE
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPF1IE
T3IE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
DMA1IE: DMA Channel 1 Interrupt Flag Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13
AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12
U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 11
U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 10
SPI1IE: SPI1 Transfer Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 9
SPF1IE: SPI1 Fault Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4
DMA0IE: DMA Channel 0 Interrupt Flag Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3
T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
DS30009996G-page 112
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-13:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
INT0IE: External Interrupt 0 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
2010-2014 Microchip Technology Inc.
DS30009996G-page 113
PIC24FJ128GA310 FAMILY
REGISTER 8-14:
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U2TXIE
U2RXIE
INT2IE(1)
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
bit 15
bit 8
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
IC7IE
—
INT1IE(1)
CNIE
CMIE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
U2TXIE: UART2 Transmitter Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14
U2RXIE: UART2 Receiver Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13
INT2IE: External Interrupt 2 Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12
T5IE: Timer5 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 11
T4IE: Timer4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 10
OC4IE: Output Compare Channel 4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 9
OC3IE: Output Compare Channel 3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8
DMA2IE: DMA Channel 2 Interrupt Flag Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7
Unimplemented: Read as ‘0’
bit 6
IC7IE: Input Capture Channel 7 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5
Unimplemented: Read as ‘0’
bit 4
INT1IE: External Interrupt 1 Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Note 1:
x = Bit is unknown
If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn
pin. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
DS30009996G-page 114
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-14:
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED)
bit 3
CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2
CMIE: Comparator Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
MI2C1IE: Master I2C1 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
SI2C1IE: Slave I2C1 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Note 1:
If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn
pin. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
2010-2014 Microchip Technology Inc.
DS30009996G-page 115
PIC24FJ128GA310 FAMILY
REGISTER 8-15:
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DMA4IE
PMPIE
—
OC7IE
OC6IE
OC5IE
IC6IE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
IC5IE
IC4IE
IC3IE
DMA3IE
—
—
SPI2IE
SPF2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
DMA4IE: DMA Channel 4 Interrupt Flag Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13
PMPIE: Parallel Master Port Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12
Unimplemented: Read as ‘0’
bit 11
OC7IE: Output Compare Channel 7 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 10
OC6IE: Output Compare Channel 6 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 9
OC5IE: Output Compare Channel 5 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8
IC6IE: Input Capture Channel 6 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7
IC5IE: Input Capture Channel 5 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6
IC4IE: Input Capture Channel 4 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4
DMA3IF: DMA Channel 3 Interrupt Flag Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3-2
Unimplemented: Read as ‘0’
DS30009996G-page 116
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-15:
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
bit 1
SPI2IE: SPI2 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
SPF2IE: SPI2 Fault Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
REGISTER 8-16:
IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
RTCIE
DMA5IE
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
—
INT4IE(1)
INT3IE(1)
—
—
MI2C2IE
SI2C2IE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
RTCIE: Real-Time Clock/Calendar Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13
DMA5IE: DMA Channel 5 Interrupt Flag Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12-7
Unimplemented: Read as ‘0’
bit 6
INT4IE: External Interrupt 4 Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5
INT3IE: External Interrupt 3 Enable bit(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4-3
Unimplemented: Read as ‘0’
bit 2
MI2C2IE: Master I2C2 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
SI2C2IE: Slave I2C2 Event Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn
pin. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
2010-2014 Microchip Technology Inc.
DS30009996G-page 117
PIC24FJ128GA310 FAMILY
REGISTER 8-17:
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
—
—
CTMUIE
—
—
—
—
HLVDIE
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
—
—
—
—
CRCIE
U2ERIE
U1ERIE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
CTMUIE: CTMU Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12-9
Unimplemented: Read as ‘0’
bit 8
HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7-4
Unimplemented: Read as ‘0’
bit 3
CRCIE: CRC Generator Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2
U2ERIE: UART2 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
U1ERIE: UART1 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
Unimplemented: Read as ‘0’
DS30009996G-page 118
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-18:
IEC5: INTERRUPT ENABLE CONTROL REGISTER 5
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
U4TXIE
U4RXIE
bit 15
bit 8
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
U4ERIE
—
—
—
U3TXIE
U3RXIE
U3ERIE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
Unimplemented: Read as ‘0’
bit 9
U4TXIE: UART4 Transmitter Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8
U4RXIE: UART4 Receiver Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 7
U4ERIE: UART4 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6-4
Unimplemented: Read as ‘0’
bit 3
U3TXIE: UART3 Transmitter Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2
U3RXIE: UART3 Receiver Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
U3ERIE: UART3 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 119
PIC24FJ128GA310 FAMILY
REGISTER 8-19:
IEC6: INTERRUPT ENABLE CONTROL REGISTER 6
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
LCDIE
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-5
Unimplemented: Read as ‘0’
bit 4
LCDIE: LCD Controller Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 8-20:
x = Bit is unknown
IEC7: INTERRUPT ENABLE CONTROL REGISTER 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
JTAGIE
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
Unimplemented: Read as ‘0’
bit 5
JTAGIE: JTAG Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4-0
Unimplemented: Read as ‘0’
DS30009996G-page 120
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-21:
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T1IP: Timer1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP: Input Capture Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP: External Interrupt 0 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 121
PIC24FJ128GA310 FAMILY
REGISTER 8-22:
IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2
DMA0IP1
DMA0IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T2IP: Timer2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP: Output Compare Channel 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP: Input Capture Channel 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA0IP: DMA Channel 0 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS30009996G-page 122
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-23:
IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
SPF1IP2
SPF1IP1
SPF1IP0
—
T3IP2
T3IP1
T3IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP: UART1 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP: SPI1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPF1IP: SPI1 Fault Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP: Timer3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 123
PIC24FJ128GA310 FAMILY
REGISTER 8-24:
IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
DMA1IP2
DMA1IP1
DMA1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
AD1IP2
AD1IP1
AD1IP0
—
U1TXIP2
U1TXIP1
U1TXIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
DMA1IP: DMA Channel 1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
AD1IP: ADC1 Conversion Complete Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS30009996G-page 124
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-25:
IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
CNIP2
CNIP1
CNIP0
—
CMIP2
CMIP1
CMIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP: Input Change Notification Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
CMIP: Comparator Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MI2C1IP: Master I2C1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP: Slave I2C1 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 125
PIC24FJ128GA310 FAMILY
REGISTER 8-26:
IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
IC7IP2
IC7IP1
IC7IP0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
IC7IP: Input Capture Channel 7 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
INT1IP: External Interrupt 1 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS30009996G-page 126
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-27:
IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2
DMA2IP1
DMA2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T4IP: Timer4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC4IP: Output Compare Channel 4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC3IP: Output Compare Channel 3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA2IP: DMA Channel 2 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 127
PIC24FJ128GA310 FAMILY
REGISTER 8-28:
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U2TXIP: UART2 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2RXIP: UART2 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP: External Interrupt 2 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T5IP: Timer5 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS30009996G-page 128
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-29:
IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPF2IP2
SPF2IP1
SPF2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
SPI2IP: SPI2 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPF2IP: SPI2 Fault Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 129
PIC24FJ128GA310 FAMILY
REGISTER 8-30:
IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
IC5IP2
IC5IP1
IC5IP0
—
IC4IP2
IC4IP1
IC4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2
DMA3IP1
DMA3IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC5IP: Input Capture Channel 5 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC4IP: Input Capture Channel 4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC3IP: Input Capture Channel 3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA3IP: DMA Channel 3 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS30009996G-page 130
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-31:
IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
OC7IP2
OC7IP1
OC7IP0
—
OC6IP2
OC6IP1
OC6IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
OC5IP2
OC5IP1
OC5IP0
—
IC6IP2
IC6IP1
IC6IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
OC7IP: Output Compare Channel 7 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC6IP: Output Compare Channel 6 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC5IP: Output Compare Channel 5 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
IC6IP: Input Capture Channel 6 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 131
PIC24FJ128GA310 FAMILY
REGISTER 8-32:
IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
DMA4IP2
DMA4IP1
DMA4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
PMPIP2
PMPIP1
PMPIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
DMA4IP: DMA Channel 4 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PMPIP: Parallel Master Port Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS30009996G-page 132
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-33:
IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
MI2C2IP2
MI2C2IP1
MI2C2IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
MI2C2IP: Master I2C2 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2C2IP: Slave I2C2 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 133
PIC24FJ128GA310 FAMILY
REGISTER 8-34:
IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
INT4IP: External Interrupt 4 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT3IP: External Interrupt 3 Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS30009996G-page 134
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-35:
IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
RTCIP2
RTCIP1
RTCIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
DMA5IP2
DMA5IP1
DMA5IP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
RTCIP: Real-Time Clock and Calendar Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
DMA5IP: DMA Channel 5 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 135
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REGISTER 8-36:
IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
CRCIP2
CRCIP1
CRCIP0
—
U2ERIP2
U2ERIP1
U2ERIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
U1ERIP2
U1ERIP1
U1ERIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CRCIP: CRC Generator Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2ERIP: UART2 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1ERIP: UART1 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS30009996G-page 136
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-37:
IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
HLVDIP2
HLVDIP1
HLVDIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
HLVDIP: High/Low-Voltage Detect Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
REGISTER 8-38:
x = Bit is unknown
IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
CTMUIP2
CTMUIP1
CTMUIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
CTMUIP: CTMU Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 137
PIC24FJ128GA310 FAMILY
REGISTER 8-39:
IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
U3TXIP2
U3TXIP1
U3TXIP0
—
U3RXIP2
U3RXIP1
U3RXIP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
U3ERIP2
U3ERIP1
U3ERIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U3TXIP: UART3 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U3RXIP: UART3 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U3ERIP: UART3 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS30009996G-page 138
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-40:
IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
U4ERIP2
U4ERIP1
U4ERIP0
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U4ERIP: UART4 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11-0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 139
PIC24FJ128GA310 FAMILY
REGISTER 8-41:
IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
U4TXIP2
U4TXIP1
U4TXIP0
—
U4RXIP2
U4RXIP1
U4RXIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
U4TXIP: UART4 Transmitter Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U4RXIP: UART4 Receiver Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
DS30009996G-page 140
x = Bit is unknown
2010-2014 Microchip Technology Inc.
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REGISTER 8-42:
IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
LCDIP2
LCDIP1
LCDIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
LCDIP: LCD Controller Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
REGISTER 8-43:
x = Bit is unknown
IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
JTAGIP2
JTAGIP1
JTAGIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
JTAGIP: JTAG Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 141
PIC24FJ128GA310 FAMILY
REGISTER 8-44:
INTTREG: INTERRUPT CONTROLLER TEST REGISTER
R-0, HSC
U-0
R/W-0
U-0
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
CPUIRQ
—
VHOLD
—
ILR3
ILR2
ILR1
ILR0
bit 15
bit 8
U-0
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
—
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CPUIRQ: Interrupt Request from Interrupt Controller CPU bit
1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens
when the CPU priority is higher than the interrupt priority
0 = No interrupt request is unacknowledged
bit 14
Unimplemented: Read as ‘0’
bit 13
VHOLD: Vector Number Capture Configuration bit
1 = The VECNUMx bits contain the value of the highest priority pending interrupt
0 = The VECNUMx bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that
has occurred with higher priority than the CPU, even if other interrupts are pending)
bit 12
Unimplemented: Read as ‘0’
bit 11-8
ILR: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM: Vector Number of Pending Interrupt or Last Acknowledged Interrupt bits
VHOLD = 1: The VECNUMx bits indicate the vector number (from 0 to 118) of the last interrupt to occur
VHOLD = 0: The VECNUMx bits indicate the vector number (from 0 to 118) of the interrupt request
currently being handled
DS30009996G-page 142
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
8.4
Interrupt Setup Procedures
8.4.1
INITIALIZATION
To configure an interrupt source:
1.
2.
Set the NSTDIS (INTCON1) control bit if
nested interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
Note:
3.
4.
At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to Priority Level 4.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
8.4.2
8.4.3
TRAP SERVICE ROUTINE (TSR)
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
8.4.4
INTERRUPT DISABLE
All user interrupts can be disabled using the following
procedure:
1.
2.
Push the current SR value onto the software
stack using the PUSH instruction.
Force the CPU to Priority Level 7 by inclusive
ORing the value 0Eh with SRL.
To enable user interrupts, the POP instruction may be
used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (Levels 8-15)
cannot be disabled.
The DISI instruction provides a convenient way to
disable interrupts of Priority Levels 1-6 for a fixed
period of time. Level 7 interrupt sources are not
disabled by the DISI instruction.
INTERRUPT SERVICE ROUTINE
(ISR)
The method that is used to declare an Interrupt Service
Routine (ISR) and initialize the IVT with the correct vector address will depend on the programming language
(i.e., ‘C’ or assembler) and the language development
toolsuite that is used to develop the application. In
general, the user must clear the interrupt flag in the
appropriate IFSx register for the source of the interrupt
that the ISR handles; otherwise, the ISR will be
re-entered immediately after exiting the routine. If the
ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved
PC value, SRL value and old CPU priority level.
2010-2014 Microchip Technology Inc.
DS30009996G-page 143
PIC24FJ128GA310 FAMILY
NOTES:
DS30009996G-page 144
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
9.0
• Software-controllable switching between various
clock sources
• Software-controllable postscaler for selective
clocking of CPU for system power savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
• A separate and independently configurable system
clock output for synchronizing external hardware
OSCILLATOR
CONFIGURATION
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference source. For more information, refer
to “Oscillator” (DS39700) in the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
A simplified diagram of the oscillator system is shown
in Figure 9-1.
The oscillator system for PIC24FJ128GA310 family
devices has the following features:
• A total of four external and internal oscillator options
as clock sources, providing 11 different clock modes
• On-chip 4x PLL to boost internal operating frequency
on select internal and external oscillator sources
FIGURE 9-1:
PIC24FJ128GA310 FAMILY CLOCK DIAGRAM
Primary Oscillator
REFOCON
XT, HS, EC
OSCO
Reference Clock
Generator
OSCI
4 x PLL
8 MHz
(nominal)
REFO
8 MHz
4 MHz
Postscaler
FRC
Oscillator
XTPLL, HSPLL,
ECPLL, FRCPLL
FRCDIV
Peripherals
CLKDIV
FRC
CLKO
LPRC
Postscaler
LPRC
Oscillator
31 kHz (nominal)
Secondary Oscillator
SOSC
SOSCO
SOSCI
CPU
CLKDIV
SOSCEN
Enable
Oscillator
Clock Control Logic
Fail-Safe
Clock
Monitor
WDT, PWRT
Clock Source Option
for Other Modules
2010-2014 Microchip Technology Inc.
DS30009996G-page 145
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9.1
CPU Clocking Scheme
9.2
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have the
option of using the internal 4x PLL. The frequency of
the FRC clock source can optionally be reduced by the
programmable clock divider. The selected clock source
generates the processor and peripheral clock sources.
The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this
document, the instruction cycle clock is also denoted
by FOSC/2. The internal instruction cycle clock, FOSC/2,
can be provided on the OSCO I/O pin for some
operating modes of the primary oscillator.
Initial Configuration on POR
The oscillator source (and operating mode) that is
used at a device Power-on Reset event is selected
using Configuration bit settings. The Oscillator
Configuration bit settings are located in the
Configuration registers in the program memory (refer
to Section 29.0 “Special Features” for further
details). The Primary Oscillator Configuration bits,
POSCMD (Configuration Word 2), and the
Initial
Oscillator
Select
Configuration
bits,
FNOSC (Configuration Word 2), select
the oscillator source that is used at a Power-on Reset.
The FRC Primary Oscillator with Postscaler (FRCDIV)
is the default (unprogrammed) selection. The Secondary Oscillator (SOSC), or one of the internal oscillators,
may be chosen by programming these bit locations.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 9-1.
9.2.1
CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM Configuration bits (Configuration
Word 2) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when the
FCKSM bits are both programmed (‘00’).
TABLE 9-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD
FNOSC
Fast RC Oscillator with Postscaler
(FRCDIV)
Internal
11
111
1, 2
(Reserved)
Internal
xx
110
1
Low-Power RC Oscillator (LPRC)
Note
Internal
11
101
1
Secondary
11
100
1
Primary Oscillator (XT) with PLL
Module (XTPLL)
Primary
01
011
Primary Oscillator (EC) with PLL
Module (ECPLL)
Primary
00
011
Primary Oscillator (HS)
Primary
10
010
Primary Oscillator (XT)
Primary
01
010
Primary Oscillator (EC)
Primary
00
010
Fast RC Oscillator with PLL Module
(FRCPLL)
Internal
11
001
1
Fast RC Oscillator (FRC)
Internal
11
000
1
Secondary (Timer1) Oscillator
(SOSC)
Note 1:
2:
OSCO pin function is determined by the OSCIOFCN Configuration bit.
This is the default oscillator mode for an unprogrammed (erased) device.
DS30009996G-page 146
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9.3
Control Registers
The operation of the oscillator is controlled by three
Special Function Registers:
• OSCCON
• CLKDIV
• OSCTUN
The OSCCON register (Register 9-1) is the main control register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
REGISTER 9-1:
The CLKDIV register (Register 9-2) controls the
features associated with Doze mode, as well as the
postscaler for the FRC oscillator.
The OSCTUN register (Register 9-3) allows the user to
fine tune the FRC oscillator over a range of approximately ±1.5%. Each bit increment or decrement
changes the factory calibrated frequency of the FRC
oscillator by a fixed amount.
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
R-0
R-0
R-0
U-0
R/W-x(1)
R/W-x(1)
R/W-x(1)
—
COSC2
COSC1
COSC0
—
NOSC2
NOSC1
NOSC0
bit 15
bit 8
R/SO-0
R/W-0
R-0(3)
U-0
R/CO-0
R/W-0
R/W-0
R/W-0
CLKLOCK
IOLOCK(2)
LOCK
—
CF
POSCEN
SOSCEN
OSWEN
bit 7
bit 0
Legend:
CO = Clearable Only bit
SO = Settable Only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC: Current Oscillator Selection bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC: New Oscillator Selection bits(1)
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
Note 1:
2:
3:
x = Bit is unknown
Reset values for these bits are determined by the FNOSCx Configuration bits.
The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.
This bit also resets to ‘0’ during any valid clock switch or whenever a Non-PLL Clock mode is selected.
2010-2014 Microchip Technology Inc.
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PIC24FJ128GA310 FAMILY
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 7
CLKLOCK: Clock Selection Lock Enabled bit
If FSCM is Enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is Disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6
IOLOCK: I/O Lock Enable bit(2)
1 = I/O lock is active
0 = I/O lock is not active
bit 5
LOCK: PLL Lock Status bit(3)
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4
Unimplemented: Read as ‘0’
bit 3
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2
POSCEN: Primary Oscillator Sleep Enable bit
1 = Primary oscillator continues to operate during Sleep mode
0 = Primary oscillator is disabled during Sleep mode
bit 1
SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enables Secondary Oscillator
0 = Disables Secondary Oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1 = Initiates an oscillator switch to a clock source specified by the NOSC bits
0 = Oscillator switch is complete
Note 1:
2:
3:
Reset values for these bits are determined by the FNOSCx Configuration bits.
The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.
This bit also resets to ‘0’ during any valid clock switch or whenever a Non-PLL Clock mode is selected.
DS30009996G-page 148
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PIC24FJ128GA310 FAMILY
REGISTER 9-2:
R/W-0
CLKDIV: CLOCK DIVIDER REGISTER
R/W-0
ROI
DOZE2
R/W-1
DOZE1
R/W-1
DOZE0
R/W-0
(1)
DOZEN
R/W-0
R/W-0
R/W-1
RCDIV2
RCDIV1
RCDIV0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE: CPU Peripheral Clock Ratio Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 11
DOZEN: DOZE Enable bit(1)
1 = DOZE bits specify the CPU peripheral clock ratio
0 = CPU peripheral clock ratio set to 1:1
bit 10-8
RCDIV: FRC Postscaler Select bits
111 = 31.25 kHz (divide-by-256)
110 = 125 kHz (divide-by-64)
101 = 250 kHz (divide-by-32)
100 = 500 kHz (divide-by-16)
011 = 1 MHz (divide-by-8)
010 = 2 MHz (divide-by-4)
001 = 4 MHz (divide-by-2)
000 = 8 MHz (divide-by-1)
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
2010-2014 Microchip Technology Inc.
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PIC24FJ128GA310 FAMILY
REGISTER 9-3:
OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
—
TUN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
TUN: FRC Oscillator Tuning bits(1)
011111 = Maximum frequency deviation
011110 =
000001 =
000000 = Center frequency, oscillator is running at factory calibrated frequency
111111 =
100001 =
100000 = Minimum frequency deviation
Note 1:
9.4
Increments or decrements of TUN may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
Clock Switching Operation
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC24F devices have a safeguard
lock built into the switching process.
Note:
The Primary Oscillator mode has three
different submodes (XT, HS and EC)
which are determined by the POSCMDx
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
DS30009996G-page 150
9.4.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSMx Configuration
bits in CW2 must be programmed to ‘00’. (Refer to
Section 29.1 “Configuration Bits” for further details.)
If the FCKSMx Configuration bits are unprogrammed
(‘1x’), the clock switching function and Fail-Safe Clock
Monitor function are disabled. This is the default setting.
The NOSCx control bits (OSCCON) do not
control the clock selection when clock switching is disabled. However, the COSCx bits (OSCCON)
will reflect the clock source selected by the FNOSCx
Configuration bits.
The OSWEN control bit (OSCCON) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
9.4.2
OSCILLATOR SWITCHING
SEQUENCE
A recommended code sequence for a clock switch
includes the following:
At a minimum, performing a clock switch requires this
basic sequence:
1.
1.
2.
2.
3.
4.
5.
If
desired,
read
the
COSCx
bits
(OSCCON) to determine the current
oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
Write the appropriate value to the NOSCx bits
(OSCCON) for the new oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
Set the OSWEN bit to initiate the oscillator
switch.
3.
4.
5.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
6.
1.
7.
2.
3.
4.
5.
6.
The clock switching hardware compares the
COSCx bits with the new value of the NOSCx
bits. If they are the same, then the clock switch
is a redundant operation. In this case, the
OSWEN bit is cleared automatically and the
clock switch is aborted.
If a valid clock switch has been initiated, the
LOCK (OSCCON) and CF (OSCCON)
bits are cleared.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSCx bits values are transferred to the COSCx
bits.
The old clock source is turned off at this time, with
the exception of LPRC (if WDT or FSCM are
enabled) or SOSC (if SOSCEN remains set).
Note 1: The processor will continue to execute
code throughout the clock switching
sequence. Timing-sensitive code should
not be executed during this time.
8.
Disable interrupts during the OSCCON register
unlock and write sequence.
Execute the unlock sequence for the OSCCON
high byte by writing 78h and 9Ah to
OSCCON
in
two
back-to-back
instructions.
Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
Execute the unlock sequence for the OSCCON
low byte by writing 46h and 57h to
OSCCON in two back-to-back instructions.
Set the OSWEN bit in the instruction immediately
following the unlock sequence.
Continue to execute code that is not
clock-sensitive (optional).
Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then
check the LOCK bit to determine the cause of
failure.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 9-1.
EXAMPLE 9-1:
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV
#OSCCONH, w1
MOV
#0x78, w2
MOV
#0x9A, w3
MOV.b
w2, [w1]
MOV.b
w3, [w1]
;Set new oscillator selection
MOV.b
WREG, OSCCONH
;OSCCONL (low byte) unlock sequence
MOV
#OSCCONL, w1
MOV
#0x46, w2
MOV
#0x57, w3
MOV.b
w2, [w1]
MOV.b
w3, [w1]
;Start oscillator switch operation
BSET
OSCCON,#0
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direction. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
2010-2014 Microchip Technology Inc.
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PIC24FJ128GA310 FAMILY
9.5
9.5.1
Secondary Oscillator (SOSC)
BASIC SOSC OPERATION
PIC24FJ128GA310 family devices do not have to set the
SOSCEN bit to use the Secondary Oscillator. Any
module requiring the SOSC (such as RTCC, Timer1 or
DSWDT) will automatically turn on the SOSC when the
clock signal is needed. The SOSC, however, has a long
start-up time. To avoid delays for peripheral start-up, the
SOSC can be manually started using the SOSCEN bit.
To use the Secondary Oscillator, the SOSCSEL bit
(CW3) must be set (= 1). Programming SOSCSEL
(= 0) configures the SOSC pins for Digital mode,
enabling digital input functionality on the pins.
9.5.2
EXTERNAL (DIGITAL) CLOCK
MODE (SCLKI)
The SOSC can also be configured to run from an
external 32 kHz clock source, rather than the internal
oscillator. In this mode, also referred to as Digital mode,
the clock source provided on the SCLKI pin is used to
clock any modules that are configured to use the
Secondary Oscillator. In this mode, the crystal driving
circuit is disabled and the SOSCEN bit (OSCCON)
has no effect.
9.5.3
SOSC LAYOUT CONSIDERATIONS
The pinout limitations on low pin count devices, such as
those in the PIC24FJ128GA310 family, may make the
SOSC more susceptible to noise than other PIC24FJ
devices. Unless proper care is taken in the design and
layout of the SOSC circuit, this external noise may
introduce inaccuracies into the oscillator’s period.
Note:
A typical 50K ESR (65K-70K Max) crystal
is recommended for the reliable operation
of the SOSC. The duty cycle of the SOSC
output can be measured on the REFO pin
and is recommended to be within ±15%
from a 50% duty cycle.
DS30009996G-page 152
In general, the crystal circuit connections should be as
short as possible. It is also good practice to surround
the crystal circuit with a ground loop or ground plane.
For more information on crystal circuit design, please
refer to “Oscillator” (DS39700) in the “dsPIC33/PIC24
Family Reference Manual”. Additional information is
also available in these Microchip Application Notes:
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PICmicro® Devices”
(DS00826)
• AN849, “Basic PICmicro® Oscillator Design”
(DS00849).
9.6
Reference Clock Output
In addition to the CLKO output (FOSC/2) available in
certain oscillator modes, the device clock in the
PIC24FJ128GA310 family devices can also be configured to provide a reference clock output signal to a port
pin. This feature is available in all oscillator configurations and allows the user to select a greater range of
clock submultiples to drive external devices in the
application.
This reference clock output is controlled by the
REFOCON register (Register 9-4). Setting the ROEN
bit (REFOCON) makes the clock signal available
on the REFO pin. The RODIVx bits (REFOCON)
enable the selection of 16 different clock divider
options.
The ROSSLP and ROSEL bits (REFOCON)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
on OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on REFO
when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for one of the primary
modes (EC, HS or XT). Otherwise, if the POSCEN bit
is also not set, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 9-4:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ROEN
—
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROEN: Reference Oscillator Output Enable bit
1 = Reference oscillator is enabled on the REFO pin
0 = Reference oscillator is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
ROSSLP: Reference Oscillator Output Stop in Sleep bit
1 = Reference oscillator continues to run in Sleep
0 = Reference oscillator is disabled in Sleep
bit 12
ROSEL: Reference Oscillator Source Select bit
1 = Primary oscillator is used as the base clock. Note that the crystal oscillator must be enabled using
the FOSC bits; the crystal maintains the operation in Sleep mode.
0 = System clock is used as the base clock; base clock reflects any clock switching of the device
bit 11-8
RODIV: Reference Oscillator Divisor Select bits
1111 = Base clock value divided by 32,768
1110 = Base clock value divided by 16,384
1101 = Base clock value divided by 8,192
1100 = Base clock value divided by 4,096
1011 = Base clock value divided by 2,048
1010 = Base clock value divided by 1,024
1001 = Base clock value divided by 512
1000 = Base clock value divided by 256
0111 = Base clock value divided by 128
0110 = Base clock value divided by 64
0101 = Base clock value divided by 32
0100 = Base clock value divided by 16
0011 = Base clock value divided by 8
0010 = Base clock value divided by 4
0001 = Base clock value divided by 2
0000 = Base clock value
bit 7-0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
DS30009996G-page 153
PIC24FJ128GA310 FAMILY
NOTES:
DS30009996G-page 154
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
10.0
POWER-SAVING FEATURES
This data sheet summarizes the features
of this group of PIC24FJ devices. It is not
intended to be a comprehensive
reference source. For more information,
refer to “Power-Saving Features with
VBAT” (DS30622) in the “dsPIC33/PIC24
Family
Reference
Manual”.
The
information in this data sheet supersedes
the information in the FRM.
Note:
The PIC24FJ128GA310 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked reduces consumed
power.
PIC24FJ128GA310 family devices manage power
consumption with five strategies:
•
•
•
•
•
Instruction-Based Power Reduction Modes
Hardware-Based Power Reduction Features
Clock Frequency Control
Software Controlled Doze Mode
Selective Peripheral Control in Software
10.1
Overview of Power-Saving Modes
In addition to full-power operation, otherwise known as
Run mode, the PIC24FJ128GA310 family of devices
offers three Instruction-Based, Power-Saving modes
and one Hardware-Based mode:
•
•
•
•
Idle
Sleep (Sleep and Low-Voltage Sleep)
Deep Sleep
VBAT (with and without RTCC)
All four modes can be activated by powering down different functional areas of the microcontroller, allowing
progressive reductions of operating and Idle power
consumption. In addition, three of the modes can be
tailored for more power reduction, at a trade-off of
some operating features. Table 10-1 lists all of the
operating modes, in order of increasing power savings.
Table 10-2 summarizes how the microcontroller exits
the different modes. Specific information is provided in
the following sections.
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
TABLE 10-1:
OPERATING MODES FOR PIC24FJ128GA310 FAMILY DEVICES
Active Systems
Mode
Run (default)
Idle
Core
Peripherals
Data RAM
Retention
RTCC(1)
DSGPR0/
DSGPR1
Retention
Entry
N/A
Y
Y
Y
Y
Y
Instruction
N
Y
Y
Y
Y
Instruction
N
S(2)
Y
Y
Y
Instruction +
RETEN bit
N
S(2)
Y
Y
Y
Instruction +
DSEN bit
N
N
N
Y
Y
Hardware
N
N
N
Y
Y
Sleep:
Sleep
Low-Voltage Sleep
Deep Sleep:
Deep Sleep
VBAT:
with RTCC
Note 1:
2:
If RTCC is otherwise enabled in firmware.
A select peripheral can operate during this mode from LPRC or some external clock.
2010-2014 Microchip Technology Inc.
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TABLE 10-2:
EXITING POWER SAVING MODES
Exit Conditions
INT0
All
POR
MCLR
RTCC
Alarm
WDT
All
VDD
Restore
Code
Execution
Resumes(2)
Idle
Y
Y
Y
Y
Y
Y
Y
N/A
Next Instruction
Sleep (all modes)
Y
Y
Y
Y
Y
Y
Y
N/A
(1)
N/A
Reset Vector
Y
Reset Vector
Mode
Interrupts
Resets
Deep Sleep
N
Y
N
Y
Y
Y
VBAT
N
N
N
N
N
N
Note 1:
2:
10.1.1
N
Deep Sleep WDT.
Code execution resumption is also valid for all the exit conditions; for example, a MCLR and POR exit will
cause code execution from the Reset vector.
INSTRUCTION-BASED
POWER-SAVING MODES
Three of the power-saving modes are entered through
the execution of the PWRSAV instruction. Sleep mode
stops clock operation and halts all code execution. Idle
mode halts the CPU and code execution, but allows
peripheral modules to continue operation. Deep Sleep
mode stops clock operation, code execution and all
peripherals, except RTCC and DSWDT. It also freezes
I/O states and removes power to Flash memory and
may remove power to SRAM.
The assembly syntax of the PWRSAV instruction is shown
in Example 10-1. Sleep and Idle modes are entered
directly with a single assembler command. Deep Sleep
requires an additional sequence to unlock and enable
the entry into Deep Sleep, which is described in
Section 10.4.1 “Entering Deep Sleep Mode”.
Note:
Y
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
The features enabled with the low-voltage/retention
regulator results in some changes to the way that Sleep
mode behaves. See Section 10.3 “Sleep Mode”.
10.1.1.1
Interrupts Coincident with Power
Save Instructions
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into
Sleep/Deep Sleep or Idle mode has completed. The
device will then wake-up from Sleep/Deep Sleep or Idle
mode.
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
To enter Deep Sleep, the DSCON bit
should be cleared before setting the
DSEN bit,
EXAMPLE 10-1:
PWRSAV INSTRUCTION SYNTAX
// Syntax to enter Sleep mode:
PWRSAV
#SLEEP_MODE
;
//
//Synatx to enter Idle mode:
PWRSAV
#IDLE_MODE
;
//
// Syntax to enter Deep Sleep mode:
// First use the unlock sequence to
CLR
DSCON
CLR
DSCON
;
BSET
DSCON, #DSEN
;
BSET
DSCON, #DSEN
;
PWRSAV
#SLEEP_MODE
;
DS30009996G-page 156
Put the device into SLEEP mode
Put the device into IDLE mode
set the DSEN bit (see Example 10-2)
(repeat the command)
Enable Deep Sleep
Enable Deep Sleep (repeat the command)
Put the device into Deep SLEEP mode
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
10.1.2
HARDWARE-BASED
POWER-SAVING MODE
The hardware-based VBAT mode does not require any
action by the user during code development. Instead, it
is a hardware design feature that allows the microcontroller to retain critical data (using the DSGPRx
registers) and maintain the RTCC when VDD is removed
from the application. This is accomplished by supplying
a backup power source to a specific power pin. VBAT
mode is described in more detail in Section 10.5 “Vbat
Mode”.
10.1.3
LOW-VOLTAGE/RETENTION
REGULATOR
PIC24FJ128GA310 family devices incorporate a
second on-chip voltage regulator, designed to provide
power to select microcontroller features at 1.2V nominal. This regulator allows features, such as data RAM
and the WDT, to be maintained in power-saving modes
where they would otherwise be inactive, or maintain
them at a lower power than would otherwise be the
case.
The low-voltage/retention regulator is only available
when Sleep or Deep Sleep modes are invoked. It is
controlled by the LPCFG Configuration bit (CW1)
and in firmware by the RETEN bit (RCON).
LPCFG must be programmed (= 0) and the RETEN bit
must be set (= 1) for the regulator to be enabled.
10.2
Idle Mode
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.8
“Selective Peripheral Module Control”).
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAV instruction or
the first instruction in the ISR.
2010-2014 Microchip Technology Inc.
10.3
Sleep Mode
Sleep mode includes these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum provided that no I/O pin is sourcing
current.
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock will continue to run in Sleep
mode if the WDT or RTCC, with LPRC as clock
source, is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may
continue to operate in Sleep mode. This includes
items, such as the Input Change Notification on
the I/O ports, or peripherals that use an external
clock input. Any peripheral that requires the system clock source for its operation will be disabled
in Sleep mode.
The device will wake-up from Sleep mode on any of
these events:
• On any interrupt source that is individually
enabled
• On any form of device Reset
• On a WDT time-out
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
10.3.1
LOW-VOLTAGE/RETENTION SLEEP
MODE
Low-Voltage/Retention Sleep mode functions as Sleep
mode with the same features and wake-up triggers.
The difference is that the low-voltage/retention regulator allows core digital logic voltage (VCORE) to drop to
1.2V nominal. This permits an incremental reduction of
power consumption over what would be required if
VCORE was maintained at a 1.8V (minimum) level.
Low-Voltage Sleep mode requires a longer wake-up
time than Sleep mode, due to the additional time
required to bring VCORE back to 1.8V (known as TREG).
In addition, the use of the low-voltage/retention regulator limits the amount of current that can be sourced to
any active peripherals, such as the RTCC/LCD, etc.
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10.4
Deep Sleep Mode
Deep Sleep mode provides the lowest levels of power
consumption available from the Instruction-Based
modes.
Deep Sleep modes have these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum.
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock will continue to run in Deep
Sleep mode if the WDT or RTCC with LPRC as
clock source is enabled.
• The dedicated Deep Sleep WDT and BOR
systems, if enabled, are used.
• The RTCC and its clock source continue to run, if
enabled. All other peripherals are disabled.
Entry into Deep Sleep mode is completely under
software control. Exit from the Deep Sleep modes can
be triggered from any of the following events:
•
•
•
•
•
POR event
MCLR event
RTCC alarm (If the RTCC is present)
External Interrupt 0
Deep Sleep Watchdog Timer (DSWDT) time-out
10.4.1
ENTERING DEEP SLEEP MODE
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a Sleep
command (PWRSAV #SLEEP_MODE) within one instruction cycle, to minimize the chance that Deep Sleep will
be spuriously entered.
If the PWRSAV command is not given within one
instruction cycle, the DSEN bit will be cleared by the
hardware and must be set again by the software before
entering Deep Sleep mode. The DSEN bit is also
automatically cleared when exiting Deep Sleep mode.
Note:
To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 TCY
after clearing the RELEASE bit.
DS30009996G-page 158
The sequence to enter Deep Sleep mode is:
1.
2.
3.
4.
5.
If the application requires the Deep Sleep WDT,
enable it and configure its clock source. For
more information on Deep Sleep WDT, see
Section 10.4.5 “Deep Sleep WDT”.
If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (FDS).
If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module. For more information on RTCC,
see Section 22.0 “Real-Time Clock and
Calendar (RTCC)”.
If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
Enable Deep Sleep mode by setting the DSEN
bit (DSCON).
Note:
6.
A repeat sequence is required to set the
DSEN bit. The repeat sequence (repeating
the instruction twice) is required to write
into any of the Deep Sleep registers
(DSCON, DSWAKE, DSGPR0, DSGPR1).
This is required to avoid the user from
entering Deep Sleep by mistake. Any write
to these registers has to be done twice to
actually complete the write (see
Example 10-2).
Enter Deep Sleep mode by issuing three NOP
commands and then a PWRSAV #0 instruction.
Any time the DSEN bit is set, all bits in the DSWAKE
register will be automatically cleared.
EXAMPLE 10-2:
Example 1:
mov #8000, w2
mov w2, DSCON
mov w2, DSCON
Example 2:
bset DSCON, #15
nop
nop
nop
bset DSCON, #15
THE REPEAT SEQUENCE
; enable DS
; second write required to
actually write to DSCON
; enable DS (two writes required)
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10.4.2
EXITING DEEP SLEEP MODES
10.4.3
Deep Sleep modes exit on any one of the following events:
• POR event on VDD supply. If there is no DSBOR
circuit to re-arm the VDD supply POR circuit, the
external VDD supply must be lowered to the
natural arming voltage of the POR circuit.
• DSWDT time-out. When the DSWDT timer times
out, the device exits Deep Sleep.
• RTCC alarm (if RTCEN = 1).
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
Note:
Any interrupt pending, when entering
Deep Sleep mode, is cleared.
Exiting Deep Sleep generally does not retain the state
of the device and is equivalent to a Power-on Reset
(POR) of the device. Exceptions to this include the
RTCC (if present), which remains operational through
the wake-up, the DSGPRx registers and DSWDT.
Wake-up events that occur from the time Deep Sleep
exits, until the time the POR sequence completes, are
not ignored. The DSWAKE register will capture ALL
wake-up events, from DSEN set to RELEASE clear.
The sequence for exiting Deep Sleep mode is:
1.
2.
3.
4.
5.
6.
After a wake-up event, the device exits Deep
Sleep and performs a POR. The DSEN bit is
cleared automatically. Code execution resumes
at the Reset vector.
To determine if the device exited Deep Sleep,
read the Deep Sleep bit, DPSLP (RCON).
This bit will be set if there was an exit from Deep
Sleep mode. If the bit is set, clear it.
Determine the wake-up source by reading the
DSWAKE register.
Determine if a DSBOR event occurred during
Deep Sleep mode by reading the DSBOR bit
(DSCON).
If application context data has been saved, read
it back from the DSGPR0 and DSGPR1 registers.
Clear the RELEASE bit (DSCON).
2010-2014 Microchip Technology Inc.
SAVING CONTEXT DATA WITH THE
DSGPRx REGISTERS
As exiting Deep Sleep mode causes a POR, most
Special Function Registers reset to their default POR
values. In addition, because VCORE power is not supplied in Deep Sleep mode, information in data RAM
may be lost when exiting this mode.
Applications which require critical data to be saved
prior to Deep Sleep may use the Deep Sleep General
Purpose registers, DSGPR0 and DSGPR1, or data
EEPROM (if available). Unlike other SFRs, the
contents of these registers are preserved while the
device is in Deep Sleep mode. After exiting Deep
Sleep, software can restore the data by reading the
registers and clearing the RELEASE bit (DSCON).
10.4.4
I/O PINS IN DEEP SLEEP MODES
During Deep Sleep, the general purpose I/O pins retain
their previous states and the Secondary Oscillator
(SOSC) will remain running, if enabled. Pins that are
configured as inputs (TRISx bit set), prior to entry into
Deep Sleep, remain high-impedance during Deep
Sleep. Pins that are configured as outputs (TRISx bit
clear), prior to entry into Deep Sleep, remain as output
pins during Deep Sleep. While in this mode, they
continue to drive the output level determined by their
corresponding LATx bit at the time of entry into Deep
Sleep.
Once the device wakes back up, all I/O pins continue to
maintain their previous states, even after the device
has finished the POR sequence and is executing
application code again. Pins configured as inputs
during Deep Sleep remain high-impedance, and pins
configured as outputs continue to drive their previous
value. After waking up, the TRISx and LATx registers,
and the SOSCEN bit (OSCCON) are reset. If
firmware modifies any of these bits or registers, the
I/Os will not immediately go to the newly configured
states. Once the firmware clears the RELEASE bit
(DSCON), the I/O pins are “released”. This causes
the I/O pins to take the states configured by their
respective TRISx and LATx bit values.
This means that keeping the SOSC running after
waking up requires the SOSCEN bit to be set before
clearing RELEASE.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR or a true POR event occurs during Deep
Sleep, the I/O pins will be immediately released, similar
to clearing the RELEASE bit. All previous state
information will be lost, including the general purpose
DSGPR0 and DSGPR1 contents.
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If a MCLR Reset event occurs during Deep Sleep, the
DSGPRx, DSCON and DSWAKE registers will remain
valid, and the RELEASE bit will remain set. The state
of the SOSC will also be retained. The I/O pins,
however, will be reset to their MCLR Reset state. Since
RELEASE is still set, changes to the SOSCEN bit
(OSCCON) cannot take effect until the RELEASE
bit is cleared.
In all other Deep Sleep wake-up cases, application
firmware must clear the RELEASE bit in order to
reconfigure the I/O pins.
10.4.5
DEEP SLEEP WDT
To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (CW4). The
device WDT need not be enabled for the DSWDT to
function. Entry into Deep Sleep modes automatically
reset the DSWDT.
The DSWDT clock source is selected by the
DSWDTOSC Configuration bit (CW4). The
postscaler options are programmed by the
DSWDPS Configuration bits (CW4). The
minimum time-out period that can be achieved is 1 ms
and the maximum is 25.7 days. For more details on the
CW4 Configuration register and DSWDT configuration
options, refer to Section 29.0 “Special Features”.
10.4.5.1
Switching Clocks in Deep Sleep
Mode
Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC, of approximately 5 to 10%. If a
more accurate RTCC is required, it must be run from the
SOSC clock source. The RTCC clock source is selected
with the RTCLK bits (RTCPWC).
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled), without the need
for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.
DS30009996G-page 160
10.4.6
CHECKING AND CLEARING THE
STATUS OF DEEP SLEEP
Upon entry into Deep Sleep mode, the status bit,
DPSLP (RCON), becomes set and must be
cleared by the software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode, and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
• Both the DPSLP and POR bits are cleared. In this
case, the Reset was due to some event other
than a Deep Sleep mode exit.
• The DPSLP bit is clear, but the POR bit is set; this
is a normal POR.
• Both the DPSLP and POR bits are set. This
means that Deep Sleep mode was entered, the
device was powered down and Deep Sleep mode
was exited.
10.4.7
POWER-ON RESETS (PORs)
VDD voltage is monitored to produce PORs. Since
exiting from Deep Sleep mode functionally looks like a
POR, the technique described in Section 10.4.6
“Checking and Clearing the Status of Deep Sleep”
should be used to distinguish between Deep Sleep and
a true POR event. When a true POR occurs, the entire
device, including all Deep Sleep logic (Deep Sleep
registers, RTCC, DSWDT, etc.) are reset.
10.5
VBAT Mode
This mode represents the lowest power state that the
microcontroller can achieve and still resume operation.
VBAT mode is automatically triggered when the microcontroller’s main power supply on VDD fails. When this
happens, the microcontroller’s on-chip power switch
connects to a backup power source, such as a battery,
supplied to the VBAT pin. This maintains a few key
systems at an extremely low-power draw until VDD is
restored.
The power supplied on VBAT only runs two systems: the
RTCC and the Deep Sleep Semaphore registers
(DSGPR0 and DSGPR1). To maintain these systems
during a sudden loss of VDD, it is essential to connect a
power source, other than VDD or AVDD, to the VBAT pin.
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When the RTCC is enabled, it continues to operate with
the same clock source (SOSC or LPRC) that was
selected prior to entering VBAT mode. There is no provision to switch to a lower power clock source after the
mode switch.
With VBPOR set, the user should clear it, and the next
time, this bit will only set when VDD = 0 and the VBAT
pin has gone below level VBTRST.
Since the loss of VDD is usually an unforeseen event, it
is recommended that the contents of the Deep Sleep
Semaphore registers be loaded with the data to be
retained at an early point in code execution.
All I/O pins should be maintained at VSS level; no I/O
pins should be given VDD (refer to “Absolute Maximum
Ratings” in Section 32.0 “Electrical Characteristics”) during VBAT mode. The only exceptions are the
SOSCI and SOSCO pins, which maintain their states if
the Secondary Oscillator is being used as the RTCC
clock source. It is the user’s responsibility to restore the
I/O pins to their proper states, using the TRISx and LATx
bits, once VDD has been restored.
10.5.1
VBAT MODE WITH NO RTCC
By disabling RTCC operation during VBAT mode, power
consumption is reduced to the lowest of all
power-saving modes. In this mode, only the Deep
Sleep Semaphore registers are maintained.
10.5.2
10.5.3
10.5.4
WAKE-UP FROM VBAT MODES
When VDD is restored to a device in VBAT mode, it automatically wakes. Wake-up occurs with a POR, after
which the device starts executing code from the Reset
vector. All SFRs, except the Deep Sleep Semaphores
and RTCC registers are reset to their POR values. If
the RTCC was not configured to run during VBAT mode,
it will remain disabled and RTCC will not run. Wake-up
timing is similar to that for a normal POR.
To differentiate a wake-up from VBAT mode from other
POR states, check the VBAT status bit (RCON2). If
this bit is set while the device is starting to execute the
code from Reset vector, it indicates that there has been
an exit from VBAT mode. The application must clear the
VBAT bit to ensure that future VBAT wake-up events are
captured.
If a POR occurs without a power source connected to
the VBAT pin, the VBPOR bit (RCON2) is set. If this
bit is set on a POR, it indicates that a battery needs to
be connected to the VBAT pin.
I/O PINS DURING VBAT MODES
SAVING CONTEXT DATA WITH THE
DSGPRx REGISTERS
As with Deep Sleep mode, all SFRs are reset to their
POR values after VDD has been restored. Only the
Deep Sleep Semaphore registers are preserved. Applications which require critical data to be saved should
save it in DSGPR0 and DSGPR1.
Note:
If the VBAT mode is not used, the
recommendation is to connect the VBAT
pin to VDD and connect a 0.1 μF capacitor
close to the VBAT pin to ground.
When the VBAT mode is used (connected
to the battery), it is suggested to connect
a 0.1 μF capacitor from the VBAT pin to
ground. The capacitor should be located
very close to the VBAT pin.
The BOR should be enabled for the reliable operation
of the VBAT.
In addition, if the VBAT power source falls below the
level needed for Deep Sleep Semaphore operation
while in VBAT mode (e.g., the battery has been
drained), the VBPOR bit will be set. VBPOR is also set
when the microcontroller is powered up the very first
time, even if power is supplied to VBAT.
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DSCON: DEEP SLEEP CONTROL REGISTER(1)
REGISTER 10-1:
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
DSEN
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
U-0
—
U-0
—
U-0
—
r-0
R/W-0
(2)
r
DSBOR
R/C-0, HS
RELEASE
bit 7
bit 0
Legend:
C = Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HS = Hardware Settable bit
r = Reserved bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
DSEN: Deep Sleep Enable bit
1 = Enters Deep Sleep on execution of PWRSAV #0
0 = Enters normal Sleep on execution of PWRSAV #0
bit 14-3
Unimplemented: Read as ‘0’
bit 2
Reserved: Maintain as ‘0’
bit 1
DSBOR: Deep Sleep BOR Event bit(2)
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was not active or was active but did not detect a BOR event during Deep Sleep
bit 0
RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry
0 = Releases I/O pins from their state previous to Deep Sleep entry, and allows their respective TRISx
and LATx bits to control their states
Note 1:
2:
All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms POR.
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REGISTER 10-2:
DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0, HS
—
—
—
—
—
—
—
DSINT0
bit 15
bit 8
R/W-0, HS
U-0
U-0
R/W-0, HS
R/W-0, HS
R/W-0, HS
U-0
U-0
DSFLT
—
—
DSWDT
DSRTCC
DSMCLR
—
—
bit 7
bit 0
Legend:
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
DSINT0: Deep Sleep Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
bit 7
DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been
corrupted
0 = No Fault was detected during Deep Sleep
bit 6-5
Unimplemented: Read as ‘0’
bit 4
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3
DSRTCC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
bit 2
DSMCLR: MCLR Event bit
1 = The MCLR pin was active and was asserted during Deep Sleep
0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
All register bits are cleared when the DSEN (DSCON) bit is set.
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REGISTER 10-3:
RCON2: RESET AND SYSTEM CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
U-0
—
r-0
r
R/CO-1
VDDBOR
(1)
R/CO-1
(1,2)
VDDPOR
R/CO-1
(1,3)
VBPOR
R/CO-0
VBAT(1)
bit 7
bit 0
Legend:
CO = Clearable Only bit
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4
Reserved: Maintain as ‘0’
bit 3
VDDBOR: VDD Brown-out Reset Flag bit(1)
1 = A VDD Brown-out Reset has occurred (set by hardware)
0 = A VDD Brown-out Reset has not occurred
bit 2
VDDPOR: VDD Power-On Reset Flag bit(1,2)
1 = A VDD Power-on Reset has occurred (set by hardware)
0 = A VDD Power-on Reset has not occurred
bit 1
VBPOR: VBPOR Flag bit(1,3)
1 = A VBAT POR has occurred (no battery connected to the VBAT pin, or VBAT power below Deep Sleep
Semaphore retention level, set by hardware)
0 = A VBAT POR has not occurred
bit 0
VBAT: VBAT Flag bit(1)
1 = A POR exit has occurred while power was applied to the VBAT pin (set by hardware)
0 = A POR exit from VBAT has not occurred
Note 1:
2:
3:
This bit is set in hardware only; it can only be cleared in software.
Indicates a VDD POR. Setting the POR bit (RCON) indicates a VCORE POR.
This bit is set when the device is originally powered up, even if power is present on VBAT. It is recommended that the user clear this flag, and the next time, this bit will only set when the VBAT voltage goes
below 0.4-0.6V with VDD = 0.
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10.6
Clock Frequency and Clock
Switching
In Run and Idle modes, all PIC24FJ devices allow for a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or
high-precision oscillators by simply changing the
NOSCx bits. The process of changing a system clock
during operation, as well as limitations to the process, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
10.7
Doze Mode
Generally, changing clock speed and invoking one of
the power-saving modes are the preferred strategies
for reducing power consumption. There may be
circumstances, however, where this is not practical. For
example, it may be necessary for an application to
maintain uninterrupted synchronous communication,
even while it is doing nothing else. Reducing system
clock speed may introduce communication errors,
while using a power-saving mode may stop
communications completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV). The ratio between peripheral and core
clock speed is determined by the DOZE bits
(CLKDIV). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default.
It is also possible to use Doze mode to selectively reduce
power consumption in event driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU Idles, waiting for something to invoke an
interrupt routine. Enabling the automatic return to
full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV). By default, interrupt
events have no effect on Doze mode operation.
2010-2014 Microchip Technology Inc.
10.8
Selective Peripheral Module
Control
Idle and Doze modes allow users to substantially
reduce power consumption by slowing or stopping the
CPU clock. Even so, peripheral modules still remain
clocked, and thus, consume power. There may be
cases where the application needs what these modes
do not provide: the allocation of power resources to
CPU processing with minimal power consumption from
the peripherals.
PIC24F devices address this requirement by allowing
peripheral modules to be selectively disabled, reducing
or eliminating their power consumption. This can be
done with two control bits:
• The Peripheral Enable bit, generically named,
“XXXEN”, located in the module’s main control
SFR.
• The Peripheral Module Disable (PMD) bit,
generically named, “XXXMD”, located in one of
the PMD Control registers (XXXMD bits are in
PMD1, PMD2, PMD3, PMD4, PMD6, PMD7
registers).
Both bits have similar functions in enabling or disabling
its associated module. Setting the PMD bit for a module
disables all clock sources to that module, reducing its
power consumption to an absolute minimum. In this
state, the control and status registers associated with
the peripheral will also be disabled, so writes to those
registers will have no effect and read values will be
invalid. Many peripheral modules have a corresponding
PMD bit.
In contrast, disabling a module by clearing its XXXEN
bit disables its functionality, but leaves its registers
available to be read and written to. Power consumption
is reduced, but not by as much as the PMD bits are
used. Most peripheral modules have an enable bit;
exceptions include capture, compare and RTCC.
To achieve more selective power savings, peripheral
modules can also be selectively disabled when the
device enters Idle mode. This is done through the control
bit of the generic name format, “XXXIDL”. By default, all
modules that can operate during Idle mode will do so.
Using the disable on Idle feature disables the module
while in Idle mode, allowing further reduction of power
consumption during Idle mode, enhancing power
savings for extremely critical power applications.
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NOTES:
DS30009996G-page 166
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11.0
Note:
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
I/O PORTS
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to “I/O
Ports with Peripheral Pin Select (PPS)”
(DS39711) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
All of the device pins (except VDD, VSS, MCLR and
OSCI/CLKI) are shared between the peripherals and
the parallel I/O ports. All I/O input ports feature Schmitt
Trigger (ST) inputs for improved noise immunity.
11.1
Parallel I/O (PIO) Ports
A Parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The peripheral’s
output buffer data and control signals are provided to a
pair of multiplexers. The multiplexers select whether the
peripheral or the associated port has ownership of the
output data and control signals of the I/O pin. The logic
also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the
same pin. Figure 11-1 shows how ports are shared with
other peripherals and the associated I/O pin to which
they are connected.
FIGURE 11-1:
All port pins have three registers directly associated
with their operation as digital I/Os and one register
associated with their operation as analog inputs. The
Data Direction register (TRISx) determines whether the
pin is an input or an output. If the data direction bit is a
‘1’, then the pin is an input. All port pins are defined as
inputs after a Reset. Reads from the Output Latch register (LATx), read the latch; writes to the latch, write the
latch. Reads from the port (PORTx), read the port pins;
writes to the port pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers, and the port pin will read as zeros.
When a pin is shared with another peripheral or function that is defined as an input only, it is regarded as a
dedicated port because there is no other competing
source of inputs. RC13 and RC14 can be input ports
only; they cannot be configured as outputs.
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
Read TRIS
I/O
1
Output Enable
0
1
Output Data
0
Data Bus
D
WR TRIS
CK
Q
I/O Pin
TRIS Latch
D
WR LAT +
WR PORT
Q
CK
Data Latch
Read LAT
Input Data
Read PORT
2010-2014 Microchip Technology Inc.
DS30009996G-page 167
PIC24FJ128GA310 FAMILY
11.1.1
I/O PORT WRITE/READ TIMING
11.2
One instruction cycle is required between a port direction
change or port write operation and a read operation of
the same port. Typically, this instruction would be a NOP.
11.1.2
OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx and TRISx registers for
data control, each port pin can also be individually
configured for either a digital or open-drain output. This
is controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired
digital only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
Configuring Analog Port Pins
(ANSx)
The ANSx and TRISx registers control the operation of
the pins with analog function. Each port pin with analog
function is associated with one of the ANSx bits (see
Register 11-1 through Register 11-6), which decides if
the pin function should be analog or digital. Refer to
Table 11-1 for detailed behavior of the pin for different
ANSx and TRISx bit settings.
When reading the PORTx register, all pins configured as
analog input channels will read as cleared (a low level).
11.2.1
ANALOG INPUT PINS AND
VOLTAGE CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Most input pins are
able to handle DC voltages of up to 5.5V, a level typical
for digital logic circuits. However, several pins can only
tolerate voltages up to VDD. Voltage excursions beyond
VDD on these pins should always be avoided.
Table 11-2 summarizes the different voltage tolerances.
Refer to Section 32.0 “Electrical Characteristics” for
more details.
TABLE 11-1:
CONFIGURING ANALOG/DIGITAL FUNCTION OF AN I/O PIN
Pin Function
ANSx Setting
TRISx Setting
Analog Input
1
1
It is recommended to keep ANSx = 1.
Analog Output
1
1
It is recommended to keep ANSx = 1.
Digital Input
0
1
Firmware must wait at least one instruction cycle
after configuring a pin as a digital input before a valid
input value can be read.
Digital Output
0
0
Make sure to disable the analog output function on
the pin if any is present.
TABLE 11-2:
Comments
INPUT VOLTAGE LEVELS FOR PORT OR PIN TOLERATED DESCRIPTION INPUT
Port or Pin
Tolerated Input
Description
(1)
PORTA
PORTB
PORTC(1)
Tolerates input levels above VDD; useful
PORTD(1)
5.5V
for most standard logic.
(1)
PORTE
PORTF(1)
PORTG(1)
PORTA(1)
PORTB
PORTC(1)
VDD
Only VDD input levels are tolerated.
PORTD
PORTE(1)
PORTG
Note 1: Not all of these pins are implemented on 64-pin or 80-pin devices. Refer to Section 1.0 “Device Overview”
for a complete description of port pin implementation.
DS30009996G-page 168
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 11-1:
ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER
U-0
U-0
—
U-0
—
—
U-0
U-0
—
R/W-1
R/W-1
U-0
ANSA(2)
—
—
bit 15
bit 8
R/W-1
R/W-1
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
(1)
ANSA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-9
ANSA: Analog Function Selection bits(2)
1 = Pin is configured in Analog mode; I/O port read is disabled
0 = Pin is configured in Digital mode; I/O port read is enabled
bit 7-6
ANSA: Analog Function Selection bits(1)
1 = Pin is configured in Analog mode; I/O port read is disabled
0 = Pin is configured in Digital mode; I/O port read is enabled
bit 5-0
Unimplemented: Read as ‘0’
Note 1:
2:
These bits are not available in 64-pin and 80-pin devices.
These bits are not available in 64-pin devices.
REGISTER 11-2:
R/W-1
ANSB: PORTB ANALOG FUNCTION SELECTION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSB
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSB
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
ANSB: Analog Function Selection bits
1 = Pin is configured in Analog mode; I/O port read is disabled
0 = Pin is configured in Digital mode; I/O port read is enabled
2010-2014 Microchip Technology Inc.
DS30009996G-page 169
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REGISTER 11-3:
ANSC: PORTC ANALOG FUNCTION SELECTION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-1
U-0
U-0
U-0
U-0
—
—
—
ANSC4(1)
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4
ANSC4: Analog Function Selection bit(1)
1 = Pin is configured in Analog mode; I/O port read is disabled
0 = Pin is configured in Digital mode; I/O port read is enabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
This bit is not available in 64-pin and 80-pin devices.
REGISTER 11-4:
ANSD: PORTD ANALOG FUNCTION SELECTION REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-1
R/W-1
U-0
U-0
—
—
ANSD
bit 15
bit 8
R/W-1
R/W-1
ANSD
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11
ANSD: Analog Function Selection bits
1 = Pin is configured in Analog mode; I/O port read is disabled
0 = Pin is configured in Digital mode; I/O port read is enabled
bit 9-8
Unimplemented: Read as ‘0’
bit 7-6
ANSD: Analog Function Selection bits
1 = Pin is configured in Analog mode; I/O port read is disabled
0 = Pin is configured in Digital mode; I/O port read is enabled
bit 5-0
Unimplemented: Read as ‘0’
DS30009996G-page 170
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
ANSE: PORTE ANALOG FUNCTION SELECTION REGISTER(1)
REGISTER 11-5:
U-0
U-0
—
U-0
—
—
U-0
—
U-0
—
U-0
—
R/W-1
ANSE9
U-0
(2)
—
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
ANSE
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
Unimplemented: Read as ‘0’
bit 9
ANSE9: Analog Function Selection bit(2)
1 = Pin is configured in Analog mode; I/O port read is disabled
0 = Pin is configured in Digital mode; I/O port read is enabled
bit 8
Unimplemented: Read as ‘0’
bit 7-4
ANSE: Analog Function Selection bits(1)
1 = Pin is configured in Analog mode; I/O port read is disabled
0 = Pin is configured in Digital mode; I/O port read is enabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1:
2:
x = Bit is unknown
This register is not available in 64-pin and 80-pin devices.
This bit is unimplemented on 64-pin devices. In 80-pin devices, this bit needs to be cleared to get digital
functionality on RE9.
REGISTER 11-6:
ANSG: PORTG ANALOG FUNCTION SELECTION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-1
R/W-1
ANSG
bit 15
bit 8
R/W-1
R/W-1
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
ANSG
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
Unimplemented: Read as ‘0’
bit 9-6
ANSG: Analog Function Selection bits
1 = Pin is configured in Analog mode; I/O port read is disabled
0 = Pin is configured in Digital mode; I/O port read is enabled
bit 5-0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 171
PIC24FJ128GA310 FAMILY
11.3
Input Change Notification
The Input Change Notification (ICN) function of the I/O
ports allows the PIC24FJ128GA310 family of devices
to generate interrupt requests to the processor in
response to a Change-of-State (COS) on selected
input pins. This feature is capable of detecting input
Change-of-States, even in Sleep mode when the
clocks are disabled. Depending on the device pin
count, there are up to 82 external inputs that may be
selected (enabled) for generating an interrupt request
on a Change-of-State.
Registers, CNEN1 through CNEN6, contain the
interrupt enable control bits for each of the Change
Notification (CN) input pins. Setting any of these bits
enables a CN interrupt for the corresponding pins.
Each CN pin has both a weak pull-up and a weak
pull-down connected to it. The pull-ups act as a current
source that is connected to the pin, while the
pull-downs act as a current sink that is connected to the
pin. These eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups and pull-downs are separately enabled
using the CNPU1 through CNPU6 registers (for
pull-ups) and the CNPD1 through CNPD6 registers (for
pull-downs). Each CN pin has individual control bits for
its pull-up and pull-down. Setting a control bit enables
the weak pull-up or pull-down for the corresponding
pin.
When the internal pull-up is selected, the pin pulls up to
VDD – 1.1V (typical). When the internal pull-down is
selected, the pin pulls down to VSS.
Note:
EXAMPLE 11-1:
MOV
MOV
NOP
BTSS
0xFF00, W0
W0, TRISB
PORTB, #13
EXAMPLE 11-2:
PORT WRITE/READ IN ASSEMBLY
;
;
;
;
Configure PORTB as inputs
and PORTB as outputs
Delay 1 cycle
Next Instruction
PORT WRITE/READ IN ‘C’
TRISB = 0xFF00;
Nop();
If (PORTBbits.RB13){ };
DS30009996G-page 172
Pull-ups on Change Notification pins
should always be disabled whenever the
port pin is configured as a digital output.
// Configure PORTB as inputs and PORTB as outputs
// Delay 1 cycle
// Next Instruction
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
11.4
Peripheral Pin Select (PPS)
A major challenge in general purpose devices is providing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. In an
application that needs to use more than one peripheral
multiplexed on a single pin, inconvenient work arounds
in application code, or a complete redesign, may be the
only option.
The Peripheral Pin Select (PPS) feature provides an
alternative to these choices by enabling the user’s
peripheral set selection and its placement on a wide
range of I/O pins. By increasing the pinout options
available on a particular device, users can better tailor
the microcontroller to their entire application, rather
than trimming the application to fit the device.
The Peripheral Pin Select feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of any one of many digital
peripherals to any one of these I/O pins. PPS is performed in software and generally does not require the
device to be reprogrammed. Hardware safeguards are
included that prevent accidental or spurious changes to
the peripheral mapping once it has been established.
11.4.1
AVAILABLE PINS
The PPS feature is used with a range of up to 44 pins,
depending on the particular device and its pin count.
Pins that support the Peripheral Pin Select feature
include the designation, “RPn” or “RPIn”, in their full pin
designation, where “n” is the remappable pin number.
“RP” is used to designate pins that support both remappable input and output functions, while “RPI” indicates
pins that support remappable input functions only.
PIC24FJ128GA310 family devices support a larger
number of remappable input only pins than remappable
input/output pins. In this device family, there are up to
32 remappable input/output pins, depending on the pin
count of the particular device selected. These pins are
numbered, RP0 through RP31. Remappable input only
pins are numbered above this range, from RPI32 to
RPI43 (or the upper limit for that particular device).
See Table 1-4 for a summary of pinout options in each
package offering.
11.4.2
AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digital
only peripherals. These include general serial communications (UART and SPI), general purpose timer clock
inputs, timer related peripherals (input capture and output compare) and external interrupt inputs. Also
included are the outputs of the comparator module,
since these are discrete digital signals.
2010-2014 Microchip Technology Inc.
PPS is not available for these peripherals:
•
•
•
•
•
•
•
I2C™ (input and output)
Change Notification inputs
RTCC alarm output(s)
EPMP signals (input and output)
LCD signals
Analog inputs
INT0
A key difference between pin select and non-pin select
peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must
always be assigned to a specific I/O pin before it can be
used. In contrast, non-pin select peripherals are always
available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.
11.4.2.1
Peripheral Pin Select Function
Priority
Pin-selectable peripheral outputs (e.g., OCx, UARTx
transmit) will take priority over general purpose digital
functions on a pin, such as EPMP and port I/O. Specialized digital outputs (e.g., USB on USB-enabled
devices) will take priority over PPS outputs on the same
pin. The pin diagrams list peripheral outputs in the
order of priority. Refer to them for priority concerns on
a particular pin.
Unlike PIC24F devices with fixed peripherals,
pin-selectable peripheral inputs will never take ownership of a pin. The pin’s output buffer will be controlled
by the TRISx setting or by a fixed peripheral on the pin.
If the pin is configured in Digital mode then the PPS
input will operate correctly. If an analog function is
enabled on the pin, the PPS input will be disabled.
11.4.3
CONTROLLING PERIPHERAL PIN
SELECT
PPS features are controlled through two sets of Special
Function Registers (SFRs): one to map peripheral
inputs and one to map outputs. Because they are
separately controlled, a particular peripheral’s input
and output (if the peripheral has both) can be placed on
any selectable function pin without constraint.
The association of a peripheral to a peripheral-selectable
pin is handled in two different ways, depending on if an
input or an output is being mapped.
DS30009996G-page 173
PIC24FJ128GA310 FAMILY
11.4.3.1
Input Mapping
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 11-7
through Register 11-26).
TABLE 11-3:
Each register contains two sets of 6-bit fields, with each
set associated with one of the pin-selectable peripherals. Programming a given peripheral’s bit field, with an
appropriate 6-bit value, maps the RPn/RPIn pin with
that value to that peripheral. For any given device, the
valid range of values for any of the bit fields corresponds to the maximum number of Peripheral Pin
Selections supported by the device.
SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
Function Name
Register
Function Mapping
Bits
DSM Modulation Input
MDMIN
RPINR30
MDMIR
DSM Carrier 1 Input
MDCIN1
RPINR31
MDC1R
DSM Carrier 2 Input
MDCIN2
RPINR31
MDC2R
External Interrupt 1
INT1
RPINR0
INT1R
External Interrupt 2
INT2
RPINR1
INT2R
External Interrupt 3
INT3
RPINR1
INT3R
External Interrupt 4
INT4
RPINR2
INT4R
Input Capture 1
IC1
RPINR7
IC1R
Input Capture 2
IC2
RPINR7
IC2R
Input Capture 3
IC3
RPINR8
IC3R
Input Capture 4
IC4
RPINR8
IC4R
Input Capture 5
IC5
RPINR9
IC5R
Input Capture 6
IC6
RPINR9
IC6R
Input Capture 7
IC7
RPINR10
IC7R
Input Name
Output Compare Fault A
OCFA
RPINR11
OCFAR
Output Compare Fault B
OCFB
RPINR11
OCFBR
SPI1 Clock Input
SCK1IN
RPINR20
SCK1R
SPI1 Data Input
SDI1
RPINR20
SDI1R
SS1IN
RPINR21
SS1R
SCK2IN
RPINR22
SCK2R
SPI1 Slave Select Input
SPI2 Clock Input
SPI2 Data Input
SDI2
RPINR22
SDI2R
SPI2 Slave Select Input
SS2IN
RPINR23
SS2R
Timer1 External Clock
T1CK
RPINR23
T1CKR
Timer2 External Clock
T2CK
RPINR3
T2CKR
Timer3 External Clock
T3CK
RPINR3
T3CKR
Timer4 External Clock
T4CK
RPINR4
T4CKR
Timer5 External Clock
T5CK
RPINR4
T5CKR
UART1 Clear-to-Send
U1CTS
RPINR18
U1CTSR
UART1 Receive
UART2 Clear-to-Send
UART2 Receive
UART3 Clear-to-Send
UART3 Receive
UART4 Clear-to-Send
UART4 Receive
Note 1:
U1RX
RPINR18
U1RXR
U2CTS
RPINR19
U2CTSR
U2RX
RPINR19
U2RXR
U3CTS
RPINR21
U3CTSR
U3RX
RPINR17
U3RXR
U4CTS
RPINR27
U4CTSR
U4RX
RPINR27
U4RXR
Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.
DS30009996G-page 174
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
11.4.3.2
Output Mapping
corresponds to one of the peripherals and that
peripheral’s output is mapped to the pin (see
Table 11-4).
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Each register contains two 6-bit fields, with each field
being associated with one RPn pin (see Register 11-27
through Register 11-42). The value of the bit field
TABLE 11-4:
Because of the mapping technique, the list of peripherals for output mapping also includes a null value of
‘000000’. This permits any given pin to remain disconnected from the output of any of the pin-selectable
peripherals.
SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT)
Output Function Number(1)
Function
0
NULL(2)
Null
1
C1OUT
Comparator 1 Output
2
C2OUT
Comparator 2 Output
3
U1TX
UART1 Transmit
UART1 Request-to-Send
4
U1RTS
5
U2TX
6
U2RTS(3)
7
SDO1
SPI1 Data Output
8
SCK1OUT
SPI1 Clock Output
9
SS1OUT
UART2 Transmit
UART2 Request-to-Send
SPI1 Slave Select Output
10
SDO2
SPI2 Data Output
11
SCK2OUT
SPI2 Clock Output
12
SS2OUT
18
OC1
Output Compare 1
19
OC2
Output Compare 2
20
OC3
Output Compare 3
21
OC4
Output Compare 4
22
OC5
Output Compare 5
23
OC6
Output Compare 6
24
OC7
Output Compare 7
28
U3TX
(3)
29
U3RTS
30
U4TX
31
36
Note 1:
2:
3:
(3)
Output Name
U4RTS
(3)
SPI2 Slave Select Output
UART3 Transmit
UART3 Request-to-Send
UART4 Transmit
UART4 Request-to-Send
C3OUT
Comparator 3 Output
37
MDOUT
DSM Modulator Output
38-63
(unused)
NC
Setting the RPORx register with the listed value assigns that output function to the associated RPn pin.
The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function.
IrDA® BCLK functionality uses this output.
2010-2014 Microchip Technology Inc.
DS30009996G-page 175
PIC24FJ128GA310 FAMILY
11.4.3.3
Mapping Limitations
11.4.4.1
The control schema of the Peripheral Pin Select is
extremely flexible. Other than systematic blocks that
prevent signal contention, caused by two physical pins
being configured as the same functional input or two
functional outputs configured as the same pin, there
are no hardware enforced lock outs. The flexibility
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to
drive multiple output pins.
11.4.3.4
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
Mapping Exceptions for
PIC24FJ128GA310 Family Devices
1.
2.
3.
Although the PPS registers theoretically allow for up to
64 remappable I/O pins, not all of these are implemented in all devices. For PIC24FJ128GA310 family
devices, the maximum number of remappable pins
available is 44, which includes 12 input only pins. In
addition, some pins in the RPn and RPIn sequences
are unimplemented in lower pin count devices. The
differences in available remappable pins are
summarized in Table 11-5.
11.4.4.2
Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
• For the RPINRx registers, bit combinations corresponding to an unimplemented pin for a particular
device are treated as invalid; the corresponding
module will not have an input mapped to it. For all
PIC24FJ128GA310 family devices, this includes
all values greater than 43 (‘101011’).
• For RPORx registers, the bit fields corresponding
to an unimplemented pin will also be
unimplemented. Writing to these fields will have
no effect.
11.4.4.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be configured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY
(CW2) Configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit
and re-enable peripheral remapping is to perform a
device Reset.
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the Peripheral
Pin Select registers.
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
TABLE 11-5:
Write 46h to OSCCON.
Write 57h to OSCCON.
Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence, followed by an update
to all control registers, then locked with a second lock
sequence.
When developing applications that use remappable
pins, users should also keep these things in mind:
11.4.4
Control Register Lock
REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ128GA310 FAMILY DEVICES
RP Pins (I/O)
RPI Pins
Device
PIC24FJXXXGA306
Total
Unimplemented
Total
Unimplemented
29
RP5, RP15, RP31
1
RPI32-36, RPI38-43
PIC24FJXXXGA308
31
—
9
RPI32, RPI39, RPI41
PIC24FJXXXGA310
32
—
12
—
DS30009996G-page 176
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
11.4.5
CONSIDERATIONS FOR
PERIPHERAL PIN SELECTION
The ability to control Peripheral Pin Selection introduces several considerations into application design
that could be overlooked. This is particularly true for
several common peripherals that are available only as
remappable peripherals.
The main consideration is that the Peripheral Pin
Selects are not available on default pins in the device’s
default (Reset) state. Since all RPINRx registers reset
to ‘111111’ and all RPORx registers reset to ‘000000’,
all Peripheral Pin Select inputs are tied to VSS and all
Peripheral Pin Select outputs are disconnected.
Note:
In tying Peripheral Pin Select inputs to
RP63, RP63 need not exist on a device for
the registers to be reset to it.
This situation requires the user to initialize the device
with the proper peripheral configuration before any
other application code is executed. Since the IOLOCK
bit resets in the unlocked state, it is not necessary to
execute the unlock sequence after the device has
come out of Reset. For application safety, however, it is
best to set IOLOCK and lock the configuration after
writing to the control registers.
Because the unlock sequence is timing-critical, it must
be executed as an assembly language routine in the
same manner as changes to the oscillator configuration. If the bulk of the application is written in ‘C’, or
another high-level language, the unlock sequence
should be performed by writing in-line assembly.
Choosing the configuration requires the review of all
Peripheral Pin Selects and their pin assignments,
especially those that will not be used in the application.
In all cases, unused pin-selectable peripherals should
be disabled completely. Unused peripherals should
have their inputs assigned to an unused RPn/RPIn pin
function. I/O pins with unused RPn functions should be
configured with the null peripheral output.
The assignment of a peripheral to a particular pin does
not automatically perform any other configuration of the
pin’s I/O circuitry. In theory, this means adding a
pin-selectable output to a pin may mean inadvertently
driving an existing peripheral input when the output is
driven. Users must be familiar with the behavior of
other fixed peripherals that share a remappable pin and
know when to enable or disable them. To be safe, fixed
digital peripherals that share the same pin should be
disabled when not in use.
Along these lines, configuring a remappable pin for a
specific peripheral does not automatically turn that
feature on. The peripheral must be specifically configured for operation, and enabled as if it were tied to a
fixed pin. Where this happens in the application code
(immediately following device Reset and peripheral configuration, or inside the main application routine)
depends on the peripheral and its use in the application.
A final consideration is that Peripheral Pin Select functions neither override analog inputs nor reconfigure
pins with analog functions for digital I/O. If a pin is
configured as an analog input on device Reset, it must
be explicitly reconfigured as digital I/O when used with
a Peripheral Pin Select.
Example 11-3 shows a configuration for bidirectional
communication with flow control using UART1. The
following input and output functions are used:
• Input Functions: U1RX, U1CTS
• Output Functions: U1TX, U1RTS
EXAMPLE 11-3:
CONFIGURING UART1
INPUT AND OUTPUT
FUNCTIONS
// Unlock Registers
asm volatile( "MOV
#OSCCON,
"MOV
#0x46,
"MOV
#0x57,
"MOV.b w2,
"MOV.b w3,
"BCLR OSCCON,#6")
w1
w2
w3
[w1]
[w1]
;
\n"
\n"
\n"
\n"
\n"
// or use C30 built-in macro:
__builtin_write_OSCCONL(OSCCON & 0xbf);
//
// Configure Input Functions (Table 11-2))
// Assign U1RX To Pin RP0
RPINR18bits.U1RXR = 0;
// Assign U1CTS To Pin RP1
RPINR18bits.U1CTSR = 1;
// Configure Output Functions (Table 11-4)
// Assign U1TX To Pin RP2
RPOR1bits.RP2R = 3;
// Assign U1RTS To Pin RP3
RPOR1bits.RP3R = 4;
// Lock Registers
asm volatile
("MOV
"MOV
"MOV
"MOV.b
"MOV.b
"BSET
#OSCCON,
#0x46,
#0x57,
w2,
w3,
OSCCON,
w1 \n"
w2 \n"
w3 \n"
[w1]\n"
[w1]\n"
#6" ;
// or use C30 built-in macro:
// __builtin_write_OSCCONL(OSCCON | 0x40);
2010-2014 Microchip Technology Inc.
DS30009996G-page 177
PIC24FJ128GA310 FAMILY
11.4.6
PERIPHERAL PIN SELECT
REGISTERS
Note:
The PIC24FJ128GA310 family of devices implements
a total of 35 registers for remappable peripheral
configuration:
Input and output register values can only
be changed if IOLOCK (OSCCON) = 0.
See Section 11.4.4.1 “Control Register
Lock” for a specific command sequence.
• Input Remappable Peripheral Registers (20)
• Output Remappable Peripheral Registers (16)
REGISTER 11-7:
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT1R5
INT1R4
INT1R3
INT1R2
INT1R1
INT1R0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
INT1R: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits
bit 7-0
Unimplemented: Read as ‘0’
REGISTER 11-8:
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT3R5
INT3R4
INT3R3
INT3R2
INT3R1
INT3R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT2R5
INT2R4
INT2R3
INT2R2
INT2R1
INT2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
INT3R: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
INT2R: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits
DS30009996G-page 178
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 11-9:
RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT4R5
INT4R4
INT4R3
INT4R2
INT4R1
INT4R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
INT4R: Assign External Interrupt 4 (INT4) to Corresponding RPn or RPIn Pin bits
REGISTER 11-10: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
T3CKR5
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
T2CKR5
T2CKR4
T2CKR3
T2CKR2
T2CKR1
T2CKR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
T3CKR: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
T2CKR: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits
2010-2014 Microchip Technology Inc.
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REGISTER 11-11: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
T5CKR5
T5CKR4
T5CKR3
T5CKR2
T5CKR1
T5CKR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
T4CKR5
T4CKR4
T4CKR3
T4CKR2
T4CKR1
T4CKR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
T5CKR: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
T4CKR: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits
REGISTER 11-12: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
IC2R5
IC2R4
IC2R3
IC2R2
IC2R1
IC2R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
IC1R5
IC1R4
IC1R3
IC1R2
IC1R1
IC1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
IC2R: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IC1R: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits
DS30009996G-page 180
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REGISTER 11-13: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
IC4R5
IC4R4
IC4R3
IC4R2
IC4R1
IC4R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
IC3R5
IC3R4
IC3R3
IC3R2
IC3R1
IC3R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
IC4R: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IC3R: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits
REGISTER 11-14: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
IC6R5
IC6R4
IC6R3
IC6R2
IC6R1
IC6R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
IC5R5
IC5R4
IC5R3
IC5R2
IC5R1
IC5R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
IC6R: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IC5R: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits
2010-2014 Microchip Technology Inc.
DS30009996G-page 181
PIC24FJ128GA310 FAMILY
REGISTER 11-15: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
IC7R5
IC7R4
IC7R3
IC7R2
IC7R1
IC7R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
IC7R: Assign Input Capture 7 (IC7) to Corresponding RPn or RPIn Pin bits
REGISTER 11-16: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
OCFBR5
OCFBR4
OCFBR3
OCFBR2
OCFBR1
OCFBR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
OCFAR5
OCFAR4
OCFAR3
OCFAR2
OCFAR1
OCFAR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
OCFBR: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
OCFAR: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits
DS30009996G-page 182
2010-2014 Microchip Technology Inc.
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REGISTER 11-17: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U3RXR5
U3RXR4
U3RXR3
U3RXR2
U3RXR1
U3RXR0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
U3RXR: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits
bit 7-0
Unimplemented: Read as ‘0’
REGISTER 11-18: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U1CTSR5
U1CTSR4
U1CTSR3
U1CTSR2
U1CTSR1
U1CTSR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U1RXR5
U1RXR4
U1RXR3
U1RXR2
U1RXR1
U1RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
x = Bit is unknown
Unimplemented: Read as ‘0’
bit 13-8
U1CTSR: Assign UART1 Clear-to-Send (U1CTS) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
U1RXR: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits
2010-2014 Microchip Technology Inc.
DS30009996G-page 183
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REGISTER 11-19: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U2CTSR5
U2CTSR4
U2CTSR3
U2CTSR2
U2CTSR1
U2CTSR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U2RXR5
U2RXR4
U2RXR3
U2RXR2
U2RXR1
U2RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
U2CTSR: Assign UART2 Clear-to-Send (U2CTS) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
U2RXR: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits
REGISTER 11-20: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SCK1R5
SCK1R4
SCK1R3
SCK1R2
SCK1R1
SCK1R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SDI1R5
SDI1R4
SDI1R3
SDI1R2
SDI1R1
SDI1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
SCK1R: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
SDI1R: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits
DS30009996G-page 184
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REGISTER 11-21: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U3CTSR5
U3CTSR4
U3CTSR3
U3CTSR2
U3CTSR1
U3CTSR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SS1R5
SS1R4
SS1R3
SS1R2
SS1R1
SS1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
U3CTSR: Assign UART3 Clear-to-Send (U3CTS) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
SS1R: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits
REGISTER 11-22: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SCK2R5
SCK2R4
SCK2R3
SCK2R2
SCK2R1
SCK2R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SDI2R5
SDI2R4
SDI2R3
SDI2R2
SDI2R1
SDI2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
SCK2R: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
SDI2R: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-23: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
T1CKR5
T1CKR4
T1CKR3
T1CKR2
T1CKR1
T1CKR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
SS2R5
SS2R4
SS2R3
SS2R2
SS2R1
SS2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
T1CKR: Assign Timer1 External Clock (T1CK) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
SS2R: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits
REGISTER 11-24: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U4CTSR5
U4CTSR4
U4CTSR3
U4CTSR2
U4CTSR1
U4CTSR0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
U4RXR5
U4RXR4
U4RXR3
U4RXR2
U4RXR1
U4RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
x = Bit is unknown
Unimplemented: Read as ‘0’
bit 13-8
U4CTSR: Assign UART4 Clear-to-Send Input (U4CTS) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
U4RXR: Assign UART4 Receive Input (U4RX) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-25: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
MDMIR5
MDMIR4
MDMIR3
MDMIR2
MDMIR1
MDMIR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
MDMIR: Assign TX Modulation Input (MDMI) to Corresponding RPn or RPIn Pin bits
REGISTER 11-26: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
MDC2R5
MDC2R4
MDC2R3
MDC2R2
MDC2R1
MDC2R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
MDC1R5
MDC1R4
MDC1R3
MDC1R2
MDC21R1
MDC1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
MDC2R: Assign TX Carrier 2 Input (MDCIN2) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
MDC1R: Assign TX Carrier 1 Input (MDCIN1) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-27: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP1R5
RP1R4
RP1R3
RP1R2
RP1R1
RP1R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP0R5
RP0R4
RP0R3
RP0R2
RP0R1
RP0R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP1R: RP1 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP1 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP0R: RP0 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP0 (see Table 11-4 for peripheral function numbers).
REGISTER 11-28: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP3R5
RP3R4
RP3R3
RP3R2
RP3R1
RP3R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP2R5
RP2R4
RP2R3
RP2R2
RP2R1
RP2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP3R: RP3 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP3 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP2R: RP2 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP2 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-29: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
U-0
—
—
R/W-0
RP5R5
(1)
R/W-0
(1)
RP5R4
R/W-0
RP5R3
(1)
R/W-0
RP5R2
(1)
R/W-0
RP5R1
(1)
R/W-0
RP5R0(1)
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP4R5
RP4R4
RP4R3
RP4R2
RP4R1
RP4R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP5R: RP5 Output Pin Mapping bits(1)
Peripheral Output Number n is assigned to pin, RP5 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP4R: RP4 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP4 (see Table 11-4 for peripheral function numbers).
Note 1:
These bits are unimplemented in 64-pin devices; read as ‘0’.
REGISTER 11-30: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP7R5
RP7R4
RP7R3
RP7R2
RP7R1
RP7R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP6R5
RP6R4
RP6R3
RP6R2
RP6R1
RP6R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP7R: RP7 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP7 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP6R: RP6 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP6 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-31: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP9R5
RP9R4
RP9R3
RP9R2
RP9R1
RP9R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP8R5
RP8R4
RP8R3
RP8R2
RP8R1
RP8R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP9R: RP9 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP9 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP8R: RP8 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP8 (see Table 11-4 for peripheral function numbers).
REGISTER 11-32: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP11R5
RP11R4
RP11R3
RP11R2
RP11R1
RP11R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP10R5
RP10R4
RP10R3
RP10R2
RP10R1
RP10R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP11R: RP11 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP11 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP10R: RP10 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP10 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-33: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP13R5
RP13R4
RP13R3
RP13R2
RP13R1
RP13R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP12R5
RP12R4
RP12R3
RP12R2
RP12R1
RP12R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP13R: RP13 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP13 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP12R: RP12 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP12 (see Table 11-4 for peripheral function numbers).
REGISTER 11-34: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP15R5(1)
RP15R4(1)
RP15R3(1)
RP15R2(1)
RP15R1(1)
RP15R0(1)
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP14R5
RP14R4
RP14R3
RP14R2
RP14R1
RP14R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP15R: RP15 Output Pin Mapping bits(1)
Peripheral Output Number n is assigned to pin, RP15 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP14R: RP14 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP14 (see Table 11-4 for peripheral function numbers).
Note 1:
These bits are unimplemented in 64-pin devices; read as ‘0’.
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REGISTER 11-35: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP17R5
RP17R4
RP17R3
RP17R2
RP17R1
RP17R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP16R5
RP16R4
RP16R3
RP16R2
RP16R1
RP16R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP17R: RP17 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP17 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP16R: RP16 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP16 (see Table 11-4 for peripheral function numbers).
REGISTER 11-36: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP19R5
RP19R4
RP19R3
RP19R2
RP19R1
RP19R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP18R5
RP18R4
RP18R3
RP18R2
RP18R1
RP18R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP19R: RP19 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP19 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP18R: RP18 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP18 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-37: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP21R5
RP21R4
RP21R3
RP21R2
RP21R1
RP21R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP20R5
RP20R4
RP20R3
RP20R2
RP20R1
RP20R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP21R: RP21 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP21 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP20R: RP20 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP20 (see Table 11-4 for peripheral function numbers).
REGISTER 11-38: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP23R5
RP23R4
RP23R3
RP23R2
RP23R1
RP23R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP22R5
RP22R4
RP22R3
RP22R2
RP22R1
RP22R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP23R: RP23 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP23 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP22R: RP22 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP22 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-39: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP25R5
RP25R4
RP25R3
RP25R2
RP25R1
RP25R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP24R5
RP24R4
RP24R3
RP24R2
RP24R1
RP24R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP25R: RP25 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP25 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP24R: RP24 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP24 (see Table 11-4 for peripheral function numbers).
REGISTER 11-40: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP27R5
RP27R4
RP27R3
RP27R2
RP27R1
RP27R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP26R5
RP26R4
RP26R3
RP26R2
RP26R1
RP26R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP27R: RP27 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP27 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP26R: RP26 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP26 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-41: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP29R5
RP29R4
RP29R3
RP29R2
RP29R1
RP29R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP28R5
RP28R4
RP28R3
RP28R2
RP28R1
RP28R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP29R: RP29 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP29 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP28R: RP28 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP28 (see Table 11-4 for peripheral function numbers).
REGISTER 11-42: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP31R5(1)
RP31R4(1)
RP31R3(1)
RP31R2(1)
RP31R1(1)
RP31R0(1)
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP30R5
RP30R4
RP30R3
RP30R2
RP30R1
RP30R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP31R: RP31 Output Pin Mapping bits(1)
Peripheral Output Number n is assigned to pin, RP31 (see Table 11-4 for peripheral function numbers).
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP30R: RP30 Output Pin Mapping bits
Peripheral Output Number n is assigned to pin, RP30 (see Table 11-4 for peripheral function numbers).
Note 1:
These bits are unimplemented in 64-pin and 80-pin devices; read as ‘0’.
2010-2014 Microchip Technology Inc.
DS30009996G-page 195
PIC24FJ128GA310 FAMILY
NOTES:
DS30009996G-page 196
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
12.0
Figure 12-1 presents a block diagram of the 16-bit
Timer1 module.
TIMER1
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Timers”
(DS39704)
in
the
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
Note:
The Timer1 module is a 16-bit timer that can operate as
a free-running, interval timer/counter. Timer1 can
operate in three modes:
• 16-Bit Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
To configure Timer1 for operation:
1.
2.
3.
4.
5.
6.
Set the TON bit (= 1).
Select the timer prescaler ratio using the
TCKPS bits.
Set the Clock and Gating modes using the TCS,
TECS and TGATE bits.
Set or clear the TSYNC bit to configure
synchronous or asynchronous operation.
Load the timer period value into the PR1
register.
If interrupts are required, set the Timer1 Interrupt
Enable bit, T1IE. Use the Timer1 Interrupt Priority
bits, T1IP, to set the interrupt priority.
Timer1 also supports these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during CPU Idle and Sleep
modes
• Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TGATE
LPRC
Clock
Input Select
SOSCO
D
Q
1
CK
Q
0
TMR1
SOSCI
Comparator
SOSCEN
Set T1IF
Reset
Equal
PR1
Clock Input Select Detail
T1ECS
2
SOSC
Input
TON
T1CK Input
Gate
Sync
LPRC Input
Gate
Output
TCKPS
2
Prescaler
1, 8, 64, 256
0
Sync
TCY
TGATE
TCS
2010-2014 Microchip Technology Inc.
1
Clock
Output
to TMR1
TSYNC
DS30009996G-page 197
PIC24FJ128GA310 FAMILY
T1CON: TIMER1 CONTROL REGISTER(1)
REGISTER 12-1:
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
TON
—
TSIDL
—
—
—
TIECS1
TIECS0
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timer1 On bit
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9-8
TIECS: Timer1 Extended Clock Source Select bits (selected when TCS = 1)
11 = Unimplemented, do not use
10 = LPRC oscillator
01 = T1CK external clock input
00 = SOSC
bit 7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer1 Clock Source Select bit
1 = Extended clock is selected by the timer
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
Changing the value of T1CON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
DS30009996G-page 198
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
13.0
Note:
TIMER2/3 AND TIMER4/5
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference source. For more information, refer
to
“Timers”
(DS39704)
in
the
“dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet
supersedes the information in the FRM.
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as four independent, 16-bit
timers with selectable operating modes.
To configure Timer2/3 or Timer4/5 for 32-bit operation:
1.
2.
3.
4.
As 32-bit timers, Timer2/3 and Timer4/5 can each
operate in three modes:
• Two independent 16-bit timers with all 16-bit
operating modes (except Asynchronous Counter
mode)
• Single 32-bit timer
• Single 32-bit synchronous counter
They also support these features:
•
•
•
•
•
Timer Gate Operation
Selectable Prescaler Settings
Timer Operation during Idle and Sleep modes
Interrupt on a 32-Bit Period Register Match
ADC Event Trigger (only on Timer2/3 in 32-bit
mode and Timer3 in 16-bit mode)
Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the ADC event trigger.
This trigger is implemented only on Timer2/3 in 32-bit
mode and Timer3 in 16-bit mode. The operating modes
and enabled features are determined by setting the
appropriate bit(s) in the T2CON, T3CON, T4CON and
T5CON registers. T2CON and T4CON are shown in
generic form in Register 13-1; T3CON and T5CON are
shown in Register 13-2.
For 32-bit timer/counter operation, Timer2 and Timer4
are the least significant word; Timer3 and Timer4 are
the most significant word of the 32-bit timers.
Note:
5.
6.
Set the T32 or T45 bit (T2CON or
T4CON = 1).
Select the prescaler ratio for Timer2 or Timer4
using the TCKPS bits.
Set the Clock and Gating modes using the TCS
and TGATE bits. If TCS is set to an external
clock, RPINRx (TxCK) must be configured to
an available RPn/RPIn pin. For more information, see Section 11.4 “Peripheral Pin Select
(PPS)”.
Load the timer period value. PR3 (or PR5) will
contain the most significant word (msw) of the
value, while PR2 (or PR4) contains the least
significant word (lsw).
If interrupts are required, set the interrupt enable
bit, T3IE or T5IE. Use the priority bits, T3IP
or T5IP, to set the interrupt priority. Note
that while Timer2 or Timer4 controls the timer, the
interrupt appears as a Timer3 or Timer5 interrupt.
Set the TON bit (= 1).
The timer value, at any point, is stored in the register
pair, TMR (or TMR). TMR3 (TMR5) always
contains the most significant word of the count, while
TMR2 (TMR4) contains the least significant word.
To configure any of the timers for individual 16-bit
operation:
1.
2.
3.
4.
5.
6.
Clear the T32 bit corresponding to that timer
(T2CON for Timer2 and Timer3 or
T4CON for Timer4 and Timer5).
Select the timer prescaler ratio using the
TCKPS bits.
Set the Clock and Gating modes using the TCS
and TGATE bits. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
Load the timer period value into the PRx register.
If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP, to set
the interrupt priority.
Set the TON (TxCON = 1) bit.
For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 or Timer5 interrupt flags.
2010-2014 Microchip Technology Inc.
DS30009996G-page 199
PIC24FJ128GA310 FAMILY
FIGURE 13-1:
TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
T2CK
(T4CK)
1x
Gate
Sync
01
TCY
00
TON
TCKPS
2
Prescaler
1, 8, 64, 256
TGATE
TGATE(2)
TCS(2)
Q
1
Set T3IF (T5IF)
Q
0
PR3
(PR5)
ADC Event Trigger(3)
Equal
D
CK
PR2
(PR4)
Comparator
MSB
LSB
TMR3
(TMR5)
Reset
TMR2
(TMR4)
Sync
16
Read TMR2 (TMR4)
(1)
Write TMR2 (TMR4)(1)
16
TMR3HLD
(TMR5HLD)
16
Data Bus
Note 1:
2:
3:
The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode.
DS30009996G-page 200
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 13-2:
TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TON
T2CK
(T4CK)
TCKPS
2
1x
Gate
Sync
Prescaler
1, 8, 64, 256
01
00
TGATE
TCS(1)
TCY
1
Set T2IF (T4IF)
0
Reset
Equal
Q
D
Q
CK
TGATE(1)
TMR2 (TMR4)
Sync
Comparator
PR2 (PR4)
The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
Note 1:
FIGURE 13-3:
TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
T3CK
(T5CK)
Sync
1x
TON
TCKPS
2
Prescaler
1, 8, 64, 256
01
00
TGATE
TCY
1
Set T3IF (T5IF)
Q
D
Q
CK
TCS(1)
TGATE(1)
0
Reset
ADC Event Trigger(2)
Equal
TMR3 (TMR5)
Comparator
PR3 (PR5)
Note 1:
2:
The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
The ADC event trigger is available only on Timer3.
2010-2014 Microchip Technology Inc.
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TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3)
REGISTER 13-1:
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
—
TGATE
R/W-0
TCKPS1
R/W-0
R/W-0
TCKPS0
T32(1)
U-0
R/W-0
U-0
—
TCS(2)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timerx On bit
When TxCON = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When TxCON = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
T32: 32-Bit Timer Mode Select bit(1)
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timerx Clock Source Select bit(2)
1 = External clock is from pin, TxCK (on the rising edge)
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
In T4CON, the T45 bit is implemented instead of T32 to select 32-bit mode. In 32-bit mode, the T3CON or
T5CON control bits do not affect 32-bit timer operation.
If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. For more information, see
Section 11.4 “Peripheral Pin Select (PPS)”.
Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
DS30009996G-page 202
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 13-2:
R/W-0
TON
TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3)
U-0
(1)
—
R/W-0
TSIDL
(1)
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
—
TGATE(1)
TCKPS1(1)
TCKPS0(1)
—
—
TCS(1,2)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
TON: Timery On bit(1)
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timery Stop in Idle Mode bit(1)
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3-2
Unimplemented: Read as ‘0’
bit 1
TCS: Timery Clock Source Select bit(1,2)
1 = External clock from pin, TyCK (on the rising edge)
0 = Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
x = Bit is unknown
When 32-bit operation is enabled (T2CON or T4CON = 1), these bits have no effect on Timery
operation; all timer functions are set through T2CON and T4CON.
If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
2010-2014 Microchip Technology Inc.
DS30009996G-page 203
PIC24FJ128GA310 FAMILY
NOTES:
DS30009996G-page 204
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
14.0
INPUT CAPTURE WITH
DEDICATED TIMERS
Note:
14.1
14.1.1
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Input Capture with Dedicated Timer”
(DS39722) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
Devices in the PIC24FJ128GA310 family contain
seven independent input capture modules. Each of the
modules offers a wide range of configuration and
operating options for capturing external pulse events
and generating interrupts.
Key features of the input capture module include:
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 30 user-selectable
sync/trigger sources available
• A 4-level FIFO buffer for capturing and holding
timer values for several events
• Configurable interrupt generation
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
The module is controlled through two registers: ICxCON1
(Register 14-1) and ICxCON2 (Register 14-2). A general
block diagram of the module is shown in Figure 14-1.
FIGURE 14-1:
SYNCHRONOUS AND TRIGGER
MODES
When the input capture module operates in a
Free-Running mode, the internal 16-bit counter,
ICxTMR, counts up continuously, wrapping around
from FFFFh to 0000h on each overflow. Its period is
synchronized to the selected external clock source.
When a capture event occurs, the current 16-bit value
of the internal counter is written to the FIFO buffer.
In Synchronous mode, the module begins capturing
events on the ICx pin as soon as its selected clock
source is enabled. Whenever an event occurs on the
selected sync source, the internal counter is reset. In
Trigger mode, the module waits for a Sync event from
another internal module to occur before allowing the
internal counter to run.
Standard, free-running operation is selected by setting
the SYNCSELx bits (ICxCON2) to ‘00000’ and
clearing the ICTRIG bit (ICxCON2). Synchronous
and Trigger modes are selected any time the
SYNCSELx bits are set to any value except ‘00000’.
The ICTRIG bit selects either Synchronous or Trigger
mode; setting the bit selects Trigger mode operation. In
both modes, the SYNCSELx bits determine the
sync/trigger source.
When the SYNCSELx bits are set to ‘00000’ and
ICTRIG is set, the module operates in Software Trigger
mode. In this case, capture operations are started by
manually setting the TRIGSTAT bit (ICxCON2).
INPUT CAPTURE x BLOCK DIAGRAM
ICM
ICx Pin(1)
General Operating Modes
ICI
Event and
Interrupt
Logic
Edge Detect Logic
and
Clock Synchronizer
Prescaler
Counter
1:1/4/16
Set ICxIF
ICTSEL
Increment
Clock
Select
ICx Clock
Sources
Sync and
Trigger Sources
Sync and
Trigger
Logic
16
ICxTMR
16
16
Reset
ICxBUF
SYNCSEL
Trigger
Note 1:
4-Level FIFO Buffer
ICOV, ICBNE
System Bus
The ICx inputs must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
2010-2014 Microchip Technology Inc.
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14.1.2
CASCADED (32-BIT) MODE
By default, each module operates independently with
its own 16-bit timer. To increase resolution, adjacent
even and odd modules can be configured to function as
a single 32-bit module. (For example, Modules 1 and 2
are paired, as are Modules 3 and 4, and so on.) The
odd numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs and the even
module (ICy) provides the Most Significant 16 bits.
Wraparounds of the ICx registers cause an increment
of their corresponding ICy registers.
Cascaded operation is configured in hardware by
setting the IC32 bits (ICxCON2) for both modules.
14.2
Capture Operations
The input capture module can be configured to capture
timer values and generate interrupts on rising edges on
ICx or all transitions on ICx. Captures can be configured to occur on all rising edges or just some (every 4th
or 16th). Interrupts can be independently configured to
generate on each event or a subset of events.
For 32-bit cascaded operations, the setup procedure is
slightly different:
1.
2.
3.
4.
5.
Note:
To set up the module for capture operations:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Configure the ICx input for one of the available
Peripheral Pin Select pins.
If Synchronous mode is to be used, disable the
sync source before proceeding.
Make sure that any previous data has been
removed from the FIFO by reading ICxBUF until
the ICBNE bit (ICxCON1) is cleared.
Set the SYNCSELx bits (ICxCON2) to the
desired sync/trigger source.
Set the ICTSELx bits (ICxCON1) for the
desired clock source.
Set the ICIx bits (ICxCON1) to the desired
interrupt frequency
Select Synchronous or Trigger mode operation:
a) Check that the SYNCSELx bits are not set
to ‘00000’.
b) For Synchronous mode, clear the ICTRIG
bit (ICxCON2).
c) For Trigger mode, set ICTRIG, and clear the
TRIGSTAT bit (ICxCON2).
Set the ICMx bits (ICxCON1) to the
desired operational mode.
Enable the selected sync/trigger source.
DS30009996G-page 206
Set the IC32 bits for both modules
(ICyCON2) and (ICxCON2), enabling
the even numbered module first. This ensures
the modules will start functioning in unison.
Set the ICTSELx and SYNCSELx bits for both
modules to select the same sync/trigger and time
base source. Set the even module first, then the
odd module. Both modules must use the same
ICTSELx and SYNCSELx bits settings.
Clear the ICTRIG bit of the even module
(ICyCON2). This forces the module to run in
Synchronous mode with the odd module,
regardless of its trigger setting.
Use the odd module’s ICIx bits (ICxCON1)
to set the desired interrupt frequency.
Use the ICTRIG bit of the odd module
(ICxCON2) to configure Trigger or
Synchronous mode operation.
6.
For Synchronous mode operation, enable
the sync source as the last step. Both
input capture modules are held in Reset
until the sync source is enabled.
Use the ICMx bits of the odd module
(ICxCON1) to set the desired Capture
mode.
The module is ready to capture events when the time
base and the sync/trigger source are enabled. When
the ICBNE bit (ICxCON1) becomes set, at least
one capture value is available in the FIFO. Read input
capture values from the FIFO until the ICBNE clears
to ‘0’.
For 32-bit operation, read both the ICxBUF and
ICyBUF for the full 32-bit timer value (ICxBUF for the
lsw, ICyBUF for the msw). At least one capture value is
available in the FIFO buffer when the odd module’s
ICBNE bit (ICxCON1) becomes set. Continue to
read the buffer registers until ICBNE is cleared
(performed automatically by hardware).
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 14-1:
ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R-0, HSC
R-0, HSC
R/W-0
R/W-0
R/W-0
—
ICI1
ICI0
ICOV
ICBNE
ICM2(1)
ICM1(1)
ICM0(1)
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
ICSIDL: Input Capture x Module Stop in Idle Control bit
1 = Input capture module halts in CPU Idle mode
0 = Input capture module continues to operate in CPU Idle mode
bit 12-10
ICTSEL: Input Capture x Timer Select bits
111 = System clock (FOSC/2)
110 = Reserved
101 = Reserved
100 = Timer1
011 = Timer5
010 = Timer4
001 = Timer2
000 = Timer3
bit 9-7
Unimplemented: Read as ‘0’
bit 6-5
ICI: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4
ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input capture overflow has occurred
0 = No input capture overflow has occurred
bit 3
ICBNE: Input Capture x Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0
ICM: Input Capture x Mode Select bits(1)
111 = Interrupt mode: Input capture functions as an interrupt pin only when the device is in Sleep or
Idle mode (rising edge detect only, all other control bits are not applicable)
110 = Unused (module is disabled)
101 = Prescaler Capture mode: Capture on every 16th rising edge
100 = Prescaler Capture mode: Capture on every 4th rising edge
011 = Simple Capture mode: Capture on every rising edge
010 = Simple Capture mode: Capture on every falling edge
001 = Edge Detect Capture mode: Capture on every edge (rising and falling); ICI bits do not
control interrupt generation for this mode
000 = Input capture module is turned off
Note 1:
The ICx input must also be configured to an available RPn/RPIn pin. For more information, see
Section 11.4 “Peripheral Pin Select (PPS)”.
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REGISTER 14-2:
ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
IC32
bit 15
bit 8
R/W-0
R/W-0, HS
U-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
ICTRIG
TRIGSTAT
—
SYNCSEL4
SYNCSEL3
SYNCSEL2
SYNCSEL1
SYNCSEL0
bit 7
bit 0
Legend:
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
IC32: Cascade Two IC Modules Enable bit (32-bit operation)
1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules)
0 = ICx functions independently as a 16-bit module
bit 7
ICTRIG: ICx Sync/Trigger Select bit
1 = Trigger ICx from the source designated by the SYNCSELx bits
0 = Synchronize ICx with the source designated by the SYNCSELx bits
bit 6
TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running (set in hardware, can be set in software)
0 = Timer source has not been triggered and is being held clear
bit 5
Unimplemented: Read as ‘0’
Note 1:
2:
Use these inputs as trigger sources only and never as sync sources.
Never use an IC module as its own trigger source, by selecting this mode.
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REGISTER 14-2:
bit 4-0
Note 1:
2:
ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)
SYNCSEL: Synchronization/Trigger Source Selection bits
11111 = Reserved
11110 = Reserved(2)
11101 = Reserved(2)
11100 = CTMU(1)
11011 = ADC(1)
11010 = Comparator 3(1)
11001 = Comparator 2(1)
11000 = Comparator 1(1)
10111 = Reserved(2)
10110 = Input Capture 7(2)
10101 = Input Capture 6(2)
10100 = Input Capture 5(2)
10011 = Input Capture 4(2)
10010 = Input Capture 3(2)
10001 = Input Capture 2(2)
10000 = Input Capture 1(2)
01111 = Timer5
01110 = Timer4
01101 = Timer3
01100 = Timer2
01011 = Timer1
01010 = Reserved
01001 = Reserved
01000 = Reserved
00111 = Output Compare 7
•
•
•
00010 = Output Compare 2
00001 = Output Compare 1
00000 = Not synchronized to any other module
Use these inputs as trigger sources only and never as sync sources.
Never use an IC module as its own trigger source, by selecting this mode.
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NOTES:
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15.0
Note:
OUTPUT COMPARE WITH
DEDICATED TIMERS
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to “Output Compare with Dedicated Timer”
(DS39723) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
Devices in the PIC24FJ128GA310 family all feature
seven independent output compare modules. Each of
these modules offers a wide range of configuration and
operating options for generating pulse trains on internal
device events, and can produce Pulse-Width
Modulated waveforms for driving power applications.
Key features of the output compare module include:
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 31 user-selectable
trigger/sync sources available
• Two separate Period registers (a main register,
OCxR, and a secondary register, OCxRS) for
greater flexibility in generating pulses of varying
widths
• Configurable for single pulse or continuous pulse
generation on an output event, or continuous
PWM waveform generation
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
15.1
15.1.1
In Synchronous mode, the module begins performing
its compare or PWM operation as soon as its selected
clock source is enabled. Whenever an event occurs on
the selected sync source, the module’s internal counter
is reset. In Trigger mode, the module waits for a sync
event from another internal module to occur before
allowing the counter to run.
Free-Running mode is selected by default or any time
that the SYNCSELx bits (OCxCON2) are set to
‘00000’. Synchronous or Trigger modes are selected
any time the SYNCSELx bits are set to any value
except ‘00000’. The OCTRIG bit (OCxCON2)
selects either Synchronous or Trigger mode; setting the
bit selects Trigger mode operation. In both modes, the
SYNCSELx bits determine the sync/trigger source.
15.1.2
CASCADED (32-BIT) MODE
By default, each module operates independently with
its own set of 16-Bit Timer and Duty Cycle registers. To
increase resolution, adjacent even and odd modules
can be configured to function as a single 32-bit module.
(For example, Modules 1 and 2 are paired, as are
Modules 3 and 4, and so on.) The odd numbered
module (OCx) provides the Least Significant 16 bits of
the 32-bit register pairs and the even module (OCy)
provides the Most Significant 16 bits. Wraparounds of
the OCx registers cause an increment of their
corresponding OCy registers.
Cascaded operation is configured in hardware by setting the OC32 bit (OCxCON2) for both modules.
For more details on cascading, refer to “Output
Compare with Dedicated Timer” (DS39723) in the
“dsPIC33/PIC24 Family Reference Manual”.
General Operating Modes
SYNCHRONOUS AND TRIGGER
MODES
When the output compare module operates in a
Free-Running mode, the internal 16-bit counter,
OCxTMR, counts up continuously, wrapping around
from 0xFFFF to 0x0000 on each overflow. Its period is
synchronized to the selected external clock source.
Compare or PWM events are generated each time a
match between the internal counter and one of the
Period registers occurs.
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FIGURE 15-1:
OUTPUT COMPARE x BLOCK DIAGRAM (16-BIT MODE)
OCMx
OCINV
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLT
OCFLT
DCB
OCxCON1
OCTSELx
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
Clock
Select
OCx Clock
Sources
OCxCON2
OCxR and
DCB
Increment
Comparator
OCx Output and
OCxTMR
Fault Logic
Reset
Match Event
Trigger and
Sync Sources
Trigger and
Sync Logic
Comparator
OCx Pin(1)
Match Event
Match Event
OCFA/OCFB(2)
OCxRS
Reset
OCx Interrupt
Note 1:
2:
15.2
The OCx outputs must be assigned to an available RPn pin before use. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
Compare Operations
In Compare mode (Figure 15-1), the output compare
module can be configured for single-shot or continuous
pulse generation. It can also repeatedly toggle an
output pin on each timer event.
To set up the module for compare operations:
1.
2.
Configure the OCx output for one of the
available Peripheral Pin Select pins.
Calculate the required values for the OCxR and
(for Double Compare modes) OCxRS Duty
Cycle registers:
a) Determine the instruction clock cycle time.
Take into account the frequency of the
external clock to the timer source (if one is
used) and the timer prescaler settings.
b) Calculate time to the rising edge of the
output pulse relative to the timer start value
(0000h).
c) Calculate the time to the falling edge of the
pulse based on the desired pulse width and
the time to the rising edge of the pulse.
DS30009996G-page 212
3.
4.
5.
6.
7.
8.
Write the rising edge value to OCxR and the
falling edge value to OCxRS.
Set the Timer Period register, PRy, to a value
equal to or greater than the value in OCxRS.
Set the OCM bits for the appropriate
compare operation (= 0xx).
For Trigger mode operations, set OCTRIG to
enable Trigger mode. Set or clear TRIGMODE
to configure trigger operation and TRIGSTAT to
select a hardware or software trigger. For
Synchronous mode, clear OCTRIG.
Set the SYNCSEL bits to configure the
trigger or synchronization source. If free-running
timer operation is required, set the SYNCSELx
bits to ‘00000’ (no sync/trigger source).
Select the time base source with the
OCTSEL bits. If necessary, set the TON bit
for the selected timer, which enables the compare time base to count. Synchronous mode
operation starts as soon as the time base is
enabled; Trigger mode operation starts after a
trigger source event occurs.
2010-2014 Microchip Technology Inc.
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For 32-bit cascaded operation, these steps are also
necessary:
1.
2.
3.
4.
5.
6.
Set the OC32 bits for both registers
(OCyCON2) and (OCxCON2). Enable
the even numbered module first to ensure the
modules will start functioning in unison.
Clear the OCTRIG bit of the even module
(OCyCON2), so the module will run in
Synchronous mode.
Configure the desired output and Fault settings
for OCy.
Force the output pin for OCx to the output state
by clearing the OCTRIS bit.
If Trigger mode operation is required, configure
the trigger options in OCx by using the OCTRIG
(OCxCON2), TRIGMODE (OCxCON1)
and SYNCSELx (OCxCON2) bits.
Configure the desired Compare or PWM mode
of operation (OCM) for OCy first, then for
OCx.
15.3
In PWM mode, the output compare module can be
configured for edge-aligned or center-aligned pulse
waveform generation. All PWM operations are
double-buffered (buffer registers are internal to the
module and are not mapped into SFR space).
To configure the output compare module for PWM
operation:
1.
2.
3.
4.
Depending on the output mode selected, the module
holds the OCx pin in its default state and forces a transition to the opposite state when OCxR matches the
timer. In Double Compare modes, OCx is forced back
to its default state when a match with OCxRS occurs.
The OCxIF interrupt flag is set after an OCxR match in
Single Compare modes and after each OCxRS match
in Double Compare modes.
5.
Single-shot pulse events only occur once, but may be
repeated by simply rewriting the value of the
OCxCON1 register. Continuous pulse events continue
indefinitely until terminated.
8.
6.
7.
9.
Configure the OCx output for one of the
available Peripheral Pin Select pins.
Calculate the desired duty cycles and load them
into the OCxR register.
Calculate the desired period and load it into the
OCxRS register.
Select the current OCx as the synchronization
source by writing 0x1F to the SYNCSEL
bits (OCxCON2) and ‘0’ to the OCTRIG bit
(OCxCON2).
Select a clock source by writing to the
OCTSEL bits (OCxCON).
Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin
utilization.
Select the desired PWM mode with the
OCM bits (OCxCON1).
Appropriate Fault inputs may be enabled by
using the ENFLT bits as described in
Register 15-1.
If a timer is selected as a clock source, set the
selected timer prescale value. The selected
timer’s prescaler output is used as the clock
input for the OCx timer and not the selected
timer output.
Note:
2010-2014 Microchip Technology Inc.
Pulse-Width Modulation (PWM)
Mode
This peripheral contains input and output
functions that may need to be configured
by the Peripheral Pin Select. See
Section 11.4 “Peripheral Pin Select
(PPS)” for more information.
DS30009996G-page 213
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FIGURE 15-2:
OUTPUT COMPARE x BLOCK DIAGRAM (DOUBLE-BUFFERED,
16-BIT PWM MODE)
OCxCON1
OCMx
OCINV
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLT
OCFLT
DCB
OCxCON2
OCTSELx
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
OCxR and
DCB
Rollover/Reset
OCxR and
DCB Buffers
OCx Pin(1)
Clock
Select
OC Clock
Sources
Increment
Comparator
OCxTMR
Reset
Trigger and
Sync Logic
Trigger and
Sync Sources
Match Event
Comparator
Match
Event
OCx Output and
Rollover
Fault Logic
OCFA/OCFB(2)
Match
Event
OCxRS Buffer
Rollover/Reset
OCxRS
OCx Interrupt
Reset
Note 1:
2:
15.3.1
The OCx outputs must be assigned to an available RPn pin before use. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
PWM PERIOD
The PWM period is specified by writing to PRy, the
Timer Period register. The PWM period can be
calculated using Equation 15-1.
CALCULATING THE PWM PERIOD(1)
EQUATION 15-1:
PWM Period = [(PRy) + 1 • TCY • (Timer Prescale Value)
where:
PWM Frequency = 1/[PWM Period]
Note 1:
Note:
Based on TCY = TOSC * 2; Doze mode and PLL are disabled.
A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of
7, written into the PRy register, will yield a period consisting of 8 time base cycles.
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15.3.2
PWM DUTY CYCLE
Some important boundary parameters of the PWM duty
cycle include:
The PWM duty cycle is specified by writing to the
OCxRS and OCxR registers. The OCxRS and OCxR
registers can be written to at any time, but the duty
cycle value is not latched until a match between PRy
and TMRy occurs (i.e., the period is complete). This
provides a double buffer for the PWM duty cycle and is
essential for glitchless PWM operation.
log10
Maximum PWM Resolution (bits) =
FCY
( FPWM • (Timer Prescale Value))
log10(2)
bits
Based on FCY = FOSC/2; Doze mode and PLL are disabled.
EXAMPLE 15-1:
1.
See Example 15-1 for PWM mode timing details.
Table 15-1 and Table 15-2 show example PWM
frequencies and resolutions for a device operating at
4 MIPS and 10 MIPS, respectively.
CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
EQUATION 15-2:
Note 1:
• If OCxR, OCxRS, and PRy are all loaded with
0000h, the OCx pin will remain low (0% duty
cycle).
• If OCxRS is greater than PRy, the pin will remain
high (100% duty cycle).
PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)
Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL
(32 MHz device clock rate) and a Timer2 prescaler setting of 1:1.
TCY = 2 • TOSC = 62.5 ns
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 ms
PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value)
19.2 ms = (PR2 + 1) • 62.5 ns • 1
PR2 = 306
2.
Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz
device clock rate:
PWM Resolution = log10 (FCY/FPWM)/log102) bits
= (log10 (16 MHz/52.08 kHz)/log102) bits
= 8.3 bits
Note 1:
Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
TABLE 15-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
PWM Frequency
7.6 Hz
61 Hz
122 Hz
977 Hz
3.9 kHz
31.3 kHz
125 kHz
Timer Prescaler Ratio
8
1
1
1
1
1
1
Period Register Value
FFFFh
FFFFh
7FFFh
0FFFh
03FFh
007Fh
001Fh
16
16
15
12
10
7
5
Resolution (bits)
Note 1:
Based on FCY = FOSC/2; Doze mode and PLL are disabled.
TABLE 15-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
PWM Frequency
30.5 Hz
244 Hz
488 Hz
3.9 kHz
15.6 kHz
125 kHz
500 kHz
Timer Prescaler Ratio
8
1
1
1
1
1
1
Period Register Value
FFFFh
FFFFh
7FFFh
0FFFh
03FFh
007Fh
001Fh
16
16
15
12
10
7
5
Resolution (bits)
Note 1:
Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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REGISTER 15-1:
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
OCSIDL
OCTSEL2
OCTSEL1
OCTSEL0
ENFLT2(2)
ENFLT1(2)
bit 15
bit 8
R/W-0
R/W-0, HSC
R/W-0, HSC
R/W-0, HSC
R/W-0
R/W-0
R/W-0
R/W-0
ENFLT0(2)
OCFLT2(2,3)
OCFLT1(2,4)
OCFLT0(2,4)
TRIGMODE
OCM2(1)
OCM1(1)
OCM0(1)
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 12-10
OCTSEL: Output Compare x Timer Select bits
111 = Peripheral clock (FCY)
110 = Reserved
101 = Reserved
100 = Timer1 clock (only synchronous clock is supported)
011 = Timer5 clock
010 = Timer4 clock
001 = Timer3 clock
000 = Timer2 clock
bit 9
ENFLT2: Fault Input 2 Enable bit(2)
1 = Fault 2 (Comparator 1/2/3 out) is enabled(3)
0 = Fault 2 is disabled
bit 8
ENFLT1: Fault Input 1 Enable bit(2)
1 = Fault 1 (OCFB pin) is enabled(4)
0 = Fault 1 is disabled
bit 7
ENFLT0: Fault Input 0 Enable bit(2)
1 = Fault 0 (OCFA pin) is enabled(4)
0 = Fault 0 is disabled
bit 6
OCFLT2: PWM Fault 2 (Comparator 1/2/3) Condition Status bit(2,3)
1 = PWM Fault 2 has occurred
0 = No PWM Fault 2 has occurred
bit 5
OCFLT1: PWM Fault 1 (OCFB pin) Condition Status bit(2,4)
1 = PWM Fault 1 has occurred
0 = No PWM Fault 1 has occurred
Note 1:
2:
3:
4:
x = Bit is unknown
The OCx output must also be configured to an available RPn pin. For more information, see Section 11.4
“Peripheral Pin Select (PPS)”.
The Fault input enable and Fault status bits are valid when OCM = 111 or 110.
The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6
channels; Comparator 3 output controls the OC7-OC9 channels.
The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information,
see Section 11.4 “Peripheral Pin Select (PPS)”.
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REGISTER 15-1:
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 4
OCFLT0: PWM Fault 0 (OCFA pin) Condition Status bit(2,4)
1 = PWM Fault 0 has occurred
0 = No PWM Fault 0 has occurred
bit 3
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is only cleared by software
bit 2-0
OCM: Output Compare x Mode Select bits(1)
111 = Center-Aligned PWM mode on OCx(2)
110 = Edge-Aligned PWM mode on OCx(2)
101 = Double Compare Continuous Pulse mode: Initialize the OCx pin low; toggle the OCx state
continuously on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initialize the OCx pin low; toggle the OCx state on matches
of OCxR and OCxRS for one cycle
011 = Single Compare Continuous Pulse mode: Compare events continuously toggle the OCx pin
010 = Single Compare Single-Shot mode: Initialize OCx pin high; compare event forces the OCx pin low
001 = Single Compare Single-Shot mode: Initialize OCx pin low; compare event forces the OCx pin high
000 = Output compare channel is disabled
Note 1:
2:
3:
4:
The OCx output must also be configured to an available RPn pin. For more information, see Section 11.4
“Peripheral Pin Select (PPS)”.
The Fault input enable and Fault status bits are valid when OCM = 111 or 110.
The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6
channels; Comparator 3 output controls the OC7-OC9 channels.
The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information,
see Section 11.4 “Peripheral Pin Select (PPS)”.
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REGISTER 15-2:
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
FLTMD
FLTOUT
FLTTRIEN
OCINV
—
DCB1(3)
DCB0(3)
OC32
bit 15
bit 8
R/W-0
R/W-0, HS
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
OCTRIG
TRIGSTAT
OCTRIS
SYNCSEL4
SYNCSEL3
SYNCSEL2
SYNCSEL1
SYNCSEL0
bit 7
bit 0
Legend:
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FLTMD: Fault Mode Select bit
1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is
cleared in software
0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts
bit 14
FLTOUT: Fault Out bit
1 = PWM output is driven high on a Fault
0 = PWM output is driven low on a Fault
bit 13
FLTTRIEN: Fault Output State Select bit
1 = Pin is forced to an output on a Fault condition
0 = Pin I/O condition is unaffected by a Fault
bit 12
OCINV: OCMP Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
bit 11
Unimplemented: Read as ‘0’
bit 10-9
DCB: PWM Duty Cycle Least Significant bits(3)
11 = Delay OCx falling edge by ¾ of the instruction cycle
10 = Delay OCx falling edge by ½ of the instruction cycle
01 = Delay OCx falling edge by ¼ of the instruction cycle
00 = OCx falling edge occurs at the start of the instruction cycle
bit 8
OC32: Cascade Two OC Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled
0 = Cascade module operation is disabled
bit 7
OCTRIG: OCx Trigger/Sync Select bit
1 = Trigger OCx from the source designated by the SYNCSELx bits
0 = Synchronize OCx with the source designated by the SYNCSELx bits
bit 6
TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
bit 5
OCTRIS: OCx Output Pin Direction Select bit
1 = OCx pin is tri-stated
0 = Output Compare Peripheral x is connected to an OCx pin
Note 1:
2:
3:
Never use an OCx module as its own trigger source, either by selecting this mode or another equivalent
SYNCSELx setting.
Use these inputs as trigger sources only and never as sync sources.
The DCB bits are double-buffered in PWM modes only (OCM (OCxCON1) = 111, 110).
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REGISTER 15-2:
bit 4-0
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
SYNCSEL: Trigger/Synchronization Source Selection bits
11111 = This OC module(1)
11110 = Input Capture 9(2)
11101 = Input Capture 6(2)
11100 = CTMU(2)
11011 = ADC(2)
11010 = Comparator 3(2)
11001 = Comparator 2(2)
11000 = Comparator 1(2)
10111 = Input Capture 4(2)
10110 = Input Capture 3(2)
10101 = Input Capture 2(2)
10100 = Input Capture 1(2)
10011 = Input Capture 8(2)
10010 = Input Capture 7(2)
1000x = Reserved
01111 = Timer5
01110 = Timer4
01101 = Timer3
01100 = Timer2
01011 = Timer1
01010 = Input Capture 5(2)
01001 = Output Compare 9(1)
01000 = Output Compare 8(1)
00111 = Output Compare 7(1)
00110 = Output Compare 6(1)
00101 = Output Compare 5(1)
00100 = Output Compare 4(1)
00011 = Output Compare 3(1)
00010 = Output Compare 2(1)
00001 = Output Compare 1(1)
00000 = Not synchronized to any other module
Note 1:
2:
3:
Never use an OCx module as its own trigger source, either by selecting this mode or another equivalent
SYNCSELx setting.
Use these inputs as trigger sources only and never as sync sources.
The DCB bits are double-buffered in PWM modes only (OCM (OCxCON1) = 111, 110).
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NOTES:
DS30009996G-page 220
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16.0
Note:
SERIAL PERIPHERAL
INTERFACE (SPI)
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Serial Peripheral Interface (SPI)”
(DS39699) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift
registers, display drivers, ADC Converters, etc. The
SPI module is compatible with the SPI and SIOP
Motorola® interfaces. All PIC24FJ128GA310 family
devices include two SPI modules.
The module supports operation in two buffer modes. In
Standard mode, data is shifted through a single serial
buffer. In Enhanced Buffer mode, data is shifted
through an 8-level FIFO buffer.
Note:
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
The SPI serial interface consists of four pins:
•
•
•
•
SDIx: Serial Data Input
SDOx: Serial Data Output
SCKx: Shift Clock Input or Output
SSx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPI module can be configured to operate using 2,
3 or 4 pins. In the 3-pin mode, SSx is not used. In the
2-pin mode, both SDOx and SSx are not used.
Block diagrams of the module in Standard and
Enhanced modes are shown in Figure 16-1 and
Figure 16-2.
Note:
In this section, the SPI modules are
referred to together as SPIx or separately
as SPI1 or SPI2. Special Function Registers will follow a similar notation. For
example, SPIxCON1 and SPIxCON2
refer to the control registers for any of the
2 SPI modules.
Do not perform Read-Modify-Write operations (such as bit-oriented instructions) on
the SPIxBUF register in either Standard or
Enhanced Buffer mode.
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To set up the SPI module for the Standard Master mode
of operation:
To set up the SPI module for the Standard Slave mode
of operation:
1.
1.
2.
2.
3.
4.
5.
If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
Write the desired settings to the SPIxCON1
and SPIxCON2 registers with MSTEN
(SPIxCON1) = 1.
Clear the SPIROV bit (SPIxSTAT).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
FIGURE 16-1:
3.
4.
5.
6.
7.
Clear the SPIxBUF register.
If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
Write the desired settings to the SPIxCON1
and SPIxCON2 registers with MSTEN
(SPIxCON1) = 0.
Clear the SMP bit.
If the CKE bit (SPIxCON1) is set, then the
SSEN bit (SPIxCON1) must be set to enable
the SSx pin.
Clear the SPIROV bit (SPIxSTAT).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT).
SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
SCKx
SSx/FSYNCx
1:1 to 1:8
Secondary
Prescaler
Sync
Control
Control
Clock
1:1/4/16/64
Primary
Prescaler
Select
Edge
SPIxCON1
SPIxCON1
Shift Control
SDOx
Enable
Master Clock
bit 0
SDIx
FCY
SPIxSR
Transfer
Transfer
SPIxBUF
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
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To set up the SPI module for the Enhanced Buffer
Master mode of operation:
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.
1.
2.
2.
3.
4.
5.
6.
If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register.
Write the desired settings to the SPIxCON1
and SPIxCON2 registers with MSTEN
(SPIxCON1) = 1.
Clear the SPIROV bit (SPIxSTAT).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
FIGURE 16-2:
3.
4.
5.
6.
7.
8.
Clear the SPIxBUF register.
If using interrupts:
a) Clear the SPIxIF bit in the respective IFSx
register.
b) Set the SPIxIE bit in the respective IECx
register.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
Write the desired settings to the SPIxCON1
and SPIxCON2 registers with MSTEN
(SPIxCON1) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
Clear the SPIROV bit (SPIxSTAT).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT).
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
SCKx
SSx/FSYNCx
1:1 to 1:8
Secondary
Prescaler
Sync
Control
1:1/4/16/64
Primary
Prescaler
Select
Edge
Control
Clock
SPIxCON1
SPIxCON1
Shift Control
SDOx
Enable
Master Clock
bit 0
SDIx
FCY
SPIxSR
Transfer
Transfer
8-Level FIFO
Receive Buffer
8-Level FIFO
Transmit Buffer
SPIXBUF
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
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REGISTER 16-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
R-0, HSC
R-0, HSC
R-0, HSC
SPIEN(1)
—
SPISIDL
—
—
SPIBEC2
SPIBEC1
SPIBEC0
bit 15
bit 8
R-0, HSC
R/C-0, HS
R-0, HSC
R/W-0
R/W-0
R/W-0
R-0, HSC
R-0, HSC
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
bit 7
bit 0
Legend:
C = Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
HSC = Hardware Settable/Clearable bit
bit 15
SPIEN: SPIx Enable bit(1)
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
bit 14
Unimplemented: Read as ‘0’
bit 13
SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-11
Unimplemented: Read as ‘0’
bit 10-8
SPIBEC: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
bit 7
SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive
0 = SPIx Shift register is not empty
bit 6
SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user software has not read the previous
data in the SPIxBUF register
0 = No overflow has occurred
bit 5
SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty
bit 4-2
SISEL: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPIxSR; as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot
011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT
bit is set)
Note 1:
If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
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REGISTER 16-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIxTXB is full
0 = Transmit has started, SPIxTXB is empty
In Standard Buffer mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the SPIxTXB.
Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
In Enhanced Buffer mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
In Standard Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
In Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from the SPIxSR to the buffer, filling the last
unread buffer location. Automatically cleared in hardware when a buffer location is available for a
transfer from SPIxSR.
Note 1:
If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
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REGISTER 16-2:
U-0
SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
—
U-0
—
R/W-0
DISSCK
(1)
R/W-0
(2)
DISSDO
R/W-0
R/W-0
R/W-0
MODE16
SMP
CKE(3)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
(4)
SSEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
DISSCK: Disable SCKx Pin bit (SPI Master modes only)(1)
1 = Internal SPI clock is disabled; pin functions as I/O
0 = Internal SPI clock is enabled
bit 11
DISSDO: Disable SDOx Pin bit(2)
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9
SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
CKE: SPIx Clock Edge Select bit(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7
SSEN: Slave Select Enable (Slave mode) bit(4)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by the module; pin is controlled by the port function
bit 6
CKP: Clock Polarity Select bit
1 = Idle state for the clock is a high level; active state is a low level
0 = Idle state for the clock is a low level; active state is a high level
bit 5
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1:
2:
3:
4:
If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
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REGISTER 16-2:
SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE: Secondary Prescale bits (Master mode)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
.
.
.
000 = Secondary prescale 8:1
bit 1-0
PPRE: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
Note 1:
2:
3:
4:
If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
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REGISTER 16-3:
SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
SPIFPOL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SPIFE
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled
0 = Framed SPIx support is disabled
bit 14
SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13
SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
bit 12-2
Unimplemented: Read as ‘0’
bit 1
SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with the first bit clock
0 = Frame sync pulse precedes the first bit clock
bit 0
SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced buffer is enabled
0 = Enhanced buffer is disabled (Legacy mode)
DS30009996G-page 228
x = Bit is unknown
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FIGURE 16-3:
SPIx MASTER/SLAVE CONNECTION (STANDARD MODE)
Processor 1 (SPI Master)
Processor 2 (SPI Slave)
SDOx
SDIx
Serial Receive Buffer
(SPIxRXB)(2)
Serial Receive Buffer
(SPIxRXB)
SDOx
SDIx
Shift Register
(SPIxSR)
Shift Register
(SPIxSR)(2)
LSb
MSb
MSb
Serial Transmit Buffer
(SPIxTXB)
Serial Transmit Buffer
(SPIxTXB)(2)
SCKx
SPIx Buffer
(SPIxBUF)(2)
LSb
Serial Clock
SCKx
SPIx Buffer
(SPIxBUF)(2)
SSx(1)
SSEN (SPIxCON1) = 1 and MSTEN (SPIxCON1) = 0
MSTEN (SPIxCON1) = 1)
Note
1:
2:
FIGURE 16-4:
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.
SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
Processor 1 (SPI Enhanced Buffer Master)
Shift Register
(SPIxSR)
Processor 2 (SPI Enhanced Buffer Slave)
SDOx
SDIx
SDIx
SDOx
MSb
LSb
MSb
8-Level FIFO Buffer
SPIx Buffer
(SPIxBUF)(2)
Note
1:
2:
LSb
8-Level FIFO Buffer
SCKx
SSx
MSTEN (SPIxCON1) = 1 and
SPIBEN (SPIxCON2) = 1
Shift Register
(SPIxSR)
Serial Clock
SCKx
SPIx Buffer
(SPIxBUF)(2)
SSx(1)
SSEN (SPIxCON1) = 1,
MSTEN (SPIxCON1) = 0 and
SPIBEN (SPIxCON2) = 1
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.
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FIGURE 16-5:
SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24F
(SPI Master, Frame Master)
Processor 2
SDOx
SDIx
SDIx
SCKx
SSx
FIGURE 16-6:
SDOx
Serial Clock
Frame Sync
Pulse
SCKx
SSx
SPIx MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24F
SPI Master, Frame Slave)
SDOx
SDIx
SDIx
SDOx
SCKx
SSx
FIGURE 16-7:
Processor 2
Serial Clock
Frame Sync
Pulse
SCKx
SSx
SPIx SLAVE, FRAME MASTER CONNECTION DIAGRAM
Processor 2
PIC24F
(SPI Slave, Frame Master)
SDOx
SDIx
SDIx
SDOx
SCKx
SSx
FIGURE 16-8:
Serial Clock
Frame Sync.
Pulse
SCKx
SSx
SPIx SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24F
(SPI Slave, Frame Slave)
Processor 2
SDOx
SDIx
SDIx
SCKx
SSx
DS30009996G-page 230
SDOx
Serial Clock
Frame Sync
Pulse
SCKx
SSx
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EQUATION 16-1:
RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1)
FSCK =
Note 1:
TABLE 16-1:
FCY
Primary Prescaler x Secondary Prescaler
Based on FCY = FOSC/2; Doze mode and PLL are disabled.
SAMPLE SCKx FREQUENCIES(1,2)
Secondary Prescaler Settings
FCY = 16 MHz
Primary Prescaler Settings
1:1
2:1
4:1
6:1
8:1
1:1
Invalid
8000
4000
2667
2000
4:1
4000
2000
1000
667
500
16:1
1000
500
250
167
125
64:1
250
125
63
42
31
1:1
5000
2500
1250
833
625
4:1
1250
625
313
208
156
16:1
313
156
78
52
39
64:1
78
39
20
13
10
FCY = 5 MHz
Primary Prescaler Settings
Note 1:
2:
Based on FCY = FOSC/2; Doze mode and PLL are disabled.
SCKx frequencies are shown in kHz.
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NOTES:
DS30009996G-page 232
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17.0
Note:
INTER-INTEGRATED
CIRCUIT™ (I2C™)
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Inter-Integrated
Circuit™
(I2C™)”
(DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”. The information in
this data sheet supersedes the information
in the FRM.
The Inter-Integrated Circuit™ (I2C™) module is a serial
interface useful for communicating with other peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, display drivers, ADC
Converters, etc.
17.1
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1.
2.
3.
4.
5.
6.
The I2C module supports these features:
•
•
•
•
•
•
•
•
•
Independent master and slave logic
7-bit and 10-bit device addresses
General call address as defined in the I2C protocol
Clock stretching to provide delays for the
processor to respond to a slave data request
Both 100 kHz and 400 kHz bus specifications
Configurable address masking
Multi-Master modes to prevent loss of messages
in arbitration
Bus Repeater mode, allowing the acceptance of
all messages as a slave regardless of the address
Automatic SCL
Communicating as a Master in a
Single Master Environment
7.
8.
9.
10.
11.
12.
13.
Assert a Start condition on SDAx and SCLx.
Send the I 2C device address byte to the slave
with a write indication.
Wait for and verify an Acknowledge from the
slave.
Send the first data byte (sometimes known as
the command) to the slave.
Wait for and verify an Acknowledge from the
slave.
Send the serial memory address low byte to the
slave.
Repeat Steps 4 and 5 until all data bytes are
sent.
Assert a Repeated Start condition on SDAx and
SCLx.
Send the device address byte to the slave with
a read indication.
Wait for and verify an Acknowledge from the
slave.
Enable master reception to receive serial
memory data.
Generate an ACK or NACK condition at the end
of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
A block diagram of the module is shown in Figure 17-1.
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FIGURE 17-1:
I2C™ BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
SCLx
Read
Shift
Clock
I2CxRSR
LSB
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSB
Shift Clock
Read
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
TCY/2
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17.2
Setting Baud Rate When
Operating as a Bus Master
17.3
The I2CxMSK register (Register 17-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00100000’, the slave module will detect both
addresses, ‘0000000’ and ‘0100000’.
To compute the Baud Rate Generator reload value, use
Equation 17-1.
EQUATION 17-1:
COMPUTING BAUD RATE
RELOAD VALUE(1,2)
FCY
FSCL =
I2CxBRG + 1 +
or:
I2CxBRG =
(
FCY
FSCL
–
Slave Address Masking
FCY
10,000,000
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2CxCON).
FCY
–1
10,000,000
)
Note:
Note 1: Based on FCY = FOSC/2; Doze mode and
PLL are disabled.
2: These clock rate values are for guidance
only. The actual clock rate can be affected
by various system level parameters. The
actual clock rate should be measured in
its intended application.
TABLE 17-1:
As a result of changes in the I2C™ protocol, the addresses in Table 17-2 are
reserved and will not be Acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
I2C™ CLOCK RATES(1,2)
I2CxBRG Value
Required System FSCL
Actual FSCL
FCY
(Decimal)
(Hexadecimal)
100 kHz
16 MHz
157
9D
100 kHz
100 kHz
8 MHz
78
4E
100 kHz
100 kHz
4 MHz
39
27
99 kHz
400 kHz
16 MHz
37
25
404 kHz
400 kHz
8 MHz
18
12
404 kHz
400 kHz
4 MHz
9
9
385 kHz
400 kHz
2 MHz
4
4
385 kHz
1 MHz
16 MHz
13
D
1.026 MHz
1 MHz
8 MHz
6
6
1.026 MHz
1 MHz
4 MHz
3
3
0.909 MHz
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2: These clock rate values are for guidance only. The actual clock rate can be affected by various system
level parameters. The actual clock rate should be measured in its intended application.
TABLE 17-2:
I2C™ RESERVED ADDRESSES(1)
Slave Address
R/W Bit
0000 000
0
General Call Address(2)
0000 000
1
Start Byte
0000 001
x
CBus Address
0000 01x
x
Reserved
0000 1xx
x
HS Mode Master Code
1111 0xx
x
10-Bit Slave Upper Byte(3)
1111
Note 1:
2:
3:
Description
1xx
x
Reserved
The address bits listed here will never cause an address match, independent of address mask settings.
The address will be Acknowledged only if GCEN = 1.
A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
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REGISTER 17-1:
I2CxCON: I2Cx CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-1, HC
R/W-0
R/W-0
R/W-0
R/W-0
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions
bit 14
Unimplemented: Read as ‘0’
bit 13
I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of slave transmission. Hardware is clear at the end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave
transmission.
bit 11
IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit
1 = IPMI Support mode is enabled; all addresses are Acknowledged
0 = IPMI mode is disabled
bit 10
A10M: 10-Bit Slave Addressing bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8
SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specifications
0 = Disables the SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)
0 = General call address is disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receive clock stretching
0 = Disables software or receive clock stretching
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REGISTER 17-1:
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master; applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.
Hardware is clear at the end of the master Acknowledge sequence.
0 = Acknowledge sequence is not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of the master receive
data byte.
0 = Receive sequence is not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on the SDAx and SCLx pins. Hardware is clear at the end of the master Stop
sequence.
0 = Stop condition is not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on the SDAx and SCLx pins. Hardware is clear at the end of the
master Repeated Start sequence.
0 = Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start
sequence.
0 = Start condition is not in progress
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REGISTER 17-2:
I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC
R-0, HSC
U-0
U-0
U-0
R/C-0, HS
R-0, HSC
R-0, HSC
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
bit 15
bit 8
R/C-0, HS
R/C-0, HS
R-0, HSC
R/C-0, HSC
R/C-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
bit 7
bit 0
Legend:
C = Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
HSC = Hardware Settable/Clearable bit
bit 15
ACKSTAT: Acknowledge Status bit
1 = NACK was detected last
0 = ACK was detected last
Hardware is set or cleared at the end of Acknowledge.
bit 14
TRSTAT: Transmit Status bit
(when operating as I2C™ master; applicable to master transmit operation.)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at the beginning of master transmission; hardware is clear at the end of slave Acknowledge.
bit 13-11
Unimplemented: Read as ‘0’
bit 10
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware is set at the detection of a bus collision.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when the address matches the general call address; hardware is clear at Stop detection.
bit 8
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at the match of the 2nd byte of the matched 10-bit address; hardware is clear at Stop detection.
bit 7
IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware is set at an occurrence of write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5
D/A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at the device address match. Hardware is set after a transmission finishes or by
reception of a slave byte.
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REGISTER 17-2:
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
bit 2
R/W: Read/Write Information bit (when operating as I2C slave)
1 = Read: Indicates the data transfer is output from the slave
0 = Write: Indicates the data transfer is input to the slave
Hardware is set or clear after the reception of an I 2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware is set when I2CxRCV is written with the received byte; hardware is clear when the software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
Hardware is set when software writes to I2CxTRN; hardware is clear at the completion of data transmission.
REGISTER 17-3:
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
AMSK
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
AMSK: Mask for Address Bit x Select bits
1 = Enables masking for bit x of the incoming message address; bit match is not required in this position
0 = Disables masking for bit x; bit match is required in this position
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NOTES:
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18.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“UART” (DS39708) in the “dsPIC33/PIC24
Family Reference Manual”. The information in this data sheet supersedes the
information in the FRM.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules available
in the PIC24F device family. The UART is a full-duplex,
asynchronous system that can communicate with
peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. The module
also supports a hardware flow control option with the
UxCTS and UxRTS pins, and includes an IrDA® encoder
and decoder.
The primary features of the UART module are:
• Full-Duplex, 8 or 9-Bit Data Transmission through
the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with the UxCTS
and UxRTS Pins
FIGURE 18-1:
• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
• Baud Rates Ranging from 15 bps to 1 Mbps at
16 MIPS
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UART is shown in
Figure 18-1. The UART module consists of these key
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
UxRTS/BCLKx
UxCTS
Note:
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
The UART inputs and outputs must all be assigned to available RPn/RPIn pins before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
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18.1
UART Baud Rate Generator (BRG)
The UART module includes a dedicated, 16-bit Baud
Rate Generator. The UxBRG register controls the
period of a free-running, 16-bit timer. Equation 18-1
shows the formula for computation of the baud rate with
BRGH = 0.
EQUATION 18-1:
The maximum baud rate (BRGH = 0) possible is
FCY/16 (for UxBRG = 0) and the minimum baud rate
possible is FCY/(16 * 65536).
Equation 18-2 shows the formula for computation of
the baud rate with BRGH = 1.
EQUATION 18-2:
UARTx BAUD RATE WITH
BRGH = 0(1,2)
Baud Rate =
FCY
Baud Rate =
16 • (UxBRG + 1)
FCY
16 • Baud Rate
UxBRG =
Note 1:
2:
UxBRG =
–1
FCY denotes the instruction cycle clock
frequency (FOSC/2).
Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
• FCY = 4 MHz
• Desired Baud Rate = 9600
EXAMPLE 18-1:
UARTx BAUD RATE WITH
BRGH = 1(1,2)
Note 1:
2:
FCY
4 • (UxBRG + 1)
FCY
4 • Baud Rate
–1
FCY denotes the instruction cycle clock
frequency.
Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
The maximum baud rate (BRGH = 1) possible is FCY/4
(for UxBRG = 0) and the minimum baud rate possible
is FCY/(4 * 65536).
Writing a new value to the UxBRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
Desired Baud Rate
= FCY/(16 (BRGx + 1))
Solving for BRGx Value:
BRGx
BRGx
BRGx
= ((FCY/Desired Baud Rate)/16) – 1
= ((4000000/9600)/16) – 1
= 25
Calculated Baud Rate = 4000000/(16 (25 + 1))
= 9615
Error
Note 1:
= (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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18.2
1.
2.
3.
4.
5.
6.
Set up the UART:
a) Write appropriate values for data, parity and
Stop bits.
b) Write appropriate baud rate value to the
UxBRG register.
c) Set up transmit and receive interrupt enable
and priority bits.
Enable the UART.
Set the UTXEN bit (causes a transmit interrupt,
two cycles after being set).
Write a data byte to the lower byte of the
UxTXREG word. The value will be immediately
transferred to the Transmit Shift Register (TSR)
and the serial bit stream will start shifting out
with the next rising edge of the baud clock.
Alternatively, the data byte may be transferred
while UTXEN = 0 and then the user may set
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will
start from a cleared state.
A transmit interrupt will be generated as per
interrupt control bit, UTXISELx.
18.3
1.
2.
3.
4.
5.
6.
Transmitting in 8-Bit Data Mode
Transmitting in 9-Bit Data Mode
Set up the UART (as described in Section 18.2
“Transmitting in 8-Bit Data Mode”).
Enable the UART.
Set the UTXEN bit (causes a transmit interrupt).
Write UxTXREG as a 16-bit value only.
A word write to UxTXREG triggers the transfer
of the 9-bit data to the TSR. The serial bit stream
will start shifting out with the first rising edge of
the baud clock.
A transmit interrupt will be generated as per the
setting of control bit, UTXISELx.
18.4
Break and Sync Transmit
Sequence
The following sequence will send a message frame
header, made up of a Break, followed by an auto-baud
Sync byte.
1.
2.
3.
4.
5.
Configure the UART for the desired mode.
Set UTXEN and UTXBRK to set up the Break
character.
Load the UxTXREG with a dummy character to
initiate transmission (value is ignored).
Write ‘55h’ to UxTXREG; this loads the Sync
character into the transmit FIFO.
After the Break has been sent, the UTXBRK bit
is reset by hardware. The Sync character now
transmits.
2010-2014 Microchip Technology Inc.
18.5
1.
2.
3.
4.
5.
Receiving in 8-Bit or 9-Bit Data
Mode
Set up the UART (as described in Section 18.2
“Transmitting in 8-Bit Data Mode”).
Enable the UART.
A receive interrupt will be generated when one
or more data characters have been received as
per interrupt control bit, URXISELx.
Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
Read UxRXREG.
The act of reading the UxRXREG character will move
the next character to the top of the receive FIFO,
including a new set of PERR and FERR values.
18.6
Operation of UxCTS and UxRTS
Control Pins
UARTx Clear-to-Send (UxCTS) and Request-to-Send
(UxRTS) are the two hardware controlled pins that are
associated with the UART module. These two pins
allow the UART to operate in Simplex and Flow Control
mode. They are implemented to control the transmission and reception between the Data Terminal
Equipment (DTE). The UEN bits in the UxMODE
register configure these pins.
18.7
Infrared Support
The UART module provides two types of infrared UART
support: one is the IrDA clock output to support an
external IrDA encoder and decoder device (legacy
module support), and the other is the full implementation of the IrDA encoder and decoder. Note that
because the IrDA modes require a 16x baud clock, they
will only work when the BRGH bit (UxMODE) is ‘0’.
18.7.1
IrDA CLOCK OUTPUT FOR
EXTERNAL IrDA SUPPORT
To support external IrDA encoder and decoder devices,
the BCLKx pin (same as the UxRTS pin) can be
configured to generate the 16x baud clock. With
UEN = 11, the BCLKx pin will output the 16x
baud clock if the UART module is enabled. It can be
used to support the IrDA codec chip.
18.7.2
BUILT-IN IrDA ENCODER AND
DECODER
The UART has full implementation of the IrDA encoder
and decoder as part of the UART module. The built-in
IrDA encoder and decoder functionality is enabled
using the IREN bit (UxMODE). When enabled
(IREN = 1), the receive pin (UxRX) acts as the input
from the infrared receiver. The transmit pin (UxTX) acts
as the output to the infrared transmitter.
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REGISTER 18-1:
UxMODE: UARTx MODE REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
UARTEN(1)
—
USIDL
IREN(2)
RTSMD
—
UEN1
UEN0
bit 15
bit 8
R/W-0, HC
R/W-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN: UARTx Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by port
latches
bit 7
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared
in hardware on the following rising edge
0 = No wake-up is enabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
Note 1:
2:
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)” for more information.
This feature is only available for the 16x BRG mode (BRGH = 0).
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REGISTER 18-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4
RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = High-Speed mode (4 BRG clock cycles per bit)
0 = Standard Speed mode (16 BRG clock cycles per bit)
bit 2-1
PDSEL: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1:
2:
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)” for more information.
This feature is only available for the 16x BRG mode (BRGH = 0).
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REGISTER 18-2:
R/W-0
UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1
UTXINV
(1)
R/W-0
U-0
UTXISEL0
—
R/W-0, HC
UTXBRK
R/W-0
(2)
UTXEN
R-0, HSC
R-1, HSC
UTXBF
TRMT(3)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1, HSC
R-0, HSC
R-0, HSC
R/C-0, HS
R-0, HSC
URXISEL1
URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
C = Clearable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Settable bit
HC = Hardware Clearable bit
x = Bit is unknown
bit 15,13
UTXISEL: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14
UTXINV: IrDA® Encoder Transmit Polarity Inversion bit(1)
IREN = 0:
1 = UxTX is Idle ‘0’
0 = UxTX is Idle ‘1’
IREN = 1:
1 = UxTX is Idle ‘1’
0 = UxTX is Idle ‘0’
bit 12
Unimplemented: Read as ‘0’
bit 11
UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10
UTXEN: UARTx Transmit Enable bit(2)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by the port.
bit 9
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)(3)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
Note 1:
2:
3:
The value of the bit only affects the transmit properties of the module when the IrDA® encoder is enabled
(IREN = 1).
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)” for more information.
The TRMT bit will be active only after two instruction cycles once the UTXREG is loaded.
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REGISTER 18-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 7-6
URXISEL: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 0 transition); will reset
the receiver buffer and the RSR to the empty state
bit 0
URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1:
2:
3:
The value of the bit only affects the transmit properties of the module when the IrDA® encoder is enabled
(IREN = 1).
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)” for more information.
The TRMT bit will be active only after two instruction cycles once the UTXREG is loaded.
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NOTES:
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19.0
The modulated output signal is generated by performing a logical AND operation of both the carrier and
modulator signals and then it is provided to the MDOUT
pin. Using this method, the DSM can generate the
following types of key modulation schemes:
DATA SIGNAL MODULATOR
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Data
Signal
Modulator
(DSM)”
(DS39744) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
• Frequency Shift Keying (FSK)
• Phase Shift Keying (PSK)
• On-Off Keying (OOK)
Figure 19-1 shows a simplified block diagram of the
Data Signal Modulator peripheral.
The Data Signal Modulator (DSM) allows the user to
mix a digital data stream (the “modulator signal”) with a
carrier signal to produce a modulated output. Both the
carrier and the modulator signals are supplied to the
DSM module, either internally from the output of a
peripheral, or externally through an input pin.
FIGURE 19-1:
SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
MDCH
VSS
MDCIN1
MDCIN2
REFO Clock
OC/PWM1
OC/PWM2
OC/PWM3
OC/PWM4
OC/PWM5
OC/PWM6
OC/PWM7
MDEN
EN
Data Signal
Modulator
CARH
CHPOL
D
SYNC
MDMS
MDBIT
MDMIN
SSP1 (SDO)
SSP2 (SDO)
UART1 (TX)
UART2 (TX)
UART3 (TX)
UART4 (TX)
OC/PWM1
OC/PWM2
OC/PWM3
OC/PWM4
OC/PWM5
OC/PWM6
OC/PWM7
Q
1
0
CHSYNC
MOD
MDOUT
MDOPOL
MDOE
D
SYNC
MDCL
VSS
MDCIN1
MDCIN2
REFO Clock
OC/PWM1
OC/PWM2
OC/PWM3
OC/PWM4
OC/PWM5
OC/PWM6
OC/PWM7
Q
1
0
CARL
2010-2014 Microchip Technology Inc.
CLSYNC
CLPOL
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REGISTER 19-1:
MDCON: MODULATOR CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
MDEN
—
MSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
—
MDOE
MDSLR
MDOPOL
—
—
—
MDBIT(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
MDEN: Modulator Module Enable bit
1 = Modulator module is enabled and mixing input signals
0 = Modulator module is disabled and has no output
bit 14
Unimplemented: Read as ‘0’
bit 13
MSIDL: Modulator Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
MDOE: Modulator Module Pin Output Enable bit
1 = Modulator pin output is enabled
0 = Modulator pin output is disabled
bit 5
MDSLR: MDOUT Pin Slew Rate Limiting bit
1 = MDOUT pin slew rate limiting is enabled
0 = MDOUT pin slew rate limiting is disabled
bit 4
MDOPOL: Modulator Output Polarity Select bit
1 = Modulator output signal is inverted
0 = Modulator output signal is not inverted
bit 3-1
Unimplemented: Read as ‘0’
bit 0
MDBIT: Manual Modulation Input bit(1)
1 = Carrier is modulated
0 = Carrier is not modulated
Note 1:
x = Bit is unknown
The MDBIT must be selected as the modulation source (MDSRC = 0000).
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REGISTER 19-2:
MDSRC: MODULATOR SOURCE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-x
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
SODIS(1)
—
—
—
MS3(2)
MS2(2)
MS1(2)
MS0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7
SODIS: Modulation Source Output Disable bit(1)
1 = Output signal driving the peripheral output pin (selected by MDMS) is disabled
0 = Output signal driving the peripheral output pin (selected by MDMS) is enabled
bit 6-4
Unimplemented: Read as ‘0’
bit 3-0
MS Modulation Source Selection bits(2)
1111 = Unimplemented
1110 = Output Compare/PWM Module 7 output
1101 = Output Compare/PWM Module 6 output
1100 = Output Compare/PWM Module 5 output
1011 = Output Compare/PWM Module 4 output
1010 = Output Compare/PWM Module 3 output
1001 = Output Compare/PWM Module 2 output
1000 = Output Compare/PWM Module 1 output
0111 = UART4 TX output
0110 = UART3 TX output
0101 = UART2 TX output
0100 = UART1 TX output
0011 = SPI2 module output (SDO2)
0010 = SPI1 module output (SDO1)
0001 = Input on MDMIN pin
0000 = Manual modulation using MDBIT (MDCON)
Note 1:
2:
This bit is only affected by a POR.
These bits are not affected by a POR.
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REGISTER 19-3:
MDCAR: MODULATOR CARRIER CONTROL REGISTER
R/W-x
R/W-x
R/W-x
U-0
R/W-x
R/W-x
R/W-x
R/W-x
CHODIS
CHPOL
CHSYNC
—
CH3(1)
CH2(1)
CH1(1)
CH0(1)
bit 15
bit 8
R/W-0
R/W-x
CLODIS
CLPOL
R/W-x
CLSYNC
U-0
R/W-x
R/W-x
R/W-x
R/W-x
—
CL3(1)
CL2(1)
CL1(1)
CL0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CHODIS: Modulator High Carrier Output Disable bit
1 = Output signal driving the peripheral output pin (selected by CH) is disabled
0 = Output signal driving the peripheral output pin is enabled
bit 14
CHPOL: Modulator High Carrier Polarity Select bit
1 = Selected high carrier signal is inverted
0 = Selected high carrier signal is not inverted
bit 13
CHSYNC: Modulator High Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the high carrier before allowing a switch to the low carrier
0 = Modulator output is not synchronized to the high time carrier signal(1)
bit 12
Unimplemented: Read as ‘0’
bit 11-8
CH Modulator Data High Carrier Selection bits(1)
1111
. . . = Reserved
1011
1010 = Output Compare/PWM Module 7 output
1001 = Output Compare/PWM Module 6 output
1000 = Output Compare/PWM Module 5 output
0111 = Output Compare/PWM Module 4 output
0110 = Output Compare/PWM Module 3 output
0101 = Output Compare/PWM Module 2 output
0100 = Output Compare/PWM Module 1 output
0011 = Reference clock (REFO) output
0010 = Input on MDCIN2 pin
0001 = Input on MDCIN1 pin
0000 = VSS
bit 7
CLODIS: Modulator Low Carrier Output Disable bit
1 = Output signal driving the peripheral output pin (selected by CL) is disabled
0 = Output signal driving the peripheral output pin is enabled
bit 6
CLPOL: Modulator Low Carrier Polarity Select bit
1 = Selected low carrier signal is inverted
0 = Selected low carrier signal is not inverted
bit 5
CLSYNC: Modulator Low Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the low carrier before allowing a switch to the high carrier
0 = Modulator output is not synchronized to the low time carrier signal(1)
bit 4
Unimplemented: Read as ‘0’
bit 3-0
CL Modulator Data Low Carrier Selection bits(1)
Bit settings are identical to those for CH.
Note 1:
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
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20.0
Note:
•
•
•
•
Programmable Address/Data Multiplexing
Programmable Address Wait States
Programmable Data Wait States (per Chip Select)
Programmable Polarity on Control Signals
(per Chip Select)
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support:
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
ENHANCED PARALLEL
MASTER PORT (EPMP)
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Enhanced Parallel Master Port (EPMP)”
(DS39730) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
20.1
Specific Package Variations
The Enhanced Parallel Master Port (EPMP) module
provides a parallel, 4-bit (Master mode only), 8-bit
(Master and Slave modes) or 16-bit (Master mode only)
data bus interface to communicate with off-chip
modules, such as memories, FIFOs, LCD controllers
and other microcontrollers. This module can serve as
either the master or the slave on the communication
bus.
While all PIC24FJ128GA310 family devices implement
the EPMP, I/O pin constraints place some limits on
16-Bit Master mode operations in some package types.
This is reflected in the number of dedicated Chip Select
pins implemented and the number of dedicated
address lines that are available. The differences are
summarized in Table 20-1. All available EPMP pin
functions are summarized in Table 20-2.
For EPMP Master modes, all external addresses are
mapped into the internal Extended Data Space (EDS).
This is done by allocating a region of the EDS for each
Chip Select, and then assigning each Chip Select to a
particular external resource, such as a memory or
external controller. This region should not be assigned
to another device resource, such as RAM or SFRs. To
perform a write or read on an external resource, the
CPU simply performs a write or read within the address
range assigned for the EPMP.
For 64-pin devices, the dedicated Chip Select pins
(PMCS1 and PMCS2) are not implemented. In addition, only 16 address lines (PMA) are available.
If required, PMA14 and PMA15 can be remapped to
function as PMCS1 and PMCS2, respectively.
Key features of the EPMP module are:
• Extended Data Space (EDS) Interface allows
Direct Access from the CPU
• Up to 23 Programmable Address Lines
• Up to 2 Chip Select Lines
• Up to 2 Acknowledgment Lines
(one per Chip Select)
• 4-Bit, 8-Bit or 16-Bit-Wide Data Bus
• Programmable Strobe Options (per Chip Select):
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
TABLE 20-1:
For 80-pin devices, the dedicated PMCS2 pin is not
implemented. It also only implements 16 address lines
(PMA). If required, PMA15 can be remapped to
function as PMCS2.
The memory space addressable by the device
depends on the number of address lines available, as
well as the number of Chip Select signals required for
the application. Devices with lower pin counts are more
affected by Chip Select requirements, as these take
away address lines. Table 20-1 shows the maximum
addressable range for each pin count.
EPMP FEATURE DIFFERENCES BY DEVICE PIN COUNT
Dedicated Chip Select
Device
CS1
CS2
No CS
64K
PIC24FJXXXGA306 (64-pin)
—
—
16
PIC24FJXXXGA308 (80-pin)
X
—
16
PIC24FJXXXGA310 (100-pin)
X
X
23
2010-2014 Microchip Technology Inc.
Address Range (bytes)
Address
Lines
1 CS
2 CS
32K
16K
64K
32K
16M
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TABLE 20-2:
ENHANCED PARALLEL MASTER PORT PIN DESCRIPTIONS
Pin Name
(Alternate Function)
PMA
PMA
(PMCS2)
PMA
(PMCS1)
Type
Description
O
Address Bus bits
O
Address Bus bit 15
I/O
Data Bus bit 15 (16-bit port with multiplexed addressing)
O
Chip Select 2 (alternate location)
O
Address Bus bit 14
I/O
Data Bus bit 14 (16-bit port with multiplexed addressing)
O
Chip Select 1 (alternate location)
O
Address Bus bits
I/O
Data Bus bits (16-bit port with multiplexed addressing)
PMA
O
Address Bus bits
PMA
O
Address Bus bit 2
PMA
(PMALU)
O
Address Latch Upper Strobe for Multiplexed Address
PMA
I/O
Address Bus bit 1
(PMALH)
O
Address Latch High Strobe for Multiplexed Address
PMA
I/O
Address Bus bit 0
(PMALL)
O
Address Latch Low Strobe for Multiplexed Address
PMD
I/O
Data Bus bits (demultiplexed addressing)
PMD
I/O
Data Bus bits
O
Address Bus bits (4-bit port with 1-phase multiplexed addressing)
PMD
I/O
Data Bus bits
PMCS1(1)
I/O
Chip Select 1
PMCS2(2)
O
Chip Select 2
PMWR
I/O
Write Strobe(3)
(PMENB)
I/O
Enable Signal(3)
PMRD
I/O
Read Strobe(3)
(PMRD/PMWR)
I/O
Read/Write Signal(3)
PMBE1
O
Byte Indicator
PMBE0
O
Nibble or Byte Indicator
PMACK1
I
Acknowledgment Signal 1
PMACK2
I
Acknowledgment Signal 2
Note 1:
2:
3:
These pins are implemented in 80-pin and 100-pin devices only.
These pins are implemented in 100-pin devices only.
Signal function depends on the setting of the MODE and SM bits (PMCON1 and PMCSxCF).
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REGISTER 20-1:
PMCON1: EPMP CONTROL REGISTER 1
R/W-0
PMPEN
bit 15
U-0
—
R/W-0
PSIDL
R/W-0
ADRMUX1
R/W-0
ADRMUX0
U-0
—
R/W-0
MODE1
R/W-0
MODE0
bit 8
R/W-0
CSF1
bit 7
R/W-0
CSF0
R/W-0
ALP
R/W-0
ALMODE
U-0
—
R/W-0
BUSKEEP
R/W-0
IRQM1
R/W-0
IRQM0
bit 0
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9-8
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
PMPEN: Parallel Master Port Enable bit
1 = EPMP is enabled
0 = EPMP is disabled
Unimplemented: Read as ‘0’
PSIDL: Parallel Master Port Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
ADRMUX: Address/Data Multiplexing Selection bits
11 = Lower address bits are multiplexed with data bits using 3 address phases
10 = Lower address bits are multiplexed with data bits using 2 address phases
01 = Lower address bits are multiplexed with data bits using 1 address phase
00 = Address and data appear on separate pins
Unimplemented: Read as ‘0’
MODE: Parallel Port Mode Select bits
11 = Master mode
10 = Enhanced PSP; pins used are PMRD, PMWR, PMCS, PMD and PMA
01 = Buffered PSP; pins used are PMRD, PMWR, PMCS and PMD
00 = Legacy Parallel Slave Port; PMRD, PMWR, PMCS and PMD pins are used
CSF: Chip Select Function bits
11 = Reserved
10 = PMA is used for Chip Select 2, PMA is used for Chip Select 1
01 = PMA is used for Chip Select 2, PMCS1 is used for Chip Select 1
00 = PMCS2 is used for Chip Select 2, PMCS1 is used for Chip Select 1
ALP: Address Latch Polarity bit
1 = Active-high (PMALL, PMALH and PMALU)
0 = Active-low (PMALL, PMALH and PMALU)
ALMODE: Address Latch Strobe Mode bit
1 = Enables “smart” address strobes (each address phase is only present if the current access would
cause a different address in the latch than the previous address)
0 = Disables “smart” address strobes
Unimplemented: Read as ‘0’
BUSKEEP: Bus Keeper bit
1 = Data bus keeps its last value when not actively being driven
0 = Data bus is in a high-impedance state when not actively being driven
IRQM: Interrupt Request Mode bits
11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),
or on a read or write operation when PMA = 11 (Addressable PSP mode only)
10 = Reserved
01 = Interrupt is generated at the end of a read/write cycle
00 = No interrupt is generated
2010-2014 Microchip Technology Inc.
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REGISTER 20-2:
PMCON2: EPMP CONTROL REGISTER 2
R-0, HSC
U-0
R/C-0, HS
R/C-0, HS
U-0
U-0
U-0
U-0
BUSY
—
ERROR
TIMEOUT
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
(1)
RADDR23
R/W-0
(1)
RADDR22
R/W-0
(1)
RADDR21
R/W-0
(1)
RADDR20
R/W-0
(1)
RADDR19
R/W-0
(1)
RADDR18
R/W-0
(1)
RADDR17
RADDR16(1)
bit 7
bit 0
HS = Hardware Settable bit
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
C = Clearable bit
bit 15
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 14
Unimplemented: Read as ‘0’
bit 13
ERROR: Error bit
1 = Transaction error (illegal transaction was requested)
0 = Transaction completed successfully
bit 12
TIMEOUT: Time-out bit
1 = Transaction timed out
0 = Transaction completed successfully
bit 11-8
Unimplemented: Read as ‘0’
bit 7-0
RADDR: Parallel Master Port Reserved Address Space bits(1)
Note 1:
If RADDR = 00000000, then the last EDS address for Chip Select 2 will be FFFFFFh.
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REGISTER 20-3:
PMCON3: EPMP CONTROL REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
PTWREN
PTRDEN
PTBE1EN
PTBE0EN
—
AWAITM1
AWAITM0
AWAITE
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
PTEN22(1)
PTEN21(1)
PTEN20(1)
PTEN19(1)
PTEN18(1)
PTEN17(1)
PTEN16(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
PTWREN: Parallel Master Port Write/Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 14
PTRDEN: Parallel Master Port Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
bit 13
PTBE1EN: Parallel Master Port High Nibble/Byte Enable Port Enable bit
1 = PMBE1 port is enabled
0 = PMBE1 port is disabled
bit 12
PTBE0EN: Parallel Master Port Low Nibble/Byte Enable Port Enable bit
1 = PMBE0 port is enabled
0 = PMBE0 port is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-9
AWAITM: Address Latch Strobe Wait States bits
11 = Wait of 3½ TCY
10 = Wait of 2½ TCY
01 = Wait of 1½ TCY
00 = Wait of ½ TCY
bit bit 8
AWAITE: Address Hold After Address Latch Strobe Wait States bits
1 = Wait of 1¼ TCY
0 = Wait of ¼ TCY
bit 7
Unimplemented: Read as ‘0’
bit 6-0
PTEN: EPMP Address Port Enable bits(1)
1 = PMA function as EPMP address lines
0 = PMA function as port I/Os
Note 1:
x = Bit is unknown
These bits are not available in 80 and 64-pin devices (PIC24FJXXXGA306, PIC24FJXXXGA308).
2010-2014 Microchip Technology Inc.
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REGISTER 20-4:
PMCON4: EPMP CONTROL REGISTER 4
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PTEN15: PMA15 Port Enable bit
1 = PMA15 functions as either Address Line 15 or Chip Select 2
0 = PMA15 functions as port I/O
bit 14
PTEN14: PMA14 Port Enable bit
1 = PMA14 functions as either Address Line 14 or Chip Select 1
0 = PMA14 functions as port I/O
bit 13-3
PTEN: EPMP Address Port Enable bits
1 = PMA function as EPMP address lines
0 = PMA function as port I/Os
bit 2-0
PTEN: PMALU/PMALH/PMALL Strobe Enable bits
1 = PMA function as either address lines or address latch strobes
0 = PMA function as port I/Os
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REGISTER 20-5:
PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
CSDIS
CSP
CSPTEN
BEP
—
WRSP
RDSP
SM
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ACKP
PTSZ1
PTSZ0
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CSDIS: Chip Select x Disable bit
1 = Disables the Chip Select x functionality
0 = Enables the Chip Select x functionality
bit 14
CSP: Chip Select x Polarity bit
1 = Active-high (PMCSx)
0 = Active-low (PMCSx)
bit 13
CSPTEN: PMCSx Port Enable bit
1 = PMCSx port is enabled
0 = PMCSx port is disabled
bit 12
BEP: Chip Select x Nibble/Byte Enable Polarity bit
1 = Nibble/byte enable is active-high (PMBE0, PMBE1)
0 = Nibble/byte enable is active-low (PMBE0, PMBE1)
bit 11
Unimplemented: Read as ‘0’
bit 10
WRSP: Chip Select x Write Strobe Polarity bit
For Slave modes and Master mode when SM = 0:
1 = Write strobe is active-high (PMWR)
0 = Write strobe is active-low (PMWR)
For Master mode when SM = 1:
1 = Enable strobe is active-high (PMENB)
0 = Enable strobe is active-low (PMENB)
bit 9
RDSP: Chip Select x Read Strobe Polarity bit
For Slave modes and Master mode when SM = 0:
1 = Read strobe is active-high (PMRD)
0 = Read strobe is active-low (PMRD)
For Master mode when SM = 1:
1 = Read/write strobe is active-high (PMRD/PMWR)
0 = Read/Write strobe is active-low (PMRD/PMWR)
bit 8
SM: Chip Select x Strobe Mode bit
1 = Read/write and enable strobes (PMRD/PMWR and PMENB)
0 = Read and write strobes (PMRD and PMWR)
bit 7
ACKP: Chip Select x Acknowledge Polarity bit
1 = ACK is active-high (PMACK1)
0 = ACK is active-low (PMACK1)
2010-2014 Microchip Technology Inc.
x = Bit is unknown
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REGISTER 20-5:
PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER (CONTINUED)
bit 6-5
PTSZ: Chip Select x Port Size bits
11 = Reserved
10 = 16-bit port size (PMD)
01 = 4-bit port size (PMD)
00 = 8-bit port size (PMD)
bit 4-0
Unimplemented: Read as ‘0’
PMCSxBS: CHIP SELECT x BASE ADDRESS REGISTER(2)
REGISTER 20-6:
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
BASE
bit 15
bit 8
R/W(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
BASE15
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
BASE: Chip Select x Base Address bits(1)
bit 6-0
Unimplemented: Read as ‘0’
Note 1:
2:
x = Bit is unknown
The value at POR is 0080h for PMCS1BS and 0880h for PMCS2BS.
If the whole PMCS2BS register is written together as 0x0000, then the last EDS address for Chip Select 1
will be FFFFFFh. In this case, Chip Select 2 should not be used. PMCS1BS has no such feature.
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REGISTER 20-7:
PMCSxMD: CHIP SELECT x MODE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
ACKM1
ACKM0
AMWAIT2
AMWAIT1
AMWAIT0
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DWAITB1
DWAITB0
DWAITM3
DWAITM2
DWAITM1
DWAITM0
DWAITE1
DWAITE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
ACKM: Chip Select x Acknowledge Mode bits
11 = Reserved
10 = PMACKx is used to determine when a read/write operation is complete
01 = PMACKx is used to determine when a read/write operation is complete with time-out
(If DWAITM = 0000, the maximum time-out is 255 TCY or else it is DWAITM cycles.)
00 = PMACKx is not used
bit 13-11
AMWAIT: Chip Select x Alternate Master Wait States bits
111 = Wait of 10 alternate master cycles
...
001 = Wait of 4 alternate master cycles
000 = Wait of 3 alternate master cycles
bit 10-8
Unimplemented: Read as ‘0’
bit 7-6
DWAITB: Chip Select x Data Setup Before Read/Write Strobe Wait States bits
11 = Wait of 3¼ TCY
10 = Wait of 2¼ TCY
01 = Wait of 1¼ TCY
00 = Wait of ¼ TCY
bit 5-2
DWAITM: Chip Select x Data Read/Write Strobe Wait States bits
For Write Operations:
1111 = Wait of 15½ TCY
...
0001 = Wait of 1½ TCY
0000 = Wait of ½ TCY
For Read Operations:
1111 = Wait of 15¾ TCY
...
0001 = Wait of 1¾ TCY
0000 = Wait of ¾ TCY
bit 1-0
DWAITE: Chip Select x Data Hold After Read/Write Strobe Wait States bits
For Write Operations:
11 = Wait of 3¼ TCY
10 = Wait of 2¼ TCY
01 = Wait of 1¼ TCY
00 = Wait of ¼ TCY
For Read Operations:
11 = Wait of 3 TCY
10 = Wait of 2 TCY
01 = Wait of 1 TCY
00 = Wait of 0 TCY
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REGISTER 20-8:
PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY)
R-0, HSC
R/W-0, HS
U-0
U-0
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
IBF
IBOV
—
—
IB3F(1)
IB2F(1)
IB1F(1)
IB0F(1)
bit 15
bit 8
R-1, HSC
R/W-0, HS
U-0
U-0
R-1, HSC
R-1, HSC
R-1, HSC
R-1, HSC
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
bit 7
bit 0
Legend:
HS = Hardware Settable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IBF: Input Buffer Full Status bit
1 = All writable Input Buffer registers are full
0 = Some or all of the writable Input Buffer registers are empty
bit 14
IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full Input register occurred (must be cleared in software)
0 = No overflow occurred
bit 13-12
Unimplemented: Read as ‘0’
bit 11-8
IB3F:IB0F: Input Buffer x Status Full bits(1)
1 = Input buffer contains unread data (reading the buffer will clear this bit)
0 = Input buffer does not contain unread data
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable Output Buffer registers are empty
0 = Some or all of the readable Output Buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty Output register (must be cleared in software)
0 = No underflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OB3E:OB0E: Output Buffer x Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains untransmitted data
Note 1:
Even though an individual bit represents the byte in the buffer, the bits corresponding to the word (Byte 0
and 1, or Byte 2 and 3) get cleared, even on byte reading.
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REGISTER 20-9:
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-1
Unimplemented: Read as ‘0’
bit 0
PMPTTL: EPMP Module TTL Input Buffer Select bit
1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers
0 = EPMP module inputs use Schmitt Trigger input buffers
2010-2014 Microchip Technology Inc.
x = Bit is unknown
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NOTES:
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21.0
Note:
The module has these features:
LIQUID CRYSTAL DISPLAY
(LCD) CONTROLLER
• Direct driving of LCD panel
• Three LCD clock sources with selectable prescaler
• Up to eight commons:
- Static (One common)
- 1/2 multiplex (two commons)
- 1/3 multiplex (three commons)
- 1/8 multiplex (eight commons)
• Ability to drive from 30 (in 64-pin devices) to
64 (100-pin) segments, depending on the
Multiplexing mode selected
• Static, 1/2 or 1/3 LCD bias
• On-chip bias generator with dedicated charge
pump to support a range of fixed and variable bias
options
• Internal resistors for bias voltage generation
• Software contrast control for LCD using internal
biasing
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to “Liquid Crystal Display (LCD)” (DS30009740)
in the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
The Liquid Crystal Display (LCD) Controller generates
the data and timing control required to directly drive a
static or multiplexed LCD panel. In 100-pin devices
(PIC24FJXXXGA310), the module can drive panels of
up to eight commons and up to 60 segments when 5 to
8 commons are used, or up to 64 segments when 1 to
4 commons are used.
A simplified block diagram of the module is shown in
Figure 21-1.
FIGURE 21-1:
LCD CONTROLLER MODULE BLOCK DIAGRAM
Data Bus
LCD DATA
32 x 16 (= 8 x 64)
16
LCDDATA31
512
LCDDATA30
.
.
.
to
64
LCDDATA1
MUX
64
SEG
LCDDATA0
Bias
Voltage
To I/O Pins
Timing Control
LCDCON
8
LCDPS
LCDSEx
COM
LCD Bias Generation
LCDREG
LCDREF
Resistor Ladder
FRC Oscillator
LPRC Oscillator
SOSC
(Secondary Oscillator)
LCD Clock
Source Select
2010-2014 Microchip Technology Inc.
LCD
Charge Pump
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21.1
Registers
The LCD controller has up to 40 registers:
•
•
•
•
•
LCD Control Register (LCDCON)
LCD Charge Pump Control Register (LCDREG)
LCD Phase Register (LCDPS)
LCD Voltage Ladder Control Register (LCDREF)
Four LCD Segment Enable Registers
(LCDSE3:LCDSE0)
• Up to 32 LCD Data Registers
(LCDDATA31:LCDDATA0)
REGISTER 21-1:
LCDCON: LCD CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
LCDEN
—
LCDSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/C-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SLPEN
WERR
CS1
CS0
LMUX2
LMUX1
LMUX0
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
LCDEN: LCD Driver Enable bit
1 = LCD driver module is enabled
0 = LCD driver module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
LCDSIDL: Stop LCD Drive in CPU Idle Mode Control bit
1 = LCD driver halts in CPU Idle mode
0 = LCD driver continues to operate in CPU Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
SLPEN: LCD Driver Enable in Sleep mode bit
1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode
bit 5
WERR: LCD Write Failed Error bit
1 = LCDDATAx register is written while WA bit (LCDPS) = 0 (must be cleared in software)
0 = No LCD write error
bit 4-3
CS: Clock Source Select bits
00 = FRC
01 = LPRC
1x = SOSC
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REGISTER 21-1:
bit 2-0
LCDCON: LCD CONTROL REGISTER (CONTINUED)
LMUX: LCD Commons Select bits
LMUX
Multiplex
Bias
111
1/8 MUX (COM)
1/3
110
1/7 MUX (COM)
1/3
101
1/6 MUX (COM)
1/3
100
1/5 MUX (COM)
1/3
011
1/4 MUX (COM)
1/3
010
1/3 MUX (COM)
1/2 or 1/3
001
1/2 MUX (COM)
1/2 or 1/3
000
Static (COM0)
Static
Note:
For multiplex above 4 commons, COM4, COM5, COM6 and COM7 also have segment
functionality. Therefore, if the COM is enabled in multiplexing, the segment will not be
available on that pin.
2010-2014 Microchip Technology Inc.
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REGISTER 21-2:
LCDREG: LCD CHARGE PUMP CONTROL REGISTER
RW-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
CPEN(1)
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
RW-1
RW-1
RW-1
RW-1
RW-0
RW-0
—
—
BIAS2
BIAS1
BIAS0
MODE13
CKSEL1
CKSEL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CPEN: 3.6V Charge Pump Enable bit(1)
1 = The regulator generates the highest (3.6V) voltage
0 = Highest voltage in the system is supplied externally (AVDD)
bit 14-6
Unimplemented: Read as ‘0’
bit 5-3
BIAS: Regulator Voltage Output Control bits
111 = 3.60V peak (offset on LCDBIAS0 of 0V)
110 = 3.47V peak (offset on LCDBIAS0 of 0.13V)
101 = 3.34V peak (offset on LCDBIAS0 of 0.26V)
100 = 3.21V peak (offset on LCDBIAS0 of 0.39V)
011 = 3.08V peak (offset on LCDBIAS0 of 0.52V)
010 = 2.95V peak (offset on LCDBIAS0 of 0.65V)
001 = 2.82V peak (offset on LCDBIAS0 of 0.78V)
000 = 2.69V peak (offset on LCDBIAS0 of 0.91V)
bit 2
MODE13: 1/3 LCD Bias Enable bit
1 = Regulator output supports 1/3 LCD Bias mode
0 = Regulator output supports Static LCD Bias mode
bit 1-0
CLKSEL: Regulator Clock Select Control bits
11 = LPRC 31 kHz
10 = 8 MHz FRC
01 = SOSC
00 = Disables regulator and floats regulator voltage output
Note 1:
x = Bit is unknown
When using the charge pump, the LCDBIASx pins and the VLCAP1/VLCAP2 pins should be made analog,
and the respective TRISx bits should be set as inputs.
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REGISTER 21-3:
LCDPS: LCD PHASE REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
WFT
BIASMD
LCDA
WA
LP3
LP2
LP1
LP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7
WFT: Waveform Type Select bit
1 = Type-B waveform (phase changes on each frame boundary)
0 = Type-A waveform (phase changes within each common type)
bit 6
BIASMD: Bias Mode Select bit
When LMUX = 000 or 011 through 111:
0 = Static Bias mode (do not set this bit to ‘1’)
When LMUX = 001 or 010:
1 = 1/2 Bias mode
0 = 1/3 Bias mode
bit 5
LCDA: LCD Active Status bit
1 = LCD driver module is active
0 = LCD driver module is inactive
bit 4
WA: LCD Write Allow Status bit
1 = Writes into the LCDDATAx registers are allowed
0 = Writes into the LCDDATAx registers are not allowed
bit 3-0
LP: LCD Prescaler Select bits
1111 = 1:16
1110 = 1:15
1101 = 1:14
1100 = 1:13
1011 = 1:12
1010 = 1:11
1001 = 1:10
1000 = 1:9
0111 = 1:8
0110 = 1:7
0101 = 1:6
0100 = 1:5
0011 = 1:4
0010 = 1:3
0001 = 1:2
0000 = 1:1
2010-2014 Microchip Technology Inc.
x = Bit is unknown
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REGISTER 21-4:
LCDSEx: LCD SEGMENT x ENABLE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SE(n+15)
SE(n+14)
SE(n+13)
SE(n+12)
SE(n+11)
SE(n+10)
SE(n+9)
SE(n+8)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SE(n+7)
SE(n+6)
SE(n+5)
SE(n+4)
SE(n+3)
SE(n+2)
SE(n+1)
SE(n)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
SE(n + 15):SE(n): Segment Enable bits
For LCDSE0: n = 0
For LCDSE1: n = 16
For LCDSE2: n = 32
For LCDSE3: n = 48(1)
1 = Segment function of the pin is enabled, digital I/O is disabled
0 = Segment function of the pin is disabled, digital I/O is enabled
For the SEG49 to work correctly, the JTAG needs to be disabled.
REGISTER 21-5:
LCDDATAx: LCD DATA x REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+15)Cy
S(n+14)Cy
S(n+13)Cy
S(n+12)Cy
S(n+11)Cy
S(n+10)Cy
S(n+9)Cy
S(n+8)Cy
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+7)Cy
S(n+6)Cy
S(n+5)Cy
S(n+4)Cy
S(n+3)Cy
S(n+2)Cy
S(n+1)Cy
S(n)Cy
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
S(n + 15)Cy:S(n)Cy: Pixel On bits
For registers, LCDDATA0 through LCDDATA3: n = (16x), y = 0
For registers, LCDDATA4 through LCDDATA7: n = (16(x – 4)), y = 1
For registers, LCDDATA8 through LCDDATA11: n = (16(x – 8)), y = 2
For registers, LCDDATA12 through LCDDATA15: n = (16(x – 12)), y = 3
For registers, LCDDATA16 through LCDDATA19: n = (16(x – 16)), y = 4
For registers, LCDDATA20 through LCDDATA23: n = (16(x – 20)), y = 5
For registers, LCDDATA24 through LCDDATA27: n = (16(x – 24)), y = 6
For registers, LCDDATA28 through LCDDATA31: n = (16(x – 28)), y = 7
1 = Pixel is on
0 = Pixel is off
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TABLE 21-1:
LCDDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS
Segments
COM Lines
0
1
2
3
4
5
6
7
0 to 15
16 to 31
32 to 47
48 to 64
LCDDATA0
S00C0:S15C0
LCDDATA4
S00C1:S15C1
LCDDATA8
S00C2:S15C2
LCDDATA12
S00C3:S15C3
LCDDATA16
S00C4:S15C4
LCDDATA20
S00C5:S15C5
LCDDATA24
S00C6:S15C6
LCDDATA28
S00C7:S15C7
LCDDATA1
S16C0:S31C0
LCDDATA5
S16C1:S31C1
LCDDATA9
S16C2:S31C2
LCDDATA13
S16C3:S31C3
LCDDATA17
S16C4:S31C4
LCDDATA21
S16C5:S31C5
LCDDATA25
S16C6:S31C6
LCDDATA29
S16C7:S31C7
LCDDATA2
S32C0:S47C0
LCDDATA6
S32C1:S47C1
LCDDATA10
S32C2:S47C2
LCDDATA14
S32C3:S47C3
LCDDATA18
S32C4:S47C4
LCDDATA22
S32C5:S47C5
LCDDATA26
S32C6:S47C6
LCDDATA30
S32C7:S47C7
LCDDATA3
S48C0:S63C0
LCDDATA7
S48C1:S63C1
LCDDATA11
S48C2:S63C2
LCDDATA15
S48C3:S63C3
LCDDATA19
S48C4:S59C4
LCDDATA23
S48C5:S69C5
LCDDATA27
S48C6:S59C6
LCDDATA31
S48C7:S59C7
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REGISTER 21-6:
R/W-0
LCDREF: LCD REFERENCE LADDER CONTROL REGISTER
U-0
—
LCDIRE
R/W-0
LCDCST2
R/W-0
LCDCST1
R/W-0
R/W-0
R/W-0
R/W-0
LCDCST0
VLCD3PE(1)
VLCD2PE(1)
VLCD1PE(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
LRLAP1
LRLAP0
LRLBP1
LRLBP0
—
LRLAT2
LRLAT1
LRLAT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
LCDIRE: LCD Internal Reference Enable bit
1 = Internal LCD reference is enabled and connected to the internal contrast control circuit
0 = Internal LCD reference is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13-11
LCDCST: LCD Contrast Control bits
Selects the resistance of the LCD contrast control resistor ladder:
111 = Resistor ladder is at maximum resistance (minimum contrast)
110 = Resistor ladder is at 6/7th of maximum resistance
101 = Resistor ladder is at 5/7th of maximum resistance
100 = Resistor ladder is at 4/7th of maximum resistance
011 = Resistor ladder is at 3/7th of maximum resistance
010 = Resistor ladder is at 2/7th of maximum resistance
001 = Resistor ladder is at 1/7th of maximum resistance
000 = Minimum resistance (maximum contrast); resistor ladder is shorted
bit 10
VLCD3PE: Bias 3 Pin Enable bit(1)
1 = Bias 3 level is connected to the external pin, LCDBIAS3
0 = Bias 3 level is internal (internal resistor ladder)
bit 9
VLCD2PE: Bias 2 Pin Enable bit(1)
1 = Bias 2 level is connected to the external pin, LCDBIAS2
0 = Bias 2 level is internal (internal resistor ladder)
bit 8
VLCD1PE: Bias 1 Pin Enable bit(1)
1 = Bias 1 level is connected to the external pin, LCDBIAS1
0 = Bias 1 level is internal (internal resistor ladder)
bit 7-6
LRLAP: LCD Reference Ladder A Time Power Control bits
During Time Interval A:
11 = Internal LCD reference ladder is powered in High-Power mode
10 = Internal LCD reference ladder is powered in Medium Power mode
01 = Internal LCD reference ladder is powered in Low-Power mode
00 = Internal LCD reference ladder is powered down and unconnected
bit 5-4
LRLBP: LCD Reference Ladder B Time Power Control bits
During Time Interval B:
11 = Internal LCD reference ladder is powered in High-Power mode
10 = Internal LCD reference ladder is powered in Medium Power mode
01 = Internal LCD reference ladder is powered in Low-Power mode
00 = Internal LCD reference ladder is powered down and unconnected
bit 3
Unimplemented: Read as ‘0’
Note 1:
When using the external resistor ladder biasing, the LCDBIASx pins should be made analog and the
respective TRISx bits should be set as inputs.
DS30009996G-page 272
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REGISTER 21-6:
bit 2-0
Note 1:
LCDREF: LCD REFERENCE LADDER CONTROL REGISTER (CONTINUED)
LRLAT: LCD Reference Ladder A Time Interval Control bits
Sets the number of 32 clock counts when the A Time Interval Power mode is active.
For Type-A Waveforms (WFT = 0):
111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 9 clocks
110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 10 clocks
101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 11 clocks
100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 12 clocks
011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 13 clocks
010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 14 clocks
001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 15 clocks
000 = Internal LCD reference ladder is always in B Power mode
For Type-B Waveforms (WFT = 1):
111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 25 clocks
110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 26 clocks
101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 27 clocks
100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 28 clocks
011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 29 clocks
010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 30 clocks
001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 31 clocks
000 = Internal LCD reference ladder is always in B Power mode
When using the external resistor ladder biasing, the LCDBIASx pins should be made analog and the
respective TRISx bits should be set as inputs.
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NOTES:
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22.0
Note:
REAL-TIME CLOCK AND
CALENDAR (RTCC)
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Real-Time Clock and Calendar, refer to
“RTCC with External Power Control”
(DS39745) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
The RTCC provides the user with a Real-Time Clock
and Calendar (RTCC) function that can be calibrated.
22.1
RTCC Source Clock
The user can select between the SOSC crystal
oscillator, LPRC internal oscillator or an external
50 Hz/60 Hz power line input as the clock reference for
the RTCC module. This gives the user an option to
trade off system cost, accuracy and power
consumption, based on the overall system needs. If
using SOSC for a time-sensitive application, do not
enable the LCD pin (SEG17) adjacent to the SOSCI
pin.
Note:
Do not enable the LCD segment pin,
SEG17 on RD0, if the SOSC is used for
time-sensitive
applications.
Avoid
high-frequency switching adjacent to the
SOSCO and SOSCI pins.
Key features of the RTCC module are:
• Operates in Deep Sleep mode
• Selectable clock source
• Provides hours, minutes and seconds using
24-hour format
• Visibility of one half second period
• Provides calendar – weekday, date, month and year
• Alarm-configurable for half a second, one second,
10 seconds, one minute, 10 minutes, one hour,
one day, one week, one month or one year
• Alarm repeat with decrementing counter
• Alarm with indefinite repeat chime
• Year 2000 to 2099 leap year correction
• BCD format for smaller software overhead
• Optimized for long-term battery operation
• User calibration of the 32.768 kHz clock crystal/
32K INTRC frequency with periodic auto-adjust
• Optimized for long term battery operation
• Fractional second synchronization
• Calibration to within ±2.64 seconds error per month
• Calibrates up to 260 ppm of crystal error
• Ability to periodically wake up external devices
without CPU intervention (external power control)
• Power control output for external circuit control
• Calibration takes effect every 15 seconds
• Runs from any one of the following:
- External Real-Time Clock (RTC) of 32.768 kHz
- Internal 31.25 kHz LPRC clock
- 50 Hz or 60 Hz external input
2010-2014 Microchip Technology Inc.
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FIGURE 22-1:
Input from
SOSC/LPRC
Oscillator or
External Source
RTCC BLOCK DIAGRAM
RTCC Clock Domain
CPU Clock Domain
RCFGCAL
RTCC Prescalers
ALCFGRPT
RTCVAL
YEAR
MTHDY
WKDYHR
MINSEC
ALRMVAL
ALMTHDY
ALWDHR
ALMINSEC
0.5 Sec
RTCC Timer
Alarm
Event
Comparator
Alarm Registers with Masks
Repeat Counter
RTCC Interrupt Logic
Alarm
Pulse
RTCC
Interrupt
RTCOE
RTCOUT
00
1s
01
Clock Source 10
DS30009996G-page 276
RTCC
Pin
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22.2
TABLE 22-2:
RTCC Module Registers
The RTCC module registers are organized into three
categories:
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
22.2.1
REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through
corresponding register pointers. The RTCC Value
register window (RTCVALH and RTCVALL) uses the
RTCPTR bits (RCFGCAL) to select the desired
Timer register pair (see Table 22-1).
By writing the RTCVALH byte, the RTCC Pointer value,
the RTCPTR bits decrement by one until they
reach ‘00’. Once they reach ‘00’, the MINUTES and
SECONDS value will be accessible through RTCVALH
and RTCVALL until the pointer value is manually
changed.
TABLE 22-1:
RTCVAL REGISTER MAPPING
RTCC Value Register Window
RTCPTR
RTCVAL
RTCVAL
00
MINUTES
SECONDS
HOURS
01
WEEKDAY
10
MONTH
DAY
11
—
YEAR
ALRMPTR
EXAMPLE 22-1:
asm
asm
asm
asm
asm
asm
asm
asm
asm
asm
Alarm Value Register Window
ALRMVAL ALRMVAL
00
ALRMMIN
ALRMSEC
01
ALRMWD
ALRMHR
10
ALRMMNTH
ALRMDAY
11
—
—
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL bytes, the ALRMPTR value will be
decremented. The same applies to the RTCVALH or
RTCVALL bytes with the RTCPTR being
decremented.
Note:
22.2.2
This only applies to read operations and
not write operations.
WRITE LOCK
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL1) must
be set (see Example 22-1).
Note:
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits (ALCFGRPT)
to select the desired Alarm register pair (see Table 22-2).
By writing the ALRMVALH byte, the Alarm Pointer
value, ALRMPTR bits, decrement by one until
they reach ‘00’. Once they reach ‘00’, the ALRMMIN
and ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
ALRMVAL REGISTER
MAPPING
22.2.3
To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL1) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only one instruction cycle time
window allowed between the 55h/AA
sequence and the setting of RTCWREN;
therefore, it is recommended that code
follow the procedure in Example 22-1.
SELECTING RTCC CLOCK SOURCE
The clock source for the RTCC module can be selected
using the RTCLK bits in the RTCPWC register.
When the bits are set to ‘00’, the Secondary Oscillator
(SOSC) is used as the reference clock and when the bits
are ‘01’, LPRC is used as the reference clock. When
RTCLK = 10 and 11, the external power line
(50 Hz and 60 Hz) is used as the clock source.
SETTING THE RTCWREN BIT
volatile(“push w7”);
volatile(“push w8”);
volatile(“disi #5”);
volatile(“mov #0x55, w7”);
volatile(“mov w7, _NVMKEY”);
volatile(“mov #0xAA, w8”);
volatile(“mov w8, _NVMKEY”);
volatile(“bset _RCFGCAL1, #13”); //set the RTCWREN bit
volatile(“pop w8”);
volatile(“pop w7”);
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22.3
RTCC Control Registers
RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER(1)
REGISTER 22-1:
R/W-0
U-0
R/W-0
R-0, HSC
R-0, HSC
R/W-0
R/W-0
R/W-0
RTCEN(2)
—
RTCWREN
RTCSYNC
HALFSEC(3)
RTCOE
RTCPTR1
RTCPTR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
RTCEN: RTCC Enable bit(2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 11
HALFSEC: Half Second Status bit(3)
1 = Second half period of a second
0 = First half period of a second
bit 10
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
bit 9-8
RTCPTR: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL:
11 = Reserved
10 = MONTH
01 = WEEKDAY
00 = MINUTES
RTCVAL:
11 = YEAR
10 = DAY
01 = HOURS
00 = SECONDS
Note 1:
2:
3:
The RCFGCAL register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
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REGISTER 22-1:
bit 7-0
RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER(1) (CONTINUED)
CAL: RTC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 127 RTC clock pulses every 15 seconds
.
.
.
01111111 = Minimum positive adjustment; adds 1 RTC clock pulse every 15 seconds
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts 1 RTC clock pulse every 15 seconds
.
.
.
10000000 = Maximum negative adjustment; subtracts 128 RTC clock pulses every 15 seconds
Note 1:
2:
3:
The RCFGCAL register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
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RTCPWC: RTCC POWER CONTROL REGISTER(1)
REGISTER 22-2:
R/W-0
PWCEN
R/W-0
PWCPOL
R/W-0
PWCPRE
R/W-0
R/W-0
PWSPRE
RTCLK1(2)
R/W-0
RTCLK0
(2)
R/W-0
R/W-0
RTCOUT1
RTCOUT0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PWCEN: Power Control Enable bit
1 = Power control is enabled
0 = Power control is disabled
bit 14
PWCPOL: Power Control Enable bit
1 = Power control is enabled
0 = Power control is disabled
bit 13
PWCPRE: Power Control/Stability Prescaler bits
1 = PWC stability window clock is divide-by-2 of the source RTCC clock
0 = PWC stability window clock is divide-by-1 of the source RTCC clock
bit 12
PWSPRE: Power Control Sample Prescaler bits
1 = PWC sample window clock is divide-by-2 of the source RTCC clock
0 = PWC sample window clock is divide-by-1 of the source RTCC clock
bit 11-10
RTCLK: RTCC Clock Source Select bits(2)
11 = External power line (60 Hz)
10 = External power line source (50 Hz)
01 = Internal LPRC Oscillator
00 = External Secondary Oscillator (SOSC)
bit 9-8
RTCOUT: RTCC Output Source Select bits
11 = Power control
10 = RTCC clock
01 = RTCC seconds clock
00 = RTCC alarm pulse
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
2:
The RTCPWC register is only affected by a POR.
When a new value is written to these register bits, the lower half of the MINSEC register should also be
written to properly reset the clock prescalers in the RTCC.
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REGISTER 22-3:
ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0
ALRMEN
bit 15
R/W-0
CHIME
R/W-0
AMASK3
R/W-0
AMASK2
R/W-0
AMASK1
R/W-0
AMASK0
R/W-0
ALRMPTR1
R/W-0
ARPT7
bit 7
R/W-0
ARPT6
R/W-0
ARPT5
R/W-0
ARPT4
R/W-0
ARPT3
R/W-0
ARPT2
R/W-0
ARPT1
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-10
bit 9-8
bit 7-0
W = Writable bit
‘1’ = Bit is set
R/W-0
ALRMPTR0
bit 8
R/W-0
ARPT0
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 00h and
CHIME = 0)
0 = Alarm is disabled
CHIME: Chime Enable bit
1 = Chime is enabled; ARPT bits are allowed to roll over from 00h to FFh
0 = Chime is disabled; ARPT bits stop once they reach 00h
AMASK: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every 4 years)
101x = Reserved – do not use
11xx = Reserved – do not use
ALRMPTR: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers.
The ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = PWCSTAB
ALRMVAL:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = PWCSAMP
ARPT: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
.
.
.
00000000 = Alarm will not repeat
The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless
CHIME = 1.
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22.3.1
RTCVAL REGISTER MAPPINGS
YEAR: YEAR VALUE REGISTER(1)
REGISTER 22-4:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YRTEN3
YRTEN2
YRTEN2
YRTEN1
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-4
YRTEN: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0
YRONE: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to the YEAR register is only allowed when RTCWREN = 1.
MTHDY: MONTH AND DAY VALUE REGISTER(1)
REGISTER 22-5:
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
bit 11-8
MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
DS30009996G-page 282
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REGISTER 22-6:
WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1)
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
WDAY: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
REGISTER 22-7:
MINSEC: MINUTES AND SECONDS VALUE REGISTER
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 283
PIC24FJ128GA310 FAMILY
22.3.2
ALRMVAL REGISTER MAPPINGS
ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1)
REGISTER 22-8:
U-0
—
bit 15
U-0
—
U-0
—
R/W-x
MTHTEN0
R/W-x
MTHONE3
R/W-x
MTHONE2
R/W-x
MTHONE1
R/W-x
MTHONE0
bit 8
U-0
—
U-0
—
R/W-x
DAYTEN1
R/W-x
DAYTEN0
R/W-x
DAYONE3
R/W-x
DAYONE2
R/W-x
DAYONE1
R/W-x
DAYONE0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12
bit 11-8
bit 7-6
bit 5-4
bit 3-0
Note 1:
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
Unimplemented: Read as ‘0’
DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
A write to this register is only allowed when RTCWREN = 1.
ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1)
REGISTER 22-9:
U-0
—
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
WDAY2
R/W-x
WDAY1
R/W-x
WDAY0
bit 8
U-0
—
U-0
—
R/W-x
HRTEN1
R/W-x
HRTEN0
R/W-x
HRONE3
R/W-x
HRONE2
R/W-x
HRONE1
R/W-x
HRONE0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-8
bit 7-6
bit 5-4
bit 3-0
Note 1:
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
WDAY: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
Unimplemented: Read as ‘0’
HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
A write to this register is only allowed when RTCWREN = 1.
DS30009996G-page 284
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 22-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 285
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REGISTER 22-11: RTCCSWT: POWER CONTROL AND SAMPLE WINDOW TIMER REGISTER(1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
PWCSTAB7
PWCSTAB6
PWCSTAB5
PWCSTAB4
PWCSTAB3
PWCSTAB2
PWCSTAB1
PWCSTAB0
bit 15
bit 8
R/W-x
R/W-x
(2)
PWCSAMP7
R/W-x
(2)
PWCSAMP6
R/W-x
(2)
PWCSAMP5
R/W-x
(2)
PWCSAMP4
R/W-x
(2)
PWCSAMP3
R/W-x
(2)
PWCSAMP2
R/W-x
(2)
PWCSAMP1
PWCSAMP0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
PWCSTAB: Power Control Stability Window Timer bits
11111111 = Stability Window is 255 TPWCCLK clock periods
11111110 = Stability Window is 254 TPWCCLK clock periods
...
00000001 = Stability Window is 1 TPWCCLK clock period
00000000 = No Stability Window; Sample Window starts when the alarm event triggers
bit 7-0
PWCSAMP: Power Control Sample Window Timer bits(2)
11111111 = Sample Window is always enabled, even when PWCEN = 0
11111110 = Sample Window is 254 TPWCCLK clock periods
...
00000001 = Sample Window is 1 TPWCCLK clock period
00000000 = No Sample Window
Note 1:
2:
A write to this register is only allowed when RTCWREN = 1.
The Sample Window always starts when the Stability Window timer expires, except when its initial value is 00h.
DS30009996G-page 286
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
22.4
Calibration
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than 3 seconds
per month. This is accomplished by finding the number
of error clock pulses and storing the value into the
lower half of the RCFGCAL register. The 8-bit signed
value loaded into the lower half of RCFGCAL is
multiplied by four and will either be added or subtracted
from the RTCC timer, once every minute. Refer to the
steps below for RTCC calibration:
1.
2.
3.
Using another timer resource on the device, the
user must find the error of the 32.768 kHz crystal.
Once the error is known, it must be converted to
the number of error clock pulses per minute.
a) If the oscillator is faster than ideal (negative
result form Step 2), the RCFGCAL register value
must be negative. This causes the specified
number of clock pulses to be subtracted from
the timer counter, once every minute.
b) If the oscillator is slower than ideal (positive
result from Step 2), the RCFGCAL register value
must be positive. This causes the specified
number of clock pulses to be subtracted from
the timer counter, once every minute.
EQUATION 22-1:
(Ideal Frequency† – Measured Frequency) * 60 =
Clocks per Minute
† Ideal Frequency = 32,768 Hz
Writes to the lower half of the RCFGCAL register
should only occur when the timer is turned off, or
immediately after the rising edge of the seconds pulse,
except when SECONDS = 00, 15, 30 or 45. This is due
to the auto-adjust of the RTCC at 15 second intervals.
Note:
22.5
It is up to the user to include, in the error
value, the initial error of the crystal: drift
due to temperature and drift due to crystal
aging.
Alarm
• Configurable from half second to one year
• Enabled using the ALRMEN bit
(ALCFGRPT)
• One-time alarm and repeat alarm options
available
2010-2014 Microchip Technology Inc.
22.5.1
CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
ALRMVAL should only take place when ALRMEN = 0.
As shown in Figure 22-2, the interval selection of the
alarm is configured through the AMASKx bits
(ALCFGRPT). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur.
The alarm can also be configured to repeat based on a
preconfigured interval. The amount of times this
occurs, once the alarm is enabled, is stored in the
ARPT bits (ALCFGRPT). When the value
of the ARPTx bits equals 00h and the CHIME bit
(ALCFGRPT) is cleared, the repeat function is
disabled and only a single alarm will occur. The alarm
can be repeated, up to 255 times, by loading
ARPT with FFh.
After each alarm is issued, the value of the ARPTx bits
is decremented by one. Once the value has reached
00h, the alarm will be issued one last time, after which,
the ALRMEN bit will be cleared automatically and the
alarm will turn off.
Indefinite repetition of the alarm can occur if the
CHIME bit = 1. Instead of the alarm being disabled
when the value of the ARPTx bits reaches 00h, it rolls
over to FFh and continues counting indefinitely while
CHIME is set.
22.5.2
ALARM INTERRUPT
At every alarm event, an interrupt is generated. In
addition, an alarm pulse output is provided that
operates at half the frequency of the alarm. This output
is completely synchronous to the RTCC clock and can
be used as a trigger clock to other peripherals.
Note:
Changing any of the registers, other than
the RCFGCAL and ALCFGRPT registers,
and the CHIME bit while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0). It is recommended that
the ALCFGRPT register and CHIME bit be
changed when RTCSYNC = 0.
DS30009996G-page 287
PIC24FJ128GA310 FAMILY
FIGURE 22-2:
ALARM MASK SETTINGS
Alarm Mask Setting
(AMASK)
Day of
the
Week
Month
Day
Hours
Minutes
Seconds
0000 - Every half second
0001 - Every second
0010 - Every 10 seconds
s
0011 - Every minute
s
s
m
s
s
m
m
s
s
0100 - Every 10 minutes
0101 - Every hour
0110 - Every day
0111 - Every week
d
1000 - Every month
1001 - Every year(1)
Note 1:
22.6
m
m
h
h
m
m
s
s
h
h
m
m
s
s
d
d
h
h
m
m
s
s
d
d
h
h
m
m
s
s
Annually, except when configured for February 29.
Power Control
22.7
RTCC VBAT Operation
The RTCC includes a power control feature that allows
the device to periodically wake-up an external device,
wait for the device to be stable before sampling
wake-up events from that device, and then shut down
the external device. This can be done completely
autonomously by the RTCC, without the need to wake
from the current lower power mode (Sleep, Deep
Sleep, etc.).
The RTCC can operate in VBAT mode when there is a
power loss on the VDD pin. The RTCC will continue to
operate if the VBAT pin is powered on (it is usually
connected to the battery).
To use this feature:
The VBAT BOR can be enabled/disabled using the
VBTBOR bit in the CW3 Configuration register
(CW3). If the VBTBOR enable bit is cleared, the
VBAT BOR is always disabled and there will be no indication of a VBAT BOR. If the VBTBOR bit is set, the
RTCC can receive a Reset and the RTCEN bit will get
cleared when the voltage reaches VBTRTC.
1.
2.
3.
Enable the RTCC (RTCEN = 1).
Set the PWCEN bit (RTCPWC).
Configure the RTCC pin to drive the PWC control
signal (RTCOE = 1 and RTCOUT = 11).
The polarity of the PWC control signal may be chosen
using the PWCPOL bit (RTCPWC). An active-low
or active-high signal may be used with the appropriate
external switch to turn on or off the power to one or
more external devices. The active-low setting may also
be used in conjunction with an open-drain setting on
the RTCC pin, in order to drive the ground pin(s) of the
external device directly (with the appropriate external
VDD pull-up device), without the need for external
switches. Finally, the CHIME bit should be set to enable
the PWC periodicity.
DS30009996G-page 288
Note:
It is recommended to connect the VBAT
pin to VDD if the VBAT mode is not used
(not connected to the battery).
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
23.0
The 32-bit programmable CRC generator provides a
hardware implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
Note:
• User-programmable CRC polynomial equation,
up to 32 bits
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable interrupt output
• Data FIFO
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS30009729) in
the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
FIGURE 23-1:
Figure 23-1 displays a simplified block diagram of the
CRC generator. A simple version of the CRC shift
engine is displayed in Figure 23-2.
CRC BLOCK DIAGRAM
CRCDATH
CRCDATL
FIFO Empty
Event
Variable FIFO
(4x32, 8x16 or 16x8)
CRCWDATH
CRCISEL
CRCWDATL
1
LENDIAN
Shift Buffer
0
CRC
Interrupt
1
CRC Shift Engine
0
Shift
Complete
Event
Shifter Clock
2 * FCY
FIGURE 23-2:
CRC SHIFT ENGINE DETAIL
CRC Shift Engine
CRCWDATH
CRCWDATL
Read/Write Bus
X0
Shift Buffer
Data
Note 1:
Xn(1)
X1
Bit 0
Bit 1
Bit n(1)
n = PLEN + 1.
2010-2014 Microchip Technology Inc.
DS30009996G-page 289
PIC24FJ128GA310 FAMILY
23.1
23.1.1
23.1.2
User Interface
POLYNOMIAL INTERFACE
The CRC module can be programmed for CRC
polynomials of up to the 32nd order, using up to 32 bits.
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN bits
(CRCCON2).
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the equation. Functionally, this includes an XOR operation on
the corresponding bit in the CRC engine. Clearing the
bit disables the XOR.
For example, consider two CRC polynomials, one a
16-bit and the other a 32-bit equation.
EQUATION 23-1:
DATA INTERFACE
The module incorporates a FIFO that works with a
variable data width. Input data width can be configured
to any value between 1 and 32 bits using the
DWIDTH bits (CRCCON2). When the
data width is greater than 15, the FIFO is 4 words deep.
When the DWIDTHx bits are between 15 and 8, the
FIFO is 8 words deep. When the DWIDTHx bits are
less than 8, the FIFO is 16 words deep.
The data for which the CRC is to be calculated must
first be written into the FIFO. Even if the data width is
less than 8, the smallest data element that can be
written into the FIFO is 1 byte. For example, if the
DWIDTHx bits are 5, then the size of the data is
DWIDTH + 1 or 6. The data is written as a whole
byte; the two unused upper bits are ignored by the
module.
Once data is written into the MSb of the CRCDAT registers (that is, the MSb as defined by the data width),
the value of the VWORD bits (CRCCON1)
increments by one. For example, if the DWIDTHx bits
are 24, the VWORDx bits will increment when bit 7 of
CRCDATH is written. Therefore, CRCDATL must
always be written to before CRCDATH.
16-BIT, 32-BIT CRC
POLYNOMIALS
X16 + X12 + X5 + 1
and
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +
X8 + X7 + X5 + X4 + X2 + X + 1
The CRC engine starts shifting data when the CRCGO
bit is set and the value of the VWORDx bits is greater
than zero.
To program these polynomial into the CRC generator,
set the register bits, as shown in Table 23-1.
Note that the appropriate positions are set to ‘1’ to indicate that they are used in the equation (for example,
X26 and X23). The ‘0’ bit required by the equation is
always XORed; thus, X0 is a don’t care. For a polynomial of length 32, it is assumed that the 32nd bit will
be used. Therefore, the X bits do not have the
32nd bit.
Each word is copied out of the FIFO into a buffer register, which decrements the VWORDx bits. The data is
then shifted out of the buffer. The CRC engine continues shifting at a rate of two bits per instruction cycle,
until the VWORDx bits reach zero. This means that for
a given data width, it takes half that number of instructions for each word to complete the calculation. For
example, it takes 16 cycles to calculate the CRC for a
single word of 32-bit data.
When the VWORDx bits reach the maximum value for
the configured value of the DWIDTHx bits (4, 8 or 16),
the CRCFUL bit becomes set. When the VWORD bits
reach zero, the CRCMPT bit becomes set. The FIFO is
emptied and the VWORD bits are set to ‘00000’
whenever CRCEN is ‘0’.
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORDx bits is done.
TABLE 23-1:
CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS
Bit Values
CRC Control Bits
16-Bit Polynomial
32-Bit Polynomial
PLEN
01111
11111
X
0000 0000 0000 0001
0000 0100 1100 0001
X
0001 0000 0010 000X
0001 1101 1011 011x
DS30009996G-page 290
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
23.1.3
DATA SHIFT DIRECTION
The LENDIAN bit (CRCCON1) is used to control
the shift direction. By default, the CRC will shift data
through the engine, MSb first. Setting LENDIAN (= 1)
causes the CRC to shift data, LSb first. This setting
allows better integration with various communication
schemes and removes the overhead of reversing the
bit order in software. Note that this only changes the
direction the data is shifted into the engine. The result
of the CRC calculation will still be a normal CRC result,
not a reverse CRC result.
23.1.4
3.
4.
5.
6.
7.
INTERRUPT OPERATION
Preload the FIFO by writing to the CRCDATL
and CRCDATH registers until the CRCFUL bit is
set or no data is left.
Clear old results by writing 00h to CRCWDATL
and CRCWDATH. The CRCWDAT registers can
also be left unchanged to resume a previously
halted calculation.
Set the CRCGO bit to start calculation.
Write remaining data into the FIFO as space
becomes available.
When the calculation completes, CRCGO is
automatically cleared. An interrupt will be
generated if CRCISEL = 1.
Read CRCWDATL and CRCWDATH for the
result of the calculation.
The module generates an interrupt that is configurable
by the user for either of two conditions.
8.
If CRCISEL is ‘0’, an interrupt is generated when the
VWORD bits make a transition from a value of ‘1’
to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated
after the CRC operation finishes and the module sets
the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’
will not generate an interrupt. Note that when an
interrupt occurs, the CRC calculation would not yet be
complete. The module will still need (PLEN + 1)/2 clock
cycles after the interrupt is generated until the CRC
calculation is finished.
There are eight registers used to control programmable
CRC operation:
23.1.5
TYPICAL OPERATION
To use the module for a typical CRC calculation:
1.
2.
Set the CRCEN bit to enable the module.
Configure the module for desired operation:
a) Program the desired polynomial using the
CRCXORL and CRCXORH registers, and the
PLEN bits.
b) Configure the data width and shift direction
using the DWIDTHx and LENDIAN bits.
c) Select the desired Interrupt mode using the
CRCISEL bit.
2010-2014 Microchip Technology Inc.
•
•
•
•
•
•
•
•
CRCCON1
CRCCON2
CRCXORL
CRCXORH
CRCDATL
CRCDATH
CRCWDATL
CRCWDATH
The
CRCCON1
and
CRCCON2
registers
(Register 23-1 and Register 23-2) control the operation
of the module and configure the various settings.
The CRCXOR registers (Register 23-3 and
Register 23-4) select the polynomial terms to be used
in the CRC equation. The CRCDAT and CRCWDAT
registers are each register pairs that serve as buffers
for the double-word input data and CRC processed
output, respectively.
DS30009996G-page 291
PIC24FJ128GA310 FAMILY
REGISTER 23-1:
CRCCON1: CRC CONTROL 1 REGISTER
R/W-0
U-0
R/W-0
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
CRCEN
—
CSIDL
VWORD4
VWORD3
VWORD2
VWORD1
VWORD0
bit 15
bit 8
R-0, HSC
R-1, HSC
R/W-0
R/W-0, HC
R/W-0
U-0
U-0
U-0
CRCFUL
CRCMPT
CRCISEL
CRCGO
LENDIAN
—
—
—
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CRCEN: CRC Enable bit
1 = Enables module
0 = Disables module; all state machines, pointers and CRCWDAT/CRCDATH registers reset; other
SFRs are NOT reset
bit 14
Unimplemented: Read as ‘0’
bit 13
CSIDL: CRC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-8
VWORD: Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN 7 or 16
when PLEN 7.
bit 7
CRCFUL: CRC FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6
CRCMPT: CRC FIFO Empty bit
1 = FIFO is empty
0 = FIFO is not empty
bit 5
CRCISEL: CRC Interrupt Selection bit
1 = Interrupt on FIFO is empty; the final word of data is still shifting through the CRC
0 = Interrupt on shift is complete and results are ready
bit 4
CRCGO: Start CRC bit
1 = Starts CRC serial shifter
0 = CRC serial shifter is turned off
bit 3
LENDIAN: Data Shift Direction Select bit
1 = Data word is shifted into the CRC, starting with the LSb (little endian)
0 = Data word is shifted into the CRC, starting with the MSb (big endian)
bit 2-0
Unimplemented: Read as ‘0’
DS30009996G-page 292
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 23-2:
CRCCON2: CRC CONTROL 2 REGISTER
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DWIDTH4
DWIDTH3
DWIDTH2
DWIDTH1
DWIDTH0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
PLEN4
PLEN3
PLEN2
PLEN1
PLEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
DWIDTH: Data Word Width Configuration bits
Configures the width of the data word (Data Word Width – 1).
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
PLEN: Polynomial Length Configuration bits
Configures the length of the polynomial (Polynomial Length – 1).
REGISTER 23-3:
R/W-0
CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
X
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-1
X: XOR of Polynomial Term xn Enable bits
bit 0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 293
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REGISTER 23-4:
R/W-0
CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
X: XOR of Polynomial Term xn Enable bits
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24.0
Note:
12-BIT A/D CONVERTER (ADC)
WITH THRESHOLD SCAN
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference source. For more information on the
12-Bit ADC, refer to “12-Bit A/D
Converter with Threshold Detect”
(DS39739) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
24.1
To perform a standard ADC conversion:
1.
The 12-bit A/D Converter (ADC) has the following key
features:
• Successive Approximation Register (SAR)
Conversion
• Conversion Speeds of up to 200 ksps
• Up to 32 Analog Input Channels (internal and
external)
• Selectable 10-Bit (default) or 12-Bit Conversion
Resolution
• Multiple Internal Reference Input Channels
• External Voltage Reference Input Pins
• Unipolar Differential Sample-and-Hold (S/H)
Amplifier
• Automated Threshold Scan and Compare
Operation to Pre-Evaluate Conversion Results
• Selectable Conversion Trigger Source
• Fixed Length (one word per channel),
Configurable Conversion Result Buffer
• Four Options for Results Alignment
• Configurable Interrupt Generation
• Enhanced DMA Operations with Indirect Address
Generation
• Operation During CPU Sleep and Idle modes
Basic Operation
2.
3.
Configure the module:
a) Configure port pins as analog inputs by
setting the appropriate bits in the ANSx
registers (see Section 11.2 “Configuring
Analog Port Pins (ANSx)” for more
information).
b) Select the voltage reference source to
match expected range on analog inputs
(AD1CON2).
c) Select the positive and negative multiplexer
inputs for each channel (AD1CHS).
d) Select the analog conversion clock to match
the desired data rate with the processor
clock (AD1CON3).
e) Select the appropriate sample/conversion
sequence
(AD1CON1
and
AD1CON3).
f) For Channel A scanning operations, select
the positive channels to be included
(AD1CSSH and AD1CSSL registers).
g) Select how conversion results are presented
in the buffer (AD1CON1 bits and
AD1CON5 register).
h) Select the interrupt rate (AD1CON2).
i) Turn on ADC module (AD1CON1).
Configure the ADC interrupt (if required):
a) Clear the AD1IF bit (IFS0).
b) Enable the AD1IE interrupt (IEC0).
c) Select
the
ADC
interrupt
priority
(IPC3).
If the module is configured for manual sampling,
set the SAMP bit (AD1CON1) to begin
sampling.
The 12-bit ADC module is an enhanced version of the
10-bit module offered in earlier PIC24 devices. It is a
Successive Approximation Register (SAR) Converter,
enhanced with 12-bit resolution, a wide range of automatic sampling options, tighter integration with other
analog modules and a configurable results buffer.
It also includes a unique Threshold Detect feature that
allows the module itself to make simple decisions
based on the conversion results, and enhanced operation with the DMA controller through Peripheral Indirect
Addressing (PIA).
A simplified block diagram for the module is shown in
Figure 24-1.
2010-2014 Microchip Technology Inc.
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FIGURE 24-1:
12-BIT ADC1 BLOCK DIAGRAM (PIC24FJ128GA310 FAMILY)
Internal Data Bus
AVSS
VREF+
VREF-
VR Select
AVDD
VR+
16
VRComparator
VINH
VINL
AN0
VRS/H
VR+
DAC
AN1
12-Bit SAR
AN2
Conversion Logic
Data Formatting
VINH
Extended DMA data
MUX A
AN14
AN15
ADC1BUF0:
ADC1BUF25
AN16(1)
VINL
AD1CON1
AD1CON2
AD1CON3
AD1CON4
AN21(1)
AD1CON5
MUX B
AN22(1)
AN23(1)
VBG
VBG/2
VINH
AD1CHS
AD1CHITL
VINL
AD1CHITH
AD1CSSL
AD1CSSH
AD1DMBUF
VBG/6
VBAT/2
AVDD
Sample Control
AVSS
Control Logic
CTMU
Note 1:
Conversion Control
16
Input MUX Control
DMA Data Bus
AN16 through AN23 are implemented on 100-pin devices only.
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24.2
Extended DMA Operations
In addition to the standard features available on all
12-bit ADC modules, PIC24FJ128GA310 family
devices implement a limited extension of DMA functionality. This extension adds features that work with
the device’s DMA controller to expand the ADC
module’s data storage abilities beyond the module’s
built-in buffer.
The Extended DMA functionality is controlled by the
DMAEN bit (AD1CON1); setting this bit enables
the functionality. The DMABM bit (AD1CON1)
configures how the DMA feature operates.
24.2.1
EXTENDED BUFFER MODE
Extended Buffer mode (DMABM = 1) is useful for storing the results of conversions on the upper channels
(i.e., 26 and above), which do not have their own
memory-mapped buffers inside the ADC module. It can
also be used to store the conversion results on any
ADC channel in any implemented address in data
RAM.
The IA is created by combining the base address within
a channel buffer with three to five bits (depending on
the buffer size) to identify the channel. The base
address ranges from zero to seven bits wide, depending on the buffer size. The address is right-padded with
a ‘0’ in order to maintain address alignment in the Data
Space. The concatenated channel and base address
bits are then left-padded with zeros, as necessary, to
complete the 11-bit IA.
The IA is configured to auto-increment during write
operations by using the SMPIx bits (AD1CON2).
As with PIA operations for any DMA-enabled module,
the base destination address in the DMADST register
must be masked properly to accommodate the IA.
Table 24-1 shows how complete addresses are
formed. Note that the address masking varies for each
buffer size option. Because of masking requirements,
some address ranges may not be available for certain
buffer sizes. Users should verify that the DMA base
address is compatible with the buffer size selected.
When using Extended Buffer mode, always set the
BUFREGEN bit to disable FIFO operation. In addition,
disable the Split Buffer mode by clearing the BUFM bit.
Figure 24-2 shows how the parts of the address define
the buffer locations in data memory. In this case, the
module “allocates” 256 bytes of data RAM (1000h to
1100h) for 32 buffers of four words each. However, this
is not a hard allocation and nothing prevents these
locations from being used for other purposes. For
example, in the current case, if Analog Channels 1, 3
and 8 are being sampled and converted, conversion
data will only be written to the channel buffers, starting
at 1008h, 1018h and 1040h. The holes in PIA buffer
space can be used for any other purpose. It is the
user’s responsibility to keep track of buffer locations
and preventing data overwrites.
24.2.2
24.3
In Extended Buffer mode, all data from the ADC Buffer
register, and channels above 26, is mapped into data
RAM. Conversion data is written to a destination
specified by the DMA controller, specifically by the
DMADST register. This allows users to read the conversion results of channels above 26, which do not
have their own memory-mapped ADC buffer locations,
from data memory.
PIA MODE
When DMABM = 0, the ADC module is configured to
function with the DMA controller for Peripheral Indirect
Addressing (PIA) mode operations. In this mode, the
ADC module generates an 11-bit Indirect Address (IA).
This is ORed with the destination address in the DMA
controller to define where the ADC conversion data will
be stored.
In PIA mode, the buffer space is created as a series of
contiguous smaller buffers, one per analog channel. The
size of the channel buffer determines how many analog
channels can be accommodated. The size of the buffer
is selected by the DMABLx bits (AD1CON4). The
size options range from a single word per buffer to
128 words. Each channel is allocated a buffer of this
size, regardless of whether or not the channel will
actually have conversion data.
2010-2014 Microchip Technology Inc.
ADC Operation with VBAT
One of the ADC channels is connected to the VBAT pin
to monitor the VBAT voltage. This allows monitoring the
VBAT pin voltage (battery voltage) with no external connection. The voltage measured, using the ADC VBAT
monitor, is VBAT/2. The voltage can be calculated by
reading ADC = ((VBAT/2)/VDD) * 1024 for 10-bit ADC
and ((VBAT/2)/VDD) * 4096 for 12-bit ADC.
When using the VBAT ADC monitor:
• Connect the ADC channel to ground to discharge
the sample capacitor.
• Because of the high-impedance of VBAT, select
higher sampling time to get an accurate reading.
Since the VBAT pin is connected to the ADC during
sampling, to prolong the VBAT battery life, the
recommendation is to select the VBAT channel when
needed.
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24.4
Control Registers
The 12-bit ADC is controlled through a total of
13 registers:
• AD1CON1 through AD1CON5 (Register 24-1
through Register 24-5)
• AD1CS (Register 24-6)
• AD1CHITH and AD1CHITL (Register 24-8 and
Register 24-9)
TABLE 24-1:
• AD1CSSH and AD1CSSL (Register 24-10 and
Register 24-11)
• AD1CTMENH and AD1CTMENL (Register 24-12
and Register 24-13)
• AD1DMBUF (not shown) – The 16-bit conversion
buffer for Extended Buffer mode
INDIRECT ADDRESS GENERATION IN PIA MODE
DMABL
Buffer Size per
Channel (words)
Generated Offset
Address (lower 11 bits)
Available
Input
Channels
Allowable DMADST
Addresses
000
1
000 00cc ccc0
32
xxxx xxxx xx00 0000
001
2
000 0ccc ccn0
32
xxxx xxxx x000 0000
010
4
000 cccc cnn0
32
xxxx xxxx 0000 0000
011
8
00c cccc nnn0
32
xxxx xxx0 0000 0000
100
16
0cc cccn nnn0
32
xxxx xx00 0000 0000
101
32
ccc ccnn nnn0
32
xxxx x000 0000 0000
110
64
ccc cnnn nnn0
16
xxxx x000 0000 0000
111
128
ccc nnnn nnn0
8
xxxx x000 0000 0000
Legend: ccc = Channel number (three to five bits), n = Base buffer address (zero to seven bits),
x = User-definable range of DMADST for base address, 0 = Masked bits of DMADST for IA.
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FIGURE 24-2:
EXAMPLE OF BUFFER ADDRESS GENERATION IN PIA MODE
(4-WORD BUFFERS PER CHANNEL)
ADC Module
(PIA Mode)
DMABL = 010
(16-Word Buffer Size)
Data RAM
BBA Channel
ccccc (0-31)
000 cccc cnn0 (IA)
nn (0-3)
(Buffer Base Address)
DMADST
Ch 7 Buffer (4 Words)
Ch 8 Buffer (4 Words)
1038h
1040h
Ch 29 Buffer (4 Words)
Ch 29 Buffer (4 Words)
Ch 31 Buffer (4 Words)
10F0h
10F8h
1100h
Buffer Address
Channel Address
Address Mask
DMA Base Address
Ch 0, Word 0
Ch 0, Word 1
Ch 0, Word 2
Ch 0, Word 3
Ch 1, Word 0
Ch 1, Word 1
Ch 1, Word 2
Ch 1, Word 3
2010-2014 Microchip Technology Inc.
1000h
1008h
1010h
1018h
Destination
Range
1000h (DMA Base Address)
DMA Channel
Ch 0 Buffer (4 Words)
Ch 1 Buffer (4 Words)
Ch 2 Buffer (4 Words)
Ch 3 Buffer (4 Words)
1000h
1002h
1004h
1006h
1008h
100Ah
100Ch
100Eh
0001
0001
0001
0001
0001
0001
0001
0001
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
0100
0110
1000
1010
1100
1110
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REGISTER 24-1:
R/W-0
AD1CON1: ADC1 CONTROL REGISTER 1
U-0
ADON
—
R/W-0
ADSIDL
R/W-0
DMABM
(1)
R/W-0
R/W-0
R/W-0
R/W-0
DMAEN
MODE12
FORM1
FORM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0, HSC
R/C-0, HSC
SSRC3
SSRC2
SSRC1
SSRC0
—
ASAM
SAMP
DONE
bit 7
bit 0
Legend:
C = Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC module is off
bit 14
Unimplemented: Read as ‘0’
bit 13
ADSIDL: ADC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
DMABM: Extended DMA Buffer Mode Select bit(1)
1 = Extended Buffer mode: Buffer address is defined by the DMAnDST register
0 = PIA mode: Buffer addresses are defined by the DMA controller and AD1CON4
bit 11
DMAEN: Extended DMA/Buffer Enable bit
1 = Extended DMA and buffer features are enabled
0 = Extended features are disabled
bit 10
MODE12: 12-Bit Operation Mode bit
1 = 12-bit ADC operation
0 = 10-bit ADC operation
bit 9-8
FORM: Data Output Format bits (see formats following)
11 = Fractional result, signed, left justified
10 = Absolute fractional result, unsigned, left justified
01 = Decimal result, signed, right justified
00 = Absolute decimal result, unsigned, right justified
bit 7-4
SSRC: Sample Clock Source Select bits
1xxx = Unimplemented, do not use
0111 = Internal counter ends sampling and starts conversion (auto-convert); do not use in Auto-Scan mode
0110 = Timer1 in Sleep (for Auto-Scan mode)
0101 = TMR1
0100 = CTMU
0011 = TMR5
0010 = TMR3
0001 = INT0
0000 = The SAMP bit must be cleared by software to start conversion
bit 3
Unimplemented: Read as ‘0’
bit 2
ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion; SAMP bit is auto-set
0 = Sampling begins when SAMP bit is manually set
Note 1:
This bit is only available when extended DMA/buffer features are available (DMAEN = 1).
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REGISTER 24-1:
AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
bit 1
SAMP: ADC Sample Enable bit
1 = ADC Sample-and-Hold amplifiers are sampling
0 = ADC Sample-and-Hold amplifiers are holding
bit 0
DONE: ADC Conversion Status bit
1 = ADC conversion cycle has completed
0 = ADC conversion has not started or is in progress
Note 1:
This bit is only available when extended DMA/buffer features are available (DMAEN = 1).
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REGISTER 24-2:
AD1CON2: ADC1 CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
PVCFG1
PVCFG0
NVCFG0
OFFCAL
BUFREGEN
CSCNA
—
—
bit 15
bit 8
R/W-0
R/W-0
(1)
SMPI4
BUFS
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
R/W-0
R/W-0
(1)
BUFM
ALTS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
PVCFG: ADC Converter Positive Voltage Reference Configuration bits
1x = Unimplemented, do not use
01 = External VREF+
00 = AVDD
bit 13
NVCFG0: ADC Converter Negative Voltage Reference Configuration bits
1 = External VREF0 = AVSS
bit 12
OFFCAL: Offset Calibration Mode Select bit
1 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AVSS
0 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs
bit 11
BUFREGEN: ADC Buffer Register Enable bit
1 = Conversion result is loaded into the buffer location determined by the converted channel
0 = ADC result buffer is treated as a FIFO
bit 10
CSCNA: Scan Input Selections for CH0+ During Sample A bit
1 = Scans inputs
0 = Does not scan inputs
bit 9-8
Unimplemented: Read as ‘0’
bit 7
BUFS: Buffer Fill Status bit(1)
1 = ADC is filling the upper half of the buffer; user should access data in the lower half
0 = ADC is filling the lower half of the buffer; user should access data in the upper half
bit 6-2
SMPI: Interrupt Sample/DMA Increment Rate Select bits
When DMAEN = 1:
0001 = For 2-channel DMA ADC operation
0000 = For 1-channel DMA ADC operation
When DMAEN = 0:
Selects the number of sample/conversions per each interrupt.
11111 = Interrupt/address increment at the completion of conversion for each 32nd sample
11110 = Interrupt/address increment at the completion of conversion for each 31st sample
00001 = Interrupt/address increment at the completion of conversion for every other sample
00000 = Interrupt/address increment at the completion of conversion for each sample
Note 1:
These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS
is only used when BUFM = 1.
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REGISTER 24-2:
AD1CON2: ADC1 CONTROL REGISTER 2 (CONTINUED)
bit 1
BUFM: Buffer Fill Mode Select bit(1)
1 = ADC buffer is two, 13-word buffers, starting at ADC1BUF0 and ADC1BUF12, and sequential
conversions fill the buffers alternately (Split mode)
0 = ADC buffer is a single, 26-word buffer and fills sequentially from ADC1BUF0 (FIFO mode)
bit 0
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
Note 1:
These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS
is only used when BUFM = 1.
REGISTER 24-3:
AD1CON3: ADC1 CONTROL REGISTER 3
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADRC
EXTSAM
PUMPEN
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ADRC: ADC Conversion Clock Source bit
1 = RC Clock
0 = Clock derived from system clock
bit 14
EXTSAM: Extended Sampling Time bit
1 = ADC is still sampling after SAMP = 0
0 = ADC is finished sampling
bit 13
PUMPEN: Charge Pump Enable bit
1 = Charge pump for switches is enabled
0 = Charge pump for switches is disabled
bit 12-8
SAMC: Auto-Sample Time Select bits
11111 = 31 TAD
00001 = 1 TAD
00000 = 0 TAD
bit 7-0
ADCS: ADC Conversion Clock Select bits
11111111
= Reserved
01000000
00111111 = 64·TCY = TAD
00000001 = 2·TCY = TAD
00000000 = TCY = TAD
2010-2014 Microchip Technology Inc.
x = Bit is unknown
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REGISTER 24-4:
AD1CON4: ADC1 CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
DMABL2(1)
DMABL1(1)
DMABL0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
DMABL: DMA Buffer Size Select bits(1)
111 = Allocates 128 words of buffer to each analog input
110 = Allocates 64 words of buffer to each analog input
101 = Allocates 32 words of buffer to each analog input
100 = Allocates 16 words of buffer to each analog input
011 = Allocates 8 words of buffer to each analog input
010 = Allocates 4 words of buffer to each analog input
001 = Allocates 2 words of buffer to each analog input
000 = Allocates 1 word of buffer to each analog input
Note 1:
x = Bit is unknown
The DMABL bits are only used when AD1CON1 = 1 and AD1CON = 0; otherwise, their
value is ignored.
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REGISTER 24-5:
AD1CON5: ADC1 CONTROL REGISTER 5
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
ASEN
LPEN
CTMREQ
BGREQ
—
—
ASINT1
ASINT0
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
WM1
WM0
CM1
CM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ASEN: Auto-Scan Enable bit
1 = Auto-scan is enabled
0 = Auto-scan is disabled
bit 14
LPEN: Low-Power Enable bit
1 = Low power is enabled after scan
0 = Full power is enabled after scan
bit 13
CTMREQ: CTMU Request bit
1 = CTMU is enabled when the ADC is enabled and active
0 = CTMU is not enabled by the ADC
bit 12
BGREQ: Band Gap Request bit
1 = Band gap is enabled when the ADC is enabled and active
0 = Band gap is not enabled by the ADC
bit 11-10
Unimplemented: Read as ‘0’
bit 9-8
ASINT: Auto-Scan (Threshold Detect) Interrupt Mode bits
11 = Interrupt after Threshold Detect sequence completed and valid compare has occurred
10 = Interrupt after valid compare has occurred
01 = Interrupt after Threshold Detect sequence completed
00 = No interrupt
bit 7-4
Unimplemented: Read as ‘0’
bit 3-2
WM: Write Mode bits
11 = Reserved
10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid
match occurs, as defined by the CMx and ASINTx bits)
01 = Convert and save (conversion results are saved to locations as determined by the register bits
when a match occurs, as defined by the CMx bits)
00 = Legacy operation (conversion data is saved to a location determined by the buffer register bits)
bit 1-0
CM: Compare Mode bits
11 = Outside Window mode (valid match occurs if the conversion result is outside of the window defined by
the corresponding buffer pair)
10 = Inside Window mode (valid match occurs if the conversion result is inside the window defined by the
corresponding buffer pair)
01 = Greater Than mode (valid match occurs if the result is greater than the value in the corresponding
buffer register)
00 = Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer
register)
2010-2014 Microchip Technology Inc.
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REGISTER 24-6:
AD1CHS: ADC1 SAMPLE SELECT REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NB2
CH0NB1
CH0NB0
CH0SB4
CH0SB3
CH0SB2
CH0SB1
CH0SB0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NA2
CH0NA1
CH0NA0
CH0SA4
CH0SA3
CH0SA2
CH0SA1
CH0SA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
CH0NB: Sample B Channel 0 Negative Input Select bits
1xx = Unimplemented
011 = Unimplemented
010 = AN1
001 = Unimplemented
000 = VREF-/AVSS
bit 12-8
CH0SB: Sample B Channel 0 Positive Input Select bits
11111 = VBAT/2(1)
11110 = AVDD(1)
11101 = AVSS(1)
11100 = Band gap reference (VBG)(1)
11011 = VBG/2(1)
11010 = VBG/6(1)
11001 = CTMU
11000 = CTMU temperature sensor input (does not require AD1CTMENH to be set)
10111 = AN23(2)
10110 = AN22(2)
10101 = AN21(2)
10100 = AN20(2)
10011 = AN19(2)
10010 = AN18(2)
10001 = AN17(2)
10000 = AN16(2)
01111 = AN15
01110 = AN14
01101 = AN13
01100 = AN12
01011 = AN11
01010 = AN10
01001 = AN9
01000 = AN8
00111 = AN7
00110 = AN6
00101 = AN5
00100 = AN4
00011 = AN3
00010 = AN2
00001 = AN1
00000 = AN0
Note 1:
2:
These input channels do not have corresponding memory-mapped result buffers.
These channels are implemented in 100-pin devices only.
DS30009996G-page 306
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REGISTER 24-6:
AD1CHS: ADC1 SAMPLE SELECT REGISTER (CONTINUED)
bit 7-5
CH0NA: Sample A Channel 0 Negative Input Select bits
Same definitions as for CHONB.
bit 4-0
CH0SA: Sample A Channel 0 Positive Input Select bits
Same definitions as for CHOSB.
Note 1:
2:
These input channels do not have corresponding memory-mapped result buffers.
These channels are implemented in 100-pin devices only.
REGISTER 24-7:
ANCFG: ADC BAND GAP REFERENCE CONFIGURATION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
VBG6EN
VBG2EN
VBGEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2
VBG6EN: ADC Input VBG/6 Enable bit
1 = Band gap voltage, divided by six reference (VBG/6), is enabled
0 = Band gap, divided by six reference (VBG/6), is disabled
bit 1
VBG2EN: ADC Input VBG/2 Enable bit
1 = Band gap voltage, divided by two reference (VBG/2), is enabled
0 = Band gap, divided by two reference (VBG/2), is disabled
bit 0
VBGEN: ADC Input VBG Enable bit
1 = Band gap voltage reference (VBG) is enabled
0 = Band gap reference (VBG) is disabled
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 307
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REGISTER 24-8:
AD1CHITH: ADC1 SCAN COMPARE HIT REGISTER (HIGH WORD)
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
CHH
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHH
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
CHH: ADC Compare Hit bits
If CM = 11:
1 = ADC Result Buffer n has been written with data or a match has occurred
0 = ADC Result Buffer n has not been written with data
For All Other Values of CM:
1 = A match has occurred on ADC Result Channel n
0 = No match has occurred on ADC Result Channel n
REGISTER 24-9:
R/W-0
AD1CHITL: ADC1 SCAN COMPARE HIT REGISTER (LOW WORD)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHH
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHH
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
CHH: ADC Compare Hit bits
If CM = 11:
1 = ADC Result Buffer n has been written with data or a match has occurred
0 = ADC Result Buffer n has not been written with data
For All Other Values of CM:
1 = A match has occurred on ADC Result Channel n
0 = No match has occurred on ADC Result Channel n
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REGISTER 24-10: AD1CSSH: ADC1 INPUT SCAN SELECT REGISTER (HIGH WORD)
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
CSS
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-0
CSS: ADC Input Scan Selection bits
1 = Includes corresponding channel for input scan
0 = Skips channel for input scan
x = Bit is unknown
REGISTER 24-11: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER (LOW WORD)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
CSS: ADC Input Scan Selection bits
1 = Includes corresponding channel for input scan
0 = Skips channel for input scan
2010-2014 Microchip Technology Inc.
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REGISTER 24-12: AD1CTMENH: ADC1 CTMU ENABLE REGISTER (HIGH WORD)(1)
R/W-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
CTMEN: CTMU Enabled During Conversion bits
1 = CTMU is enabled and connected to the selected channel during conversion
0 = CTMU is not connected to this channel
The actual number of channels available depends on which channels are implemented on a specific
device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’.
REGISTER 24-13: AD1CTMENL: ADC1 CTMU ENABLE REGISTER (LOW WORD)(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
CTMEN: CTMU Enabled During Conversion bits
1 = CTMU is enabled and connected to the selected channel during conversion
0 = CTMU is not connected to this channel
The actual number of channels available depends on which channels are implemented on a specific
device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’.
DS30009996G-page 310
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FIGURE 24-3:
10-BIT ADC MODULE ANALOG INPUT MODEL
RIC 250
Rs
VA
ANx
Sampling
Switch
RSS
CPIN
ILEAKAGE
500 nA
RSS 3 k
CHOLD
= 4.4 pF
VSS
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC
= Interconnect Resistance
RSS
= Sampling Switch Resistance
CHOLD
= Sample/Hold Capacitance (from DAC)
Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs 5 k.
EQUATION 24-1:
ADC CONVERSION CLOCK PERIOD
TAD = TCY (ADCS + 1)
ADCS =
TAD
–1
TCY
Note: Based on TCY = 2/FOSC; Doze mode and PLL are disabled.
2010-2014 Microchip Technology Inc.
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FIGURE 24-4:
12-BIT ADC TRANSFER FUNCTION
Output Code
(Binary (Decimal))
1111 1111 1111 (4095)
1111 1111 1110 (4094)
0010 0000 0011 (2051)
0010 0000 0010 (2050)
0010 0000 0001 (2049)
0010 0000 0000 (2048)
0001 1111 1111 (2047)
0001 1111 1110 (2046)
0001 1111 1101 (2045)
0000 0000 0001 (1)
DS30009996G-page 312
(VINH – VINL)
VR+
4096
4095 * (VR+ – VR-)
VR- +
4096
VR-+
2048 * (VR+ – VR-)
4096
VR- +
Voltage Level
VR+ – VR-
0
VR-
0000 0000 0000 (0)
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 24-5:
10-BIT ADC TRANSFER FUNCTION
Output Code
(Binary (Decimal))
11 1111 1111 (1023)
11 1111 1110 (1022)
10 0000 0011 (515)
10 0000 0010 (514)
10 0000 0001 (513)
10 0000 0000 (512)
01 1111 1111 (511)
01 1111 1110 (510)
01 1111 1101 (509)
00 0000 0001 (1)
2010-2014 Microchip Technology Inc.
(VINH – VINL)
VR+
1024
1023 * (VR+ – VR-)
VR- +
1024
VR-+
512 * (VR+ – VR-)
1024
VR- +
Voltage Level
VR+ – VR-
0
VR-
00 0000 0000 (0)
DS30009996G-page 313
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NOTES:
DS30009996G-page 314
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PIC24FJ128GA310 FAMILY
25.0
voltage reference input from one of the internal band
gap references or the comparator voltage reference
generator (VBG, VBG/2, VBG/6 and CVREF).
TRIPLE COMPARATOR
MODULE
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Scalable
Comparator
Module”
(DS39734) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be
configured to use any one of five external analog inputs
(CxINA, CxINB, CxINC, CxIND and VREF+) and a
FIGURE 25-1:
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure 25-1. Diagrams of the possible individual
comparator configurations are shown in Figure 25-2.
Each comparator has its own control register,
CMxCON (Register 25-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 25-2).
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
EVPOL
CCH
Input
Select
Logic
CPOL
VIN-
CXINB
00
CXINC
01
CXIND
10
VIN+
Trigger/Interrupt
Logic
CEVT
COE
C1
COUT
-
VBG
00
VBG/2
01
VBG/6
10
VREF+
11
EVPOL
11
CPOL
Trigger/Interrupt
Logic
CEVT
COE
VINVIN+
C2
COUT
CVREFM(1)
0
CXINA
VREF+
0
CVREF
1
C1OUT
Pin
EVPOL
+
1
CVREFP(1)
C2OUT
Pin
CPOL
VINVIN+
Trigger/Interrupt
Logic
CEVT
COE
C3
COUT
C3OUT
Pin
CREF
Note 1:
Refer to the CVRCON register (Register 26-1) for bit details.
2010-2014 Microchip Technology Inc.
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FIGURE 25-2:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0
Comparator Off
CEN = 0, CREF = x, CCH = xx
COE
VINVIN+
Cx
Off (Read as ‘0’)
CxOUT
Pin
Comparator CxINB > CxINA Compare
Comparator CxINC > CxINA Compare
CEN = 1, CCH = 00, CVREFM = xx
CEN = 1, CCH = 01, CVREFM = xx
CXINB
CXINA
COE
VINVIN+
Cx
CxOUT
Pin
COE
VIN-
CXINC
Cx
VIN+
CXINA
CxOUT
Pin
Comparator CxIND > CxINA Compare
Comparator VBG > CxINA Compare
CEN = 1, CCH = 10, CVREFM = xx
CEN = 1, CCH = 11, CVREFM = 00
CXIND
CXINA
COE
VINVIN+
Cx
CxOUT
Pin
COE
VIN-
VBG
Cx
VIN+
CXINA
CxOUT
Pin
Comparator VBG > CxINA Compare
Comparator VBG > CxINA Compare
CEN = 1, CCH = 11, CVREFM = 01
CEN = 1, CCH = 11, CVREFM = 10
VBG/2
CXINA
COE
VINVIN+
Cx
VIN+
CXINA
CxOUT
Pin
COE
VIN-
VBG/6
Cx
CxOUT
Pin
Comparator CxIND > CxINA Compare
CEN = 1, CCH = 11, CVREFM = 11
VREF+
CXINA
DS30009996G-page 316
COE
VINVIN+
Cx
CxOUT
Pin
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 25-3:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0
Comparator CxINB > CVREF Compare
Comparator CxINC > CVREF Compare
CEN = 1, CCH = 00, CVREFM = xx
CEN = 1, CCH = 01, CVREFM = xx
CXINB
CVREF
COE
VIN-
CXINC
VIN+
Cx
CVREF
CxOUT
Pin
COE
VINVIN+
Cx
CxOUT
Pin
Comparator CxIND > CVREF Compare
Comparator VBG > CVREF Compare
CEN = 1, CCH = 10, CVREFM = xx
CEN = 1, CCH = 11, CVREFM = 00
CXIND
CVREF
COE
VIN-
VBG
Cx
VIN+
CVREF
CxOUT
Pin
COE
VINVIN+
Cx
CxOUT
Pin
Comparator VBG > CVREF Compare
Comparator VBG > CVREF Compare
CEN = 1, CCH = 11, CVREFM = 01
CEN = 1, CCH = 11, CVREFM = 10
VBG/2
CVREF
COE
VIN-
VBG/6
Cx
VIN+
CxOUT
Pin
CVREF
COE
VINVIN+
Cx
CxOUT
Pin
Comparator CxIND > CVREF Compare
CEN = 1, CCH = 11, CVREFM = 11
VIN+
CVREF
FIGURE 25-4:
COE
VIN-
VREF+
Cx
CxOUT
Pin
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 1
Comparator CxINB > CVREF Compare
Comparator CxINC > CVREF Compare
CEN = 1, CCH = 00, CVREFM = xx
CEN = 1, CCH = 01, CVREFM = xx
CXINB
VREF+
COE
VINVIN+
CXINC
Cx
CxOUT
Pin
VREF+
COE
VINVIN+
Cx
CxOUT
Pin
Comparator CxIND > CVREF Compare
Comparator VBG > CVREF Compare
CEN = 1, CCH = 10, CVREFM = xx
CEN = 1, CCH = 11, CVREFM = 00
CXIND
VREF+
COE
VINVIN+
VBG
Cx
CxOUT
Pin
VREF+
COE
VINVIN+
Cx
CxOUT
Pin
Comparator VBG > CVREF Compare
Comparator VBG > CVREF Compare
CEN = 1, CCH = 11, CVREFM = 01
CEN = 1, CCH = 11, CVREFM = 10
VBG/2
VREF+
COE
VINVIN+
VBG/6
Cx
2010-2014 Microchip Technology Inc.
CxOUT
Pin
VREF+
COE
VINVIN+
Cx
CxOUT
Pin
DS30009996G-page 317
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REGISTER 25-1:
CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3)
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0, HS
R-0, HSC
CEN
COE
CPOL
—
—
—
CEVT
COUT
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
bit 7
bit 0
Legend:
HS = Hardware Settable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CEN: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14
COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-10
Unimplemented: Read as ‘0’
bit 9
CEVT: Comparator Event bit
1 = Comparator event that is defined by EVPOL has occurred; subsequent triggers and interrupts
are disabled until the bit is cleared
0 = Comparator event has not occurred
bit 8
COUT: Comparator Output bit
When CPOL = 0:
1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1:
1 = VIN+ < VIN0 = VIN+ > VIN-
bit 7-6
EVPOL: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
High-to-low transition only.
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
01 = Trigger/event/interrupt is generated on transition of comparator output:
If CPOL = 0 (non-inverted polarity):
Low-to-high transition only.
If CPOL = 1 (inverted polarity):
High-to-low transition only.
00 = Trigger/event/interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
DS30009996G-page 318
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REGISTER 25-1:
CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3) (CONTINUED)
bit 4
CREF: Comparator Reference Select bits (non-inverting input)
1 = Non-inverting input connects to the internal CVREF voltage
0 = Non-inverting input connects to the CxINA pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH: Comparator Channel Select bits
11 = Inverting input of the comparator connects to the internal selectable reference voltage specified
by the CVREFM bits in the CVRCON register
10 = Inverting input of the comparator connects to the CxIND pin
01 = Inverting input of the comparator connects to the CxINC pin
00 = Inverting input of the comparator connects to the CxINB pin
REGISTER 25-2:
CMSTAT: COMPARATOR MODULE STATUS REGISTER
R/W-0
U-0
U-0
U-0
U-0
R-0, HSC
R-0, HSC
R-0, HSC
CMIDL
—
—
—
—
C3EVT
C2EVT
C1EVT
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R-0, HSC
R-0, HSC
R-0, HSC
—
—
—
—
—
C3OUT
C2OUT
C1OUT
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CMIDL: Comparator Stop in Idle Mode bit
1 = Discontinues operation of all comparators when device enters Idle mode
0 = Continues operation of all enabled comparators in Idle mode
bit 14-11
Unimplemented: Read as ‘0’
bit 10
C3EVT: Comparator 3 Event Status bit (read-only)
Shows the current event status of Comparator 3 (CM3CON).
bit 9
C2EVT: Comparator 2 Event Status bit (read-only)
Shows the current event status of Comparator 2 (CM2CON).
bit 8
C1EVT: Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON).
bit 7-3
Unimplemented: Read as ‘0’
bit 2
C3OUT: Comparator 3 Output Status bit (read-only)
Shows the current output of Comparator 3 (CM3CON).
bit 1
C2OUT: Comparator 2 Output Status bit (read-only)
Shows the current output of Comparator 2 (CM2CON).
bit 0
C1OUT: Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON).
2010-2014 Microchip Technology Inc.
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NOTES:
DS30009996G-page 320
2010-2014 Microchip Technology Inc.
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26.0
Note:
COMPARATOR VOLTAGE
REFERENCE
26.1
Configuring the Comparator
Voltage Reference
The voltage reference module is controlled through the
CVRCON register (Register 26-1). The comparator
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The range to be
used is selected by the CVRR bit (CVRCON). The
primary difference between the ranges is the size of the
steps selected by the CVREF Selection bits
(CVR), with one range offering finer resolution.
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“Dual Comparator Module” (DS39710)
in the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF-. The voltage source is selected by the CVRSS
bit (CVRCON).
The settling time of the comparator voltage reference
must be considered when changing the CVREF output.
FIGURE 26-1:
VREF+
AVDD
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
8R
CVRSS = 0
CVR
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
CVREF
CVROE
R
R
CVREF
Pin
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
AVSS
2010-2014 Microchip Technology Inc.
DS30009996G-page 321
PIC24FJ128GA310 FAMILY
REGISTER 26-1:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
CVREFP
CVREFM1
CVREFM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10
CVREFP: Comparator Voltage Reference Select bit (valid only when CREF is ‘1’)
1 = VREF+ is used as a reference voltage to the comparators
0 = The CVR (4-bit DAC) within this module provides the reference voltage to the comparators
bit 9-8
CVREFM: Band Gap Reference Source Select bits (valid only when CCH = 11)
00 = Band gap voltage is provided as an input to the comparators
01 = Band gap voltage, divided by two, is provided as an input to the comparators
10 = Band gap voltage, divided by six, is provided as an input to the comparators
11 = VREF+ pin is provided as an input to the comparators
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on the CVREF pin
0 = CVREF voltage level is disconnected from the CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step-size
0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step-size
bit 4
CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = VREF+ – VREF0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR: Comparator VREF Value Selection 0 CVR 15 bits
When CVRR = 1:
CVREF = (CVR/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR/32) (CVRSRC)
DS30009996G-page 322
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
27.0
Note:
CHARGE TIME
MEASUREMENT UNIT (CTMU)
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Charge Measurement Unit, refer to
“Charge Time Measurement Unit
(CTMU)
with
Threshold
Detect”
(DS39743) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that provides charge
measurement, accurate differential time measurement
between pulse sources and asynchronous pulse
generation. Its key features include:
27.1
Measuring Capacitance
The CTMU module measures capacitance by
generating an output pulse with a width equal to the
time between edge events on two separate input
channels. The pulse edge events to both input
channels can be selected from four sources: two
internal peripheral modules (OC1 and Timer1) and up
to 13 external pins (CTEDG1 through CTEDG13). This
pulse is used with the module’s precision current
source to calculate capacitance according to the
relationship:
EQUATION 27-1:
dV
I = C ------dT
•
•
•
•
For capacitance measurements, the ADC samples an
external capacitor (CAPP) on one of its input channels
after the CTMU output’s pulse. A precision resistor
(RPR) provides current source calibration on a second
ADC channel. After the pulse ends, the converter
determines the voltage on the capacitor. The actual
calculation of capacitance is performed in software by
the application.
Together with other on-chip analog modules, the CTMU
can be used to precisely measure time, measure
capacitance, measure relative changes in capacitance
or generate output pulses that are independent of the
system clock. The CTMU module is ideal for interfacing
with capacitive-based touch sensors.
Figure 27-1 illustrates the external connections used
for capacitance measurements, and how the CTMU
and ADC modules are related in this application. This
example also shows the edge events coming from
Timer1, but other configurations using external edge
sources are possible. A detailed discussion on
measuring capacitance and time with the CTMU
module is provided in “Charge Time Measurement
Unit (CTMU)” (DS39724) in the “dsPIC33/PIC24
Family Reference Manual”.
Thirteen external edge input trigger sources
Polarity control for each edge source
Control of edge sequence
Control of response to edge levels or edge
transitions
• Time measurement resolution of one nanosecond
• Accurate current source suitable for capacitive
measurement
The CTMU is controlled through three registers:
CTMUCON1,
CTMUCON2
and
CTMUICON.
CTMUCON1 enables the module and controls the mode
of operation of the CTMU, as well as controlling edge
sequencing. CTMUCON2 controls edge source selection and edge source polarity selection. The CTMUICON
register selects the current range of current source and
trims the current.
2010-2014 Microchip Technology Inc.
DS30009996G-page 323
PIC24FJ128GA310 FAMILY
FIGURE 27-1:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR
CAPACITANCE MEASUREMENT
PIC24F Device
Timer1
CTMU
EDG1
Current Source
EDG2
Output Pulse
ADC Module
ANx
ANY
CAPP
27.2
RPR
Measuring Time
Time measurements on the pulse width can be similarly
performed using the ADC module’s internal capacitor
(CAD) and a precision resistor for current calibration.
Figure 27-2 displays the external connections used for
time measurements, and how the CTMU and ADC
modules are related in this application. This example
also shows both edge events coming from the external
CTEDG pins, but other configurations using internal
edge sources are possible.
27.3
Pulse Generation and Delay
The CTMU module can also generate an output pulse
with edges that are not synchronous with the device’s
system clock. More specifically, it can generate a pulse
with a programmable delay from an edge event input to
the module.
DS30009996G-page 324
When the module is configured for pulse generation
delay by setting the TGEN bit (CTMUCON1), the
internal current source is connected to the B input of
Comparator 2. A capacitor (CDELAY) is connected to
the Comparator 2 pin, C2INB, and the comparator
voltage reference, CVREF, is connected to C2INA.
CVREF is then configured for a specific trip point. The
module begins to charge CDELAY when an edge event
is detected. When CDELAY charges above the CVREF
trip point, a pulse is output on CTPLS. The length of the
pulse delay is determined by the value of CDELAY and
the CVREF trip point.
Figure 27-3 illustrates the external connections for
pulse generation, as well as the relationship of the
different analog modules required. While CTED1 is
shown as the input pulse source, other options are
available. A detailed discussion on pulse generation
with the CTMU module is provided in the “dsPIC33/
PIC24 Family Reference Manual”.
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 27-2:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME
MEASUREMENT
PIC24F Device
CTMU
CTEDX
EDG1
CTEDX
EDG2
Current Source
Output Pulse
ADC Module
ANx
CAD
RPR
FIGURE 27-3:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
PIC24F Device
CTEDX
CTMU
EDG1
CTPLS
Current Source
Comparator
C2INB
-
CDELAY
CVREF
2010-2014 Microchip Technology Inc.
C2
DS30009996G-page 325
PIC24FJ128GA310 FAMILY
REGISTER 27-1:
CTMUCON1: CTMU CONTROL REGISTER 1
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CTMUSIDL: CTMU Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 10
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9
IDISSEN: Analog Current Source Control bit
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8
CTTRIG: CTMU Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
bit 7-0
Unimplemented: Read as ‘0’
DS30009996G-page 326
x = Bit is unknown
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 27-2:
CTMUCON2: CTMU CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG1MOD
EDG1POL
EDG1SEL3
EDG1SEL2
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
EDG2MOD
EDG2POL
EDG2SEL3
EDG2SEL2
EDG2SEL1
EDG2SEL0
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
EDG1MOD: Edge 1 Edge-Sensitive Select bit
1 = Input is edge-sensitive
0 = Input is level-sensitive
bit 14
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
bit 13-10
EDG1SEL: Edge 1 Source Select bits
1111 = Edge 1 source is Comparator 3 output
1110 = Edge 1 source is Comparator 2 output
1101 = Edge 1 source is Comparator 1 output
1100 = Edge 1 source is IC3
1011 = Edge 1 source is IC2
1010 = Edge 1 source is IC1
1001 = Edge 1 source is CTED8
1000 = Edge 1 source is CTED7(1)
0111 = Edge 1 source is CTED6
0110 = Edge 1 source is CTED5
0101 = Edge 1 source is CTED4
0100 = Edge 1 source is CTED3(1)
0011 = Edge 1 source is CTED1
0010 = Edge 1 source is CTED2
0001 = Edge 1 source is OC1
0000 = Edge 1 source is Timer1
bit 9
EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control current source.
1 = Edge 2 has occurred
0 = Edge 2 has not occurred
bit 8
EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control current source.
1 = Edge 1 has occurred
0 = Edge 1 has not occurred
bit 7
EDG2MOD: Edge 2 Edge-Sensitive Select bit
1 = Input is edge-sensitive
0 = Input is level-sensitive
bit 6
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge
0 = Edge 2 is programmed for a negative edge
Note 1:
Edge sources, CTED3, CTED7, CTED10 and CTED11, are available in 100-pin devices only.
2010-2014 Microchip Technology Inc.
DS30009996G-page 327
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REGISTER 27-2:
CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED)
bit 5-2
EDG2SEL: Edge 2 Source Select bits
1111 = Edge 2 source is Comparator 3 output
1110 = Edge 2 source is Comparator 2 output
1101 = Edge 2 source is Comparator 1 output
1100 = Unimplemented Do not use
1011 = Edge 2 source is IC3
1010 = Edge 2 source is IC2
1001 = Edge 2 source is IC1
1000 = Edge 2 source is CTED13
0111 = Edge 2 source is CTED12
0110 = Edge 2 source is CTED11(1)
0101 = Edge 2 source is CTED10(1)
0100 = Edge 2 source is CTED9
0011 = Edge 2 source is CTED1
0010 = Edge 2 source is CTED2
0001 = Edge 2 source is OC1
0000 = Edge 2 source is Timer1
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
Edge sources, CTED3, CTED7, CTED10 and CTED11, are available in 100-pin devices only.
DS30009996G-page 328
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 27-3:
CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
ITRIM: Current Source Trim bits
011111 = Maximum positive change from nominal current
011110
.
.
.
000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG
111111 = Minimum negative change from nominal current
.
.
.
100010
100001 = Maximum negative change from nominal current
bit 9-8
IRNG: Current Source Range Select bits
11 = 100 × Base Current
10 = 10 × Base Current
01 = Base current level (0.55 A nominal)
00 = 1000 × Base Current
bit 7-0
Unimplemented: Read as ‘0’
2010-2014 Microchip Technology Inc.
x = Bit is unknown
DS30009996G-page 329
PIC24FJ128GA310 FAMILY
NOTES:
DS30009996G-page 330
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
28.0
The High/Low-Voltage Detect (HLVD) module is a
programmable circuit that allows the user to specify
both the device voltage trip point and the direction of
change.
HIGH/LOW-VOLTAGE DETECT
(HLVD)
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the High/Low-Voltage Detect, refer
to “High-Level
Integration
with
Programmable
High/Low-Voltage
Detect (HLVD)” (DS39725) in the
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
FIGURE 28-1:
VDD
An interrupt flag is set if the device experiences an
excursion past the trip point in the direction of change.
If the interrupt is enabled, the program execution will
branch to the interrupt vector address and the software
can then respond to the interrupt.
The HLVD Control register (see Register 28-1)
completely controls the operation of the HLVD module.
This allows the circuitry to be “turned off” by the user
under software control, which minimizes the current
consumption for the device.
HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Externally Generated
Trip Point
VDD
HLVDIN
HLVDL
16-to-1 MUX
HLVDEN
VDIR
Set
HLVDIF
Band Gap
1.2V Typical
HLVDEN
2010-2014 Microchip Technology Inc.
DS30009996G-page 331
PIC24FJ128GA310 FAMILY
REGISTER 28-1:
HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
HLVDEN
—
HLSIDL
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VDIR
BGVST
IRVST
—
HLVDL3
HLVDL2
HLVDL1
HLVDL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD is enabled
0 = HLVD is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
HLSIDL: HLVD Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-8
Unimplemented: Read as ‘0’
bit 7
VDIR: Voltage Change Direction Select bit
1 = Event occurs when voltage equals or exceeds trip point (HLVDL)
0 = Event occurs when voltage equals or falls below trip point (HLVDL)
bit 6
BGVST: Band Gap Voltage Stable Flag bit
1 = Indicates that the band gap voltage is stable
0 = Indicates that the band gap voltage is unstable
bit 5
IRVST: Internal Reference Voltage Stable Flag bit
1 = Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the
specified voltage range
0 = Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt
flag at the specified voltage range and the HLVD interrupt should not be enabled
bit 4
Unimplemented: Read as ‘0’
bit 3-0
HLVDL: High/Low-Voltage Detection Limit bits
1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = Trip Point 1(1)
1101 = Trip Point 2(1)
1100 = Trip Point 3(1)
.
.
.
0100 = Trip Point 11(1)
00xx = Unused
Note 1:
For the actual trip point, see Section 32.0 “Electrical Characteristics”.
DS30009996G-page 332
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
29.0
Note:
29.1.1
SPECIAL FEATURES
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
following sections of the “dsPIC33/PIC24
Family Reference Manual”. The information in this data sheet supersedes the
information in the FRMs.
In PIC24FJ128GA310 family devices, the Configuration bytes are implemented as volatile memory. This
means that configuration data must be programmed
each time the device is powered up. Configuration data
is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration
Words. Their specific locations are shown in
Table 29-1. These are packed representations of the
actual device Configuration bits, whose actual
locations are distributed among several locations in
configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the
proper Configuration registers during device Resets.
• “Watchdog Timer (WDT)”
(DS39697)
• “High-Level Device Integration”
(DS39719)
• “Programming and Diagnostics”
(DS39716)
Note:
PIC24FJ128GA310 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
•
•
•
•
•
•
The upper byte of all Flash Configuration Words in
program memory should always be ‘0000 0000’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘0’s to these
locations has no effect on device operation.
Configuration Bits
The Configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting at
program memory location, F80000h. A detailed explanation of the various bit functions is provided in
Register 29-1 through Register 29-6.
Note:
Note that address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh) which can only be
accessed using Table Reads and Table Writes.
TABLE 29-1:
Configuration data is reloaded on all types
of device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
Flexible Configuration
Watchdog Timer (WDT)
Code Protection
JTAG Boundary Scan Interface
In-Circuit Serial Programming™
In-Circuit Emulation
29.1
CONSIDERATIONS FOR
CONFIGURING PIC24FJ128GA310
FAMILY DEVICES
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ128GA310 FAMILY
DEVICES
Configuration Word Addresses
Device
1
2
3
4
PIC24FJ64GA3XX
ABFEh
ABFCh
ABFAh
ABF8h
PIC24FJ128GA3XX
157FEh
157FCh
157FAh
157F8h
2010-2014 Microchip Technology Inc.
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PIC24FJ128GA310 FAMILY
REGISTER 29-1:
CW1: FLASH CONFIGURATION WORD 1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
r-x
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
r
JTAGEN
GCP
GWRP
DEBUG
LPCFG
ICS1
ICS0
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
WINDIS
FWDTEN1
FWDTEN0
FWPSA
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
r = Reserved bit
PO = Program once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
Unimplemented: Read as ‘1’
bit 15
Reserved: The value is unknown; program as ‘0’
bit 14
JTAGEN: JTAG Port Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
bit 13
GCP: General Segment Program Memory Code Protection bit
1 = Code protection is disabled
0 = Code protection is enabled for the entire program memory space
bit 12
GWRP: General Segment Code Flash Write Protection bit
1 = Writes to program memory are allowed
0 = Writes to program memory are not allowed
bit 11
DEBUG: Background Debugger Enable bit
1 = Device resets into Operational mode
0 = Device resets into Debug mode
bit 10
LPCFG: Low-Voltage/Retention Regulator Configuration bit
1 = Low-voltage/retention regulator is always disabled
0 = Low-power, low-voltage/retention regulator is enabled and controlled in firmware by the RETEN bit
bit 9-8
ICS: Emulator Pin Placement Select bits
11 = Emulator functions are shared with PGEC1/PGED1
10 = Emulator functions are shared with PGEC2/PGED2
01 = Emulator functions are shared with PGEC3/PGED3
00 = Reserved; do not use
bit 7
WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard Watchdog Timer is enabled
0 = Windowed Watchdog Timer is enabled; (FWDTEN must not be ‘00’)
bit 6-5
FWDTEN: Watchdog Timer Configuration bits
11 = WDT is always enabled; SWDTEN bit has no effect
10 = WDT is enabled and controlled in firmware by the SWDTEN bit
01 = WDT is enabled only in Run mode and disabled in Sleep modes; SWDTEN bit is disabled
00 = WDT is disabled; SWDTEN bit is disabled
DS30009996G-page 334
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 29-1:
CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)
bit 4
FWPSA: WDT Prescaler Ratio Select bit
1 = Prescaler ratio of 1:128
0 = Prescaler ratio of 1:32
bit 3-0
WDTPS: Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
2010-2014 Microchip Technology Inc.
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REGISTER 29-2:
CW2: FLASH CONFIGURATION WORD 2
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
r-1
r-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
IESO
r
r
ALTVRF1
ALTVRF0
FNOSC2
FNOSC1
FNOSC0
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
r-1
R/PO-1
R/PO-1
FCKSM1
FCKSM0
OSCIOFCN
IOL1WAY
BOREN1
r
POSCMD1
POSCMD0
bit 7
bit 0
Legend:
r = Reserved bit
PO = Program once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
Unimplemented: Read as ‘1’
bit 15
IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
bit 14-13
Reserved: Always maintain as ‘1’
bit 12-11
ALTVRF: Alternate VREF/CVREF Pins Selection bits
00 = Comparator Voltage reference input VREF+ is RB0, VREF- is RB1, ADC VREF+ is RB0
ADC VREF- is RB1
01 = Comparator Voltage reference input VREF+ is RB0, VREF- is RB1, ADC VREF+ is RA10
ADC VREF- is RA9
10 = Comparator Voltage reference input VREF+ is RA10, VREF- is RA9, ADC VREF+ is RB0
ADC VREF- is RB1
11 = Comparator Voltage reference input VREF+ is RA10, VREF- is RA9, ADC VREF+ is RA10
ADC VREF- is RA9
bit 10-8
FNOSC: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7-6
FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5
OSCIOFCN: OSCO Pin Configuration bit
If POSCMD = 11 or 00:
1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2)
0 = OSCO/CLKO/RC15 functions as port I/O (RC15)
If POSCMD = 10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RC15.
DS30009996G-page 336
and
and
and
and
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 29-2:
CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
bit 4
IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON) can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
completed
bit 3
BOREN1: BOR Override bit
This bit should be set/cleared based on the BOREN (CW3) setting.
1 = BOR is enabled (CW3, BOREN = 1)
0 = BOR is disabled (CW3, BOREN = 0)
Allowed Combinations are Shown Below:
BOREN (CW3), BOREN1 (CW2):
11 = BOR is enabled
10 = Reserved
01 = Reserved
00 = BOR is disabled
bit 2
Reserved: Always maintain as ‘1’
bit 1-0
POSCMD: Primary Oscillator Configuration bits
11 = Primary Oscillator mode is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
2010-2014 Microchip Technology Inc.
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REGISTER 29-3:
CW3: FLASH CONFIGURATION WORD 3
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
r-1
R/PO-1
WPEND
WPCFG
WPDIS
BOREN
WDTWIN1
WDTWIN0
r
SOSCSEL
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
VBTBOR
WPFP6(3)
WPFP5
WPFP4
WPFP3
WPFP2
WPFP1
WPFP0
bit 7
bit 0
Legend:
r = Reserved bit
PO = Program once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
Unimplemented: Read as ‘1’
bit 15
WPEND: Segment Write Protection End Page Select bit
1 = Protected code segment upper boundary is at the last page of program memory; the lower
boundary is the code page specified by WPFP
0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper
boundary is the code page specified by WPFP
bit 14
WPCFG: Configuration Word Code Page Write Protection Select bit
1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected(1)
0 = Last page and Flash Configuration Words are write-protected provided WPDIS = 0
bit 13
WPDIS: Segment Write Protection Disable bit
1 = Segmented code protection is disabled
0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and
WPFPx Configuration bits
bit 12
BOREN: Brown-out Reset Enable bit (also see CW2 BOREN1)
1 = BOR is enabled (all modes except Deep Sleep) (BOREN1 = 1)
0 = BOR is disabled
Allowed Combinations are Shown Below:
BOREN (CW3), BOREN1 (CW2):
11 = BOR is enabled
10 = Reserved
01 = Reserved
00 = BOR is disabled (BOREN1 = 0)
bit 11-10
WDTWIN: Watchdog Timer Window Width Select bits
11 = 25%
10 = 37.5%
01 = 50%
00 = 75%
bit 9
Reserved: Always maintain as ‘1’
Note 1:
2:
3:
Regardless of WPCFG status, if WPEND = 1 or if WPFPx corresponds to the Configuration Word page,
the Configuration Word page is protected.
Ensure that the SCLKI pin is made a digital input while using this configuration (see Table 11-1).
For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be
maintained as ‘0’.
DS30009996G-page 338
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 29-3:
CW3: FLASH CONFIGURATION WORD 3 (CONTINUED)
bit 8
SOSCSEL: SOSC Selection bit
1 = SOSC circuit is selected
0 = Digital (SCLKI) mode(2)
bit 7
VBTBOR: VBAT BOR Enable bit
1 = VBAT BOR is enabled
0 = VBAT BOR is disabled
bit 6-0
WPFP: Write-Protected Code Segment Boundary Page bits(3)
Designates the 256 instruction words page boundary of the protected code segment.
If WPEND = 1:
Specifies the lower page boundary of the code-protected segment; the last page being the last
implemented page in the device.
If WPEND = 0:
Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary.
Note 1:
2:
3:
Regardless of WPCFG status, if WPEND = 1 or if WPFPx corresponds to the Configuration Word page,
the Configuration Word page is protected.
Ensure that the SCLKI pin is made a digital input while using this configuration (see Table 11-1).
For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be
maintained as ‘0’.
2010-2014 Microchip Technology Inc.
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PIC24FJ128GA310 FAMILY
REGISTER 29-4:
CW4: FLASH CONFIGURATION WORD 4
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
r-1
r-1
r-1
r-1
r-1
r-1
r-1
R/PO-1
r
r
r
r
r
r
r
DSSWEN
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DSWDTEN
DSBOREN
DSWDTOSC
DSWDPS4
DSWDPS3
DSWDPS2
DSWDPS1
DSWDPS0
bit 7
bit 0
Legend:
r = Reserved bit
PO = Program once bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
Unimplemented: Read as ‘1’
bit 15-9
Reserved: Read as ‘1’
bit 8
DSSWEN: Deep Sleep Software Control Select bit
1 = Deep Sleep operation is enabled and controlled by the DSEN bit
0 = Deep Sleep operation is disabled
bit 7
DSWDTEN: Deep Sleep Watchdog Timer Enable bit
1 = Deep Sleep WDT is enabled
0 = Deep Sleep WDT is disabled
bit 6
DSBOREN: Deep Sleep Brown-out Reset Enable bit
1 = BOR is enabled in Deep Sleep mode
0 = BOR is disabled in Deep Sleep mode (remains active in other Sleep modes)
bit 5
DSWDTOSC: Deep Sleep Watchdog Timer Clock Select bit
1 = Clock source is LPRC
0 = Clock source is SOSC
DS30009996G-page 340
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 29-4:
bit 4-0
CW4: FLASH CONFIGURATION WORD 4 (CONTINUED)
DSWDPS: Deep Sleep Watchdog Timer Postscaler Select bits
11111 = 1:68,719,476,736 (25.7 days)
11110 = 1:34,359,738,368(12.8 days)
11101 = 1:17,179,869,184 (6.4 days)
11100 = 1:8,589,934592 (77.0 hours)
11011 = 1:4,294,967,296 (38.5 hours)
11010 = 1:2,147,483,648 (19.2 hours)
11001 = 1:1,073,741,824 (9.6 hours)
11000 = 1:536,870,912 (4.8 hours)
10111 = 1:268,435,456 (2.4 hours)
10110 = 1:134,217,728 (72.2 minutes)
10101 = 1:67,108,864 (36.1 minutes)
10100 = 1:33,554,432 (18.0 minutes)
10011 = 1:16,777,216 (9.0 minutes)
10010 = 1:8,388,608 (4.5 minutes)
10001 = 1:4,194,304 (135.3 s)
10000 = 1:2,097,152 (67.7 s)
01111 = 1:1,048,576 (33.825 s)
01110 = 1:524,288 (16.912 s)
01101 = 1:262,114 (8.456 s)
01100 = 1:131,072 (4.228 s)
01011 = 1:65,536 (2.114 s)
01010 = 1:32,768 (1.057 s)
01001 = 1:16,384 (528.5 ms)
01000 = 1:8,192 (264.3 ms)
00111 = 1:4,096 (132.1 ms)
00110 = 1:2,048 (66.1 ms)
00101 = 1:1,024 (33 ms)
00100 = 1:512 (16.5 ms)
00011 = 1:256 (8.3 ms)
00010 = 1:128 (4.1 ms)
00001 = 1:64 (2.1 ms)
00000 = 1:32 (1 ms)
2010-2014 Microchip Technology Inc.
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PIC24FJ128GA310 FAMILY
REGISTER 29-5:
DEVID: DEVICE ID REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R
R
R
R
R
R
R
R
FAMID7
FAMID6
FAMID5
FAMID4
FAMID3
FAMID2
FAMID1
FAMID0
bit 15
bit 8
R
R
R
R
R
R
R
R
DEV7
DEV6
DEV5
DEV4
DEV3
DEV2
DEV1
DEV0
bit 7
bit 0
Legend: R = Readable bit
U = Unimplemented bit
bit 23-16
Unimplemented: Read as ‘1’
bit 15-8
FAMID: Device Family Identifier bits
0100 0110 = PIC24FJ128GA310 family
bit 7-0
DEV: Individual Device Identifier bits
1100 0000 = PIC24FJ64GA306
1100 0010 = PIC24FJ128GA306
1100 0100 = PIC24FJ64GA308
1100 0110 = PIC24FJ128GA308
1100 1000 = PIC24FJ64GA310
1100 1010 = PIC24FJ128GA310
REGISTER 29-6:
DEVREV: DEVICE REVISION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 23
bit 16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
—
—
—
—
R
R
R
R
REV
bit 7
bit 0
Legend: R = Readable bit
bit 23-4
Unimplemented: Read as ‘0’
bit 3-0
REV: Device revision identifier bits
DS30009996G-page 342
U = Unimplemented bit
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
29.2
On-Chip Voltage Regulator
All PIC24FJ128GA310 family devices power their core
digital logic at a nominal 1.8V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ128GA310 family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
This regulator is always enabled. It provides a constant
voltage (1.8V nominal) to the digital core logic, from a
VDD of about 2.1V all the way up to the device’s
VDDMAX. It does not have the capability to boost VDD
levels. In order to prevent “brown-out” conditions when
the voltage drops too low for the regulator, the
Brown-out Reset occurs. Then the regulator output
follows VDD with a typical voltage drop of 300 mV.
A low-ESR capacitor (such as ceramic) must be
connected to the VCAP pin (Figure 29-1). This helps to
maintain the stability of the regulator. The recommended
value for the filter capacitor (CEFC) is provided in
Section 32.1 “DC Characteristics”.
FIGURE 29-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
3.3V(1)
PIC24FJXXXGA3XX
29.2.1
ON-CHIP REGULATOR AND POR
The voltage regulator takes approximately 10 s for it
to generate output. During this time, designated as
TVREG, code execution is disabled. TVREG is applied
every time the device resumes operation after any
power-down, including Sleep mode. TVREG is determined by the status of the VREGS bit (RCON) and
the WDTWINx Configuration bits (CW3). Refer
to Section 32.0 “Electrical Characteristics” for more
information on TVREG.
Note:
29.2.2
For more information, see Section 32.0
“Electrical Characteristics”. The information in this data sheet supersedes the
information in the FRM.
VOLTAGE REGULATOR STANDBY
MODE
The on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when
the device is in Sleep mode, even though the core
digital logic does not require power. To provide additional savings in applications where power resources
are critical, the regulator can be made to enter Standby
mode on its own whenever the device goes into Sleep
mode. This feature is controlled by the VREGS bit
(RCON). Clearing the VREGS bit enables the
Standby mode. When waking up from Standby mode,
the regulator needs to wait for TVREG to expire before
wake-up.
VDD
VCAP
CEFC
(10 F typ)
Note 1:
VSS
This is a typical operating voltage. Refer to
Section 32.0 “Electrical Characteristics”
for the full operating ranges of VDD.
29.2.3
LOW-VOLTAGE/RETENTION
REGULATOR
When power-saving modes, such as Sleep and Deep
Sleep are used, PIC24FJ128GA310 family devices
may use a separate low-power, low-voltage/retention
regulator to power critical circuits. This regulator, which
operates at 1.2V nominal, maintains power to data
RAM and the RTCC while all other core digital logic is
powered down. It operates only in Sleep, Deep Sleep
and VBAT modes.
The low-voltage/retention regulator is described in more
detail in Section 10.1.3 “Low-Voltage/Retention
Regulator”.
2010-2014 Microchip Technology Inc.
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PIC24FJ128GA310 FAMILY
29.3
Watchdog Timer (WDT)
For PIC24FJ128GA310 family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT Time-out period (TWDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS Configuration bits (CW1), which allows the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
Note:
29.3.1
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CW1) to ‘0’.
The WDT, prescaler and postscaler are reset:
29.3.2
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
The WDT is enabled or disabled by the FWDTEN
Configuration bits. When the Configuration bits,
FWDTEN = 11, the WDT is always enabled.
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE
(RCON) bits will need to be cleared in software
after the device wakes up.
FIGURE 29-2:
CONTROL REGISTER
The WDT can be optionally controlled in software when
the Configuration bits, FWDTEN = 10. When
FWDTEN = 00, the Watchdog Timer is always
disabled. The WDT is enabled in software by setting
the SWDTEN control bit (RCON). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
WDT BLOCK DIAGRAM
SWDTEN
FWDTEN
LPRC Control
FWPSA
WDTPS
Prescaler
(5-bit/7-bit)
LPRC Input
31 kHz
Wake from Sleep
WDT
Counter
Postscaler
1:1 to 1:32.768
WDT Overflow
Reset
1 ms/4 ms
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
DS30009996G-page 344
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
29.4
Program Verification and
Code Protection
PIC24FJ128GA310 family devices provide two complimentary methods to protect application code from
overwrites and erasures. These also help to protect the
device from inadvertent configuration changes during
run time.
29.4.1
GENERAL SEGMENT PROTECTION
For all devices in the PIC24FJ128GA310 family, the
on-chip program memory space is treated as a single
block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration
bit, GCP. This bit inhibits external reads and writes to
the program memory space. It has no direct effect in
normal execution mode.
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.
29.4.2
CODE SEGMENT PROTECTION
In addition to global General Segment protection, a
separate subrange of the program memory space can
be individually protected against writes and erases.
This area can be used for many purposes where a separate block of write and erase-protected code is
needed, such as bootloader applications. Unlike
common boot block implementations, the specially
protected segment in the PIC24FJ128GA310 family
devices can be located by the user anywhere in the
program space and configured in a wide range of sizes.
Code segment protection provides an added level of
protection to a designated area of program memory by
disabling the NVM safety interlock whenever a write or
erase address falls within a specified range. It does not
override General Segment protection controlled by the
GCP or GWRP bits. For example, if GCP and GWRP
are enabled, enabling segmented code protection for
the bottom half of program memory does not undo
General Segment protection for the top half.
The size and type of protection for the segmented code
range are configured by the WPFPx, WPEND, WPCFG
and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS
bit (= 0). The WPFPx bits specify the size of the
segment to be protected by specifying the 512-word
code page that is the start or end of the protected
segment. The specified region is inclusive, therefore,
this page will also be protected.
The WPEND bit determines if the protected segment
uses the top or bottom of the program space as a
boundary. Programming WPEND (= 0) sets the bottom
of program memory (000000h) as the lower boundary
of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the
last page of implemented program memory, including
the Configuration Word locations.
A separate bit, WPCFG, is used to protect the last page
of program space, including the Flash Configuration
Words. Programming WPCFG (= 0) protects the last
page in addition to the pages selected by the WPEND
and WPFP bits setting. This is useful in circumstances where write protection is needed for both the
code segment in the bottom of the memory and the
Flash Configuration Words.
The various options for segment code protection are
shown in Table 29-2.
TABLE 29-2:
CODE SEGMENT PROTECTION CONFIGURATION OPTIONS
Segment Configuration Bits
Write/Erase Protection of Code Segment
WPDIS
WPEND
WPCFG
1
x
x
No additional protection is enabled; all program memory protection is configured
by GCP and GWRP.
0
1
x
Addresses from the first address of the code page are defined by
WPFP through the end of implemented program memory (inclusive);
erase/write-protected, including Flash Configuration Words.
0
0
1
Address, 000000h through the last address of the code page, is defined by
WPFP (inclusive); erase/write-protected.
0
0
0
Address, 000000h through the last address of the code page, is defined by
WPFP (inclusive); erase/write-protected and the last page, including Flash
Configuration Words, are erase/write-protected.
2010-2014 Microchip Technology Inc.
DS30009996G-page 345
PIC24FJ128GA310 FAMILY
29.4.3
CONFIGURATION REGISTER
PROTECTION
The Configuration registers are protected against
inadvertent or unwanted changes or reads in two ways.
The primary protection method is the same as that of
the RP registers – shadow registers contain a complimentary value which is constantly compared with the
actual value.
To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level
disruptions (such as ESD events) will cause a parity
error and trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence. Even
if General Segment protection is not enabled, the
device configuration can be protected by using the
appropriate code segment protection setting.
29.5
JTAG Interface
PIC24FJ128GA310 family devices implement a JTAG
interface, which supports boundary scan device
testing.
DS30009996G-page 346
29.6
In-Circuit Serial Programming
PIC24FJ128GA310 family microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGECx)
and data (PGEDx), and three other lines for power
(VDD), ground (VSS) and MCLR. This allows customers
to manufacture boards with unprogrammed devices
and then program the microcontroller just before
shipping the product. This also allows the most recent
firmware or a custom firmware to be programmed.
29.7
In-Circuit Debugger
When MPLAB® ICD 3 is selected as a debugger, the
in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pins.
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICSx Configuration bits. In addition,
when the feature is enabled, some of the resources are
not available for general use. These resources include
the first 80 bytes of data RAM and two I/O pins.
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
30.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
30.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2010-2014 Microchip Technology Inc.
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30.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
30.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
30.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
30.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
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30.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
30.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2010-2014 Microchip Technology Inc.
30.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
30.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
30.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
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30.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
30.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS30009996G-page 350
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31.0
Note:
INSTRUCTION SET SUMMARY
This chapter is a brief summary of the
PIC24F Instruction Set Architecture (ISA)
and is not intended to be a comprehensive
reference source.
The PIC24F instruction set adds many enhancements
to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
•
•
•
•
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register, ‘Wb’,
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register, ‘Wd’, with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the Table Read and Table Write
instructions
Word or byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
Table 31-1 shows the general symbols used in
describing the instructions. The PIC24F instruction set
summary in Table 31-2 lists all the instructions, along
with the status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register, ‘Wb’, without any address modifier
• The second source operand, which is typically a
register, ‘Ws’, with or without an address modifier
• The destination of the result, which is typically a
register, ‘Wd’, with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
Most bit-oriented instructions (including
rotate/shift instructions) have two operands:
The literal instructions that involve data movement may
use some of the following operands:
simple
All instructions are a single word, except for certain
double-word instructions, which were made
double-word instructions so that all the required information is available in these 48 bits. In the second word,
the 8 MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter (PC) is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles, with the additional instruction cycle(s)
executed as a NOP. Notable exceptions are the BRA
(unconditional/computed branch), indirect CALL/GOTO,
all Table Reads and Table Writes, and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles.
Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if
the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register, ‘Wb’)
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TABLE 31-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{ }
Optional field or operation
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
bit4
4-bit Bit Selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0000h...1FFFh}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16383}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388607}; LSB must be ‘0’
None
Field does not require an entry, may be blank
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor Working register pair (direct addressing)
Wn
One of 16 Working registers {W0..W15}
Wnd
One of 16 Destination Working registers {W0..W15}
Wns
One of 16 Source Working registers {W0..W15}
WREG
W0 (Working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
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TABLE 31-2:
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
BSW
BTG
BTSC
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
ADD
f
f = f + WREG
1
1
C, DC, N, OV, Z
ADD
f,WREG
WREG = f + WREG
1
1
C, DC, N, OV, Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C, DC, N, OV, Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C, DC, N, OV, Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C, DC, N, OV, Z
ADDC
f
f = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C, DC, N, OV, Z
AND
f
f = f .AND. WREG
1
1
N, Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N, Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N, Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N, Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N, Z
ASR
f
f = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C, N, OV, Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N, Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N, Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if Greater than or Equal
1
1 (2)
None
BRA
GEU,Expr
Branch if Unsigned Greater than or Equal
1
1 (2)
None
BRA
GT,Expr
Branch if Greater than
1
1 (2)
None
BRA
GTU,Expr
Branch if Unsigned Greater than
1
1 (2)
None
BRA
LE,Expr
Branch if Less than or Equal
1
1 (2)
None
BRA
LEU,Expr
Branch if Unsigned Less than or Equal
1
1 (2)
None
BRA
LT,Expr
Branch if Less than
1
1 (2)
None
BRA
LTU,Expr
Branch if Unsigned Less than
1
1 (2)
None
BRA
N,Expr
Branch if Negative
1
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws
1
1
None
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
None
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
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TABLE 31-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTSS
BTST
BTSTS
Assembly Syntax
# of
Words
Description
# of
Cycles
Status Flags
Affected
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
None
(2 or 3)
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
None
(2 or 3)
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws to C
1
1
C
Z
BTST.Z
Ws,Wb
Bit Test Ws to Z
1
1
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
CALL
CALL
lit23
Call Subroutine
2
2
None
CALL
Wn
Call Indirect Subroutine
1
2
None
CLR
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
Clear Watchdog Timer
1
1
WDTO, Sleep
CLRWDT
CLRWDT
COM
COM
f
f=f
1
1
N, Z
COM
f,WREG
WREG = f
1
1
N, Z
COM
Ws,Wd
Wd = Ws
1
1
N, Z
CP
f
Compare f with WREG
1
1
C, DC, N, OV, Z
CP
Wb,#lit5
Compare Wb with lit5
1
1
C, DC, N, OV, Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C, DC, N, OV, Z
CP0
CP0
f
Compare f with 0x0000
1
1
C, DC, N, OV, Z
CP0
Ws
Compare Ws with 0x0000
1
1
C, DC, N, OV, Z
CPB
CPB
f
Compare f with WREG, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C, DC, N, OV, Z
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, Skip if =
1
1
None
(2 or 3)
CPSGT
CPSGT
Wb,Wn
Compare Wb with Wn, Skip if >
1
1
None
(2 or 3)
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, Skip if <
1
1
None
(2 or 3)
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, Skip if
1
1
None
(2 or 3)
DAW
DAW.B
Wn
Wn = Decimal Adjust Wn
1
1
DEC
DEC
f
f = f –1
1
1
C, DC, N, OV, Z
DEC
f,WREG
WREG = f –1
1
1
C, DC, N, OV, Z
CP
C
DEC
Ws,Wd
Wd = Ws – 1
1
1
C, DC, N, OV, Z
DEC2
f
f=f–2
1
1
C, DC, N, OV, Z
DEC2
f,WREG
WREG = f – 2
1
1
C, DC, N, OV, Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C, DC, N, OV, Z
DISI
DISI
#lit14
Disable Interrupts for k Instruction Cycles
1
1
None
DIV
DIV.SW
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.UW
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N, Z, C, OV
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
DEC2
DS30009996G-page 354
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 31-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
GOTO
INC
INC2
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
GOTO
Expr
Go to Address
2
2
None
GOTO
Wn
Go to Indirect
1
2
None
INC
f
f=f+1
1
1
C, DC, N, OV, Z
INC
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC
Ws,Wd
Wd = Ws + 1
1
1
INC2
f
f=f+2
1
1
C, DC, N, OV, Z
INC2
f,WREG
WREG = f + 2
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N, Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N, Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N, Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N, Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N, Z
LNK
LNK
#lit14
Link Frame Pointer
1
1
None
LSR
LSR
f
f = Logical Right Shift f
1
1
C, N, OV, Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C, N, OV, Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C, N, OV, Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N, Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N, Z
MOV
f,Wn
Move f to Wn
1
1
None
MOV
[Wns+Slit10],Wnd
Move [Wns+Slit10] to Wnd
1
1
None
MOV
f
Move f to f
1
1
N, Z
MOV
f,WREG
Move f to WREG
1
1
N, Z
MOV
#lit16,Wn
Move 16-bit Literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit Literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wns,[Wns+Slit10]
Move Wns to [Wns+Slit10]
1
1
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
N, Z
MOV.D
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd+1):W(nd)
1
2
None
MUL.SS
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
f
f=f+1
1
1
C, DC, N, OV, Z
NEG
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
NEG
Ws,Wd
IOR
MOV
MUL
NEG
NOP
POP
Wd = Ws + 1
1
1
C, DC, N, OV, Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)
1
2
None
Pop Shadow Registers
1
1
All
POP.S
PUSH
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns+1) to Top-of-Stack (TOS)
1
2
None
Push Shadow Registers
1
1
None
PUSH.S
2010-2014 Microchip Technology Inc.
DS30009996G-page 355
PIC24FJ128GA310 FAMILY
TABLE 31-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
PWRSAV
PWRSAV
#lit1
Go into Sleep or Idle mode
1
1
WDTO, Sleep
RCALL
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
REPEAT
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
RESET
RESET
Software Device Reset
1
1
None
RETFIE
RETFIE
Return from Interrupt
1
3 (2)
None
RETLW
RETLW
Return with Literal in Wn
1
3 (2)
None
RETURN
RETURN
Return from Subroutine
1
3 (2)
None
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C, N, Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C, N, Z
C, N, Z
RLNC
RRC
RRNC
#lit10,Wn
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
RLNC
f
f = Rotate Left (No Carry) f
1
1
N, Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N, Z
N, Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
RRC
f
f = Rotate Right through Carry f
1
1
C, N, Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C, N, Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C, N, Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N, Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N, Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N, Z
SE
SE
Ws,Wnd
Wnd = Sign-Extended Ws
1
1
C, N, Z
SETM
SETM
f
f = FFFFh
1
1
None
SETM
WREG
WREG = FFFFh
1
1
None
SETM
Ws
Ws = FFFFh
1
1
None
SL
f
f = Left Shift f
1
1
C, N, OV, Z
SL
f,WREG
WREG = Left Shift f
1
1
C, N, OV, Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C, N, OV, Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N, Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N, Z
SUB
f
f = f – WREG
1
1
C, DC, N, OV, Z
SUB
f,WREG
WREG = f – WREG
1
1
C, DC, N, OV, Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C, DC, N, OV, Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C, DC, N, OV, Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C, DC, N, OV, Z
SUBB
f
f = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C, DC, N, OV, Z
SL
SUB
SUBB
SUBR
SUBBR
SWAP
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C, DC, N, OV, Z
SUBR
f
f = WREG – f
1
1
C, DC, N, OV, Z
SUBR
f,WREG
WREG = WREG – f
1
1
C, DC, N, OV, Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
SUBBR
f
f = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
SWAP.b
Wn
Wn = Nibble Swap Wn
1
1
None
SWAP
Wn
Wn = Byte Swap Wn
1
1
None
DS30009996G-page 356
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 31-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
Description
# of
Words
# of
Cycles
Status Flags
Affected
TBLRDH
TBLRDH
Ws,Wd
Read Prog to Wd
1
2
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
2
None
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog
1
2
None
ULNK
ULNK
Unlink Frame Pointer
1
1
None
XOR
XOR
f
f = f .XOR. WREG
1
1
N, Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N, Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N, Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N, Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N, Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C, Z, N
ZE
2010-2014 Microchip Technology Inc.
None
DS30009996G-page 357
PIC24FJ128GA310 FAMILY
NOTES:
DS30009996G-page 358
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
32.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ128GA310 family electrical characteristics. Additional information will
be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ128GA310 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin, and MCLR with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS when VDD < 3.0V............................................ -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS when VDD > 3.0V..................................................... -0.3V to (+5.5V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 1)................................................................................................................250 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 1)....................................................................................................200 mA
Note 1:
†
Maximum allowable current is a function of device maximum power dissipation (see Table 32-1).
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2010-2014 Microchip Technology Inc.
DS30009996G-page 359
PIC24FJ128GA310 FAMILY
32.1
DC Characteristics
FIGURE 32-1:
PIC24FJ128GA310 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
3.6V
3.6V
Voltage (VDD)
PIC24FJXXXGA3XX
2.2V
2.0V
2.2V
2.0V
32 MHz
Frequency
VCAP (nominal On-Chip Regulator output voltage) = 1.8V.
Note:
TABLE 32-1:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
PIC24FJ128GA310 Family:
Power Dissipation:
Internal Chip Power Dissipation: PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJMAX – TA)/JA
W
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 32-2:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Note
Package Thermal Resistance, 14x14x1 mm 100-pin TQFP
JA
43.0
—
°C/W
(Note 1)
Package Thermal Resistance, 12x12x1 mm 100-pin TQFP
JA
45.0
—
°C/W
(Note 1)
Package Thermal Resistance, 12x12x1 mm 80-pin TQFP
JA
48.0
—
°C/W
(Note 1)
Package Thermal Resistance, 10x10x1 mm 64-pin TQFP
JA
48.3
—
°C/W
(Note 1)
Package Thermal Resistance, 9x9x0.9 mm 64-pin QFN
JA
28.0
—
°C/W
(Note 1)
Package Thermal Resistance, 10x10x1.1 mm 121-pin BGA
JA
40.2
—
°C/W
(Note 1)
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS30009996G-page 360
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-3:
DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
Operating Voltage
DC10
VDD
Supply Voltage
2
—
3.6
V
DC12
VDR
RAM Data Retention
Voltage(1)
1.9
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
VSS
—
—
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
V/ms
VBOR
Brown-out Reset Voltage
on VDD Transition,
High-to-Low
2
—
2.2
V
Note 1:
With BOR disabled
0-3.3V in 66 ms
0-2.5V in 50 ms
This is the limit to which the RAM data can be retained while the on-chip regulator output voltage starts
following the VDD.
TABLE 32-4:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Operating
Temperature
VDD
Conditions
Operating Current (IDD)
DC19
0.15
—
mA
-40°C to +85°C
2.0V
DC20A
0.15
—
mA
-40°C to +85°C
3.3V
DC20
0.31
—
mA
-40°C to +85°C
2.0V
0.32
—
mA
-40°C to +85°C
3.3V
1.2
—
mA
-40°C to +85°C
2.0V
1.25
—
mA
-40°C to +85°C
3.3V
4.8
6.8
mA
-40°C to +85°C
2.0V
4.9
6.9
mA
-40°C to +85°C
3.3V
26
78
A
-40°C to +85°C
2.0V
26
80
A
-40°C to +85°C
3.3V
DC23
DC24
DC31
Note 1:
0.5 MIPS,
FOSC = 1 MHz
1 MIPS,
FOSC = 2 MHz
4 MIPS,
FOSC = 8 MHz
16 MIPS,
FOSC = 32 MHz
LPRC (15.5 KIPS),
FOSC = 31 kHz
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Typical parameters are for design
guidance only and are not tested.
2010-2014 Microchip Technology Inc.
DS30009996G-page 361
PIC24FJ128GA310 FAMILY
TABLE 32-5:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Max
Units
Operating
Temperature
VDD
81
—
A
-40°C to +85°C
2.0V
86
—
A
-40°C to +85°C
3.3V
Typical(1)
Conditions
Idle Current (IIDLE)
DC40
DC43
DC47
DC50
DC51
Note 1:
0.27
—
mA
-40°C to +85°C
2.0V
0.28
—
mA
-40°C to +85°C
3.3V
1
1.35
mA
-40°C to +85°C
2.0V
1.07
1.4
mA
-40°C to +85°C
3.3V
0.47
—
mA
-40°C to +85°C
2.0V
0.48
—
mA
-40°C to +85°C
3.3V
21
76
A
-40°C to +85°C
2.0V
21
78
A
-40°C to +85°C
3.3V
1 MIPS,
FOSC = 2 MHz
4 MIPS,
FOSC = 8 MHz
16 MIPS,
FOSC = 32 MHz
4 MIPS (FRC),
FOSC = 8 MHz
LPRC (15.5 KIPS),
FOSC = 31 kHz
Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
DS30009996G-page 362
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-6:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Operating
Temperature
Conditions
VDD
Power-Down Current (IPD)
DC60
DC61
DC70
Note 1:
2:
3:
4:
—
—
A
-40°C
3.7
—
A
+25°C
6.2
—
A
+60°C
13.6
27.5
A
+85°C
—
—
A
-40°
3.8
—
A
+25°C
6.3
—
A
+60°C
13.7
28
A
+85°C
—
—
A
-40°
0.33
—
A
+25°C
2
—
A
+60°C
7.7
14.5
A
+85°C
—
—
A
-40°
0.34
—
A
+25°C
2
—
A
+60°C
7.9
15
A
+85°C
—
—
A
-40°
0.01
—
A
+25°C
—
—
A
+60°C
—
1.1
A
+85°C
—
—
A
-40°
0.04
—
A
+25°C
—
—
A
+60°C
—
1.4
A
+85°C
0.4
2.0
A
-40°C to +85°C
2.0V
3.3V
Sleep(2)
2.0V
Low-Voltage Sleep(3)
3.3V
2.0V
3.3V
0V
Deep Sleep
RTCC with VBAT mode (LPRC/SOSC)(4)
Data in the Typical column is at 3.3V, +25°C unless otherwise stated. IPD is measured with all peripherals
and clocks (PMD) shutdown; all the ports are made output and driven low.
The retention low-voltage regulator is disabled; RETEN (RCON) = 0, LPCFG (CW1) = 1.
The retention low-voltage regulator is enabled; RETEN (RCON) = 1, LPCFG (CW1) = 0.
The VBAT pin is connected to the battery and RTCC is running with VDD = 0.
2010-2014 Microchip Technology Inc.
DS30009996G-page 363
PIC24FJ128GA310 FAMILY
TABLE 32-7:
DC CHARACTERISTICS: CURRENT (BOR, WDT, DSBOR, DSWDT, LCD)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Operating
Temperature
VDD
Conditions
Incremental Current Brown-out Reset (BOR)(2)
DC20
3.1
5
A
-40°C to +85°C
2.0V
4.3
6
A
-40°C to +85°C
3.3V
BOR(2)
Incremental Current Watch Dog Timer (WDT)(2)
DC71
0.8
1.5
A
-40°C to +85°C
2.0V
0.8
1.5
A
-40°C to +85°C
3.3V
WDT(2)
Incremental Current HLVD (HLVD)(2)
DC75
5.7
15
A
-40°C to +85°C
2.0V
5.7
15
A
-40°C to +85°C
3.3V
HLVD(2)
Incremental Current Real-Time Clock and Calendar (RTCC)(2)
DC77
0.4
1
A
-40°C to +85°C
2.0V
0.4
1
A
-40°C to +85°C
3.3V
RTCC(2),
RTCC with SOSC
Incremental Current Real-Time Clock and Calendar (RTCC)(2)
DC77a
0.4
1
A
0.4
1
A
-40°C to +85°C
2.0V
-40°C to +85°C
3.3V
RTCC(2),
RTCC with LPRC
(2)
Incremental Current Deep Sleep BOR ( DSBOR)
DC81
0.07
0.3
A
-40°C to +85°C
2.0V
0.07
0.3
A
-40°C to +85°C
3.3V
Deep Sleep BOR(2)
Incremental Current Deep Sleep Watchdog Timer Reset ( DSWDT)(2)
DC80
0.27
0.4
A
-40°C to +85°C
2.0V
0.27
0.4
A
-40°C to +85°C
3.3V
Deep Sleep WDT(2)
Incremental Current LCD ( LCD)(2)
DC90
0.8
3
A
-40°C to +85°C
20
30
A
-40°C to +85°C
2.0V
24
40
A
-40°C to +85°C
3.3V
LCD Charge Pump(2,4),
1/8 MUX, 1/3 Bias
1.5
—
A
-40°C to +85°C
3.3V
VBAT = 2V
4
—
A
-40°C to +85°C
3.3V
VBAT = 3.3V
3.3V
LCD External/Internal(2,3),
1/8 MUX, 1/3 Bias
VBAT ADC Monitor(5)
DC91
Note 1:
2:
3:
4:
5:
Data in the Typical column is at 3.3V, +25°C unless otherwise stated. IPD is measured with all peripherals
and clocks (PMD) shut down; all the ports are made output and driven low.
Incremental current while the module is enabled and running.
LCD is enabled and running; no glass is connected; the resistor ladder current is not included.
LCD is enabled and running; no glass is connected.
The ADC channel is connected to the VBAT pin internally; this is the current during ADC VBAT operation.
DS30009996G-page 364
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Typ(1)
Max
Units
Input Low Voltage(3)
DI10
I/O Pins with ST Buffer
VSS
—
0.2 VDD
V
DI11
I/O Pins with TTL Buffer
VSS
—
0.15 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
OSCI (XT mode)
VSS
—
0.2 VDD
V
DI17
OSCI (HS mode)
VSS
—
0.2 VDD
V
DI18
I/O Pins with I2C™ Buffer
VSS
—
0.3 VDD
V
I/O Pins with SMBus Buffer
VSS
—
0.8
V
I/O Pins with ST Buffer:
with Analog Functions,
Digital Only
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
I/O Pins with TTL Buffer:
with Analog Functions,
Digital Only
0.25 VDD + 0.8
0.25 VDD + 0.8
—
—
VDD
5.5
V
V
DI19
VIH
DI20
DI21
Conditions
SMBus enabled
Input High Voltage(3)
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSCI (XT mode)
0.7 VDD
—
VDD
V
DI27
OSCI (HS mode)
0.7 VDD
—
VDD
V
I/O Pins with
Buffer:
with Analog Functions,
Digital Only
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
I/O Pins with SMBus Buffer:
with Analog Functions,
Digital Only
2.1
2.1
VDD
5.5
V
V
CNxx Pull-up Current
150
290
550
A
VDD = 3.3V, VPIN = VSS
CNxx Pull-down Current
150
260
550
A
VDD = 3.3V, VPIN = VDD
—
—
+1
A
VSS VPIN VDD,
pin at high-impedance
—
—
+1
A
VSS VPIN 5.5,
pin at high-impedance
I2C™
DI28
DI29
DI30
ICNPU
DI30A ICNPD
IIL
DI50
2.5V VPIN VDD
Input Leakage Current(2)
I/O Ports
DI51
Analog Input Pins
—
—
+1
A
VSS VPIN VDD,
pin at high-impedance
DI55
MCLR
—
—
+1
A
VSS VPIN VDD
DI56
OSCI/CLKI
—
—
+1
A
VSS VPIN VDD,
EC, XT and HS modes
Note 1:
2:
3:
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Negative current is defined as current sourced by the pin.
Refer to Table 1-4 for I/O pins buffer types.
2010-2014 Microchip Technology Inc.
DS30009996G-page 365
PIC24FJ128GA310 FAMILY
TABLE 32-9:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
Symbol
No.
VOL
DO10
OSCO/CLKO
VOH
DO20
Typ(1)
Max
Units
Conditions
—
—
0.4
V
IOL = 6.6 mA, VDD = 3.6V
—
—
0.4
V
IOL = 5.0 mA, VDD = 2V
—
—
0.4
V
IOL = 6.6 mA, VDD = 3.6V
—
—
0.4
V
IOL = 5.0 mA, VDD = 2V
3.0
—
—
V
IOH = -3.0 mA, VDD = 3.6V
Output High Voltage
I/O Ports
DO26
Min
Output Low Voltage
I/O Ports
DO16
Note 1:
Characteristic
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
OSCO/CLKO
2.4
—
—
V
IOH = -6.0 mA, VDD = 3.6V
1.65
—
—
V
IOH = -1.0 mA, VDD = 2V
1.4
—
—
V
IOH = -3.0 mA, VDD = 2V
2.4
—
—
V
IOH = -6.0 mA, VDD = 3.6V
1.4
—
—
V
IOH = -1.0 mA, VDD = 2V
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
TABLE 32-10: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Min
Typ(1)
Max
Units
10000
—
—
E/W
Conditions
Program Flash Memory
D130
EP
D131
VPR
Cell Endurance
-40C to +85C
VDD for Read
VMIN
—
3.6
V
VMIN = Minimum operating voltage
D132B
VDD for Self-Timed Write
VMIN
—
3.6
V
VMIN = Minimum operating voltage
D133A TIW
Self-Timed Word Write
Cycle Time
—
20
—
s
Self-Timed Row Write
Cycle Time
—
1.5
—
ms
D133B TIE
Self-Timed Page Erase
Time
20
—
40
ms
D134
TRETD
Characteristic Retention
20
—
—
Year
D135
IDDP
Supply Current during
Programming
—
16
—
mA
Note 1:
If no other specifications are violated
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS30009996G-page 366
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
Symbol
No.
Characteristics
Min
Typ
Max Units
Comments
VRGOUT
Regulator Output Voltage
—
1.8
—
V
VBG
Internal Band Gap Reference
1.14
1.2
1.26
V
CEFC
External Filter Capacitor Value
4.7
10
—
F
Series resistance < 3 Ohm
recommended; < 5 Ohm required
VREGS = 1 with any POR or BOR
TVREG
Voltage Regulator Start-up Time
—
10
—
s
TBG
Band Gap Reference Start-up
Time
—
1
—
ms
VLVR
Low-Voltage Regulator Output
Voltage
—
1.2
—
V
RETEN = 1, LPCFG = 0
TABLE 32-12: VBAT OPERATING VOLTAGE SPECIFICATIONS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Comments
VBT
Operating Voltage
1.6
—
3.6
V
Battery connected to the VBAT pin
VBTADC
VBAT ADC Monitoring
Voltage Specification(1)
1.6
—
3.6
V
ADC monitoring the VBAT pin
using the internal ADC channel
VBTRTC
—
1.65
—
V
RTCC Reset voltage with
VBTBOR (CW3) = 1
VBTRST
—
0.65
—
V
VBPOR bit (RCON2)
Reset voltage
Note 1:
Measuring the ADC value, using the ADC, is represented by the equation:
Measured Voltage = ((VBAT/2)/VDD) * 1024) for 10-bit ADC and
Measured Voltage = ((VBAT/2)VDD) * 4096) for 12-bit ADC.
TABLE 32-13: CTMU CURRENT SOURCE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param
No.
Min
Note 1:
2:
Sym
Characteristic
Typ(1) Max
Units
Comments
IOUT1 CTMU Current
Source, Base Range
—
550
—
nA
CTMUICON = 00
IOUT2 CTMU Current
Source, 10x Range
—
5.5
—
A
CTMUICON = 01
IOUT3 CTMU Current
Source, 100x Range
—
55
—
A
CTMUICON = 10
IOUT4 CTMU Current
Source, 1000x Range
—
550
—
A
CTMUICON = 11(2)
V
—
3
—
mV/°C
Voltage Change per
Degree Celsius
Conditions
2.5V < VDD < VDDMAX
Nominal value at center point of current trim range (CTMUICON = 000000).
Do not use this current range with temperature sensing diode.
2010-2014 Microchip Technology Inc.
DS30009996G-page 367
PIC24FJ128GA310 FAMILY
TABLE 32-14: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
Symbol
No.
DC18
VHLVD
DC101 VTHL
Note 1:
Characteristic
Min
Typ
Max
Units
3.45
—
3.75
V
3.30
—
3.6
V
HLVDL = 0110
3.00
—
3.3
V
HLVDL = 0111
2.80
—
3.1
V
HLVDL = 1000
2.70
—
2.95
V
HLVDL = 1001
2.50
—
2.75
V
HLVDL = 1010
2.40
—
2.60
V
HLVDL = 1011
2.30
—
2.5
V
HLVDL = 1100
2.20
—
2.4
V
HLVDL = 1101
2.10
—
2.3
V
HLVDL = 1110
2.00
—
2.2
V
—
1.20
—
V
HLVD Voltage on VDD HLVDL = 0100(1)
Transition
HLVDL = 0101
HLVD Voltage on
HLVDL = 1111
HLVDIN Pin Transition
Conditions
Trip points for values of HLVD, from ‘0000’ to ‘0011’, are not implemented.
TABLE 32-15: COMPARATOR DC SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Comments
D300
VIOFF
Input Offset Voltage
—
20
40
mV
D301
VICM
Input Common-Mode Voltage)
0
—
VDD
V
D302
CMRR
Common-Mode Rejection Ratio
55
—
—
dB
D306
IQCMP
AVDD Quiescent Current per
Comparator
—
27
—
A
Comparator
enabled
D307
TRESP
Response Time
—
300
—
ns
(Note 1)
D308
TMC2OV
Comparator Mode Change to
Valid Output
—
—
10
S
Note 1:
Measured with one input at VDD/2 and the other transitioning from VSS to VDD, 40 mV step,
15 mV overdrive.
TABLE 32-16: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
VDD/24
—
VDD/32
LSb
VRD310 CVRES
Resolution
VRD311 CVRAA
Absolute Accuracy
—
—
AVDD – 1.5
LSb
VRD312 CVRUR
Unit Resistor Value (R)
—
2K
—
DS30009996G-page 368
Comments
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
32.2
AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ128GA310 family AC characteristics and timing parameters.
TABLE 32-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Operating voltage VDD range as described in Section 32.1 “DC Characteristics”.
AC CHARACTERISTICS
FIGURE 32-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSCO
Load Condition 2 – for OSCO
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSCO
15 pF for OSCO output
VSS
TABLE 32-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO50
COSCO
OSCO/CLKO Pin
—
—
15
pF
In XT and HS modes when
external clock is used to drive
OSCI
DO56
CIO
All I/O Pins and OSCO
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
Note 1:
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2010-2014 Microchip Technology Inc.
DS30009996G-page 369
PIC24FJ128GA310 FAMILY
FIGURE 32-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OS30
OS30
Q1
Q2
Q3
OSCI
OS20
OS31
OS31
OS25
CLKO
OS40
OS41
TABLE 32-19: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Characteristic
Min
Typ(1)
Max
Units
External CLKI Frequency
(External clocks allowed
only in EC mode)
DC
4
—
—
32
8
MHz
MHz
EC
ECPLL
Oscillator Frequency
3.5
4
10
4
31
—
—
—
—
—
10
8
32
8
33
MHz
MHz
MHz
MHz
kHz
XT
XTPLL
HS
HSPLL
SOSC
OS20 TOSC
TOSC = 1/FOSC
—
—
—
—
OS25 TCY
Instruction Cycle Time(2)
62.5
—
DC
ns
OS30 TosL,
TosH
External Clock in (OSCI)
High or Low Time
0.45 x TOSC
—
—
ns
EC
OS31 TosR,
TosF
External Clock in (OSCI)
Rise or Fall Time
—
—
20
ns
EC
OS40 TckR
CLKO Rise Time(3)
—
6
10
ns
OS41 TckF
CLKO Fall Time(3)
—
6
10
ns
OS10 FOSC
Note 1:
2:
3:
Conditions
See Parameter OS10 for
FOSC value
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the
Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
DS30009996G-page 370
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-20: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2V TO 3.6V)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
OS50
FPLLI
Characteristic
PLL Input Frequency
Range(1)
OS52
TLOCK
PLL Start-up Time
(Lock Time)
OS53
DCLK
CLKO Stability (Jitter)
Note 1:
Min
Typ(1)
Max
Units
4
—
8
MHz
ECPLL mode
4
Conditions
—
8
MHz
HSPLL mode
4
—
8
MHz
XTPLL mode
—
—
128
s
-0.25
—
0.25
%
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
TABLE 32-21: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ
Max
Units
-1
—
1
%
F20
FRC Accuracy @
8 MHz(1,2)
-1.5
—
1.5
F21
LPRC @ 31 kHz
-20
—
20
Note 1:
2:
Conditions
-10°C TA +85°C
2V VDD 3.6V
%
-40°C TA -10°C
2V VDD 3.6V
%
-40°C TA +85°C
VCAP (on-chip regulator
output voltage) = 1.8V
Frequency is calibrated at +25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB)
must be kept to a minimum.
TABLE 32-22: RC OSCILLATOR START-UP TIME
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ
Max
Units
TFRC
—
15
—
s
TLPRC
—
50
—
s
2010-2014 Microchip Technology Inc.
Conditions
DS30009996G-page 371
PIC24FJ128GA310 FAMILY
FIGURE 32-4:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note:
Refer to Figure 32-2 for load conditions.
TABLE 32-23: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ(1)
Max
Units
DO31
TIOR
Port Output Rise Time
—
10
25
ns
DO32
TIOF
Port Output Fall Time
—
10
25
ns
DI35
TINP
INTx Pin High or Low
Time (input)
20
—
—
ns
DI40
TRBP
CNx High or Low Time
(input)
2
—
—
TCY
Note 1:
Conditions
Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS30009996G-page 372
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-24: RESET AND BROWN-OUT RESET REQUIREMENTS
AC CHARACTERISTICS
Para
m
No.
Symbo
l
Characteristic
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Min
Typ
Max
Units
Conditions
SY10
TMCL
MCLR Pulse Width (Low)
2
—
—
s
SY12
TPOR
Power-on Reset Delay
—
2
—
s
SY13
TIOZ
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
—
—
100
ns
SY25
TBOR
Brown-out Reset Pulse
Width
1
—
—
s
TRST
Internal State Reset Time
—
50
—
s
TPM
Program Memory
Wake-up Time
—
20
—
s
Sleep wake-up(1) with
VREGS = 0
—
1
—
s
Sleep wake-up(1) with
VREGS = 1
—
90
—
s
Sleep wake-up(1) with
VREGS = 0
—
70
—
s
Sleep wake-up(1) with
VREGS = 1
—
200
—
s
VCAP fully discharged before
wake-up(1)
SY71
SY72
TLVR
Low-Voltage Regulator
Wake-up Time
TDSWU Deep Sleep Wake-up
Time
Note 1:
VDD VBOR
Wake-up times are based on the CPU running on the external EC clock.
2010-2014 Microchip Technology Inc.
DS30009996G-page 373
PIC24FJ128GA310 FAMILY
FIGURE 32-5:
TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT TIMING
TxCK Pin
TtL
TtH
TtP
TABLE 32-25: TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT REQUIREMENTS(1)
Param.
No.
Symbol
TtH
TtL
Characteristic
Min
Max
Units
TxCK High Pulse Time Synchronous w/Prescaler
TCY + 20
—
ns
10
—
ns
Asynchronous Counter
20
—
ns
TCY + 20
—
ns
TxCK Low Pulse Time Synchronous w/Prescaler
TtP
TxCK External Input
Period
Delay for Input Edge
to Timer Increment
Note 1:
Asynchronous w/Prescaler
Asynchronous w/Prescaler
10
—
ns
Asynchronous Counter
20
—
ns
Synchronous w/Prescaler
2 * TCY + 40
—
ns
Asynchronous w/Prescaler
Greater of:
20 or
2 * TCY + 40
N
—
ns
Asynchronous Counter
40
—
ns
Synchronous
1
2
TCY
Asynchronous
—
20
ns
Conditions
Must also meet
Parameter Ttp
Must also meet
Parameter Ttp
N = Prescale Value
(1, 4, 8, 16)
Asynchronous mode is available only on Timer1.
FIGURE 32-6:
INPUT CAPTURE x TIMINGS
ICx Pin
(Input Capture Mode)
IC10
IC11
IC15
TABLE 32-26: INPUT CAPTURE x REQUIREMENTS
Param.
Symbol
No.
IC10
IC11
IC15
TccL
TccH
TccP
Characteristic
ICx Input Low Time –
Synchronous Timer
With Prescaler
No Prescaler
ICx Input Low Time –
Synchronous Timer
With Prescaler
No Prescaler
ICx Input Period – Synchronous Timer
DS30009996G-page 374
Min
Max
Units
TCY + 20
—
ns
20
—
ns
TCY + 20
—
ns
20
—
ns
2 * TCY + 40
N
—
ns
Conditions
Must also meet
Parameter IC15
Must also meet
Parameter IC15
N = Prescale Value
(1, 4, 16)
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 32-7:
INPUT CAPTURE x TIMINGS
ICx Pin
(Input Capture Mode)
IC11
IC10
IC15
TABLE 32-27: INPUT CAPTURE x TIMINGS REQUIREMENTS
Param.
Symbol
No.
IC10
IC11
IC15
TccL
TccH
TccP
Characteristic
ICx Input Low Time –
Synchronous Timer
ICx Input Low Time –
Synchronous Timer
Max
Units
TCY + 20
—
ns
20
—
ns
TCY + 20
—
ns
20
—
ns
2 * TCY + 40
N
—
ns
No Prescaler
With Prescaler
No Prescaler
With Prescaler
ICx Input Period – Synchronous Timer
FIGURE 32-8:
Min
Conditions
Must also meet
Parameter IC15
Must also meet
Parameter IC15
N = Prescale
Value (1, 4, 16)
OUTPUT COMPARE x TIMINGS
OCx
(Output Compare or PWM Mode)
OC11
TABLE 32-28:
OUTPUT COMPARE 1 TIMINGS
Param.
No.
Symbol
OC11
TCCR
OC1 Output Rise Time
OC10
TCCF
OC1 Output Fall Time
FIGURE 32-9:
OC10
Characteristic
Min
Max
Unit
—
10
ns
—
—
ns
—
10
ns
—
—
ns
Condition
PWM MODULE TIMING REQUIREMENTS
OC20
OCFx
OC15
PWM
2010-2014 Microchip Technology Inc.
DS30009996G-page 375
PIC24FJ128GA310 FAMILY
TABLE 32-29: PWM TIMING REQUIREMENTS
Param.
Symbol
No.
Characteristic
Min
Typ(1)
Max
Unit
Condition
OC15
TFD
Fault Input to PWM I/O
Change
—
—
25
ns
VDD = 3.0V, -40C to +85C
OC20
TFH
Fault Input Pulse Width
50
—
—
ns
VDD = 3.0V, -40C to +85C
Note 1: Data in “Typ” column is at 3.3V, +25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 32-10:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
TABLE 32-30: I2Cx BUS START/STOP BITS TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C (Industrial)
AC CHARACTERISTICS
Param
Symbol
No.
IM30
TSU:STA
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
IM31
TSU:STO Stop Condition
Setup Time
IM33
Min(1)
Max
Units
100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
1 MHz mode(2)
TCY/2 (BRG + 1)
—
s
100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
1 MHz mode(2)
TCY/2 (BRG + 1)
—
s
Characteristic
100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
mode(2)
TCY/2 (BRG + 1)
—
s
100 kHz mode
TCY/2 (BRG + 1)
—
ns
400 kHz mode
TCY/2 (BRG + 1)
—
ns
1 MHz mode(2)
TCY/2 (BRG + 1)
—
ns
1 MHz
THD:STO Stop Condition
IM34
Hold Time
Note 1:
2:
Conditions
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
2C™
Baud Rate Generator. Refer to Section 17.2 “Setting Baud Rate When
BRG is the value of the I
Operating as a Bus Master” for details.
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
DS30009996G-page 376
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 32-11:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM11
SCLx
IM21
IM10
IM20
IM26
IM25
SDAx
In
IM45
IM40
SDAx
Out
TABLE 32-31: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C (Industrial)
AC CHARACTERISTICS
Param
No.
Symbol
TLO:SCL
IM10
IM11
THI:SCL
Characteristic
Min(1)
Max
Units
Clock Low Time 100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
1 MHz mode(2)
TCY/2 (BRG + 1)
—
s
Clock High Time 100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
mode(2)
TCY/2 (BRG + 1)
—
s
—
300
ns
1 MHz
IM20
TF:SCL
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
1 MHz mode(2)
IM21
TR:SCL
IM25
TSU:DAT
IM26
THD:DAT
IM40
TAA:SCL
IM45
TBF:SDA
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
Data Input
Setup Time
Data Input
Hold Time
Output Valid
From Clock
Bus Free Time
CB
Note 1:
2:
300
ns
—
100
ns
—
1000
ns
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(2)
—
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
1 MHz mode(2)
—
—
ns
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
1 MHz mode(2)
—
—
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(2)
IM50
20 + 0.1 CB
Bus Capacitive Loading
—
—
s
—
400
pF
Conditions
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Time the bus must be
free before a new
transmission can start
BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 17.2 “Setting Baud Rate When
Operating as a Bus Master” for details.
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
2010-2014 Microchip Technology Inc.
DS30009996G-page 377
PIC24FJ128GA310 FAMILY
FIGURE 32-12:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
TABLE 32-32: I2Cx BUS START/STOP BITS TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C (Industrial)
AC CHARACTERISTICS
Param
No.
IS30
Symbol
TSU:STA
THD:STA
IS31
TSU:STO
IS33
THD:STO
IS34
Note 1:
Characteristic
Start Condition
Setup Time
100 kHz mode
Min
Max
Units
Conditions
4.7
—
s
Only relevant for Repeated
Start condition
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
—
s
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
—
s
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.6
—
s
Stop Condition
100 kHz mode
4000
—
ns
Hold Time
400 kHz mode
600
—
ns
1 MHz mode(1)
250
—
ns
Start Condition
Hold Time
Stop Condition
Setup Time
After this period, the first
clock pulse is generated
Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).
FIGURE 32-13:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS11
IS10
IS21
SCLx
IS25
IS20
IS26
SDAx
In
IS45
IS40
SDAx
Out
DS30009996G-page 378
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C (Industrial)
AC CHARACTERISTICS
Param
No.
IS10
IS11
IS20
IS21
IS25
IS26
IS40
IS45
IS50
Note 1:
Symbol
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
TSU:DAT
THD:DAT
TAA:SCL
TBF:SDA
CB
Characteristic
Clock Low Time
Clock High Time
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
Data Input
Setup Time
Data Input
Hold Time
Min
Max
Units
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(1)
100
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
1 MHz mode(1)
0
0.3
s
Output Valid From 100 kHz mode
Clock
400 kHz mode
0
3500
ns
0
1000
ns
1 MHz mode(1)
0
350
ns
Bus Free Time
Conditions
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(1)
0.5
—
s
—
400
pF
Bus Capacitive Loading
—
—
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Time the bus must be free
before a new transmission
can start
Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).
2010-2014 Microchip Technology Inc.
DS30009996G-page 379
PIC24FJ128GA310 FAMILY
FIGURE 32-14:
SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 0)
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP31
SDIx
LSb
SP30
MSb In
LSb In
Bit 14 - - - -1
SP40 SP41
TABLE 32-34: SPIx MASTER MODE TIMING REQUIREMENTS (CKE = 0)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
SP10
TscL
SCKx Output Low Time(2)
TCY/2
—
—
ns
SP11
TscH
SCKx Output High Time(2)
TCY/2
—
—
ns
—
10
25
ns
—
10
25
ns
Time(3)
SP20
TscF
SCKx Output Fall
SP21
TscR
SCKx Output Rise Time(3)
(3)
SP30
TdoF
SDOx Data Output Fall Time
—
10
25
ns
SP31
TdoR
SDOx Data Output Rise Time(3)
—
10
25
ns
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—
—
30
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
20
—
—
ns
Conditions
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not
violate this specification.
3: Assumes 50 pF load on all SPIx pins.
DS30009996G-page 380
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 32-15:
SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 1)
SP36
SCKx
(CKP = 0)
SP11
SCKx
(CKP = 1)
SP10
SP21
SP20
SP20
SP21
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP40
SDIx
LSb
SP30,SP31
Bit 14 - - - -1
MSb In
LSb In
SP41
TABLE 32-35: SPIx MODULE MASTER MODE TIMING REQUIREMENTS (CKE = 1)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
SP10
TscL
SCKx Output Low Time(2)
TCY/2
—
—
ns
SP11
TscH
SCKx Output High Time(2)
TCY/2
—
—
ns
—
10
25
ns
—
10
25
ns
—
10
25
ns
—
10
25
ns
(3)
SP20
TscF
SCKx Output Fall Time
SP21
TscR
SCKx Output Rise Time(3)
Time(3)
SP30
TdoF
SDOx Data Output Fall
SP31
TdoR
SDOx Data Output Rise Time(3)
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
30
ns
SP36
TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
20
—
—
ns
Hold Time of SDIx Data Input
to SCKx Edge
Conditions
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
3: Assumes 50 pF load on all SPIx pins.
2010-2014 Microchip Technology Inc.
DS30009996G-page 381
PIC24FJ128GA310 FAMILY
FIGURE 32-16:
SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 0)
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
LSb
Bit 14 - - - - - -1
SP51
SP30,SP31
SDIx
SDI
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
TABLE 32-36: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 0)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
SP70
TscL
SCKx Input Low Time
30
—
—
ns
SP71
TscH
SCKx Input High Time
30
—
—
ns
SP72
TscF
SCKx Input Fall Time(2)
—
10
25
ns
SP73
TscR
SCKx Input Rise Time(2)
—
10
25
ns
—
10
25
ns
—
10
25
ns
(2)
SP30
TdoF
SDOx Data Output Fall Time
SP31
TdoR
SDOx Data Output Rise Time(2)
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
30
ns
SP40
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
20
—
—
ns
SP50
TssL2scH, SSx to SCKx or SCKx Input
TssL2scL
120
—
—
ns
SP51
TssH2doZ
10
—
50
ns
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
SSx to SDOx Output
High-Impedance
Conditions
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Assumes 50 pF load on all SPIx pins.
DS30009996G-page 382
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 32-17:
SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 1)
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIx
MSb In
LSb In
Bit 14 - - - -1
SP41
SP40
TABLE 32-37: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
SP70
TscL
SCKx Input Low Time
30
—
—
ns
SP71
TscH
SCKx Input High Time
30
—
—
ns
—
10
25
ns
—
10
25
ns
—
10
25
ns
—
10
25
ns
Time(2)
SP72
TscF
SCKx Input Fall
SP73
TscR
SCKx Input Rise Time(2)
Time(2)
SP30
TdoF
SDOx Data Output Fall
SP31
TdoR
SDOx Data Output Rise Time(2)
SP35
TscH2doV, SDOx Data Output Valid after SCKx Edge
TscL2doV
—
—
30
ns
SP40
TdiV2scH, Setup Time of SDIx Data Input to
TdiV2scL SCKx Edge
20
—
—
ns
SP41
TscH2diL, Hold Time of SDIx Data Input to
TscL2diL SCKx Edge
20
—
—
ns
SP50
TssL2scH, SSx to SCKx or SCKx Input
TssL2scL
120
—
—
ns
SP51
TssH2doZ SSx to SDOx Output
High-Impedance(3)
10
—
50
ns
Conditions
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
3: Assumes 50 pF load on all SPIx pins.
2010-2014 Microchip Technology Inc.
DS30009996G-page 383
PIC24FJ128GA310 FAMILY
TABLE 32-37: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1) (CONTINUED)
Standard Operating Conditions: 2.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Min
Typ(1)
Max
Units
1.5 TCY + 40
—
—
ns
—
—
50
ns
Characteristic
SSx after SCKx Edge
SP52
TscH2ssH
TscL2ssH
SP60
TssL2doV SDOx Data Output Valid after SSx Edge
Conditions
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
3: Assumes 50 pF load on all SPIx pins.
FIGURE 32-18:
UARTx BAUD RATE GENERATOR OUTPUT TIMING
BRGx + 1 * TCY TLW
THW
BCLKx
TBLD
TBHD
UxTX
FIGURE 32-19:
UARTx START BIT EDGE DETECTION
BRGx
Any Value
Start bit Detected, BRGx Started
TCY
Cycle
Clock
TSETUP
TSTDELAY
UxRX
DS30009996G-page 384
2010-2014 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-38: UARTx AC SPECIFICATIONS
Symbol
Characteristics
Min
Typ
Max
Units
TLW
BCLKx High Time
20
TCY/2
—
ns
THW
BCLKx Low Time
20
(TCY * BRGx) + TCY/2
—
ns
TBLD
BCLKx Falling Edge Delay from UxTX
-50
—
50
ns
TBHD
BCLKx Rising Edge Delay from UxTX
TCY/2 – 50
—
TCY/2 + 50
ns
TWAK
Min. Low on UxRX Line to Cause Wake-up
TCTS
Min. Low on UxCTS Line to Start
Transmission
TSETUP
Start bit Falling Edge to System Clock Rising
Edge Setup Time
TSTDELAY Maximum Delay in the Detection of the
Start bit Falling Edge
2010-2014 Microchip Technology Inc.
—
1
—
s
TCY
—
—
ns
3
—
—
ns
—
—
TCY + TSETUP
ns
DS30009996G-page 385
PIC24FJ128GA310 FAMILY
TABLE 32-39: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 2V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 2.2
—
Lesser of:
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
VSS – 0.3
—
VSS + 0.3
V
AD05
VREFH
Reference Voltage High
AVSS + 1.7
AVDD
V
AD06
VREFL
Reference Voltage Low
AD07
VREF
Absolute Reference
Voltage
Reference Inputs
—
AVSS
—
AVDD – 1.7
V
AVSS – 0.3
—
AVDD + 0.3
V
—
VREFH
V
Analog Input
AD10
VINH-VINL Full-Scale Input Span
AD11
VIN
Absolute Input Voltage
AVSS – 0.3
—
AVDD + 0.3
V
AD12
VINL
Absolute VINL Input
Voltage
AVSS – 0.3
—
AVDD/3
V
Leakage Current
—
±1.0
±610
nA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V,
Source Impedance = 2.5 k
Recommended Impedance
of Analog Voltage Source
—
—
2.5K
10-bit
AD13
AD17
RIN
VREFL
(Note 2)
ADC Accuracy
AD20B Nr
Resolution
—
12
—
bits
AD21B INL
Integral Nonlinearity
—
±1
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