SAM9X60
Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based
MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100
Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Introduction
The SAM9X60 is a high-performance, ultra-low power ARM926EJ-S CPU-based embedded microprocessor (MPU)
running up to 600 MHz, with support for multiple memories such as SDRAM, LP-SDRAM, LPDDR, DDR2, and QSPI
and e.MMC Flash. The device integrates powerful peripherals for connectivity and user interface applications, and
offers security functions (tamper detection, secure boot program, secure key storage, etc.), TRNG, as well as highperformance crypto accelerators for AES and SHA.
Features
•
•
•
•
CPU running up to 600 MHz
– ARM926EJ-S Arm Thumb® processor
– 32-Kbyte data cache, 32-Kbyte instruction cache, Memory Management Unit (MMU)
Memories
– One 160-Kbyte internal ROM
• 64-Kbyte internal ROM embedding a secure bootloader program supporting boot on Nand Flash,
SDCard, SPI or QSPI Flash. Bootloader features selectable by OTP bits
• 96-Kbyte ROM for NAND Flash BCH ECC table
– One 64-Kbyte internal SRAM (SRAM0), single-cycle access at system speed
– High-bandwidth Multi-port DDR2/LPDDR Controller
– 32/16-bit External Bus Interface (EBI) supporting 8/4-bank DDR2/LPDDR, 4/2-bank SDR/LPSDR, static
memories, with scrambling
– NAND Flash Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code
– One 11-Kbyte OTP memory for secure key storage with emulation mode (OTP bits are emulated by a 4Kbyte SRAM (SRAM1))
System Running up to 200 MHz
– Power-on reset cells, Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer
running on internal slow RC oscillator (32 kHz typical) and Real Time Clock running on slow crystal
oscillator (32.768 kHz)
– Two internal trimmed RC oscillators with typical values: 32 kHz (slow) and 12 MHz (fast)
– Two crystal oscillators: 32.768 kHz (slow) and 12 to 48 MHz (fast)
– One PLL for the system and one PLL optimized for USB high-speed operation (480 MHz)
– One dual-port 16-channel DMA Controller
– Advanced Interrupt Controller and Debug Unit
– JTAG port with disable bit in OTP memory
– Two programmable clock output signals
Low-power Modes
– Backup mode with RTC, eight 32-bit general purpose backup registers, and Shutdown Controller to control
the external power supply
– Clock Generator and Power Management Controller
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1
SAM9X60
•
•
•
•
•
•
– Software-programmable ultra-low power modes: Very Slow Clock operating mode (ULP0), and No-clock
operating Mode (ULP1) with fast wake-up capabilities
– Software programmable power optimization capabilities
Peripherals
– LCD Controller with overlay, alpha-blending, rotation, scaling and color conversion. Up to 1024 x 768
resolution
– 2D Graphics Controller supporting fill BLT, copy BLT, transparent BLT, blend/alpha BLT, ROP4 BLT (Raster
Operations) and command ring buffer
– ITU-R BT. 601/656, up to 12-bit Image Sensor Interface
– One USB Device High Speed, three USB Host High Speed with dedicated On-Chip Transceivers
– Two 10/100 Mbps Ethernet Mac Controller
– Two 4-bit Secure Digital MultiMedia Card Controller
– Two CAN Controllers
– One Quad I/O SPI Controller
– Two three-channel 32-bit Timers/Counters
– One high resolution (64-bit) Periodic Interval Timer
– One Synchronous Serial Controller
– One Inter-IC Sound Multi-Channel Controller with TDM support
– One Audio Class D Controller with single-ended or bridge-tied load connection to power stage
– One four-channel 16-bit PWM Controller
– Thirteen FLEXCOMs (USART, SPI and TWI)
– One 12-channel 12-bit Analog-to-Digital Converter with 4/5 wires resistive touchscreen support
Hardware Cryptography
– SHA (SHA1, SHA224, SHA256, SHA384, SHA512) and HMAC: compliant with FIPS PUB 180-2
– AES: 256-, 192-, 128-bit key algorithms, compliant with FIPS PUB 197
– TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3
– True Random Number Generator, compliant with NIST Special Publication 800-22 Test Suite and FIPS
PUBs 140-2 and 140-3
I/O Ports
– Four 32-bit Parallel Input/Output Controllers
– Up to 112 programmable I/O lines multiplexed with up to three peripheral I/Os
– Input change interrupt capability on each I/O line, optional Schmitt trigger input
– Individually programmable open-drain, pull-up and pull-down resistor, synchronous output
– General-purpose analog and digital inputs tolerant to positive and negative current injection
Package
– 228-ball TFBGA 11x11 mm², 0.65 mm pitch, optimized for standard class PCB layout (down to four layers)
Design for low ElectroMagnetic Interference (EMI)
– Slewrate-controlled I/Os
– DDR/SDR Phy with impedance-calibrated drivers
– Spread spectrum PLLs
– Careful BGA power/ground ball assignment to provide optimum decoupling capacitors placement
Operating Conditions
– Ambient temperature range (TA): -40°C to +105°C
– Junction temperature range (TJ): -40°C to +125°C
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 2
SAM9X60
Configuration Summary
1.
Configuration Summary
Table 1-1. Configuration Summary
Feature
SAM9X60
Package
BGA228, 11 x 11 mm², 0.65-mm pitch
Core
ARM926 @ 600MHz
SRAM0 + SRAM1
64 Kbytes + 4 Kbytes
L1 Cache (I + D)
32 Kbytes + 32 Kbytes
SDRAM Support
(LPSDR / SDR) 16/32-bit, (LPDDR / DDR2) 16-bit
External Bus I/F
Parallel Bus, NAND Flash
Camera I/F (ISI)
1x 12-bit
EMAC 10/100
1x MII / RMII + 1x RMII
USB
3x HS Tranceivers
2x Host + 1x (H or D)
CAN
2x
LCD / GFX2D
SDIO / SDCard / eMMC
ADC
Serial I/F
24-bit RGB
Up to 1024 x 768 @ 60 fps
2x (4-bit / up to 52 MHz)
1x 12-bit ADC
13x FLEXCOMs
DDR QSPI
1x
Audio Peripherals
SSC / I2S / CLASSD
Security
© 2020 Microchip Technology Inc.
1/1/1
TDES / AES / SHA + Secure Bootloader
Complete Datasheet
DS60001579C-page 3
SAM9X60
Block Diagram
Block Diagram
Figure 2-1. SAM9X60 Block Diagram
ARM926EJ-S
JTAG
Boundary
Scan
NTRST
EBI
In-Circuit Emulator
ICache
32 Kbytes
Key
DCache
32 Kbytes
MMU
SDRAMC
+
Bus Interface Unit
Digital
Analog
I
Memories
MPDDRC
D
(Dynamic Memory
Controller)
PIO
M
Backup Area
ROM
(96 Kbytes +
64 Kbytes)
OTP Memory
(11 Kbytes)
SRAM1
(4 Kbytes)
S
SRAM0
(64 Kbytes)
S
XDMA
M
M
M
S
S
S
SMC
(Static Memory
Controller)
S
PMECC
PMERRLOC
Private
Key
Bus
Peripheral
Bridge
M
M
S
USB HOST
HS EHCI
FS OHCI
PC
HS
Trans
HHSDPC
HHSDMC
HS
Trans
HHSDPB
HHSDMB
HS
Trans
DHSDP / HHSDPA
DHSDM / HHSDMA
PB
PA
RTUNE
CLASSD
I2SMCC_MCK, I2SMCC_ DOUT
I2SMCC_WS, I2SMCC_CK
I2SMCC_DIN
I2SMCC
TDES
M
M
TRNG
ISI
ISI_D[11:0]
ISI_PCK
ISI_HSYNC, ISI_VSYNC
ISI_MCK
LCDC
LCDDAT[23:0]
LCDVSYNC, LCDVSYNC
LCDPCLK, LCDEN
LCDDISP, LCDPWM
GFX2D
EMAC0
EMAC1
(RMII)
E1_REFCK, E1_RXER
E1_TXEN, E1_TX[1:0]
E1_CRSDV, E1_RX[1:0]
E1_MDIO
E1_MDC
SDMMC
(x2)
SDMMCx_CMD
SDMMCx_CK
SDMMCx_DAT[3:0]
PIO
M
FLEXCOM
FLEXCOMx_IO0..7
PWM
PWM0..3
ADVREFP, ADVREFN
12-bit
12-channel
ADC
PIO
AD0..11
ADTRG
Peripheral Bus 0
(USART/SPI/I2C)
0–3 & 6–10
(x9)
M
M
M
VDDIN33
CAN
(x2)
PMC
RTC /
RTT
VDDBU SHDWC
POR
Complete Datasheet
3
P1
–1
T
–1
U
PC
ST
R
_O
N
R
ST
N
P0
D
KU
VDDIN33
POR
PIO
Backup Area
SH
VDDCORE
POR
RSTC
KU
Main XTAL 32768 Hz
XTAL OSC
OSC
GPBR
(8x32)
K0
SLOW RC
OSC.
W
Main RC
OSC
N
© 2020 Microchip Technology Inc.
VDDOUT25
REG
Internal Wakeups
W
EX
T
EX _FI
T_ Q
IR
Q
TX
D D
R
XD
PIO
Clock
Sources
UPLL
U
T3
XI 2
N
32
AIC
PLLA
XO
DBGU
WDT
U
T
XI
N
64-bit Timer
QSCK
QCS
QIO0..3
System Clocks
Clock Generator
XO
PIT64B
QSPI
S
System Controller
PIO
A–D
E0_TXEN, E0_TXER
E0_TX[3:0], E0_MDC
E0_TXCK, E0_RXCK
E0_CRS, E0_COL, E0_RX[3:0]
E0_RXER, E0_RXDV
E0_MDIO
DMA
TC
32-bit Timer
(x6)
TIOAx, TIOBx
TCLKx
DMA
S
DMA
Peripheral
Bridge
CANTXx
CANRXx
System
Bus
Matrix M
HS USB
PIO
CLASSD_L0..3
SHA
M
DMA
SSC
Peripheral Bus 1
TF, TK
TD
RF, RK
RD
DMA
AES
DMA
(USART/SPI/I2C)
4–5 & 11–12
(x4)
DMA
FLEXCOM
FLEXCOMx_IO0..7
NWAIT
A[20:25]
D[16:31]
NCS2..5
NANDOE, NANDWE
NANDALE, NANDCLE
NANDCS
S
M
OTPC
DMA
M
S
Processor and
Crypto-accelerators
Matrix Master
Matrix Slave
DDR_VREF, DDR_CAL
D[15:0]
A0 / NBS0
A1 / NBS2 / NWR2 / DQM2
A[15:2], A19
A16 / BA0
A17 / BA1
A18 / BA2
NCS0
NCS1 / SDCS
NRD
NWR0 / NWE
NWR1 / NBS1
NWR3 / NBS3 / DQM3
SDCK, SDCKN, SDCKE
RAS, CAS
SDWE, SDA10
DQM0..1
DQS0..1
NDQS0..1
PIO
JTAGSEL
TMS, TCK
TDI
TDO, RTCK
D
2.
DS60001579C-page 4
SAM9X60
Signal Description
3.
Signal Description
The following table gives details on signal names classified by peripheral.
Table 3-1. Signal Description List
Signal Name
Function
Type
Comments
Active Level
Clocks, Oscillators and PLLs
XIN
Main Crystal Oscillator Input
Input
–
–
XOUT
Main Crystal Oscillator Output
Output
–
–
XIN32
32.768 kHz Crystal Oscillator Input
Input
–
–
XOUT32
32.768 kHz Crystal Oscillator Output
Output
–
–
RTUNE
USB External Resistor
Analog
–
–
PCK0..1
Programmable Clock Output
Output
–
–
Output
–
–
Input
–
–
Shutdown, Wakeup Logic
SHDN
Shutdown Control
WKUP0..13
Wake-Up Inputs
ICE and JTAG
TCK
Test Clock
Input
–
–
TDI
Test Data In
Input
–
–
TDO
Test Data Out
Output
–
–
TMS
Test Mode Select
Input
–
–
JTAGSEL
JTAG Selection
Input
–
–
RTCK
Return Test Clock
Output
–
Reset/Test
NRST
External nReset Input
NRST_OUT
Reset Controller Output
NTRST
Test Reset Signal
Input
–
Low
Output
–
Low
Input
–
Debug Unit - DBGU
DRXD
Debug Receive Data
Input
–
–
DTXD
Debug Transmit Data
Output
–
–
Advanced Interrupt Controller - AIC
EXT_IRQ
External Interrupt Input
Input
–
–
EXT_FIQ
Fast Interrupt Input
Input
–
–
PIO Controller - PIOA - PIOB - PIOC - PIOD
PA0..31
Parallel IO Controller A
I/O
–
–
PB0..25
Parallel IO Controller B
I/O
–
–
PC0..31
Parallel IO Controller C
I/O
–
–
PD0..21
Parallel IO Controller D
I/O
–
–
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 5
SAM9X60
Signal Description
...........continued
Signal Name
Function
Type
Comments
Active Level
External Bus Interface - EBI
D[15:0]
Data Bus
I/O
–
–
D[31:16]
Data Bus
I/O
–
–
A[25:0]
Address Bus
Output
–
–
NWAIT
External Wait Signal
Input
–
Low
Static Memory Controller - SMC
NCS0..5
Chip Select Lines
Output
–
Low
NWR0..3
Write Signal
Output
–
Low
NRD
Read Signal
Output
–
Low
NWE
Write Enable
Output
–
Low
NBS0..3
Byte Mask Signal
Output
–
Low
NAND Flash Controller
NANDCS
NAND Flash Chip Select
Output
–
Low
NANDOE
NAND Flash Output Enable
Output
–
Low
NANDWE
NAND Flash Write Enable
Output
–
Low
NANDALE
NAND Flash Address Latch Enable
Output
–
–
NANDCLE
NAND Flash Command Latch Enable
Output
–
–
–
–
DDR2 / SDRAM / LPDDR / LPSDR Controller
SDCK
DRAM Clock
Output
SDCKN
DRAM Clock bar (DDR2 / LPDDR only)
SDCKE
DRAM Clock Enable
Output
–
High
SDCS
DRAM Chip Select
Output
–
Low
BA0..2
Bank Select
Output
–
Low
SDWE
DRAM Write Enable
Output
–
Low
DDR_VREF
DDR2 I/O Reference Voltage
Input
–
–
DDR_CAL
LPDDR / DDR2 Calibration Input
Input
–
–
RAS - CAS
Row and Column Signal
Output
–
Low
SDA10
SDRAM Address 10 Line
Output
–
–
DQS0..1
Positive Data Strobe
I/O
–
–
NDSQ0..1
Negative Data Strobe
I/O
–
–
DQM0..3
Write Data Mask
Output
–
–
I/O
–
–
Output
–
–
I/O
–
–
–
Secure Data Memory Card - SDMMCx [0..1]
SDMMCx_CMD
SDCard / eMMC Command line
SDMMCx_CK
SDCard / eMMC Clock Signal
SDMMCx_DAT[3:0]
SDCard / eMMC Data Lines
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 6
SAM9X60
Signal Description
...........continued
Signal Name
Function
Type
Comments
Active Level
Flexible Serial Communication Controller - FLEXCOMx [0..12]
FLEXCOMx_IO0
TXD / MOSI / TWD
I/O
–
–
FLEXCOMx_IO1
RXD / MISO / TWCK
I/O
–
–
FLEXCOMx_IO2
SCK / SPCK / –
I/O
–
–
FLEXCOMx_IO3
CTS / NPCS0 or NSS / –
I/O
–
–
FLEXCOMx_IO4
RTS / NPCS1 / –
Output
–
–
FLEXCOMx_IO5
– / NPCS2 / –
Output
–
–
FLEXCOMx_IO6
– / NPCS3 / –
Output
–
–
FLEXCOMx_IO7
LONCOL / – / –
Input
–
–
Synchronous Serial Controller - SSC
TD
SSC Transmit Data
Output
–
–
RD
SSC Receive Data
Input
–
–
TK
SSC Transmit Clock
I/O
–
–
RK
SSC Receive Clock
I/O
–
–
TF
SSC Transmit Frame Sync
I/O
–
–
RF
SSC Receive Frame Sync
I/O
–
–
Image Sensor Interface - ISI
ISI_D[11:0]
Image Sensor Data
Input
–
–
ISI_MCK
Image sensor Reference Clock
output
–
–
ISI_HSYNC
Image Sensor Horizontal Synchro
input
–
–
ISI_VSYNC
Image Sensor Vertical Synchro
input
–
–
ISI_PCK
Image Sensor Data Clock
input
–
–
Input
–
–
Timer / Counter - TCx [0..5]
TCLKx
TC Channel x External Clock Input
TIOAx
TC Channel x I/O Line A
I/O
–
–
TIOBx
TC Channel x I/O Line B
I/O
–
–
–
–
Pulse Width Modulation Controller- PWMC
PWM0..3
Pulse Width Modulation Output
Output
USB Host High Speed Port - UHPHS
HHSDMA
USB Host Port A High Speed Data -
Analog
–
–
HHSDPA
USB Host Port A High Speed Data +
Analog
–
–
HHSDMB
USB Host Port B High Speed Data -
Analog
–
–
HHSDPB
USB Host Port B High Speed Data +
Analog
–
–
HHSDMC
USB Host Port C High Speed Data -
Analog
–
–
HHSDPC
USB Host Port C High Speed Data +
Analog
–
–
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 7
SAM9X60
Signal Description
...........continued
Signal Name
Function
Type
Comments
Active Level
USB Device High Speed Port - UDPHS
DHSDM
USB Device High Speed Data -
Analog
–
–
DHSDP
USB Device High Speed Data +
Analog
–
–
Ethernet 10/100 - EMAC0
E0_TXCK
Transmit Clock or Reference Clock
Input
–
–
E0_RXCK
Receive Clock
Input
–
–
E0_TXEN
Transmit Enable
Output
–
–
E0_TX[3:0]
Transmit Data
Output
–
–
E0_TXER
Transmit Coding Error
Output
–
–
E0_RXDV
Receive Data Valid
Input
–
–
E0_RX[3:0]
Receive Data
Input
–
–
E0_RXER
Receive Error
Input
–
–
E0_CRS
Carrier Sense and Data Valid
Input
–
–
E0_COL
Collision Detect
Input
–
–
E0_MDC
Management Data Clock
Output
–
–
E0_MDIO
Management Data Input/Output
I/O
–
–
Input
–
–
RMII Ethernet 10/100 - EMAC1
E1_REFCK
Transmit Clock or Reference Clock
E1_TXEN
Transmit Enable
Output
–
–
E1_TX[1:0]
Transmit Data
Output
–
–
E1_CRSDV
Receive Data Valid
Input
–
–
E1_RX[1:0]
Receive Data
Input
–
–
E1_RXER
Receive Error
Input
–
–
E1_MDC
Management Data Clock
Output
–
–
E1_MDIO
Management Data Input/Output
I/O
–
–
LCD Controller - LCDC
LCDDAT[23:0]
LCD Data Bus
Output
–
–
LCDVSYNC
LCD Vertical Synchronization
Output
–
–
LCDHSYNC
LCD Horizontal Synchronization
Output
–
–
LCDPCLK
LCD Pixel Clock
Output
–
–
LCDDEN
LCD Data Enable
Output
–
–
LCDPWM
LCD Contrast Control
Output
–
–
LCDDISP
LCD Display Enable
Output
–
–
12-bit Analog-to-Digital Converter with Resistive Touch - ADC
AD0XP_UL
Top/Upper Left Channel
© 2020 Microchip Technology Inc.
Analog
Complete Datasheet
–
–
DS60001579C-page 8
SAM9X60
Signal Description
...........continued
Signal Name
Function
Type
Comments
Active Level
AD1XM_UR
Bottom/Upper Right Channel
Analog
–
–
AD2YP_LL
Right/Lower Left Channel
Analog
–
–
AD3YM_SENSE
Left/Sense Channel
Analog
–
–
AD4LR
Lower Right Channel
Analog
–
–
AD5..11
7 Analog Inputs
Analog
–
–
ADTRG
ADC Trigger
Input
–
–
ADVREFN
ADC Negative Input Reference Voltage
Analog
–
–
ADVREFP
ADC Positive Input Reference Voltage
Analog
–
–
CAN Controller - CANx [0..1]
CANRXx
CAN Receive
Input
–
–
CANTXx
CAN Transmit
Output
–
–
Class D Controller - CLASSD
CLASSD_L0
Class D Controller Left Output 0
Output
CLASSD_L1
Class D Controller Left Output 1
Output
CLASSD_L2
Class D Controller Left Output 2
Output
CLASSD_L3
Class D Controller Left Output 3
Output
Quad I/O SPI - QSPI
QSCK
Quad IO SPI Serial Clock
Output
QCS
Quad IO SPI Chip Select
Output
QIO3..0
Quad IO SPI I/O 0 to 3
I/O
Inter IC Sound Multi Channel Controller - I2SMCC
I2SMCC_MCK
Master Clock
Output
I2SMCC_CK
Serial Clock
I/O
I2SMCC_WS
I2S Word Select
I/O
I2SMCC_DIN
Serial Data Input
Input
I2SMCC_DOUT
Serial Data Output
© 2020 Microchip Technology Inc.
Output
Complete Datasheet
DS60001579C-page 9
SAM9X60
Microchip Recommended Power Management Solutions
4.
Microchip Recommended Power Management Solutions
MCP16502 and MCP16501 are multi-channel Power Management Integrated Circuits (PMICs) recommended for the
SAM9X60.
4.1
MCP16502 PMIC
MCP16502 features four 1A DC-DC buck regulators and two 0.3A auxiliary LDO regulators, and provides a
comprehensive interface to the MPU, which includes an interrupt flag and a 1-MHz I²C interface.
The PMIC-processor interface is optimized so that it remains leakage-free in Backup mode. The following figure gives
an application schematic example of a SAM9X60 with DDR2-SDRAM system, powered by MCP16502AE. This
variant is specifically tailored for SAM9X60 systems with CPU frequency up to 600 MHz. The 3.3V, 1.8V and 1.15V
supply rails are fed from DC-DC converters for maximum efficiency. The fourth DC-DC converter (Buck4) of
MCP16502AE is left OFF by default during start-up and its components may be removed, if not needed for other
purposes.
The two LDO regulator outputs LOUT1 and LOUT2 are auxiliary power rails available for the application. LOUT1
output is ON by default at power-up and its default voltage is set to 1.8V, 2.5V or 3.3V depending on the SELV1 pin
connection. Buck4 and LOUT2, OFF by default at power-up, can be started by software through the I²C control bus to
the necessary voltage.
For further details, refer to the MCP16502 documentation on www.microchip.com.
Figure 4-1. MCP16502 Simplified Application Block Diagram
VIN : 5V TYP
VIN
VDDIOM
VDDNF
VDDQSPI
VDDIOP0
VDDIOP1
VOUT2
MEMORY
VOLTAGE
SELECTION
DDR2
VDDBU
VVDDBU
VDDANA
VDDIN33
VIN
17
PGND2
MCP16502AE
BACKUP SUPPLY
(BATTERY
or SUPERCAP)
SW2
OUT2
22
8
SHDN
23
SAM9X60
MPU
SELV2
VVDDBU
PVIN2
R3
R4
R5
WKUP0
NRST
GPIOx
7
PWRHLD
HPM
PGND1
SW1
OUT1
SGND
nSTRTO
nRSTO
1
5
TWD
TWCK
C2
22µF
VOUT2
1.8V
PVIN1
VOUT1
R2
L2
1.5-2.2µH
16
VIN
LPM
SVIN
R1
13
14
C6
4.7µF
LVIN
nINTO
LOUT1
SDA
LOUT2
12
11
C4
4.7µF
L1
1.5-2.2µH
C1
22µF
VOUT1
3.3V
9
VIN
4
C9
2.2µF
3
VIN
20
VLOUT1
1.8V
19
21
C12
4.7µF
SCL
C11
2.2µF4.7µF
C10
2.2µF4.7µF
VLOUT2
3.3V
nSTRT
SELVL1
18
VIN
VIN
26
VOUT3
1.15V
VDDCORE
C7
4.7µF
C3
22µF
L3
1.5-2.2µH
28
27
25
4.2
VLOUT1 LDO1
OUTPUT VOLTAGE
SELECTION
PVIN4
PGND4
SW4
OUT4
31
29
30
32
MCP16501 PMIC
MCP16501 is a 4-channel PMIC designed for PCB area constrained applications. In a 4x4mm QFN24 package, it
features three 1A DC-DC buck regulators and one 0.3A auxiliary LDO regulator, and provides a simple, leakage-free
interface with SAM9X60.
The following figure gives an application schematic example of SAM9X60 with DDR2-SDRAM system, powered by
MCP16501A. This variant is specifically tailored for SAM9X60 systems with CPU frequency up to 600 MHz. The
3.3V, 1.8V and 1.15V supply rails are fed from DC-DC converters for maximum efficiency. The LDO regulator output
LOUT is controlled with the LEN input and its output voltage is set with the resistive divider R3/R4.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 10
SAM9X60
Microchip Recommended Power Management Solutions
For further details, refer to the MCP16501 documentation on www.microchip.com.
Figure 4-2. MCP16501 Simplified Application Block Diagram
VIN :5V TYP
VIN
VIN
VOUT2
MEMORY
VOLTAGE
SELECTION
VDDNF
DDR2
4
VDDANA
VDDIN33
SELV2
PVIN2
PGND2
SW2
LPM
OUT2
9
8
C5
4.7µF
L2
1.5-2.2µH
6
VIN
PVIN1
3
SHDN
GPIOx
PWRHLD
LEN
SAM9X60
MPU
PGND1
SW1
OUT1
VOUT1
22
23
2
nRSTO
VVDDBU
16
C7
2.2µF
R1
WKUP0
VDDBU
5
VVDDBU
BACKUP SUPPLY
(BATTERY
or SUPERCAP)
nSTRTO
nSTRT
LFB
LOUT
VOUT3
CORE VOLTAGE
SELECTION
OPEN = 1.15V
SELV3
Complete Datasheet
C8
4.7µF
R4
18
PVIN3
15
R3
19
VLOUT
VIN
PGND3
VDDCORE
C1
22µF
VIN
VIN
SGND
C4
4.7µF
L1
1.5-2.2µH
1
MCP16501A
R2
NRST
© 2020 Microchip Technology Inc.
C2
22µF
SW3
10
11
C6
4.7µF
L3
1.5-2.2µH
Up to
300 mA
Load
C3
22µF
OUT3
DS60001579C-page 11
SAM9X60
Safety and Security Features
5.
Safety and Security Features
5.1
Design for Safety and IEC60730 Class B Certification
5.1.1
Background Information
The IEC 60730 standard encompasses all aspects of appliance design. Annex H of the standard covers the aspects
most relevant to microcontrollers. It details the tests and diagnostics which are intended to ensure safe operation of
embedded control hardware and software. IEC 60730 defines three classifications for electronic control functions:
•
•
•
Class A - Control functions which are not intended to be relied upon for safety of the equipment
Class B - Control functions intended to prevent unsafe operation of the controlled equipment
Class C - Control functions intended to prevent special hazards such as explosions
Specific design techniques have been used in the SAM9X60 to ease compliance with the IEC 60730 Class B
Certification and to resolve general-purpose safety concerns. This allows reduced software development and code
size as well as savings on external hardware circuitry, since built-in self-tests are already embedded in the MPU.
Table 5-1 gives the list of peripherals which incorporate these techniques, and details whether these features are
applicable for the IEC 60730 Class B Certification or for general-purpose safety considerations.
5.2
Design for Security
The SAM9X60 embeds peripherals with security features to prevent counterfeiting, to secure external
communication, and to authenticate the system.
Table 5-2 provides the list of peripherals and an overview of their security function. For more information, see the
sections on each peripheral.
5.3
Safety and IEC 60730 Features
Table 5-1. Safety and IEC 60730 Features
Peripheral
Component
Fault/Error/Feature
Requirements
for Class B
IEC 60730(1)
PMC
System Controller
© 2020 Microchip Technology Inc.
Clock
All
General
Safety
MCK frequency monitor
- MCK out-of-range operation
–
X
32.768 kHz crystal oscillator
frequency monitor
- Abnormal frequency deviation
X
X
Main crystal oscillator failure
detector
- Crystal failure detection
X
X
Safety critical peripherals and/or
counters are fed by the alwayson slow RC oscillator
- WDT, RSTC, startup counters,
timeout counters, etc.
–
X
Complete Datasheet
DS60001579C-page 12
SAM9X60
Safety and Security Features
...........continued
Peripheral
Component
Fault/Error/Feature
Requirements
for Class B
IEC 60730(1)
PIOC
I/O lines
ADCC
NAND Flash
Controller ECC
Memory
WDT,
RSTC
ARM926EJ-S MMU
Watchdog
General
Safety
Digital I/O
- Plausibility check
X
–
Analog I/O and ADC converter
- Plausibility check
X
–
Non-volatile memory
- Multiple error detection (2 to 24)
–
X
Watchdog is driven by an internal
always on clock
- Program counter stuck at faults
X
X
Watchdog configuration can be
locked until the next reset
- Errant writes (programming
errors, errors introduced by
system or hardware failures)
–
X
Watchdog overflow generates a
system reset
X
X
–
X
–
X
–
X
Memory Management ARM926EJ-S Memory
Unit
Management Unit
MATRIX, AIC, RTC,
RTT, RSTC, SHDWC,
SDRAM, PMC, PIOC,
MPDDRC, SMC,
CLASSD, SSC,
FLEXCOM, QSPI,
TC, I2SMCC, ADC
Peripherals
Configuration, Interrupt Enable/
Disable, Control registers can be
independently write-protected
- Errant writes (programming
errors, errors introduced by
system or hardware failures)
AES, TDES, SHA,
PIT64B, TC,
SDRAMC, MPDDRC
Peripherals
Embedded integrity checker with
reports in status registers
Note:
1. Class B IEC 60730 Requirements. Annex H - Table H.1 (H.11.12.7 in Edition 3).
5.4
Security Features
Table 5-2. Security Features
Peripheral
Function
ARM926EJ-S MMU
PIO
© 2020 Microchip Technology Inc.
Description
Comments
Memory Management
Unit
Memory Management Unit
–
I/O Control/ Peripheral
Access
When a peripheral is not
selected (PIO-controlled),
I/O lines have no access to the
peripheral.
–
Complete Datasheet
DS60001579C-page 13
SAM9X60
Safety and Security Features
...........continued
Peripheral
Function
Description
Hardware-accelerated AES up
to 256 bits
AES
SHA
TDES
Comments
SHA up to 512 and HMACSHA
Cryptography
Standards
Hardware-accelerated Triple
DES
FIPS-compliant
True Random Number
Generator
TRNG
Cryptography Tamper
Immediate clear of keys in
case of external tamper event
detection (if enabled)
AES, TDES, SHA
Cryptography Integrity
Checks
AES/TDES/SHA embed
integrity checks on
configuration registers and
algorithm circuitries and a
specific flag in status register. If
this specific flag is set, an
–
integrity error has been
detected. This can occur only
on abnormal operating
conditions (electromagnetic
attacks, VDD glitches, etc.)
OTPC, AES, TDES, TRNG
Cryptography Private
Key Bus
Capability to transfer a key to
AES/TDES in a totally invisible
manner from software
–
Secure Boot
Secure Boot
Code encrypted/decrypted,
Trusted Code Authentication
Hardware SHA (HMAC) +
Software RSA or AES
Hardware (CMAC)
Memories
Scrambling
On-the-fly scrambling/
unscrambling for memories
All external memories such
as QSPI, DDR, and all
memories on SMC
AES, TDES
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 14
SAM9X60
Safety and Security Features
...........continued
Peripheral
RTC
Function
Description
Comments
IO Tamper Pin
Eight tamper detection pins
VDDCORE WKUP1 to
WKUP8 pins can be
selected as a source of
tamper, performing an
immediate clear of AES/
TDES keys (if enabled),
immediate clear of
scrambling keys in
SDR/DDR/QSPI/SMC, and
immediate clear of General
Purposes Backup
Registers (if enabled)
Timestamping
Timestamping of tamper
events
All events are logged in the
RTC. Timestamping gives
the source of the reset/
erase memory/interruption
Protection against bad
configuration (invalid entry for
date and time are impossible)
–
Glitch on 32 KHz does not
corrupt the downstream
counters
Glitch on 32 KHz can only
create a phase shift of the
downstream counters
If RTC Status flag TDERR is
set, counters integrity have
been corrupted
–
Disable JTAG access by OTP
bit
–
Configuration
Glitch Robustness
Integrity Check
Secure OTP
PIT64B, TC
JTAG Access Control
Integrity Checks
Access Protection
GPBR can be write-protected
and/or read-protected
–
Tamper
GBPR can be immediately
cleared on tamper detection (if
enabled)
–
GPBR
© 2020 Microchip Technology Inc.
PIT64B/TC embed integrity
checks on configuration
registers and algorithm
circuitries and a specific flag in
status register. If this specific
–
flag is set, an integrity error has
been detected. This can occur
only on abnormal operating
conditions (electromagnetic
attacks, VDD glitches, etc.)
Complete Datasheet
DS60001579C-page 15
SAM9X60
Package and Pinout
6.
Package and Pinout
6.1
Packages
The SAM9X60 is available in the package indicated in the following table.
Table 6-1. SAM9X60 Package
Package Name
Pin Count
Ball Pitch
TFBGA228L
228
0.65 mm
For further details, refer to 59. Mechanical Characteristics.
6.2
Pinout
Figure 6-1. SAM9X60 BGA228 Pinout
PB10
PB13
PB7
PB20
PB21
PB24
D11
NWR1
A12
A6
A2
DDR
_VREF
PB16
GND
ANA
PB15
PB23
PB22
DDR
_CAL
D13
A0
A13
A4
GND
SD
CKN
VDD
ANA
ADV
REFN
PB19
VDD
QSPI
DQM1
D15
VDD
IOM
A10
CAS
VDD
IOM
ADV
REFP
PB11
D9
DQS1
D14
SDA10
A
GND
B
PB17
C
PB1
PB12
D
PB3
PB6
PB2
E
PB5
PB25
PB4
PB18
F
PA28
PB14
TDI
PB0
G
PA22
PA30
VDD
IOP0
H
PA25
PA27
PA29
J
PA18
PA20
PA17
K
PA14
PA16
VDD
IOP0
L
PA12
PA10
PA3
PA5
M
PA8
PA6
PA1
PC0
N
PA4
GND
VDD
IOP1
P
PA2
PA0
R
NRST
T
GND
1
PB9
A7
A14
A18
A9
A3
SDWE
A11
A16
RAS
NCS1
SD
CKE
A17
NCS0
A8
VDD
IOM
A15
A1
GND
NWR0
ND
QS1
GND
A5
TMS
VDD
CORE
PA26
PA24
D10
D12
VDD
CORE
NRD
GND
PA21
PA9
D8
DQM0
GND
PA31
TDO
PA15
PA11
GND
GND
D1
D3
DQS0
ND
QS0
A19
D2
D0
PA23
PA19
PA13
PC15
GND
GND
PD9
D5
PD7
D7
D4
PD13
D6
GND
PA7
PC17
PC23
PD11
GND
VDD
NF
PD8
PD6
PC4
VDD
CORE
PC13
PC19
PC25
PC29
VDD
IN33
PD14
PD18
NWR3
PD12
PD10
PC6
GND
PC21
PC27
GND
IN33
PD20
PC31
PD16
PC3
PD21
PC3
PD15
PC8
PC28
PD3
GND
PD17
PD2
PD19
PD5
HS
DMC
VDD
OUT25
RTU
NE
HS
DPC
VDD
IN33
XOUT
32
XIN
SHDN
HS
DMA
GND
IN33
PD0
PC26
XIN
32
XOUT
WK
UP0
HS
DPA
HS
DPB
HS
DMB
PD1
GND
8
9
10
11
12
13
14
15
16
PC11
PC1
PC3
PC10
VDD
BU
PC20
JTAG
SEL
TCK
PC5
PC12
PC16
PC22
PC24
RTCK
PC7
PC9
PC14
PC18
PC30
2
3
4
5
6
7
© 2020 Microchip Technology Inc.
GND
PB8
PC2
Power
SDCK
Ground
PD4
Analog Signals
Complete Datasheet
DS60001579C-page 16
© 2020 Microchip Technology Inc.
Table 6-2. Pin Description
Primary
228-pin
BGA
rotatethispage90
P2
Power
Rail
VDDIOP0
Alternate
Signal
GPIO
PA0
Dir
I/O
Signal
—
Dir
—
VDDIOP0
GPIO
PA1
I/O
—
—
P1
VDDIOP0
GPIO
PA2
I/O
WKUP1
—
Complete Datasheet
N1
VDDIOP0
VDDIOP0
GPIO
GPIO
PA3
PA4
I/O
I/O
—
—
—
—
L4
VDDIOP0
GPIO
PA5
I/O
—
—
M2
VDDIOP0
GPIO
PA6
I/O
—
—
K6
VDDIOP0
GPIO
PA7
I/O
—
—
VDDIOP0
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
A
FLEXCOM0_IO0
I/O
GPIO
PA8
I/O
—
—
VDDIOP0
GPIO
PA9
I/O
WKUP2
—
L2
VDDIOP0
GPIO
PA10
I/O
WKUP3
—
FLEXCOM5_IO4
O
FLEXCOM4_IO4
O
A
FLEXCOM0_IO1
I/O
B
FLEXCOM4_IO5
O
A
FLEXCOM0_IO4
O
B
SDMMC1_DAT1
I/O
C
E0_TX0
O
A
FLEXCOM0_IO3
I/O
B
SDMMC1_DAT2
I/O
C
E0_TX1
O
A
FLEXCOM0_IO2
I/O
B
SDMMC1_DAT3
I/O
C
E0_TXER
O
A
FLEXCOM1_IO0
I/O
B
CANTX1
O
A
FLEXCOM1_IO1
I/O
B
CANRX1
I
A
FLEXCOM2_IO0
I/O
B
FLEXCOM4_IO4
O
C
FLEXCOM5_IO4
O
A
FLEXCOM2_IO1
I/O
B
FLEXCOM5_IO3
I/O
C
FLEXCOM4_IO5
O
A
DRXD
I
B
CANRX0
I
A
DTXD
O
B
CANTX0
O
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAM9X60
G8
B
C
Package and Pinout
DS60001579C-page 17
M1
Reset State
I/O Type
M3
L3
PIO Peripheral
© 2020 Microchip Technology Inc.
...........continued
Primary
228-pin
BGA
Power
Rail
I/O Type
H7
VDDIOP0
L1
Alternate
Signal
Dir
Signal
Dir
GPIO
PA11
I/O
—
—
VDDIOP0
GPIO
PA12
I/O
—
—
J6
VDDIOP0
GPIO
PA13
I/O
—
—
rotatethispage90
PIO Peripheral
Reset State
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
A
FLEXCOM4_IO1
I/O
B
SDMMC1_DAT0
I/O
A
FLEXCOM4_IO0
I/O
B
SDMMC1_CMD
I/O
A
FLEXCOM4_IO2
I/O
B
SDMMC1_CK
I/O
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
Complete Datasheet
VDDIOP0
GPIO
PA14
I/O
—
—
A
FLEXCOM4_IO3
I/O
PIO, I, PU, ST
VDDIOP0
GPIO
PA15
I/O
—
—
A
SDMMC0_DAT0
I/O
PIO, I, PU, ST
K2
VDDIOP0
GPIO
PA16
I/O
—
—
A
SDMMC0_CMD
I/O
PIO, I, PU, ST
J3
VDDIOP0
GPIO
PA17
I/O
—
—
A
SDMMC0_CK
I/O
PIO, I, PU, ST
J1
VDDIOP0
GPIO
PA18
I/O
—
—
A
SDMMC0_DAT1
I/O
PIO, I, PU, ST
J5
VDDIOP0
GPIO
PA19
I/O
—
—
A
SDMMC0_DAT2
I/O
PIO, I, PU, ST
J2
VDDIOP0
GPIO
PA20
I/O
—
—
A
SDMMC0_DAT3
I/O
PIO, I, PU, ST
A
TIOA0
I/O
B
FLEXCOM5_IO1
I/O
A
TIOA1
I/O
B
FLEXCOM5_IO0
I/O
A
TIOA2
I/O
B
FLEXCOM5_IO2
I/O
A
TCLK0
I
B
TK
I/O
C
CLASSD_L0
O
A
TCLK1
I
B
TF
I/O
C
CLASSD_L1
O
A
TCLK2
I
B
TD
O
C
CLASSD_L2
O
G6
VDDIOP0
GPIO
PA21
I/O
—
—
G1
VDDIOP0
GPIO
PA22
I/O
—
—
J4
VDDIOP0
GPIO
PA23
I/O
—
—
F8
VDDIOP0
GPIO
PA24
I/O
—
—
H1
VDDIOP0
GPIO
GPIO
PA25
PA26
I/O
I/O
—
—
—
—
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAM9X60
F7
VDDIOP0
PIO, I, PU, ST
Package and Pinout
DS60001579C-page 18
K1
H6
© 2020 Microchip Technology Inc.
...........continued
Primary
228-pin
BGA
Power
Rail
I/O Type
H2
VDDIOP0
GPIO
rotatethispage90
Alternate
Signal
Dir
Signal
Dir
PA27
I/O
—
—
F1
VDDIOP0
GPIO
PA28
I/O
WKUP4
—
H3
VDDIOP0
GPIO
PA29
I/O
—
—
Complete Datasheet
G2
H4
VDDIOP0
VDDIOP0
GPIO
GPIO
PA30
PA31
I/O
I/O
—
—
—
—
GPIO
PB0
I/O
WKUP5
—
C1
VDDANA
GPIO
PB1
I/O
—
—
D3
VDDANA
GPIO
PB2
I/O
—
—
D1
VDDANA
GPIO
PB3
I/O
WKUP6
—
E3
VDDANA
GPIO
PB4
I/O
—
—
E1
VDDANA
GPIO
PB5
I/O
—
—
D2
VDDANA
GPIO
PB6
I/O
AD7
—
A5
VDDANA
GPIO
PB7
I/O
AD8
—
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
A
TIOB0
I/O
B
RD
I
C
CLASSD_L3
O
A
TIOB1
I/O
B
RK
I/O
A
TIOB2
I/O
B
RF
I/O
C
FLEXCOM2_IO7
I
A
FLEXCOM6_IO0
I/O
B
FLEXCOM5_IO6
O
C
E0_MDC
O
A
FLEXCOM6_IO1
I/O
B
FLEXCOM5_IO5
O
C
E0_TXEN
O
A
E0_RX0
I
B
FLEXCOM2_IO4
O
A
E0_RX1
I
B
FLEXCOM2_IO3
I/O
A
E0_RXER
I
B
FLEXCOM2_IO2
I/O
A
E0_RXDV
I
B
FLEXCOM4_IO6
O
A
E0_TXCK
I/O
B
FLEXCOM8_IO0
I/O
A
E0_MDIO
I/O
B
FLEXCOM8_IO1
I/O
A
E0_MDC
O
B
FLEXCOM0_IO7
I
A
E0_TXEN
O
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAM9X60
VDDANA
Reset State
Package and Pinout
DS60001579C-page 19
F4
PIO Peripheral
© 2020 Microchip Technology Inc.
...........continued
Primary
228-pin
BGA
Power
Rail
I/O Type
E6
VDDANA
GPIO
rotatethispage90
Alternate
PIO Peripheral
Reset State
Complete Datasheet
Signal
Dir
Signal
Dir
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
PB8
I/O
AD9
—
A
E0_TXER
O
PIO, I, PU, ST
A
E0_TX0
O
B
PCK1
O
A
E0_TX1
O
B
PCK0
O
A
E0_TX2
O
B
PWM0
O
A
E0_TX3
O
B
PWM1
O
A
E0_RX2
I
B
PWM2
O
A
E0_RX3
I
B
PWM3
O
A2
VDDANA
GPIO
PB9
I/O
AD10
—
A3
VDDANA
GPIO
PB10
I/O
AD11
—
D6
VDDANA
GPIO
PB11
I/O
AD0
—
C2
VDDANA
GPIO
PB12
I/O
AD1
—
A4
VDDANA
GPIO
PB13
I/O
AD2
—
F2
VDDANA
GPIO
PB14
I/O
AD3
—
B5
VDDANA
GPIO
PB15
I/O
AD4
—
A
E0_RXCK
I
PIO, I, PU, ST
B3
VDDANA
GPIO
PB16
I/O
AD5
—
A
E0_CRS
I
PIO, I, PU, ST
B1
VDDANA
GPIO
PB17
I/O
AD6
—
A
E0_COL
I
PIO, I, PU, ST
A
IRQ
I
B
ADTRG
I
E4
VDDANA
GPIO
PB18
I/O
WKUP7
—
C6
VDDQSPI
GPIO
PB19
I/O
—
—
VDDQSPI
GPIO
GPIO
PB20
PB21
I/O
I/O
—
—
—
—
O
I2SMCC_CK
I/O
C
FLEXCOM11_IO0
I/O
A
QCS
O
B
I2SMCC_WS
I/O
C
FLEXCOM11_IO1
I/O
A
QIO0
I/O
B
I2SMCC_DIN0
I
C
FLEXCOM12_IO0
I/O
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAM9X60
DS60001579C-page 20
A7
VDDQSPI
QSCK
B
PIO, I, PU, ST
Package and Pinout
A6
A
PIO, I, PU, ST
© 2020 Microchip Technology Inc.
...........continued
Primary
228-pin
BGA
Power
Rail
I/O Type
B7
VDDQSPI
GPIO
rotatethispage90
Alternate
Signal
Dir
Signal
Dir
PB22
I/O
—
—
B6
VDDQSPI
GPIO
PB23
I/O
—
—
A8
VDDQSPI
GPIO
PB24
I/O
—
—
Complete Datasheet
E2
VDDIOP0
GPIO
PB25
I/O
WKUP8
—
M4
VDDIOP1
GPIO
PC0
I/O
—
—
P4
N5
P5
M6
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
GPIO
GPIO
GPIO
GPIO
GPIO
PC1
PC2
PC3
PC4
PC5
PC6
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
—
—
—
—
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
A
QIO1
I/O
B
I2SMCC_DOUT0
O
C
FLEXCOM12_IO1
I/O
A
QIO2
I/O
B
I2SMCC_MCK
O
A
QIO3
I/O
PIO, I, PU, ST
A
NRST_OUT
O
B
NTRST
I
NRST_OUT, O,
PD
A
LCDDAT0
O
B
ISI_D0
I
C
FLEXCOM7_IO0
I/O
A
LCDDAT1
O
Func
B
ISI_D1
I
C
FLEXCOM7_IO1
I/O
A
LCDDAT2
O
B
ISI_D2
I
C
TIOA3
I/O
A
LCDDAT3
O
B
ISI_D3
I
C
TIOB3
I/O
A
LCDDAT4
O
B
ISI_D4
I
C
TCLK3
I
A
LCDDAT5
O
B
ISI_D5
I
C
TIOA4
I/O
A
LCDDAT6
O
B
ISI_D6
I
C
TIOB4
I/O
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAM9X60
DS60001579C-page 21
R4
VDDIOP1
GPIO
Reset State
Package and Pinout
L5
VDDIOP1
PIO Peripheral
© 2020 Microchip Technology Inc.
...........continued
Primary
228-pin
BGA
Power
Rail
I/O Type
T3
VDDIOP1
GPIO
rotatethispage90
N8
T4
Complete Datasheet
P6
N6
R5
L7
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Dir
Signal
Dir
PC7
I/O
—
—
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reset State
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
A
LCDDAT7
O
B
ISI_D7
I
C
TCLK4
I
A
LCDDAT8
O
B
ISI_D8
I
C
FLEXCOM9_IO0
I/O
A
LCDDAT9
O
B
ISI_D9
I
C
FLEXCOM9_IO1
I/O
A
LCDDAT10
O
B
ISI_D10
I
C
PWM0
O
A
LCDDAT11
O
B
ISI_D11
I
C
PWM1
O
A
LCDDAT12
O
B
ISI_PCK
I
C
TIOA5
I/O
A
LCDDAT13
O
B
ISI_VSYNC
I
C
TIOB5
I/O
A
LCDDAT14
O
B
ISI_HSYNC
I
C
TCLK5
I
A
LCDDAT15
O
B
ISI_MCK
O
C
PCK0
O
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAM9X60
DS60001579C-page 22
J7
VDDIOP1
GPIO
Signal
PIO Peripheral
Package and Pinout
T5
VDDIOP1
Alternate
© 2020 Microchip Technology Inc.
...........continued
Primary
228-pin
BGA
Power
Rail
I/O Type
R6
VDDIOP1
GPIO
rotatethispage90
K8
T6
Complete Datasheet
L8
P8
M8
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
GPIO
GPIO
GPIO
GPIO
GPIO
Alternate
Signal
Dir
Signal
Dir
PC16
I/O
—
—
PC17
PC18
PC19
PC20
PC21
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
—
—
GPIO
PC22
I/O
—
—
K9
VDDIOP1
GPIO
PC23
I/O
—
—
R8
VDDIOP1
GPIO
PC24
I/O
WKUP9
—
L9
VDDIOP1
GPIO
PC25
I/O
WKUP10
—
T8
VDDIOP1
GPIO
PC26
I/O
—
—
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
A
LCDDAT16
O
B
E1_RXER
I
C
FLEXCOM10_IO0
I/O
A
LCDDAT17
O
B
FLEXCOM1_IO7
I
C
FLEXCOM10_IO1
I/O
A
LCDDAT18
O
B
E1_TX0
O
C
PWM0
O
A
LCDDAT19
O
B
E1_TX1
O
C
PWM1
O
A
LCDDAT20
O
B
E1_RX0
I
C
PWM2
O
A
LCDDAT21
O
B
E1_RX1
I
C
PWM3
O
A
LCDDAT22
O
B
FLEXCOM3_IO0
I/O
A
LCDDAT23
O
B
FLEXCOM3_IO1
I/O
A
LCDDISP
O
B
FLEXCOM3_IO4
O
A
—
—
B
FLEXCOM3_IO3
I/O
A
LCDPWM
O
B
FLEXCOM3_IO2
I/O
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAM9X60
VDDIOP1
Reset State
Package and Pinout
DS60001579C-page 23
R7
PIO Peripheral
© 2020 Microchip Technology Inc.
...........continued
Primary
228-pin
BGA
Power
Rail
I/O Type
M9
VDDIOP1
GPIO
rotatethispage90
N9
L10
Complete Datasheet
T7
M13
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
GPIO
GPIO
GPIO
GPIO
Alternate
Signal
Dir
Signal
Dir
PC27
I/O
—
—
PC28
PC29
PC30
PC31
I/O
I/O
I/O
I/O
—
—
—
WKUP11
—
—
—
—
PIO Peripheral
Reset State
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
A
LCDVSYNC
O
B
E1_TXEN
O
C
FLEXCOM1_IO4
O
A
LCDHSYNC
O
B
E1_CRSDV
I
C
FLEXCOM1_IO3
I/O
A
LCDDEN
O
B
E1_TXCK
I/O
C
FLEXCOM1_IO2
I/O
A
LCDPCK
O
B
E1_MDC
O
C
FLEXCOM3_IO7
I
A
FIQ
I
B
E1_MDIO
I/O
C
PCK1
O
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
R14
VDDNF
GPIO
PD0
I/O
—
—
A
NANDOE
O
PIO, I, PU, ST
T15
VDDNF
GPIO
PD1
I/O
—
—
A
NANDWE
O
PIO, I, PU, ST
A21,O, PD, ST
GPIO
PD2
I/O
—
—
A
A21/NANDALE
O
VDDNF
GPIO
PD3
I/O
—
—
A
A22/NANDCLE
O
A22,O, PD
R16
VDDNF
GPIO
PD4
I/O
—
—
A
NCS3/NANDCS
O
PIO, I, PU, ST
N11
VDDNF
GPIO
PD5
I/O
—
—
A
NWAIT
I
PIO, I, PU, ST
K16
VDDNF
GPIO
PD6
I/O
—
—
A
D16
I/O
PIO, I, PU, ST
J12
VDDNF
GPIO
PD7
I/O
—
—
A
D17
I/O
PIO, I, PU, ST
K15
VDDNF
GPIO
PD8
I/O
—
—
A
D18
I/O
PIO, I, PU, ST
J10
VDDNF
GPIO
PD9
I/O
—
—
A
D19
I/O
PIO, I, PU, ST
L16
VDDNF
GPIO
PD10
I/O
—
—
A
D20
I/O
PIO, I, PU, ST
K11
VDDNF
GPIO
PD11
I/O
—
—
A
D21
I/O
PIO, I, PU, ST
L15
VDDNF
GPIO
PD12
I/O
—
—
A
D22
I/O
PIO, I, PU, ST
J15
VDDNF
GPIO
PD13
I/O
—
—
A
D23
I/O
PIO, I, PU, ST
SAM9X60
VDDNF
Package and Pinout
DS60001579C-page 24
P15
N14
© 2020 Microchip Technology Inc.
...........continued
Primary
228-pin
BGA
Power
Rail
I/O Type
L12
VDDNF
GPIO
rotatethispage90
Alternate
PIO Peripheral
Reset State
Complete Datasheet
Signal
Dir
Signal
Dir
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
PD14
I/O
—
—
A
D24
I/O
PIO, I, PU, ST
A
D25
I/O
B
A20
O
A
D26
I/O
B
A23
O
A
D27
I/O
B
A24
O
A
D28
I/O
B
A25
O
A
D29
I/O
B
NCS2
O
A
D30
I/O
B
NCS4
O
A
D31
I/O
B
NCS5
O
VDDNF
GPIO
PD15
I/O
—
—
A20, O, PD
M14
VDDNF
GPIO
PD16
I/O
—
—
N16
VDDNF
GPIO
PD17
I/O
WKUP12
—
L13
VDDNF
GPIO
PD18
I/O
WKUP13
—
P16
VDDNF
GPIO
PD19
I/O
—
—
M11
VDDNF
GPIO
PD20
I/O
—
—
M15
VDDNF
GPIO
PD21
I/O
—
—
H16
VDDIOM
DDRIO
D0
—
—
—
—
—
—
O, PD
H10
VDDIOM
DDRIO
D1
—
—
—
—
—
—
O, PD
H15
VDDIOM
DDRIO
D2
—
—
—
—
—
—
O, PD
H11
VDDIOM
DDRIO
D3
—
—
—
—
—
—
O, PD
J14
VDDIOM
DDRIO
D4
—
—
—
—
—
—
O, PD
J11
VDDIOM
DDRIO
D5
—
—
—
—
—
—
O, PD
J16
VDDIOM
DDRIO
D6
—
—
—
—
—
—
O, PD
J13
VDDIOM
DDRIO
D7
—
—
—
—
—
—
O, PD
G9
VDDIOM
DDRIO
D8
—
—
—
—
—
—
O, PD
D8
VDDIOM
DDRIO
D9
—
—
—
—
—
—
O, PD
F9
VDDIOM
DDRIO
D10
—
—
—
—
—
—
O, PD
A23, O, PD
A24, O, PD
A25, O, PD
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
VDDIOM
DDRIO
D11
—
—
—
—
—
—
O, PD
VDDIOM
DDRIO
D12
—
—
—
—
—
—
O, PD
B9
VDDIOM
DDRIO
D13
—
—
—
—
—
—
O, PD
SAM9X60
A9
F10
Package and Pinout
DS60001579C-page 25
M16
© 2020 Microchip Technology Inc.
...........continued
Primary
Alternate
PIO Peripheral
Reset State
Complete Datasheet
Signal
Dir
Signal
Dir
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
DDRIO
D14
—
—
—
—
—
—
O, PD
DDRIO
D15
—
—
—
—
—
—
O, PD
VDDIOM
DDRIO
A0
—
NBS0
—
—
—
—
O, PD
G16
VDDIOM
DDRIO
A1
—
NBS2/DQM2/NWR2
—
—
—
—
O, PD
A13
VDDIOM
DDRIO
A2
—
—
—
—
—
—
O, PD
D15
VDDIOM
DDRIO
A3
—
—
—
—
—
—
O, PD
B12
VDDIOM
DDRIO
A4
—
—
—
—
—
—
O, PD
E11
VDDIOM
DDRIO
A5
—
—
—
—
—
—
O, PD
A12
VDDIOM
DDRIO
A6
—
—
—
—
—
—
O, PD
B16
VDDIOM
DDRIO
A7
—
—
—
—
—
—
O, PD
F16
VDDIOM
DDRIO
A8
—
—
—
—
—
—
O, PD
D14
VDDIOM
DDRIO
A9
—
—
—
—
—
—
O, PD
228-pin
BGA
Power
Rail
I/O Type
D11
VDDIOM
C9
VDDIOM
B10
rotatethispage90
DDRIO
A10
—
—
—
—
—
—
O, PD
VDDIOM
DDRIO
A11
—
—
—
—
—
—
O, PD
A11
VDDIOM
DDRIO
A12
—
—
—
—
—
—
O, PD
B11
VDDIOM
DDRIO
A13
—
—
—
—
—
—
O, PD
C15
VDDIOM
DDRIO
A14
—
—
—
—
—
—
O, PD
G15
VDDIOM
DDRIO
A15
—
—
—
—
—
—
O, PD
E14
VDDIOM
DDRIO
A16
—
BA0
—
—
—
—
O, PD
F14
VDDIOM
DDRIO
A17
—
BA1
—
—
—
—
O, PD
C16
VDDIOM
DDRIO
A18
—
BA2
—
—
—
—
O, PD
H14
VDDIOM
DDRIO
A19
—
—
—
—
—
—
O, PD
F15
VDDIOM
DDRIO
NCS0
—
—
—
—
—
—
O, PU
E16
VDDIOM
DDRIO
NCS1
—
SDCS
—
—
—
—
O, PU
F12
VDDIOM
DDRIO
NRD
—
—
—
—
—
—
O, PU
E8
VDDIOM
DDRIO
NWR0
—
NWE
—
—
—
—
O, PU
A10
VDDIOM
DDRIO
NWR1
—
NBS1
—
—
—
—
O, PU
L14
VDDIOM
GPIO
NWR3
—
NBS3/DQM3
—
—
—
—
O, PU
A15
VDDIOM
DDRIO
SDCK
—
—
—
—
—
—
O, PD
SAM9X60
VDDIOM
Package and Pinout
DS60001579C-page 26
C11
E13
© 2020 Microchip Technology Inc.
...........continued
Primary
Alternate
PIO Peripheral
Reset State
Complete Datasheet
Signal
Dir
Signal
Dir
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
DDRIO
SDCKN
—
—
—
—
—
—
O, PU
DDRIO
SDCKE
—
—
—
—
—
—
O, PU
VDDIOM
DDRIO
RAS
—
—
—
—
—
—
O, PU
C12
VDDIOM
DDRIO
CAS
—
—
—
—
—
—
O, PU
D16
VDDIOM
DDRIO
SDWE
—
—
—
—
—
—
O, PU
D12
VDDIOM
DDRIO
SDA10
—
—
—
—
—
—
O, PU
G11
VDDIOM
DDRIO
DQM0
—
—
—
—
—
—
O, PU
C8
VDDIOM
DDRIO
DQM1
—
—
—
—
—
—
O, PU
H12
VDDIOM
DDRIO
DQS0
—
—
—
—
—
—
O, PD
H13
VDDIOM
DDRIO
NDQS0
—
—
—
—
—
—
O, PU
D9
VDDIOM
DDRIO
DQS1
—
—
—
—
—
—
O, PD
E9
VDDIOM
DDRIO
NDQS1
—
—
—
—
—
—
O, PU
228-pin
BGA
Power
Rail
I/O Type
B14
VDDIOM
F13
VDDIOM
E15
rotatethispage90
B8
VDDIOM
—
DDR_CAL
I/O
—
—
—
—
—
I
A14
VDDIOM
—
DDR_VREF
I/O
—
—
—
—
—
I
D5
VDDANA
—
ADVREFP
I
—
—
—
—
—
I
C5
VDDANA
—
ADVREFN
I
—
—
—
—
—
I
P11
VDDIN33
—
RTUNE
I/O
—
—
—
—
—
I
T12
VDDIN33
—
HHSDPA
I/O
DHSDP
—
—
—
—
O, PD
R12
VDDIN33
—
HHSDMA
I/O
DHSDM
—
—
—
—
O, PD
T13
VDDIN33
—
HHSDPB
I/O
—
—
—
—
—
O, PD
T14
VDDIN33
—
HHSDMB
I/O
—
—
—
—
—
O, PD
—
HHSDPC
I/O
—
—
—
—
—
O, PD
VDDIN33
—
HHSDMC
I/O
—
—
—
—
—
O, PD
T11
VDDBU
—
WKUP0
I
—
—
—
—
—
I, ST
R11
VDDBU
—
SHDN
O
—
—
—
—
—
O, PD
P9
VDDBU
—
JTAGSEL
I
—
—
—
—
—
I, PD
R3
VDDIOP0
—
TCK
I
—
—
—
—
—
I, ST
F3
VDDIOP0
—
TDI
I
—
—
—
—
—
I, ST
H5
VDDIOP0
—
TDO
O
—
—
—
—
—
O
SAM9X60
VDDIN33
Package and Pinout
DS60001579C-page 27
P12
N12
© 2020 Microchip Technology Inc.
...........continued
Primary
PIO Peripheral
Reset State
Dir
Signal
Dir
Func
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST,
SEC,
FILTER
TMS
I
—
—
—
—
—
I, ST
RTCK
O
—
—
—
—
—
O
I
—
—
—
—
—
I, PU, ST
228-pin
BGA
Power
Rail
I/O Type
F5
VDDIOP0
—
T2
VDDIOP0
—
R1
VDDIOP0
—
NRST
rotatethispage90
Alternate
Signal
Complete Datasheet
T9
VDDBU
—
XIN32
I
—
—
—
—
—
I
R9
VDDBU
—
XOUT32
I/O
—
—
—
—
—
O
R10
VDDIN33
—
XIN
I
—
—
—
—
—
I
T10
VDDIN33
—
XOUT
I/O
—
—
—
—
—
O
C10, C13, G14
VDDIOM
power
—
—
—
—
—
—
—
—
A1, A16, B13,
E7, E10, G5,
G12, H8, H9,
J8, J9, K5,
K12, M7, N2,
N15, T1, T16
GND
ground
—
—
—
—
—
—
—
—
K14
VDDNF
power
—
—
—
—
—
—
—
—
G3, K3
VDDIOP0
power
—
—
—
—
—
—
—
—
N3
VDDIOP1
power
—
—
—
—
—
—
—
—
P7
VDDBU
power
—
—
—
—
—
—
—
—
C4
VDDANA
power
—
—
—
—
—
—
—
—
B4
GNDANA
ground
—
—
—
—
—
—
—
—
P10
VDDOUT25
output
—
—
—
—
—
—
—
—
L11, P13
VDDIN33
power
—
—
—
—
—
—
—
—
GNDIN33
ground
—
—
—
—
—
—
—
—
VDDCORE
power
—
—
—
—
—
—
—
—
C7
VDDQSPI
power
—
—
—
—
—
—
—
—
SAM9X60
Package and Pinout
DS60001579C-page 28
M10, R13
F6, F11, L6
SAM9X60
Memories
7.
Memories
Figure 7-1. Memory Mapping
0x00000000
Address memory space
Internal memories
0x10000000
0x00300000
0x20000000
0x00400000
0x00500000
EBI Chip Select 1
MPDDRC
SDRAMC
0x00600000
0x00700000
EBI Chip Select 2
0x40000000
0x00800000
0xF0000000
0x50000000
0xF0004000
EBI Chip Select 4
0xF0008000
0x60000000
0xF000C000
EBI Chip Select 5
0xF0010000
0x70000000
0xF0014000
QSPI MEM
0xF0018000
0x80000000
0xF001C000
SDMMC0
12
0x90000000
0xF0024000
SDMMC1
26
0xA0000000
0xF0020000
Undefined (Abort)
0xF0028000
0xF002C000
0xF0030000
0xEFF00000
0xF0034000
OTPC
46
0xEFF01000
Undefined (Abort)
0xF0000000
0xF0038000
0xF003C000
0xF0040000
Internal peripherals
0xF8000000
0xF8004000
0xFFFFFFFF
0xFFFFC000
Boot Memory
ECC ROM
0xFFFFE600
SRAM0
0xF8008000
SRAM1
+0x40
UDPHS (DMA)
+0x80
UHPHS_OHCI
0xF800C000
UHPHS_EHCI
Undefined (Abort)
+0x40
+0x80
Internal peripherals
FLEXCOM5
XDMAC
QSPI
GFX2D
I2SMCC
FLEXCOM11
FLEXCOM12
PIT64B
SHA
TRNG
AES
TDES
CLASSD
13
14
20
CAN1
TC0
TC0
28
35
36
34
32
33
37
41
38
39
40
42
TC4
TC1
FLEXCOM7
FLEXCOM8
0xF801C000
FLEXCOM0
FLEXCOM1
0xF8024000
FLEXCOM2
0xF8028000
FLEXCOM3
0xF802C000
EMAC0
0xF8030000
EMAC1
0xF8034000
PWM
0xF8038000
LCDC
0xF803C000
UDPHS
0xF8040000
FLEXCOM9
0xF8044000
FLEXCOM10
0xF8048000
ISI
0xF804C000
ADC
0xF8050000
30
0xFFFFEA00
45
0xFFFFEC00
MPDDRC
SMC
SDRAMC
AIC
0xFFFFF800
11
0xFFFFFA00
5
0xFFFFFC00
6
0xFFFFFE00
7
+0x10
8
+0x20
24
+0x40
27
+0x50
18
+0x54
25
+0x60
23
+0xa8
15
+0xc8
16
+0x180
0;31
DBGU
0xFFFFF400
10
49
reserved
0xFFFFF200
0xFFFFF600
48
PMERRLOC
0xFFFFF100
9
21
PMECC
0xFFFFEE00
TC5
FLEXCOM6
0xF8018000
17
TC2
TC3
0xF8014000
0xFFFFC000
TC1
TC1
PIOA
47
2
PIOB
3
PIOC
4
PIOD
44
PMC
SYSC
RSTC
SYSC
SHDWC
SYSC
RTT
SYSC
PIT
SYSC
SCKC
SYSC
BSC
SYSC
GPBR
SYSC
RTC
SYSC
SYSCWP
SYSC
WDT
43
1
1
1
1
1
1
1
(1)
1
1
1
19
SFR
0xF8054000
29
MATRIX
0xFFFFE800
TC0
TC1
0xF8020000
reserved
CAN0
TC0
0xF8010000
reserved
SSC
reserved
0xFFFFE000
Undefined (Abort)
FLEXCOM4
System controller
0xFFFFDE00
0x0FFFFFFF
EBI Chip Select 3
NANDFlash
offset
0x00100000
0x00200000
EBI Chip Select 0
0x30000000
Internal memories
0x00000000
reserved
System controller
0xFFFFFFFF
block
peripheral
ID
(+ : wired-or)
(1) Refer to the table System Controller Peripheral Mapping in section 13. System Controller Write Protection
(SYSCWP) for RTC detailed mapping.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 29
SAM9X60
Memories
7.1
Embedded Memories
7.1.1
Internal SRAM
The SAM9X60 embeds 68 Kbytes of high-speed SRAM, SRAM0. SRAM0 is always accessible at address
0x0030 0000. After remap, SRAM0 is also available at address 0x0000 0000. A 4-Kbyte SRAM memory, SRAM1, is
used for OTP emulation and is always accessible at address 0x0040 0000.
7.1.2
Internal ROM
The ROM contains a bootloader program mapped at address 0 after reset and the BCH (Bose, Chaudhuri and
Hocquenghem) code table mapped at address 0x0010_0000 for NAND Flash ECC correction.
7.1.3
Boot Strategies
For standard boot strategies, refer to 12. Boot Strategies.
For secure boot strategies, refer to the document “SAM9X60 Secure Boot Strategy”, document no. DS00003195
(Non-Disclosure Agreement required).
7.2
External Memory
The SAM9X60 offers connections to a wide range of external memories or to parallel peripherals.
7.2.1
External Bus Interface
The External Bus Interface (EBI) is an interface that features:
•
•
•
•
Four external memory controllers:
– a Static Memory Controller (SMC),
– a NAND Flash Controller (NFC)
– a Multi-Port DDR-SDRAM Controller (MPDDRC) to drive DDR2 and LPDDR
– SDRAM controller to drive SDRAM and LPSDR devices
8-, 16-, or 32-bit data bus
Up to 26-bit address bus
Up to six chip selects with configurable assignment:
– Static Memory Controller on NCS0, NCS1, NCS2, NCS3, NCS4, NCS5
– MPDDRC/SDRAMC (SDCS) or Static Memory Controller on NCS1
– Optional NAND Flash support on NCS3
The drive levels are configured in the EBI I/O Drive Configuration register (SFR_CCFG_EBICSA.EBI_DRIVE) in
section 24. Special Function Registers (SFR). At reset, the selected drive is low. The user must make sure to
program the correct drive. Refer to 58. Electrical Characteristics.
7.2.2
Supported Memories on MPDDRC/SDRAMC Interface
The MPDDRC and SDRAMC support the following memories:
•
•
•
7.2.3
4/2-bank SDR-SDRAM and LPSDR-SDRAM with 16 or 32-bit data path
8/4-bank DDR2-SDRAM and 4/2-bank LPDDR1-SDRAM with 16-bit data path
2K, 4K, 8K, 16K row address memory parts
Supported Memories on Static Memories and NAND Flash Interfaces
The SMC supports:
•
•
Asynchronous SRAM-like memories and parallel peripherals
8-, 16- or 32-bit data bus
The NFC supports:
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 30
SAM9X60
Memories
•
•
8-bit NAND Flash (SLC)
Programmable Multi-bit Error Correcting Code (PMECC) based on BCH codes
7.2.4
DDR/SDR I/O Calibration and DDR Voltage Reference
7.2.4.1
DDR/SDR I/O Calibration
The DDR/SDR I/Os embed an automatic impedance matching control to avoid overshoots and reach the best
performance levels depending on the bus load and external memories. A serial termination connection scheme,
where the driver has an output impedance matched to the characteristic impedance of the line, is used to improve
signal quality and reduce EMI.
One specific analog input, DDR_CAL, is used to calibrate all DDR/SDR I/Os.
The MPDDRC and SDRAMC support the ZQ calibration procedure used to calibrate the SAM9X60 DDR/SDR I/O
drive strength and the commands to set up the external memory device drive strength (refer to 32. AHB Multiport
DDR-SDRAM Controller (MPDDRC)). The calibration cell supports all the supported memory types. Calibration is
performed in the initialization phase only.
Figure 7-2. DDR Calibration Cell
CAL_CTRL
DDR_CAL
CALCODEN/CALCODEP
Calibration Cell
RZQ
MPDDRC
CZQ
cal_nmos
cal_pmos
drive
DDR I/O
PCB Trace
DDR
Memory
DDR I/O
PCB Trace
The calibration cell provides an input pin, DDR_CAL, loaded with one of the following resistor RZQ values:
•
•
•
•
20 KΩ for LPDDR
20 KΩ for DDR2
16.9 KΩ for SDRAM
20 KΩ for LPSDRAM
The typical value for CZQ is 22 pF.
7.2.4.2
DDR_VREF Recommended Circuits
The DDR_VREF pin serves as a voltage reference input for the DDR I/Os when DDR2 or LPDDR external SDRAM
memories are used. This pin is not used with SDR or LPSDR SDRAM memories, and must therefore be connected to
ground.
The following figures give the recommended schematics for each case: DDR2, LPDDR and SDR/LPSDR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 31
SAM9X60
Memories
Figure 7-3. DDR_VREF Recommended Schematic with DDR2-SDRAM
VDD (1.8V)
VDDIOM
DDR_VREF
4.7k
1%
100n
4.7k
1%
100n
VREF VDDx
DDR I/O
PCB Trace
DDR2SDRAM
MPDDRC
DDR I/O
PCB Trace
Figure 7-4. DDR_VREF Recommended Schematic with LPDDR-SDRAM
VDD (1.8V)
VDDIOM
DDR_VREF
10k
1%
100n
10k
1%
100n
VDDx
DDR I/O
PCB Trace
LPDDRSDRAM
MPDDRC
DDR I/O
© 2020 Microchip Technology Inc.
PCB Trace
Complete Datasheet
DS60001579C-page 32
SAM9X60
Memories
Figure 7-5. DDR_VREF Recommended Schematic with (LP)SDR-SDRAM
VDDIOM
VDD (1.8V or 3.3V)
DDR_VREF
VDDx
DDR I/O
PCB Trace
(SDR- /
LPSDR- )
SDRAM
SDRAMC
DDR I/O
© 2020 Microchip Technology Inc.
PCB Trace
Complete Datasheet
DS60001579C-page 33
SAM9X60
System Controller
8.
System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system, such as power,
resets, clocks, time, interrupts, watchdog, etc.
The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address space, between
addresses 0xFFFF_C000 and 0xFFFF_FFFF.
The following figure shows the System Controller block diagram.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 34
SAM9X60
System Controller
Figure 8-1. System Controller Block Diagram
System Controller
VDDCORE Power Domain
nirq
ext_irq
ext_fiq
periph_irq[i]
pit_irq
rtc_irq
wdt_irq
rtt_irq
pmc_irq
rstc_irq
MCK
periph_nreset
dbgu_rxd
nfiq
Advanced
Interrupt
Controller
MD_SLCK
debug
idle
proc_nreset
Watchdog
Timer
wdt_irq
por_ntrst
jtag_nreset
Reset
Controller
CPU_CLK
dbgu_txd
pit_irq
debug
jtag_nreset
periph_nreset
rstc_irq
periph_nreset
proc_nreset
backup_nreset
UHP48M
Bus Matrix
UPLLCK
UHP12M
MD_SLCK
USB High Speed
Host Port
periph_nreset
periph_irq[22]
8x 32-bit GPBR
WKUP1..8
Tamper detection
MD_SLCK
SHDN
WKUP0
Boundary Scan
TAP Controller
MCK
wdt_fault (WDRPROC)
VDDBU Power Domain
vddin33_nreset
VDDBU
POR
dbgu_irq
Periodic
Interval
Timer
nrst_out
VDDCORE
POR
ARM926EJ-S
proc_nreset
Debug
Unit
MCK
debug
periph_nreset
NRST
PB25
por_ntrst
AIC_int
Shutdown
Controller
backup_nreset
rtc_alarm
rtt_alarm
Boot
Sequence
Controller
UPLLCK
USB High Speed
Device Port
periph_nreset
backup_nreset
Slow RC
Oscillator
XIN32
XOUT32
32.768kHz
Crystal
Oscillator
TD_SLCK
SCKCR
VDDOUT25
Power Domain
Main RC
Oscillator
XIN
XOUT
MD_SLCK
rtt_irq
Real-Time
Clock
rtc_irq
periph_irq[23]
rtt_alarm
rtc_alarm
MD_SLCK
AIC_int
MAINRC_CK
Main
Crystal
Oscillator
MAINCK
PLLA
PLLACK
UPLL
UPLLCK
WKUP1..13
Real-Time
Timer
Wake_on_LAN 0&1
rtt_alarm
rtc_alarm
USB_resume
Power
Management
Controller
WKUP1..13
WKUP14/15
periph_clk[i]
Wake-up
events
periph_nreset
periph_nreset
periph_clk[i]
dbgu_rxd
PA0-PA31
PB0-PB25
PC0-PC31
PD0-PD21
periph_clk[i]
pck[0-1]
UHP48M
UHP12M
PCK
MCK
DDR_2x_MCK
QSPI_2x_MCK
pmc_irq
idle
PIO
Controllers
periph_irq
ext_irq
ext_fiq
dbgu_txd
Embedded
Peripherals
periph_irq[i]
in
out
enable
vddin33_nreset
VDDIN33
VDDOUT25
VDDOUT25
Regulator
© 2020 Microchip Technology Inc.
VDDIN33
POR
OTP
Controller
MAINRC_CK
Complete Datasheet
DS60001579C-page 35
SAM9X60
System Controller
8.1
Power-On Reset
The SAM9X60 embeds three Power-On Resets (PORs) cells on VDDBU, VDDCORE and VDDIN33. Refer to 58.
Electrical Characteristics for associated thresholds and timing information.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 36
SAM9X60
Peripherals
9.
Peripherals
9.1
Peripheral Mapping
As shown in Figure 7-1, the peripherals are mapped in the upper 256 Mbytes of the address space, between
addresses 0xF000 0000 and 0xFFFC 0000.
9.2
Peripheral Identifiers
Table 9-1. Peripheral Identifiers
Instance ID Instance Name
Internal
Interrupt
External
Interrupt
PMC
Clock
Control
Generic
Clock
fGCLK
(Max)
PLLACLK UPLLCLK Instance Description
0
AIC
–
EXT_FIQ
–
–
–
–
–
1
SYSC
X
–
–
–
–
–
–
2
PIOA
X
–
X
–
–
–
–
3
PIOB
X
–
X
–
–
–
–
4
PIOC
X
–
X
–
–
–
–
5
6
7
8
9
10
11
FLEXCOM0
FLEXCOM1
FLEXCOM2
FLEXCOM3
FLEXCOM6
FLEXCOM7
FLEXCOM8
X
X
X
X
X
X
X
–
–
–
–
–
–
–
X
X
X
X
X
X
X
X
X
X
X
X
X
X
fMCK/ 3
fMCK/ 3
fMCK/ 3
fMCK/ 3
fMCK/ 3
fMCK/ 3
fMCK/ 3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
12
SDMMC0
X
–
X
X
105 MHz
X
X
13
14
15
16
17
FLEXCOM4
FLEXCOM5
FLEXCOM9
FLEXCOM10
TC0
X
X
X
X
X
–
–
–
–
–
X
X
X
X
X
X
X
X
X
X
fMCK/ 3
fMCK/ 3
fMCK/ 3
fMCK/ 3
fMCK/ 3
X
X
X
X
X
X
X
X
X
X
18
PWM
X
–
X
–
–
–
–
19
ADC
X
–
X
X
fMCK/ 3
X
X
20
XDMAC
X
–
X
–
–
–
–
21
22
MATRIX
UHPHS
X
X
–
–
–
X
–
–
–
–
–
–
–
–
23
UDPHS
X
–
X
–
–
–
–
24
EMAC0
X
–
X
–
–
–
–
© 2020 Microchip Technology Inc.
Complete Datasheet
Advanced Interrupt
Controller
Logical-OR interrupt of
SYSC, PMC, WDT,
PIT, RSTC, RTT, RTC
Parallel I/O Controller
A
Parallel I/O Controller
B
Parallel I/O Controller
C
FLEXCOM 0
FLEXCOM 1
FLEXCOM 2
FLEXCOM 3
FLEXCOM 6
FLEXCOM 7
FLEXCOM 8
Secure Data Memory
Card Controller 0
FLEXCOM 4
FLEXCOM 5
FLEXCOM 9
FLEXCOM 10
Timer Counters 0,1,2
Pulse Width
Modulation Controller
ADC Controller
Extended DMA
Controller
Matrix
USB Host High Speed
USB Device High
Speed
Ethernet MAC 0
DS60001579C-page 37
SAM9X60
Peripherals
...........continued
25
LCDC
X
–
PMC
Clock
Control
X
26
SDMMC1
X
–
X
X
105 MHz
X
X
27
EMAC1
X
–
X
–
–
–
–
28
SSC
X
–
X
–
–
–
–
29
30
CAN0
CAN1
–
–
X
X
–
–
–
–
–
–
–
–
31
AIC
X
X
–
–
–
–
–
32
33
FLEXCOM11
FLEXCOM12
X
X
–
–
X
X
X
X
fMCK/ 3
fMCK/ 3
X
X
X
X
34
I2SMCC
X
–
X
X
105 MHz
X
X
35
QSPI
X
–
X
–
–
–
–
36
37
GFX2D
PIT64B
X
X
–
–
X
X
–
X
–
fMCK/ 3
–
X
–
X
38
TRNG
X
–
X
–
–
–
–
39
AES
X
–
X
–
–
–
–
40
TDES
X
–
X
–
–
–
–
41
SHA
X
–
X
–
–
–
–
42
CLASSD
X
–
X
X
100 MHz
X
X
43
ISI
X
–
X
–
–
–
–
44
PIOD
X
–
X
–
–
–
–
45
46
47
TC1
OTPC
DBGU
X
X
X
–
–
–
X
–
X
X
–
X
fMCK/ 3
–
fMCK/ 3
X
–
X
X
–
X
48
PMECC
X
–
–
–
–
–
–
49
SDRAMC/
MPDDRC
X
–
X
–
–
–
–
50
UTMI
–
–
–
–
–
–
–
Instance ID Instance Name
Internal
Interrupt
External
Interrupt
© 2020 Microchip Technology Inc.
EXT_IRQ
Generic
Clock
fGCLK
(Max)
X
140 MHz
X
X
Complete Datasheet
PLLACLK UPLLCLK Instance Description
LCD Controller
Secure Data Memory
Card Controller 1
Ethernet MAC 1
Synchronous Serial
Controller
CAN Controller 0
CAN Controller 1
Advanced Interrupt
Controller
FLEXCOM 11
FLEXCOM 12
I2S Multi Channel
Controller
Quad I/O SPI
Controller
2D Graphics Controller
64-bit Timer
True Random Number
Generator
Advanced Encryption
Standard
Triple Data Encryption
Standard
Secure Hash
Algorithm
CLASS D Controller
Image Sensor
Interface
Parallel I/O Controller
D
Timer Counter 3, 4, 5
OTP Controller
Debug Unit
logical-OR interrupt of
PMECC and
PMERRLOC
logical-OR interrupt of
SDRAMC, MPDDRC
and HSMC
UTMI Controller
DS60001579C-page 38
SAM9X60
Peripherals
9.3
FLEXCOM Features
Table 9-2. FLEXCOM Features
Functions and Features
FLEXCOM Instance
0
1
2
3
4
5
6
7
8
9
10
11
12
TWI Function
X
X
X
X
X
X
X
X
X
X
X
X
X
Normal/fast (400 kbit/s) / FM+ (1 Mbit/s)
X
X
X
X
X
X
X
X
X
X
X
X
X
Alternate command
X
X
X
X
X
X
X
X
X
X
X
X
X
Three-slave ADDR
X
X
X
X
X
X
X
X
X
X
X
X
X
High speed (3.4 Mbit/s)
X
X
X
X
X
X
X
X
X
X
X
X
X
Sniffer
X
X
X
X
X
X
X
X
X
X
X
X
X
TWI FIFO size
16 bytes
UART / USART Function
X
X
X
X
X
X
X
X
X
X
X
X
X
Two-wire UART
X
X
X
X
X
X
X
X
X
X
X
X
X
Five-wire USART
X
X
X
X
X
X
–
–
–
–
–
–
–
Hardware handshaking/RS485
X
X
X
X
X
X
–
–
–
–
–
–
–
ISO7816
X
X
X
X
X
X
–
–
–
–
–
–
–
IrDA
X
X
X
X
X
X
–
–
–
–
–
–
–
LIN
X
X
X
X
X
X
–
–
–
–
–
–
–
LON
X
X
X
X
–
–
–
–
–
–
–
–
–
Manchester
X
X
X
X
X
X
–
–
–
–
–
–
–
USART FIFO Size
16 bytes
SPI Function
X
X
X
X
X
X
–
–
–
–
–
–
–
1CS
X
X
X
X
X
X
–
–
–
–
–
–
–
4CS
–
–
–
–
X
X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SPI FIFO size
9.4
16 bytes
Peripheral Signal Multiplexing on I/O Lines
The SAM9X60 features several PIO controllers that multiplex the I/O lines of the peripheral set.
Table 6-2 defines how the I/O lines are multiplexed on the different PIO Controllers.
The column “Reset State” shows whether the PIO line resets in I/O mode or in Peripheral mode. If I/O is shown, the
PIO line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset
is released. As a result, the bit corresponding to the PIO line in register PIO_CFGR (PIO Configuration Register)
resets low.
If a signal name is shown in the “Reset State” column, the PIO line is assigned to this function and the corresponding
bit in PIO_CFGR resets high. That is the case for pins controlling memories, in particular address lines, which require
the pin to be driven as soon as the reset is released.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
ARM926EJ-S Processor
10.
ARM926EJ-S Processor
The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The
ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full
memory management, high performance, low die size and low power are important features.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade
off between high performance and high code density. It also supports the 8-bit Java instruction set and includes
features for efficient execution of Java bytecode, providing a Java performance similar to JITs (Just-In-Time
compilers), for the next generation of Java-powered wireless and embedded devices. It includes an enhanced
multiplier design for improved DSP performance.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and
software debug.
The ARM926EJ-S provides a complete high performance processor subsystem, including:
• an ARM9EJ-S™ integer core,
• a Memory Management Unit (MMU),
• separate instruction and data AMBA AHB bus interfaces,
• a 32-Kbyte L1 instruction cache and a 32-Kbyte data cache.
For information on the ARM926EJ-S processor, refer to ARM926EJ-S™ Technical Reference Manual on
www.arm.com.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Debug and Test
11.
Debug and Test
11.1
Description
The product features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit
Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through
programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It
manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug
Communication Channel.
A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test
environment.
11.2
Embedded Characteristics
•
•
•
ARM926 Real-time In-circuit Emulator
– Two real-time watchpoint units
– Two independent registers: Debug Control register and Debug Status register
– Test access port accessible through JTAG protocol
– Debug communications channel
Debug Unit
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID register
®
IEEE 1149.1 JTAG Boundary-scan on All Digital Pins
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Complete Datasheet
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SAM9X60
Debug and Test
11.3
Block Diagram
Figure 11-1. Debug and Test Block Diagram
TMS
TCK
PIO
TDI
ICE/JTAG
TAP
Boundary
Port
NTRST (PB25.B)
JTAGSEL
TDO
RTCK
VDDCORE
POR
Reset
ARM9EJ-S
ICE-RT
DMA
DBGU
PIO
ARM926EJ-S
DTXD
DRXD
TAP: Test Access Port
11.4
11.4.1
Application Examples
Debug Environment
The following figure shows a complete debug environment example. The ICE/JTAG interface is used for standard
debugging functions, such as downloading code and single-stepping through the program. A software debugger
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Complete Datasheet
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SAM9X60
Debug and Test
running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/
JTAG interface.
Figure 11-2. Application Debug and Trace Environment Example
Host Debugger
ICE/JTAG
Interface
ICE/JTAG
Connector
SAM9
RS232
Connector
Terminal
SAM9-based Application Board
11.4.2
Test Environment
The following figure shows a test environment example. Test vectors are sent and interpreted by the tester. In this
example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be
connected to form a single scan chain.
Figure 11-3. Application Test Environment Example
Test Adaptor
Tester
JTAG
Interface
ICE/JTAG
Connector
SAM9
Chip n
Chip 2
Chip 1
SAM9-based Application Board In Test
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SAM9X60
Debug and Test
11.5
Debug and Test Pin Description
Table 11-1. Debug and Test Pin List
Pin Name
Function
Type
Active Level
Input
Low
Reset/Test
NRST
Microcontroller Reset
ICE and JTAG
NTRST
Test Reset Signal
Input
Low
TCK
Test Clock
Input
–
TDI
Test Data In
Input
–
TDO
Test Data Out
Output
–
TMS
Test Mode Select
Input
–
RTCK
Returned Test Clock
Output
–
JTAGSEL
JTAG Selection
Input
–
Debug Unit
DRXD
Debug Receive Data
Input
–
DTXD
Debug Transmit Data
Output
–
11.6
Functional Description
11.6.1
EmbeddedICE™
The Arm 9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an
ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The
internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially
inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a storemultiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers.
This data can be serially shifted out without affecting the rest of the system.
There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of
the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port.
EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG
operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the EmbeddedICE-RT, refer to the Arm document ARM9EJ-S Technical Reference Manual
(DDI 0222A).
11.6.2
JTAG Signal Description
TMS is the Test Mode Select input which controls the transitions of the test interface state machine.
TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction
Register, or other data registers).
TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment
controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and
propagates them to the next chip in the serial test circuit.
NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in Arm cores and used to reset
the debug logic. On Microchip ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on
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SAM9X60
Debug and Test
power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK
periods.
TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and
not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S
cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from
the 32.768 kHz slow clock.
RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators.
From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care
about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in
JTAG ICE Mode and not in boundary scan mode.
11.6.3
Debug Unit
The Debug Unit manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and
that trace the activity of the Debug Communication Channel. The Debug Unit allows blockage of access to the
system through the ICE interface.
For further details on the Debug Unit, refer to 22. Debug Unit (DBGU).
11.6.4
IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS
functions are implemented. In ICE debug mode, the Arm processor responds with a non-JTAG chip ID that identifies
the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL
is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
© 2020 Microchip Technology Inc.
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SAM9X60
Debug and Test
11.6.5
JTAG ID Code Register
Access: Read-only
Bit
31
30
29
28
27
VERSION
Bit
23
22
26
25
24
PART NUMBER
21
20
19
18
17
16
11
10
9
8
PART NUMBER
Bit
15
14
13
12
PART NUMBER
Bit
7
6
MANUFACTURER IDENTITY
5
4
3
2
1
MANUFACTURER IDENTITY
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
Product part number is 0x5B2F
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
Bit[0] required by IEEE Std. 1149.1.
Set to 0x1.
JTAG ID Code value is 0x05B2_F03F.
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0
SAM9X60
Boot Strategies
12.
Boot Strategies
12.1
Description
The system always boots from the ROM memory at address 0x0.
The ROM code is a boot program contained in the embedded ROM. It is also called “Boot loader”.
By default, the chip starts in a Standard Boot mode. To know how the Secure Boot mode can be enabled, refer to the
document “SAM9X60 Secure Boot Strategy”, document no. DS00003195. To obtain this application note and
additional information about the secure boot and related tools, contact a Microchip sales representative.
Note: JTAG access is disabled during execution of the ROM code sequence. It is re-enabled when jumping into
SRAM when a valid code has been found on an external Non-Volatile Memory (NVM) at the same time the ROM
memory is hidden. If no valid boot has been found on an external NVM, the ROM code enables the USB connection
®
and one UART serial port, starts the standard SAM-BA monitor, locks access to the ROM memory and re-enables
the JTAG connection.
12.2
Flow Diagram
The following figure shows the ROM code global flow.
Figure 12-1. ROM Code Flow Diagram
Chip Setup
OTPC UID invalid
or
corruption error found
in OTPC_SR
Yes
while(1)
No
Valid boot code
found in one
NVM
Yes
Copy boot code and
run it in internal SRAM
No
Monitor disabled
Yes
while(1)
No
SAM-BA Monitor
© 2020 Microchip Technology Inc.
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SAM9X60
Boot Strategies
12.3
Chip Setup
When the chip is powered on, the processor clock (CPU_CLK) and the master clock (MCK) source is the Main clock
(MAINCK).
The ROM code performs a low-level initialization that follows the steps described below:
1.
2.
PLLA initialized at a frequency of 396 MHz.
Master clock selection: when the PLLA is stabilized, the master clock source is switched from the main clock
to the PLLA clock. The PMC Status Register is polled to wait for MCK Ready. Now, the CPU_CLK frequency is
the same as the PLLA clock, whereas the MCK frequency is the quarter of the PLLA clock.
For clock frequencies, see Table 12-4.
Note: No external crystal or clock is needed during the external boot memories sequence. An external clock source
is checked before the launch of the SAM-BA monitor to get a more accurate clock signal for USB.
12.4
Boot Configuration
The boot sequence is controlled using Boot Configuration Packet, stored in the OTP area and configured through the
OTP Controller (OTPC).
12.4.1
Default Boot Sequence (Without Boot Configuration Packet)
When no Boot Configuration Packet is available in the OTP area, the ROM code uses an internal default Boot
Configuration Packet to configure the DBGU as a console and tries to boot from one of the following memories:
•
•
•
•
•
SDMMC0 IOSET0
SDMMC1 IOSET0
QSPI0 IOSET0
SPI0 IOSET0
NAND0 IOSET0
Refer to Table 12-5 for further details.
If no bootable file is found in these memories, the ROM code goes to the monitor.
12.4.2
Using Boot Configuration Packet
The boot configuration data are stored in the Boot Configuration Packet in the OTP area. These data can be used for
various boot sequence customizations:
•
•
•
•
Set the IO pin configuration where the external memories used to boot are connected (see 12.4.8 Hardware
and Software Constraints for a description of the IO).
Enable the boot from selected memories.
Configure the UART port used as a console.
Enable/disable JTAG used for debug.
See 12.4.4 Boot Configuration User Interface for a detailed description of all the fields in these data.
By default, the values of the Boot Configuration Packet are 0x0. During prototyping phases, those values can be
overridden by the content of the emulation memory through OTPC Emulation mode. To enable this feature, the bit
BSCR_CR.EMUL_EN must be set.
The current running mode of the User area can be observed by reading BSCR_CR.EMUL_EN. If this bit is set, the
Emulation mode is enabled, otherwise, the Emulation mode is disabled.
After a reset, the ROM code reads the Boot Configuration Packet from the SRAM dedicated to Emulation mode if the
bit BSCR_CR.EMUL_EN is set to 1. Otherwise the packet is read from the OTP matrix.
Using Emulated OTP enables the user to test several boot configuration options, including Secure Boot mode,
without programming the OTP.
Note: If Emulation mode is enabled, the emulation SRAM is not backed up. After a power off/on, the configuration
and content are lost.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Boot Strategies
Figure 12-2. Boot Configuration Loading
Read BSC_CR
No
EMUL_EN bit set
Boot sequence uses
OTPC Boot configuration
Yes
Boot sequence uses Emulated
OTPC Boot configuration
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Boot Strategies
12.4.3
Boot Sequence Controller Configuration Register
Name:
BSC_CR
Address: 0xFFFFFE54
Bit
31
30
29
28
27
26
25
24
19
18
17
16
WPKEY[15:8]
Access
Reset
Bit
23
22
21
20
WPKEY[7:0]
Access
Reset
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EMUL_EN
Access
Reset
Bit
Access
Reset
Bits 31:16 – WPKEY[15:0] Write Protect Key
Value
Name
Description
0x6683
PASSWD Writing any other value in this field aborts the write operation of the BOOT field. Always
reads as 0.
Bit 0 – EMUL_EN Emulation Enable
Value
Description
0
Emulation mode is disabled.
1
The OTP user area is emulated in internal SRAM1.
12.4.4
Boot Configuration User Interface
Table 12-1. Boot Configuration Packet Mapping
Offset
Name
Description
0x00
MON_DIS
Disables monitor
0x04
ZERO
Must be filled with zero
0x08
RESERVED
Reserved
0x0C
JTAG_DIS
Disables JTAG
0x10
CONSOLE_PIN
Console pin muxing
MEM_CFGx[2]
Two 32-bit words used to set memory configurations for
x=0..6
MEM_CFGx[0]: this word contains mandatory options
for all connected memories.
0x14-0x48
MEM_CFGx[1]: this word contains mandatory options
for specific memories.
© 2020 Microchip Technology Inc.
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SAM9X60
Boot Strategies
12.4.4.1 Monitor Disable
Name:
Bit
MON_DIS
31
30
29
28
27
DISABLE_MONITOR[31:24]
26
25
24
23
22
21
20
19
DISABLE_MONITOR[23:16]
18
17
16
15
14
13
12
11
DISABLE_MONITOR[15:8]
10
9
8
7
6
5
4
3
DISABLE_MONITOR[7:0]
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:0 – DISABLE_MONITOR[31:0] SAM-BA Monitor Disable
Value
Description
0
If no boot file is found, launches the SAM-BA monitor.
Non-Zero
The SAM-BA monitor is never launched.
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SAM9X60
Boot Strategies
12.4.4.2 Boot Configuration Word Disable JTAG
Name:
Bit
JTAG_DIS
31
30
29
28
27
DISABLE_JTAG[31:24]
26
25
24
23
22
21
20
19
DISABLE_JTAG[23:16]
18
17
16
15
14
13
12
11
DISABLE_JTAG[15:8]
10
9
8
7
6
5
4
3
DISABLE_JTAG[7:0]
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:0 – DISABLE_JTAG[31:0] JTAG Disable
Value
Description
0
Enables JTAG.
Non-Zero
Disables JTAG.
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SAM9X60
Boot Strategies
12.4.4.3 Console Pin Muxing
Name:
WARNING
Bit
CONSOLE_PIN
To avoid any malfunctioning, the user must not write the "DO NOT USE (DNU)" bits.
31
DNU
30
DNU
29
DNU
28
DNU
27
DNU
26
DNU
25
DNU
24
DNU
23
DNU
22
DNU
21
DNU
20
DNU
19
DNU
18
DNU
17
DNU
16
DNU
15
DNU
14
DNU
13
DNU
12
DNU
11
DNU
10
DNU
9
DNU
8
DNU
7
DNU
6
DNU
5
DNU
4
DNU
3
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
2
1
CONSOLE_IOSET[3:0]
0
Access
Reset
Bits 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DNU DO
NOT USE
Bits 3:0 – CONSOLE_IOSET[3:0] Selects the pins and UART interface used as a console terminal
Value
Name
Description
0
DBGU
Uses DBGU
1
UART0
Uses FLEXCOM0 UART pins
2
UART1
Uses FLEXCOM1 UART pins
3
UART2
Uses FLEXCOM2 UART pins
4
UART3
Uses FLEXCOM3 UART pins
5
UART4
Uses FLEXCOM4 UART pins
6
UART5
Uses FLEXCOM5 UART pins
7
UART6
Uses FLEXCOM6 UART pins
8
UART7
Uses FLEXCOM7 UART pins
9
UART8
Uses FLEXCOM8 UART pins
10
UART9
Uses FLEXCOM9 UART pins
11
UART10
Uses FLEXCOM10 UART pins
12
UART11
Uses FLEXCOM11 UART pins
13
UART12
Uses FLEXCOM12 UART pins
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SAM9X60
Boot Strategies
12.4.4.4 QSPI Memory Configuration Data (First Word)
Name:
WARNING
Bit
MEM_CFGx[0]
To avoid any malfunctioning, the user must not write the "DO NOT USE (DNU)" bits.
31
DNU
30
DNU
29
DNU
28
DNU
27
DNU
26
DNU
25
DNU
24
DNU
23
DNU
22
DNU
21
DNU
20
DNU
19
DNU
18
DNU
17
DNU
16
DNU
15
DNU
14
DNU
13
DNU
12
DNU
11
10
9
IFACE_TYPE[3:0]
8
4
3
2
1
IFACE_IOSET[3:0]
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
5
INSTANCE_ID[3:0]
Access
Reset
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DNU DO NOT USE
Bits 11:8 – IFACE_TYPE[3:0] Interface Type
Value
Description
0
Interface is disabled
1
QSPI interface
Bits 7:4 – INSTANCE_ID[3:0] IP Instance ID
Value
Description
0
IP instance 0, QSPI
Bits 3:0 – IFACE_IOSET[3:0] Memory IOSET
Value
Description
0
PIO set 1, QSPI
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SAM9X60
Boot Strategies
12.4.4.5 QSPI Memory Configuration Data (Second Word)
Name:
Bit
MEM_CFGx[1]
31
30
29
28
27
XIP_ENABLE[31:24]
26
25
24
23
22
21
20
19
XIP_ENABLE[23:16]
18
17
16
15
14
13
12
11
XIP_ENABLE[15:8]
10
9
8
7
6
5
4
3
XIP_ENABLE[7:0]
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:0 – XIP_ENABLE[31:0] XIP Mode Enable
Value
Description
0
XIP mode disabled
Non-Zero
XIP mode enabled
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SAM9X60
Boot Strategies
12.4.4.6 SDMMC Memory Configuration Data (First Word)
Name:
WARNING
Bit
MEM_CFGx[0]
To avoid any malfunctioning, the user must not write the "DO NOT USE (DNU)" bits.
31
DNU
30
DNU
29
DNU
28
DNU
27
DNU
26
DNU
25
DNU
24
DNU
23
DNU
22
DNU
21
DNU
20
DNU
19
DNU
18
DNU
17
DNU
16
DNU
15
DNU
14
DNU
13
DNU
12
DNU
11
10
9
IFACE_TYPE[3:0]
8
4
3
2
1
IFACE_IOSET[3:0]
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
5
INSTANCE_ID[3:0]
Access
Reset
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DNU DO NOT USE
Bits 11:8 – IFACE_TYPE[3:0] Interface Type
Value
Description
0
Interface is disabled
3
SDMMC interface
Bits 7:4 – INSTANCE_ID[3:0] IP Instance ID
Value
Description
0
IP instance 0, SDMMC
1
IP instance 1, SDMMC
Bits 3:0 – IFACE_IOSET[3:0] Memory IOSET
Value
Description
0
PIO set 1, SDMMC
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SAM9X60
Boot Strategies
12.4.4.7 SDMMC Memory Configuration Data (Second Word)
Name:
WARNING
Bit
MEM_CFGx[1]
To avoid any malfunctioning, the user must not write the "DO NOT USE (DNU)" bits.
31
DNU
30
DNU
29
DNU
28
DNU
27
DNU
26
DNU
25
DNU
24
DNU
23
DNU
22
DNU
21
DNU
20
DNU
19
DNU
18
DNU
17
DNU
16
DNU
15
14
13
12
11
10
9
8
3
2
PIN[4:0]
1
0
Access
Reset
Bit
Access
Reset
Bit
WPKEY[7:0]
Access
Reset
Bit
7
ENABLE
6
5
4
PID[1:0]
Access
Reset
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DNU DO NOT USE
Bits 15:8 – WPKEY[7:0] Write Protect Key
Value
Name
Description
0x96
PASSWD
If any other value is written in this field, all the other bit values are ignored.
Bit 7 – ENABLE Card Detect Enable
Value
Description
0
Card detect disable, the ROM code does not use any card detect pin and directly tries to boot from the
memory connected to the SDMMC controller.
1
Card detect enable, the ROM code checks the level of the card detect pin. If the level is 0, the ROM
code tries to boot from the memory connected to the SDMMC controller. If the level is 1, the ROM code
skips the SDMMC controller and jumps to the next interface in the boot sequence.
Bits 6:5 – PID[1:0] Peripheral ID
The peripheral ID of the PIO controller managing the card detect pin.
Value
Description
0
PIOA
1
PIOB
2
PIOC
3
PIOD
Bits 4:0 – PIN[4:0] Card Detect Pin Index
The index of the card detect pin inside the PIO controller.
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12.4.4.8 FLEXCOM SPI Memory Configuration Data (First Word)
Name:
WARNING
Bit
MEM_CFGx[0]
To avoid any malfunctioning, the user must not write the "DO NOT USE (DNU)" bits.
31
DNU
30
DNU
29
DNU
28
DNU
27
DNU
26
DNU
25
DNU
24
DNU
23
DNU
22
DNU
21
DNU
20
DNU
19
DNU
18
DNU
17
DNU
16
DNU
15
DNU
14
DNU
13
DNU
12
DNU
11
10
9
IFACE_TYPE[3:0]
8
4
3
2
1
IFACE_IOSET[3:0]
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
5
INSTANCE_ID[3:0]
Access
Reset
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DNU DO NOT USE
Bits 11:8 – IFACE_TYPE[3:0] Interface Type
Value
Description
0
Interface is disabled
2
FLEXCOM SPI interface
Bits 7:4 – INSTANCE_ID[3:0] IP Instance ID
Value
Description
0
IP instance 0, FLEXCOM SPI
1
IP instance 1, FLEXCOM SPI
2
IP instance 2, FLEXCOM SPI
3
IP instance 3, FLEXCOM SPI
4
IP instance 4, FLEXCOM SPI
5
IP instance 5, FLEXCOM SPI
Bits 3:0 – IFACE_IOSET[3:0] Memory IOSET
Value
Description
0
PIO set 1, all FLEXCOM SPIs
1
PIO set 2, all FLEXCOM SPIs
2
PIO set 3, only for FLEXCOM4_SPI and FLEXCOM5_SPI
3
PIO set 4, only for FLEXCOM4_SPI and FLEXCOM5_SPI
4
PIO set 5, only for FLEXCOM4_SPI and FLEXCOM5_SPI
5
PIO set 6, only for FLEXCOM4_SPI
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12.4.4.9 FLEXCOM SPI Memory Configuration Data (Second Word)
Name:
WARNING
Bit
MEM_CFGx[1]
To avoid any malfunctioning, the user must not write the "DO NOT USE (DNU)" bits.
31
DNU
30
DNU
29
DNU
28
DNU
27
DNU
26
DNU
25
DNU
24
DNU
23
DNU
22
DNU
21
DNU
20
DNU
19
DNU
18
DNU
17
DNU
16
DNU
15
DNU
14
DNU
13
DNU
12
DNU
11
DNU
10
DNU
9
DNU
8
DNU
7
DNU
6
DNU
5
DNU
4
DNU
3
DNU
2
DNU
1
DNU
0
DNU
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 –
DNU DO NOT USE
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12.4.4.10 NAND Memory Configuration Data (First Word)
Name:
WARNING
Bit
MEM_CFGx[0]
To avoid any malfunctioning, the user must not write the "DO NOT USE (DNU)" bits.
31
DNU
30
DNU
29
DNU
28
DNU
27
DNU
26
DNU
25
DNU
24
DNU
23
DNU
22
DNU
21
DNU
20
DNU
19
DNU
18
DNU
17
DNU
16
DNU
15
DNU
14
DNU
13
DNU
12
DNU
11
10
9
IFACE_TYPE[3:0]
8
4
3
2
1
IFACE_IOSET[3:0]
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
5
INSTANCE_ID[3:0]
Access
Reset
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DNU DO NOT USE
Bits 11:8 – IFACE_TYPE[3:0] Interface Type
Value
Description
0
Interface is disabled
4
NAND interface
Bits 7:4 – INSTANCE_ID[3:0] IP Instance ID
Value
Description
0
IP instance 0, NAND
Bits 3:0 – IFACE_IOSET[3:0] Memory IOSET
Value
Description
0
PIO set 1, NAND
1
PIO set 2, NAND
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12.4.4.11 NAND Memory Configuration Data (Second Word)
Name:
WARNING
Bit
MEM_CFGx[1]
To avoid any malfunctioning, the user must not write the "DO NOT USE (DNU)" bits.
31
DNU
30
DNU
29
DNU
28
DNU
27
DNU
26
DNU
25
DNU
24
DNU
23
DNU
22
DNU
21
DNU
20
DNU
19
DNU
18
DNU
17
DNU
16
DNU
15
DNU
14
DNU
13
DNU
12
DNU
11
DNU
10
DNU
9
DNU
8
DNU
7
DNU
6
DNU
5
DNU
4
DNU
3
DNU
2
DNU
1
DNU
0
DNU
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 –
DNU DO NOT USE
12.4.5
NVM Boot Sequence
The ROM code performs the initialization and valid code detection for external memories as described below when
the memory interface boot is enabled in the Boot Configuration packet.
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Figure 12-3. NVM Bootloader Program
Device
Setup
No
Next interface valid
Yes
Detect valid code
in NVM
No
Yes
Copy code from
NVM to SRAM0
Run
Yes
Monitor disabled
while(1)
No
SAM-BA
Monitor
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Figure 12-4. NVM Boot Diagram
Start
Initialize NVM
No
Initialization OK?
Restore the reset values
for the peripherals and jump
to the next boot solution
Yes
Valid code detection in NVM
No
NVM contains valid code
Yes
Copy the valid code
from external NVM to internal SRAM
Restore the reset values for the peripherals.
Perform remap and set the PC to 0
to jump to the downloaded application
End
The NVM bootloader program first initializes the PIOs related to the NVM device. Then it configures the right
peripheral depending on the NVM and tries to access this memory. If the initialization fails, it restores the reset values
for the PIO and the peripheral, and then tries to perform the same operations on the next NVM of the sequence.
If the initialization is successful, the NVM bootloader program reads the beginning of the NVM and determines if the
NVM contains a valid code.
If the NVM does not contain a valid code, the NVM bootloader program restores the reset value for the peripherals
and then tries to perform the same operations on the next NVM of the sequence.
If a valid code is found, this code is loaded from the NVM into the internal SRAM and executed by branching at
address 0x0000_0000 after remap. This code may be the application code or a second-level bootloader.
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Figure 12-5. Remap Action after Download Completion
0x0000_0000
0x0000_0000
Internal
ROM
Internal
SRAM0
Remap
0x0030_0000
0x0030_0000
Internal
SRAM0
Internal
SRAM0
12.4.6
Valid Code Detection
Two types of valid code detection are available:
• Arm Exception Vectors Check
• boot.bin File Check
12.4.6.1 Arm Exception Vectors Check
The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven Arm exception
vectors. Except for the sixth vector, these bytes must implement the Arm instructions for either branch or load PC
with PC-relative addressing.
Figure 12-6. LDR Opcode
31
1
28 27
1
1
0
0
24 23
1
I
P
U
20 19
1
W
0
16 15
Rn
12 11
Rd
0
Offset
Figure 12-7. B Opcode
31
1
28 27
1
1
0
1
24 23
0
1
0
0
Offset (24 bits)
Unconditional instruction: 0xE for bits 31 to 28.
Load PC with the PC-relative addressing instruction:
•
•
•
•
•
Rn = Rd = PC = 0xF
I==0 (12-bit immediate value)
P==1 (pre-indexed)
U offset added (U==1) or subtracted (U==0)
W==1
The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with
the user’s own vector. This procedure is described below.
Figure 12-8. Arm Vector 6 Structure
31
0
Size of the code to download in bytes
The value must be lower than 32 Kbytes.
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The following is an example of valid vectors:
00
04
08
0c
10
14
18
ea000006
eafffffe
eafffffe
eafffffe
eafffffe
00001234
eafffffe
B
B
B
B
B
←
B
0x20
0x04
0x08
0x0c
0x10
Code size = 4660 bytes
0x18
12.4.6.2 boot.bin File Check
This method is the one used on FAT-formatted SDCard and e.MMC. The boot program must be a file named
boot.bin written in the file system root directory. Its size must not exceed the maximum size allowed: 32 Kbytes
(0x8000). The Arm exception vectors at offset 0 in the “boot.bin” file must also pass the test described in 12.4.6.1
Arm Exception Vectors Check.
12.4.7
Detailed Memory Boot Procedures
12.4.7.1 NAND Flash Boot: NAND Flash Detection
After the NAND Flash interface configuration, a reset command is sent to the memory.
The reset time of the NAND memory, after this reset command, must not be higher than 100 µs.
Hardware ECC detection and correction are provided by the PMECC peripheral. See Section 37.18 “PMECC
Controller Functional Description” for more details.
The Boot Program is able to retrieve NAND Flash parameters and ECC requirements using either one of the
following methods:
•
•
Method 1 (recommended): NAND Flash Specific Header Detection
Method 2: ONFI 2.2 Parameters
It is highly recommended to use Method 1, since it indicates exactly how the PMECC has been configured to read or
write the bootable program in the NAND Flash, and does not rely only on the NAND Flash capabilities.
Once the Boot program retrieves the parameter, using one of the above two methods, it reads the first page again,
with or without ECC, depending on the usePmecc parameter. Then it looks for a valid code programmed just after the
header offset 0xD0. If the code is valid, the program is copied at the beginning of the internal SRAM.
Note: Booting on 16-bit NAND Flash is not possible; only 8-bit NAND Flash memories are supported.
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Figure 12-9. Boot NAND Flash Download
Start
Initialize NAND Flash interface
Send Reset command
No
First page contains valid header
Yes
NAND Flash is ONFI-compliant
No
Yes
Read NAND Flash and PMECC
parameters from the header
Read NAND Flash and PMECC
parameters from the ONFI
Check the Arm exception vectors
Copy the valid code
from external NVM to internal SRAM
Restore the reset values for the peripherals.
Perform remap and set the PC to 0
to jump to the downloaded application
Restore the reset values
for the peripherals and jump
to the next bootable memory
End
12.4.7.1.1 Method 1 (recommended): NAND Flash Specific Header Detection
This is the first method used to determine NAND Flash parameters. After receiving the Initialization and Reset
command, the Boot Program reads the first page without an ECC check, to determine whether the NAND parameter
header is present. The header is made of 52 times the same 32-bit word (for redundancy reasons) which must
contain NAND and PMECC parameters used to correctly perform the read of the rest of the data in the NAND. This
32-bit word is described below.
If the header is valid, the Boot program continues with the detection of a valid code.
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[NAND Flash Specific Header Detection]
Name:
Bit
31
NAND Flash Specific Header Detection
30
29
28
27
26
20
19
18
key[3:0]
25
eccOffset[8:6]
24
Access
Reset
Bit
23
22
21
eccOffset[5:0]
17
16
sectorSize[1:0]
Access
Reset
Bit
15
14
eccBitReq[2:0]
13
12
11
10
spareSize[8:4]
9
8
7
6
5
4
3
2
nbSectorPerPage[2:0]
1
0
usePmecc
Access
Reset
Bit
spareSize[3:0]
Access
Reset
Bits 31:28 – key[3:0] Value 0xC Must be Written here to Validate the Content of the Whole Word
Bits 26:18 – eccOffset[8:0] Offset of the First ECC Byte in the Spare Zone
A value below 2 is not allowed and is considered as 2.
Bits 17:16 – sectorSize[1:0] Size of the ECC Sector
Value
Description
0
For 512 bytes
1
For 1024 bytes per sector
Other values
For future use
Bits 15:13 – eccBitReq[2:0] Number of ECC Bits Required
Value
Description
0
2-bit ECC
1
4-bit ECC
2
8-bit ECC
3
12-bit ECC
4
24-bit ECC
Bits 12:4 – spareSize[8:0] Size of the Spare Zone in Bytes
Bits 3:1 – nbSectorPerPage[2:0] Number of Sectors per Page
Value
Description
0
1 sector per page
1
2 sectors per page
2
4 sectors per page
3
8 sectors per page
4
16 sectors per page
Bit 0 – usePmecc Use PMECC
Value
Description
0
Do not use PMECC to detect and correct the data.
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Value
1
Description
Use PMECC to detect and correct the data.
12.4.7.2 NAND Flash Boot: PMECC Error Detection and Correction
NAND Flash boot procedure uses PMECC to detect and correct errors during NAND Flash read operations in two
cases:
•
•
When the usePmecc flag is set in a specific NAND header. If the flag is not set, no ECC correction is performed
during the NAND Flash page read.
When the NAND Flash has been detected using ONFI parameters.
The ROM memory embeds the Galois field tables. The user does not need to embed them in his/her own software.
The Galois field tables are mapped in the ROM just after the ROM code, as shown in the following figure.
Figure 12-10. Galois Field Table Mapping
0x0000_0000
ROM code
0x0010_0000
0x0010_8000
Galois field
tables for
512-byte
sectors
correction
Galois field
tables for
1024-byte
sectors
correction
For a full description and an example of how to use the PMECC detection and correction feature, refer to the
software package dedicated to this device on www.microchip.com.
12.4.7.3 SDCard/e.MMC Boot
In the case of activated Card Detect pin in the Boot Configuration packet, and if the level of the Card Detect pin is
high, no communication with SDCard/e.MMC is performed (no IOs toggling). Otherwise, the SDCard/e.MMC access
is initiated (IOs toggling).
Supported SDCard Devices
SDCard Boot supports all SDCard memories compliant with the SD Memory Card Specification V3.0. This includes
SDMMC cards.
e.MMC with Boot Partition
The ROM code first checks if the e.MMC Boot Partition is enabled. If enabled, the ROM code reads the first
32 Kbytes of the boot partition, and copy them into the internal SRAM0.
FAT Filesystem Boot
If no boot partition is enabled on an e.MMC, the boot process continues with a standard SDCard/e.MMC detection,
and the ROM code looks for a boot.bin file in the root directory of a FAT12/16/32 file system.
12.4.7.4 SPI Flash Boot
Two types of SPI Flash are supported: SPI Serial Flash and SPI DataFlash.
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The SPI Flash bootloader tries to boot on SPI0, first looking for SPI Serial Flash, and then for SPI DataFlash.
It uses only one valid code detection: analysis of Arm exception vectors.
The SPI Flash read is done by means of a Continuous Read command from the address 0x0. This command is 0xE8
for DataFlash and 0x0B for Serial Flash devices.
Supported DataFlash Devices
The SPI Flash Boot program supports the DataFlash devices listed in the following table.
Table 12-2. DataFlash Devices
Device
Density
Page Size (bytes)
Number of Pages
AT45DB011
1 Mbit
264
512
AT45DB021
2 Mbits
264
1024
AT45DB041
4 Mbits
264
2048
AT45DB081
8 Mbits
264
4096
AT45DB161
16 Mbits
528
4096
AT45DB321
32 Mbits
528
8192
AT45DB642
64 Mbits
1056
8192
AT45DB641
64 Mbits
264
37768
Supported Serial Flash Devices
The SPI Flash Boot program supports all SPI Serial Flash devices responding correctly to both Get Status and
Continuous Read commands.
12.4.7.5 QSPI NOR Flash Boot
Hardware Considerations
The ROM code configures the hardware so that:
•
•
•
•
the QSPI controller uses SPI Mode 0 (CPOL = 0 and CPHA = 0),
the QSPIx_SCK clock frequency is ≤ 50 MHz,
QSPIx_SCK and QSPIx_CS do not use any internal pull-up/pull-down resistor,
each QSPIx_IO{0,1,2,3} uses the PIO controller’s internal pull-up resistor.
Software Considerations
Before reading any data, the ROM code sends a software reset to the QSPI NOR memory. Then the ROM code
looks for the Serial Flash Discoverable Parameters (SFDP) of the QSPI NOR memory, if available, to learn the
parameters (instruction op code, timing settings) required to read the user-programmed boot file.
If SFDP tables are not available, the ROM code uses hard-coded values as fallback settings to read the boot file.
The ROM code supports any QSPI NOR memory which can provide its Serial Flash Discoverable Parameters
(SFDP) as defined in the JEDEC JESD216B standard.
The supported revisions of this JEDEC standard are:
•
•
•
JESD216 (version 1.0)
JESD216 rev. A (version 1.5)
JESD216 rev. B (version 1.6)
Refer the QSPI NOR memory datasheet to check compliance with any of the above JEDEC JESD216 standard
revisions/versions.
•
QSPI NOR memories with SFDP (JEDEC JESD216x compliant)
The ROM code reads the memory SFDP tables to learn the factory settings (instruction op code, number of dummy
cycles, etc.). The ROM code also reads bits[22:20] in DWORD15 from the Basic Flash Parameter table (refer to
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JEDEC JESD216B specification) to select and then execute the relevant procedure, if any, to set the Quad Enable
(QE) bit in some internal register of the QSPI NOR memory.
For most memory manufacturers, this QE bit is nonvolatile and must be set before performing any Quad SPI
command. This is the only persistent setting that the ROM code may change in the internal registers of the QSPI
NOR memory. All other settings are kept unchanged.
Refer to the QSPI NOR memory datasheet to find which value was chosen by the memory manufacturer and written
into the SFDP tables.
Finally, the ROM code reads the boot file from the data area of the QSPI NOR memory, and then continues its boot
procedure.
•
QSPI NOR memories without SFDP
This section only applies when the ROM code fails to read the SFDP tables from the QSPI NOR memory.
The ROM code reads the JEDEC ID of the QSPI NOR memory, and then selects the read settings based on the
manufacturer ID (first byte of the JEDEC ID) from the following hard-coded values:
Cypress
(01h)
Micron (20h)
Macronix
(C2h)
Winbond
(EFh)
Others
Fast Read protocol
SPI 1-4-4
SPI 1-4-4
SPI 1-4-4
SPI 1-4-4
SPI 1-1-1
Fast Read op code
EBh
EBh
EBh
EBh
0Bh
24 bits
24 bits
24 bits
24 bits
24 bits
Number of mode clock cycles
2
1
2
2
0
Number of wait states
4
9
4
4
8
Value of mode cycles to enter
the 0-4-4 mode (XIP)
A0h
0h
The ROM code first sets
XIP bit[3] in the Volatile
Configuration Register
(VCR)
0Fh
A5h
N/A
Value of mode cycles to exit
the 0-4-4 mode (normal read)
00h
1h
00h
FFh
N/A
XIP supported
yes
yes
yes
yes
no
Address width
Those hard-coded parameters give a last chance to the ROM code to boot from a QSPI NOR memory in either
normal mode or XIP (Continuous Read) mode.
Table 12-3. QSPI NOR Memories Tested with and Supported by ROM Code (non-exhaustive)
Manufacturer
Memories
SST26VF016B
SST26VF032B
Microchip (SST)
SST26VF032BA
SST26VF064B
N25Q128A
N25Q128A13ESF
Micron
N25Q256A13ESF
N25Q512A13
MT25QL01G
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...........continued
Manufacturer
Memories
MX25V4035FM2I
MX25V8035FM2I
MX25V1635FM2I
MX25L3233FM2I-08G
MX25L3273FM2I-08G
MX25L6433FM2I-08G
MX25L6473FM2I-08G
Macronix
MX25L12835FM2I-10G
MX25L12845GMI-08G
MX25L12873GM2I-08G
MX25L25645G
MX25L25673G
MX25L51245GMI-10G
MX66L1G45GMI-08G
Spansion
S25FL127 (normal boot only; XIP fails)
S25FL164
S25FL512
Winbond
W25M512
Note: For an updated list of memories, refer to the "Booting from External Non-Volatile Memory (NVM) on
SAM9X60" application note (available later).
12.4.8
Hardware and Software Constraints
The table below provides clock frequencies configured by the ROM code during boot.
Table 12-4. Clock Frequencies During External Memory Boot Sequence
Clock
Frequency
PLLA
396 MHz
CPU_CLK
396 MHz
MCK
99 MHz
SDMMC (init/operational)
400 kHz / 25 MHz
SPI
11 MHz
QSPI
33 MHz
The NVM drivers use several PIOs in Peripheral mode to communicate with external memory devices. Care must be
taken when these PIOs are used by the application. The connected devices could be unintentionally driven at boot
time, and thus electrical conflicts between the output pins used by the NVM drivers and the connected devices could
occur.
The following table contains a list of pins that are driven during the boot program execution. These pins are driven
during the boot sequence for a period of less than 1 second if no correct boot program is found. The drive strength of
PULL-UP I/O pins is set to High while the pins are used in Peripheral mode by the ROM code.
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SAM9X60
Boot Strategies
Before performing the jump to the application in the internal SRAM, all the PIOs and peripherals used in the boot
program are set to their reset state.
Table 12-5. PIO Driven during Boot Program Execution
NVM Bootloader
Peripheral
IO Set
SDMMC_0
1
SDMMC_1
1
SDCard/e.MMC
Signal
SDMMC0_DAT0
SDMMC0_CMD
SDMMC0_CK
SDMMC0_DAT1
SDMMC0_DAT2
SDMMC0_DAT3
SDMMC1_DAT1
SDMMC1_DAT2
SDMMC1_DAT3
SDMMC1_DAT0
SDMMC1_CMD
SDMMC1_CK
D16–D23
1
NAND Flash
HSMC
NANDOE
NANDWE
NAND ALE
NAND CLE
NANDCS3
NAND WAIT
NANDOE
NANDWE
A21-A22
2
NANDCS3
NAND WAIT
D0-D7
A20
A23-A25
NANDCS2
NANDCS4
-NANDCS5
© 2020 Microchip Technology Inc.
Complete Datasheet
PIO Line
PIO_PA15A
PIO_PA16A
PIO_PA17A
PIO_PA18A
PIO_PA19A
PIO_PA20A
PIO_PA2B
PIO_PA3B
PIO_PA4B
PIO_PA11B
PIO_PA12B
PIO_PA13B
PIO_PD6APIO_PD13A
PIO_PD0A
PIO_PD1A
PIO_PD2A
PIO_PD3A
PIO_PD4A
PIO_PD5A
PIO_PD0A
PIO_PD1A
PIO_PD2APIO_PD3A
PIO_PD4A
PIO_PD5A
–
PIO_PD15B
PIO_PD16BPIO_PD18B
PIO_PD19B
PIO_PD20BPIO_PD21B
Pull-up
X
X
–
X
X
X
X
X
X
X
X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DS60001579C-page 72
SAM9X60
Boot Strategies
...........continued
NVM Bootloader
Peripheral
IO Set
1
FLEXCOM0_SPI
2
1
FLEXCOM1_SPI
2
SPI Flash
1
FLEXCOM2_SPI
2
1
FLEXCOM3_SPI
2
© 2020 Microchip Technology Inc.
Signal
MOSI
MISO
NPCS0
SPCK
MOSI
MISO
NPCS1
SPCK
MOSI
MISO
NPCS0
SPCK
MOSI
MISO
NPCS1
SPCK
MOSI
MISO
SPCK
NPCS0
MOSI
MISO
SPCK
NPCS1
MOSI
MISO
NPCS0
SPCK
MOSI
MISO
NPCS1
SPCK
Complete Datasheet
PIO Line
PIO_PA0A
PIO_PA1A
PIO_PA3A
PIO_PA4A
PIO_PA0A
PIO_PA1A
PIO_PA2A
PIO_PA4A
PIO_PA5A
PIO_PA6A
PIO_PC28C
PIO_PC29C
PIO_PA5A
PIO_PA6A
PIO_PC27C
PIO_PC29C
PIO_PA7A
PIO_PA8A
PIO_PB1B
PIO_PB2B
PIO_PA7A
PIO_PA8A
PIO_PB2B
PIO_PB0B
PIO_PC22B
PIO_PC23B
PIO_PC25B
PIO_PC26B
PIO_PC22B
PIO_PC23B
PIO_PC24B
PIO_PC26B
Pull-up
–
X
–
–
–
X
–
–
–
X
–
–
–
X
–
–
–
X
–
–
–
X
–
–
–
X
–
X
–
X
–
–
DS60001579C-page 73
SAM9X60
Boot Strategies
...........continued
NVM Bootloader
Peripheral
IO Set
1
2
3
SPI Flash
FLEXCOM4_SPI
4
5
6
1
2
SPI Flash
FLEXCOM5_SPI
3
4
5
© 2020 Microchip Technology Inc.
Signal
MISO
MOSI
SPCK
NPCS0
MISO
MOSI
SPCK
NPCS1
MISO
MOSI
SPCK
NPCS1
MISO
MOSI
SPCK
NPCS2
MISO
MOSI
SPCK
NPCS2
MISO
MOSI
SPCK
NPCS3
NPCS0
MISO
MOSI
SPCK
NPCS1
MISO
MOSI
SPCK
MISO
MOSI
SPCK
NPCS1
MISO
MOSI
SPCK
NPCS2
MISO
MOSI
SPCK
NPCS3
Complete Datasheet
PIO Line
PIO_PA11A
PIO_PA12A
PIO_PA13A
PIO_PA14A
PIO_PA11A
PIO_PA12A
PIO_PA13A
PIO_PA0C
PIO_PA11A
PIO_PA12A
PIO_PA13A
PIO_PA7B
PIO_PA11A
PIO_PA12A
PIO_PA13A
PIO_PA1B
PIO_PA11A
PIO_PA12A
PIO_PA13A
PIO_PA8C
PIO_PA11A
PIO_PA12A
PIO_PA13A
PIO_PB3B
PIO_PA8B
PIO_PA21B
PIO_PA22B
PIO_PA23B
PIO_PA0B
PIO_PA21B
PIO_PA22B
PIO_PA23B
PIO_PA21B
PIO_PA22B
PIO_PA23B
PIO_PA7C
PIO_PA21B
PIO_PA22B
PIO_PA23B
PIO_PA31B
PIO_PA21B
PIO_PA22B
PIO_PA23B
PIO_PA30B
Pull-up
X
–
–
–
X
–
–
–
X
–
–
–
X
–
–
–
X
–
–
–
X
–
–
–
–
X
–
–
–
X
–
–
X
–
–
–
X
–
–
–
–
X
–
–
DS60001579C-page 74
SAM9X60
Boot Strategies
...........continued
NVM Bootloader
Peripheral
QSPI Flash
Console and
SAM-BA Monitor
12.5
IO Set
QSPI_0
1
DBGU
1
FLEXCOM0_ UART
1
FLEXCOM1_UART
1
FLEXCOM2_UART
1
FLEXCOM3_UART
1
FLEXCOM4_UART
1
FLEXCOM5_UART
1
FLEXCOM6_UART
1
FLEXCOM7_UART
1
FLEXCOM8_UART
1
FLEXCOM9_UART
1
FLEXCOM10_UART
1
FLEXCOM11_UART
1
FLEXCOM12_UART
1
Signal
QSCK
QCS
QIO0
QIO1
QIO2
QIO3
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
DTXD
DRXD
PIO Line
PIO_PB19A
PIO_PB20A
PIO_PB21A
PIO_PB22A
PIO_PB23A
PIO_PB24A
PIO_PA10A
PIO_PA9A
PIO_PA0A
PIO_PA1A
PIO_PA5A
PIO_PA6A
PIO_PA7A
PIO_PA8A
PIO_PC22B
PIO_PC23B
PIO_PA12A
PIO_PA11A
PIO_PA22B
PIO_PA21B
PIO_PA30A
PIO_PA31A
PIO_PC0C
PIO_PC1C
PIO_PB4B
PIO_PB5B
PIO_PC8C
PIO_PC9C
PIO_PC16C
PIO_PC17C
PIO_PB19C
PIO_PB20C
PIO_PB21C
PIO_PB22C
Pull-up
–
–
X
X
X
X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SAM-BA Monitor
This part of the ROM code is executed when no valid code is found in any NVM during the NVM boot sequence, and
if the MON_DIS field is not set to 1 in the Boot Configuration packet.
The main RC oscillator is used as the Main Clock. To configure the USB clock, the Main Oscillator is enabled by
setting the CKGR_MOR.MOSCXTEN and CKGR_MOR.MOSCSEL bits. Then the external quartz detection is
started. This detection is successful when the MOSCXTS bit rises, else the USB is not activated and only UART is
used in SAM-BA Monitor.
If an external clock or crystal frequency is found, then the UPLL is configured to allow communication on the USB link
for the SAM-BA Monitor.
The SAM-BA Monitor steps are:
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 75
SAM9X60
Boot Strategies
•
•
•
Initialize UART and USB.
Check if USB Device enumeration occurred.
Check if characters are received on the UART.
Once the communication interface is identified, the application runs in an infinite loop waiting for different commands
as listed in Table 12-6.
Figure 12-11. SAM-BA Monitor
No valid code
in NVM
Init UART
External clock
detection
Init USB
No
USB enumeration
successful?
No
Character(s) received
on UART?
Yes
Run monitor
Wait for command
on the USB link
12.5.1
Yes
Run monitor
Wait for command
on the UART link
Command List
Table 12-6. Commands Available Through SAM-BA Monitor
Command
Action
Argument(s)
Example
N
Set Normal Mode
No argument
N#
T
Set Terminal Mode
No argument
T#
O
Write a byte
Address, Value#
O200001,CA#
o
Read a byte
Address,#
o200001,#
H
Write a halfword
Address, Value#
H200002,CAFE#
h
Read a halfword
Address,#
h200002,#
W
Write a word
Address, Value#
W200000,CAFEDECA#
w
Read a word
Address,#
w200000,#
S
Send a file
Address,#
S200000,#
R
Receive a file
Address, NbOfBytes#
R200000,1234#
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 76
SAM9X60
Boot Strategies
...........continued
Command
Action
Argument(s)
Example
G
Go
Address#
G200200#
V
Display version
No argument
V#
•
•
•
•
•
•
•
12.5.2
Mode commands:
– Normal mode configures SAM-BA Monitor to send/receive data in binary format.
– Terminal mode configures SAM-BA Monitor to send/receive data in ASCII format.
Write commands: Writes a byte (O), a halfword (H) or a word (W) to the target.
– Address: address in hexadecimal
– Value: byte, halfword or word to write in hexadecimal
– Output: ‘>’
Read commands: Reads a byte (o), a halfword (h) or a word (w) from the target.
– Address: address in hexadecimal
– Output: the byte, halfword or word read in hexadecimal followed by ‘>’
Send a file (S): Sends a file to a specified address.
– Address: address in hexadecimal
– Output: ‘>’
Note: There is a timeout on this command which is reached when the prompt ‘>’ appears before the end
of the command execution.
Receive a file (R): Receives data into a file from a specified address.
– Address: address in hexadecimal
– NbOfBytes: number of bytes in hexadecimal to receive
– Output: ‘>’
Go (G): Jumps to a specified address and executes the code.
– Address: address to jump to in hexadecimal
– Output: ‘>’ once returned from the program execution. If the executed program does not handle the link
register at its entry and does not return, the prompt is not displayed.
Get Version (V): Returns the Boot Program version.
– Output: version, date and time of ROM code followed by ‘>’
DBGU/UART Console Port
Communication is performed through the DBGU/UART port initialized to 115,200 bauds: 8 bits of data, no parity, 1stop bit.
12.5.2.1 Xmodem Protocol
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal using this protocol
can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size
embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the
Xmodem protocol requires some SRAM memory in order to work.
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC16 to
guarantee detection of maximum bit errors.
Xmodem protocol with CRC is supported by successful transmission reports provided both by a sender and by a
receiver. Each transfer block is as follows:
in which:
•
•
•
•
= 01 hex
= binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
= 1’s complement of the blk#.
= 2-byte CRC16
The following figure shows a transmission using this protocol.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 77
SAM9X60
Boot Strategies
Figure 12-12. Xmodem Transfer Example
Host
Device
C
SOH 01 FE Data[128] CRC CRC
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
12.5.3
USB Device Port
12.5.3.1 Supported External Crystal / External Clocks
The SAM-BA Monitor supports an external crystal or external clock frequency at 12 MHz, 16 MHz, 24 MHz or 48 MHz
to allow USB communication.
12.5.3.2 USB Class
The device uses the USB Communication Device Class (CDC) drivers to take advantage of the installed PC Serial
Communication software to talk over the USB. The CDC is implemented in all releases of Microsoft Windows®,
starting from Windows 98SE®. The CDC document, available at www.usb.org, describes how to implement devices
such as ISDN modems and virtual COM ports.
The vendor ID is 0x03EB. The product ID is 0x6124. These references are used by the host operating system to
mount the correct driver. On Windows systems, INF files contain the correspondence between vendor ID and product
ID.
12.5.3.3 Enumeration Process
The USB protocol is a master/slave protocol. The host starts the enumeration, sending requests to the device
through the control endpoint. The device handles standard requests as defined in the USB Specification.
Table 12-7. Handled Standard Requests
Request
Definition
GET_DESCRIPTOR
Returns the current device configuration value
SET_ADDRESS
Sets the device address for all future device accesses
SET_CONFIGURATION
Sets the device configuration
GET_CONFIGURATION
Returns the current device configuration value
GET_STATUS
Returns status for the specified recipient
SET_FEATURE
Used to set or enable a specific feature
CLEAR_FEATURE
Used to clear or disable a specific feature
The device also handles some class requests defined in the CDC class.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 78
SAM9X60
Boot Strategies
Table 12-8. Handled Class Requests
Request
Definition
SET_LINE_CODING
Configures DTE rate, stop bits, parity and number of character bits
GET_LINE_CODING
Requests current DTE rate, stop bits, parity and number of character bits
SET_CONTROL_LINE_STATE
RS-232 signal used to indicate to the DCE device that the DTE device is now
present
Unhandled requests are stalled.
12.5.3.4 Communication Endpoints
Endpoint 0 is used for the enumeration process.
Endpoint 1 (64-byte Bulk OUT) and endpoint 2 (64-byte Bulk IN) are used as communication endpoints.
SAM-BA Boot commands are sent by the host through Endpoint 1. If required, the message is split into several data
payloads by the host driver.
If the command requires a response, the host sends IN transactions to pick up the response.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 79
SAM9X60
System Controller Write Protection (SYSCWP)
13.
System Controller Write Protection (SYSCWP)
13.1
Functional Description
13.1.1
System Controller Peripheral Mapping
Table 13-1. System Controller Peripheral Mapping
13.1.2
Offset
System Controller Peripheral
Name
0x000-0x00C
Reset Controller
RSTC
0x010-0x01C
Shutdown Controller
SHDWC
0x020-0x03C
Real Time Timer
RTT
0x040-0x04C
Period Interval Timer
PIT
0x050-0x05C
Slow Clock Controller
SCKC
0x060-0x0A4
General Purpose Backup Registers
GPBR
0x0A8-0xD8
Real Time Clock
RTC
0x0DC
Write Protection Mode Register
SYSC_WPMR
0x0E0
Write Protection Status Register
SYSC_WPSR
0x100-0x16C
Real Time Clock (tamper control and timestamp)
RTC
0x180-0x1AC
Watchdog Timer
WDT
Register Write Protection
To prevent any single software error from modifying the configuration of the Reset Controller (RSTC), Shutdown
Controller (SHDWC), Real-time Timer (RTT), Periodic Interval Timer (PIT), Slow Clock Controller (SCKC), General
Purpose Backup Register (GPBR), Real-time Clock (RTC) and Watchdog Timer (WDT), some registers of these
peripherals can be write-protected by setting the WPEN and/or WPITEN bits in the System Controller Write
Protection Mode register (SYSC_WPMR).
Note: The WDT embeds additional write protection mechanisms.
When write protection is enabled, any attempt to write these registers is reported in the System Controller Write
Protection Status register (SYSC_WPSR).
The following registers can be write-protected when SYSC_WPMR.WPEN=1:
•
•
•
•
•
•
•
•
•
•
•
•
•
WDT Control Register
WDT Mode Register
RSTC Mode Register
SHDWC Mode Register
SHDWC Wakeup Inputs Register
PIT Mode Register
SCKC Configuration Register
RTC Control Register
RTC Mode Register
RTC Time Alarm Register
RTC Calendar Alarm Register
RTT Mode Register
RTT Alarm Register
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 80
SAM9X60
System Controller Write Protection (SYSCWP)
•
•
•
RTT Modulo Selection Register
GPBR Full Clear Register
GPBR Registers
The following registers can be write-protected when SYSC_WPMR.WPITEN=1:
•
•
RTC Interrupt Enable Register
RTC Interrupt Disable Register
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 81
SAM9X60
System Controller Write Protection (SYSCWP)
13.2
Register Summary
Offset
Name
0x00
SYSC_WPMR
0x04
SYSC_WPSR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
6
5
4
3
2
1
0
WPITEN
WPEN
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WVSRC[7:0]
WPVS
Complete Datasheet
DS60001579C-page 82
SAM9X60
System Controller Write Protection (SYSCWP)
13.2.1
SYSC Write Protection Mode Register
Name:
Offset:
Reset:
Property:
SYSC_WPMR
0x00
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
WPITEN
R/W
0
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x535943 PASSWD Writing any other value in this field aborts the write operation of the WPEN and WPITEN
bits. Always reads as 0.
Bit 1 – WPITEN Write Protection RTC Interrupt Enable
Value
Description
0
Disables the write protection of the RTC_IER/RTC_IDR configuration registers if WPKEY corresponds
to 0x535943 (“SYC” in ASCII).
1
Enables the write protection of the RTC_IER/RTC_IDR configuration registers if WPKEY corresponds
to 0x535943 (“SYC” in ASCII).
Bit 0 – WPEN Write Protection Enable
Value
Description
0
Disables the write protection of the configuration registers if WPKEY corresponds to 0x535943 (“SYC”
in ASCII).
1
Enables the write protection of the configuration registers if WPKEY corresponds to 0x535943 (“SYC”
in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 83
SAM9X60
System Controller Write Protection (SYSCWP)
13.2.2
SYSC Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
SYSC_WPSR
0x04
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
WVSRC[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
WPVS
R
0
Access
Reset
Bits 15:8 – WVSRC[7:0] Write Violation Source
When bit WPVS is equal to 1, the field WVSRC indicates the register address offset at which a write access has been
attempted.
Bit 0 – WPVS Write Protection Register Violation Status
WDT_CR, WDT_MR, RTT_MODR, RTC_IDR and RTC_IER can be write-protected but WPVS does not report any
violation for these registers.
Value
Description
0
No write protection violation has occurred since the last read of SYSC_WPSR.
1
A write protection violation has occurred since the last read of SYSC_WPSR. The associated violation
is reported into field WVSRC.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 84
SAM9X60
General Purpose Backup Registers (GPBR)
14.
General Purpose Backup Registers (GPBR)
14.1
Description
The System Controller embeds 256 bits of General Purpose Backup registers organized as 8 32-bit registers.
It is possible to generate an immediate clear of the content of General Purpose Backup registers 0 to 3 if a tamper
event is detected on WKUP1 to WKUP8 pins. These pins are internally routed through the VDDCORE area, thus
tamper events can be generated only when the VDDCORE is powered. These pins are also used for fast wakeup in
Power Management Controller (PMC). Thus, if some WKUP pins are not enabled for fast wakeup in PMC, they can
be enabled for tamper event detection. The immediate clear of the GPBR is enabled if RSTC_MR.ENGCLR=1.
The immediate clear on tamper detection can be extended to all General Purpose Backup registers by writing to ‘1’
GPBR_FCLR.FCLR.
If an event has been detected on WKUP pins enabled for event detection in RTC, it is not possible to write to the
General Purpose Backup registers (SYS_GPBRx) while the event has not been cleared.
SYS_GPBR0 to SYS_GPBR7 can be individually (each 32-bit part-select) read and write-protected by configuring the
register GPBR_MR. This register is write-once, which means that once it has been configured, the read or write
protection is available until the loss of VDDBU.
14.2
Embedded Characteristics
•
•
•
256 bits of General Purpose Backup Registers
Immediate Clear on WKUP Event
Read and Write Protection for SYS_GPBR0 to SYS_GPBR7
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 85
SAM9X60
General Purpose Backup Registers (GPBR)
14.3
Register Summary
Offset
Name
0x00
GPBR_MR
0x04
GPBR_FCLR
0x08
SYS_GPBR0
0x0C
SYS_GPBR1
0x10
SYS_GPBR2
0x14
SYS_GPBR3
0x18
SYS_GPBR4
0x1C
SYS_GPBR5
0x20
SYS_GPBR6
0x24
SYS_GPBR7
Bit Pos.
7
6
5
4
3
2
1
0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
GPBRRP15
GPBRRP7
GPBRWP15
GPBRWP7
GPBRRP14
GPBRRP6
GPBRWP14
GPBRWP6
GPBRRP13
GPBRRP5
GPBRWP13
GPBRWP5
GPBRRP12
GPBRRP4
GPBRWP12
GPBRWP4
GPBRRP11
GPBRRP3
GPBRWP11
GPBRWP3
GPBRRP10
GPBRRP2
GPBRWP10
GPBRWP2
GPBRRP9
GPBRRP1
GPBRWP9
GPBRWP1
GPBRRP8
GPBRRP0
GPBRWP8
GPBRWP0
© 2020 Microchip Technology Inc.
FCLR
GPBR_VALUE[31:24]
GPBR_VALUE[23:16]
GPBR_VALUE[15:8]
GPBR_VALUE[7:0]
GPBR_VALUE[31:24]
GPBR_VALUE[23:16]
GPBR_VALUE[15:8]
GPBR_VALUE[7:0]
GPBR_VALUE[31:24]
GPBR_VALUE[23:16]
GPBR_VALUE[15:8]
GPBR_VALUE[7:0]
GPBR_VALUE[31:24]
GPBR_VALUE[23:16]
GPBR_VALUE[15:8]
GPBR_VALUE[7:0]
GPBR_VALUE[31:24]
GPBR_VALUE[23:16]
GPBR_VALUE[15:8]
GPBR_VALUE[7:0]
GPBR_VALUE[31:24]
GPBR_VALUE[23:16]
GPBR_VALUE[15:8]
GPBR_VALUE[7:0]
GPBR_VALUE[31:24]
GPBR_VALUE[23:16]
GPBR_VALUE[15:8]
GPBR_VALUE[7:0]
GPBR_VALUE[31:24]
GPBR_VALUE[23:16]
GPBR_VALUE[15:8]
GPBR_VALUE[7:0]
Complete Datasheet
DS60001579C-page 86
SAM9X60
General Purpose Backup Registers (GPBR)
14.3.1
GPBR Mode Register
Name:
Offset:
Reset:
Property:
GPBR_MR
0x0
0x00000000
Read/Write-Once
This register is write-once. All bits are cleared at first power-up and on each loss of VDDBU.
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
GPBRRP15
R/W
0
30
GPBRRP14
R/W
0
29
GPBRRP13
R/W
0
28
GPBRRP12
R/W
0
27
GPBRRP11
R/W
0
26
GPBRRP10
R/W
0
25
GPBRRP9
R/W
0
24
GPBRRP8
R/W
0
23
GPBRRP7
R/W
0
22
GPBRRP6
R/W
0
21
GPBRRP5
R/W
0
20
GPBRRP4
R/W
0
19
GPBRRP3
R/W
0
18
GPBRRP2
R/W
0
17
GPBRRP1
R/W
0
16
GPBRRP0
R/W
0
15
GPBRWP15
R/W
0
14
GPBRWP14
R/W
0
13
GPBRWP13
R/W
0
12
GPBRWP12
R/W
0
11
GPBRWP11
R/W
0
10
GPBRWP10
R/W
0
9
GPBRWP9
R/W
0
8
GPBRWP8
R/W
0
7
GPBRWP7
R/W
0
6
GPBRWP6
R/W
0
5
GPBRWP5
R/W
0
4
GPBRWP4
R/W
0
3
GPBRWP3
R/W
0
2
GPBRWP2
R/W
0
1
GPBRWP1
R/W
0
0
GPBRWP0
R/W
0
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – GPBRRPx GPBRx Read Protection
Value
Description
0
The content of the corresponding GPBR register (32-bit part-select) can be read.
1
The corresponding GPBR register (32-bit part-select) always returns zero when read.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – GPBRWPx GPBRx Write Protection
Value
Description
0
The corresponding GPBR register (32-bit part-select) can be written.
1
The corresponding GPBR register (32-bit part-select) is write-protected.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 87
SAM9X60
General Purpose Backup Registers (GPBR)
14.3.2
GPBR Full Clear Register
Name:
Offset:
Reset:
Property:
GPBR_FCLR
0x04
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
All bits are cleared at first power-up and on each loss of VDDBU.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FCLR
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – FCLR Full Clear Enable
GPBR full clear is only possible if the system is not in Backup mode. In Backup mode, FCLR has no effect.
Value
Description
0
SYS_GPBR0 to SYS_GPBR3 are immediately cleared in case of fast wakeup pin tamper event.
1
All SYS_GPBRx are immediately cleared in case of fast wakeup pin tamper event.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 88
SAM9X60
General Purpose Backup Registers (GPBR)
14.3.3
General Purpose Backup Register x [x=0..7]
Name:
Offset:
Reset:
Property:
SYS_GPBRx
0x08 + x*0x04 [x=0..7]
0x00000000
R/W
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
These registers are reset at first power-up and on each loss of VDDBU.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
GPBR_VALUE[31:24]
R/W
R/W
0
0
20
19
GPBR_VALUE[23:16]
R/W
R/W
0
0
12
11
GPBR_VALUE[15:8]
R/W
R/W
0
0
4
3
GPBR_VALUE[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – GPBR_VALUE[31:0] Value of SYS_GPBRx
Note: If an event has been detected on WKUP pins enabled for tamper event detection in RTC, it is not possible to
write to the General Purpose Backup registers (SYS_GPBRx) while the event has not been cleared.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 89
SAM9X60
Watchdog Timer (WDT)
15.
Watchdog Timer (WDT)
15.1
Description
The Watchdog Timer (WDT) is used to prevent system lockup if the software becomes trapped in a deadlock. It
features one 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). The
WDT can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in
Debug mode or Sleep mode (Idle mode).
15.2
Embedded Characteristics
•
•
•
•
15.3
12-bit Key-protected Programmable Counter
Watchdog Clock is Independent from Processor Clock
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped while the Processor is in Debug State or in Idle Mode
Block Diagram
Figure 15-1. WDT Block Diagram
WD_MR.RPTHRST
WDT_RESET
(to reset controller)
WD_MR.PERIODRST
WDT_WL.PERIOD
load
SLCK/128
12-bit down
counter
WDT_VR.COUNTER
WD_IMR.PERINT
=0
WD_IMR.RPTHINT
en_load
≤ PERIOD - RPTH
WDT_CR.WDRSTT
WD_IMR.LVLINT
WDT_INT
(to interrupt controller)
≤ PERIOD - LVLTH
15.4
Functional Description
The WDT is used to prevent system lockup if the software becomes trapped in a deadlock. It is supplied with
VDDCORE. It restarts with initial values on processor reset.
The WDT is built around a 12-bit down counter loaded with the value defined in field PERIOD of the Window Level
Register (WDT_WLR). WDT uses slow clock divided by 128 to establish the maximum watchdog period to 16
seconds (with a typical slow clock of 32.768 kHz).
The following parameters can be configured:
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 90
SAM9X60
Watchdog Timer (WDT)
•
•
•
Watchdog event period: a watchdog event occurs when the 12-bit down counter reaches 0, and leads to either
an interrupt (if bit PERINT in the Interrupt Mask register (WDT_IMR) is high) or a reset (if bit PERIODRST in the
Mode register (WDT_MR) is high).
Minimum restart period: if the restart command is performed before this period, WDT creates a repeat violation.
A repeat violation leads to either an interrupt (if WDT_IMR.RPTHINT = 1) or a reset (if WDT_MR.RPTHRST =
1).
Maximum period before single interrupt event: if WDT_IMR.LVLINT = 1, a single interrupt is generated (no
reset). The WDT_ILR.LVLTH value must be lower than WDT_WLR.PERIOD.
After a processor reset, the value of PERIOD is 0xFFF, corresponding to the maximum value of the counter with the
external reset generation enabled (bit PERIODRST at 1 after a backup reset). This means that the WDT is running at
reset, i.e., at powerup. The user can either disable the WDT by setting bit WDT_MR.WDDIS to ‘1’ or reprogram the
WDT to meet the maximum WDT period the application requires.
If the WDT is restarted by writing into the corresponding Control register (WDT_CR), the corresponding WDT_MR
must not be programmed during a period of time of three slow clock periods following the WDT_CR write access. In
any case, programming a new value in WDT_MR automatically initiates a restart instruction.
WDT_MR, WDT_WLR and WDT_ILR (Interrupt Level register) can be written until a WDT_CR.LOCKMR command is
issued in the corresponding WDT_CR. Only a peripheral reset can configure the bit LOCKMR to 0.
When the bit WDT_CR.LOCKMR = 0, writing WDT_WLR reloads the corresponding WDT with the newly
programmed mode parameters.
In normal operation, the user reloads the WDT at regular intervals before the timer underflow occurs, by setting bit
WDT_CR.WDRSTT. The WDT counter is then immediately reloaded from PERIOD and restarted, and the slow clock
128 divider is reset and restarted.
Writing WDR_CR without the correct hard-coded key has no effect (see Watchdog Timer Control Register).
A repeat threshold can be defined for each watchdog in order to protect against dead-locks that would repeatedly
restart the watchdog. WDT_WLR.RPTH defines the minimum number of cycles to wait after a watchdog restart
before the WDT can be started again. If a watchdog restart occurs before this limit is reached, a repeat threshold
failure is asserted and the RPTHINT bit in the Interrupt Status register (WDT_ISR) is set to one.
If WDT_IMR.RPTHINT is high and a repeat threshold violation occurs in the WDT, an interrupt is generated.
If WDT_MR.RPTHRST is high and a repeat threshold violation occurs in the WDT, a watchdog reset is generated.
WDT reload must occur while the WDT counter is within a window between 0 and (PERIOD–RPTH). PERIOD and
RPTH are defined in WDT_WLR.
Note that this feature can be disabled by programming a null RPTH value. In such configuration, restarting the WDT
is permitted in the whole range [0 up to PERIOD] and does not generate an error. This is the default configuration on
reset (RPTH is null).
If a reset is generated or if WDT_SR is read, the status bits are reset and the interrupt is cleared.
Writing WDT_MR reloads and restarts the down counter.
While the processor is in debug state or in Sleep mode, the counter may be stopped depending on the value
programmed for the bits WDIDLEHLT and WDDBGHLT in WDT_MR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 91
SAM9X60
Watchdog Timer (WDT)
Figure 15-2. Watchdog Timing Diagram
WDT Down Counter
Value
PERIOD
WDT_WLR.PERIOD
RPTH
(Repeat Threshold)
LVLTH
(Level Threshold)
Forbidden window:
in case of a WDT
restart, an interrupt
or a reset can be
generated
If the WDT counter reaches this point,
an interrupt can be generated.
Permitted window:
WDT can be safely
restarted in this area
Time
If the WDT counter reaches 0,
an interrupt or a reset can be generated
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 92
SAM9X60
Watchdog Timer (WDT)
15.5
Register Summary
Offset
Name
0x00
WDT_CR
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
WDT_MR
WDT_VR
WDT_WLR
WDT_ILR
WDT_IER
WDT_IDR
WDT_ISR
WDT_IMR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
6
5
4
3
2
1
0
KEY[7:0]
LOCKMR
WDIDLEHLT WDDBGHLT
RPTHRST
WDRSTT
WDDIS
PERIODRST
COUNTER[11:8]
COUNTER[7:0]
RPTH[11:8]
RPTH[7:0]
PERIOD[11:8]
PERIOD[7:0]
LVLTH[11:8]
LVLTH[7:0]
Complete Datasheet
LVLINT
RPTHINT
PERINT
LVLINT
RPTHINT
PERINT
LVLINT
RPTHINT
PERINT
LVLINT
RPTHINT
PERINT
DS60001579C-page 93
SAM9X60
Watchdog Timer (WDT)
15.5.1
Watchdog Timer Control Register
Name:
Offset:
Reset:
Property:
WDT_CR
0x00
–
Write-only
The WDT_CR register values must not be modified within three slow clock periods following a restart of the WDT
performed by a write access in WDT_CR. Any modification will cause the WDT to trigger an end of period earlier than
expected.
Bit
31
30
29
28
27
26
25
24
KEY[7:0]
Access
Reset
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
LOCKMR
W
–
3
2
1
0
WDRSTT
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:24 – KEY[7:0] Password
Value
Name
Description
0xA5
PASSWD
Writing any other value in this field aborts the write operation.
Bit 4 – LOCKMR Lock Mode Register Write Access
Value
Description
0
No effect.
1
Locks the configuration registers if KEY is written to 0xA5. Write accesses to WDT_MR, WDT_WLR
and WDT_ILR have no effect.
Bit 0 – WDRSTT Watchdog Restart
Value
Description
0
No effect.
1
Restarts the WDT if KEY is written to 0xA5.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 94
SAM9X60
Watchdog Timer (WDT)
15.5.2
Watchdog Timer Mode Register
Name:
Offset:
Reset:
Property:
WDT_MR
0x04
0x00000030
Read/Write
Write access to this register has no effect if the LOCKMR command is issued in WDT_CR (unlocked on hardware
reset).
The WDT_MR register values must not be modified within three slow clock periods following a restart of the WDT
performed by a write access in WDT_CR. Any modification will cause the WDT to trigger an end of period earlier than
expected.
Bit
31
30
29
WDIDLEHLT
R/W
0
28
WDDBGHLT
R/W
0
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
WDDIS
R/W
0
11
10
9
8
7
6
5
RPTHRST
R/W
1
4
PERIODRST
R/W
1
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 29 – WDIDLEHLT Watchdog Idle Halt
Value
Description
0
The WDT runs when the system is in idle state.
1
The WDT stops when the system is in idle state.
Bit 28 – WDDBGHLT Watchdog Debug Halt
Value
Description
0
The WDT runs when the processor is in debug state.
1
The WDT stops when the processor is in debug state.
Bit 12 – WDDIS Watchdog Disable
Value
Description
0
Enables the WDT.
1
Disables the WDT.
Bit 5 – RPTHRST Minimum Restart Period
Value
Description
0
No reset is generated if the WDT is restarted before the RPTH threshold.
1
A reset is generated if the WDT is restarted before the RPTH threshold.
Bit 4 – PERIODRST Period Reset
Value
Description
0
No reset is generated if the WDT down counter reaches 0.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 95
SAM9X60
Watchdog Timer (WDT)
Value
1
Description
A reset is generated once the WDT down counter reaches 0.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 96
SAM9X60
Watchdog Timer (WDT)
15.5.3
Watchdog Timer Value Register
Name:
Offset:
Reset:
Property:
Bit
WDT_VR
0x08
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
COUNTER[11:8]
R
R
0
0
8
R
0
2
1
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
4
3
COUNTER[7:0]
R
R
0
0
Bits 11:0 – COUNTER[11:0] Watchdog Down Counter Value
Shows the current value of the WDT down counter for debug operation.
Due to the asynchronous operation of the WDT with respect to the rest of the chip, to be certain that the value read in
this register is valid and stable, it is necessary to read the register twice. If the data is the same both times, then it is
valid. Therefore, a minimum of two and a maximum of three accesses are required.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 97
SAM9X60
Watchdog Timer (WDT)
15.5.4
Watchdog Timer Window Level Register
Name:
Offset:
Reset:
Property:
Bit
31
WDT_WLR
0x0C
0x00000FFF
Read/Write
30
29
28
27
26
25
24
RPTH[11:8]
Access
Reset
Bit
23
22
21
20
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
RPTH[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
Access
Reset
Bit
Access
Reset
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
4
3
PERIOD[7:0]
R/W
R/W
1
1
10
9
PERIOD[11:8]
R/W
R/W
1
1
8
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 27:16 – RPTH[11:0] Repeat Threshold
Defines the period before which a WDT restart generates an interrupt.
Bits 11:0 – PERIOD[11:0] Watchdog Period
Defines the period after which the WDT generates a reset.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 98
SAM9X60
Watchdog Timer (WDT)
15.5.5
Watchdog Timer Interrupt Level Register
Name:
Offset:
Reset:
Property:
Bit
WDT_ILR
0x10
0x00000FFF
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
R/W
1
7
6
5
4
9
LVLTH[11:8]
R/W
R/W
1
1
8
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
LVLTH[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 11:0 – LVLTH[11:0] Level Threshold
Defines the period after which the WDT generates an interrupt.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 99
SAM9X60
Watchdog Timer (WDT)
15.5.6
Watchdog Interrupt Enable Register
Name:
Offset:
Reset:
Property:
WDT_IER
0x14
–
Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
LVLINT
W
–
1
RPTHINT
W
–
0
PERINT
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – LVLINT Interrupt Level Threshold Interrupt Enable
Bit 1 – RPTHINT Repeat Threshold Interrupt Enable
Bit 0 – PERINT Period Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 100
SAM9X60
Watchdog Timer (WDT)
15.5.7
Watchdog Interrupt Disable Register
Name:
Offset:
Reset:
Property:
WDT_IDR
0x18
–
Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
LVLINT
W
–
1
RPTHINT
W
–
0
PERINT
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – LVLINT Interrupt Level Threshold Interrupt Disable
Bit 1 – RPTHINT Repeat Threshold Interrupt Disable
Bit 0 – PERINT Period Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 101
SAM9X60
Watchdog Timer (WDT)
15.5.8
Watchdog Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
WDT_ISR
0x1C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
LVLINT
R
0
1
RPTHINT
R
0
0
PERINT
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – LVLINT Interrupt Level Threshold Interrupt Status (cleared on read)
Value
Description
0
No level threshold failure has occurred in the WDT since the last read of WDT_ISR.
1
At least one level threshold failure has occurred in the WDT since the last read of WDT_ISR.
Bit 1 – RPTHINT Repeat Threshold Interrupt Status (cleared on read)
Value
Description
0
No repeat threshold failure has occurred in the WDT since the last read of WDT_ISR.
1
At least one repeat threshold failure has occurred in the WDT since the last read of WDT_ISR.
Bit 0 – PERINT Period Interrupt Status (cleared on read)
Value
Description
0
No period failure has occurred in the WDT since the last read of WDT_ISR.
1
At least one period failure has occurred in the WDT since the last read of WDT_ISR.
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SAM9X60
Watchdog Timer (WDT)
15.5.9
Watchdog Interrupt Mask Register
Name:
Offset:
Reset:
Property:
WDT_IMR
0x20
0x00000000
Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
LVLINT
R
0
1
RPTHINT
R
0
0
PERINT
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – LVLINT Interrupt Level Threshold Interrupt Mask
Bit 1 – RPTHINT Repeat Threshold Interrupt Mask
Bit 0 – PERINT Period Interrupt Mask
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SAM9X60
Reset Controller (RSTC)
16.
Reset Controller (RSTC)
16.1
Description
The Reset Controller (RSTC) handles all the resets of the system without any external components. It reports which
reset occurred last.
The RSTC is driven by Power-on Reset (POR) cells, software, an external reset pin, and peripheral events.
The RSTC drives simultaneously the External reset and the Peripheral and Processor resets.
16.2
Embedded Characteristics
•
•
•
16.3
Driven by Embedded Power-on Reset, Software, External Reset Pin and Peripheral Events
Management of All System Resets, Including
– External devices through an I/O multiplexed output reset pin
– Processor
– Peripheral set
Reset Source Status
– Status of the last reset
– Either VDDCORE, VDDIN33 and VDDBU POR reset, Software reset, User reset, Watchdog reset, 32.768
kHz Crystal Oscillator Failure Detection reset
Block Diagram
Figure 16-1. RSTC Block Diagram
BACKUP area reset
POR
VDDBU
Reset Controller
POR
VDDIN33
POR
VDDCORE
RSTC
interrupt line
VDDCORE reset
Reset
State
Manager
NRST Pin
I/O Pin
PIO
Ctrl
nrst_out
NRST
Manager
Processor and
peripherals
reset line
external_reset
From wd_fault
watchdog
Config.
Reg.
MD_SLCK
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GPBR
Enable Clear on
Tamper Event
DS60001579C-page 104
SAM9X60
Reset Controller (RSTC)
16.4
Functional Description
16.4.1
Overview
The RSTC is made up of an NRST manager and a reset state manager. The RSTC clock is MD_SLCK (monitoring
domain slow clock). The RSTC generates the following reset signals:
•
•
•
Processor reset line (also resets the Watchdog Timer)
Entire set of embedded peripherals reset line
NRST pin
Note: Processor and peripheral reset lines are driven in the same way.
These internal reset signals are asserted by the RSTC, either on events generated by peripherals, events on NRST
pin, or on software action. The reset state manager controls the generation of reset signals and drives the NRST pin
when required.
The NRST manager asserts the NRST pin during a programmable time, thus controlling external device resets.
The Mode register (RSTC_MR), used to configure the RSTC, is powered by VDDBU.
16.4.2
NRST Manager
The NRST manager samples the NRST pin and drives this pin low when required by the reset state manager. See
the following figure.
Figure 16-2. NRST Pin Management
RSTC_MR
URSTIEN
RSTC_SR
URSTS
NRSTL
RSTC_MR
URSTEN
NRST
Other
reset
interrupt
sources
RSTC
Interrupt line
user_reset
RSTC_MR
ERSTL
I/O
nrst_out
External Reset Timer
external_reset
PIO
Ctrl
16.4.2.1 NRST Signal or Interrupt
The NRST manager handles the NRST input line asynchronously if RSTC_MR.URSTASYNC =1. When the NRST
input is low, a user reset is immediately reported to the Reset State manager and the internal reset signals are
asserted even if there is a clock failure on MD_SLCK (safe reset).
The NRST manager handles the NRST input line synchronously if RSTC_MR.URSTASYNC=0. When the line is low,
it is first resynchronized on slow clock before it is reported to the Reset State manager. In both cases, when the
NRST goes from low to high, the internal reset is synchronized with the monitoring slow clock to provide a safe
internal de-assertion of reset (if enabled).
If RSTC_MR.URSTEN=0, the assertion of the NRST input pin does not trigger a VDDCORE domain reset.
The level of the pin NRST is reported in NRSTL of the Status register (RSTC_SR).
As soon as the pin NRST is asserted (low level), RSTC_SR.URSTS=1. This bit is cleared on read.
If RSTC_MR.URSTIEN=1, the assertion of NRST pin triggers an interrupt rather than a VDDCORE reset.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Reset Controller (RSTC)
16.4.2.2 NRST External Reset Control
The RSTC can be configured to assert the external reset line (NRST). The NRST pin is driven low for a time
programmed by RSTC_MR.ERSTL. This assertion duration lasts 2(ERSTL+1) MD_SLCK cycles. This assertion
duration time is in the range of 60 µs to 2 seconds. If ERSTL=0 , a two slow clock period duration is generated on the
NRST pin.
This feature allows the NRST line to be compliant with any external devices connected on the system reset (i.e.,
when external devices require a longer start-up time than the processor system).
16.4.3
Reset States
The reset state manager handles the different reset sources and generates the internal reset signals. It reports the
reset status in RSTC_SR.RSTTYP. RSTC_SR.RSTTYP is updated when the Processor reset is released.
If more than one reset event occurred since the last read of RST_SR, the field RSTTYP reports the first reset that
occurred.
16.4.3.1 General Reset
A general reset occurs when a VDDBU Power-on reset is detected. The internal VDDCORE reset signal is asserted
when a general reset occurs. All the reset signals are released and RSTC_SR.RSTTYP reports a general reset.
The NRST line rises two cycles after the VDDCORE reset line, as ERSTL defaults at value 0x0.
The following figure shows how the general reset affects the reset signals.
Figure 16-3. General Reset Timing Diagram
Power Supply
Activation
MD_SLCK
Main RC
Oscillator
Any
Freq.
MCK
Backup Area POR
Output
Backup Logic
Reset
2 SLCK cycles
Active
5 SLCK
cycles
5 Main RC cycles
Inactive
Regulator Startup
VDDCORE POR
Output
Inactive
6.5 SLCK cycles + 2 Main RC cycles
Processor
Reset Line
Active
Inactive
Peripheral
Reset Line
Active
Inactive
NRST
(nrst_out)
Active
3 SLCK cycles
RSTTYP
XXX
0x0 = General Reset
Inactive
XXX
16.4.3.2 Backup Exit Reset
A Backup reset occurs when the chip exits from Backup mode. While exiting Backup mode, the VDDCORE reset
signal is de-asserted.
RSTC_SR.RSTTYP is updated to report a Backup reset.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Reset Controller (RSTC)
16.4.3.3 32.768 kHz Crystal Oscillator Failure Detection Reset
The 32.768 kHz Crystal Oscillator Failure Detection reset is done when the 32.768 kHz crystal oscillator frequency
monitoring circuitry in the PMC detects a failure and RSTC_MR.SCKSW is written to '1'. This reset lasts three slow
clock cycles.
When RSTC_MR.SCKSW is written to ‘0’, the 32.768 kHz crystal oscillator fault has no impact on the RSTC.
During the 32.768 kHz Crystal Oscillator Failure Detection reset, the Processor reset and the Peripheral reset are
asserted. The NRST line is also asserted, depending on the value of RSTC_MR.ERSTL.
When the 32.768 kHz crystal oscillator failure generates a VDDCORE reset, PMC_SR.XT32KERR is automatically
cleared by the Peripheral and Processor resets.
Figure 16-4. 32.768 kHz Crystal Oscillator Failure Detection Reset Timing Diagram
MD_SLCK
32K Crystal
Clock Fail
Main RC
Oscillator
MCK
Any
Frequency.
Processor and
Peripherals
Reset Line
Any
Frequency.
3 MD_SLCK cycles + 2 MCK cycles
Inactive
Inactive
Active
Min = 2 MD_SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2)
NRST
(nrst_out)
RSTTYP
Inactive
XXX
Active
Inactive
0x7 = XTAL Fail Reset
16.4.3.4 Watchdog Reset
The Watchdog reset is entered when a watchdog fault occurs. This reset lasts three MD_SLCK cycles.
When in Watchdog reset, the Processor reset and the Peripheral reset are asserted. The NRST line is also asserted,
depending on the value of RSTC_MR.ERSTL. However, the resulting low level on NRST does not result in a User
reset state.
The WDT is reset by the Processor reset signal. As the watchdog fault always causes a Processor reset if
WDT_MR.WDRSTEN is written to ‘1’, the WDT is always reset after a Watchdog reset, and the Watchdog is enabled
by default and with a period set to a maximum.
When WDT_MR.WDRSTEN is written to ‘0’, the watchdog fault has no impact on the RSTC.
After a watchdog overflow occurs, the report on the RSTC_SR.RSTTYP may differ (either WDT_RST or USER_RST)
depending on the external components driving the NRST pin. For example, if the NRST line is driven through a
resistor and a capacitor (NRST pin debouncer), the reported value is USER_RST if the low-to-high transition is
greater than one MD_SLCK cycle.
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Complete Datasheet
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SAM9X60
Reset Controller (RSTC)
Figure 16-5. Watchdog Reset Timing Diagram
MD_SLCK
WDT Fault
Main RC
Oscillator
MCK
Any
Frequency.
Any
Frequency.
3 MD_SLCK cycles + 2 MCK cycles
RSTTYP
Processor and
Peripherals
Reset Line
XXX
Inactive
0x2 = Watchdog Reset
Active
Inactive
Min = 2 MD_SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2)
NRST
(nrst_out)
Inactive
Active
Inactive
16.4.3.5 Software Reset
The RSTC offers commands to assert the different reset signals. These commands are performed by writing the
Control register (RSTC_CR) with the following bits at ‘1’:
•
•
RSTC_CR.PROCRST: Writing a ‘1’ to PROCRST resets the processor and all the embedded peripherals,
including the memory system and, in particular, the Remap Command.
RSTC_CR.EXTRST: Writing a ‘1’ to EXTRST asserts low the NRST pin during a time defined by the field
RSTC_MR.ERSTL.
The Software reset is entered if at least one of these bits is written to ‘1’ by the software. All these commands can be
performed independently or simultaneously. The Software reset lasts three MD_SLCK cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the Software reset has ended, i.e., synchronously to MD_SLCK.
If EXTRST is written to ‘1’, the nrst_out signal is asserted depending on the configuration of RSTC_MR.ERSTL.
However, the resulting falling edge on NRST does not lead to a User reset.
If and only if the RSTC_CR.PROCRST is written to ‘1’, the RSTC reports the software status in field
RSTC_SR.RSTTYP. Other software resets are not reported in RSTTYP.
As soon as a software operation is detected, RSTC_SR.SRCMP is written to ‘1’. SRCMP is cleared at the end of the
Software reset. No other Software reset can be performed while SRCMP=‘1’, and writing any value in the RSTC_CR
has no effect.
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Complete Datasheet
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SAM9X60
Reset Controller (RSTC)
Figure 16-6. Software Reset Timing Diagram
MD_SLCK
Up to 1 MD_SLCK cycle
Write RSTC_CR
Main RC
Oscillator
MCK
Any
Frequency.
Any
Frequency.
3 MD_SLCK cycles + 2 MCK cycles
RSTTYP
Processor and
Peripherals
Reset Line
XXX
Inactive
0x3 = Software Reset
Active
Inactive
Min = 2 MD_SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2)
NRST
(nrst_out)
if EXTRST=1
Inactive
Active
Inactive
RSTC_SR.SRCMP
16.4.3.6 User Reset
The User reset is entered when a low level is detected on the NRST pin and RSTC_MR.URSTEN =1. If
URSTASYNC=1, a falling edge of the NRST input signal immediately asserts internal reset lines. If URSTASYNC=0,
the NRST input signal is resynchronized and internal reset lines are asserted once a falling edge has been detected
on the resynchronized NRST input signal.
The Processor reset and the Peripheral reset are asserted.
The User reset is released when NRST rises, after a two-cycle resynchronization time and a 2-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the Processor reset signal is released, RSTC_SR.RSTTYP is loaded with the value 0x4, indicating a User
reset.
The NRST manager ensures that the NRST line is asserted as programmed in the field ERSTL. However, if NRST is
driven low externally, the internal reset lines remain asserted until NRST rises.
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Complete Datasheet
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SAM9X60
Reset Controller (RSTC)
Figure 16-7. User Reset State (URSTASYNC = '0')
MD_SLCK
2 MD_SLCK cycles
NRST pin
Main RC
Oscillator
Any
Frequency.
MCK
RSTTYP
Any
Frequency.
XXX
0x4 = User Reset
6 MD_SLCK cycles
Processor and
Peripherals
Reset Line
Inactive
Inactive
Active
Min = 2 MD_SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2)
NRST
(nrst_out)
Inactive
Active
Inactive
Figure 16-8. User Reset State (URSTASYNC = '1')
MD_SLCK
NRST pin
Main RC
Oscillator
MCK
Any
Frequency.
RSTTYP
Processor and
Peripherals
Reset Line
NRST
(nrst_out)
16.4.4
Any
Frequency.
XXX
0x4 = User Reset
6 MD_SLCK cycles
Inactive
Inactive
Active
Min = 2 MD_SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2)
Inactive
Active
Inactive
Reset State Priorities
The reset state manager manages the priorities among the different reset sources. The resets are listed in order of
priority as follows:
1.
2.
3.
4.
General reset
Backup reset
32.768 kHz Crystal Failure Detection reset
Watchdog reset
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Complete Datasheet
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SAM9X60
Reset Controller (RSTC)
5.
6.
Software reset
User reset
Specific cases are listed below:
•
•
•
When in User reset:
– A watchdog event is impossible because the WDT is being reset by the Processor reset signal.
– A Software reset is impossible, since the Processor reset is being activated.
When in Software reset:
– A watchdog event has priority over the current state.
– The NRST has no effect.
When in Watchdog reset:
– The Processor reset is active and so a Software reset cannot be programmed.
– A User reset cannot be entered.
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Complete Datasheet
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SAM9X60
Reset Controller (RSTC)
16.5
Register Summary
Offset
Name
0x00
RSTC_CR
0x04
0x08
RSTC_SR
RSTC_MR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
6
5
4
3
2
1
0
KEY[7:0]
EXTRST
PROCRST
SRCMP
RSTTYP[2:0]
NRSTL
URSTS
KEY[7:0]
ENGCLR
URSTIEN
Complete Datasheet
ERSTL[3:0]
URSTASYNC
SCKSW
URSTEN
DS60001579C-page 112
SAM9X60
Reset Controller (RSTC)
16.5.1
RSTC Control Register
Name:
Offset:
Reset:
Property:
Bit
31
RSTC_CR
0x00
–
Write-only
30
29
28
27
26
25
24
KEY[7:0]
Access
Reset
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
EXTRST
W
–
2
1
0
PROCRST
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:24 – KEY[7:0] System Reset Key
Value
Name
Description
0xA5
PASSWD
Writing any other value in this field aborts the write operation.
Bit 3 – EXTRST External Reset
Value
Description
0
No effect.
1
If KEY = 0xA5, asserts the NRST pin.
Bit 0 – PROCRST Processor Reset
Value
Description
0
No effect.
1
If KEY = 0xA5, resets the processor and all the embedded peripherals.
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Complete Datasheet
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SAM9X60
Reset Controller (RSTC)
16.5.2
RSTC Status Register
Name:
Offset:
Reset:
Property:
RSTC_SR
0x04
0x00000000
Read-only
The reset value assumes that a general reset has been performed, subject to change if other types of reset are
generated.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SRCMP
R
0
16
NRSTL
R
0
15
14
13
12
11
10
8
R
0
9
RSTTYP[2:0]
R
0
2
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
5
4
3
Access
Reset
R
0
0
URSTS
R
0
Bit 17 – SRCMP Software Reset Command in Progress
When set, this bit indicates that a software reset command is in progress and that no further software reset should be
performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
Value
Description
0
No software command is being performed by the RSTC. The RSTC is ready for a software command.
1
A software reset command is being performed by the RSTC. The RSTC is busy.
Bit 16 – NRSTL NRST Pin Level
Registers the NRST pin level sampled on each MCK rising edge.
Bits 10:8 – RSTTYP[2:0] Reset Type
This field reports the cause of the last processor reset. Reading RSTC_SR does not reset this field.
Value
Name
Description
0
GENERAL_RST
First power-up reset
1
BACKUP_RST
Return from Backup mode
2
WDT_RST
Watchdog fault occurred
3
SOFT_RST
Processor reset required by the software
4
USER_RST
NRST pin detected low
5
–
Reserved
6
–
Reserved
7
SLCK_XTAL_RST
32.768 kHz crystal failure detection fault occurred
Bit 0 – URSTS User Reset Status
A high-to-low transition of the NRST pin sets URSTS. This transition is also detected on the MCK rising edge. If the
user reset is disabled (RSTC_MR.URSTEN = 0) and if the interrupt is enabled by RSTC_MR.URSTIEN, URSTS
triggers an interrupt. Reading RSTC_SR resets URSTS and clears the interrupt.
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Complete Datasheet
DS60001579C-page 114
SAM9X60
Reset Controller (RSTC)
Value
0
1
Description
No high-to-low edge on NRST happened since the last read of RSTC_SR.
At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
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Complete Datasheet
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SAM9X60
Reset Controller (RSTC)
16.5.3
RSTC Mode Register
Name:
Offset:
Reset:
Property:
RSTC_MR
0x08
0x00000001
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
25
24
KEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
–
Bit
23
22
21
20
ENGCLR
R/W
0
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
ERSTL[3:0]
Access
Reset
Bit
7
6
5
Access
Reset
4
URSTIEN
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
URSTASYNC
R/W
0
1
SCKSW
R/W
0
0
URSTEN
R/W
1
Bits 31:24 – KEY[7:0] Write Access Password
Value
Name
Description
0xA5
PASSWD
Writing any other value in this field aborts the write operation.
Always reads as 0.
Bit 20 – ENGCLR Enable GPBR Clear on Tamper Event
Value
Description
0
Disables the GPBR immediate clear on tamper detection event.
1
Enables the GPBR immediate clear on tamper detection event
Bits 11:8 – ERSTL[3:0] External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) MD_SLCK
cycles. This allows assertion duration to be programmed between 60 μs and 2 seconds. Note that synchronization
cycles must also be considered when calculating the actual reset length as previously described.
Bit 4 – URSTIEN User Reset Interrupt Enable
Value
Description
0
RSTC_SR.USRTS at ‘1’ has no effect on the RSTC interrupt line.
1
RSTC_SR.USRTS at ‘1’ asserts the RSTC interrupt line if URSTEN = 0.
Bit 2 – URSTASYNC User Reset Asynchronous Control
See 16.4.2.1 NRST Signal or Interrupt for important information on the use of URSTASYNC.
Value
Description
0
The NRST input signal is managed synchronously.
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SAM9X60
Reset Controller (RSTC)
Value
1
Description
The NRST input signal is managed asynchronously.
Note: This mode cannot be selected if the external bus interface drives an SDR/DDR memory device
and another memory on the same bus.
Bit 1 – SCKSW Slow Clock Switching
Value
Description
0
The detection of a 32.768 kHz crystal failure has no effect.
1
The detection of a 32.768 kHz crystal failure resets the logic supplied by VDDCORE.
Bit 0 – URSTEN User Reset Enable
Value
Description
0
The detection of a low level on the NRST pin does not generate a user reset.
1
The detection of a low level on the NRST pin triggers a user reset.
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SAM9X60
Real-time Timer (RTT)
17.
Real-time Timer (RTT)
17.1
Description
The Real-time Timer (RTT) is built around a 32-bit counter used to count roll-over events of the programmable 16-bit
prescaler driven from the 32-kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a
programmed value.
The RTT can also be configured to be driven by the 1Hz RTC signal, thus taking advantage of a calibrated 1Hz clock.
The slow clock source can be fully disabled to reduce power consumption when only an elapsed seconds count is
required.
17.2
Embedded Characteristics
•
•
•
•
Block Diagram
Figure 17-1. RTT Block Diagram
RTT_MR
RTT_MR
RTT_MR
RTTDIS
RTTRST
RTPRES
RTT_MR
reload
16-bit
Prescaler
RTT
slow clock
RTTINCIEN
RTTRST
RTT_MR
1
RTT_SR
RTT_MR
RTC 1Hz
RTC1HZ
set
0
0
1
and
RTTINC
reset
0
rtt_int
32-bit
Counter
or
read
RTT_SR
RTT_MR
ALMIEN
RTT_VR
reset
CRTV
RTT_SR
and
ALMS
set
rtt_alarm
or
=
RTT_AR
ALMV
and
17.3
32-bit Free-running Counter on prescaled slow clock or RTC calibrated 1Hz clock
16-bit Configurable Prescaler
Interrupt on Alarm or Counter Increment
Programmable Event
RTT_MODR
SELINC2
RTT_MR
INC2AEN
CRTV
modulo N
=
set
‘0’
RTT_SR
read
RTT_SR
© 2020 Microchip Technology Inc.
(event to exit
system from
low-power
mode)
Complete Datasheet
RTTINC2
reset
DS60001579C-page 118
SAM9X60
Real-time Timer (RTT)
17.4
Functional Description
The programmable 16-bit prescaler value can be configured through the RTPRES field in the RTT Mode register
(RTT_MR).
Configuring the RTPRES field value to 0x8000 (default value) corresponds to feeding the real-time counter with a
1Hz signal (if the slow clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more
than 136 years, then roll over to 0. Bit RTTINC in the RTT Status Register (RTT_SR) is set each time there is a
prescaler roll-over (see the figure below).
The real-time 32-bit counter can also be supplied by the 1Hz RTC clock. This mode is interesting when the RTC 1Hz
is calibrated (CORRECTION field ≠ 0 in RTC_MR) in order to guaranty the synchronism between RTC and RTT
counters.
Setting the RTC1HZ bit in the RTT_MR drives the 32-bit RTT counter from the 1Hz RTC clock. In this mode, the
RTPRES field has no effect on the 32-bit counter.
The prescaler roll-over generates an increment of the real-time timer counter if RTC1HZ = 0. Otherwise, if RTC1HZ =
1, the RTT counter is incremented every second. The RTTINC bit is set independently from the 32-bit counter
increment.
The RTT can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing
RTPRES to 3 in RTT_MR.
Programming RTPRES to 1 or 2 is forbidden.
The CRTV field can be read at any time in the RTT Value register (RTT_VR). As this value can be updated
asynchronously with the Master Clock, the CRTV field must be read twice at the same value to read a correct value.
The current value of the counter is compared with the value written in the RTT Alarm register (RTT_AR). If the
counter value matches the alarm, the ALMS bit in the RTT_SR is set. The RTT_AR is set to its maximum value
(0xFFFFFFFF) after a reset.
The ALMS flag is always a source of the RTT alarm signal that may be used to exit the system from low power
modes (see the Real-time Timer Block Diagram above).
The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value in the
RTT_AR.
The RTTINC bit can be used to start a periodic interrupt, the period being one second when the RTPRES field value
= 0x8000 and the slow clock = 32.768 kHz.
The RTTINCIEN bit must be cleared prior to writing a new RTPRES value in the RTT_MR.
Reading the RTT_SR automatically clears the RTTINC and ALMS bits.
Writing the RTTRST bit in the RTT_MR immediately reloads and restarts the clock divider with the new programmed
value. This also resets the 32-bit counter.
When not used, the RTT can be disabled in order to suppress dynamic power consumption in this module. This can
be achieved by setting the RTTDIS bit in the RTT_MR.
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Complete Datasheet
DS60001579C-page 119
SAM9X60
Real-time Timer (RTT)
Figure 17-2. RTT Counting
RTT
Slow Clock
RTPRES - 1
Prescaler
0
CRTV
...
0
ALMV-1
ALMV
ALMV+1
ALMV+2
ALMV+3
RTTINC (RTT_SR)
ALMS (RTT_SR)
Bus Interface
APB cycle
read RTT_SR
APB cycle
The RTTINC2 flag is set when the number of prescaler roll-overs programmed through the SELINC2 field in the RTT
Modulo Selection register (RTT_MODR) has been reached since the last read of the RTT_SR.
For example, it is possible to generate 2 sources of interrupt of different periods with flags RTTINC and RTTINC2. If
the RTT slow clock frequency is 32.768 kHz and RTPRES=32, the RTTINC flag rises 1024 times per second (less
than 1 ms period). If the field SELINC2=5, the RTTINC2 flag rises once per second.
If RTTINC is defined as the unique source of interrupt (RTTINCEN=1, ALMIEN=0 and INC2AEN=0 in RTT_MR), the
value read in RTT_SR by the interrupt handler determines if the current interrupt event corresponds to a 1-second
event (RTT_SR[2:1]=3) or to a 1-millisecond event (RTT_SR[2:1]=1). See the figure below.
If the bit INC2AEN=1, RTTINC2 flag is also a source for the RTT alarm signal. See Figure 17-1.
Figure 17-3. RTTINC2 Behavior
RTT slow clock=32.768KHz, RTPRES=32, SELINC2=5
1 second
CRTV
RTTINC
(1s/1024=
~1ms tick)
1 second
L
L+1
~1 ms
~1 ms
L+2
N
M
M+1
M+2
M+3
~1 ms
RTTINC2
(1s flag)
RTT
interrupt line
Read RTT_SR
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 120
SAM9X60
Real-time Timer (RTT)
17.5
Register Summary
Offset
Name
0x00
RTT_MR
0x04
RTT_AR
0x08
RTT_VR
0x0C
RTT_SR
0x10
0x14
RTT_MODR
RTT_TSR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
6
5
INC2AEN
4
3
RTTDIS
RTPRES[15:8]
RTPRES[7:0]
ALMV[31:24]
ALMV[23:16]
ALMV[15:8]
ALMV[7:0]
CRTV[31:24]
CRTV[23:16]
CRTV[15:8]
CRTV[7:0]
2
1
0
RTTRST
RTTINCIEN
RTC1HZ
ALMIEN
RTTINC2
RTTINC
ALMS
SELINC2[2:0]
TSTAMP[23:16]
TSTAMP[15:8]
TSTAMP[7:0]
Complete Datasheet
DS60001579C-page 121
SAM9X60
Real-time Timer (RTT)
17.5.1
Real-time Timer Mode Register
Name:
Offset:
Reset:
Property:
RTT_MR
0x00
0x00008000
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
25
24
RTC1HZ
R/W
0
23
22
21
INC2AEN
R/W
0
20
RTTDIS
R/W
0
19
18
RTTRST
R/W
0
17
RTTINCIEN
R/W
0
16
ALMIEN
R/W
0
15
14
13
10
9
8
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
12
11
RTPRES[15:8]
R/W
R/W
0
0
4
3
RTPRES[7:0]
R/W
R/W
0
0
Bit 24 – RTC1HZ Real-Time Clock 1Hz Clock Selection
Value
Description
0
The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events.
1
The RTT 32-bit counter is driven by the 1Hz RTC clock.
Bit 21 – INC2AEN RTTINC2 Alarm and Interrupt Enable
Value
Description
0
The RTTINC2 flag is not a source of the RTT alarm signal nor a source of interrupt.
1
The RTTINC2 flag is a source of the RTT alarm signal and a source of interrupt.
Bit 20 – RTTDIS Real-time Timer Disable
Value
Description
0
The RTT is enabled.
1
The RTT is disabled (no dynamic power consumption).
Bit 18 – RTTRST Real-time Timer Restart
Value
Description
0
No effect.
1
Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit
counter.
Bit 17 – RTTINCIEN Real-time Timer Increment Interrupt Enable
Value
Description
0
The bit RTTINC in RTT_SR has no effect on interrupt.
1
The bit RTTINC in RTT_SR asserts interrupt.
Bit 16 – ALMIEN Alarm Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 122
SAM9X60
Real-time Timer (RTT)
Value
0
1
Description
The bit ALMS in RTT_SR has no effect on interrupt.
The bit ALMS in RTT_SR asserts interrupt.
Bits 15:0 – RTPRES[15:0] Real-time Timer Prescaler Value
Defines the number of RTT slow clock periods required to increment the Real-time timer. The RTTINCIEN bit must be
cleared prior to writing a new RTPRES value.
RTPRES is defined as follows:
• RTPRES = 0: The prescaler period is equal to 216 * slow clock periods.
• RTPRES = 1 or 2: forbidden.
• RTPRES ≠ 0, 1 or 2: The prescaler period is equal to RTPRES * slow clock periods.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 123
SAM9X60
Real-time Timer (RTT)
17.5.2
Real-time Timer Alarm Register
Name:
Offset:
Reset:
Property:
RTT_AR
0x04
0xFFFFFFFF
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register
(SYSC_WPMR).
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
28
27
ALMV[31:24]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
20
19
ALMV[23:16]
R/W
R/W
1
1
12
ALMV[15:8]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
ALMV[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 31:0 – ALMV[31:0] Alarm Value
When the CRTV value in RTT_VR equals the ALMV field, the ALMS flag is set in RTT_SR.
The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 124
SAM9X60
Real-time Timer (RTT)
17.5.3
Real-time Timer Value Register
Name:
Offset:
Reset:
Property:
Bit
31
RTT_VR
0x08
0x00000000
Read-only
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
CRTV[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
CRTV[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
CRTV[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
CRTV[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – CRTV[31:0] Current Real-time Value
Returns the current value of the RTT.
As CRTV can be updated asynchronously, it must be read twice at the same value.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 125
SAM9X60
Real-time Timer (RTT)
17.5.4
Real-time Timer Status Register
Name:
Offset:
Reset:
Property:
Bit
RTT_SR
0x0C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RTTINC2
R
0
1
RTTINC
R
0
0
ALMS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – RTTINC2 Predefined Number of Prescaler Roll-overs Status (cleared on read)
Value
Description
0
SELINC2 = 0 or the number of prescaler roll-overs programmed through the SELINC2 field in
RTT_MODR has not been reached since the last read of the RTT_SR.
1
The number of prescaler roll-overs programmed through the SELINC2 field has been reached since
the last read of the RTT_SR.
Bit 1 – RTTINC Prescaler Roll-over Status (cleared on read)
Value
Description
0
No prescaler roll-over occurred since the last read of the RTT_SR.
1
Prescaler roll-over occurred since the last read of the RTT_SR.
Bit 0 – ALMS Real-time Alarm Status (cleared on read)
Value
Description
0
The Real-time Alarm has not occurred since the last read of RTT_SR.
1
The Real-time Alarm occurred since the last read of RTT_SR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 126
SAM9X60
Real-time Timer (RTT)
17.5.5
Real-time Timer Modulo Selection Register
Name:
Offset:
Reset:
Property:
RTT_MODR
0x10
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SELINC2[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bits 2:0 – SELINC2[2:0] Selection of the 32-bit Counter Modulo to generate RTTINC2 Flag
Value
Name
Description
0
NO_RTTINC2 The RTTINC2 flag never rises.
1
MOD64
The RTTINC2 flag is set when CRTV modulo 64 equals 0.
2
MOD128
The RTTINC2 flag is set when CRTV modulo 128 equals 0.
3
MOD256
The RTTINC2 flag is set when CRTV modulo 256 equals 0.
4
MOD512
The RTTINC2 flag is set when CRTV modulo 512 equals 0.
5
MOD1024
The RTTINC2 flag is set when CRTV modulo 1024 equals 0.
Example: If RTPRES=32 then RTTINC2 flag rises once per second if the slow clock is
32.768 kHz.
6
MOD2048
The RTTINC2 flag is set when CRTV modulo 2048 equals 0.
7
MOD4096
The RTTINC2 flag is set when CRTV modulo 4096 equals 0.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 127
SAM9X60
Real-time Timer (RTT)
17.5.6
Real-time Timer Timestamp Register
Name:
Offset:
Reset:
Property:
Bit
RTT_TSR
0x14
0x00000000
Read-only
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
TSTAMP[23:16]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
TSTAMP[15:8]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
TSTAMP[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 23:0 – TSTAMP[23:0] Real-time Timer Value Timestamp
Each time an event triggers the flag RTT_SR.RTTINC2, RTT_VR.CRTV is copied into RTT_TSR.TSTAMP. The field
TSTAMP remains stable until next event RTT_SR.RTTINC2 and can be used for event timestamping.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 128
SAM9X60
Real-time Clock (RTC)
18.
Real-time Clock (RTC)
18.1
Description
The Real-time Clock (RTC) peripheral is designed for very low power consumption. For optimal functionality, the RTC
requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator.
It combines a complete time-of-day clock with alarm and a Gregorian or Persian calendar, complemented by a
programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus.
The RTC can also be configured for the UTC time format.
The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour
mode or 12-hour mode with an AM/PM indicator.
Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit
data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an
incompatible date according to the current month/year/century.
A clock divider calibration circuitry can be used to compensate for crystal oscillator frequency variations.
Timestamping capability reports the first and last occurrences of tamper events.
18.2
Embedded Characteristics
•
•
•
•
•
•
•
•
•
18.3
Full Asynchronous Design for Ultra Low-Power Consumption
Gregorian, UTC and Persian Modes Supported
Programmable Periodic Interrupt
Safety/Security Features:
– Valid time and date programming check
– On-the-fly time and date validity check
Counters Calibration Circuitry to Compensate for Crystal Oscillator Variations
Waveform Generation for Trigger Event
Tamper Control Registers and Detection Logic
Tamper Timestamping Registers
Register Write Protection
Block Diagram
Figure 18-1. RTC Block Diagram
Slow Clock
32768 Divider
Wave
Generator
Date
Time
Clock Calibration
System
Bus
User Interface
© 2020 Microchip Technology Inc.
Entry
Control
Alarm
Interrupt
Control
Complete Datasheet
RTCOUT0
(ADC AD[n:0] trigger)
RTCOUT1
(ADC AD[n] trigger)
Where n is the higher index
available (last channel)
RTC Interrupt
DS60001579C-page 129
SAM9X60
Real-time Clock (RTC)
18.4
Product Dependencies
18.4.1
Power Management
The Real-time Clock is continuously clocked at 32.768 kHz. The Power Management Controller (PMC) has no effect
on RTC behavior.
18.4.2
Interrupt
Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts.
Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller.
RTC interrupt requires the interrupt controller to be programmed first.
When a System Controller interrupt occurs, the service routine must first determine the cause of the interrupt. This is
done by reading each status register of the System Controller peripherals successively.
18.5
Functional Description
The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years),
month, date, day, hours, minutes and seconds reported in RTC Time Register (RTC_TIMR) and RTC Calendar
Register (RTC_CALR).
The RTC can operate in UTC mode, giving the number of seconds elapsed since a reference time defined by the
user (the UTC standard—ISO 8601—reference time is the 30th of June 1972). In this mode, the timefield is 32 bits
wide and coded in hexadecimal format.
The valid year range is up to 2099 in Gregorian mode (or 1300 to 1499 in Persian mode).
The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator.
Corrections for leap years are included (all years divisible by 4 being leap years except 1900). This is correct up to
the year 2099.
The RTC can generate events to trigger ADC measurements.
18.5.1
Reference Clock
The reference clock is the slow clock. It can be driven externally by a 32.768 kHz crystal, or internally.
18.5.2
Timing
In Gregorian and Persian modes, the RTC is updated in real time at one-second intervals in Normal mode for the
counters of seconds, at one-minute intervals for the counter of minutes and so on.
In UTC mode, the RTC is updated in real-time at one-second intervals (32-bit UTC counter default configuration).
Due to the asynchronous operation of the RTC with respect to the rest of the chip, to ensure that the value read in the
RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read
these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum
of three accesses are required.
18.5.3
Alarm
In Gregorian and Persian modes, the RTC has five programmable fields: month, date, hours, minutes and seconds.
Each of these fields can be enabled or disabled to match the alarm condition:
•
•
If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt
generated if enabled) at a given month, date, hour/minute/second.
If only the “seconds” field is enabled, then an alarm is generated every minute.
Depending on the fields that are enabled in the RTC Calendar Alarm register (RTC_CALALR) and the RTC Time
Alarm register(RTC_TIMALR), a large number of possibilities are available to the user ranging from minutes to
365/366 days.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 130
SAM9X60
Real-time Clock (RTC)
Note: To change one of the RTC_TIMALR.SEC, MIN, HOUR and/or RTC_CALALR.DATE, MONTH fields, it is
recommended to disable the field before changing the value and then re-enable it after the change has been made.
This requires up to three accesses to the RTC_TIMALR or RTC_CALALR. The first access clears the enable
corresponding to the field to change (RTC_TIMALR.SECEN, MINEN, HOUREN and/or RTC_CALALR.DATEEN,
MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the
value (RTC_TIMALR.SEC, MIN, HOUR and/or RTC_CALALR.DATE, MONTH). The third access is required to reenable the field by writing 1 in RTC_TIMALR.SECEN, MINEN, HOUREN and/or RTC_CALALR.DATEEN, MTHEN.
In UTC mode, RTC_TIMALR must be configured to set the UTC alarm value and bit 0 in RTC_CALALR must be used
to enable or disable the UTC alarm. If the UTC alarm is enabled, the alarm is generated once the UTC time matches
the programmed UTC_TIME alarm field.
To change the UTC_TIME alarm field, proceed as follows:
1.
2.
3.
18.5.4
Disable the UTC alarm by clearing RTC_CALALR.UTCEN if it is not already cleared.
Change the RTC_TIMALR.UTC_TIME alarm value.
Re-enable the UTC alarm by setting RTC_CALALR.UTCEN.
Error Checking when Programming
Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes,
seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the
year and century configured.
If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity
register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any
further side effects in the hardware. The same procedure is followed for the alarm.
The following checks are performed:
1.
2.
3.
4.
5.
6.
7.
8.
Century (check if it is in range 19–20 or 13–14 in Persian mode)
Year (BCD entry check)
Date (check range 01–31)
Month (check if it is in BCD range 01–12, check validity regarding “date”)
Day (check range 1–7)
Hour (BCD checks: in 24-hour mode, check range 00–23 and check that AM/PM flag is not set if RTC is set in
24-hour mode; in 12-hour mode check range 01–12)
Minute (check BCD and range 00–59)
Second (check BCD and range 00–59)
Notes:
1. If the 12-hour mode is selected by means of the Mode register (RTC_MR), a 12-hour value can be
programmed and the returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control
checks the value of the AM/PM indicator (bit 22 of RTC_TIMR) to determine the range to be checked.
2. In UTC mode, no check is performed on the entries. The RTC does not report any failure.
18.5.5
RTC Internal Free-Running Counter Error Checking
To improve the reliability and security of the RTC, a permanent check is performed on the internal free-running
counters to report non-BCD or invalid date/time values.
An error is reported by RTC_SR.TDERR if an incorrect value has been detected. The flag can be cleared by setting
the RTC_SCCR.TDERRCLR.
In all cases, RTC_SR.TDERR is set again if the source of the error has not been cleared before clearing
RTC_SR.TDERR. The clearing of the source of such error can be done by reprogramming a correct value on
RTC_CALR and/or RTC_TIMR.
The RTC internal free-running counters may automatically clear the source of RTC_SR.TDERR due to their roll-over
(i.e., every 10 seconds for SECONDS[3:0] in RTC_TIMR). In this case, RTC_SR.TDERR is held high until a clear
command is asserted by writing a 1 in RTC_SCCR.TDERRCLR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 131
SAM9X60
Real-time Clock (RTC)
18.5.6
Updating Time/Calendar
18.5.6.1 Gregorian and Persian Modes
To update time and date, the RTC must be stopped by setting the corresponding field in the Control register
(RTC_CR). RTC_CR.UPDTIM must be set to update time fields (hour, minute, second) and RTC_CR.UPDCAL must
be set to update calendar fields (century, year, month, date, day).
RTC_SR.ACKUPD must then be read to 1 by either polling RTC_SR or by enabling the acknowledge update interrupt
by writing RTC_IER.ACKUPD to ‘1’. Once RTC_SR.ACKUPD is read to 1, it is mandatory to clear this flag by writing
a 1 in RTC_SCCR.ACKCLR, after which the user can write to the Time register (RTC_TIMR), the Calendar register
(RTC_CALR), or both.
Once the update is finished, the user must write a ‘0’ in RTC_CR.UPDTIM and/or RTC_CR.UPDCAL.
The timing sequence of the time/calendar update is described in the figure below.
When entering the Programming mode of the calendar fields, the time fields remain enabled. When entering the
Programming mode of the time fields, both the time and the calendar fields are stopped. This is due to the location of
the calendar logical circuity (downstream for low-power considerations).
In successive update operations, the user must first check that RTC_CR.UPDTIM and RTC_CR.UPDCAL read 0
before writing these bits to ‘1’.
Figure 18-2. Time/Calendar Update Timing Diagram
//
1 Hz RTC Clock
RTC_TIMR.SEC
Software
Time Line
20
Update request
from SW
RTC_CR.UPDTIM
1
2
//
//
//
3
16
Clear
UPDTIM bit
RTC BACK TO
NORMAL MODE
4
Update
RTC_TIMR.SEC to 15
RTC_SR.ACKUPD
© 2020 Microchip Technology Inc.
//
15
(counter stopped)
Clear
ACKUPD bit
//
Complete Datasheet
//
//
//
//
DS60001579C-page 132
SAM9X60
Real-time Clock (RTC)
Figure 18-3. Gregorian and Persian Modes Update Sequence
Begin
Prepare Time or Calendar Fields
Set RTC_CR.UPDTIM and/or
RTC_CR.UPDCAL
Read RTC_SR
Polling or
Interrupt
(if enabled)
ACKUPD
= 1?
No
Yes
Clear RTC_SR.ACKUPD by
writing a ‘1’ to RTC_SCCR.ACKCLR
Update Time and/or Calendar values in
RTC_TIMR/RTC_CALR
Clear RTC_CR.UPDTIM and/or
RTC_CR.UPDCAL
End
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 133
SAM9X60
Real-time Clock (RTC)
18.5.6.2 UTC Mode
To update the UTC time, the RTC must be stopped by writing a 1 in RTC_CR.UPDTIM and RTC_CR.UPDCAL.
RTC_SR.ACKUPD must then be read to 1 by either polling RTC_SR or by enabling the acknowledge update interrupt
by writing a 1 in RTC_IER.ACKUP. Once RTC_SR.ACKUPD is read to 1, it is mandatory to clear this flag by writing a
1 in RTC_SCCR.ACKCLR, after which the user can write to RTC_TIMR.
Once the update is finished, the user must write a 0 in RTC_CR.UPDTIM and a 0 in RTC_CR.UPCAL.
In successive update operations, the user must first check that RTC_CR.UPDTIM and RTC_CR.UPDCAL read 0
before writing a 1 in these bits.
The timing sequence of the UTC time update is described in the figure below.
Figure 18-4. UTC Time Update Timing Diagram
General Time Update
//
1 Hz RTC Clock
RTC_TIMR.UTC_TIME
Software
Time Line
20
Update request
from SW
RTC_CR.UPDTIM
RTC_CR.UPDCAL
1
2
//
//
//
3
16
Clear
UPDTIM/UPDCAL bits
RTC BACK TO
NORMAL MODE
4
Update
RTC_TIMR.UTC_TIME to 15
RTC_SR.ACKUPD
© 2020 Microchip Technology Inc.
//
15
(counter stopped)
Clear
ACKUPD bit
//
Complete Datasheet
//
//
//
//
DS60001579C-page 134
SAM9X60
Real-time Clock (RTC)
Figure 18-5. UTC Mode Update Sequence
Begin
Prepare Time Field
Set RTC_CR.UPDTIM and
RTC_CR.UPDCAL
Read RTC_SR
Polling or
Interrupt
(if enabled)
No
ACKUPD
= 1?
Yes
Clear RTC_SR.ACKUPD by
writing a ‘1’ to RTC_SCCR.ACKCLR
Update Time value in
RTC_TIMR
Clear RTC_CR.UPDTIM and
RTC_CR/UPDCAL
End
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 135
SAM9X60
Real-time Clock (RTC)
RTC Accurate Clock Calibration
The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation.
The RTC is equipped with circuitry able to correct slow clock crystal drift.
To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be
programmed on-the-fly and also programmed during application manufacturing, in order to correct the crystal
frequency accuracy at room temperature (20–25°C). The typical clock drift range at room temperature is ±20 ppm.
In the device operating temperature range, the 32.768 kHz crystal oscillator clock inaccuracy can be up to -200 ppm.
The RTC clock calibration circuitry allows positive or negative correction in a range of 1.5 ppm to 1950 ppm.
The calibration circuitry is fully digital. Thus, the configured correction is independent of temperature, voltage,
process, etc., and no additional measurement is required to check that the correction is effective.
If the correction value configured in the calibration circuitry results from an accurate crystal frequency measure, the
remaining accuracy is bounded by the values listed below:
•
•
•
Below 1 ppm, for an initial crystal drift between 1.5 ppm up to 20 ppm, and from 30 ppm to 90 ppm
Below 2 ppm, for an initial crystal drift between 20 ppm up to 30 ppm, and from 90 ppm to 130 ppm
Below 5 ppm, for an initial crystal drift between 130 ppm up to 200 ppm
The calibration circuitry does not modify the 32.768 kHz crystal oscillator clock frequency but it acts by slightly
modifying the 1 Hz clock period from time to time. The correction event occurs every 1 + [(20 - (19 x HIGHPPM)) x
CORRECTION] seconds. When the period is modified, depending on the sign of the correction, the 1 Hz clock period
increases or reduces by around 4 ms. Depending on the CORRECTION, NEGPPM and HIGHPPM values configured
in RTC_MR, the period interval between two correction events differs.
Figure 18-6. Calibration Circuitry
RTC
Divider by 32768
32.768 kHz
Add
Oscillator
18.5.7
32.768 kHz
1Hz
Time/Calendar
Suppress
Integrator
Comparator
CORRECTION, HIGHPPM
NEGPPM
Other Logic
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 136
SAM9X60
Real-time Clock (RTC)
Figure 18-7. Calibration Circuitry Waveforms
Monotonic 1 Hz
Counter value
32.768 kHz +50 ppm
Phase adjustment
(~4 ms)
Nominal 32.768 kHz
32.768 kHz -50 ppm
-25 ppm
Crystal frequency
remains unadjusted
-50 ppm
Internal 1 Hz clock
is adjusted
Time
User configurable period
(integer multiple of 1s or 20s)
Time
-50 ppm correction period
-25 ppm correction period
POSITIVE CORRECTION
NEGATIVE CORRECTION
Crystal clock
Internally divided clock (256 Hz)
Clock pulse periodically suppressed
when correction period elapses
Internally divided clock (128 Hz)
1.000 second
128 Hz clock edge delayed by 3.906 ms
when correction period elapses
1.003906 second
Internally divided clock (256 Hz)
Clock edge periodically added
when correction period elapses
Internally divided clock (128 Hz)
Internally divided clock (64 Hz)
128 Hz clock edge delayed by 3.906 ms
when correction period elapses
0.996094 second
1.000 second
dashed lines = no correction
The inaccuracy of a crystal oscillator at typical room temperature (±20 ppm at 20–25 °C) can be compensated if a
reference clock/signal is used to measure such inaccuracy. This kind of calibration operation can be set up during the
final product manufacturing by means of measurement equipment embedding such a reference clock. The correction
of value must be programmed into RTC_MR, and this value is kept as long as the circuitry is powered (backup area).
Removing the backup power supply cancels this calibration. This room temperature calibration can be further
processed by means of the networking capability of the target application.
Note that this adjustment does not take into account the temperature variation.
The frequency drift (up to -200 ppm) due to temperature variation can be compensated using a reference time if the
application can access such a reference. If a reference time cannot be used, a temperature sensor can be placed
close to the crystal oscillator in order to get the operating temperature of the crystal oscillator. Once obtained, the
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 137
SAM9X60
Real-time Clock (RTC)
temperature may be converted using a lookup table (describing the accuracy/temperature curve of the crystal
oscillator used) and RTC_MR configured accordingly. The calibration can be performed on-the-fly. This adjustment
method is not based on a measurement of the crystal frequency/drift and therefore can be improved by means of the
networking capability of the target application.
If no crystal frequency adjustment has been done during manufacturing, it is still possible to make adjustments. In the
case where a reference time of the day can be obtained through a LAN/WAN network, it is possible to calculate the
drift of the application crystal oscillator by comparing the values read on RTC_TIMR and RTC_CALR and
programming RTC_MR.HIGHPPM and RTC_MR.CORRECTION according to the difference measured between the
reference time and those of RTC_TIMR and RTC_CALR.
18.5.8
Waveform Generation
Waveforms can be generated in order to take advantage of the RTC inherent prescalers while the RTC is the only
powered circuitry (Low-power mode of operation, Backup mode) or in any active mode. Entering Backup or Lowpower operating modes does not affect the waveform generation outputs.
The RTC waveforms are internally routed to ADC trigger events. These events can be configured to provide several
types of waveforms. The figure below illustrates the different signals available to generate the waveforms. Two
different triggers can be generated at a time. The first is configured in RTC_MR.OUT0 while the second is
configurable in RTC_MR.OUT1. OUT0 manages the trigger for channel AD[n:0] (where n is the higher index available
(last channel)), while OUT1 manages the channel AD[n] only for specific modes. See the section "Analog to Digital
Converter (ADC)" for selection of the measurement triggers and associated modes of operation.
The first selection choice sticks the associated output at 0. (This is the reset value and it can be used at any time to
disable the waveform generation).
Selection choices 1 to 4 respectively select 1 Hz, 32 Hz, 64 Hz and 512 Hz.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 138
SAM9X60
Real-time Clock (RTC)
Figure 18-8. Waveform Generation for ADC Trigger Event
‘0’
0
‘0’
0
1 Hz
1
1 Hz
1
32 Hz
2
32 Hz
2
64 Hz
3
64 Hz
3
512 Hz
4
512 Hz
4
toggle_alarm
5
toggle_alarm
5
flag_alarm
6
flag_alarm
6
pulse
7
pulse
7
To ADC trigger
event for
all channels
RTC_MR(OUT0)
To ADC trigger
event for AD[n]
n = higher index
available
RTC_MR(OUT1)
alarm match
event 2
alarm match
event 1
flag_alarm
RTC_SCCR.ALRCLR
RTC_SCCR.ALRCLR
toggle_alarm
pulse
Thigh
Tperiod
Tperiod
18.5.9
Tamper Control Registers and Detection Logic
The WKUP pins used for fast wakeup in PMC are also routed to the tamper detection logic. Any WKUP pin which is
not already configured as source of fast wakeup can be configured and selected as a source of a tamper event.
The tamper event can be used to immediately clear (no peripheral clock required) the content of the GPBR, clear the
keys stored in AES/TDES, clear the scrambling keys of QSPI/SDR/DDR/SMC memory controllers. Each of these
peripherals embeds a configuration bit to allow/disallow the clear on tamper event.
The polarity of each of the WKUP pins can be configured.
Each of the WKUP pins are debounced prior to create the tamper event.
The tamper event is asserted when one of the lines matches the configured polarity after the debouncing period (see
the figure below).
The WKUP pins routed to tamper detection logic are all located on VDDCORE domain, thus there is no tamper
detection event when the product is in Backup mode.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 139
SAM9X60
Real-time Clock (RTC)
Figure 18-9. Tamper Detection Circuitry
RTC_TDPR.PERA
RTC_TDPR.PERB
RTC_TDPR.SELP0
WKUP1
RTC_TMR.EN0
period
Debouncer 0
RTC_TMR.POL0
VDDCORE
MD_SLCK
Tamper
Event
RTC_TDPR.PERA
RTC_TDPR.PERB
OR
RTC_TDPR.SELPx
WKUPx
RTC_TMR.ENx
RTC_TMR.POLx
period
Debouncer X
MD_SLCK
To enable WKUPx pin to be a source of tamper event, not already configured for a fast wakeup (refer to PMC
configuration), the bit RTC_TMR.ENx must be written to 1.
The polarity of the WKUPx pin is configured in RTC_TMR.POLx.
Two debounce periods can be defined by configuring the fields RTC_TDPR.PERA and RTC_TDPR.PERB.
For each WKPUPx pin, the debounce period can be selected from either RTC_TDPR.PERA or RTC_TDPR.PERB by
configuring the bit RTC_TDPR.SELPx.
For safety/security reasons, it is possible to lock the tamper configuration registers by writing RTC_TMR.TLOCK=1.
Once written to 1, the only way to clear this bit is to perform a VDDCORE reset.
18.5.10 Tamper Timestamping
As soon as a tamper is detected, the tamper counter is incremented and the RTC stores the time of the day, the date
and the source of the tamper event in registers located in the backup area. Up to two tamper events can be stored.
In UTC mode, only the UTC time is stored. The date information is not relevant.
The tamper counter saturates at 15. Once this limit is reached, the exact number of tamper occurrences since the
last read of stamping registers cannot be known.
The first set of timestamping registers (RTC_TSTR0, RTC_TSDR0, RTC_TSSR0) cannot be overwritten. Once they
have been written, all data are stored until the registers are reset. Thus these registers store the first tamper
occurrence after a read.
The second set of timestamping registers (RTC_TSTR1, RTC_TSDR1, RTC_TSSR1) are overwritten each time a
tamper event is detected. Thus the date and the time data of the first and the second stamping registers may be
equal. This occurs when the tamper counter value carried on RTC_TSTR0.TEVCNT equals 1. Thus this second set
of registers stores the last occurrence of tamper before a read.
Reading a set of timestamping registers requires three accesses, one for the time of the day, one for the date and
one for the tamper source.
Reading the third part (RTC_TSSR0/1) of a timestamping register set clears the whole content of the registers (time,
date and tamper source) and makes the timestamping registers available to store a new event.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 140
SAM9X60
Real-time Clock (RTC)
18.6
Register Summary
Offset
Name
0x00
RTC_CR
0x04
RTC_MR
0x08
RTC_TIMR
0x08
RTC_TIMR
(UTC_MODE)
0x0C
RTC_CALR
0x10
RTC_TIMALR
0x10
RTC_TIMALR
(UTC_MODE)
0x14
RTC_CALALR
0x14
RTC_CALALR
(UTC_MODE)
0x18
0x1C
0x20
0x24
0x28
RTC_SR
RTC_SCCR
RTC_IER
RTC_IDR
RTC_IMR
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
5
4
3
2
CORRECTION[6:0]
NEGPPM
AMPM
AMPM
PERSIAN
HRMOD
HOUR[5:0]
MIN[6:0]
SEC[6:0]
UTC_TIME[31:24]
UTC_TIME[23:16]
UTC_TIME[15:8]
UTC_TIME[7:0]
DATE[5:0]
MONTH[4:0]
DATEEN
MTHEN
© 2020 Microchip Technology Inc.
UTC
HOUR[5:0]
MIN[6:0]
SEC[6:0]
UTC_TIME[31:24]
UTC_TIME[23:16]
UTC_TIME[15:8]
UTC_TIME[7:0]
DATE[5:0]
MONTH[4:0]
YEAR[7:0]
CENT[6:0]
DAY[2:0]
HOUREN
MINEN
SECEN
0
CALEVSEL[1:0]
TIMEVSEL[1:0]
UPDCAL
UPDTIM
THIGH[2:0]
OUT0[2:0]
TPERIOD[1:0]
OUT1[2:0]
HIGHPPM
1
UTCEN
TDERR
CALEV
TIMEV
SEC
ALARM
ACKUPD
TDERRCLR
CALCLR
TIMCLR
SECCLR
ALRCLR
ACKCLR
TDERREN
CALEN
TIMEN
SECEN
ALREN
ACKEN
TDERRDIS
CALDIS
TIMDIS
SECDIS
ALRDIS
ACKDIS
TDERR
CAL
TIM
SEC
ALR
ACK
Complete Datasheet
DS60001579C-page 141
SAM9X60
Real-time Clock (RTC)
...........continued
Offset
Name
0x2C
RTC_VER
0x30
...
0x57
0x58
0x5C
0x60
...
0xAF
Bit Pos.
7
6
5
4
3
2
1
0
NVCALALR
NVTIMALR
NVCAL
NVTIM
31:24
23:16
15:8
7:0
Reserved
RTC_TMR
RTC_TDPR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
TRLOCK
POL7
POL6
POL5
POL4
POL3
POL2
POL1
POL0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
SELP7
SELP6
SELP5
SELP4
SELP3
SELP2
SELP1
SELP0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
BACKUP
PERB[3:0]
PERA[3:0]
Reserved
0xB0
RTC_TSTR0
0xB0
RTC_TSTR0
(UTC_MODE)
0xB4
RTC_TSDR0
0xB4
RTC_TSDRx
(UTC_MODE)
0xB8
RTC_TSSR0
0xBC
RTC_TSTR1
0xBC
RTC_TSTR1
(UTC_MODE)
0xC0
RTC_TSDR1
0xC4
RTC_TSSR1
TEVCNT[3:0]
AMPM
HOUR[5:0]
MIN[6:0]
SEC[6:0]
BACKUP
TEVCNT[3:0]
DATE[5:0]
MONTH[4:0]
DAY[2:0]
YEAR[7:0]
CENT[6:0]
UTC_TIME[31:24]
UTC_TIME[23:16]
UTC_TIME[15:8]
UTC_TIME[7:0]
DET7
DET6
DET5
DET4
DET3
DET2
DET1
DET0
DET1
DET0
BACKUP
AMPM
HOUR[5:0]
MIN[6:0]
SEC[6:0]
BACKUP
DATE[5:0]
MONTH[4:0]
DAY[2:0]
YEAR[7:0]
CENT[6:0]
DET7
© 2020 Microchip Technology Inc.
DET6
DET5
DET4
Complete Datasheet
DET3
DET2
DS60001579C-page 142
SAM9X60
Real-time Clock (RTC)
18.6.1
RTC Control Register
Name:
Offset:
Reset:
Property:
RTC_CR
0x00
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CALEVSEL[1:0]
R/W
R/W
0
0
15
14
13
12
11
10
9
8
TIMEVSEL[1:0]
R/W
R/W
0
0
7
6
5
4
3
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
UPDCAL
R/W
0
0
UPDTIM
R/W
0
Bits 17:16 – CALEVSEL[1:0] Calendar Event Selection
The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL
In UTC mode, this field has no effect on RTC_SR.
Value
Name
Description
0
WEEK
Week change (every Monday at time 00:00:00)
1
MONTH
Month change (every 01 of each month at time 00:00:00)
2
YEAR
Year change (every January 1 at time 00:00:00)
3
YEAR
Reserved
Bits 9:8 – TIMEVSEL[1:0] Time Event Selection
The event that generates the flag TIMEV in RTC_SR depends on the value of TIMEVSEL.
In UTC mode, this field has no effect on RTC_SR.
Value
Name
Description
0
MINUTE
Minute change
1
HOUR
Hour change
2
MIDNIGHT
Every day at midnight
3
NOON
Every day at noon
Bit 1 – UPDCAL Update Request Calendar Register
Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed
once this bit is set and acknowledged by the RTC_SR.ACKUPD bit.
In UTC mode, both UPDTIM and UPDCAL must be set to '1' in order to update the UTC time value.
Value
Description
0
No effect or, if UPDCAL has been previously written to 1, stops the update procedure.
1
Stops the RTC calendar counting.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 143
SAM9X60
Real-time Clock (RTC)
Bit 0 – UPDTIM Update Request Time Register
Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set
and acknowledged by the RTC_SR.ACKUPD bit.
In UTC mode, both UPDTIM and UPDCAL must be set to '1' in order to update the UTC time value.
Value
Description
0
No effect or, if UPDTIM has been previously written to 1, stops the update procedure.
1
Stops the RTC time counting.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 144
SAM9X60
Real-time Clock (RTC)
18.6.2
RTC Mode Register
Name:
Offset:
Reset:
Property:
RTC_MR
0x04
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
Bit
31
30
Access
Reset
Bit
23
Access
Reset
Bit
Access
Reset
Bit
22
29
28
TPERIOD[1:0]
R/W
R/W
0
0
R/W
0
21
OUT1[2:0]
R/W
0
20
R/W
0
15
HIGHPPM
R/W
0
14
13
12
R/W
0
R/W
0
R/W
0
7
6
5
4
NEGPPM
R/W
0
Access
Reset
Bits 29:28 – TPERIOD[1:0] Period of the Output Pulse
Value
Name
0
P_1S
1
P_500MS
2
P_250MS
3
P_125MS
27
26
R/W
0
19
11
CORRECTION[6:0]
R/W
0
3
18
25
THIGH[2:0]
R/W
0
24
R/W
0
R/W
0
17
OUT0[2:0]
R/W
0
16
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
UTC
R/W
0
1
PERSIAN
R/W
0
0
HRMOD
R/W
0
Description
1 second
500 ms
250 ms
125 ms
Bits 26:24 – THIGH[2:0] High Duration of the Output Pulse
Value
Name
Description
0
H_31MS
31.2 ms
1
H_16MS
15.6 ms
2
H_4MS
3.91 ms
3
H_976US
976 μs
4
H_488US
488 μs
5
H_122US
122 μs
6
H_30US
30.5 μs
7
H_15US
15.2 μs
Bits 22:20 – OUT1[2:0] ADC Last Channel Trigger Event Source Selection
Value
Name
Description
0
NO_WAVE
No waveform, stuck at ‘0’
1
FREQ1HZ
1 Hz square wave
2
FREQ32HZ
32 Hz square wave
3
FREQ64HZ
64 Hz square wave
4
FREQ512HZ
512 Hz square wave
5
ALARM_TOGGLE
Output toggles when alarm flag rises
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SAM9X60
Real-time Clock (RTC)
Value
6
7
Name
ALARM_FLAG
PROG_PULSE
Description
Output is a copy of the alarm flag
Duty cycle programmable pulse
Bits 18:16 – OUT0[2:0] All ADC Channel Trigger Event Source Selection
Value
Name
Description
0
NO_WAVE
No waveform, stuck at ‘0’
1
FREQ1HZ
1 Hz square wave
2
FREQ32HZ
32 Hz square wave
3
FREQ64HZ
64 Hz square wave
4
FREQ512HZ
512 Hz square wave
5
ALARM_TOGGLE
Output toggles when alarm flag rises
6
ALARM_FLAG
Output is a copy of the alarm flag
7
PROG_PULSE
Duty cycle programmable pulse
Bit 15 – HIGHPPM HIGH PPM Correction
If the absolute value of the correction to be applied is lower than 30 ppm, it is recommended to clear HIGHPPM.
HIGHPPM set to 1 is recommended for 30 ppm correction and above.
Formula:
If HIGHPPM = 0, then the clock frequency correction range is from 1.5 ppm up to 98 ppm. The RTC accuracy is less
than 1 ppm for a range correction from 1.5 ppm up to 30 ppm.
The correction field must be programmed according to the required correction in ppm; the formula is as follows:
3906
CORRECTION =
−1
20 × ppm
The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field.
If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is
less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm.
The correction field must be programmed according to the required correction in ppm; the formula is as follows:
3906
CORRECTION =
−1
ppm
The value obtained must be rounded to the nearest integer prior to be programmed into CORRECTION field.
If NEGPPM is set to 1, the ppm correction is negative (used to correct crystals that are faster than the nominal
32.768 kHz).
Value
Description
0
Lower range ppm correction with accurate correction.
1
Higher range ppm correction with accurate correction.
Bits 14:8 – CORRECTION[6:0] Slow Clock Correction
Value
Description
0
No correction
1–127
The slow clock will be corrected according to the formula given in HIGHPPM description.
Bit 4 – NEGPPM Negative PPM Correction
See CORRECTION and HIGHPPM field descriptions.
NEGPPM must be cleared to correct a crystal slower than 32.768 kHz.
Value
Description
0
Positive correction (the divider will be slightly higher than 32768).
1
Negative correction (the divider will be slightly lower than 32768).
Bit 2 – UTC UTC Time Format
It is forbidden to write a one to the UTC and PERSIAN bits at the same time.
Value
Description
0
Gregorian or Persian calendar.
1
UTC format.
Bit 1 – PERSIAN PERSIAN Calendar
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SAM9X60
Real-time Clock (RTC)
Value
0
1
Description
Gregorian calendar.
Persian calendar.
Bit 0 – HRMOD 12-/24-hour Mode
Value
Description
0
24-hour mode is selected.
1
12-hour mode is selected.
© 2020 Microchip Technology Inc.
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SAM9X60
Real-time Clock (RTC)
18.6.3
RTC Time Register
Name:
Offset:
Reset:
Property:
RTC_TIMR
0x08
0x00000000
Read/Write
In UTC mode, this register view is not relevant, see 18.6.7 RTC_TIMALR (UTC_MODE) .
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
25
24
23
22
AMPM
R/W
0
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14
13
12
11
MIN[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
HOUR[5:0]
3
SEC[6:0]
R/W
0
Bit 22 – AMPM Ante Meridiem Post Meridiem Indicator
This bit is the AM/PM indicator in 12-hour mode.
Value
Description
0
AM.
1
PM.
Bits 21:16 – HOUR[5:0] Current Hour
The range that can be set is 1–12 (BCD) in 12-hour mode or 0–23 (BCD) in 24-hour mode.
Bits 14:8 – MIN[6:0] Current Minute
The range that can be set is 0–59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
Bits 6:0 – SEC[6:0] Current Second
The range that can be set is 0–59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
© 2020 Microchip Technology Inc.
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SAM9X60
Real-time Clock (RTC)
18.6.4
RTC Time Register (UTC_MODE)
Name:
Offset:
Reset:
Property:
RTC_TIMR (UTC_MODE)
0x08
0x00000000
Read/Write
This configuration is relevant only if UTC = 1 in RTC_MR.
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
UTC_TIME[31:24]
R/W
R/W
0
0
20
19
UTC_TIME[23:16]
R/W
R/W
0
0
12
11
UTC_TIME[15:8]
R/W
R/W
0
0
4
3
UTC_TIME[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – UTC_TIME[31:0] Current UTC Time
Any value can be set.
© 2020 Microchip Technology Inc.
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SAM9X60
Real-time Clock (RTC)
18.6.5
RTC Calendar Register
Name:
Offset:
Reset:
Property:
RTC_CALR
0x0C
0x01411720
Read/Write
In UTC mode, values read in this register are not relevant.
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
25
24
DATE[5:0]
Access
Reset
Bit
Access
Reset
Bit
23
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
17
16
R/W
0
R/W
1
21
20
19
R/W
0
22
DAY[2:0]
R/W
1
R/W
0
R/W
0
R/W
0
18
MONTH[4:0]
R/W
0
15
14
13
12
11
10
9
8
YEAR[7:0]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
7
6
5
4
2
1
0
R/W
0
R/W
1
R/W
0
3
CENT[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
Bits 29:24 – DATE[5:0] Current Day in Current Month
The range that can be set is 01–31 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
Bits 23:21 – DAY[2:0] Current Day in Current Week
The range that can be set is 1–7 (BCD).
The coding of the number (which number represents which day) is user-defined as it has no effect on the date
counter.
Bits 20:16 – MONTH[4:0] Current Month
The range that can be set is 01–12 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
Bits 15:8 – YEAR[7:0] Current Year
The range that can be set is 00–99 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
Bits 6:0 – CENT[6:0] Current Century
The range that can be set is 19–20 (Gregorian) or 13–14 (Persian) (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Real-time Clock (RTC)
18.6.6
RTC Time Alarm Register
Name:
Offset:
Reset:
Property:
RTC_TIMALR
0x10
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and
then re-enable it after the change has been made. This requires up to three accesses to RTC_TIMALR. The first
access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN). If the field is already
cleared, this access is not required. The second access performs the change of value (SEC, MIN, HOUR). The third
access is required to re-enable the field by writing 1 in the SECEN, MINEN, HOUREN fields.
Bit
31
30
29
28
27
26
25
24
23
HOUREN
R/W
0
22
AMPM
R/W
0
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
MINEN
R/W
0
14
13
12
11
MIN[6:0]
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
SECEN
R/W
0
HOUR[5:0]
3
SEC[6:0]
R/W
0
Bit 23 – HOUREN Hour Alarm Enable
Value
Description
0
The hour-matching alarm is disabled.
1
The hour-matching alarm is enabled.
Bit 22 – AMPM AM/PM Indicator
This field is the alarm field corresponding to the BCD-coded hour counter.
Bits 21:16 – HOUR[5:0] Hour Alarm
This field is the alarm field corresponding to the BCD-coded hour counter.
Bit 15 – MINEN Minute Alarm Enable
Value
Description
0
The minute-matching alarm is disabled.
1
The minute-matching alarm is enabled.
Bits 14:8 – MIN[6:0] Minute Alarm
This field is the alarm field corresponding to the BCD-coded minute counter.
Bit 7 – SECEN Second Alarm Enable
© 2020 Microchip Technology Inc.
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SAM9X60
Real-time Clock (RTC)
Value
0
1
Description
The second-matching alarm is disabled.
The second-matching alarm is enabled.
Bits 6:0 – SEC[6:0] Second Alarm
This field is the alarm field corresponding to the BCD-coded second counter.
© 2020 Microchip Technology Inc.
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SAM9X60
Real-time Clock (RTC)
18.6.7
RTC Time Alarm Register (UTC_MODE)
Name:
Offset:
Reset:
Property:
RTC_TIMALR (UTC_MODE)
0x10
0x00000000
Read/Write
This configuration is relevant only if UTC = 1 in RTC_MR.
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
UTC_TIME[31:24]
R/W
R/W
0
0
20
19
UTC_TIME[23:16]
R/W
R/W
0
0
12
11
UTC_TIME[15:8]
R/W
R/W
0
0
4
3
UTC_TIME[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – UTC_TIME[31:0] UTC_TIME Alarm
This field is the alarm field corresponding to the UTC time counter. To change it, proceed as follows:
1. Disable the UTC alarm by clearing RTC_CALALR.UTCEN if it is not already cleared.
2. Change the UTC_TIME alarm value.
3. Enable the UTC alarm by setting RTC_CALALR.UTCEN.
© 2020 Microchip Technology Inc.
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SAM9X60
Real-time Clock (RTC)
18.6.8
RTC Calendar Alarm Register
Name:
Offset:
Reset:
Property:
RTC_CALALR
0x14
0x01010000
Read/Write
In UTC mode, this register view is not relevant, see 18.6.9 RTC_CALALR (UTC_MODE).
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and
then re-enable it after the change has been made. This requires up to three accesses to RTC_CALALR. The first
access clears the enable corresponding to the field to change (DATEEN, MTHEN). If the field is already cleared, this
access is not required. The second access performs the change of the value (DATE, MONTH). The third access is
required to re-enable the field by writing 1 in DATEEN, MTHEN fields.
Bit
Access
Reset
Bit
Access
Reset
Bit
31
DATEEN
R/W
0
30
23
MTHEN
R/W
0
22
15
14
7
6
29
28
27
26
25
24
DATE[5:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
21
20
19
17
16
R/W
0
R/W
0
18
MONTH[4:0]
R/W
0
R/W
0
R/W
1
13
12
11
10
9
8
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit 31 – DATEEN Date Alarm Enable
Value
Description
0
The date-matching alarm is disabled.
1
The date-matching alarm is enabled.
Bits 29:24 – DATE[5:0] Date Alarm
This field is the alarm field corresponding to the BCD-coded date counter.
Bit 23 – MTHEN Month Alarm Enable
Value
Description
0
The month-matching alarm is disabled.
1
The month-matching alarm is enabled.
Bits 20:16 – MONTH[4:0] Month Alarm
This field is the alarm field corresponding to the BCD-coded month counter.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Real-time Clock (RTC)
18.6.9
RTC Calendar Alarm Register (UTC_MODE)
Name:
Offset:
Reset:
Property:
RTC_CALALR (UTC_MODE)
0x14
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UTCEN
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – UTCEN UTC Alarm Enable
Value
Description
0
The UTC-matching alarm is disabled.
1
The UTC-matching alarm is enabled.
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SAM9X60
Real-time Clock (RTC)
18.6.10 RTC Status Register
Name:
Offset:
Reset:
Property:
Bit
RTC_SR
0x18
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
TDERR
R
0
4
CALEV
R
0
3
TIMEV
R
0
2
SEC
R
0
1
ALARM
R
0
0
ACKUPD
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – TDERR Time and/or Date Free Running Error
If the RTC is configured in UTC mode, the value returned by this field is not relevant.
Value
Name
Description
0
CORRECT
The internal free running counters are carrying valid values since the last read of the
Status register (RTC_SR).
1
ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, nonBCD values) since the last read and/or they are still invalid.
Bit 4 – CALEV Calendar Event
The calendar event is selected in RTC_CR.TIMEVSEL and can be any one of the following events: week change,
month change and year change. If the RTC is configured in UTC mode, the value returned by this field is not
relevant.
Value
Name
Description
0
NO_CALEVENT
No calendar event has occurred since the last clear.
1
CALEVENT
At least one calendar event has occurred since the last clear.
Bit 3 – TIMEV Time Event
The time event is selected in RTC_CR.TIMEVSEL and can be any one of the following events: minute change, hour
change, noon, midnight (day change). If the RTC is configured in UTC mode, the value returned by this field is not
relevant.
Value
Name
Description
0
NO_TIMEVENT
No time event has occurred since the last clear.
1
TIMEVENT
At least one time event has occurred since the last clear.
Bit 2 – SEC Second Event
Value
Name
0
NO_SECEVENT
1
SECEVENT
© 2020 Microchip Technology Inc.
Description
No second event has occurred since the last clear.
At least one second event has occurred since the last clear.
Complete Datasheet
DS60001579C-page 156
SAM9X60
Real-time Clock (RTC)
Bit 1 – ALARM Alarm Flag
Value
Name
0
NO_ALARMEVENT
1
ALARMEVENT
Description
No alarm matching condition occurred.
An alarm matching condition has occurred.
Bit 0 – ACKUPD Acknowledge for Update
Value
Name
Description
0
FREERUN
Time and calendar registers cannot be updated.
1
UPDATE
Time and calendar registers can be updated.
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SAM9X60
Real-time Clock (RTC)
18.6.11 RTC Status Clear Command Register
Name:
Offset:
Reset:
Property:
RTC_SCCR
0x1C
–
Write-only
To avoid missing clearing commands, wait for three slow clock cycles between two accesses to this register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding status flag in the Status register (RTC_SR).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
TDERRCLR
W
–
4
CALCLR
W
–
3
TIMCLR
W
–
2
SECCLR
W
–
1
ALRCLR
W
–
0
ACKCLR
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – TDERRCLR Time and/or Date Free Running Error Clear
If the RTC is configured in UTC mode, this bit has no effect.
Bit 4 – CALCLR Calendar Clear
If the RTC is configured in UTC mode, this bit has no effect.
Bit 3 – TIMCLR Time Clear
If the RTC is configured in UTC mode, this bit has no effect.
Bit 2 – SECCLR Second Clear
Bit 1 – ALRCLR Alarm Clear
Bit 0 – ACKCLR Acknowledge Clear
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SAM9X60
Real-time Clock (RTC)
18.6.12 RTC Interrupt Enable Register
Name:
Offset:
Reset:
Property:
RTC_IER
0x20
–
Write-only
This register can only be written if the WPITEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
TDERREN
W
–
4
CALEN
W
–
3
TIMEN
W
–
2
SECEN
W
–
1
ALREN
W
–
0
ACKEN
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – TDERREN Time and/or Date Error Interrupt Enable
If the RTC is configured in UTC mode, this bit has no effect.
Bit 4 – CALEN Calendar Event Interrupt Enable
If the RTC is configured in UTC mode, this bit has no effect.
Bit 3 – TIMEN Time Event Interrupt Enable
If the RTC is configured in UTC mode, this bit has no effect.
Bit 2 – SECEN Second Event Interrupt Enable
Bit 1 – ALREN Alarm Interrupt Enable
Bit 0 – ACKEN Acknowledge Update Interrupt Enable
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SAM9X60
Real-time Clock (RTC)
18.6.13 RTC Interrupt Disable Register
Name:
Offset:
Reset:
Property:
RTC_IDR
0x24
–
Write-only
This register can only be written if the WPITEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
TDERRDIS
W
–
4
CALDIS
W
–
3
TIMDIS
W
–
2
SECDIS
W
–
1
ALRDIS
W
–
0
ACKDIS
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – TDERRDIS Time and/or Date Error Interrupt Disable
If the RTC is configured in UTC mode, this bit has no effect.
Bit 4 – CALDIS Calendar Event Interrupt Disable
If the RTC is configured in UTC mode, this bit has no effect.
Bit 3 – TIMDIS Time Event Interrupt Disable
If the RTC is configured in UTC mode, this bit has no effect.
Bit 2 – SECDIS Second Event Interrupt Disable
Bit 1 – ALRDIS Alarm Interrupt Disable
Bit 0 – ACKDIS Acknowledge Update Interrupt Disable
© 2020 Microchip Technology Inc.
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SAM9X60
Real-time Clock (RTC)
18.6.14 RTC Interrupt Mask Register
Name:
Offset:
Reset:
Property:
RTC_IMR
0x28
0x00000000
Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
TDERR
R
0
4
CAL
R
0
3
TIM
R
0
2
SEC
R
0
1
ALR
R
0
0
ACK
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – TDERR Time and/or Date Error Mask
If the RTC is configured in UTC mode, this bit has no effect.
Bit 4 – CAL Calendar Event Interrupt Mask
If the RTC is configured in UTC mode, this bit is not relevant.
Bit 3 – TIM Time Event Interrupt Mask
If the RTC is configured in UTC mode, this bit is not relevant.
Bit 2 – SEC Second Event Interrupt Mask
Bit 1 – ALR Alarm Interrupt Mask
Bit 0 – ACK Acknowledge Update Interrupt Mask
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 161
SAM9X60
Real-time Clock (RTC)
18.6.15 RTC Valid Entry Register
Name:
Offset:
Reset:
Property:
RTC_VER
0x2C
0x00000000
Read-only
If the RTC is configured in UTC mode, the values returned by this register are not relevant.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
NVCALALR
R
0
2
NVTIMALR
R
0
1
NVCAL
R
0
0
NVTIM
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 3 – NVCALALR Non-valid Calendar Alarm
Value
Description
0
No invalid data has been detected in RTC_CALALR (Calendar Alarm register).
1
RTC_CALALR has contained invalid data since it was last programmed.
Bit 2 – NVTIMALR Non-valid Time Alarm
Value
Description
0
No invalid data has been detected in RTC_TIMALR (Time Alarm register).
1
RTC_TIMALR has contained invalid data since it was last programmed.
Bit 1 – NVCAL Non-valid Calendar
Value
Description
0
No invalid data has been detected in RTC_CALR (Calendar register).
1
RTC_CALR has contained invalid data since it was last programmed.
Bit 0 – NVTIM Non-valid Time
Value
Description
0
No invalid data has been detected in RTC_TIMR (Time register).
1
RTC_TIMR has contained invalid data since it was last programmed.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 162
SAM9X60
Real-time Clock (RTC)
18.6.16 RTC TimeStamp Time Register 0
Name:
Offset:
Reset:
Property:
RTC_TSTR0
0xB0
0x00000000
Read-only
These fields are valid for non-UTC mode only.
RTC_TSTR0 reports the timestamp of the first tamper event after reading RTC_TSSR0.
Bit
Access
Reset
Bit
31
BACKUP
R
0
30
23
22
AMPM
R
0
21
R
0
R
0
14
13
12
R
0
R
0
R
0
6
5
4
R
0
R
0
R
0
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
29
28
27
26
25
24
R
0
R
0
R
0
18
17
16
R
0
R
0
R
0
R
0
11
MIN[6:0]
R
0
10
9
8
R
0
R
0
R
0
3
SEC[6:0]
R
0
2
1
0
R
0
R
0
R
0
TEVCNT[3:0]
R
0
20
19
HOUR[5:0]
Bit 31 – BACKUP System Mode of the Tamper (cleared by reading RTC_TSSR0)
Value
Description
0
The state of the system is different from Backup mode when the tamper event occurs.
1
The system is in Backup mode when the tamper event occurs.
Bits 27:24 – TEVCNT[3:0] Tamper Events Counter (cleared by reading RTC_TSSR0)
Each time a tamper event occurs, this counter is incremented. This counter saturates at 15. Once this value is
reached, it is no more possible to know the exact number of tamper events.
If this field is not null, this implies that at least one tamper event occurs since last register reset and that the values
stored in timestamping registers are valid.
Bit 22 – AMPM AM/PM Indicator of the Tamper (cleared by reading RTC_TSSR0)
Bits 21:16 – HOUR[5:0] Hours of the Tamper (cleared by reading RTC_TSSR0)
Bits 14:8 – MIN[6:0] Minutes of the Tamper (cleared by reading RTC_TSSR0)
Bits 6:0 – SEC[6:0] Seconds of the Tamper (cleared by reading RTC_TSSR0)
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 163
SAM9X60
Real-time Clock (RTC)
18.6.17 RTC TimeStamp Time Register 0 (UTC_MODE)
Name:
Offset:
Reset:
Property:
RTC_TSTR0 (UTC_MODE)
0xB0
0x00000000
Read-only
RTC_TSTR0 reports the timestamp of the first tamper event after reading RTC_TSSR0.
Bit
Access
Reset
Bit
31
BACKUP
R
0
30
29
23
22
21
15
14
7
6
28
27
26
25
24
TEVCNT[3:0]
R
0
R
0
R
0
R
0
20
19
18
17
16
13
12
11
10
9
8
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 31 – BACKUP System Mode of the Tamper (cleared by reading RTC_TSSR0)
Value
Description
0
The state of the system is different from Backup mode when the tamper event occurs.
1
The system is in Backup mode when the tamper event occurs.
Bits 27:24 – TEVCNT[3:0] Tamper Events Counter (cleared by reading RTC_TSSR0)
Each time a tamper event occurs, this counter is incremented. This counter saturates at 15. Once this value is
reached, it is no more possible to know the exact number of tamper events.
If this field is not null, this implies that at least one tamper event occurs since last register reset and that the values
stored in timestamping registers are valid.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 164
SAM9X60
Real-time Clock (RTC)
18.6.18 RTC TimeStamp Time Register 1
Name:
Offset:
Reset:
Property:
RTC_TSTR1
0xBC
0x00000000
Read-only
These fields are valid for non-UTC mode only.
RTC_TSTR1 reports the timestamp of the last tamper event after reading RTC_TSSR1.
Bit
Access
Reset
Bit
31
BACKUP
R
0
30
29
28
27
23
22
AMPM
R
0
21
20
19
R
0
R
0
14
13
12
R
0
R
0
R
0
6
5
4
R
0
R
0
R
0
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
26
25
24
18
17
16
R
0
R
0
R
0
R
0
11
MIN[6:0]
R
0
10
9
8
R
0
R
0
R
0
3
SEC[6:0]
R
0
2
1
0
R
0
R
0
R
0
HOUR[5:0]
Bit 31 – BACKUP System Mode of the Tamper (cleared by reading RTC_TSSR1)
Value
Description
0
The state of the system is different from Backup mode when the tamper event occurs.
1
The system is in Backup mode when the tamper event occurs.
Bit 22 – AMPM AM/PM Indicator of the Tamper (cleared by reading RTC_TSSR1)
Bits 21:16 – HOUR[5:0] Hours of the Tamper (cleared by reading RTC_TSSR1)
Bits 14:8 – MIN[6:0] Minutes of the Tamper (cleared by reading RTC_TSSR1)
Bits 6:0 – SEC[6:0] Seconds of the Tamper (cleared by reading RTC_TSSR1)
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 165
SAM9X60
Real-time Clock (RTC)
18.6.19 RTC TimeStamp Time Register 1 (UTC_MODE)
Name:
Offset:
Reset:
Property:
RTC_TSTR1 (UTC_MODE)
0xBC
0x00000000
Read-only
RTC_TSTR1 reports the timestamp of the last tamper event after reading RTC_TSSR1.
Bit
Access
Reset
Bit
31
BACKUP
R
0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 31 – BACKUP System Mode of the Tamper (cleared by reading RTC_TSSR1)
Value
Description
0
The state of the system is different from Backup mode when the tamper event occurs.
1
The system is in Backup mode when the tamper event occurs.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 166
SAM9X60
Real-time Clock (RTC)
18.6.20 RTC TimeStamp Date Register
Name:
Offset:
Reset:
Property:
RTC_TSDRx
0xB4 + x*0x0C [x=0..1]
0x00000000
Read-only
These fields contain the date and the source of a tamper occurrence if RTC_TSTR0.TEVCNT field is not null.
These fields are relevant for non-UTC mode only.
RTC_TSDR0 reports the timestamp of the first tamper event after reading RTC_TSSR0, and RTC_TSDR1 reports
the timestamp of the last tamper event.
Bit
31
30
29
28
27
26
25
24
DATE[5:0]
Access
Reset
Bit
23
Access
Reset
R
0
22
DAY[2:0]
R
0
Bit
15
14
R
0
R
0
R
0
R
0
R
0
R
0
21
20
19
17
16
R
0
R
0
R
0
18
MONTH[4:0]
R
0
R
0
R
0
13
12
11
10
9
8
YEAR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
2
1
0
R
0
R
0
R
0
3
CENT[6:0]
R
0
R
0
R
0
R
0
Access
Reset
Bits 29:24 – DATE[5:0] Date of the Tamper (cleared by reading RTC_TSSRx)
Bits 23:21 – DAY[2:0] Day of the Tamper (cleared by reading RTC_TSSRx)
Bits 20:16 – MONTH[4:0] Month of the Tamper (cleared by reading RTC_TSSRx)
Bits 15:8 – YEAR[7:0] Year of the Tamper (cleared by reading RTC_TSSRx)
Bits 6:0 – CENT[6:0] Century of the Tamper (cleared by reading RTC_TSSRx)
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 167
SAM9X60
Real-time Clock (RTC)
18.6.21 RTC TimeStamp Date Register (UTC_MODE)
Name:
Offset:
Reset:
Property:
RTC_TSDRx (UTC_MODE)
0xB4
0x00000000
Read-only
RTC_TSDR0 reports the timestamp of the first tamper event after reading RTC_TSSR0, and RTC_TSDR1 reports
the timestamp of the last tamper event.
This register is cleared by reading RTC_TSSRx.
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
28
27
UTC_TIME[31:24]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
UTC_TIME[23:16]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
UTC_TIME[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
UTC_TIME[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 31:0 – UTC_TIME[31:0] Time of the Tamper (UTC format)
This configuration is relevant only if UTC = 1 in RTC_MR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 168
SAM9X60
Real-time Clock (RTC)
18.6.22 RTC TimeStamp Source Register
Name:
Offset:
Reset:
Property:
RTC_TSSRx
0xB8 + x*0x0C [x=0..1]
0x00000000
Read-only
This register is cleared after read and the read access also performs a clear on RTC_TSTRx and RTC_TSDRx.
The following configuration values are valid for all listed bit names of this register:
0: No alarm generated since the last clear.
1: An alarm has been generated by the corresponding monitor since the last clear.
Bit
31
30
29
28
27
26
25
24
23
DET7
R
0
22
DET6
R
0
21
DET5
R
0
20
DET4
R
0
19
DET3
R
0
18
DET2
R
0
17
DET1
R
0
16
DET0
R
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19, 20, 21, 22, 23 – DETx Tamper Detection on VDDCORE WKUP[8:1] (cleared on read)
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 169
SAM9X60
Real-time Clock (RTC)
18.6.23 RTC Tamper Mode Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
RTC_TMR
0x58
0x00000000
Read/Write
31
TRLOCK
W
0
30
29
28
27
26
25
24
23
POL7
R/W
0
22
POL6
R/W
0
21
POL5
R/W
0
20
POL4
R/W
0
19
POL3
R/W
0
18
POL2
R/W
0
17
POL1
R/W
0
16
POL0
R/W
0
15
14
13
12
11
10
9
8
7
EN7
R/W
0
6
EN6
R/W
0
5
EN5
R/W
0
4
EN4
R/W
0
3
EN3
R/W
0
2
EN2
R/W
0
1
EN1
R/W
0
0
EN0
R/W
0
Access
Reset
Bit
Access
Reset
Bit 31 – TRLOCK Tamper Registers Lock (Write-once, cleared by VDDCORE reset)
Value
Name
Description
0
UNLOCKED RTC_TMR and RTC_TDPR can be written.
1
LOCKED
RTC_TMR and RTC_TDPR cannot be written until the next VDDCORE domain reset.
Bits 16, 17, 18, 19, 20, 21, 22, 23 – POLx WKUPx+1 Polarity
Value
Name Description
0
LOW If the source of tamper remains low for a debounce period, a tamper event is generated.
1
HIGH If the source of tamper remains high for a debounce period, a tamper event is generated.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – ENx WKUPx+1 Tamper Source Enable
Value
Name
Description
0
DISABLE
WKUP pin index x+1 is not enabled as a source of tamper.
1
ENABLE
WKUP pin index x+1 is enabled as a source of tamper.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 170
SAM9X60
Real-time Clock (RTC)
18.6.24 RTC Tamper Debounce Period Register
Name:
Offset:
Reset:
Property:
Bit
RTC_TDPR
0x5C
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
SELP7
R/W
0
22
SELP6
R/W
0
21
SELP5
R/W
0
20
SELP4
R/W
0
19
SELP3
R/W
0
18
SELP2
R/W
0
17
SELP1
R/W
0
16
SELP0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
PERB[3:0]
Access
Reset
R/W
0
R/W
0
PERA[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
Bits 16, 17, 18, 19, 20, 21, 22, 23 – SELPx WKUPx+1 Debounce Period Selection
Value
Name
Description
0
SEL_PA
WKUP pin index x+1 is debounced with PERA period.
1
SEL_PB
WKUP pin index x+1 is debounced with PERB period.
Bits 7:4 – PERB[3:0] Debounce Period B
Value
Name
Description
0
MD_SLCK_2
The source of tamper must remain active for at least 2 monitoring domain slow clock
cycles to generate a tamper event.
1
MD_SLCK_4
The source of tamper must remain active for at least 4 monitoring domain slow clock
cycles to generate a tamper event.
2
MD_SLCK_8
The source of tamper must remain active for at least 8 monitoring domain slow clock
cycles to generate a tamper event.
3
MD_SLCK_16 The source of tamper must remain active for at least 16 monitoring domain slow clock
cycles to generate a tamper event.
4
MD_SLCK_32 The source of tamper must remain active for at least 32 monitoring domain slow clock
cycles to generate a tamper event.
5
MD_SLCK_64 The source of tamper must remain active for at least 64 monitoring domain slow clock
cycles to generate a tamper event.
6
MD_SLCK_128 The source of tamper must remain active for at least 128 monitoring domain slow
clock cycles to generate a tamper event.
7
MD_SLCK_256 The source of tamper must remain active for at least 256 monitoring domain slow
clock cycles to generate a tamper event.
Bits 3:0 – PERA[3:0] Debounce Period A
Value
Name
Description
0
MD_SLCK_2
The source of tamper must remain active for at least 2 monitoring domain slow clock
cycles to generate a tamper event.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 171
SAM9X60
Real-time Clock (RTC)
Value
1
2
3
4
5
6
7
Name
MD_SLCK_4
Description
The source of tamper must remain active for at least 4 monitoring domain slow clock
cycles to generate a tamper event.
MD_SLCK_8
The source of tamper must remain active for at least 8 monitoring domain slow clock
cycles to generate a tamper event.
MD_SLCK_16 The source of tamper must remain active for at least 16 monitoring domain slow clock
cycles to generate a tamper event.
MD_SLCK_32 The source of tamper must remain active for at least 32 monitoring domain slow clock
cycles to generate a tamper event.
MD_SLCK_64 The source of tamper must remain active for at least 64 monitoring domain slow clock
cycles to generate a tamper event.
MD_SLCK_128 The source of tamper must remain active for at least 128 monitoring domain slow
clock cycles to generate a tamper event.
MD_SLCK_256 The source of tamper must remain active for at least 256 monitoring domain slow
clock cycles to generate a tamper event.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 172
SAM9X60
Shutdown Controller (SHDWC)
19.
Shutdown Controller (SHDWC)
19.1
Description
The Shutdown Controller (SHDWC) controls the SHDN output signal (to enable and disable an external power supply
circuit), and manages the wake-up events detection.
19.2
Embedded Characteristics
•
•
19.3
Shutdown Logic
– Software assertion of the Shutdown Output Pin (SHDN)
– Programmable de-assertion from the wake-up events
Wake-Up Logic
– Programmable wake-up event detection input pins, and internal wake-up event from RTC and RTT
Block Diagram
Figure 19-1. SHDWC Block Diagram
MD_SLCK
Shutdown Controller
SHDW_WUIR
WKUPT0
WKUPEN0
WKUP0
read SHDW_SR
reset
WKUPIS0
SHDW_SR
set
read SHDW_SR
Wake-up
reset
RTTWKEN SHDW_MR
RTT Alarm
RTTWK
Shutdown
Output
Controller
SHDW_SR
set
SHDW_CR
read SHDW_SR
SHDW
SHDN
Shutdown
reset
RTCWKEN SHDW_MR
RTC Alarm
19.4
RTCWK
SHDW_SR
set
I/O Lines Description
Table 19-1. I/O Lines Description
Name
Description
Type
WKUP0
Wake-up inputs
Input
SHDN
Shutdown output
Output
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 173
SAM9X60
Shutdown Controller (SHDWC)
19.5
19.5.1
Product Dependencies
Power Management
The SHDWC is continuously clocked by the Monitoring Domain Slow Clock (MD_SLCK). The Power Management
Controller has no effect on the behavior of the SHDWC.
19.6
Functional Description
The SHDWC manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins
and one output pin, SHDN.
A typical application connects the pin SHDN to the enable input of the device's power supply circuit. The wake-up
inputs (WKUP0) connect to any push-buttons or signal that wake up the system.
The software is able to control the pin SHDN by writing the Shutdown Control Register (SHDW_CR) with the bit
SHDW at 1. The shutdown is taken into account only two MD_SLCK cycles after the write of SHDW_CR. This
register is password-protected and so the value written should contain the correct key for the command to be taken
into account. As a result, the SHDN pin is driven low and the system should be powered down.
19.6.1
Wake-up Inputs
Any level change on the WKUP pin can trigger a wake-up. Wake-up is configured in theMode register (SHDW_MR)
and Wakeup Inputs register (SHDW_WUIR). The transition detector can be programmed to detect either a positive or
negative transition on the WKUP pin. The detection can also be disabled. Programming is performed by enabling the
Wake-up Input (WKUPEN0 bit) and defining the Wake-up Input Type (WKUPT0 bit) in the SHDW_WUIR.
Moreover, a debouncing circuit can be programmed for WKUP. The debouncing circuit filters pulses on WKUP
shorter than the programmed value in SHDW_MR.WKUPDBC. If the programmed level change is detected on a pin,
a counter starts. When the counter reaches the value programmed in WKUPDBC, the SHDN pin is released. If a new
input change is detected before the counter reaches the corresponding value, the counter is stopped and cleared.
WKUPIS0 of the Status register (SHDW_SR) reports the detection of the programmed events on WKUP with a reset
after the read of SHDW_SR.
The SHDWC can be programmed so as to activate the wake-up using the RTC and RTT alarms (detection of the
rising edge event is synchronized with SLCK). This is done by writing the SHDW_MR using the RTCWKEN and
RTTWKEN bits. When enabled, the detection of RTC and RTT alarms is reported in the RTCWK and RTTWK bits of
SHDW_SR. They are cleared after reading SHDW_SR. When using the RTC and RTT alarms to wake up the
system, the user must ensure that RTC and RTT alarm status flags are cleared before shutting down the system.
Otherwise, no rising edge of the status flags may be detected and the wake-up fails.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 174
SAM9X60
Shutdown Controller (SHDWC)
19.7
Register Summary
Offset
Name
0x00
SHDW_CR
0x04
SHDW_MR
0x08
SHDW_SR
0x0C
SHDW_WUIR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
6
5
4
3
2
1
0
KEY[7:0]
SHDW
WKUPDBC[2:0]
RTCWKEN
RTTWKEN
WKUPIS0
RTCWK
RTTWK
WKUPS
WKUPT0
WKUPEN0
Complete Datasheet
DS60001579C-page 175
SAM9X60
Shutdown Controller (SHDWC)
19.7.1
SHDWC Control Register
Name:
Offset:
Reset:
Property:
Bit
31
SHDW_CR
0x00
–
Write-only
30
29
28
27
26
25
24
KEY[7:0]
Access
Reset
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SHDW
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:24 – KEY[7:0] Password
Value
Name
Description
0xA5
PASSWD
Writing any other value in this field aborts the write operation.
Bit 0 – SHDW Shutdown Command
Value
Description
0
No effect.
1
If KEY value is correct, asserts the SHDN pin.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 176
SAM9X60
Shutdown Controller (SHDWC)
19.7.2
SHDWC Mode Register
Name:
Offset:
Reset:
Property:
SHDW_MR
0x04
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register
(SYSC_WPMR).
Bit
31
30
29
28
27
Access
Reset
Bit
26
R/W
0
24
R/W
0
23
22
21
20
19
18
17
RTCWKEN
R/W
0
16
RTTWKEN
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
25
WKUPDBC[2:0]
R/W
0
Access
Reset
Bit
Access
Reset
Bits 26:24 – WKUPDBC[2:0] Wake-up Inputs Debouncer Period
Value
Name
Description
0
IMMEDIATE
Immediate, no debouncing, detected active at least on one MD_SLCK edge
1
3_SLCK
WKUP shall be in its active state for at least 3 MD_SLCK periods
2
32_SLCK
WKUP shall be in its active state for at least 32 MD_SLCK periods
3
512_SLCK
WKUP shall be in its active state for at least 512 MD_SLCK periods
4
4096_SLCK
WKUP shall be in its active state for at least 4,096 SLCK periods
5
32768_SLCK
WKUP shall be in its active state for at least 32,768 MD_SLCK periods
Bit 17 – RTCWKEN Real-time Clock Wake-up Enable
Value
Description
0
The RTC Alarm signal has no effect on the SHDWC.
1
The RTC Alarm signal forces the de-assertion of the SHDN pin.
Bit 16 – RTTWKEN Real-time Timer Wake-up Enable
Value
Description
0
The RTT Alarm signal has no effect on the SHDWC.
1
The RTT Alarm signal forces the de-assertion of the SHDN pin.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 177
SAM9X60
Shutdown Controller (SHDWC)
19.7.3
SHDWC Status Register
Name:
Offset:
Reset:
Property:
SHDW_SR
0x08
0x00000000
Read-only
Note: The events are detected only when the system is in Backup mode.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WKUPIS0
R
0
15
14
13
12
11
10
9
8
7
6
5
RTCWK
R
0
4
RTTWK
R
0
3
2
1
0
WKUPS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 16 – WKUPIS0 Wake-up 0 Input Status
Value
Name
Description
0
DISABLE The wake-up 0 input is disabled, or was inactive at the time the debouncer triggered a
wake-up event.
1
ENABLE The wake-up 0 input was active at the time the debouncer triggered a wake-up event.
Bit 5 – RTCWK Real-time Clock Wake-up
Value
Description
0
No wake-up alarm from the RTC occurred since the last read of SHDW_SR.
1
At least one wake-up alarm from the RTC occurred since the last read of SHDW_SR.
Bit 4 – RTTWK Real-time Timer Wake-up
Value
Description
0
No wake-up alarm from the RTT occurred since the last read of SHDW_SR.
1
At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR.
Bit 0 – WKUPS WKUP Wake-up Status
Value
Name
Description
0
NO
No wake-up due to the assertion of the WKUP pins has occurred since the last read of
SHDW_SR.
1
PRESENT At least one wake-up due to the assertion of the WKUP pins has occurred since the last
read of SHDW_SR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 178
SAM9X60
Shutdown Controller (SHDWC)
19.7.4
SHDWC Wake-up Inputs Register
Name:
Offset:
Reset:
Property:
SHDW_WUIR
0x0C
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WKUPT0
R
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WKUPEN0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 16 – WKUPT0 Wake-up 0 Input Type
Value
Name Description
0
LOW A falling edge followed by a low level on the wake-up 0 input, for a period defined by
WKUPDBC, forces wake-up of the core power supply.
1
HIGH A rising edge followed by a high level on the wake-up 0 input, for a period defined by
WKUPDBC, forces wake-up of the core power supply.
Bit 0 – WKUPEN0 Wake-up 0 Input Enable
Value
Name
Description
0
DISABLE
The wake-up 0 input has no wake-up effect.
1
ENABLE
The wake-up 0 input forces wake-up of the core power supply.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 179
SAM9X60
Periodic Interval Timer (PIT)
20.
Periodic Interval Timer (PIT)
20.1
Description
The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum
accuracy and efficient management, even for systems with long response time.
20.2
Embedded Characteristics
•
•
•
20.3
20-bit Programmable Counter plus 12-bit Interval Counter
Reset-on-read Feature
Both Counters Work on Master Clock/16
Block Diagram
Figure 20-1. Periodic Interval Timer
PIT_MR
PIV
=
PIT_MR
PITIEN
set
0
PIT_SR
PITS
pit_irq
reset
0
MCK
Prescaler
20.4
0
0
1
12-bit
Adder
1
read PIT_PIVR
20-bit
Counter
MCK/16
CPIV
PIT_PIVR
CPIV
PIT_PIIR
PICNT
PICNT
Functional Description
The Periodic Interval Timer provides periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode
Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval
Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the
interrupt is enabled (PITIEN in PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 180
SAM9X60
Periodic Interval Timer (PIT)
When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow
counter (PICNT) is reset and the PITS bit is cleared, thus acknowledging the interrupt. The value of PICNT gives the
number of periodic intervals elapsed since the last read of PIT_PIVR.
When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no
effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without
clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.
The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only
becomes effective when the CPIV value is 0. The figure below illustrates the PIT counting. After the PIT Enable bit is
reset (PITEN = 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting,
only if the PITEN is set again.
The PIT is stopped when the core enters debug state.
Figure 20-2. Enabling/Disabling PIT with PITEN
APB cycle
APB cycle
MCK
15
restarts MCK Prescaler
MCK Prescaler 0
PITEN
CPIV
0
PICNT
1
PIV - 1
0
PIV
1
0
1
0
PITS (PIT_SR)
APB Interface
read PIT_PIVR
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 181
SAM9X60
Periodic Interval Timer (PIT)
20.5
Register Summary
Offset
Name
0x00
PIT_MR
0x04
PIT_SR
0x08
PIT_PIVR
0x0C
PIT_PIIR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
6
5
4
3
2
1
PITIEN
PIV[19:16]
0
PITEN
PIV[15:8]
PIV[7:0]
PITS
PICNT[11:4]
PICNT[3:0]
CPIV[19:16]
CPIV[15:8]
CPIV[7:0]
PICNT[11:4]
PICNT[3:0]
CPIV[19:16]
CPIV[15:8]
CPIV[7:0]
Complete Datasheet
DS60001579C-page 182
SAM9X60
Periodic Interval Timer (PIT)
20.5.1
Periodic Interval Timer Mode Register
Name:
Offset:
Reset:
Property:
PIT_MR
0x00
0x000FFFFF
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
23
22
21
20
19
18
Access
Reset
Bit
25
PITIEN
R/W
0
24
PITEN
R/W
0
17
16
PIV[19:16]
Access
Reset
Bit
15
14
13
12
R/W
1
R/W
1
R/W
1
R/W
1
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
PIV[15:8]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
PIV[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bit 25 – PITIEN Period Interval Timer Interrupt Enable
Value
Description
0
The bit PITS in PIT_SR has no effect on the interrupt.
1
The bit PITS in PIT_SR asserts an interrupt.
Bit 24 – PITEN Period Interval Timer Enabled
Value
Description
0
The Periodic Interval Timer is disabled when the PIV value is reached.
1
The Periodic Interval Timer is enabled.
Bits 19:0 – PIV[19:0] Periodic Interval Value
Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal
to (PIV + 1).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 183
SAM9X60
Periodic Interval Timer (PIT)
20.5.2
Periodic Interval Timer Status Register
Name:
Offset:
Reset:
Property:
Bit
PIT_SR
0x04
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PITS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – PITS Periodic Interval Timer Status
Value
Description
0
The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR.
1
The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 184
SAM9X60
Periodic Interval Timer (PIT)
20.5.3
Periodic Interval Timer Value Register
Name:
Offset:
Reset:
Property:
PIT_PIVR
0x08
0x00000000
Read-only
Reading this register clears PITS in PIT_SR.
Bit
31
30
29
28
27
26
25
24
R
0
R
0
17
16
PICNT[11:4]
Access
Reset
R
0
R
0
Bit
23
22
R
0
R
0
R
0
R
0
21
20
19
18
PICNT[3:0]
CPIV[19:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
CPIV[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
CPIV[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:20 – PICNT[11:0] Periodic Interval Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
Bits 19:0 – CPIV[19:0] Current Periodic Interval Value
Returns the current value of the periodic interval timer.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 185
SAM9X60
Periodic Interval Timer (PIT)
20.5.4
Periodic Interval Timer Image Register
Name:
Offset:
Reset:
Property:
Bit
31
PIT_PIIR
0x0C
0x00000000
Read-only
30
29
28
27
26
25
24
R
0
R
0
17
16
PICNT[11:4]
Access
Reset
R
0
R
0
Bit
23
22
R
0
R
0
R
0
R
0
21
20
19
18
PICNT[3:0]
CPIV[19:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
CPIV[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
CPIV[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:20 – PICNT[11:0] Periodic Interval Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
Bits 19:0 – CPIV[19:0] Current Periodic Interval Value
Returns the current value of the periodic interval timer.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 186
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.
64-bit Periodic Interval Timer (PIT64B)
21.1
Description
The 64-bit Periodic Interval Timer (PIT64B) provides the operating system scheduler interrupt, as well as any periodic
source of interrupt to software. It is designed to offer maximum accuracy and efficient management, even for systems
with long response times.
21.2
Embedded Characteristics
•
•
•
•
•
21.3
4-bit Prescaler
64-bit Timer
Single Shot or Continuous Mode
Safety/Security Access Reports
Register Write protection
Block Diagram
Figure 21-1. Block Diagram
PIT64B_MR.SGCLK
PIT64B_MSBPR.MSBPERIOD
PIT64B_LSBPR.LSBPERIOD
PIT64B_MR.PRESCALER
PRESC = 0
GCLK
Edge
detection
load value
4-bit prescaler
1
‘1’
1
enable
0
selected
clock
load value
64-bit timer
AND
PIT64B_ISR.OVRE
enable
=0
load
clock
=0
0
clock
load
PIT64B_ISR.PERIOD
peripheral
clock
PIT64B_TMSBPR.MSBTIMER
PIT64B_TLSBPR.LSBTIMER
PIT64B_CR.START
timer = 0 and prescaler = 0
issued START command
and timer = 0 and prescaler = 0
AND
OR
0
1
PIT64B_IMR.PERIOD
AND
PIT64B_MR.CONT
PIT64B_ISR.PERIOD
OR
PIT64B_IMR.OVRE
PIT64B_ISR.OVRE
21.4
Product Dependencies
21.4.1
Power Management
interrupt
line
AND
The Power Management Controller (PMC) controls the PIT64B clock in order to save power. The programmer must
first enable the PIT64B clock in the PMC before using the PIT64B.
After a hardware reset, the PIT64B clock is disabled by default.
21.4.2
Interrupt Generation
The PIT64B interface has an interrupt line connected to the Interrupt Controller.
Handling the PIT64B interrupt requires programming the Interrupt Controller before configuring the PIT64B.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 187
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.5
21.5.1
Functional Description
Timer Clock Source
The two clock sources for the 64-bit timer are the peripheral clock and the generic clock (GCLK), which can be fully
asynchronous to the peripheral clock. The selected clock can be prescaled before triggering the 64-bit timer.
The GCLK is selected as source clock for the prescaler when the SGCLK bit, in the Mode register (PIT64B_MR), is
written to 1. The prescaler is active as soon as PIT64B_MR.PRESCALER>0.
If PIT64B_MR.PRESCALER=0, the timer is triggered either on each rising edge detection event of the GCLK if
PIT64B_MR.SGCLK is written to 1, or on each rising edge of the peripheral clock.
If GCLK is selected, the frequency must be at least 3 times lower than the peripheral clock.
21.5.2
Single Period Mode
When the PIT64B_MR.CONT bit is written to 0, the PIT64B produces a single timer event. The timer period starts as
soon as the START bit, in the Control register (PIT64B_CR), is written to 1. The period is defined by configuring the
LSBPERIOD field in the LSB Period register (PIT64B_LSBPR) and the MSBPERIOD field in the MSB Period register
(PIT64B_MSBPR). When the START command is issued, the 64-bit timer loads 0 and increments up to LSBPERIOD
and MSBPERIOD field value minus 1, then automatically reloads 0 and stops.
When time reaches the maximum value, the PERIOD flag, in the Interrupt Status register (PIT64B_ISR), is set. No
other period will be started until a new START command is issued.
After a period is started and while it is not elapsed, any new values written in PIT64B_MR, PIT64B_LSBPR or
PIT64B_MSBPR have no effect on the current period if bit PIT64B_MR.SMOD=0 (see Figure Single Waveform in
Single Period Mode if bit PIT64B_MR.SMOD=0
If PIT64B_MR.SMOD=1 a start is also performed as soon as PIT64B_LSBPR is written, thus a modification of the
period can be performed on-the-fly with a single write operation if the period requires no more than 32 bits. When
writing a 64-bit value, the 32-bit MSB part must be configured first, followed by the 32-bit LSB part (see Figure
Waveform in Single Period Mode if bit PIT64B_MR.SMOD=1). When configuring a value lower or equal to 32 bits
after processing a period defined on 64 bits, first PIT64B_MSBPR must be written to 0, and then the 32-bit LSB must
be written into PIT64B_LSBPR.
If PIT64B_CR.SWRST is written to 1, the current period is immediately stopped.
Figure 21-2. Single Waveform in Single Period Mode if bit PIT64B_MR.SMOD=0
PIT64B_MR.CONT=0
Write PIT64B_MR,
PIT64B_LSBPR,
PIT64B_MSBPR
Period = P2
Period = P1
No effect start commands
Write PIT64B_CR.START=1
Period = P1
Period = P2
64-bit timer value
PIT64B_ISR.PERIOD
Read PIT64B_ISR
PIT64B_ISR.OVRE
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 188
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
Figure 21-3. Waveform in Single Period Mode if bit PIT64B_MR.SMOD=1
PIT64B_MR.CONT=0
Write PIT64B_MR,
Period = P1 (MSB part)
Period = P2 (MSB part)
Period = P3 (MSB part)
PIT64B_MSBPR
Period = P3 (LSB part)
and start trigger
Write PIT64B_LSBPR
start command
= no effect
start commands
= no effect
Write PIT64B_CR.START=1
Period = P1
Period = P3
Period = P2
Start
Period = P3
64-bit timer value
Start
Period = P2
Start
Period = P3
PIT64B_ISR.PERIOD
Read PIT64B_ISR
21.5.3
Continuous Period Mode
When the PIT64B_MR.CONT bit is written to 1, the PIT64B continuously produces timer events. The timer is started
as soon as the PIT64B_CR.START bit is written to 1. The period is defined by configuring the
PIT64B_LSBPR.LSBPERIOD field and PIT64B_MSBPR.MSBPERIOD field. When the START command is issued,
the 64-bit timer loads 0 and increments up to LSBPERIOD and MSBPERIOD field value minus 1, then automatically
reloads 0 anc restarts a new counting period until bit PIT64B_CR.SWRST is written to 1.
When the timer reaches its maximum value, the flag PIT64B_ISR.PERIOD is set. PIT64B_ISR.PERIOD is cleared
when reading PIT64B_ISR. If a new period elapses and the PIT64B_ISR.PERIOD is 1, the PIT64B_ISR.OVRE flag is
set to indicate a potential latency at system level
After the START command has been issued, any new values written in PIT64B_MR, PIT64B_LSBPR or
PIT64B_MSBPR have no effect on the current period if bit PIT64B_MR.SMOD=0 (see Figure Waveform in
Continuous Period Mode if the bit PIT64B_MR.SMOD=0). A software reset must be issued before configuring new
values in PIT64B_LSBPR and PIT64B_MSBPR if bit PIT64B_MR.SMOD=0.
If PIT64B_MR.SMOD=1 a start can be also performed as soon as PIT64B_LSBPR is written, thus a modification of
the period can be performed on-the-fly with a single write operation if the period requires no more than 32 bits. When
writing a 64-bit value, the 32-bit MSB part must be configured first followed by a 32-bit LSB part (see Figure
Waveform in Continuous Period Mode if the bit PIT64B_MR.SMOD=1). When configuring a value lower or equal to
32 bits after processing a period defined on 64 bits, first PIT64B_MSBPR must be written to 0, and then the 32-bit
LSB must be written into PIT64B_LSBPR.
If PIT64B_CR.SWRST is written to 1, the current period is immediately stopped.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 189
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
Figure 21-4. Waveform in Continuous Period Mode if bit PIT64B_MR.SMOD=0
PIT64B_MR.CONT=1
Write PIT64B_MR,
PIT64B_LSBPR,
PIT64B_MSBPR
Period = P2 = no effect
Period = P1
No effect start commands
Write PIT64B_CR.START=1
Period = P1
64-bit timer value
PIT64B_ISR.PERIOD
Read PIT64B_ISR
PIT64B_ISR.OVRE
Figure 21-5. Waveform in Continuous Period Mode if bit PIT64B_MR.SMOD=1
PIT64B_MR.CONT=1 & PIT64B_MR.SMOD = 1
Write PIT64B_MR,
Period = P2 due to PIT64B_MSBPR = no effect
Period = P1
PIT64B_MSBPR
Period = P3 due to PIT64B_LSBPR write
Write PIT64B_LSBPR
No effect start commands
Write PIT64B_CR.START=1
Period = P3
Period = P1
Period = P1
Start Period
= P1
64-bit timer value
Period = P3
PIT64B_ISR.PERIOD
Read PIT64B_ISR
21.5.4
Security and Safety Analysis and Reports
Several types of checks are performed when the PIT64B is running.
The peripheral clock of the PIT64B is monitored by a specific circuitry to detect abnormal waveforms on the internal
clock that may affect the behavior of the PIT64B. Corruption on the triggering edge of the clock or a pulse with a
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 190
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
minimum duration may be identified. If the CGD flag is set in the Write Protection Status register (PIT64B_WPSR), an
abnormal condition occurred on the peripheral clock. This flag is not set under normal operating conditions.
The internal timer sequence of the PIT64B is also monitored and if an abnormal state is detected, the flag
PIT64B_WPSR.SEQE is set. This flag is not set under normal operating conditions.
The software accesses to the PIT64B are monitored and if an incorrect access is performed, the flag
PIT64B_WPSR.SWE is set. The type of incorrect/abnormal software access is reported in the
PIT64B_WPSR.SWETYP field (see PIT64B Write Protection Status Register for details), e.g., writing PIT64B_MR,
PIT64B_LSBPR (if PIT64B_MR.SMOD=0), PIT64B_MSBPR (if PIT64B_MR.SMOD=0) when the timer is running
(after a START command has been issued) is an error. PIT64B_WPSR.ECLASS is an indicator reporting the
criticality of the SWETYP report.
The flags CGD, SEQE, SWE and WPVS are automatically cleared when PIT64B_WPSR is read.
If one of these flags is set, the PIT64B_ISR.SECE flag is set and can trigger an interrupt if the SECE bit, in the
Interrupt Mask register (PIT64B_IMR), is ‘1’. SECE is cleared by reading PIT64B_ISR.
21.5.5
Register Write Protection
To prevent any single software error from corrupting PIT64B behavior, certain registers in the address space can be
write-protected by setting the WPEN (Write Protection Enable), WPITEN (Write Protection Interrupt Enable), and/or
WPCREN (Write Protection Control Enable) bits in the PIT64B Write Protection Mode Register (PIT64B_WPMR).
If a write access to a write-protected register is detected, the WPVS (Write Protection Violation Status) flag in the
PIT64B Write Protection Status Register (PIT64B_WPSR) is set and the WPVSRC (Write Protection Violation
Source) field indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading PIT64B_WPSR.
The following registers can be write-protected when WPEN is set in PIT64B_WPMR:
•
•
•
PIT64B Mode Register
PIT64B LSB Period Register
PIT64B MSB Period Register
Note: PIT64B LSB Period Register and PIT64B MSB Period Register are not write-protected if
PIT64B_MR.SMOD=1.
The following registers can be write-protected when WPITEN is set in PIT64B_WPMR:
•
•
PIT64B Interrupt Enable Register
PIT64B Interrupt Disable Register
The following register can be write-protected when WPCREN is set in PIT64B_WPMR:
•
PIT64B Control Register
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 191
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6
Register Summary
Offset
Name
0x00
PIT64B_CR
0x04
PIT64B_MR
0x08
PIT64B_LSBPR
0x0C
PIT64B_MSBPR
0x10
PIT64B_IER
0x14
0x18
0x1C
PIT64B_IDR
PIT64B_IMR
PIT64B_ISR
0x20
PIT64B_TLSBR
0x24
PIT64B_TMSBR
0x28
...
0xE3
Reserved
0xE4
0xE8
PIT64B_WPMR
PIT64B_WPSR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
6
5
4
3
2
1
0
SWRST
START
PRESCALER[3:0]
SMOD
SGCLK
LSBPERIOD[31:24]
LSBPERIOD[23:16]
LSBPERIOD[15:8]
LSBPERIOD[7:0]
MSBPERIOD[31:24]
MSBPERIOD[23:16]
MSBPERIOD[15:8]
MSBPERIOD[7:0]
CONT
SECE
OVRE
PERIOD
SECE
OVRE
PERIOD
SECE
OVRE
PERIOD
SECE
LSBTIMER[31:24]
LSBTIMER[23:16]
LSBTIMER[15:8]
LSBTIMER[7:0]
MSBTIMER[31:24]
MSBTIMER[23:16]
MSBTIMER[15:8]
MSBTIMER[7:0]
OVRE
PERIOD
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
FIRSTE
WPCREN
ECLASS
© 2020 Microchip Technology Inc.
WPVSRC[15:8]
WPVSRC[7:0]
SWE
Complete Datasheet
SEQE
WPITEN
WPEN
SWETYP[1:0]
CGD
WPVS
DS60001579C-page 192
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.1
PIT64B Control Register
Name:
Offset:
Reset:
Property:
PIT64B_CR
0x00
–
Write-only
This register can only be written if the WPCREN bit is cleared in the PIT64B Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
SWRST
W
–
7
6
5
4
3
2
1
0
START
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 8 – SWRST Software Reset
Value
Description
0
No effect.
1
Performs a software reset, clears the configuration and stops any timer period in progress.
Bit 0 – START Start Timer
Value
Description
0
No effect.
1
The timer counter is started for 1 or more periods. If the START command is applied during a nonelapsed timer period, there is no effect. Thus, in Continuous mode, the SWRST command is the only
command to stop the PIT64B.
If PIT64B_MR.SMOD=1 a start is also performed as soon as PIT64B_LSBPR is written (see 21.5.2
Single Period Mode and 21.5.3 Continuous Period Mode).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 193
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.2
PIT64B Mode Register
Name:
Offset:
Reset:
Property:
PIT64B_MR
0x04
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the PIT64B Write Protection Mode Register.
When the timer is running, writing a value to this register has no effect. The value written is this register is loaded
anytime before a START command is issued.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
R/W
0
7
6
Access
Reset
5
4
SMOD
R/W
0
3
SGCLK
R/W
0
10
9
PRESCALER[3:0]
R/W
R/W
0
0
2
1
8
R/W
0
0
CONT
R/W
0
Bits 11:8 – PRESCALER[3:0] Prescaler Period
Value
Description
0
A prescaler divider of 1 is used.
1-15
The 64-bit timer is incremented at each (PRESCALER+1)x selected period (see SGCLK).
Bit 4 – SMOD Start Mode
Value
Description
0
Writing PIT64B_LSBPR does not start the timer period.
1
Writing PIT64B_LSBPR starts the timer period.
Bit 3 – SGCLK Generic Clock Selection Enable
If GCLK is asynchronous to the peripheral clock, a jitter of 1 peripheral clock period is created on the periodic interval
event when Continuous mode is selected.
Value
Description
0
The prescaler is triggered at each rising edge of “Peripheral clock” and the timer is triggered.
1
GCLK clock is selected as clock source of the 8-bit prescaler.
Bit 0 – CONT Continuous Mode
Value
Description
0
A single period interrupt is generated from a START command.
1
Continuous periodic interrupts are generated after a single START command.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 194
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.3
PIT64B LSB Period Register
Name:
Offset:
Reset:
Property:
PIT64B_LSBPR
0x08
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the PIT64B Write Protection Mode Register or if
PIT64B_MR.SMOD=1.
When the timer is running, if PIT64B_MR.SMOD=0, writing a value to this register has no effect. The value written is
this register must be loaded anytime before a START command is issued if PIT64B_MR.SMOD=0. If
PIT64B_MR.SMOD=1, a write access to this register restarts a timer period.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
LSBPERIOD[31:24]
R/W
R/W
0
0
20
19
LSBPERIOD[23:16]
R/W
R/W
0
0
12
11
LSBPERIOD[15:8]
R/W
R/W
0
0
4
3
LSBPERIOD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – LSBPERIOD[31:0] 32 LSB of the Timer Period
This field defines the 32 LSB of the timer period. The timer period is defined by selected clock x
{MSBPERIOD,LSBPERIOD}.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 195
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.4
PIT64B MSB Period Register
Name:
Offset:
Reset:
Property:
PIT64B_MSBPR
0x0C
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the PIT64B Write Protection Mode Register.
When the timer is running, if PIT64B_MR.SMOD=0, writing a value to this register has no effect. The value written is
this register must be loaded anytime before a START command is issued if PIT64B_MR.SMOD=0.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
MSBPERIOD[31:24]
R/W
R/W
0
0
20
19
MSBPERIOD[23:16]
R/W
R/W
0
0
12
11
MSBPERIOD[15:8]
R/W
R/W
0
0
4
3
MSBPERIOD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – MSBPERIOD[31:0] 32 MSB of the Timer Period
This field defines the 32 MSB of the timer period. The timer period is defined by selected clock x
{MSBPERIOD,LSBPERIOD}.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 196
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.5
PIT64B Interrupt Enable Register
Name:
Offset:
Reset:
Property:
PIT64B_IER
0x10
–
Write-only
This register can only be written if the WPITEN bit is cleared in the PIT64B Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
SECE
W
–
3
2
1
OVRE
W
–
0
PERIOD
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – SECE Safety and/or Security Report Interrupt Enable
Bit 1 – OVRE Overrun Error Interrupt Enable
Bit 0 – PERIOD Elapsed Timer Period Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 197
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.6
PIT64B Interrupt Disable Register
Name:
Offset:
Reset:
Property:
PIT64B_IDR
0x14
–
Write-only
This register can only be written if the WPITEN bit is cleared in the PIT64B Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
SECE
W
–
3
2
1
OVRE
W
–
0
PERIOD
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – SECE Safety and/or Security Report Interrupt Disable
Bit 1 – OVRE Overrun Error Interrupt Disable
Bit 0 – PERIOD Elapsed Timer Period Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 198
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.7
PIT64B Interrupt Mask Register
Name:
Offset:
Reset:
Property:
PIT64B_IMR
0x18
0x00000000
Read-only
The following configuration values are valid for all listed bit names of this register:
0: Corresponding interrupt is not enabled.
1: Corresponding interrupt is enabled.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
SECE
R
0
3
2
1
OVRE
R
0
0
PERIOD
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – SECE Safety and/or Security Report Interrupt Mask
Bit 1 – OVRE Overrun Error Interrupt Mask
Bit 0 – PERIOD Elapsed Timer Period Interrupt Mask
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 199
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.8
PIT64B Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
PIT64B_ISR
0x1C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
SECE
R
0
3
2
1
OVRE
R
0
0
PERIOD
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – SECE Safety/Security Report (cleared on read)
Value
Description
0
There has been no security report in PIT64B_WPSR since the last read of PIT64B_ISR.
1
One security flag has been set in PIT64B_WPSR since the last read of PIT64B_ISR.
Bit 1 – OVRE Overrun Error (cleared on read)
Value
Description
0
No multiple rollovers occurred since the last read of PIT64B_ISR.
1
More than 1 rollover occurred since the last read of PIT64B_ISR.
Bit 0 – PERIOD Elapsed Timer Period Status Flag (cleared on read)
Value
Description
0
No timer rollover occurred since the last read of PIT64B_ISR.
1
A timer rollover occurred since the last read of PIT64B_ISR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 200
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.9
PIT64B Timer LSB Register
Name:
Offset:
Reset:
Property:
PIT64B_TLSBR
0x20
0x00000000
Read-only
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
28
27
LSBTIMER[31:24]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
LSBTIMER[23:16]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
LSBTIMER[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
LSBTIMER[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 31:0 – LSBTIMER[31:0] Current 32 LSB of the Timer
This field returns the 32 LSB of the current timer value.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 201
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.10 PIT64B Timer MSB Register
Name:
Offset:
Reset:
Property:
PIT64B_TMSBR
0x24
0x00000000
Read-only
When operating with a timer value greater than 32 bits (PIT64B_MSBPR.MSBPERIOD > 0), the PIT64B_TLSBR
must be read first, followed by the read of PIT64B_TMSBR. This sequence generates an atomic read of the 64-bit
timer value whatever the lapse of time between the accesses. When operating with a timer value up to 32 bits
(PIT64B_MSBPR.MSBPERIOD=0), reading PIT64B_TMSBR is not required.
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
28
27
MSBTIMER[31:24]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
MSBTIMER[23:16]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
MSBTIMER[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
MSBTIMER[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 31:0 – MSBTIMER[31:0] Current 32 MSB of the Timer
This field returns the 32 MSB of the current timer value.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 202
SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.11 PIT64B Write Protection Mode Register
Name:
Offset:
Reset:
Property:
PIT64B_WPMR
0xE4
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
FIRSTE
R/W
0
3
2
WPCREN
R/W
0
1
WPITEN
R/W
0
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x504954 PASSWD Writing any other value in this field aborts the write operation of the WPCREN, WPITEN and
WPEN bits. Always reads as 0.
Bit 4 – FIRSTE First Error Report Enable
Value
Description
0
The last write protection violation source is reported in PIT64B_WPSR.WPVSRC and the last software
control error type is reported in PIT64B_WPSR.SWETYP. The PIT64B_ISR.SECE flag is set at the first
error occurring within a series.
1
Only the first write protection violation source is reported in PIT64B_WPSR.WPVSRC and only the first
software control error type is reported in PIT64B_WPSR.SWETYP. The PIT64B_ISR.SECE flag is set
at the first error occurring within a series.
Bit 2 – WPCREN Write Protection Control Enable
Value
Description
0
Disables the write protection on control register if WPKEY corresponds to 0x504954 (“PIT” in ASCII).
1
Enables the write protection on control register if WPKEY corresponds to 0x504954 (“PIT” in ASCII).
Bit 1 – WPITEN Write Protection Interruption Enable
Value
Description
0
Disables the write protection on interrupt registers if WPKEY corresponds to 0x504954 (“PIT” in ASCII).
1
Enables the write protection on interrupt registers if WPKEY corresponds to 0x504954 (“PIT” in ASCII).
Bit 0 – WPEN Write Protection Enable
See Section 6.5 “Register Write Protection” for the list of registers that can be protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x504954 (“PIT” in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x504954 (“PIT” in ASCII).
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SAM9X60
64-bit Periodic Interval Timer (PIT64B)
21.6.12 PIT64B Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
PIT64B_WPSR
0xE8
0x00000000
Read-only
31
ECLASS
R
0
30
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
Bit
7
6
Access
Reset
29
28
27
26
25
24
SWETYP[1:0]
Access
Reset
R
0
R
0
20
19
WPVSRC[15:8]
R
R
0
0
18
17
16
R
0
R
0
R
0
10
9
8
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
5
4
2
SEQE
R
0
1
CGD
R
0
0
WPVS
R
0
3
SWE
R
0
Bit 31 – ECLASS Software Error Class (cleared on read)
0 (WARNING): An abnormal access that does not affect system functionality.
1 (ERROR): A write access is performed into PIT64B_MR, PIT64B_LSBR, PIT64B_MSBR while the PIT64B is
running.
Bits 25:24 – SWETYP[1:0] Software Error Type (cleared on read)
Value
Name
Description
0
READ_WO
A write-only register has been read (warning).
1
WRITE_RO
A write access has been performed on a read-only register (warning).
2
UNDEF_RW
Access to an undefined address (warning).
3
WEIRD_ACTION A write access is performed into PIT64B_MR, PIT64B_LSBR, PIT64B_MSBR while
the PIT64B is running (abnormal).
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS=1, WPVSRC indicates the register address offset at which a write access has been attempted.
When WPVS=0 and SWE=1, WPVSRC reports the address of the incorrect software access. As soon as WPVS=1,
WPVSRC returns the address of the write-protected violation.
Bit 3 – SWE Software Control Error (cleared on read)
Value
Description
0
No software error has occurred since the last read of PIT64B_WPSR.
1
A software error has occurred since the last read of PIT64B_WPSR. The field SWETYP details the
type of software error; the associated incorrect software access is reported in the field WPVSRC (if
WPVS=0).
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
Value
Description
0
No peripheral internal sequencer error has occurred since the last read of PIT64B_WPSR.
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SAM9X60
64-bit Periodic Interval Timer (PIT64B)
Value
1
Description
A peripheral internal sequencer error has occurred since the last read of PIT64B_WPSR. This flag can
only be set under abnormal operating conditions.
Bit 1 – CGD Clock Glitch Detected (cleared on read)
Value
Description
0
The clock monitoring circuitry has not been corrupted since the last read of PIT64B_WPSR. Under
normal operating conditions, this bit is always cleared.
1
The clock monitoring circuitry has been corrupted since the last read of PIT64B_WPSR. This flag can
only be set in case of abnormal clock signal waveform (glitch).
Bit 0 – WPVS Write Protection Violation Status (cleared on read)
Value
Description
0
No write protection violation has occurred since the last read of the PIT64B_WPSR.
1
A write protection violation has occurred since the last read of the PIT64B_WPSR. If this violation is an
unauthorized attempt to write a protected register, the associated violation is reported into field
WPVSRC.
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SAM9X60
Debug Unit (DBGU)
22.
Debug Unit (DBGU)
22.1
Description
The Debug Unit (DBGU) provides a single entry point from the processor for access to all the debug capabilities of
the product.
The DBGU features a two-pin UART that can be used for communication and trace purposes and offers an ideal
medium for in-situ programming solutions.
Moreover, the association with a DMA controller permits packet handling for these tasks with processor time reduced
to a minimum.
The DBGU also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the
ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and
generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control.
Chip identifier registers permit recognition of the device and its revision. These registers indicate the sizes and types
of the on-chip memories, as well as the set of embedded peripherals.
A Force NTRST capability enables the software to decide whether to prevent access to the system via the In-circuit
Emulator (ICE). This disables system access through the processor’s ICE, thus protecting the code stored in ROM by
asserting the NTRST line of the processor’s ICE.
22.2
Embedded Characteristics
•
•
•
•
ICE Access Prevention
Debug Communication Channel (DCC) Support
Chip ID Registers
Two-pin UART
– Independent receiver and transmitter with a common programmable baud rate generator
– Baud rate can be driven by processor-independent generic source clock
– Even, odd, mark or space parity generation
– Parity, framing and overrun error detection
– Automatic Echo, Local loopback and Remote Loopback Channel modes
– Digital filter on receive line
– Interrupt generation
– Support for two DMA channels with connection to receiver and transmitter
– Receiver timeout
– Register write protection
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SAM9X60
Debug Unit (DBGU)
22.3
Block Diagram
Figure 22-1. DBGU Block Diagram
DBGU
UART
DTXD
tx trigger
rx trigger
DMA
Controller
Transmit
Baud Rate
Generator
Receive
bus clock
Parallel
Input/
Output
DRXD
Bridge
System Bus
User
Interface
Interrupt
Control
GCLKx
PMC
peripheral clock
COMMRX
COMMTX
ARM
Processor
DCC
Handler
CHIP
ID
nTRST
Power-on
Reset
dbgu
interrupt
line
ICE
Access
Handler
force_ntrst
Table 22-1. DBGU Pin Description
22.4
22.4.1
Pin Name
Description
Type
DRXD
DBGU Receive Data
Input
DTXD
DBGU Transmit Data
Output
Product Dependencies
I/O Lines
The DBGU pins are multiplexed with PIO lines. The user must first configure the corresponding PIO Controller to
enable I/O line operations of the DBGU.
22.4.2
Power Management
The DBGU clock can be controlled through the Power Management Controller (PMC). In this case, the user must first
configure the PMC to enable the DBGU clock.
22.4.3
Interrupt Sources
The DBGU interrupt line is connected to one of the interrupt sources of the Interrupt Controller. Interrupt handling
requires programming of the Interrupt Controller before configuring the DBGU.
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SAM9X60
Debug Unit (DBGU)
22.5
Functional Description
The DBGU operates in Asynchronous mode only and supports only 8-bit character handling (with parity). It has no
clock pin.
The DBGU is made up of a receiver and a transmitter that operate independently, and a common baud rate
generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features
are compatible with those of a standard USART.
22.5.1
Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter.
The baud rate clock is the peripheral clock divided by 16 times the clock divisor (CD) value written in the Baud Rate
Generator register (DBGU_BRGR). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the DBGU
remains inactive. The maximum allowable baud rate is peripheral clock or GCLK divided by 16. The minimum
allowable baud rate is peripheral clock divided by (16 x 65536). The clock source driving the baud rate generator
(peripheral clock or GCLK) can be selected by writing the bit BRSRCCK in DBGU_MR.
If GCLK is selected, the baud rate is independent of the processor/bus clock. Thus the processor clock can be
changed while DBGU is enabled. The processor clock frequency changes must be performed only by programming
the field PRES in PMC_MCKR (see PMC section). Other methods to modify the processor/bus clock frequency (PLL
multiplier, etc.) are forbidden when DBGU is enabled.
The peripheral clock frequency must be at least three times higher than GCLK.
Figure 22-2. Baud Rate Generator
BRSRCCK
CD
CD
Peripheral clock
0
16-bit Counter
GCLK
OUT
>1
1
1
0
0
Divide
by 16
Baud Rate
Clock
Receiver
Sampling Clock
22.5.2
Receiver
22.5.2.1 Receiver Reset, Enable and Disable
After device reset, the DBGU receiver is disabled and must be enabled before being used. The receiver can be
enabled by writing the Control Register (DBGU_CR) with the bit RXEN at 1. At this command, the receiver starts
looking for a start bit.
The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a
start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it
waits for the stop bit before actually stopping its operation.
The receiver can be put in reset state by writing DBGU_CR with the bit RSTRX at 1. In this case, the receiver
immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is
being processed, this data is lost.
22.5.2.2 Start Detection and Data Sampling
The DBGU only supports asynchronous operations, and this affects only its receiver. The DBGU receiver detects the
start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on
DRXD is interpreted as a valid start bit if it is detected for more than seven cycles of the sampling clock, which is 16
times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space
which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
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SAM9X60
Debug Unit (DBGU)
When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is
assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles
(0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after detecting
the falling edge of the start bit.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 22-3. Start Bit Detection
DRXD
S
D0
D1 D2
D3
D4 D5 D6
D7
P
D0
stop S
D1 D2
D3 D4
D5
D6
D7
P stop
RXRDY
OVRE
RSTSTA
Figure 22-4. Character Reception
Example: 8-bit, parity enabled 1 stop
0.5 bit
period
1 bit
period
DRXD
Sampling
D0
D1
True Start Detection
D2
D3
D4
D5
D6
D7
Stop Bit
Parity Bit
22.5.2.3 Receiver Ready
When a complete character is received, it is transferred to the Receive Holding Register (DBGU_RHR) and the
RXRDY status bit in the Status Register (DBGU_SR) is set. The bit RXRDY is automatically cleared when
DBGU_RHR is read.
Figure 22-5. Receiver Ready
DRXD
S
D0
D1
D2
D3
D4
D5
D6
D7
S
P
D0
D1
D2
D3
D4
D5
D6
D7
P
RXRDY
Read UART_RHR
22.5.2.4 Receiver Overrun
The OVRE status bit in DBGU_SR is set if DBGU_RHR has not been read by the software (or the DMA Controller)
since the last transfer, the RXRDY bit is still set and a new character is received. OVRE is cleared when the software
writes a 1 to the bit RSTSTA (Reset Status) in DBGU_CR.
Figure 22-6. Receiver Overrun
DRXD
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
RXRDY
OVRE
RSTSTA
22.5.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the
field PAR in the Mode Register (DBGU_MR). It then compares the result with the received parity bit. If different, the
parity error bit PARE in DBGU_SR is set at the same time RXRDY is set. The parity bit is cleared when DBGU_CR is
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Complete Datasheet
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SAM9X60
Debug Unit (DBGU)
written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is
written, the PARE bit remains at 1.
Figure 22-7. Parity Error
DRXD
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
RXRDY
PARE
Wrong Parity Bit
RSTSTA
22.5.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop
bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time
the RXRDY bit is set. The FRAME bit remains high until the Control Register (DBGU_CR) is written with the bit
RSTSTA at 1.
Figure 22-8. Receiver Framing Error
DRXD
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
RXRDY
FRAME
Stop Bit
Detected at 0
RSTSTA
22.5.2.7 Receiver Digital Filter
The DBGU embeds a digital filter on the receive line. It is disabled by default and can be enabled by writing a logical
1 in the FILTER bit of DBGU_MR. When enabled, the receive line is sampled using the 16x bit clock and a threesample filter (majority 2 over 3) determines the value of the line.
22.5.2.8 Receiver Timeout
The Receiver Timeout provides support in handling variable-length frames. This feature detects an idle condition on
the DRXD line. When a timeout is detected, the bit TIMEOUT in DBGU_SR rises and can generate an interrupt, thus
indicating to the driver an end of frame.
The timeout delay period (during which the receiver waits for a new character) is programmed in the TO field of the
Receiver Timeout register (DBGU_RTOR). If the TO field is written to 0, the Receiver Timeout is disabled and no
timeout is detected. The TIMEOUT bit remains at 0. Otherwise, the receiver loads an 8-bit counter with the value
programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit rises. Then, the user can either:
•
•
stop the counter clock until a new character is received. This is performed by writing a one to the STTTO (Start
timeout) bit in DBGU_CR. In this case, the idle state on DRXD before a new character is received does not
provide a timeout. This prevents having to handle an interrupt before a character is received and allows waiting
for the next idle state on DRXD after a frame is received, or
obtain an interrupt while no character is received. This is performed by writing a one to the RETTO (Reload and
start timeout) bit in DBGU_CR. If RETTO is performed, the counter starts counting down immediately from the
TO value. This enables generation of a periodic interrupt so that a user timeout can be handled, for example
when no key is pressed on a keyboard.
If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on DRXD before
the start of the frame does not provide a timeout. This prevents having to obtain a periodic interrupt and enables a
wait of the end of frame when the idle state on DRXD is detected.
If RETTO is performed, the counter starts counting down immediately from the TO value. This enables generation of
a periodic interrupt so that a user timeout can be handled, for example when no key is pressed on a keyboard.
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SAM9X60
Debug Unit (DBGU)
The following figure shows the block diagram of the Receiver Timeout feature.
Figure 22-9. Receiver Timeout Block Diagram
TO
Baud Rate
Clock
1
D
Clock
Q
8-bit Time-out
Counter
8-bit
Value
=
STTTO
Character
Received
Load
Clear
TIMEOUT
0
RETTO
The following table gives the maximum timeout period for some standard baud rates.
Table 22-2. Maximum Timeout Period
22.5.3
Baud Rate (bit/s)
Bit Time (μs)
Timeout (μs)
600
1,667
425,085
1,200
833
212,415
2,400
417
106,335
4,800
208
53,040
9,600
104
26,520
14,400
69
17,595
19,200
52
13,260
28,800
35
8,925
38,400
26
6,630
56,000
18
4,590
57,600
17
4,335
200,000
5
1,275
Transmitter
22.5.3.1 Transmitter Reset, Enable and Disable
After device reset, the DBGU transmitter is disabled and must be enabled before being used. The transmitter is
enabled by writing DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be
written in the Transmit Holding Register (DBGU_THR) before actually starting the transmission.
The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stopped. However, if a character is being processed into the internal shift register and/or a
character has been written in the DBGU_THR, the characters are completed before the transmitter is actually
stopped.
The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This
immediately stops the transmitter, whether or not it is processing characters.
22.5.3.2 Transmit Format
The DBGU transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format
defined in DBGU_MR and the data stored in the internal shift register. One start bit at level 0, then the 8 data bits,
from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown
in the following figure. The field PARE in DBGU_MR defines whether or not a parity bit is shifted out. When a parity
bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.
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SAM9X60
Debug Unit (DBGU)
Figure 22-10. Character Transmission
Example: Parity enabled
Baud Rate
Clock
UTXD
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
22.5.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in DBGU_SR. The transmission starts
when the programmer writes in the DBGU_THR, and after the written character is transferred from DBGU_THR to
the internal shift register. The TXRDY bit remains high until a second character is written in DBGU_THR. As soon as
the first character is completed, the last character written in DBGU_THR is transferred into the internal shift register
and TXRDY rises again, showing that the holding register is empty.
When both the internal shift register and DBGU_THR are empty, i.e., all the characters written in DBGU_THR have
been processed, the TXEMPTY bit rises after the last stop bit has been completed.
Figure 22-11. Transmitter Control
UART_THR
Data 0
Data 1
Shift Register
DTXD
Data 0
Data 0
S
Data 1
P
stop
S
Data 1
P
stop
TXRDY
TXEMPTY
Write Data 0
in UART_THR
22.5.4
Write Data 1
in UART_THR
DMA Support
Both the receiver and the transmitter of the DBGU are connected to a DMA Controller (DMAC) channel.
The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface.
22.5.5
Register Write Protection
To prevent any single software error from corrupting DBGU behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the DBGU Write Protection Mode Register.
The following registers can be write-protected:
•
•
•
•
22.5.6
DBGU Mode Register
DBGU Baud Rate Generator Register
DBGU Receiver Timeout Register
Debug Unit Force NTRST Register
Test Modes
The DBGU supports three test modes. These modes of operation are programmed by using the CHMODE field in
DBGU_MR.
The Automatic Echo mode allows a bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to
the DTXD line. The transmitter operates normally, but has no effect on the DTXD line.
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SAM9X60
Debug Unit (DBGU)
The Local loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and
the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and
the DTXD line is held high, as in idle state.
The Remote loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are
disabled and have no effect. This mode allows a bit-by-bit retransmission.
Figure 22-12. Test Modes
Automatic Echo
DRXD
Receiver
Transmitter
Disabled
DTXD
Local Loopback
Disabled
Receiver
DRXD
VDD
Disabled
Transmitter
Remote Loopback
VDD
Receiver
Transmitter
22.5.7
DTXD
Disabled
Disabled
DRXD
DTXD
Debug Communication Channel Support
The DBGU handles the COMMRX and COMMTX signals that come from the Debug Communication Channel of the
ARM processor and are driven by the In-circuit Emulator.
The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG
side and through the coprocessor 0 on the ARM processor side.
As a reminder, the following instructions are used to read and write the Debug Communication Channel:
MRC p14, 0, Rd, c1, c0, 0
Returns the debug communication data read register into Rd
MCR p14, 0, Rd, c1, c0, 0
Writes the value in Rd to the debug communication data write register.
The COMMRX and COMMTX bits which indicate, respectively, that the read register has been written by the
debugger but not yet read by the processor, and that the write register has been written by the processor and not yet
read by the debugger, are wired on the two highest bits of DBGU_SR. These bits can generate an interrupt. This
feature can be used to handle under interrupt a debug link between a debug monitor running on the target system
and a debugger.
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SAM9X60
Debug Unit (DBGU)
22.5.8
Chip Identifier
The DBGU features two chip identifier registers, DBGU Chip ID Register (DBGU_CIDR) and DBGU Extension ID
Register (DBGU_EXID). Both registers contain a hard-wired value that is read-only.
22.5.9
ICE Access Prevention
The DBGU allows blockage of access to the system through the ARM processor's ICE interface. This feature is
implemented via the Force NTRST Register (DBGU_FNR), that allows assertion of the NTRST signal of the ICE
Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller.
On standard devices, the FNTRST bit resets to 0 and thus does not prevent ICE access.
This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be
visible.
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SAM9X60
Debug Unit (DBGU)
22.6
Register Summary
Offset
Name
0x00
DBGU_CR
0x04
DBGU_MR
0x08
DBGU_IER
0x0C
0x10
0x14
0x18
0x1C
DBGU_IDR
DBGU_IMR
DBGU_SR
DBGU_RHR
DBGU_THR
0x20
DBGU_BRGR
0x24
...
0x27
Reserved
0x28
0x2C
...
0x3F
DBGU_RTOR
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
5
4
3
2
TXDIS
TXEN
RXDIS
RXEN
STTTO
RSTTX
RETTO
RSTRX
CHMODE[1:0]
BRSRCCK
FILTER
1
0
RSTSTA
PAR[2:0]
COMMRX
COMMTX
PARE
COMMRX
FRAME
COMMTX
OVRE
TXEMPTY
TXRDY
TIMEOUT
RXRDY
PARE
COMMRX
FRAME
COMMTX
OVRE
TXEMPTY
TXRDY
TIMEOUT
RXRDY
PARE
COMMRX
FRAME
COMMTX
OVRE
TXEMPTY
TXRDY
TIMEOUT
RXRDY
PARE
FRAME
OVRE
TXEMPTY
TXRDY
TIMEOUT
RXRDY
RXCHR[7:0]
TXCHR[7:0]
CD[15:8]
CD[7:0]
31:24
23:16
15:8
7:0
TO[7:0]
Reserved
0x40
DBGU_CIDR
0x44
DBGU_EXID
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
EXT
© 2020 Microchip Technology Inc.
CHID[30:24]
CHID[23:16]
CHID[15:8]
CHID[7:0]
EXID[31:24]
EXID[23:16]
EXID[15:8]
EXID[7:0]
Complete Datasheet
DS60001579C-page 215
SAM9X60
Debug Unit (DBGU)
...........continued
Offset
Name
Bit Pos.
0x48
DBGU_FNR
31:24
23:16
15:8
7:0
0x4C
...
0xE3
0xE4
7
6
5
4
3
2
1
0
FNTRST
Reserved
DBGU_WPMR
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WPEN
Complete Datasheet
DS60001579C-page 216
SAM9X60
Debug Unit (DBGU)
22.6.1
DBGU Control Register
Name:
Offset:
Reset:
Property:
Bit
DBGU_CR
0x0000
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
STTTO
W
–
10
RETTO
W
–
9
8
RSTSTA
W
–
7
TXDIS
W
–
6
TXEN
W
–
5
RXDIS
W
–
4
RXEN
W
–
3
RSTTX
W
–
2
RSTRX
W
–
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – STTTO Start Timeout
Value
Description
0
No effect.
1
Starts waiting for a character before clocking the timeout counter. Resets status bit
DBGU_SR.TIMEOUT.
Bit 10 – RETTO Rearm Timeout
Value
Description
0
No effect.
1
Restarts timeout.
Bit 8 – RSTSTA Reset Status
Value
Description
0
No effect.
1
Resets the status bits PARE, FRAME and OVRE in DBGU_SR.
Bit 7 – TXDIS Transmitter Disable
Value
Description
0
No effect.
1
The transmitter is disabled. If a character is being processed and a character has been written in
DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.
Bit 6 – TXEN Transmitter Enable
Value
Description
0
No effect.
1
The transmitter is enabled if TXDIS is 0.
Bit 5 – RXDIS Receiver Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Debug Unit (DBGU)
Value
0
1
Description
No effect.
The receiver is disabled. If a character is being processed and RSTRX is not set, the character is
completed before the receiver is stopped.
Bit 4 – RXEN Receiver Enable
Value
Description
0
No effect.
1
The receiver is enabled if RXDIS is 0.
Bit 3 – RSTTX Reset Transmitter
Value
Description
0
No effect.
1
The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is
aborted.
Bit 2 – RSTRX Reset Receiver
Value
Description
0
No effect.
1
The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
© 2020 Microchip Technology Inc.
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SAM9X60
Debug Unit (DBGU)
22.6.2
DBGU Mode Register
Name:
Offset:
Reset:
Property:
Bit
DBGU_MR
0x0004
0x0000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
BRSRCCK
R/W
0
11
9
8
R/W
0
10
PAR[2:0]
R/W
0
R/W
0
3
2
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
15
14
CHMODE[1:0]
R/W
R/W
0
0
7
6
5
4
FILTER
R/W
0
Access
Reset
Bits 15:14 – CHMODE[1:0] Channel Mode
Value
Name
0
NORMAL
1
AUTOMATIC
2
LOCAL_LOOPBACK
3
REMOTE_LOOPBACK
0
Description
Normal mode
Automatic echo
Local loopback
Remote loopback
Bit 12 – BRSRCCK Baud Rate Source Clock
0 (PERIPH_CLK): The baud rate is driven by the peripheral clock
1 (GCLK): The baud rate is driven by a PMC-programmable clock GCLK (see section Power Management Controller
(PMC)).
Bits 11:9 – PAR[2:0] Parity Type
Value
Name
0
EVEN
1
ODD
2
SPACE
3
MARK
4
NO
Description
Even Parity
Odd Parity
Space: parity forced to 0
Mark: parity forced to 1
No parity
Bit 4 – FILTER Receiver Digital Filter
0 (DISABLED): DBGU does not filter the receive line.
1 (ENABLED): DBGU filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 219
SAM9X60
Debug Unit (DBGU)
22.6.3
DBGU Interrupt Enable Register
Name:
Offset:
Reset:
Property:
DBGU_IER
0x0008
–
Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
Access
Reset
Bit
31
COMMRX
W
–
30
COMMTX
W
–
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
TXEMPTY
W
–
8
TIMEOUT
W
–
7
PARE
W
–
6
FRAME
W
–
5
OVRE
W
–
4
3
2
1
TXRDY
W
–
0
RXRDY
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 31 – COMMRX Enable COMMRX (from ARM) Interrupt
Bit 30 – COMMTX Enable COMMTX (from ARM) Interrupt
Bit 9 – TXEMPTY Enable TXEMPTY Interrupt
Bit 8 – TIMEOUT Enable Timeout Interrupt
Bit 7 – PARE Enable Parity Error Interrupt
Bit 6 – FRAME Enable Framing Error Interrupt
Bit 5 – OVRE Enable Overrun Error Interrupt
Bit 1 – TXRDY Enable TXRDY Interrupt
Bit 0 – RXRDY Enable RXRDY Interrupt
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 220
SAM9X60
Debug Unit (DBGU)
22.6.4
DBGU Interrupt Disable Register
Name:
Offset:
Reset:
Property:
DBGU_IDR
0x000C
–
Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
Access
Reset
Bit
31
COMMRX
W
–
30
COMMTX
W
–
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
TXEMPTY
W
–
8
TIMEOUT
W
–
7
PARE
W
–
6
FRAME
W
–
5
OVRE
W
–
4
3
2
1
TXRDY
W
–
0
RXRDY
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 31 – COMMRX Disable COMMRX (from ARM) Interrupt
Bit 30 – COMMTX Disable COMMTX (from ARM) Interrupt
Bit 9 – TXEMPTY Disable TXEMPTY Interrupt
Bit 8 – TIMEOUT Disable Timeout Interrupt
Bit 7 – PARE Disable Parity Error Interrupt
Bit 6 – FRAME Disable Framing Error Interrupt
Bit 5 – OVRE Disable Overrun Error Interrupt
Bit 1 – TXRDY Disable TXRDY Interrupt
Bit 0 – RXRDY Disable RXRDY Interrupt
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 221
SAM9X60
Debug Unit (DBGU)
22.6.5
DBGU Interrupt Mask Register
Name:
Offset:
Reset:
Property:
DBGU_IMR
0x0010
0x0000000
Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Bit
Access
Reset
Bit
31
COMMRX
R
0
30
COMMTX
R
0
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
TXEMPTY
R
0
8
TIMEOUT
R
0
7
PARE
R
0
6
FRAME
R
0
5
OVRE
R
0
4
3
2
1
TXRDY
R
0
0
RXRDY
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 31 – COMMRX Mask COMMRX (from ARM) Interrupt
Bit 30 – COMMTX Mask COMMTX (from ARM) Interrupt
Bit 9 – TXEMPTY Mask TXEMPTY Interrupt
Bit 8 – TIMEOUT Mask Timeout Interrupt
Bit 7 – PARE Mask Parity Error Interrupt
Bit 6 – FRAME Mask Framing Error Interrupt
Bit 5 – OVRE Mask Overrun Error Interrupt
Bit 1 – TXRDY Disable TXRDY Interrupt
Bit 0 – RXRDY Mask RXRDY Interrupt
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 222
SAM9X60
Debug Unit (DBGU)
22.6.6
DBGU Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
DBGU_SR
0x0014
–
Read-only
31
COMMRX
R
–
30
COMMTX
R
–
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
TXEMPTY
R
–
8
TIMEOUT
R
–
7
PARE
R
–
6
FRAME
R
–
5
OVRE
R
–
4
3
2
1
TXRDY
R
–
0
RXRDY
R
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 31 – COMMRX Debug Communication Channel Read Status
Value
Description
0
COMMRX from the ARM processor is inactive.
1
COMMRX from the ARM processor is active.
Bit 30 – COMMTX Debug Communication Channel Write Status
Value
Description
0
COMMTX from the ARM processor is inactive.
1
COMMTX from the ARM processor is active.
Bit 9 – TXEMPTY Transmitter Empty
Value
Description
0
There are characters in DBGU_THR, or characters are being processed by the transmitter, or the
transmitter is disabled.
1
There are no characters in DBGU_THR and there are no characters being processed by the
transmitter.
Bit 8 – TIMEOUT Receiver Timeout
Value
Description
0
There has not been any timeout since the last Start timeout command (DBGU_CR.STTTO), or the
Timeout register is 0.
1
There has been a timeout since the last Start timeout command (DBGU_CR.STTTO).
Bit 7 – PARE Parity Error
Value
Description
0
No parity error has occurred since the last RSTSTA.
1
At least one parity error has occurred since the last RSTSTA.
Bit 6 – FRAME Framing Error
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Debug Unit (DBGU)
Value
0
1
Description
No framing error has occurred since the last RSTSTA.
At least one framing error has occurred since the last RSTSTA.
Bit 5 – OVRE Overrun Error
Value
Description
0
No overrun error has occurred since the last RSTSTA.
1
At least one overrun error has occurred since the last RSTSTA.
Bit 1 – TXRDY Transmitter Ready
Value
Description
0
A character has been written to DBGU_THR and not yet transferred to the internal shift register, or the
transmitter is disabled.
1
There is no character written to DBGU_THR that is not yet transferred to the internal shift register.
Bit 0 – RXRDY Receiver Ready
Value
Description
0
No character has been received since the last read of DBGU_RHR, or the receiver is disabled.
1
At least one complete character has been received, transferred to DBGU_RHR, and not yet read.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 224
SAM9X60
Debug Unit (DBGU)
22.6.7
DBGU Receiver Holding Register
Name:
Offset:
Reset:
Property:
Bit
DBGU_RHR
0x0018
0x0000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
RXCHR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – RXCHR[7:0] Received Character
Last received character if RXRDY is set.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 225
SAM9X60
Debug Unit (DBGU)
22.6.8
DBGU Transmit Holding Register
Name:
Offset:
Reset:
Property:
Bit
DBGU_THR
0x001C
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
–
W
–
W
–
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
TXCHR[7:0]
Access
Reset
W
–
W
–
W
–
W
–
Bits 7:0 – TXCHR[7:0] Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 226
SAM9X60
Debug Unit (DBGU)
22.6.9
DBGU Baud Rate Generator Register
Name:
Offset:
Reset:
Property:
Bit
DBGU_BRGR
0x0020
0x0000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
CD[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CD[15:0] Clock Divisor
Value
Description
0
Baud rate clock is disabled.
1
1 to 65,535:
If BRSRCCK = 0:
CD =
f peripheral clock
16 × Baud Rate
CD =
f GCLKx
16 × Baud Rate
If BRSRCCK = 1:
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Debug Unit (DBGU)
22.6.10 DBGU Receiver Timeout Register
Name:
Offset:
Reset:
Property:
Bit
DBGU_RTOR
0x0028
0x0000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
TO[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TO[7:0] Timeout Value
Value
Description
0
The receiver timeout is disabled.
1–255
The receiver timeout is enabled and the timeout delay is TO x bit period.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Debug Unit (DBGU)
22.6.11 DBGU Chip ID Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
DBGU_CIDR
0x0040
0x819B35A1
Read-only
31
EXT
R
30
29
28
R
R
R
23
22
21
20
27
CHID[30:24]
R
26
25
24
R
R
R
19
18
17
16
R
R
R
R
11
10
9
8
R
R
R
R
3
2
1
0
R
R
R
R
CHID[23:16]
Access
Reset
R
R
R
R
Bit
15
14
13
12
CHID[15:8]
Access
Reset
R
R
R
R
Bit
7
6
5
4
CHID[7:0]
Access
Reset
R
R
R
R
Bit 31 – EXT Extension Flag
Value
Description
0
Chip ID has a single register definition without extension.
1
An extended Chip ID exists.
Bits 30:0 – CHID[30:0] Chip ID Value
© 2020 Microchip Technology Inc.
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SAM9X60
Debug Unit (DBGU)
22.6.12 DBGU Chip ID Extension Register
Name:
Offset:
Reset:
Property:
Bit
31
DBGU_EXID
0x0044
–
Read-only
30
29
28
27
26
25
24
R
–
R
–
R
–
R
–
19
18
17
16
R
–
R
–
R
–
R
–
11
10
9
8
R
–
R
–
R
–
R
–
3
2
1
0
R
–
R
–
R
–
R
–
EXID[31:24]
Access
Reset
R
–
R
–
R
–
R
–
Bit
23
22
21
20
EXID[23:16]
Access
Reset
R
–
R
–
R
–
R
–
Bit
15
14
13
12
EXID[15:8]
Access
Reset
R
–
R
–
R
–
R
–
Bit
7
6
5
4
EXID[7:0]
Access
Reset
R
–
R
–
R
–
R
–
Bits 31:0 – EXID[31:0] Chip ID Extension
Read as 0 if the bit EXT in DBGU_CIDR is 0.
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Complete Datasheet
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SAM9X60
Debug Unit (DBGU)
22.6.13 Debug Unit Force NTRST Register
Name:
Offset:
Reset:
Property:
Bit
DBGU_FNR
0x0048
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FNTRST
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – FNTRST Force NTRST
Value
Description
0
NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal.
1
NTRST of the ARM processor’s TAP controller is held low.
© 2020 Microchip Technology Inc.
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SAM9X60
Debug Unit (DBGU)
22.6.14 DBGU Write Protection Mode Register
Name:
Offset:
Reset:
Property:
DBGU_WPMR
0x00E4
0x0000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x554152
PASSWD
Writing any other value in this field aborts the write operation.
Always reads as 0.
Bit 0 – WPEN Write Protection Enable
See Register Write Protection for the list of registers that can be protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x554152 (DBGU in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x554152 (DBGU in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
OTP Memory Controller (OTPC)
23.
23.1
OTP Memory Controller (OTPC)
Description
The OTP Memory Controller (OTPC) is the secure interface between the system and the OTP memory.
The default value of a memory bit is logic ‘0’ (not programmed). A programmed memory bit is logic ‘1’.
An OTP matrix is a type of non-volatile memory. Each bit in the matrix can be programmed only once. The bits are
used to store data such as:
•
•
•
•
•
23.2
calibration bits for analog cells (e.g. RC oscillators, etc.),
hardware configuration settings (e.g. JTAG disable, etc.),
chip identifiers,
key data invisible by software,
user data.
Embedded Characteristics
•
•
•
•
•
Programs and Reads the Memory by Software
Emulation Mode
Automatic Check of Programmed Bits on Startup for Safe Operation
User Area Organized by Packet for Flexibility on Size and Security:
– Individual packet locking possibility (with checksum check)
– Individual packet read access through only Private Key bus or System bus
– Individual packet hiding (for packet with System bus access only)
– Individual packet size of 32 bits to 8192 bits in 32-bit steps
– Individual packet invalidation
Firewall: Software/Hardware Protection Against Unexpected Read/Write
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
OTP Memory Controller (OTPC)
23.3
Block Diagram
Figure 23-1. OTPC Block Diagram
Emulation Memory
On-die SRAM
Router
System Bus Master Interface
FSM
(Controller)
OTP Memory
Slave Private Key Bus
RAM 8192bits
Crypto Engines
Hardware Configuration
Interrupt
23.4
Functional Description
23.4.1
Bus Interfaces
Analog Cells Trimming,
JTAG Port Disable
Emulation
Data
Registers
TRNG
Master Private Key Bus
HW Config. Reg.
Firewall
Private
Key Bus
Interfaces
User Interface
System Bus Slave Interface
System Bus
OTPC
(OTP Memory Controller)
Interrupt
Controller
The OTPC features four bus interfaces to access the OTP memory:
•
•
•
•
Master System bus
Slave System bus
Master Key bus (Private Key bus)
Slave Key bus (Private Key bus)
The Master System bus is used in Emulation mode to write and read data to/from the Emulation memory instead of
the OTP memory. The Master System bus can only access the Emulation memory.
The Slave System bus is available to access to the user interface.
The Master Key bus is available to read keys stored in the User area of the OTP memory and transfer them to the
slave crypto-engines connected to this bus (e.g. AES). No data accessible to the Master Key bus are accessible to
the System bus.
The Slave Key bus is available to write some data to the User area of the OTP memory. No data coming from the
Slave Key bus are accessible to the System bus.
23.4.2
OTP Memory Partitioning
The OTP memory is partitioned into different areas:
•
•
Reserved area
11-Kbyte User area
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
OTP Memory Controller (OTPC)
The initial value of the OTP memory is ‘0’ but the memory may contain some “defective” bits already set to the
value ‘1’.
The memory is organized into 32-bit words.
23.4.3
User Area
23.4.3.1 Area Configuration and Control
The User area is controlled and configured through the OTPC Control (OTPC_CR), OTPC Mode (OTPC_MR) and
OTPC Data (OTPC_DR) registers.
23.4.3.2 Area Mapping
The entire User area space is mapped into 32-bit words. Each 32-bit word is part of one packet.
Each packet contains a 32-bit header and 32-bit words of payload (data). The number of payload words is defined in
the header.
This mapping system allows three important functions for an OTP memory:
• Gives a flexible size for any type of data
• Improves the security by identifying and masking key areas to the System bus,
• Provides an easy way to invalidate a packet and create a replacement packet (key, data) while free space is
available in OTP.
The packet organization into the User area is shown in the figure below.
Figure 23-2. User Area Memory Mapping
31
0x00
0
Header 0
...
0x01
Payload 0
Header 1
Payload 1
Header 2
Payload 2
Header 3
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...
...
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SAM9X60
OTP Memory Controller (OTPC)
The number of packets depends on the size of the User area and the size of each packet.
23.4.3.3 Packet Definition
Each packet contains:
•
•
One 32-bit header field
One payload field containing at least 32 bits of data and up to 256 x 32 bits of data (8192 bits)
The payload field has no effect on the hardware except for “special” packets.
23.4.3.3.1 Header Field
The following table provides the definition of the header content.
31
30
29
28
27
26
25
24
18
17
16
11
10
9
8
3
2
1
0
CHECKSUM
23
22
21
20
19
CHECKSUM
15
14
13
12
SIZE
•
•
•
•
•
•
7
6
ONE
–
5
4
INVLD
LOCK
PACKET
PACKET: Indicates the packet type. Six types are available:
– REGULAR packet (value 1) accessible through the User Interface
– KEY packet (value 2) accessible only through the Private Key buses
– BOOT_CONFIGURATION “special” packet (value 3)
– SECURE_BOOT_CONFIGURATION “special” packet (value 4)
– HARDWARE_CONFIGURATION “special” packet (value 5)
– CUSTOM “special” packet (value 6)
LOCK: Written by the controller when the checksum is generated.
INVLD: Written when an invalidation process is requested.
ONE: Must be written to ‘1’.
SIZE: Indicates the size in 32-bit words of the payload field. SIZE = 0 means payload is 32-bit size, SIZE = 255
means payload is 8192-bit size.
The entire packet size (in bits) in OTP memory is 32 (header) + (32 * (SIZE + 1)).
CHECKSUM: Represents the checksum of the packet excluding the CHECKSUM field of the header. The real
value of the CHECKSUM field is not readable; it is generated by the OTPC.
– When CHECKSUM is read as 0, the checksum has not been generated. It is possible to modify the packet
content.
– When CHECKSUM is read as 0x33CC, the checksum has not been generated but some bits are already at
1. Locking the packet may fail.
– When CHECKSUM is read as 0xA5A5, the checksum has been generated and the last check was
successful. It is impossible to modify the packet content.
– When CHECKSUM is read as 0xCC33, the header of the packet is corrupted.
– When CHECKSUM is read as 0xFFFF, the entire packet is no longer valid. It is possible to modify the
packet content and it is up to the software to program the payload to a different value if needed.
– For all other values of CHECKSUM, the checksum has been generated and the last check failed to match
the checksum written in the OTP memory. It is impossible to modify the packet content.
23.4.3.3.2 “Special” Packets
The payload of “special” packets is interpreted by the OTPC and some actions can be triggered while the “special”
packets are read. The address of the “special” packets inside the area does not matter.
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OTP Memory Controller (OTPC)
If the checksum has been generated and does not match during the last read, the payload is not interpreted by the
OTPC.
The table below provides the list of “special” packets.
Table 23-1. “Special” Packets
Name
SIZE
PACKET Description
Boot Configuration
(see Note 1)
3
Boot configuration
Secure Boot Configuration
(see Note 2)
4
Secure Boot configuration
User Hardware Configuration 1
5
Hardware configuration
Custom
6
For user custom purposes. The size of this packet is user
application dependent.
N/A
Notes:
1. For details, refer to the section “Boot Strategies”.
2. For details, refer to “Secure Boot Strategy” document (Literature No. DS00003195), available under NonDisclosure Agreement (NDA). Contact a Microchip Sales Representative for details.
The address of the Boot Configuration and Secure Boot Configuration special packets can be retrieved in the OTPC
Boot Addresses (OTPC_BAR) register.
The address of the Custom special packets can be retrieved in the OTPC Custom Address (OTPC_CAR) register.
For each “special” packets, if there is more than one valid packet (of the same type), only the last packet will be
considered (previous packets will be ignored). It is recommended to invalidate prior “special” packets to keep only
one valid packet for each “special” packet type.
23.4.3.4 Init
After each reset, the OTPC parses the User area to check its content. The header of each packet will be read,
depending on the header value some actions can be triggered:
• If the header is corrupted, the init sequence is interrupted and the OTPC_ISR.COERR bit is set.
• If the INVLD field of the header is 3, the OTPC ignores the packet and jumps to the next header.
• If the LOCK bit of the header is set, the payload is read and the checksum computed during the read is
compared to the checksum saved in the header. If the checksums do not match, the OTPC_ISR.CKERR bit will
be set.
• If the PACKET field of the header is BOOT_CONFIGURATION, the address of the packet will be stored in the
OTPC_BAR.BCADDR field. Any previous value stored in the OTPC_BAR.BCADDR field is lost.
• If the PACKET field of the header is SECURE_BOOT_CONFIGURATION, the address of the packet will be
stored in the OTPC_BAR.SBCADDR field. Any previous value stored in the OTPC_BAR.SBCADDR field is lost.
• If the PACKET field of the header is HARDWARE_CONFIGURATION, the payload is read and stored in the
OTPC User Hardware Configuration (OTPC_UHCxR) registers (unless the checksums do not match if the
packet is locked, in that case the reset value of the OTPC_UHCxR registers is stored). Any previous value
stored in the OTPC_UHCxR registers is lost.
• If the PACKET field of the header is CUSTOM, the address of the packet will be stored in the
OTPC_CAR.CADDR field. Any previous value stored in the OTPC_CAR.CADDR field is lost.
At the end of the init sequence, the value of the last HARDWARE_CONFIGURATION “special“ packet found is
applied to the hardware.
23.4.3.5 Read Access
The User area can be read through the User interface at any time after a reset. Each packet is available through the
OTPC_DR register. To trigger a packet read, follow the steps below:
1. The address of the header (or any address of the payload) must be written in OTPC_MR.ADDR.
2. OTPC_CR.READ must be set to ‘1’ (the OTPC_CR.KEY field value does not matter).
3. Wait for OTPC_ISR.EOR to be set to ‘1’ or for OTPC_SR.READ to be set to ‘0’, indicating that the whole
packet has been transferred into temporary registers.
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4.
Read the header of the packet in the OTPC_HR register. To read each payload word, the address of the
payload word must be written in OTPC_AR.DADDR. The payload word is then available in OTPC_DR.
If OTPC_AR.INCRT is set to AFTER_READ, any read in the OTPC_DR increments the DADDR field.
If INCRT is set to AFTER_WRITE, any write in the OTPC_DR increments the DADDR field.
The payload of a packet with PACKET set to KEY is read as ‘0’. The payload of a packet hidden since the last reset
is read as ‘0’.
23.4.3.5.1 Transfer a Packet through the Master Key Bus
To transfer a packet from the OTP memory through the Master Key bus, follow the steps below:
1.
2.
3.
The address of the header (or any address of the payload) must be written in OTPC_MR.ADDR. Only the
packets with the packet type set to KEY are transferable on the Master Key bus.
The Key bus destination must be written in OTPC_MR.KBDST.
Write 0x7167in the OTPC_CR.KEY field and ‘1’ to OTPC_CR.KBSTART.
The end of the transfer is indicated by OTPC_ISR.EOKT=’1’ and/or OTPC_SR.MKBB=’0’.
If the type of the packet is not KEY, OTPC_ISR.KBERR is set.
To cancel a packet transfer, OTPC_CR.KEY must be set to 0x7167 and KBSTOP must be set.
23.4.3.5.2 Hiding a Packet
For security reasons, it is possible to hide a packet after having read it through the User Interface. Once hidden, any
read to the payload of the packet returns ‘0’.
To unhide a packet, a reset is necessary.
Hiding a packet does not make it available through the Key Buses.
To hide a packet, follow the steps below:
1.
2.
Write the address value of the header of the packet to hide in OTPC_MR.ADDR.
Write 0x7167 in OTPC_CR.KEY and ‘1’ to HIDE.
23.4.3.6 Write (Program) Considerations
Each word of the User area can be written only once. It is possible to write a packet payload partially and/or update a
packet payload already written.
The packet to write (either the header or the payload) may contain some bits already at ‘1’. In this case, a dummy
packet can be used to write the packet in a different location. The OTPC may also be able to fix the ‘1’ already written
if this bit also matches the packet to write. Thus before writing any new packet, it is necessary to proceed to a read at
the last address.
23.4.3.6.1 ‘1’ in the Header
After the read, the header may contain one or more ‘1’s. If the ‘1’s match the ‘1’s to write in the header, the packet
can be written.
If the ‘1’s do not all match the ‘1’s to write in the header, the packet cannot be written. It is mandatory to create (and
then invalidate if necessary) a packet with a compatible header.
23.4.3.6.2 ‘1’ in the Payload
If the payload is written and then updated later, the ‘1’s already written must match the ‘1’s to write.
If the payload is written only once (no update later), the ‘1’s already written must all match either the ‘1’ or the ‘0’ to
write (it cannot be a mix of ‘1’s and ‘0’s to write).
23.4.3.7 Write (Program) Access
The User area can be programmed at any time after a reset until OTPC_MR.WRDIS has been set.
23.4.3.7.1 Writing a New Packet from the User Interface
To write a new packet from the User Interface, follow the steps below:
1.
2.
Write OTPC_MR.NPCKT to ‘0’ if it is set at ‘1’.
Write OTPC_MR.ADDR to its maximum value.
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OTP Memory Controller (OTPC)
3.
Write a ‘1’ to OTPC_CR.READ and wait for the read completion (OTPC_ISR.EOR=‘1’ when the read is
completed).
4. Check there is no bit already set to ‘1’ in the OTPC_HR and OTPC_DR. The check for the data registers can
be replaced by reading OTPC_SR.ONEF (if ONEF is set, at least one bit of the data registers is set to ‘1’).
If the header or the payload of the packet already contains a 1, the new packet may need to be adapted.
5. Write OTPC_MR.ADDR to ‘0’ and set NPCKT.
Depending on the contents of the temporary registers, an automatic flush can be triggered. If an automatic
flush is started, OTPC_SR.FLUSH is set and OTPC_ISR.EOF is raised at the completion of the flush. It is
mandatory to wait for the end of the flush.
6. Write the header value in OTPC_HR. The value of PACKET must not be the same as KEY.
7. Set DADDR to ‘0’.
8. Write the first data in the OTPC_DR register. To update the 32-bit data later (using the packet update), the
OTPC_DR register must be set to 0.
9. Increment the DADDR field and write the next data in the OTPC_DR. Repeat this operation until all the data
has been written.
Skip the increment of DADDR if INCRT is set to AFTER_WRITE.
10. Write USER_KEY in the OTPC_CR.KEY field and ‘1’ to OTPC_CR.PGM.
Before the write operation in the OTP memory, the OTPC checks the consistency of the packet and that the packet
does not overlap on any existing packet. In case of error, OTPC_ISR.WERR is set and the write operation is
cancelled.
The end of the programming operation is indicated by OTPC_ISR.EOP=’1’ and/or OTPC_SR.PGM=’0’. At the end of
the programming, the address of the header is available in OTPC_MR.ADDR and the OTPC_MR.NPCKT must be
cleared.
The payload can be read back before programming. After read back, it is possible to update PACKET value to KEY
before programming.
If the new written packet is the User Hardware Configuration special packet, its payload is ignored until the next reset
or the next refresh. The OTPC_UHCxR registers will be updated after the reset or the refresh following programming.
23.4.3.7.2 Updating an Existing Packet from the User Interface
To update an existing packet from the User Interface, follow the steps below:
1.
2.
3.
4.
Write the address of the header of the packet to update in OTPC_MR.ADDR.
Start a read by setting OTPC_CR.READ and wait for the read completion indicated by OTPC_ISR.EOR.
Update the data using the OTPC_AR and OTPC_DR registers. Only the 32-bit data set to 0 can be updated,
the non-zero 32-bit data must be left unchanged
Write 0x7167 in the OTPC_CR.KEY field and ‘1’ to OTPC_CR.PGM.
The end of the programming operation is indicated by OTPC_ISR.EOP='1' and/or OTPC_SR.PGM='0'.
If the updated packet is the User Hardware Configuration special packet, its new payload is ignored until the next
reset. The OTPC_UHCxR registers will be updated after the reset or the refresh following programming.
23.4.3.7.3 Writing a Packet from the Slave Key Bus
To write a packet from the Slave Key bus interface (payload only), follow the steps below:
1.
2.
3.
4.
5.
6.
7.
Write OTPC_MR.ADDR to ‘0’ and set NPCKT.
Depending on the content of the temporary registers, an automatic flush can be triggered. If an automatic flush
is started, OTPC_SR.FLUSH is set and OTPC_ISR.EOF is raised at the completion of the flush. It is
mandatory to wait for the end of the flush.
Write the header value in the OTPC_HR register. The value of PACKET must be KEY.
Initiate a data transfer to the OTP memory through the TRNG Master Key bus.
Wait for the data transfer completion.
Check that no error happened during the key transfer (OTPC_ISR.KBERR must be cleared).
Write 0x7167 in the OTPC_CR.KEY field and ‘1’ to OTPC_CR.PGM.
Before the write operation in the OTP memory, the OTPC checks the consistency of the packet and that the
packet does not overlap on any existing packet. In case of error, OTPC_ISR.WERR is set and the write
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OTP Memory Controller (OTPC)
operation is cancelled. The end of the programming operation is indicated by OTPC_ISR.EOP=1 and/or
OTPC_SR.PGM=0.
If the PACKET field is changed before programming, the payload is erased (and lost).
23.4.3.7.4 Locking a Packet
To lock a packet, follow the steps below:
1.
2.
3.
Write the address value of the header of the packet to lock in OTPC_MR.ADDR.
Start a read by setting OTPC_CR.READ and waiting for the read completion indicated by OTPC_ISR.EOR.
Write 0x7167 in the OTPC_CR.KEY field and ‘1‘ in OTPC_CR.CKSGEN.
The end of the lock operation is indicated by OTPC_ISR.EOL=’1’ and/or OTPC_SR.LOCK=’0’.
Generating the checksum locks the packet and modification is no longer possible.
23.4.3.7.5 Invalidating a Packet
To invalidate a packet, follow the steps below:
1.
2.
Write the address value of the header of the packet to invalidate in OTPC_MR.ADDR.
Write 0x7167 in the OTPC_CR.KEY field and ‘1’ to OTPC_CR.INVLD.
The end of the invalidation operation is indicated by OTPC_ISR.EOI= ‘1’ and/or OTPC_SR.INVLD=’0’.
If the invalidated packet is the User Hardware Configuration special packet, its old payload remains active until the
next reset or the next refresh. The OTPC_UHCxR registers will be updated after the reset or the refresh following the
invalidation operation.
23.4.3.8 Fixing Corruption
During a programming sequence, packet header corruption may occur. This corruption can be caused by a partial
programming of the header. It is mandatory to fix any corruption prior to any usage of the Engineering Area or User
Area.
During the start sequence, the OTPC stops parsing the OTP memory at the first header corruption detected. When
OTPC_ISR.COERR is set, a corruption has been detected. The corrupted header can be read in OTPC_HR and its
location can be read in OTPC_MR.ADDR.
A header is corrupted if at least one of the following statements matches:
• The ONE bit is cleared (it must be set to fix the corruption).
• The INVLD field is 3 and the PACKET field is 0 (PACKET must be set to a non-0 value to fix the corruption).
• The SIZE and PACKET fields are not consistent (for PACKET set to PRODUCT_UID,
HARDWARE_CONFIGURATION or SECURITY_CONFIGURATION, the packet must be invalidated to fix the
corruption).
To fix a corruption, start a a read procedure at the location of the corrupted header. The OTPC reads the payload
according to the size provided in the header and reads one extra word of payload, which should match the next
header.
The corrupted header must be fixed by writing any missing ‘1’s or, if not possible, by extending its size if the
supposed next header is 0, or by invalidating the packet.
A reset is required after fixing the corruption.
23.4.3.9 “Software” Protections
The User area can be protected against read accesses and/or modifications.
To enable read protection of the User data (OTPC_DR) and header (OTPC_HR) registers, OTPC_MR.RDDIS must
be set. Clearing RDDIS allows read access again. When the OTPC_DR and OTPC_HR registers are read-protected,
any read returns 0.
To enable write protection of the OTPC_DR registers, the WRDIS bit of OTPC_MR should be set. Clearing the
WRDIS bit allows write access again.
To enable write protection of the User area, the write protection of the User data registers must be enabled.
The OTPC_MR can be locked until the next reset by setting the LOCK bit of OTPC_MR. Once locked, the current
protection configuration of the OTPC_DR and OTPC_HR registers applies, it is then also impossible to update,
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SAM9X60
OTP Memory Controller (OTPC)
program, invalidate, hide or read a packet (the OTPC_MR.ADDR field is then locked too preventing to select a
packet).
23.4.3.10 “Hardware” Protections
The User area can be protected against read accesses and/or modifications.
To enable the different protections of the User area, the User Configuration special packet must be programmed. The
packet is described in the OTPC_UHCxR registers.
As an example, to disable the JTAG interface for an indefinite period, the JTAGDIS, UHCINVDIS and UHCPGDIS
fields of the User Hardware Configuration special packet must all be programmed to a non-zero value. Thus, it will be
impossible to update or invalidate the User Hardware Configuration special packet.
WARNING
23.4.4
“Hardware” protections are in effect for an indefinite period and cannot be cancelled.
OTP Emulation Mode
The OTPC features an Emulation mode. This Emulation mode can be used to test all the operations allowed by the
controller on a memory instead of the real OTP memory.
When the Emulation mode is enabled, the controller has the same behavior. The Emulation mode is enabled only
when the OTP memory has not been previously programmed.
To enable/disable the Emulation mode on the User area, follow the steps below:
1.
2.
3.
Set OTPC_MR.EMUL to ‘1’ (to enable) or to ‘0’ (to disable).
Refresh the User area by writing a ‘1’ to OTPC_CR.REFRESH and 0x7167 in OTPC_CR.KEY.
Wait for the refresh completion by polling OTPC_ISR.EORF.
The current running mode of the User area can be observed by reading OTPC_SR.EMUL. If EMUL is set to ‘1’,
Emulation mode is enabled; if it is set to ‘0’, Emulation mode is disabled.
After a reset, Emulation mode is disabled.
23.4.5
Interrupts
An OTPC interrupt request can be triggered when one or several of the following bits are set in the OTPC Interrupt
Status register (OTPC_ISR): End Of Programming (EOP), End Of Locking (EOL), End Of Invalidation (EOI), End Of
Key Transfer (EOKT), Programming Error (PGERR), Locking Error (LKERR), Invalidation Error (IVERR), Write Error
(WERR), End Of Read (EOR), End Of Flush (EOF), End Of Hide (EOH), End Of Refresh (EOF), Checksum Check
Error (CKERR) or Key Invalid Error (KBERR).
The interrupt request is generated if the corresponding bit in the OTPC Interrupt Mask register (OTPC_IMR) is set.
Bits in OTPC_IMR are set by writing a ‘1’ to the corresponding bit in the OTPC Interrupt Enable register (OTPC_IER)
and cleared by writing a ‘1’ to the corresponding bit in the OTPC Interrupt Disable register (OTPC_IDR). The interrupt
request remains active until the corresponding bit in OTPC_ISR is cleared.
Reading the OTPC_ISR clears all bits of the register.
23.4.6
Register Write Protection
To prevent any single software error from corrupting the OTPC behavior, certain registers in the address space can
be write-protected by setting the Write Protection Configuration Enable (WPCFEN), Write Protection Interrupt Enable
(WPITEN) and/or Write Protection Control Enable (WPCTEN) bit(s) in the Write Protection Mode Register
(OTPC_WPMR).
If a write access to the protected registers is detected, the Write Protection Violation Status (WPVS) flag in the Write
Protection Status Register (OTPC_WPSR) is set and the field Write Protection Violation Source (WPVSRC) indicates
the register in which the write access has been attempted. An interrupt can be raised if the Security and/or Safety
Event (SECE) interrupt is set in OTPC_IMR.
The WPVS flag is automatically reset by reading the OTPC_WPSR.
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SAM9X60
OTP Memory Controller (OTPC)
The following registers can be write-protected with the OTPC_WPMR.WPCFEN bit:
•
OTPC Mode Register
The following registers can be write-protected with the OTPC_WPMR.WPITEN bit:
•
•
OTPC Interrupt Enable Register
OTPC Interrupt Disable Register
The following registers can be write-protected with the OTPC_WPMR.WPCTEN bit:
•
OTPC Control Register
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SAM9X60
OTP Memory Controller (OTPC)
23.5
Register Summary
Offset
Name
0x00
OTPC_CR
0x04
OTPC_MR
0x08
OTPC_AR
0x0C
0x10
0x14
0x18
0x1C
0x20
OTPC_SR
OTPC_IER
OTPC_IDR
OTPC_IMR
OTPC_ISR
OTPC_HR
0x24
OTPC_DR
0x28
...
0x2F
Reserved
0x30
OTPC_BAR
0x34
OTPC_CAR
0x38
...
0x4F
Reserved
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
5
4
3
2
1
0
INVLD
KBSTOP
CKSGEN
KBSTART
PGM
WRDIS
RDDIS
UHCRRDIS
KEY[15:8]
KEY[7:0]
REFRESH
FLUSH
READ
LOCK
EMUL
HIDE
ADDR[15:8]
ADDR[7:0]
KBDST[1:0]
NPCKT
INCRT
DADDR[7:0]
FLUSH
READ
SKBB
MKBB
SECE
EMUL
INVLD
ONEF
LOCK
HIDE
PGM
WERR
HDERR
IVERR
COERR
LKERR
CKERR
PGERR
SECE
EORF
EOKT
EOH
EOI
EOF
EOL
KBERR
EOR
EOP
WERR
HDERR
IVERR
COERR
LKERR
CKERR
PGERR
SECE
EORF
EOKT
EOH
EOI
EOF
EOL
KBERR
EOR
EOP
WERR
HDERR
IVERR
COERR
LKERR
CKERR
PGERR
SECE
EORF
EOKT
EOH
EOI
EOF
EOL
KBERR
EOR
EOP
WERR
HDERR
IVERR
COERR
LKERR
CKERR
EORF
PGERR
EOKT
CHECKSUM[15:8]
CHECKSUM[7:0]
SIZE[7:0]
INVLD[1:0]
LOCK
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
EOH
EOI
EOF
EOL
KBERR
EOR
EOP
ONE
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
PACKET[2:0]
SBCADDR[15:8]
SBCADDR[7:0]
BCADDR[15:8]
BCADDR[7:0]
CADDR[15:8]
CADDR[7:0]
Complete Datasheet
DS60001579C-page 243
SAM9X60
OTP Memory Controller (OTPC)
...........continued
Offset
Name
0x50
OTPC_UHC0R
0x54
0x58
...
0x5F
OTPC_UHC1R
OTPC_UID0R
0x64
OTPC_UID1R
0x68
OTPC_UID2R
0x6C
OTPC_UID3R
0x70
...
0xE3
Reserved
0xE8
7
6
5
4
3
2
1
0
SBCPGDIS
UHCINVDIS
URFDIS
SBCLKDIS
UPGDIS
CPGDIS
SBCINVDIS
URDDIS
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
JTAGDIS[7:0]
CLKDIS
BCPGDIS
CINVDIS
BCLKDIS
BCINVDIS
UHCPGDIS
UHCLKDIS
Reserved
0x60
0xE4
Bit Pos.
OTPC_WPMR
OTPC_WPSR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
UID[31:24]
UID[23:16]
UID[15:8]
UID[7:0]
UID[31:24]
UID[23:16]
UID[15:8]
UID[7:0]
UID[31:24]
UID[23:16]
UID[15:8]
UID[7:0]
UID[31:24]
UID[23:16]
UID[15:8]
UID[7:0]
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
FIRSTE
ECLASS
© 2020 Microchip Technology Inc.
WPVSRC[15:8]
WPVSRC[7:0]
SWE
Complete Datasheet
WPCTEN
WPITEN
SWETYP[3:0]
SEQE
CGD
WPCFEN
WPVS
DS60001579C-page 244
SAM9X60
OTP Memory Controller (OTPC)
23.5.1
OTPC Control Register
Name:
Offset:
Reset:
Property:
OTPC_CR
0x00
–
Write-only
This register can only be written if the WPCTEN bit is cleared in the OTPC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
W
–
W
–
W
–
W
–
19
18
17
16
KEY[15:8]
Access
Reset
W
–
W
–
W
–
W
–
Bit
23
22
21
20
KEY[7:0]
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
W
–
W
–
W
–
W
–
W
–
W
–
W
–
W
–
15
REFRESH
W
–
14
13
12
11
10
9
KBSTOP
W
–
8
KBSTART
W
–
7
FLUSH
W
–
6
READ
W
–
5
4
HIDE
W
–
3
2
INVLD
W
–
1
CKSGEN
W
–
0
PGM
W
–
Bits 31:16 – KEY[15:0] Programming Key
This field must be written with the correct key code (0x7167) to allow programming, checksum generation, packet
invalidation or packet hiding.
Bit 15 – REFRESH Refresh the Area
Value
Description
0
No effect.
1
Starts a refresh of the area.
Bit 9 – KBSTOP Key Bus Transfer Stop
Value
Description
0
No effect.
1
Stops an on-going transfer on the Master Key bus.
Bit 8 – KBSTART Key Bus Transfer Start
Value
Description
0
No effect.
1
Starts a transfer through the Master Key bus.
Bit 7 – FLUSH Flush Temporary Registers
Value
Description
0
No effect.
1
Starts a flush of the temporary registers used to store the payload of the packet.
Bit 6 – READ Read Packet
Value
Description
0
No effect.
1
Starts a read sequence of the selected packet.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 245
SAM9X60
OTP Memory Controller (OTPC)
Bit 4 – HIDE Hide Packet
Value
Description
0
No effect.
1
The selected packet is not readable anymore until the next reset.
Bit 2 – INVLD Invalidate Packet
Value
Description
0
No effect.
1
Invalidates the selected packet.
Bit 1 – CKSGEN Generate Checksum
Value
Description
0
No effect.
1
Generates and programs the selected packet checksum. This action also locks the packet.
Bit 0 – PGM Program Packet
Value
Description
0
No effect.
1
The selected packet is written.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 246
SAM9X60
OTP Memory Controller (OTPC)
23.5.2
OTPC Mode Register
Name:
Offset:
Reset:
Property:
OTPC_MR
0x04
0x00000000
Read/Write
This register can only be written if the WPCFEN bit is cleared in the OTPC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12
11
10
9
WRDIS
R/W
0
8
RDDIS
R/W
0
3
2
1
0
UHCRRDIS
R/W
0
ADDR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
ADDR[7:0]
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
R/W
0
15
LOCK
R/W
0
14
13
7
EMUL
R/W
0
6
KBDST[1:0]
R/W
0
R/W
0
5
4
NPCKT
R/W
0
Bits 31:16 – ADDR[15:0] Address
This field represents the address of the packet’s header.
Bit 15 – LOCK Lock Register
The LOCK bit is set-only. Only a reset can disable lock.
Value
Description
0
The OTPC_MR register is unlocked; write access changes its value.
1
The OTPC_MR register is locked; write access does not change its value.
Bits 13:12 – KBDST[1:0] Key Bus Destination
Value
Name
Description
0
TDES
The TDES is the destination of the key transfer.
1
AES
The AES is the destination of the key transfer.
Bit 9 – WRDIS Write Disable
Value
Description
0
The write capability of the OTPC_DR register is enabled.
1
The write capability of the OTPC_DR register is disabled.
Bit 8 – RDDIS Read Disable
Value
Description
0
The read capability of the OTPC_HR and OTPC_DR registers are enabled.
1
The read capability of the OTPC_HR and OTPC_DR registers are disabled. In case of read, the
returned value is 0.
Bit 7 – EMUL Emulation Enable
Value
Description
0
The Emulation mode of the User area is disabled, all accesses are computed in the OTP memory.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 247
SAM9X60
OTP Memory Controller (OTPC)
Value
1
Description
The Emulation mode of the User area is enabled, all accesses are computed in the Emulation memory.
Bit 4 – NPCKT New Packet
Value
Description
0
Updates the packet defined at the ADDR address.
1
Creates a new packet.
Bit 0 – UHCRRDIS User Hardware Configuration Register Read Disable
Value
Description
0
The User Hardware Configuration register can be read through the User Interface.
1
The User Hardware Configuration register cannot be read through the User Interface.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 248
SAM9X60
OTP Memory Controller (OTPC)
23.5.3
OTPC Address Register
Name:
Offset:
Reset:
Property:
Bit
OTPC_AR
0x08
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INCRT
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 16 – INCRT Increment Type
Value
Name
0
AFTER_READ
1
AFTER_WRITE
3
DADDR[7:0]
R/W
R/W
0
0
Description
Increment DADDR after a read of OTPC_DR.
Increment DADDR after a write of OTPC_DR.
Bits 7:0 – DADDR[7:0] Data Address
This field represents the word address of the payload to access through the OTPC_DR register.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 249
SAM9X60
OTP Memory Controller (OTPC)
23.5.4
OTPC Status Register
Name:
Offset:
Reset:
Property:
Bit
OTPC_SR
0x0C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
ONEF
R
0
8
HIDE
R
0
7
FLUSH
R
0
6
READ
R
0
5
SKBB
R
0
4
MKBB
R
0
3
EMUL
R
0
2
INVLD
R
0
1
LOCK
R
0
0
PGM
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 9 – ONEF One Found
Value
Description
0
No bit at ‘1’ found during the last packet read.
1
At least one ‘1’ has been found during the last packet read.
Bit 8 – HIDE Hiding On-Going
Value
Description
0
No packet hiding is on-going.
1
A packet hiding is on-going.
Bit 7 – FLUSH Flush On-Going
Value
Description
0
The temporary registers are not flushed.
1
The temporary registers are being flushed.
Bit 6 – READ Read On-Going
Value
Description
0
No packet read is on-going.
1
A packet read is running.
Bit 5 – SKBB Slave Key Bus Busy
Value
Description
0
The Slave Key bus is not busy.
1
The Slave Key bus is busy.
Bit 4 – MKBB Master Key Bus Busy
Value
Description
0
The Master Key bus is not busy.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 250
SAM9X60
OTP Memory Controller (OTPC)
Value
1
Description
The Master Key bus is busy.
Bit 3 – EMUL Emulation Enabled
Value
Description
0
The User area Emulation mode is disabled.
1
The User area Emulation mode is enabled.
Bit 2 – INVLD Invalidation On-Going
Value
Description
0
No packet invalidation is on-going.
1
A packet invalidation is running.
Bit 1 – LOCK Lock On-Going
Value
Description
0
No packet locking is on-going.
1
A packet locking is running.
Bit 0 – PGM Programming On-Going
Value
Description
0
No packet programming is on-going.
1
A packet programming is running.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 251
SAM9X60
OTP Memory Controller (OTPC)
23.5.5
OTPC Interrupt Enable Register
Name:
Offset:
Reset:
Property:
OTPC_IER
0x10
–
Write-only
This register can only be written if the WPITEN bit is cleared in the OTPC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
31
30
29
28
SECE
W
–
27
26
25
24
23
22
21
20
19
18
17
16
KBERR
W
–
15
14
HDERR
W
–
13
COERR
W
–
12
CKERR
W
–
11
EORF
W
–
10
EOH
W
–
9
EOF
W
–
8
EOR
W
–
7
WERR
W
–
6
IVERR
W
–
5
LKERR
W
–
4
PGERR
W
–
3
EOKT
W
–
2
EOI
W
–
1
EOL
W
–
0
EOP
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 28 – SECE Security and/or Safety Event Interrupt Enable
Bit 16 – KBERR Key Bus Error Interrupt Enable
Bit 14 – HDERR Hide Error Interrupt Enable
Bit 13 – COERR Corruption Error Interrupt Enable
Bit 12 – CKERR Checksum Check Error Interrupt Enable
Bit 11 – EORF End Of Refresh Interrupt Enable
Bit 10 – EOH End Of Hide Interrupt Enable
Bit 9 – EOF End Of Flush Interrupt Enable
Bit 8 – EOR End Of Read Interrupt Enable
Bit 7 – WERR Write Error Interrupt Enable
Bit 6 – IVERR Invalidation Error Interrupt Enable
Bit 5 – LKERR Locking Error Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 252
SAM9X60
OTP Memory Controller (OTPC)
Bit 4 – PGERR Programming Error Interrupt Enable
Bit 3 – EOKT End Of Key Transfer Interrupt Enable
Bit 2 – EOI End Of Invalidation Interrupt Enable
Bit 1 – EOL End Of Locking Interrupt Enable
Bit 0 – EOP End Of Programming Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 253
SAM9X60
OTP Memory Controller (OTPC)
23.5.6
OTPC Interrupt Disable Register
Name:
Offset:
Reset:
Property:
OTPC_IDR
0x14
–
Write-only
This register can only be written if the WPITEN bit is cleared in the OTPC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
31
30
29
28
SECE
W
–
27
26
25
24
23
22
21
20
19
18
17
16
KBERR
W
–
15
14
HDERR
W
–
13
COERR
W
–
12
CKERR
W
–
11
EORF
W
–
10
EOH
W
–
9
EOF
W
–
8
EOR
W
–
7
WERR
W
–
6
IVERR
W
–
5
LKERR
W
–
4
PGERR
W
–
3
EOKT
W
–
2
EOI
W
–
1
EOL
W
–
0
EOP
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 28 – SECE Security and/or Safety Event Interrupt Disable
Bit 16 – KBERR Key Bus Error Interrupt Disable
Bit 14 – HDERR Hide Error Interrupt Disable
Bit 13 – COERR Corruption Error Interrupt Disable
Bit 12 – CKERR Checksum Check Error Interrupt Disable
Bit 11 – EORF End Of Refresh Interrupt Disable
Bit 10 – EOH End Of Hide Interrupt Disable
Bit 9 – EOF End Of Flush Interrupt Disable
Bit 8 – EOR End Of Read Interrupt Disable
Bit 7 – WERR Write Error Interrupt Disable
Bit 6 – IVERR Invalidation Error Interrupt Disable
Bit 5 – LKERR Locking Error Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 254
SAM9X60
OTP Memory Controller (OTPC)
Bit 4 – PGERR Programming Error Interrupt Disable
Bit 3 – EOKT End Of Key Transfer Interrupt Disable
Bit 2 – EOI End Of Invalidation Interrupt Disable
Bit 1 – EOL End Of Locking Interrupt Disable
Bit 0 – EOP End Of Programming Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 255
SAM9X60
OTP Memory Controller (OTPC)
23.5.7
OTPC Interrupt Mask Register
Name:
Offset:
Reset:
Property:
OTPC_IMR
0x18
0x00000000
Read-only
The following configuration values are valid for all listed bit names of this register:
0: Corresponding interrupt is not enabled.
1: Corresponding interrupt is enabled.
Bit
31
30
29
28
SECE
R
0
27
26
25
24
23
22
21
20
19
18
17
16
KBERR
R
0
15
14
HDERR
R
0
13
COERR
R
0
12
CKERR
R
0
11
EORF
R
0
10
EOH
R
0
9
EOF
R
0
8
EOR
R
0
7
WERR
R
0
6
IVERR
R
0
5
LKERR
R
0
4
PGERR
R
0
3
EOKT
R
0
2
EOI
R
0
1
EOL
R
0
0
EOP
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 28 – SECE Security and/or Safety Event Interrupt Mask
Bit 16 – KBERR Key Bus Error Interrupt Mask
Bit 14 – HDERR Hide Error Interrupt Mask
Bit 13 – COERR Corruption Error Interrupt Mask
Bit 12 – CKERR Checksum Check Error Interrupt Mask
Bit 11 – EORF End Of Refresh Interrupt Mask
Bit 10 – EOH End Of Hide Interrupt Mask
Bit 9 – EOF End Of Flush Interrupt Mask
Bit 8 – EOR End Of Read Interrupt Mask
Bit 7 – WERR Write Error Interrupt Mask
Bit 6 – IVERR Invalidation Error Interrupt Mask
Bit 5 – LKERR Locking Error Interrupt Mask
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 256
SAM9X60
OTP Memory Controller (OTPC)
Bit 4 – PGERR Programming Error Interrupt Mask
Bit 3 – EOKT End Of Key Transfer Interrupt Mask
Bit 2 – EOI End Of Invalidation Interrupt Mask
Bit 1 – EOL End Of Locking Interrupt Mask
Bit 0 – EOP End Of Programming Interrupt Mask
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 257
SAM9X60
OTP Memory Controller (OTPC)
23.5.8
OTPC Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
OTPC_ISR
0x1C
0x00000000
Read-only
31
30
29
28
SECE
R
0
27
26
25
24
23
22
21
20
19
18
17
16
KBERR
R
0
15
14
HDERR
R
0
13
COERR
R
0
12
CKERR
R
0
11
EORF
R
0
10
EOH
R
0
9
EOF
R
0
8
EOR
R
0
7
WERR
R
0
6
IVERR
R
0
5
LKERR
R
0
4
PGERR
R
0
3
EOKT
R
0
2
EOI
R
0
1
EOL
R
0
0
EOP
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 28 – SECE Security and/or Safety Event (cleared on read)
Value
Description
0
No security or safety event occurred since the last read of OTPC_ISR.
1
One or more safety or security event occurred since the last read of OTPC_ISR. For details on the
event, refer to OTPC_WPSR.
Bit 16 – KBERR Key Bus Error (cleared on read)
Value
Description
0
No error happened on the Key bus since the last read of OTPC_ISR.
1
An error happened on the Key bus since the last read of OTPC_ISR.
Bit 14 – HDERR Hide Error (cleared on read)
Value
Description
0
No hiding error occurred since the last read of OTPC_ISR.
1
A hiding error occurred since the last read of OTPC_ISR.
Bit 13 – COERR Corruption Error (cleared on read)
Value
Description
0
No corruption occurred during the last start-up since the last read of OTPC_ISR.
1
A corruption occurred since the last read of OTPC_ISR.
Bit 12 – CKERR Checksum Check Error (cleared on read)
Value
Description
0
No checksum check failure occurred during last reading sequence since the last read of OTPC_ISR.
1
A checksum check failure occurred since the last read of OTPC_ISR.
Bit 11 – EORF End Of Refresh (cleared on read)
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 258
SAM9X60
OTP Memory Controller (OTPC)
Value
0
1
Description
No refresh sequence completion since the last read of OTPC_ISR.
At least one refresh sequence completion since the last read of OTPC_ISR.
Bit 10 – EOH End Of Hide (cleared on read)
Value
Description
0
No hiding sequence completion since the last read of OTPC_ISR.
1
At least one hiding sequence completion since the last read of OTPC_ISR.
Bit 9 – EOF End Of Flush (cleared on read)
Value
Description
0
No flush of the temporary registers since the last read of OTPC_ISR.
1
At least one flush hof the temporary registers has been completed since the last read of OTPC_ISR.
Bit 8 – EOR End Of Read (cleared on read)
Value
Description
0
No reading sequence completion since the last read of OTPC_ISR.
1
At least one reading sequence completion since the last read of OTPC_ISR.
Bit 7 – WERR Write Error (cleared on read)
Value
Description
0
No write error occurred since the last read of OTPC_ISR.
1
A write error occurred since the last read of OTPC_ISR.
Bit 6 – IVERR Invalidation Error (cleared on read)
Value
Description
0
No invalidation failure occurred during last invalidation sequence since the last read of OTPC_ISR.
1
A invalidation failure occurred since the last read of OTPC_ISR.
Bit 5 – LKERR Locking Error (cleared on read)
Value
Description
0
No locking failure occurred during last locking sequence since the last read of OTPC_ISR.
1
A locking failure occurred since the last read of OTPC_ISR.
Bit 4 – PGERR Programming Error (cleared on read)
Value
Description
0
No programming failure occurred during last programming sequence since the last read of OTPC_ISR.
1
A programming failure occurred since the last read of OTPC_ISR.
Bit 3 – EOKT End Of Key Transfer (cleared on read)
Value
Description
0
No key transfer completion since the last read of OTPC_ISR.
1
At least one key transfer has been completed on the Master Key bus since the last read of OTPC_ISR.
Bit 2 – EOI End Of Invalidation (cleared on read)
Value
Description
0
No invalidation sequence completion since the last read of OTPC_ISR.
1
At least one invalidation sequence completion since the last read of OTPC_ISR.
Bit 1 – EOL End Of Locking (cleared on read)
Value
Description
0
No locking sequence completion since the last read of OTPC_ISR.
1
At least one locking sequence completion since the last read of OTPC_ISR.
Bit 0 – EOP End Of Programming (cleared on read)
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 259
SAM9X60
OTP Memory Controller (OTPC)
Value
0
1
Description
No programming sequence completion since the last read of OTPC_ISR.
At least one programming sequence completion since the last read of OTPC_ISR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 260
SAM9X60
OTP Memory Controller (OTPC)
23.5.9
OTPC Header Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
OTPC_HR
0x20
0x00000000
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
CHECKSUM[15:8]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
3
LOCK
R/W
0
2
1
PACKET[2:0]
R/W
0
0
20
19
CHECKSUM[7:0]
R/W
R/W
0
0
12
SIZE[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bit
7
ONE
R/W
0
6
5
Access
Reset
INVLD[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:16 – CHECKSUM[15:0] Packet Checksum
When CHECKSUM is read as 0, the checksum has not been generated. It is still possible to modify the packet
content.
When CHECKSUM is read as 0x33CC, the checksum has not been generated but has already some bit at 1. Locking
the packet may fail.
When CHECKSUM is read as 0xA5A5, the checksum has been generated and the last check was successful. It is
impossible to modify the packet content.
When CHECKSUM is read as 0xCC33, the header of the packet is corrupted.
When CHECKSUM is read as 0xFFFF, the entire packet is no longer valid. It is possible to modify the packet content
and it is up to the software to program the payload to a different value if needed.
For all other values of CHECKSUM, the checksum has been generated and the last check failed to match the
checksum written in the OTP. It is impossible to modify the packet content.
This field is not writeable and is set by the OTPC during a lock request.
Bits 15:8 – SIZE[7:0] Packet Size
This field represents the size of the payload of the packet.
This field is writeable only for new packets.
Bit 7 – ONE One
This field is set to 1 by hardware and is not writeable.
Bits 5:4 – INVLD[1:0] Invalid Status
If set to value 3, this field indicates that the packet is not valid.
This field is not writeable and is set by the OTPC during an invalidation request.
Bit 3 – LOCK Lock Status
This field is not writeable and is set by the OTPC during a lock request.
Value
Description
0
The packet is not locked.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 261
SAM9X60
OTP Memory Controller (OTPC)
Value
1
Description
The packet is locked.
Bits 2:0 – PACKET[2:0] Packet Type
This field is writeable only for new packets.
Value
Name
1
REGULAR
2
KEY
3
BOOT_CONFIGURATION
4
SECURE_BOOT_CONFIGURATION
5
HARDWARE_CONFIGURATION
6
CUSTOM
© 2020 Microchip Technology Inc.
Description
Regular packet accessible through the User Interface
Key packet accessible only through the Key Buses
Boot Configuration packet
Secure Boot Configuration packet
Hardware Configuration packet
Custom packet
Complete Datasheet
DS60001579C-page 262
SAM9X60
OTP Memory Controller (OTPC)
23.5.10 OTPC Data Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
OTPC_DR
0x24
0x00000000
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
DATA[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
DATA[23:16]
R/W
R/W
0
0
12
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0] Packet Data
This field represents the data of one of the packet. The data read or written is located at the address specified by the
DADDR field of OTPC_AR register.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 263
SAM9X60
OTP Memory Controller (OTPC)
23.5.11 OTPC Boot Addresses Register
Name:
Offset:
Reset:
Property:
OTPC_BAR
0x30
0x00000000
Read-only
Bit
31
30
29
28
27
SBCADDR[15:8]
R
R
0
0
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
SBCADDR[7:0]
R
R
0
0
18
17
16
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
R
0
12
11
BCADDR[15:8]
R
R
0
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
BCADDR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:16 – SBCADDR[15:0] Secure Boot Configuration Address
This field represents the address of the “Secure Boot Configuration” special packet.
Bits 15:0 – BCADDR[15:0] Boot Configuration Address
This field represents the address of the “Boot Configuration” special packet.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 264
SAM9X60
OTP Memory Controller (OTPC)
23.5.12 OTPC Custom Address Register
Name:
Offset:
Reset:
Property:
Bit
OTPC_CAR
0x34
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
CADDR[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
CADDR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – CADDR[15:0] Custom Address
This field represents the address of the “Custom” special packet.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 265
SAM9X60
OTP Memory Controller (OTPC)
23.5.13 OTPC User Hardware Configuration 0 Register
Name:
Offset:
Reset:
Property:
OTPC_UHC0R
0x50
0x00000000
Read-only
Note: The reset value depends on hardware configuration.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
JTAGDIS[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – JTAGDIS[7:0] JTAG Disable
Value
Description
0
The JTAG is enabled.
Non-zero The JTAG is disabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 266
SAM9X60
OTP Memory Controller (OTPC)
23.5.14 OTPC User Hardware Configuration 1 Register
Name:
Offset:
Reset:
Property:
OTPC_UHC1R
0x54
0x00000000
Read-only
Note: The reset value depends on hardware configuration.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
URFDIS
R
0
16
CPGDIS
R
0
15
CLKDIS
R
0
14
CINVDIS
R
0
13
12
11
10
SBCPGDIS
R
0
9
SBCLKDIS
R
0
8
SBCINVDIS
R
0
7
BCPGDIS
R
0
6
BCLKDIS
R
0
5
BCINVDIS
R
0
4
UHCPGDIS
R
0
3
UHCLKDIS
R
0
2
UHCINVDIS
R
0
1
UPGDIS
R
0
0
URDDIS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 17 – URFDIS User Refresh Disable
Value
Description
0
The OTPC_CR.REFRESH bit is fully functional.
1
The OTPC_CR.REFRESH bit is only functional in Emulation mode.
Bit 16 – CPGDIS Custom Packet Program Disable
Value
Description
0
The programming of Custom Special Packet is allowed.
1
The programming of Custom Special Packet is forbidden.
Bit 15 – CLKDIS Custom Packet Lock Disable
Value
Description
0
The generation of the checksum (lock) of the Custom Special Packet is allowed.
1
The generation of the checksum (lock) of the Custom Special Packet is forbidden.
Bit 14 – CINVDIS Custom Packet Invalidation Disable
Value
Description
0
The invalidation of the Custom Special Packet is allowed.
1
The invalidation of the Custom Special Packet is forbidden.
Bit 10 – SBCPGDIS Secure Boot Configuration Packet Program Disable
Value
Description
0
The programming of Secure Boot Configuration Special Packet is allowed.
1
The programming of Secure Boot Configuration Special Packet is forbidden.
Bit 9 – SBCLKDIS Secure Boot Configuration Packet Lock Disable
Value
Description
0
The generation of the checksum (lock) of the Secure Boot Configuration Special Packet is allowed.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 267
SAM9X60
OTP Memory Controller (OTPC)
Value
1
Description
The generation of the checksum (lock) of the Secure Boot Configuration Special Packet is forbidden.
Bit 8 – SBCINVDIS Secure Boot Configuration Packet Invalidation Disable
Value
Description
0
The invalidation of the Secure Boot Configuration Special Packet is allowed.
1
The invalidation of the Secure Boot Configuration Special Packet is forbidden.
Bit 7 – BCPGDIS Boot Configuration Packet Program Disable
Value
Description
0
The programming of Boot Configuration Special Packet is allowed.
1
The programming of Boot Configuration Special Packet is forbidden.
Bit 6 – BCLKDIS Boot Configuration Packet Lock Disable
Value
Description
0
The generation of the checksum (lock) of the Boot Configuration Special Packet is allowed.
1
The generation of the checksum (lock) of the Boot Configuration Special Packet is forbidden.
Bit 5 – BCINVDIS Boot Configuration Packet Invalidation Disable
Value
Description
0
The invalidation of the Boot Configuration Special Packet is allowed.
1
The invalidation of the Boot Configuration Special Packet is forbidden.
Bit 4 – UHCPGDIS User Hardware Configuration Packet Program Disable
Value
Description
0
The programming of User Hardware Configuration Special Packet is allowed.
1
The programming of User Hardware Configuration Special Packet is forbidden.
Bit 3 – UHCLKDIS User Hardware Configuration Packet Lock Disable
Value
Description
0
The generation of the checksum (lock) of the User Hardware Configuration Special Packet is allowed.
1
The generation of the checksum (lock) of the User Hardware Configuration Special Packet is forbidden.
Bit 2 – UHCINVDIS User Hardware Configuration Packet Invalidation Disable
Value
Description
0
The invalidation of the User Hardware Configuration Special Packet is allowed.
1
The invalidation of the User Hardware Configuration Special Packet is forbidden.
Bit 1 – UPGDIS User programming Disable
Value
Description
0
The OTPC_CR.PGM bit is fully functional.
1
The OTPC_CR.PGM bit is not functional.
Bit 0 – URDDIS User Read Disable
Value
Description
0
The OTPC_CR.READ bit is fully functional.
1
The OTPC_CR.READ bit is not functional.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 268
SAM9X60
OTP Memory Controller (OTPC)
23.5.15 OTPC Product UID x Register
Name:
Offset:
Reset:
Property:
OTPC_UIDxR
0x60 + x*0x04 [x=0..3]
0x00000000
Read-only
Note: The reset value depends on hardware configuration.
Bit
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
UID[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
UID[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
UID[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
UID[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – UID[31:0] Unique Product ID
This field represents the unique product ID.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 269
SAM9X60
OTP Memory Controller (OTPC)
23.5.16 OTPC Write Protection Mode Register
Name:
Offset:
Reset:
Property:
OTPC_WPMR
0xE4
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
FIRSTE
R/W
0
3
2
WPCTEN
R/W
0
1
WPITEN
R/W
0
0
WPCFEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x4F5450
PASSWD
Writing any other value in this field aborts the write operation.
Always reads as 0.
Bit 4 – FIRSTE First Error Report Enable
Value
Description
0
The last write protection violation source is reported in OTPC_WPSR.WPVSRC and the last software
control error type is reported in OTPC_WPSR.SWETYP; The OTPC_ISR.SECE flag is set at the first
error occurrence within a series.
1
Only the first write protection violation source is reported in OTPC_WPSR.WPVSRC and only the first
software control error type is reported in OTPC_WPSR.SWETYP. The OTPC_ISR.SECE flag is set at
the first error occurrence within a series.
Bit 2 – WPCTEN Write Protection Control Enable
Value
Description
0
Disables the write protection of the control if WPKEY matches to 0x4F5450 (OTP in ASCII).
1
Enables the write protection of the control if WPKEY matches to 0x4F5450 (OTP in ASCII).
Bit 1 – WPITEN Write Protection Interrupt Enable
Value
Description
0
Disables the write protection of the interruption configuration if WPKEY matches to 0x4F5450 (OTP in
ASCII).
1
Enables the write protection of the interruption configuration if WPKEY matches to 0x4F5450 (OTP in
ASCII).
Bit 0 – WPCFEN Write Protection Configuration Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 270
SAM9X60
OTP Memory Controller (OTPC)
Value
0
1
Description
Disables the write protection of the configuration if WPKEY matches to 0x4F5450 (OTP in ASCII).
Enables the write protection of the configuration if WPKEY matches to 0x4F5450 (OTP in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 271
SAM9X60
OTP Memory Controller (OTPC)
23.5.17 OTPC Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
OTPC_WPSR
0xE8
0x00000000
Read-only
31
ECLASS
R
0
30
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
Bit
7
6
Access
Reset
29
28
27
26
25
24
SWETYP[3:0]
Access
Reset
R
0
R
0
R
0
R
0
20
19
WPVSRC[15:8]
R
R
0
0
18
17
16
R
0
R
0
R
0
10
9
8
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
5
4
2
SEQE
R
0
1
CGD
R
0
0
WPVS
R
0
3
SWE
R
0
Bit 31 – ECLASS Software Error Class
Value
Name
Description
0
WARNING
An abnormal access that does not have any impact.
1
ERROR
An abnormal access that may have an impact.
Bits 27:24 – SWETYP[3:0] Software Error Type
Value
Name
Description
0
READ_WO
A write-only register has been read (warning).
1
WRITE_RO
A write access has been performed on a read-only register (warning).
2
CONF_CHG A change has been made into the configuration (error).
3
KEY_ERROR A write has been computed in OTPC_CR or OTPC_WPMR register with a wrong value
in the related KEY field (error).
4
DATA_ACC
The non-secure world application tried to read a packet from the secure world (error).
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 3 – SWE Software Control Error (cleared on read)
Value
Description
0
No software error has occurred since the last read of OTPC_WPSR.
1
A software error has occurred since the last read of OTPC_WPSR. The field SWETYP details the type
of software error encountered.
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
Value
Description
0
No peripheral internal sequencer error has occurred since the last read of OTPC_WPSR.
1
A peripheral internal sequencer error has occurred since the last read of OTPC_WPSR. This flag can
be set under abnormal operating conditions.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 272
SAM9X60
OTP Memory Controller (OTPC)
Bit 1 – CGD Clock Glitch Detected (cleared on read)
Value
Description
0
No clock glitch has occurred since the last read of OTPC_WPSR.
1
A clock glitch has occurred since the last read of OTPC_WPSR. This flag can be set under abnormal
operating conditions.
Bit 0 – WPVS Write Protection Violation Status (cleared on read)
Value
Description
0
No write protection violation has occurred since the last read of OTPC_WPSR.
1
A write protection violation has occurred since the last read of OTPC_WPSR. If this violation is an
unauthorized attempt to write a protected register, the associated violation is reported into WPVSRC.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 273
SAM9X60
Special Function Registers (SFR)
24.
24.1
Special Function Registers (SFR)
Description
Special Function Registers (SFR) manage specific aspects of the integrated memory, bridge implementations,
processor and other functionality not controlled elsewhere.
24.2
Embedded Characteristics
•
32-bit Special Function Registers Control Specific Behavior of the Product
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 274
SAM9X60
Special Function Registers (SFR)
24.3
Register Summary
Offset
Name
0x00
...
0x03
Reserved
Bit Pos.
7
6
5
4
3
2
0x08
...
0x0F
0x10
0x14
0x18
...
0x33
0x34
SFR_CCFG_EBICS
A
DDR_MP_EN
23:16
15:8
7:0
DQIEN_F
EBI_CS5A
EBI_CS4A
APPSTART
ARIE
EBI_CS3A
Reserved
SFR_OHCIICR
SFR_OHCIISR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
UDPPUDIS
SUSP2
RES2
SUSP1
RES1
SUSP0
RES0
RIS2
RIS1
RIS0
Reserved
SFR_UTMIHSTRIM
0x38
SFR_UTMIFSTRIM
0x3C
SFR_UTMISWAP
0x40
...
0x7B
0
NFD0_ON_D1
6
EBI_DRIVE
EBI_DBPDC EBI_DBPUC
EBI_CS1A
31:24
0x04
1
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
SLOPE1[2:0]
SLOPE2[2:0]
SLOPE0[2:0]
ZP_CAL[2:0]
ZP[2:0]
ZN_CAL[2:0]
ZN[2:0]
PORT2
PORT1
PORT0
LS9
LS1
MEM_POWE
R_GATING_U
LP1_EN
LS8
LS0
Reserved
31:24
0x7C
SFR_LS
23:16
15:8
7:0
0x80
...
0xE3
0xE4
LS7
LS6
LS5
LS4
LS3
LS2
Reserved
SFR_WPMR
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WPEN
Complete Datasheet
DS60001579C-page 275
SAM9X60
Special Function Registers (SFR)
24.3.1
EBI Chip Select Register
Name:
Offset:
Reset:
Property:
Bit
SFR_CCFG_EBICSA
0x04
0x00000300
Read/Write
31
30
29
28
27
26
23
22
21
20
DQIEN_F
R/W
0
19
18
17
16
EBI_DRIVE
R/W
0
15
14
13
12
11
10
9
EBI_DBPDC
R/W
1
8
EBI_DBPUC
R/W
1
7
6
5
EBI_CS5A
R/W
0
4
EBI_CS4A
R/W
0
3
EBI_CS3A
R/W
0
2
1
EBI_CS1A
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
25
24
DDR_MP_EN NFD0_ON_D16
R/W
R/W
0
0
Bit 25 – DDR_MP_EN DDR Multi-port Enable
Value
Description
0
DDR Multi-port is disabled (default).
1
DDR Multi-port is enabled, performance is increased.
Bit 24 – NFD0_ON_D16 NAND Flash Databus Selection
Value
Description
0
NAND Flash I/Os are connected to D0–D7 (default).
1
NAND Flash I/Os are connected to D16–D23.
Bit 20 – DQIEN_F Force Analog Input Comparator Configuration
Value
Description
0
No effect
1
Enables the input comparator in the VDDIOM I/O data lines. This bit must be set to one in an
initialization phase whenever an MPDDRC external component (DDR2 or LPDDR) and an SMC
external component (e.g., NAND Flash) are multiplexed on the D0-D15 bus.
Bit 16 – EBI_DRIVE EBI I/O Drive Configuration
Value
Description
0
EBI D0–D15 Low Drive
1
EBI D0–D15 High Drive
Bit 9 – EBI_DBPDC EBI Data Bus Pulldown Configuration
Value
Description
0
EBI D0–D15 Data Bus bits are not internally pulled down.
1
EBI D0–D15 Data Bus bits are internally pulled down to the ground.
Bit 8 – EBI_DBPUC EBI Data Bus Pullup Configuration
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 276
SAM9X60
Special Function Registers (SFR)
Value
0
1
Description
EBI D0–D15 Data Bus bits are internally pulled up to the VDDIOM power supply.
EBI D0–D15 Data Bus bits are not internally pulled up.
Bit 5 – EBI_CS5A EBI Chip Select 5 Assignment
Value
Description
0
EBI Chip Select 5 is only assigned to the Static Memory Controller and EBI_NCS5 behaves as defined
by the SMC.
1
EBI Chip Select 5 is assigned to the Static Memory Controller.
Bit 4 – EBI_CS4A EBI Chip Select 4 Assignment
Value
Description
0
EBI Chip Select 4 is only assigned to the Static Memory Controller and EBI_NCS4 behaves as defined
by the SMC.
1
EBI Chip Select 4 is assigned to the Static Memory Controller.
Bit 3 – EBI_CS3A EBI Chip Select 3 Assignment
Value
Description
0
EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined
by the SMC.
1
EBI Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash Logic is activated.
Bit 1 – EBI_CS1A EBI Chip Select 1 Assignment
Value
Description
0
EBI Chip Select 1 is assigned to the Static Memory Controller (SMC).
1
EBI Chip Select 1 is assigned to the MPDDRC or the SDRAMC controller.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 277
SAM9X60
Special Function Registers (SFR)
24.3.2
OHCI Interrupt Configuration Register
Name:
Offset:
Reset:
Property:
Bit
SFR_OHCIICR
0x10
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
UDPPUDIS
R/W
0
22
21
20
19
18
17
16
15
14
13
12
11
10
SUSP2
R/W
0
9
SUSP1
R/W
0
8
SUSP0
R/W
0
7
6
5
APPSTART
R/W
0
4
ARIE
R/W
0
3
2
RES2
R/W
0
1
RES1
R/W
0
0
RES0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 23 – UDPPUDIS Reserved
Value
Description
0
Must write 0.
Bits 8, 9, 10 – SUSP USB PORTx
Value
Description
0
Does not suspend USB PORTx.
1
Forces PORTx suspend.
Bit 5 – APPSTART Reserved
Value
Description
0
Must write 0.
Bit 4 – ARIE OHCI Asynchronous Resume Interrupt Enable
Value
Description
0
Disables interrupt.
1
Enables interrupt.
Bits 0, 1, 2 – RESx USB PORTx Reset
Value
Description
0
No effect (USB PORTx reset released, default value)
1
Resets USB PORTx.
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Special Function Registers (SFR)
24.3.3
OHCI Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
SFR_OHCIISR
0x14
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RIS2
R/W
0
1
RIS1
R/W
0
0
RIS0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2 – RIS OHCI Resume Interrupt Status Port x
Value
Description
0
OHCI port resume is not detected.
1
OHCI port resume is detected.
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SAM9X60
Special Function Registers (SFR)
24.3.4
UTMI High-Speed Trimming Register
Name:
Offset:
Reset:
Property:
Bit
SFR_UTMIHSTRIM
0x34
0x00044433
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SLOPE2[2:0]
R/W
0
16
Access
Reset
Bit
Access
Reset
Bit
R/W
1
15
Access
Reset
Bit
7
14
R/W
1
13
SLOPE1[2:0]
R/W
0
12
R/W
0
6
5
4
11
3
10
R/W
0
R/W
1
9
SLOPE0[2:0]
R/W
0
8
R/W
0
2
1
0
Access
Reset
Bits 8:10, 12:14, 16:18 – SLOPE UTMI HS PORTx Transceiver Slope Trimming
Adjusts HS transceiver output slope for PORTx.
These bits are duplicated for each port because the HS slope depends on the PCB line length. Short lines tend to be
seen as lumped capacitances and exhibit a slower rise/fall time, while longer lines appear as transmission lines with
sharper edges.
Value
Name
111
Slower
110
–
101
–
100
Default
011
–
010
–
001
–
000
Faster
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SAM9X60
Special Function Registers (SFR)
24.3.5
UTMI Full-Speed Trimming Register
Name:
Offset:
Reset:
Property:
Bit
31
Access
Reset
Bit
30
R/W
0
23
22
29
ZP_CAL[2:0]
R/W
0
28
27
R/W
0
R/W
1
21
ZP[2:0]
R/W
0
R/W
0
15
14
13
12
7
6
5
4
Access
Reset
Bit
SFR_UTMIFSTRIM
0x38
0x00430211
Read/Write
20
26
R/W
0
19
18
25
ZN_CAL[2:0]
R/W
0
24
R/W
0
R/W
0
17
ZN[2:0]
R/W
1
16
R/W
1
11
10
9
8
3
2
1
0
Access
Reset
Bit
Access
Reset
Bits 30:28 – ZP_CAL[2:0] FS Transceiver PMOS Impedance Calibration
Adjusts the FS transceiver PMOS output impedance calibration.
Value
Name
011
Higher
010
–
001
–
000
Default
111
–
110
–
101
–
100
Lower
Bits 26:24 – ZN_CAL[2:0] FS Transceiver NMOS Impedance Calibration
Adjusts the FS transceiver NMOS output impedance calibration.
Value
Name
011
Higher
010
–
001
–
000
Default
111
–
110
–
101
–
100
Lower
Bits 22:20 – ZP[2:0] FS Transceiver PMOS Impedance Trimming
Adjusts the FS transceiver PMOS output impedance.
Value
Name
111
Higher
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SAM9X60
Special Function Registers (SFR)
Value
110
101
100
011
010
001
000
Name
–
–
Default
–
–
–
Lower
Bits 18:16 – ZN[2:0] FS Transceiver NMOS Impedance Trimming
Adjusts the FS transceiver NMOS output impedance.
Value
Name
111
Lower
110
–
101
–
100
–
011
Default
010
–
001
–
000
Higher
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Special Function Registers (SFR)
24.3.6
UTMI DP/DM Pin Swapping Register
Name:
Offset:
Reset:
Property:
Bit
SFR_UTMISWAP
0x3C
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
PORT2
R/W
0
1
PORT1
R/W
0
0
PORT0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2 – PORT PORT x DP/DM Pin Swapping
0 (NORMAL): DP/DM normal pinout.
1 (SWAPPED): DP/DM swapped pinout.
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Special Function Registers (SFR)
24.3.7
SFR Light Sleep Register
Name:
Offset:
Reset:
Property:
SFR_LS
0x7C
0x00000000
Read/Write
The following configuration values are valid for all listed LSx bit names of this register:
0: Disables Light Sleep mode.
1: Enables Light Sleep mode.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MEM_POWER_
GATING_ULP1
_EN
R/W
0
15
14
13
12
11
10
9
LS9
R/W
0
8
LS8
R/W
0
7
LS7
R/W
0
6
LS6
R/W
0
5
LS5
R/W
0
4
LS4
R/W
0
3
LS3
R/W
0
2
LS2
R/W
0
1
LS1
R/W
0
0
LS0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 16 – MEM_POWER_GATING_ULP1_EN Light Sleep Value for ULP1 Power-Gated Memories
The memory power gating can be automatically enabled when entering ULP1 Low-power mode. Refer to section
“Electrical Characteristics”.
Value
Description
0
Light Sleep mode is not activated by the MEM_POWER_GATING_ULP1 output signal from PMC.
1
Light Sleep mode is activated when the MEM_POWER_GATING_ULP1 output signal from PMC is
activated.
Bit 9 – LS9 Light Sleep Value (ARM926)
Bit 8 – LS8 Light Sleep Value (ROM + OTPC)
Bit 7 – LS7 Light Sleep Value (SRAM1 (OTPC))
Bit 6 – LS6 Light Sleep Value (SRAM0)
Bit 5 – LS5 Light Sleep Value (EHCI/OHCI)
Bit 4 – LS4 Light Sleep Value (HXDMA)
Bit 3 – LS3 Light Sleep Value (HUSB)
Bit 2 – LS2 Light Sleep Value (SDMMC)
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Special Function Registers (SFR)
Bit 1 – LS1 Light Sleep Value (HLCDC5)
Bit 0 – LS0 Light Sleep Value (GFX2D)
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Special Function Registers (SFR)
24.3.8
SFR Write Protection Mode Register
Name:
Offset:
Reset:
Property:
SFR_WPMR
0xE4
0x00000000
Read/Write
All registers are write-protected.
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x534652 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
Bit 0 – WPEN Write Protection Enable
Value
Description
0
Disables write protection if WPKEY corresponds to 0x534652 (“SFR” in ASCII).
1
Enables write protection if WPKEY corresponds to 0x534652 (“SFR” in ASCII).
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SAM9X60
Bus Matrix (MATRIX)
25.
Bus Matrix (MATRIX)
25.1
Description
The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel
access paths between multiple masters and slaves in a system, thus increasing the overall bandwidth.
The MATRIX interconnects 15 masters to 13 slaves. The normal latency to connect a master to a slave is one cycle,
except for the default master of the accessed slave which is connected directly (zero cycle latency).
The MATRIX user interface is compliant with the Arm Advanced Peripheral Bus.
25.1.1
MATRIX Masters
The MATRIX manages 15 masters listed in the table below. Each master can perform an access, concurrently with
others, to an available slave. The MATRIX operates at the master clock (MCK) frequency. Each master has its own
decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the
same decodings.
Table 25-1. List of MATRIX Masters
Master No.
Description
0
ARM926 instruction
1
ARM926 data
2, 3
25.1.2
XDMA controller with QoS support
4
SDMMC0 DMA
5
SDMMC1 DMA
6
USB high-speed device port (UDPHS) DMA
7
USB high-speed host port (UHPHS) EHCI DMA
8
USB high-speed host port (UHPHS) OHCI DMA
9
ISI DMA
10
EMAC0 DMA
11
EMAC1 DMA
12
OTP controller master interface
13
GFX2D DMA
14
LCDC DMA with QoS support
MATRIX Slaves
The MATRIX manages the 13 slaves listed in the table below. Each slave has its own arbiter providing a dedicated
arbitration per slave.
Table 25-2. List of MATRIX Slaves
Slave No.
Description
0
SRAM0
1
OTPC slave interface (ROM and OTP memory)
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Bus Matrix (MATRIX)
...........continued
Slave No.
Description
UDPHS dual port RAM
2
UHPHS OHCI configuration registers
UHPHS EHCI configuration registers
3
External Bus Interface / MPDDRC / SDRAMC port 0 with QoS support
4
MPDDRC / SDRAMC port 1(1) with QoS support
5
MPDDRC / SDRAMC port 2(1) with QoS support
6
MPDDRC / SDRAMC port 3(1) with QoS support
7
Peripheral bridge 0
8
Peripheral bridge 1
9
QSPI
10
SDMMC0 configuration registers
11
SDMMC1 configuration registers
12
SRAM1
Note:
1. The multiport is available for the SDRAMC when the Multiplexed Address/Data Lines or the Address/Data/
Command Lines mode is used. In standard SDRAM Connection mode, only port 0 is used. Refer to “Interface
with Multiplexed Data/Address Lines and Data/Address/Command Lines”, in section SDRAM Controller
(SDRAMC).
25.1.3
Master to Slave Access
The table below describes how masters and slaves can be interconnected. Writing in a register or field not dedicated
to a master or a slave has no effect.
Table 25-3. Master to Slave Access
12
13
14
LCDC DMA
11
GFX2D
10
OTPC
Master I/F
9
EMAC1 DMA
UDPHS DMA
8
EMAC0 DMA
7
ISI DMA
6
UHPHS OHCI
5
UHPHS EHCI
4
SDMMC1 DMA
3
SDMMC0 DMA
2
XDMAC0
ARM926 Data
ARM926 Instr.
Slaves
1
XDMAC1
0
Masters
0
SRAM0
X
X
X
X
X
X
X
X
X
X
X
X
–
X
X
1
OTPC Slave I/F
X
X
–
–
–
–
–
–
–
–
–
–
–
–
–
X
X
–
–
–
–
–
–
–
–
–
–
–
–
–
UDPHS DPRAM
2
UHPHS EHCI config. reg.
UHPHS OHCI config. reg.
3
EBI / MPDDRC / SDRAMC
port 0
X
X
X
X
X
X
X
X
X
X
X
X
–
X
X
4
MPDDRC / SDRAMC
port 1
X
–
X
–
X
–
X
–
–
–
X
–
–
–
–
5
MPDDRC / SDRAMC
port 2
–
X
–
X
–
X
–
X
X
–
–
X
–
X
–
6
MPDDRC / SDRAMC
port 3
–
–
–
–
–
–
–
–
–
X
–
–
–
–
X
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SAM9X60
Bus Matrix (MATRIX)
...........continued
12
13
14
LCDC DMA
11
GFX2D
10
OTPC
Master I/F
9
EMAC1 DMA
UDPHS DMA
8
EMAC0 DMA
7
ISI DMA
6
UHPHS OHCI
5
UHPHS EHCI
4
SDMMC1 DMA
3
SDMMC0 DMA
XDMAC0
2
XDMAC1
1
ARM926 Data
Slaves
0
ARM926 Instr.
Masters
7
Peripheral Bridge 0
–
X
X
X
–
–
–
–
–
–
–
–
–
–
–
8
Peripheral Bridge 1
–
X
X
X
–
–
–
–
–
–
–
–
–
–
–
9
QSPI
X
X
X
X
–
–
–
–
–
–
–
–
–
–
X
10
SDMMC0 config. reg.
–
X
–
–
–
–
–
–
–
–
–
–
–
–
–
11
SDMMC1 config. reg.
–
X
–
–
–
–
–
–
–
–
–
–
–
–
–
12
SRAM1
X
X
–
–
–
–
–
–
–
–
–
–
X
–
–
25.2
Embedded Characteristics
•
•
•
•
•
•
•
•
•
•
•
•
25.3
15 Configurable Master Ports
13 Configurable Slave Ports
One Decoder for Each Master
One Remap Function for Each Master
Support for Long Bursts of Length 32, 64, 128 and Up to the Limit of 256-bit Burst Beats of Words
Enhanced Programmable Mixed Arbitration for Each Slave
– Round-robin
– Fixed priority
– Latency Quality of Service
Programmable Default Master for Each Slave
– No default master
– Last accessed default master
– Fixed default master
Deterministic Maximum Access Latency for Masters
Zero or One Cycle Arbitration Latency for the First Access of a Burst
Bus Lock Forwarding to Slaves
Master Number Forwarding to Slaves
Register Write Protection of User Interface Registers
Memory Mapping
The MATRIX provides one decoder for every master interface. The decoder offers each master several memory
mappings. Each memory area can be assigned to several slaves. Booting at the same address while using different
slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible.
25.4
Special Bus Granting Techniques
The MATRIX provides some speculative bus granting techniques in order to anticipate access requests from masters.
Hence, latency is reduced at first access of a burst or, for a single transfer, as long as the slave is free from any other
master access. It does not provide any benefit if the slave is continuously accessed by more than one master, since
arbitration is pipelined and has no negative effect on the slave bandwidth or access latency.
This bus granting technique sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated default
master. A slave can be associated with three kinds of default masters:
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Bus Matrix (MATRIX)
•
•
•
no default master
last access master
fixed default master
To change from one type of default master to another, the user interface provides Slave Configuration registers
(MATRIX_SCFGx), one for every slave, which set a default master for each slave. MATRIX_SCFGx contain two fields
to manage master selection: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the
default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field
selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to section 25.10.2
MATRIX_SCFGx.
25.5
No Default Master
After the end of the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without
default master may be used for masters that perform significant bursts or several transfers with no Idle cycle inbetween, or if the slave bus bandwidth is widely used by one or more masters.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput
whatever the number of requesting masters.
25.6
Last Access Master
After the end of the current access, if no other request is pending, the slave remains connected to the last master that
performed an access request.
This enables the MATRIX to remove the one latency cycle for the last master that accessed the slave. Other nonprivileged masters still get one latency clock cycle if they need to access the same slave. This technique is useful for
masters that mainly perform single accesses or short bursts with some Idle cycles in-between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput
whatever is the number of requesting masters.
25.7
Fixed Default Master
After the end of the current access, if no other request is pending, the slave connects to its fixed default master.
Unlike the last access master, the fixed default master does not change unless the user modifies it by software
(FIXED_DEFMSTR field of the related MATRIX_SCFG).
This allows the MATRIX arbiters to remove the one latency clock cycle for the fixed default master of the slave. All
requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-privileged
masters get one latency cycle. This technique is useful for a master that mainly performs single accesses or short
bursts with Idle cycles in-between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput, regardless of the number of requesting masters.
25.8
Arbitration
The MATRIX provides an arbitration technique that reduces latency when conflicts occur, i.e., when two or more
masters try to access the same slave at the same time. One arbiter per slave is provided, thus arbitrating each slave
specifically.
The user can either choose one of the following arbitration types, or mix them for each slave:
1.
2.
Round-robin Arbitration (default)
Fixed Priority Arbitration
The resulting algorithm may be complemented by selecting a default master configuration for each slave.
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Bus Matrix (MATRIX)
When re-arbitration must be done, specific conditions apply. See section 25.8.1 Arbitration Scheduling .
25.8.1
Arbitration Scheduling
Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst
breaking as well as to provide the maximum throughput for slave interfaces, arbitration may only take place during
the following cycles:
•
•
•
•
Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently
accessing it.
Single Cycles: When a slave is currently doing a single access.
End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst,
predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. See
section 25.8.1.1 Undefined Length Burst Arbitration.
Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master
access is too long and must be broken. See section 25.8.1.2 Slot Cycle Limit Arbitration.
25.8.1.1 Undefined Length Burst Arbitration
In order to prevent long burst lengths that can lock the access to the slave for an excessive period of time, the user
can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from
the following Undefined Length Burst Type (ULBT) possibilities:
•
•
•
•
•
•
•
•
Unlimited: no predetermined end of burst is generated. This value enables 1 Kbyte burst lengths.
1-beat bursts: predetermined end of burst is generated at each single transfer during the INCR transfer.
4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR transfer.
8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR transfer.
16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR
transfer.
32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR
transfer.
64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR
transfer.
128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during INCR
transfer.
The use of undefined length 8-beat bursts, or less, is discouraged since this may decrease the overall bus bandwidth
due to arbitration and slave latencies at each first access of a burst.
Undefined-length bursts lower than 8 beats should not be used since this may decrease the overall bus bandwidth
due to arbitration and slave latencies at each first access of a burst.
However, if the length of undefined-length bursts is known for a master, it is recommended to configure
MATRIX_MCFG.ULBT accordingly.
25.8.1.2 Slot Cycle Limit Arbitration
The MATRIX contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an
external low speed memory). At each arbitration time, a counter is loaded with the value previously written in
MATRIX_SCFGx.SLOT_CYCLE and decreased at each clock cycle. When the counter elapses, the arbiter has the
ability to re-arbitrate at the end of the current system bus access cycle.
Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a
badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled (SLOT_CYCLE
= 0) or set to its default maximum value in order not to inefficiently break long bursts performed by some masters.
In most cases, this feature is not needed and should be disabled for power saving.
WARNING
This feature cannot prevent any slave from locking its access indefinitely.
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Bus Matrix (MATRIX)
25.8.2
Arbitration Priority Scheme
The MATRIX arbitration scheme is organized in priority pools, each corresponding to an access criticality class as
shown in the “Latency Quality of Service” column in the table below. When the Latency Quality of Service is enabled
for a master-slave pair through the MATRIX, the priority pool number to use for arbitration at the slave port is
determined from the master. When the Latency Quality of Service is disabled, it is determined through the MATRIX
user interface. See 25.10.3 MATRIX_PRASx.
After reset, the Latency Quality of Service is enabled by default on all of the master ports that are connected to a
master driving the Latency Quality of Service signals, as shown in the bit LQOSEN of 25.10.3 MATRIX_PRASx and
25.10.4 MATRIX_PRBSx.
Table 25-4. Arbitration Priority Pools
Priority Pool
Latency Quality of Service
3
Latency Critical
2
Latency Sensitive
1
Bandwidth Sensitive
0
Background Transfers
Round-robin priority is used in the highest and lowest priority pools 3 and 0, whereas fixed level priority is used
between priority pools and in the intermediate priority pools 2 and 1.
For each slave, each master is assigned to one of the slave priority pools based on the Latency Quality of Service
inputs or to the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating
master requests, this priority pool level always takes precedence.
After reset, most of the masters belong to the lowest priority pool (MxPR = 0, Background Transfer) and are therefore
granted bus access in a true round-robin order.
The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than one
master belongs to this pool, those masters are granted bus access in a biased round-robin manner which enables
tight and deterministic maximum access latency from system bus requests. In the worst case, any currently occurring
high-priority master request is granted after the current bus master access has ended and any other high priority pool
master requests have been granted once each.
The lowest priority pool shares the remaining bus bandwidth between masters.
Intermediate priority pools enable fine priority tuning. Typically, a latency-sensitive master or a bandwidth-sensitive
master use such a priority level. The higher the priority level (MxPR value), the higher the master priority.
For good CPU performance, it is recommended to let the CPU priority configured with the default reset value 2
(Latency Sensitive).
All combinations of MxPR values are allowed for all masters and slaves. For example, some masters might be
assigned the highest priority pool (round-robin), and remaining masters the lowest priority pool (round-robin), with no
master for intermediate fixed priority levels.
25.8.2.1 Fixed Priority Arbitration
The fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct
priority pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority
pools).
Fixed priority arbitration enables the MATRIX arbiters to dispatch the requests from different masters to the same
slave by using the fixed priority defined by the user in the MxPR field for each master in the registers, MATRIX_PRAS
and MATRIX_PRBS. If two or more master requests are active at the same time, the master with the highest priority
MxPR number is serviced first.
In intermediate priority pools, if two or more master requests with the same priority are active at the same time, the
master with the highest number is serviced first.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 292
SAM9X60
Bus Matrix (MATRIX)
25.8.2.2 Round-Robin Arbitration
This algorithm is only used in the highest and lowest priority pools. It allows the MATRIX arbiters to properly dispatch
requests from different masters to the same slave. If two or more master requests are active at the same time in the
priority pool, they are serviced in a round-robin increasing master number order.
25.9
Register Write Protection
To prevent any single software error from corrupting MATRIX behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the Write Protection Mode register (MATRIX_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the Write Protection Status register
(MATRIX_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS flag is reset by writing the MATRIX_WPMR with the appropriate access key WPKEY.
The registers listed below can be write-protected.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 293
SAM9X60
Bus Matrix (MATRIX)
25.10
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
MATRIX_MCFG0
31:24
23:16
15:8
7:0
ULBT[2:0]
31:24
23:16
15:8
7:0
ULBT[2:0]
...
0x38
0x3C
...
0x3F
MATRIX_MCFG14
Reserved
31:24
23:16
0x40
MATRIX_SCFG0
FIXED_DEFMSTR[3:0]
DEFMSTR_TYPE[1:0]
SLOT_CYCL
E[8]
15:8
7:0
SLOT_CYCLE[7:0]
31:24
23:16
FIXED_DEFMSTR[3:0]
...
0x70
MATRIX_SCFG12
15:8
7:0
0x74
...
0x7F
DEFMSTR_TYPE[1:0]
SLOT_CYCL
E[8]
SLOT_CYCLE[7:0]
Reserved
0x80
MATRIX_PRAS0
0x84
MATRIX_PRBS0
0x88
MATRIX_PRAS1
0x8C
MATRIX_PRBS1
0x90
MATRIX_PRAS2
0x94
MATRIX_PRBS2
0x98
MATRIX_PRAS3
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
Complete Datasheet
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
DS60001579C-page 294
SAM9X60
Bus Matrix (MATRIX)
...........continued
Offset
Name
0x9C
MATRIX_PRBS3
0xA0
MATRIX_PRAS4
0xA4
MATRIX_PRBS4
0xA8
MATRIX_PRAS5
0xAC
MATRIX_PRBS5
0xB0
MATRIX_PRAS6
0xB4
MATRIX_PRBS6
0xB8
MATRIX_PRAS7
0xBC
MATRIX_PRBS7
0xC0
MATRIX_PRAS8
0xC4
MATRIX_PRBS8
0xC8
MATRIX_PRAS9
0xCC
MATRIX_PRBS9
0xD0
MATRIX_PRAS10
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
6
5
4
LQOSEN13
M13PR[1:0]
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
Complete Datasheet
3
2
1
0
LQOSEN14
LQOSEN12
M14PR[1:0]
M12PR[1:0]
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
DS60001579C-page 295
SAM9X60
Bus Matrix (MATRIX)
...........continued
Offset
Name
0xD4
MATRIX_PRBS10
0xD8
MATRIX_PRAS11
0xDC
MATRIX_PRBS11
0xE0
MATRIX_PRAS12
0xE4
MATRIX_PRBS12
0xE8
...
0xFF
Reserved
0x0100
0x0104
...
0x014F
0x0150
0x0154
0x0158
0x015C
0x0160
MATRIX_MRCR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
6
5
4
LQOSEN13
M13PR[1:0]
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
LQOSEN7
LQOSEN5
LQOSEN3
LQOSEN1
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
M7PR[1:0]
M5PR[1:0]
M3PR[1:0]
M1PR[1:0]
LQOSEN13
LQOSEN11
LQOSEN9
M13PR[1:0]
M11PR[1:0]
M9PR[1:0]
3
2
1
0
LQOSEN14
LQOSEN12
M14PR[1:0]
M12PR[1:0]
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
LQOSEN6
LQOSEN4
LQOSEN2
LQOSEN0
LQOSEN14
LQOSEN12
LQOSEN10
LQOSEN8
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
M6PR[1:0]
M4PR[1:0]
M2PR[1:0]
M0PR[1:0]
M14PR[1:0]
M12PR[1:0]
M10PR[1:0]
M8PR[1:0]
RCB7
RCB14
RCB6
RCB13
RCB5
RCB12
RCB4
RCB11
RCB3
RCB10
RCB2
RCB9
RCB1
RCB8
RCB0
MERR7
MERR14
MERR6
MERR13
MERR5
MERR12
MERR4
MERR11
MERR3
MERR10
MERR2
MERR9
MERR1
MERR8
MERR0
MERR7
MERR14
MERR6
MERR13
MERR5
MERR12
MERR4
MERR11
MERR3
MERR10
MERR2
MERR9
MERR1
MERR8
MERR0
MERR7
MERR14
MERR6
MERR13
MERR5
MERR12
MERR4
MERR11
MERR3
MERR10
MERR2
MERR9
MERR1
MERR8
MERR0
MERR7
MERR14
MERR6
MERR13
MERR5
MERR12
MERR11
MERR4
MERR3
ERRADD[31:24]
ERRADD[23:16]
ERRADD[15:8]
ERRADD[7:0]
MERR10
MERR2
MERR9
MERR1
MERR8
MERR0
Reserved
MATRIX_MEIER
MATRIX_MEIDR
MATRIX_MEIMR
MATRIX_MESR
MATRIX_MEAR0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
...
0x0198
MATRIX_MEAR14
0x019C
...
0x01E3
Reserved
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
ERRADD[31:24]
ERRADD[23:16]
ERRADD[15:8]
ERRADD[7:0]
Complete Datasheet
DS60001579C-page 296
SAM9X60
Bus Matrix (MATRIX)
...........continued
Offset
Name
0x01E4
MATRIX_WPMR
0x01E8
MATRIX_WPSR
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
5
4
3
2
1
0
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
CFGFRZ
© 2020 Microchip Technology Inc.
WPEN
WPVSRC[15:8]
WPVSRC[7:0]
WPVS
Complete Datasheet
DS60001579C-page 297
SAM9X60
Bus Matrix (MATRIX)
25.10.1 MATRIX Master Configuration Register x
Name:
Offset:
Reset:
Property:
MATRIX_MCFGx
0x00 + x*0x04 [x=0..14]
0x00000004
Read/Write
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ULBT[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
1
R/W
0
Bits 2:0 – ULBT[2:0] Undefined Length Burst Type
Value
Name
Description
0
UNLIMITED Unlimited Length Burst—No predicted end of burst is generated, therefore INCR bursts
coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the
Slot Cycle Limit is not reached, the burst is normally completed by the master, at the
latest, on the next system bus 1 Kbyte address boundary, allowing up to 256-beat word
bursts or 128-beat double-word bursts.
1
SINGLE
2
4_BEAT
3
8_BEAT
4
16_BEAT
5
32_BEAT
6
64_BEAT
7
128_BEAT
This value should not be used in the very particular case of a master capable of
performing back-to-back undefined length bursts on a single slave, since this could
indefinitely freeze the slave arbitration and thus prevent another master from accessing
this slave.
Single Access—The undefined length burst is treated as a succession of single
accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
4-beat Burst—The undefined length burst or bursts sequence is split into 4-beat bursts or
less, allowing re-arbitration every 4 beats.
8-beat Burst—The undefined length burst or bursts sequence is split into 8-beat bursts or
less, allowing re-arbitration every 8 beats.
16-beat Burst—The undefined length burst or bursts sequence is split into 16-beat bursts
or less, allowing re-arbitration every 16 beats.
32-beat Burst—The undefined length burst or bursts sequence is split into 32-beat bursts
or less, allowing re-arbitration every 32 beats.
64-beat Burst—The undefined length burst or bursts sequence is split into 64-beat bursts
or less, allowing re-arbitration every 64 beats.
128-beat Burst—The undefined length burst or bursts sequence is split into 128-beat
bursts or less, allowing re-arbitration every 128 beats.
Unless duly needed, the ULBT should be left at its default 0 value for power saving.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 298
SAM9X60
Bus Matrix (MATRIX)
25.10.2 MATRIX Slave Configuration Register x
Name:
Offset:
Reset:
Property:
MATRIX_SCFGx
0x40 + x*0x04 [x=0..12]
0x000001FF
Read/Write
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
Bit
31
30
29
23
22
21
28
27
26
25
24
Access
Reset
Bit
Access
Reset
R/W
0
Bit
15
14
13
7
6
5
R/W
1
R/W
1
R/W
1
20
19
FIXED_DEFMSTR[3:0]
R/W
R/W
0
0
12
11
18
R/W
0
17
16
DEFMSTR_TYPE[1:0]
R/W
R/W
0
0
10
9
8
SLOT_CYCLE[
8]
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Access
Reset
Bit
Access
Reset
4
3
SLOT_CYCLE[7:0]
R/W
R/W
1
1
Bits 21:18 – FIXED_DEFMSTR[3:0] Fixed Default Master
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of
a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
Bits 17:16 – DEFMSTR_TYPE[1:0] Default Master Type
Value
Name Description
0
NONE No Default Master—At the end of the current slave access, if no other master request is
pending, the slave is disconnected from all masters.
This results in a one clock cycle latency for the first access of a burst transfer or for a single
access.
Last Default Master—At the end of the current slave access, if no other master request is
pending, the slave stays connected to the last master having accessed it.
1
LAST
2
This results in not having one clock cycle latency when the last master tries to access the
slave again.
FIXED Fixed Default Master—At the end of the current slave access, if no other master request is
pending, the slave connects to the fixed master the number that has been written in the
FIXED_DEFMSTR field.
This results in not having one clock cycle latency when the fixed master tries to access the
slave again.
Bits 8:0 – SLOT_CYCLE[8:0] Maximum Bus Grant Duration for Masters
When SLOT_CYCLE system bus clock cycles have elapsed since the last arbitration, a new arbitration takes place to
let another master access this slave. If another master is requesting the slave bus, then the current master burst is
broken.
If SLOT_CYCLE = 0, the Slot Cycle Limit feature is disabled and bursts always complete unless broken according to
the ULBT.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 299
SAM9X60
Bus Matrix (MATRIX)
This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting
for slave access.
This limit must not be too small. Unreasonably small values break every burst and the MATRIX arbitrates without
performing any data transfer. The default maximum value is usually an optimal conservative choice.
In most cases, this feature is not needed and should be disabled for power saving.
See section Slot Cycle Limit Arbitration for details.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 300
SAM9X60
Bus Matrix (MATRIX)
25.10.3 MATRIX Priority Register A For Slaves x
Name:
Offset:
Reset:
Property:
MATRIX_PRASx
0x80 + x*0x08 [x=0..12]
–
Read/Write
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
Table 25-5. MATRIX_PRASx Register Reset Values
Bit
Registers
Reset Values
PRAS0, PRAS3, PRAS7, PRAS8, PRAS9
0x00007722
PRAS1, PRAS2, PRAS10, PRAS11, PRAS12
0x00000022
PRAS4
0x00000702
PRAS5
0x00007020
PRAS6
0x00000000
31
Access
Reset
Bit
23
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
30
LQOSEN7
R/W
–
22
LQOSEN5
R/W
–
14
LQOSEN3
R/W
–
6
LQOSEN1
R/W
–
29
28
27
M7PR[1:0]
R/W
–
R/W
–
21
20
19
M5PR[1:0]
R/W
–
R/W
–
13
12
11
M3PR[1:0]
R/W
–
R/W
–
5
4
3
M1PR[1:0]
R/W
–
R/W
–
26
LQOSEN6
R/W
–
18
LQOSEN4
R/W
–
10
LQOSEN2
R/W
–
2
LQOSEN0
R/W
–
25
24
M6PR[1:0]
R/W
–
R/W
–
17
16
M4PR[1:0]
R/W
–
R/W
–
9
8
M2PR[1:0]
R/W
–
R/W
–
1
0
M0PR[1:0]
R/W
–
R/W
–
Bits 2, 6, 10, 14, 18, 22, 26, 30 – LQOSENx Latency Quality of Service Enable for Master x
Value
Description
0
Disables propagation of Latency Quality of Service from the Master x to the Slave and apply MxPR
priority for all access from Master x to the Slave.
1
Enables the propagation of Latency Quality of Service from the Master x to the Slave if supported by
the Master x.
Bits 0:1, 4:5, 8:9, 12:13, 16:17, 20:21, 24:25, 28:29 – MxPR Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
All the masters programmed with the same MxPR value for the slave make up a priority pool.
Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.
Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).
See section Arbitration Priority Scheme for details.
If LQOSENx bit is cleared, then this priority value is used as it for arbitration and downward propagation to the slave.
If LQOSENx bit is set, then this priority acts as the upper limit for the Latency Quality of Service from Master x.
For masters other than the CPU, the usual value of this field should be 0x0 if LQOSENx bit is cleared, and 0x1 if
LQOSENx bit is set. For the CPU master, the usual value of this field should be 0x2.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Bus Matrix (MATRIX)
25.10.4 MATRIX Priority Register B For Slaves x
Name:
Offset:
Reset:
Property:
MATRIX_PRBSx
0x84 + x*0x08 [x=0..12]
–
Read/Write
Table 25-6. MATRIX_PRBSx Register Reset Values
Registers
Reset Values
PRBS0, PRBS3, PRBS6, PRBS9
0x07000000
PRBS1, PRBS2, PRBS4, PRBS5, PRBS7, PRBS8, PRBS10, PRBS11, PRBS12
0x00000000
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
Bit
31
30
29
28
27
Access
Reset
Bit
23
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
22
LQOSEN13
R/W
–
14
LQOSEN11
R/W
–
6
LQOSEN9
R/W
–
21
20
19
M13PR[1:0]
R/W
–
R/W
–
13
12
11
M11PR[1:0]
R/W
–
R/W
–
5
4
3
M9PR[1:0]
R/W
–
R/W
–
26
LQOSEN14
R/W
–
18
LQOSEN12
R/W
–
10
LQOSEN10
R/W
–
2
LQOSEN8
R/W
–
25
24
M14PR[1:0]
R/W
–
R/W
–
17
16
M12PR[1:0]
R/W
–
R/W
–
9
8
M10PR[1:0]
R/W
–
R/W
–
1
0
M8PR[1:0]
R/W
–
R/W
–
Bits 2, 6, 10, 14, 18, 22, 26 – LQOSENx Latency Quality of Service Enable for Master x
Value
Description
0
Disables propagation of Latency Quality of Service from the Master x to the Slave and apply MxPR
priority for all access from Master x to the Slave.
1
Enables the propagation of Latency Quality of Service from the Master x to the Slave if supported by
the Master x.
Bits 0:1, 4:5, 8:9, 12:13, 16:17, 20:21, 24:25 – MxPR Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
All the masters programmed with the same MxPR value for the slave make up a priority pool.
Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.
Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).
See section Arbitration Priority Scheme for details.
If LQOSENx bit is cleared, then this priority value is used as it for arbitration and downward propagation to the slave.
If LQOSENx bit is set, then this priority acts as the upper limit for the Latency Quality of Service from Master x.
For masters other than the CPU, the usual value of this field should be 0x0 if LQOSENx bit is cleared, and 0x1 if
LQOSENx bit is set. For the CPU master, the usual value of this field should be 0x2.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 302
SAM9X60
Bus Matrix (MATRIX)
25.10.5 MATRIX Master Remap Control Register
Name:
Offset:
Reset:
Property:
MATRIX_MRCR
0x0100
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
RCB14
R/W
0
13
RCB13
R/W
0
12
RCB12
R/W
0
11
RCB11
R/W
0
10
RCB10
R/W
0
9
RCB9
R/W
0
8
RCB8
R/W
0
7
RCB7
R/W
0
6
RCB6
R/W
0
5
RCB5
R/W
0
4
RCB4
R/W
0
3
RCB3
R/W
0
2
RCB2
R/W
0
1
RCB1
R/W
0
0
RCB0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 – RCBx Remap Command Bit for Master x
Value
Description
0
Disables remapped address decoding for the selected master.
1
Enables remapped address decoding for the selected master.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Bus Matrix (MATRIX)
25.10.6 MATRIX Master Error Interrupt Enable Register
Name:
Offset:
Reset:
Property:
MATRIX_MEIER
0x0150
–
Write-only
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
MERR14
W
–
13
MERR13
W
–
12
MERR12
W
–
11
MERR11
W
–
10
MERR10
W
–
9
MERR9
W
–
8
MERR8
W
–
7
MERR7
W
–
6
MERR6
W
–
5
MERR5
W
–
4
MERR4
W
–
3
MERR3
W
–
2
MERR2
W
–
1
MERR1
W
–
0
MERR0
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 – MERRx Master x Access Error
Value
Description
0
No effect.
1
Enables Master x Access Error interrupt source.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Bus Matrix (MATRIX)
25.10.7 MATRIX Master Error Interrupt Disable Register
Name:
Offset:
Reset:
Property:
MATRIX_MEIDR
0x0154
–
Write-only
This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
MERR14
W
–
13
MERR13
W
–
12
MERR12
W
–
11
MERR11
W
–
10
MERR10
W
–
9
MERR9
W
–
8
MERR8
W
–
7
MERR7
W
–
6
MERR6
W
–
5
MERR5
W
–
4
MERR4
W
–
3
MERR3
W
–
2
MERR2
W
–
1
MERR1
W
–
0
MERR0
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 – MERRx Master x Access Error
Value
Description
0
No effect.
1
Disables Master x Access Error interrupt source.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Bus Matrix (MATRIX)
25.10.8 MATRIX Master Error Interrupt Mask Register
Name:
Offset:
Reset:
Property:
Bit
MATRIX_MEIMR
0x0158
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
MERR14
R
0
13
MERR13
R
0
12
MERR12
R
0
11
MERR11
R
0
10
MERR10
R
0
9
MERR9
R
0
8
MERR8
R
0
7
MERR7
R
0
6
MERR6
R
0
5
MERR5
R
0
4
MERR4
R
0
3
MERR3
R
0
2
MERR2
R
0
1
MERR1
R
0
0
MERR0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 – MERRx Master x Access Error
Value
Description
0
Master x Access Error does not trigger any interrupt.
1
Master x Access Error triggers the MATRIX interrupt line.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Bus Matrix (MATRIX)
25.10.9 MATRIX Master Error Status Register
Name:
Offset:
Reset:
Property:
Bit
MATRIX_MESR
0x015C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
MERR14
R
0
13
MERR13
R
0
12
MERR12
R
0
11
MERR11
R
0
10
MERR10
R
0
9
MERR9
R
0
8
MERR8
R
0
7
MERR7
R
0
6
MERR6
R
0
5
MERR5
R
0
4
MERR4
R
0
3
MERR3
R
0
2
MERR2
R
0
1
MERR1
R
0
0
MERR0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 – MERRx Master x Access Error
Value
Description
0
No Master Access Error has occurred since the last read of the MATRIX_MESR.
1
At least one Master Access Error has occurred since the last read of the MATRIX_MESR.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Bus Matrix (MATRIX)
25.10.10 MATRIX Master Error Address Register x
Name:
Offset:
Reset:
Property:
MATRIX_MEARx
0x0160 + x*0x04 [x=0..14]
0x00000000
Read-only
Bit
31
30
29
28
27
ERRADD[31:24]
R
R
0
0
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
ERRADD[23:16]
R
R
0
0
18
17
16
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
R
0
12
11
ERRADD[15:8]
R
R
0
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
ERRADD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – ERRADD[31:0] Master Error Address
32 most significant bits of the last access error address
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Bus Matrix (MATRIX)
25.10.11 MATRIX Write Protection Mode Register
Name:
Offset:
Reset:
Property:
MATRIX_WPMR
0x01E4
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
Bit
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
7
CFGFRZ
R/W
0
6
5
4
3
2
1
0
WPEN
R/W
0
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x4D4154 PASSWD Writing any other value in this field aborts the write operation of the WPEN and CFGFRZ
bits.
Always reads as 0.
Bit 7 – CFGFRZ Configuration Freeze
Value
Description
0
The MATRIX configuration is not frozen.
1
Freezes the MATRIX configuration until hardware reset. The registers that can be protected by the
WPEN bit and the Write Protection Mode Register are no longer modifiable.
Bit 0 – WPEN Write Protection Enable
See section Register Write Protection for the list of registers that can be write-protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Bus Matrix (MATRIX)
25.10.12 MATRIX Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
MATRIX_WPSR
0x01E8
0x00000000
Read-only
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
WPVSRC[15:8]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
4
2
1
0
WPVS
R
0
Access
Reset
3
Access
Reset
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 0 – WPVS Write Protection Violation Status
Value
Description
0
No write protection violation has occurred since the last write of the MATRIX_WPMR.
1
A write protection violation has occurred since the last write of the MATRIX_WPMR. If this violation is
an unauthorized attempt to write a protected register, the associated violation is reported into field
WPVSRC.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Advanced Interrupt Controller (AIC)
26.
26.1
Advanced Interrupt Controller (AIC)
Description
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller
providing handling of up to one hundred and twenty-eight interrupt sources. It is designed to substantially reduce the
software and real-time overhead in handling internal and external interrupts.
The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM
processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's
pins.
The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher
priority interrupts to be serviced even if a lower priority interrupt is being processed.
Internal interrupt sources can be programmed to be level-sensitive or edge-triggered. External interrupt sources can
be programmed to be rising-edge or falling-edge triggered or high-level or low-level sensitive.
The fast-forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a
normal interrupt.
26.2
Embedded Characteristics
•
•
•
•
•
•
•
•
Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM Processor
50 Individually Maskable and Vectored Interrupt Sources
– Source 0 is reserved for the fast interrupt input (FIQ)
– Source 1 is reserved for system peripheral interrupts
– Source 2 to Source 49 control up to 126 embedded peripheral interrupts or external interrupts
– Programmable edge-triggered or level-sensitive internal sources
– Programmable rising/falling edge-triggered or high/low level-sensitive external sources
8-level Priority Controller
– Drives the normal interrupt of the processor
– Handles priority of the interrupt sources 1 to 49
– Higher priority interrupts can be served during service of lower priority interrupt
Vectoring
– Optimizes interrupt service routine branch and execution
– One 32-bit vector register for all interrupt sources
– Interrupt vector register reads the corresponding current interrupt vector or the current interrupt number
Protect Mode
– Easy debugging by preventing automatic operations when protect models are enabled
Fast Forcing
– Permits redirecting any normal interrupt source to the fast interrupt of the processor
General Interrupt Mask
– Provides processor synchronization on events without triggering an interrupt
Register Write Protection
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Advanced Interrupt Controller (AIC)
26.3
Block Diagram
Figure 26-1. Block Diagram
AIC
FIQ
0
IRQ0-IRQn
ARM
Processor
Interrupt
Sources
nFIQ
Embedded
PeripheralEE
Embedded
nIRQ
n
Peripheral
Embedded
Peripheral
System Bus
26.4
Application Block Diagram
Figure 26-2. Description of the Application Block
OS-based Applications
Standalone
Applications
OS Drivers
RTOS Drivers
Hard Real-Time Tasks
General OS Interrupt Handler
Advanced Interrupt Controller
External Peripherals
(External Interrupts)
Embedded Peripherals
26.5
AIC Detailed Block Diagram
Figure 26-3. AIC Detailed Block Diagram
Advanced Interrupt Controller
FIQ
PIO
Controller
IRQ0-IRQn
nFIQ
nIRQ
Interrupt
Priority
Controller
Fast
Forcing
PIOIRQ
Embedded
Peripherals
Fast
Interrupt
Controller
External
Source
Input
Stage
ARM
Processor
Internal
Source
Input
Stage
Processor
Clock
Power
Management
Controller
User Interface
Wake Up
APB
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Advanced Interrupt Controller (AIC)
26.6
I/O Line Description
Table 26-1. I/O Line Description
26.7
26.7.1
Pin Name
Pin Description
Type
FIQ
Fast Interrupt
Input
IRQ0–IRQn
Interrupt 0–Interrupt n
Input
Product Dependencies
I/O Lines
The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the
features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned
interrupt functions. This is not applicable when the PIO controller used in the product is transparent on the input path.
26.7.2
Power Management
The AIC is continuously clocked. The Power Management Controller has no effect on the AIC behavior.
The assertion of the AIC outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle mode. The
General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the
processor, thus providing synchronization of the processor on an event.
26.7.3
Interrupt Sources
FIQ always drives Interrupt Source 0.
The System Controller interrupt drives Interrupt Source 1.
The System Controller interrupt is the result of the OR-wiring of the System Controller interrupt lines. When a System
Controller interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by
reading successively the status registers of the System Controller peripherals.
Interrupt sources 2 to 49 can either be connected to the interrupt outputs of an embedded user peripheral, or to
external interrupt lines. The external interrupt lines can be connected either directly or through the PIO Controller.
PIO controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO controller
interrupt lines are connected to interrupt sources 2 to 49.
The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the
bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional
operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID49.
26.8
Functional Description
26.8.1
Interrupt Source Control
26.8.1.1 Interrupt Source Mode
The AIC independently programs each interrupt source. The SRCTYPE field of the Source Mode register (AIC_SMR)
selects the interrupt condition of the interrupt source selected by the INTSEL field of the Source Select register
(AIC_SSR).
Note: Configuration registers such as AIC_SMR and AIC_SSR return the values corresponding to the interrupt
source selected by INTSEL.
The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either
in Level-Sensitive mode or in Edge-Triggered mode. The active level of the internal interrupts is not important for the
user.
© 2020 Microchip Technology Inc.
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SAM9X60
Advanced Interrupt Controller (AIC)
The external interrupt sources can be programmed either in High Level-Sensitive or Low Level-Sensitive modes, or in
Rising Edge-Triggered or Negative Edge-Triggered modes.
26.8.1.2 Interrupt Source Enabling
Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers
Interrupt Enable Command register (AIC_IECR) and Interrupt Disable Command register (AIC_IDCR). The interrupt
mask of the selected interrupt source can be read in the Interrupt Mask register (AIC_IMR). A disabled interrupt does
not affect servicing of other interrupts.
26.8.1.3 Interrupt Clearing and Setting
All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or
cleared by writing respectively the Interrupt Set Command register (AIC_ISCR) and Interrupt Clear Command
register (AIC_ICCR). Clearing or setting interrupt sources programmed in Level-Sensitive mode has no effect.
The clear operation is perfunctory, as the software must perform an action to reset the “memorization” circuitry
activated when the source is programmed in Edge-Triggered mode. However, the set operation is available for autotest or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt.
The AIC features an automatic clear of the current interrupt when AIC_IVR (Interrupt Vector register) is read. Only the
interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See the section
“Priority Controller”.) The automatic clear reduces the operations required by the interrupt service routine entry code
to read AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing
feature enabled, as it is considered uniquely as an FIQ source. (For further details, see the section ”Fast Forcing”).
The automatic clear of interrupt source 0 is performed when the FIQ Vector register (AIC_FVR) is read.
26.8.1.4 Interrupt Status
Interrupt Pending registers (AIC_IPR) represent the state of the interrupt lines, whether they are masked or not.
AIC_IMR can be used to define the mask of the interrupt lines.
The Interrupt Status register (AIC_ISR) reads the number of the current interrupt (see the section ”Priority Controller”)
and the Core Interrupt Status register (AIC_CISR) gives an image of the nIRQ and nFIQ signals driven on the
processor.
Each status referred to above can be used to optimize the interrupt handling of the systems.
26.8.1.5 Internal Interrupt Source Input Stage
Figure 26-4. Internal Interrupt Source Input Stage
AIC_SMRi
(SRCTYPE)
Level/
Edge
Source i
AIC_IPR
AIC_IMR
Edge
Detector
Fast Interrupt Controller
or
Priority Controller
AIC_IECR
Set Clear
FF
AIC_ISCR
AIC_ICCR
AIC_IDCR
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26.8.1.6 External Interrupt Source Input Stage
Figure 26-5. External Interrupt Source Input Stage
High/Low
AIC_SMRi
(SRCTYPE)
Level/
Edge
AIC_IPR
Source i
AIC_IMR
Fast Interrupt Controller
or
Priority Controller
AIC_IECR
Rising/Falling
Edge
Detector
Set
FF
Clear
AIC_IDCR
AIC_ISCR
AIC_ICCR
26.8.2
Interrupt Latencies
Global interrupt latencies depend on several parameters, including:
•
•
•
•
The time the software masks the interrupts
Occurrence, either at the processor level or at the AIC level
The execution time of the instruction in progress when the interrupt occurs
The treatment of higher priority interrupts and the resynchronization of the hardware signals
This section addresses hardware resynchronizations only. It gives details about the latency times between the events
on an external interrupt leading to a valid interrupt (edge or level) or the assertion of an internal interrupt source and
the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of
the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given
assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.
26.8.2.1 External Interrupt Edge Triggered Source
Figure 26-6. External Interrupt Edge Triggered Source
MCK
IRQ or FIQ
(rising edge)
IRQ or FIQ
(falling edge)
nIRQ
Maximum IRQ Latency = 4 cycles
nFIQ
Maximum FIQ Latency = 4 cycles
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26.8.2.2 External Interrupt Level Sensitive Source
Figure 26-7. External Interrupt Level Sensitive Source
MCK
IRQ or FIQ
(high level)
IRQ or FIQ
(low level)
nIRQ
Maximum IRQ
Latency = 3 cycles
nFIQ
Maximum FIQ
Latency = 3 cycles
26.8.2.3 Internal Interrupt Edge Triggered Source
Figure 26-8. Internal Interrupt Edge Triggered Source
MCK
nIRQ
Maximum IRQ Latency = 4.5 Cycles
Peripheral Interrupt
Becomes Active
26.8.2.4 Internal Interrupt Level Sensitive Source
Figure 26-9. Internal Interrupt Level Sensitive Source
MCK
nIRQ
Maximum IRQ Latency = 3.5 cycles
Peripheral Interrupt
Becomes Active
26.8.3
Normal Interrupt
26.8.3.1 Priority Controller
An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on
the interrupt sources 1 to 49 (except for those programmed in Fast Forcing).
Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing
AIC_SMR.PRIOR. Level 7 is the highest priority and level 0 the lowest.
As soon as an interrupt condition occurs, as defined by AIC_SMR.SRCTYPE, the nIRQ line is asserted. As a new
interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority
controller determines the current interrupt at the time AIC_IVR is read. The read of AIC_IVR is the entry point of the
interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software.
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The current priority level is defined as the priority level of the current interrupt.
If several interrupt sources of equal priority are pending and enabled when AIC_IVR is read, the interrupt with the
lowest interrupt source number is serviced first.
The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an
interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software
indicates to the AIC the end of the current service by writing AIC_EOICR (End of Interrupt Command register). The
write of AIC_EOICR is the exit point of the interrupt handling.
26.8.3.2 Interrupt Nesting
The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service
of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt
at the processor level.
When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is
re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt
service routine should read AIC_IVR. At this time, the current interrupt number and its priority level are pushed into
an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is
finished and AIC_EOICR is written.
The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings to match
the eight priority levels.
26.8.3.3 Interrupt Vectoring
The interrupt handler address corresponding to the interrupt source selected by the INTSEL field can be stored in
AIC_SVR (Source Vector register). When the processor reads AIC_IVR, the value written into AIC_SVR
corresponding to the current interrupt is returned. Optionally, the AIC_IVR register can return the current interrupt
number instead. This can be defined separately for each interrupt source using the AIC SVR Return Enable Register
(AIC_SVRRER) and AIC SVR Return Disable Register (AIC_SVRRDR).
This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as
AIC_IVR is mapped at the absolute address 0xFFFFF100 and thus accessible from the ARM interrupt vector at
address 0x00000018 through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus
branching the execution on the correct interrupt handler.
26.8.3.4 Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the
programmer understands the architecture of the ARM processor, and especially the Processor Interrupt modes and
the associated status bits.
It is assumed that:
1.
2.
The AIC has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine
addresses and interrupts are enabled.
The instruction at the ARM interrupt exception vector address is required to work with the vectoring
LDR PC, [PC, # -&F20]
When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:
1.
2.
3.
The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link
register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at
address 0x1C, the ARM core adjusts R14_irq, decrementing it by four.
The ARM core enters Interrupt mode, if it has not already done so.
When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in
AIC_IVR. Reading AIC_IVR has the following effects:
– Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current
level is the priority level of the current interrupt.
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4.
5.
6.
7.
8.
26.8.4
– De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order
to de-assert nIRQ.
– Automatically clears the interrupt, if it has been programmed to be edge-triggered.
– Pushes the current level and the current interrupt number on to the stack.
– Returns the value written in AIC_SVR corresponding to the current interrupt.
The previous step has the effect of branching to the corresponding interrupt service routine. This should start
by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is
saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the
instruction SUB PC, LR, #4 may be used.
Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-assertion of the nIRQ to
be taken into account by the core. This can happen if an interrupt with a higher priority than the current
interrupt occurs.
The interrupt handler can then proceed as required, saving the registers that will be used and restoring them
at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from
step 1.
Note: If the interrupt is programmed to be level-sensitive, the source of the interrupt must be cleared during
this phase.
The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is
completed in an orderly manner.
AIC_EOICR must be written in order to indicate to the AIC that the current interrupt is finished. This causes the
current level to be popped from the stack, restoring the previous current level if one exists on the stack. If
another interrupt is pending, with lower or equal priority than the old current level but with higher priority than
the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start
because the “I” bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is
restored directly into the PC. This has the effect of returning from the interrupt to whatever was being executed
before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the
state saved in SPSR_irq.
Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking
an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is
completed (interrupt is masked).
Fast Interrupt
26.8.4.1 Fast Interrupt Source
Interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is
used. Interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller.
26.8.4.2 Fast Interrupt Control
The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with
AIC_SMR and INTSEL = 0; the PRIOR field of this register is not used even if it reads what has been written.
AIC_SMR.SRCTYPE enables programming the fast interrupt source to be rising-edge triggered or falling-edge
triggered or high-level sensitive or low-level sensitive.
Writing 0x1 in AIC_IECR and AIC_IDCR respectively enables and disables the fast interrupt when INTSEL = 0. Bit 0
of AIC_IMR indicates whether the fast interrupt is enabled or disabled.
26.8.4.3 Fast Interrupt Vectoring
The fast interrupt handler address can be stored through AIC_SVR. The value written into this register when INTSEL
= 0 is returned when the processor reads AIC_FVR (FIQ Vector register). This offers a way to branch in one single
instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible
from the ARM fast interrupt vector at address 0x0000 001C through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction, it loads the value read in AIC_FVR in its program counter, thus
branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt
source if it is programmed in Edge-Triggered mode.
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26.8.4.4 Fast Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the
programmer understands the architecture of the ARM processor, and especially the Processor Interrupt modes and
associated status bits.
Assuming that:
1.
2.
3.
The AIC has been programmed, AIC_SVR is loaded with the fast interrupt service routine address, and
interrupt source 0 is enabled.
The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt:
LDR PC,[PC, # -&F20]
The user does not need nested fast interrupts.
When nFIQ is asserted, if bit “F” of CPSR is 0, the sequence is:
1.
2.
3.
The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register
(R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address
0x20, the ARM core adjusts R14_fiq, decrementing it by four.
The ARM core enters FIQ mode.
When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in
AIC_FVR. Reading AIC_FVR has the effect of automatically clearing the fast interrupt, if it has been
programmed to be edge-triggered. In this case only, it de-asserts the nFIQ line on the processor.
FIQ_Handler_Branch
mov r14, pc
bx r0
4.
5.
6.
The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save
the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed.
The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because
the FIQ mode has its own dedicated registers and registers R8 to R13 are banked. The other registers, R0 to
R7, must be saved before being used, and restored at the end (before the next step).
Note: If the fast interrupt is programmed to be level-sensitive, the source of the interrupt must be cleared
during this phase in order to de-assert interrupt source 0.
Finally, Link register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC,
LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed
before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state
saved in the SPSR.
Note: The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ
interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the interrupted
instruction is completed (FIQ is masked).
Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector
0x1C. This method does not use vectoring, so that reading AIC_FVR must be performed at the very beginning of the
handler operation. However, this method saves the execution of a branch instruction.
26.8.4.5 Fast Forcing
The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on
the fast interrupt controller.
Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable register (AIC_FFER) and the Fast Forcing
Disable register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status register
(AIC_FFSR) that controls the feature for each internal or external interrupt source.
When Fast Forcing is disabled, the interrupt sources are handled as described in the previous sections.
When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt
source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority
handler.
If the interrupt source is programmed in Level-Sensitive mode and an active level is sampled, Fast Forcing results in
the assertion of the nFIQ line to the core.
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If the interrupt source is programmed in Edge-Triggered mode and an active edge is detected, Fast Forcing results in
the assertion of the nFIQ line to the core.
The Fast Forcing feature does not affect the Source 0 pending bit in AIC_IPR.
The FIQ Vector register (AIC_FVR) reads the contents of the Source Vector register (AIC_SVR), whatever the source
of the fast interrupt may be. The read of the FVR does not clear Source 0 when the fast forcing feature is used and
the interrupt source should be cleared by writing to AIC_ICCR.
All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in
Edge-Triggered mode must be cleared by writing to the Interrupt Clear Command register. In doing so, they are
cleared independently and thus lost interrupts are prevented.
The read of AIC_IVR does not clear the source that has the fast forcing feature enabled.
Source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources.
Figure 26-10. Fast Forcing
Source 0 _ FIQ
AIC_IPR
Input Stage
Automatic Clear
AIC_IMR
nFIQ
Read FVR if Fast Forcing is
disabled on Sources 1 to 127.
AIC_FFSR
Source n
AIC_IPR
Input Stage
Automatic Clear
AIC_IMR
Priority
Manager
nIRQ
Read IVR if Source n is the current interrupt
and if Fast Forcing is disabled on Source n.
26.8.5
Protect Mode
The Protect mode is used to read the Interrupt Vector register without performing the associated automatic
operations. This is necessary when working with a debug system. When a debugger, working either with a Debug
Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC
User Interface and thus the IVR. This has adverse consequences:
•
•
If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
If there is no enabled pending interrupt, the spurious vector is returned.
In either case, an End of Interrupt command is necessary to acknowledge and restore the context of the AIC. This
operation is generally not performed by the debug system, as the debug system would become strongly intrusive and
cause the application to enter an undesired state.
This is avoided by using the Protect mode. Writing PROT in the Debug Control register (AIC_DCR) at 0x1 enables
the Protect mode.
When the Protect mode is enabled, the AIC performs interrupt stacking only when a write access is performed on
AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to AIC_IVR just after reading it. The
new context of the AIC, including the value of AIC_ISR, is updated with the current interrupt only when AIC_IVR is
written.
An AIC_IVR read on its own (e.g., by a debugger) modifies neither the AIC context nor AIC_ISR. Extra AIC_IVR
reads perform the same operations. However, it is recommended to not stop the processor between the read and the
write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context.
To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC:
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Advanced Interrupt Controller (AIC)
1.
2.
3.
4.
5.
Calculates active interrupt (higher than current or spurious).
Determines and returns the vector of the active interrupt.
Memorizes the interrupt.
Pushes the current priority level onto the internal stack.
Acknowledges the interrupt.
However, while the Protect mode is activated, only operations 1 to 3 are performed when AIC_IVR is read.
Operations 4 and 5 are only performed by the AIC when AIC_IVR is written.
Software that has been written and debugged using the Protect mode runs correctly in normal mode without
modification. However, in normal mode, the AIC_IVR write has no effect and can be removed to optimize the code.
26.8.6
Spurious Interrupt
The AIC features a protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an
interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is
most prone to occur when:
•
•
•
An external interrupt source is programmed in Level-Sensitive mode and an active level occurs for only a short
time.
An internal interrupt source is programmed in level-sensitive and the output signal of the corresponding
embedded peripheral is activated for a short time (as is the case for the watchdog).
An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the
interrupt source.
The AIC detects a spurious interrupt at the time AIC_IVR is read while no enabled interrupt source is pending. When
this happens, the AIC returns the value stored by the programmer in the Spurious Vector register (AIC_SPU). The
programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable
an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return
from interrupt.
26.8.7
General Interrupt Mask
The AIC features a General Interrupt Mask bit (AIC_DCR.GMSK) to prevent interrupts from reaching the processor.
Both the nIRQ and the nFIQ lines are driven to their inactive state if AIC_DCR.GMSK is set. However, this mask does
not prevent waking up the processor if it has entered Idle mode. This function facilitates synchronizing the processor
on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an
interrupt. It is strongly recommended to use this mask with caution.
26.8.8
Register Write Protection
To prevent any single software error from corrupting AIC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the AIC Write Protection Mode Register (AIC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the AIC Write Protection Status Register
(AIC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading AIC_WPSR.
The following registers can be write-protected:
•
•
•
•
AIC Source Mode Register
AIC Source Vector Register
AIC Spurious Interrupt Vector Register
AIC Debug Control Register
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26.9
Register Summary
Offset
Name
0x00
AIC_SSR
0x04
AIC_SMR
0x08
AIC_SVR
0x0C
...
0x0F
Reserved
0x10
AIC_IVR
0x14
AIC_FVR
0x18
AIC_ISR
0x1C
...
0x1F
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
6
5
4
3
2
1
0
INTSEL[6:0]
SRCTYPE[1:0]
PRIOR[2:0]
VECTOR[31:24]
VECTOR[23:16]
VECTOR[15:8]
VECTOR[7:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
IRQV[31:24]
IRQV[23:16]
IRQV[15:8]
IRQV[7:0]
FIQV[31:24]
FIQV[23:16]
FIQV[15:8]
FIQV[7:0]
IRQID[6:0]
Reserved
0x20
AIC_IPR0
0x24
AIC_IPR1
0x28
AIC_IPR2
0x2C
AIC_IPR3
0x30
AIC_IMR
0x34
Bit Pos.
AIC_CISR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
PID31
PID23
PID15
PID7
PID63
PID55
PID47
PID39
PID95
PID87
PID79
PID71
PID127
PID119
PID111
PID103
© 2020 Microchip Technology Inc.
PID30
PID22
PID14
PID6
PID62
PID54
PID46
PID38
PID94
PID86
PID78
PID70
PID126
PID118
PID110
PID102
PID29
PID21
PID13
PID5
PID61
PID53
PID45
PID37
PID93
PID85
PID77
PID69
PID125
PID117
PID109
PID101
PID28
PID20
PID12
PID4
PID60
PID52
PID44
PID36
PID92
PID84
PID76
PID68
PID124
PID116
PID108
PID100
PID27
PID19
PID11
PID3
PID59
PID51
PID43
PID35
PID91
PID83
PID75
PID67
PID123
PID115
PID107
PID99
PID26
PID18
PID10
PID2
PID58
PID50
PID42
PID34
PID90
PID82
PID66
PID122
PID114
PID106
PID98
PID25
PID17
PID9
SYS
PID57
PID49
PID41
PID33
PID89
PID81
PID73
PID65
PID121
PID113
PID105
PID97
PID24
PID16
PID8
FIQ
PID56
PID48
PID40
PID32
PID88
PID80
PID72
PID64
PID120
PID112
PID104
PID96
INTM
NIRQ
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NFIQ
DS60001579C-page 322
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Advanced Interrupt Controller (AIC)
...........continued
Offset
Name
0x38
AIC_EOICR
0x3C
AIC_SPU
0x40
AIC_IECR
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
...
0x5F
0x60
0x64
0x68
0x6C
0x70
...
0xE3
AIC_IDCR
AIC_ICCR
AIC_ISCR
AIC_FFER
AIC_FFDR
AIC_FFSR
Bit Pos.
7
6
5
4
3
2
1
0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
ENDIT
SIVR[31:24]
SIVR[23:16]
SIVR[15:8]
SIVR[7:0]
INTEN
INTD
INTCLR
INTSET
FFEN
FFDIS
FFS
Reserved
AIC_SVRRER
AIC_SVRRDR
AIC_SVRRSR
AIC_DCR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
SVRREN
SVRRDIS
SVRRS
GMSK
PROT
Reserved
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Advanced Interrupt Controller (AIC)
...........continued
Offset
Name
0xE4
AIC_WPMR
0xE8
AIC_WPSR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
6
5
4
3
2
1
0
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WPEN
WPVSRC[15:8]
WPVSRC[7:0]
WPVS
Complete Datasheet
DS60001579C-page 324
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.1
AIC Source Select Register
Name:
Offset:
Reset:
Property:
Bit
AIC_SSR
0x00
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
3
INTSEL[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 6:0 – INTSEL[6:0] Interrupt Line Selection
0–49 = Selects the interrupt line to handle.
See the section ”Interrupt Source Mode”.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 325
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.2
AIC Source Mode Register
Name:
Offset:
Reset:
Property:
AIC_SMR
0x04
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the AIC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
4
3
2
1
PRIOR[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
5
SRCTYPE[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bits 6:5 – SRCTYPE[1:0] Interrupt Source Type
The active level or edge is not programmable for the internal interrupt source selected by INTSEL.
Value
Name
Description
0
INT_LEVEL_SENSITIVE
High-level sensitive for internal source.
1
2
EXT_NEGATIVE_EDGE
EXT_HIGH_LEVEL
Low-level sensitive for external source.
Negative-edge triggered for external source.
High-level sensitive for internal source.
3
EXT_POSITIVE_EDGE
High-level sensitive for external source.
Positive-edge triggered for external source.
Bits 2:0 – PRIOR[2:0] Priority Level
Programs the priority level of the source selected by INTSEL except FIQ source (source 0).
The priority level can be between 0 (lowest) and 7 (highest).
The priority level is not used for the FIQ.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 326
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.3
AIC Source Vector Register
Name:
Offset:
Reset:
Property:
AIC_SVR
0x08
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the AIC Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
VECTOR[31:24]
R/W
R/W
0
0
20
19
VECTOR[23:16]
R/W
R/W
0
0
12
11
VECTOR[15:8]
R/W
R/W
0
0
4
3
VECTOR[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – VECTOR[31:0] Source Vector
The user may store in this register the address of the corresponding handler for the interrupt source selected by
INTSEL.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 327
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.4
AIC Interrupt Vector Register
Name:
Offset:
Reset:
Property:
Bit
31
AIC_IVR
0x10
0x00000000
Read-only
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
IRQV[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
IRQV[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
IRQV[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
IRQV[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – IRQV[31:0] Interrupt Vector Register
The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register or the
interrupt index corresponding to the current interrupt. (See the sections ”AIC SVR Return Enable Register”, ”AIC SVR
Return Disable Register” and ”AIC SVR Return Status Register”.)
The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read.
When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 328
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.5
AIC FIQ Vector Register
Name:
Offset:
Reset:
Property:
Bit
31
AIC_FVR
0x14
0x00000000
Read-only
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
FIQV[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
FIQV[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
FIQV[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
FIQV[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – FIQV[31:0] FIQ Vector Register
The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register when INTSEL =
0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 329
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.6
AIC Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
AIC_ISR
0x18
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
2
1
0
R
0
R
0
R
0
3
IRQID[6:0]
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 6:0 – IRQID[6:0] Current Interrupt Identifier
The Interrupt Status Register returns the current interrupt source number.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 330
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.7
AIC Interrupt Pending Register 0
Name:
Offset:
Reset:
Property:
AIC_IPR0
0x20
0x00000000
Read-only
The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at
reset, thus not pending.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
PID31
R
0
30
PID30
R
0
29
PID29
R
0
28
PID28
R
0
27
PID27
R
0
26
PID26
R
0
25
PID25
R
0
24
PID24
R
0
23
PID23
R
0
22
PID22
R
0
21
PID21
R
0
20
PID20
R
0
19
PID19
R
0
18
PID18
R
0
17
PID17
R
0
16
PID16
R
0
15
PID15
R
0
14
PID14
R
0
13
PID13
R
0
12
PID12
R
0
11
PID11
R
0
10
PID10
R
0
9
PID9
R
0
8
PID8
R
0
7
PID7
R
0
6
PID6
R
0
5
PID5
R
0
4
PID4
R
0
3
PID3
R
0
2
PID2
R
0
1
SYS
R
0
0
FIQ
R
0
Bits 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 –
PIDx Interrupt Pending
PID2...PID31 refer to the identifiers as defined in the Peripheral Identifiers section.
Value
Description
0
The corresponding interrupt is not pending.
1
The corresponding interrupt is pending.
Bit 1 – SYS Interrupt Pending
Value
Description
0
The corresponding interrupt is not pending.
1
The corresponding interrupt is pending.
Bit 0 – FIQ Interrupt Pending
Value
Description
0
The corresponding interrupt is not pending.
1
The corresponding interrupt is pending.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 331
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.8
AIC Interrupt Pending Register 1
Name:
Offset:
Reset:
Property:
AIC_IPR1
0x24
0x00000000
Read-only
The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at
reset, thus not pending.
PID32...PID63 refer to the identifiers as defined in the Peripheral Identifiers section.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
PID63
R
0
30
PID62
R
0
29
PID61
R
0
28
PID60
R
0
27
PID59
R
0
26
PID58
R
0
25
PID57
R
0
24
PID56
R
0
23
PID55
R
0
22
PID54
R
0
21
PID53
R
0
20
PID52
R
0
19
PID51
R
0
18
PID50
R
0
17
PID49
R
0
16
PID48
R
0
15
PID47
R
0
14
PID46
R
0
13
PID45
R
0
12
PID44
R
0
11
PID43
R
0
10
PID42
R
0
9
PID41
R
0
8
PID40
R
0
7
PID39
R
0
6
PID38
R
0
5
PID37
R
0
4
PID36
R
0
3
PID35
R
0
2
PID34
R
0
1
PID33
R
0
0
PID32
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 –
PIDx Interrupt Pending
Value
Description
0
The corresponding interrupt is not pending.
1
The corresponding interrupt is pending.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 332
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.9
AIC Interrupt Pending Register 2
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
AIC_IPR2
0x28
0x00000000
Read-only
31
PID95
R
0
30
PID94
R
0
29
PID93
R
0
28
PID92
R
0
27
PID91
R
0
26
PID90
R
0
25
PID89
R
0
24
PID88
R
0
23
PID87
R
0
22
PID86
R
0
21
PID85
R
0
20
PID84
R
0
19
PID83
R
0
18
PID82
R
0
17
PID81
R
0
16
PID80
R
0
15
PID79
R
0
14
PID78
R
0
13
PID77
R
0
12
PID76
R
0
11
PID75
R
0
10
9
PID73
R
0
8
PID72
R
0
7
PID71
R
0
6
PID70
R
0
5
PID69
R
0
4
PID68
R
0
3
PID67
R
0
2
PID66
R
0
1
PID65
R
0
0
PID64
R
0
Bits 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Interrupt Pending
Value
Description
0
The corresponding interrupt is not pending.
1
The corresponding interrupt is pending.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 – PIDx Interrupt Pending
Value
Description
0
The corresponding interrupt is not pending.
1
The corresponding interrupt is pending.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 333
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.10 AIC Interrupt Pending Register 3
Name:
Offset:
Reset:
Property:
AIC_IPR3
0x2C
0x00000000
Read-only
The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at
reset, thus not pending.
PID96...PID127 bit fields refer to the identifiers as defined in the Peripheral Identifiers section.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
PID127
R
0
30
PID126
R
0
29
PID125
R
0
28
PID124
R
0
27
PID123
R
0
26
PID122
R
0
25
PID121
R
0
24
PID120
R
0
23
PID119
R
0
22
PID118
R
0
21
PID117
R
0
20
PID116
R
0
19
PID115
R
0
18
PID114
R
0
17
PID113
R
0
16
PID112
R
0
15
PID111
R
0
14
PID110
R
0
13
PID109
R
0
12
PID108
R
0
11
PID107
R
0
10
PID106
R
0
9
PID105
R
0
8
PID104
R
0
7
PID103
R
0
6
PID102
R
0
5
PID101
R
0
4
PID100
R
0
3
PID99
R
0
2
PID98
R
0
1
PID97
R
0
0
PID96
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 –
PIDx Interrupt Pending
Value
Description
0
The corresponding interrupt is not pending.
1
The corresponding interrupt is pending.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 334
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.11 AIC Interrupt Mask Register
Name:
Offset:
Reset:
Property:
Bit
AIC_IMR
0x30
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTM
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – INTM Interrupt Mask
Value
Description
0
The interrupt source selected by AIC_SSR.INTSEL is disabled.
1
The interrupt source selected by AIC_SSR.INTSEL is enabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 335
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.12 AIC Core Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
AIC_CISR
0x34
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NIRQ
R
0
0
NFIQ
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – NIRQ NIRQ Status
Value
Description
0
nIRQ line is deactivated.
1
nIRQ line is active.
Bit 0 – NFIQ NFIQ Status
Value
Description
0
nFIQ line is deactivated.
1
nFIQ line is active.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 336
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.13 AIC End of Interrupt Command Register
Name:
Offset:
Reset:
Property:
Bit
AIC_EOICR
0x38
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ENDIT
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – ENDIT Interrupt Processing Complete Command
The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is
complete. Any value can be written because it is only necessary to make a write to this register location to signal the
end of interrupt treatment.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 337
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.14 AIC Spurious Interrupt Vector Register
Name:
Offset:
Reset:
Property:
AIC_SPU
0x3C
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the AIC Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
SIVR[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
SIVR[23:16]
R/W
R/W
0
0
12
SIVR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
SIVR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – SIVR[31:0] Spurious Interrupt Vector Register
The user may store the address of a spurious interrupt handler in this register. The written value is returned in
AIC_IVR in case of a spurious interrupt, or in AIC_FVR in case of a spurious fast interrupt.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 338
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.15 AIC Interrupt Enable Command Register
Name:
Offset:
Reset:
Property:
Bit
AIC_IECR
0x40
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTEN
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – INTEN Interrupt Enable
Value
Description
0
No effect.
1
Enables the interrupt source selected by AIC_SSR.INTSEL.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 339
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.16 AIC Interrupt Disable Command Register
Name:
Offset:
Reset:
Property:
Bit
AIC_IDCR
0x44
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTD
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – INTD Interrupt Disable
Value
Description
0
No effect.
1
Disables the interrupt source selected by AIC_SSR.INTSEL.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 340
SAM9X60
Advanced Interrupt Controller (AIC)
26.9.17 AIC Interrupt Clear Command Register
Name:
Offset:
Reset:
Property:
Bit
AIC_ICCR
0x48
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTCLR
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – INTCLR Interrupt Clear
Clears one the following depending on the setting of AIC_SSR.INTSEL: FIQ, SYS, PID2-PID49
Value
Description
0
No effect.
1
Clears the interrupt source selected by AIC_SSR.INTSEL.
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.18 AIC Interrupt Set Command Register
Name:
Offset:
Reset:
Property:
Bit
AIC_ISCR
0x4C
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTSET
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – INTSET Interrupt Set
Value
Description
0
No effect.
1
Sets the interrupt source selected by INTSEL.
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.19 AIC Fast Forcing Enable Register
Name:
Offset:
Reset:
Property:
Bit
AIC_FFER
0x50
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FFEN
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – FFEN Fast Forcing Enable
Value
Description
0
No effect.
1
Enables the fast forcing feature on the interrupt source selected by INTSEL.
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.20 AIC Fast Forcing Disable Register
Name:
Offset:
Reset:
Property:
Bit
AIC_FFDR
0x54
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FFDIS
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – FFDIS Fast Forcing Disable
Value
Description
0
No effect.
1
Disables the Fast Forcing feature on the interrupt source selected by INTSEL.
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Complete Datasheet
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.21 AIC Fast Forcing Status Register
Name:
Offset:
Reset:
Property:
Bit
AIC_FFSR
0x58
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FFS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – FFS Fast Forcing Status
Value
Description
0
The Fast Forcing feature is disabled on the interrupt source selected by INTSEL.
1
The Fast Forcing feature is enabled on the interrupt source selected by INTSEL.
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.22 AIC SVR Return Enable Register
Name:
Offset:
Reset:
Property:
Bit
AIC_SVRRER
0x60
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SVRREN
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – SVRREN SVR Return Enable
Value
Description
0
No effect.
1
IVR register returns the interrupt index for the interrupt source selected by INTSEL.
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Complete Datasheet
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.23 AIC SVR Return Disable Register
Name:
Offset:
Reset:
Property:
Bit
AIC_SVRRDR
0x64
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SVRRDIS
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – SVRRDIS SVR Return Disable
Value
Description
0
No effect.
1
IVR register returns the corresponding vector programmed in AIC_SVR for the interrupt source
selected by INTSEL.
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Complete Datasheet
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.24 AIC SVR Return Status Register
Name:
Offset:
Reset:
Property:
Bit
AIC_SVRRSR
0x68
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SVRRS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – SVRRS SVR Return Status
Value
Description
0
IVR register returns the corresponding vector programmed in AIC_SVR for the interrupt source
selected by INTSEL.
1
IVR register returns the interrupt index for the interrupt source selected by INTSEL.
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.25 AIC Debug Control Register
Name:
Offset:
Reset:
Property:
AIC_DCR
0x6C
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the AIC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GMSK
R/W
0
0
PROT
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – GMSK General Interrupt Mask
Value
Description
0
The nIRQ and nFIQ lines are normally controlled by the AIC.
1
The nIRQ and nFIQ lines are tied to their inactive state.
Bit 0 – PROT Protection Mode
Value
Description
0
The Protection mode is disabled.
1
The Protection mode is enabled.
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.26 AIC Write Protection Mode Register
Name:
Offset:
Reset:
Property:
AIC_WPMR
0xE4
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x414943 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
Bit 0 – WPEN Write Protection Enable
See section ”Register Write Protection” for the list of registers that can be protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x414943 (“AIC” in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x414943 (“AIC” in ASCII).
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Complete Datasheet
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SAM9X60
Advanced Interrupt Controller (AIC)
26.9.27 AIC Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
AIC_WPSR
0xE8
0x00000000
Read-only
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
WPVSRC[15:8]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
4
2
1
0
WPVS
R
0
Access
Reset
3
Access
Reset
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 0 – WPVS Write Protection Violation Status
Value
Description
0
No write protection violation has occurred since the last read of AIC_WPSR.
1
A write protection violation has occurred since the last read of AIC_WPSR. If this violation is an
unauthorized attempt to write a protected register, the associated violation is reported into field
WPVSRC.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Slow Clock Controller (SCKC)
27.
27.1
Slow Clock Controller (SCKC)
Description
The System Controller embeds a Slow Clock Controller (SCKC). The SCKC selects the slow clock for the RTT and
the RTC from one of two sources:
•
•
27.2
Embedded Characteristics
•
•
27.3
External 32.768 kHz crystal oscillator
Embedded 32 kHz (typical) RC oscillator
32 kHz (typical) RC Oscillator or 32.768 kHz Crystal Oscillator Selector
VDDBU Powered
Block Diagram
Figure 27-1. Block Diagram
MD_SLCK
Slow
RC Oscillator
TD_SLCK
XIN32
XOUT32
32.768 kHz
Crystal
Oscillator
TD_OSCSEL
OSC32EN
OSC32BYP
27.4
Functional Description
The TD_OSCSEL bit located in the Slow Clock Controller Configuration register (SCKC_CR) is in the backup domain
and its value is kept while VDDBU is present.
The embedded 32 kHz (typical) Slow RC oscillator is always enabled as soon as VDDBU is established. The Slow
Clock Selector command TD_OSCSEL bit selects the slow clock source of the RTT and the RTC.
After the VDDBU power-on reset, the default configuration is TD_OSCSEL = 0.
The programmer controls the slow clock switching by software, so precautions must be taken during the switching
phase.
27.4.1
Switching from Embedded 32 kHz RC Oscillator to 32.768 kHz Crystal Oscillator
The sequence to switch from the embedded 32 kHz (typical) RC oscillator to the 32.768 kHz crystal oscillator is the
following:
1.
2.
Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power
Management Controller.
Switch from the embedded 32 kHz (typical) RC oscillator to the 32.768 kHz crystal oscillator by writing a 1 to
the TD_OSCSEL bit.
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Complete Datasheet
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SAM9X60
Slow Clock Controller (SCKC)
3.
27.4.2
Wait 5 slow clock cycles for internal resynchronization.
Bypassing the 32.768 kHz Crystal Oscillator
The sequence to bypass the 32.768 kHz crystal oscillator is the following:
1.
2.
3.
27.4.3
An external clock must be connected on XIN32.
Enable the bypass path by writing a 1 to the OSC32BYP bit.
Disable the 32.768 kHz crystal oscillator by writing a 0 to the OSC32EN bit.
Switching from 32.768 kHz Crystal Oscillator to Embedded 32 kHz RC Oscillator
The sequence to switch from the 32.768 kHz crystal oscillator to the embedded 32 kHz (typical) RC oscillator is the
following:
1.
2.
3.
4.
Switch the master clock to a source different from slow clock (PLL or Main Oscillator).
Switch from the 32.768 kHz crystal oscillator to the embedded RC oscillator by writing a 0 to the TD_OSCSEL
bit.
Wait 5 slow clock cycles for internal resynchronization.
Disable the 32.768 kHz crystal oscillator by writing a 0 to the OSC32EN bit.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Slow Clock Controller (SCKC)
27.5
Register Summary
Offset
Name
Bit Pos.
0x00
SCKC_CR
31:24
23:16
15:8
7:0
7
© 2020 Microchip Technology Inc.
6
5
4
3
2
1
0
TD_OSCSEL
OSC32BYP
Complete Datasheet
OSC32EN
DS60001579C-page 354
SAM9X60
Slow Clock Controller (SCKC)
27.5.1
Slow Clock Controller Configuration Register
Name:
Offset:
Reset:
Property:
SCKC_CR
0x0
0x00000001
Read/Write
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register
(SYSC_WPMR).
Bit
31
30
29
28
27
26
25
24
TD_OSCSEL
R/W
0
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
OSC32BYP
R/W
0
1
OSC32EN
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 24 – TD_OSCSEL Timing Domain Slow Clock Selector
Value
Description
0 (RC)
Slow clock of the timing domain is driven by the embedded RCFREQ kHz (typical) RC oscillator.
1 (XTAL) Slow clock of the timing domain is driven by the 32.768 kHz crystal oscillator.
Bit 2 – OSC32BYP 32.768 kHz Crystal Oscillator Bypass
Value Description
0
32.768 kHz crystal oscillator is not bypassed.
1
32.768 kHz crystal oscillator is bypassed and accepts an external slow clock on XIN32.
Bit 1 – OSC32EN 32.768 kHz Crystal Oscillator
Value
Description
0
32.768 kHz crystal oscillator is disabled.
1
32.768 kHz crystal oscillator is enabled.
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SAM9X60
Clock Generator
28.
Clock Generator
28.1
Description
The Clock Generator user interface is embedded within the Power Management Controller and is described in the
29.16 Register Summary. However, the Clock Generator registers are named CKGR_.
28.2
Embedded Characteristics
The Clock Generator is made up of:
•
•
Oscillators
– A low-power 32.768 kHz oscillator supporting crystals, resonators and Bypass mode (referred to as
“32.768 KHz crystal oscillator” throughout the document)
– An embedded always-on, slow RC oscillator generating a typical 32 kHz clock
– A 12 to 48 MHz oscillator supporting crystals, resonators and Bypass mode (referred to as “main crystal
oscillator” throughout the document)
– A main RC oscillator generating a typical 12 MHz clock
Two fractional-N PLLs with an input range of 12 to 48 MHz and an internal frequency range of 600 to 1200 MHz
The Clock Generator provides the following clocks:
•
•
•
•
MD_SLCK—Monitoring domain slow clock. This clock, sourced from the always-on slow RC oscillator only, is
the only permanent clock of the system and feeds safety-critical functions of the device (WDT, RSTC, SCKC,
frequency monitors and detectors, PMC startup time counters).
TD_SLCK—Timing domain slow clock. This clock, sourced from the 32.768 kHz crystal oscillator or the alwayson slow RC oscillator, is routed to the RTC and RTT peripherals.
MAINCK—Output of the main clock oscillator selection. This clock is either the main crystal oscillator or the main
RC oscillator.
PLL Clocks—Outputs of embedded PLLs
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SAM9X60
Clock Generator
28.3
Block Diagram
Figure 28-1. Clock Generator Block Diagram
Clock Generator
SCKC_CR.TD_OSCSEL
Slow RC
Oscillator
0
Timing Domain Slow Clock
(TD_SLCK)
32.768 kHz
Crystal
Oscillator
XOUT32
XIN32
1
Monitoring Domain Slow Clock
(MD_SLCK)
SCKC_CR.OSC32BYP
MOSCRCEN
MOSCSEL
Main
RC Oscillator
XOUT
Main Clock
(MAINCK)
Main
Crystal
Oscillator
XIN
CKGR_MOR.MOSCXTEN
UPLL
UPLLCK
PLLA
PLLACK
MAINCK
Status
Control
Power Management
Controller
User Interface
28.4
Slow Clock
The PMC does not control the slow clock generation. The control of the slow clock is performed by the Slow Clock
Controller (SCKC) which embeds a slow clock generator that is supplied with the VDDBU power supply. As soon as
VDDBU is supplied, both the 32.768 kHz crystal oscillator and the slow RC oscillator are powered, but only the slow
RC oscillator is enabled.
MD_SLCK is always generated by the slow RC oscillator.
TD_SLCK is generated either by the 32.768 kHz crystal oscillator or by the slow RC oscillator.
The TD_SLCK source clock selection is made via the TD_OSCSEL bit in the Slow Clock Controller Configuration
register (SCKC_CR).
28.4.1
Slow RC Oscillator (32 kHz typical)
The slow RC oscillator is a permanent clock that is the source clock of MD_SLCK and the default source clock of
TD_SLCK.
Compared to the 32.768 kHz crystal oscillator, this oscillator offers a faster startup time and is less exposed to the
external environment, as it is fully integrated. However, its output frequency is subject to larger variations with supply
voltage, temperature and manufacturing process. Therefore, the user must take these variations into account when
this oscillator is used as a time base (startup counter, frequency monitor, etc.). Refer to the section “Electrical
Characteristics”.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Clock Generator
28.4.2
32.768 kHz Crystal Oscillator
By default, the 32.768 kHz oscillator is disabled. To use this oscillator, the XIN32 and XOUT32 pins must be
connected to a 32.768 kHz crystal or to a ceramic resonator. Refer to the section “Electrical Characteristics” for
appropriate loading capacitors selection on XIN32 and XOUT32.
To select the 32.768 kHz crystal oscillator as the source of TD_SLCK, SCKC_CR.TD_OSCSEL must be set. The
switch of TD_SLCK source is glitch-free.
Reverting to the slow RC oscillator is only possible by shutting down the VDDBU power supply.
The user can also set the 32.768 kHz crystal oscillator in Bypass mode instead of connecting a crystal. In this case,
the user must provide the external clock signal on XIN32. For input characteristics of the XIN32 pin, refer to the
section “Electrical Characteristics”. To enter Bypass mode, the OSC32BYP bit of the Slow Clock Controller
Configuration register (SCKC_CR) must be set prior to setting SCKC_CR.TD_OSCSEL.
28.5
Main Clock
The main clock (MAINCK) has two sources:
•
•
A main RC oscillator with a fast startup time and that is selected by default to start the system
A main crystal oscillator with Bypass mode
Figure 28-2. Main Clock (MAINCK) Block Diagram
CKGR_MOR
MOSCRCEN
PMC_SR
MOSCRCS
Main RC
Oscillator
CKGR_MOR
PMC_SR
MOSCSEL
MOSCSELS
0
CKGR_MOR
MAINCK
Main Clock
MOSCXTEN
1
XOUT
XIN
Main Crystal
Oscillator
MOSCXTEN
CKGR_MOR
28.5.1
Main RC Oscillator
After reset, the main RC oscillator is enabled. This oscillator is selected as the source of MAINCK. MAINCK is the
default clock selected to start the system.
The main RC oscillator is calibrated in production. For output frequency specifications, refer to the section “Electrical
Characteristics”.
The software can disable or enable the main RC oscillator with the MOSCRCEN bit in the Clock Generator Main
Oscillator register (CKGR_MOR).
When disabling the main RC oscillator by clearing the CKGR_MOR.MOSCRCEN bit, the PMC_SR.MOSCRCS bit is
automatically cleared, indicating that the oscillator is off.
Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) triggers an
interrupt to the processor.
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Complete Datasheet
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SAM9X60
Clock Generator
28.5.2
Main RC Oscillator Frequency Adjustment
The user can adjust the value of the main RC oscillator frequency by modifying the trimming values set in production
by Microchip. This may be used to compensate frequency drifts due to temperature or voltage.
By default, PMC_OCR.SEL12 is cleared, so the main RC oscillator is driven with the factory-defined calibration bits
which are programmed during chip production.
In order to adjust the oscillator frequency, PMC_OCR.SEL12 must be set to ‘1’ and a valid value must be configured
in PMC_OCR.CAL12.
It is possible to adjust the oscillator frequency while operating from this oscillator.
When reading the PMC_OCR register, the CAL12 field contains the value of the trimming that is currently sent to the
main RC oscillator. This means that the read value is either the factory-defined value (PMC_OCR.SEL12=’0’) or the
value written in the register by the user (PMC_OCR.SEL12=’1’).
At any time, the user can measure the main RC oscillator output frequency by means of the main frequency counter
(see Main Frequency Counter). Once the frequency measurement is done, the main RC oscillator calibration field
CAL12 can be adjusted accordingly to correct this oscillator output frequency.
28.5.3
Main Crystal Oscillator
After reset, the main crystal oscillator is disabled and is not selected as the source of MAINCK.
The software enables or disables this oscillator in order to reduce power consumption via CKGR_MOR.MOSCXTEN.
When disabling this oscillator by clearing CKGR_MOR.MOSCXTEN, the PMC_SR.MOSCXTS status bit is
automatically cleared, indicating the oscillator is off. To activate the Main Crystal Oscillator Bypass mode, see
Bypassing the Main Crystal Oscillator.
When enabling this oscillator, the user must initiate the startup time counter. The startup time depends on the
characteristics of the external device connected to this oscillator.
When CKGR_MOR.MOSCXTEN and CKGR_MOR.MOSCXTST are written to enable this oscillator, XIN and XOUT
are driven by the main crystal oscillator. PMC_SR.MOSCXTS is cleared and the counter starts counting down on
MD_SLCK divided by 8 from the CKGR_MOR.MOSCXTST value. Since the CKGR_MOR.MOSCXTST value is
coded with 8 bits, the startup time can be programmed up to 2048 MD_SLCK periods, corresponding to about 62 ms
when running at 32.768 kHz.
When the startup time counter reaches ‘0’, PMC_SR.MOSCXTS is set, indicating that the oscillator is stabilized.
Setting the MOSCXTS bit in the Interrupt Mask Register (PMC_IMR) can trigger an interrupt to the processor.
28.5.4
Main Clock Source Selection
The source of MAINCK can be selected from the following:
•
•
•
the main RC oscillator
the main crystal oscillator
an external clock signal provided on the XIN input (Bypass mode of the main crystal oscillator)
The advantage of the main RC oscillator is its fast startup time. By default, this oscillator is selected to start the
system and it must be selected prior to entering ULP mode 1.
The advantage of the main crystal oscillator is its high level of accuracy.
The selection of the oscillator is made by configuring CKGR_MOR.MOSCSEL. The switchover of the MAINCK
source is glitch-free, thus the switchover can be performed even if MCK is fed by MAINCK. PMC_SR.MOSCSELS
indicates when the switch sequence is done.
Setting PMC_IMR.MOSCSELS triggers an interrupt to the processor.
28.5.5
Bypassing the Main Crystal Oscillator
Prior to bypassing the main crystal oscillator, the XOUT pin must be grounded and the external clock frequency
provided on the XIN pin must be stable and within the values specified in the XIN Clock characteristics in the section
“Electrical Characteristics”. Then the main crystal oscillator must be enabled by setting the CKGR_MOR.MOSCXTEN
bit to 1.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Clock Generator
28.5.6
Main Frequency Counter
The main frequency counter measures the main RC oscillator or the main crystal oscillator against the MD_SLCK
and is managed by CKGR_MCFR.
During the measurement period, the main frequency counter increments at the speed of the clock defined by the bit
CKGR_MCFR.CCSS.
A measurement is started in the following cases:
•
•
•
•
When CKGR_MCFR.RCMEAS is written to ‘1’.
When the main RC oscillator is selected as the source of MAINCK and when this oscillator is stable (i.e., when
the MOSCRCS bit is set)
When the main crystal oscillator is selected as the source of MAINCK and when this oscillator is stable (i.e.,
when the MOSCXTS bit is set)
When MAINCK source selection is modified
The measurement period ends at the 16th falling edge of MD_SLCK, the MAINFRDY bit in CKGR_MCFR is set and
the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of clock
cycles during 16 periods of MD_SLCK, so that the frequency of the main RC oscillator or main crystal oscillator can
be determined.
When switching the source of MAINCK from the main RC oscillator to the main crystal oscillator, follow the
programming sequence below to ensure that the oscillator is present and that its frequency is valid:
1.
2.
3.
4.
5.
6.
Enable the main crystal oscillator by setting CKGR_MOR.MOSCXTEN. Configure the CKGR_MOR.
MOSCXTST field with the main crystal oscillator startup time as defined in the section “Electrical
Characteristics”.
Wait for PMC_SR.MOSCXTS flag to rise, indicating the end of a startup period of the main crystal oscillator.
Select the main crystal oscillator as the source clock of the main frequency counter by setting
CKGR_MCFR.CCSS.
Initiate a frequency measurement by setting CKGR_MCFR.RCMEAS.
Read CKGR_MCFR.MAINFRDY until its value equals 1.
Read CKGR_MCFR.MAINF and compute the value of the main crystal frequency.
If the MAINF value is valid, software can switch MAINCK to the main crystal oscillator. See Main Clock Source
Selection.
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SAM9X60
Clock Generator
Figure 28-3. Main Frequency Counter Block Diagram
MOSCXTST
PMC_SR
Main Crystal
Oscillator Startup
Counter
MD_SLCK
MOSCXTS
CKGR_MOR
MOSCRCEN
CKGR_MOR
CKGR_MCFR
MOSCXTEN
RCMEAS
CKGR_MOR
MOSCSEL
CKGR_MCFR
Main RC
Oscillator
0
Main Crystal
Oscillator
Reference
Clock
MAINF
Main Frequency
Counter
CKGR_MCFR
MAINFRDY
1
CCSS
CKGR_MCFR
28.6
PLL Controls
The PMC embeds 2 PLLs (PLLA and UPLL) that are controlled by the PMC_PLL_CTRL0, PMC_PLL_CTRL1,
PMC_PLL_SSR, PMC_PLL_ACR and PMC_PLL_UPDATE registers. Each PLL is accessed in read or write through
its index as defined in the table below, corresponding to the register field PMC_PLL_UPDT.ID. At any time,
PLL_CTRL0, PLL_CTRL1 and PLL_ACR reflect the controls for the PLL with index PMC_PLL_UPDT.ID. When the
UPDATE bit is set in PMC_PLL_UPDT, the PLL of index PMC_PLL_UPDT.ID is updated with the content of registers
PLL_CTRL0, PLL_CTRL1 and PLL_ACR.
PLLA is fed by MAINCK while UPLL is fed by the main crystal oscillator. Each PLL has a constraint on the frequency
it can generate on its clock output. Refer to the section “Electrical Characteristics”.
The table below describes all PLLs with their names and source clocks. For maximum frequency, refer to the section
“Electrical Characteristics”.
Table 28-1. PLL IDs
28.6.1
Index
Name
Clock Source
0
PLLA
MAINCK
1
UPLL
MAINXTAL
Divider and Phase Lock Loop Programming
Each PLL is controlled the same way. The internal clock frequency is configured by setting PMC_PLL_CTRL1.MUL
and PMC_PLL_CTRL1.FRACR.
PLLA can apply a division ratio on this internal clock to generate the clock for the PMC (PLLACK). UPLL always
divides the internal clock by two to generate the clock for the PMC (UPLLCK) and the UTMI USB.
The COREPLLCK operating frequency is defined as:
�COREPLLCK = �ref MUL + 1 +
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SAM9X60
Clock Generator
The PLLA clock frequency is defined by the following formula:
�COREPLLCK
DIVPMC + 1
�PLL Clock =
The UPLL clock frequency is defined by the following formula:
�PLL Clock =
�COREPLLCK
2
Each PLL sends a lock signal to the PMC to indicate its lock status. Once the lock signal has risen, the clock
generated by the PLL is stable and can be sent to the PMC.
This signal reports the lock status of the PLL by setting the corresponding PMC_PLL_CTRL0.ENLOCK to ‘1’.
If the lock status is disabled, a startup time can be used instead in the PMC_PLL_UPDT register. The startup time is
expressed as a number of MD_SLCK cycles. Once the counter has reached the specified value, a flag rises. The
startup time field can only be written while all PLLs are disabled (i.e., their PLLEN fields are null).
If both a startup time and the lock are enabled, the lock sent by the PLL is read once the startup time has elapsed.
If neither the startup time nor the lock are enabled, there is no way to know the lock status of the PLL.
The PLL also embeds an unlock status that informs when the PLL lock is lost. When enabled, this status is read once
the startup time (if defined) has elapsed.
The lock and unlock status can be used as interrupts.
See the following figure.
Figure 28-4. PLL Controls
PMC_PLL_CTRL0
PMC_PLL_CTRL0
PMC_PLL_CTRL0
ENPLL
ENPLLCK
DIVPMC
MAINCK or mainxtalck
PLL
CORE
ON/OFF
COREPLLCK
div by (DIVPMC+1)*
PLL Clock (to PMC)
*: only div by 2 for UPLL
PMC_PLL_UPDT
UPDATE
FRACR
MUL
PMC_PLL_CTRL1
PLLx
PLL_UNLOCK
COUNTER_END
UNLOCKx
PMC_PLL_ISR
UNLOCKx
PLL_LOCK
PMC_PLL_IMR
PMC_PLL_UPDT
PLL_INT
ENLOCK
PMC_SR
STUPTIM
PMC_PLL_CTRL0
MD_SLCK
Counter
==
STUPTIM
COUNTER_END
LOCKx
PMC_PLL_ISR
LOCKx
PMC_PLL_IMR
Follow the steps below to enable a PLL:
1.
2.
3.
4.
5.
6.
7.
Define the ID (ID=n) and startup time by configuring the fields PMC_PLL_UPDT.ID and
PMC_PLL_UPDT.STUPTIM. Set PMC_PLL_UPDT.UPDATE to ‘0’.
Configure PMC_PLL_ACR.LOOP_FILTER.
Define the MUL and FRACR to be applied to PLL(n) in PMC_PLL_CTRL1.
In case UPLL is being configured, follow Step 4. to Step 7., otherwise jump to Step 8.
Write PMC_PLL_ACR.UTMIBG to ‘1’ to enable the UTMI internal bandgap.
Wait 10 µs.
Write PMC_PLL_ACR.UTMIVR to ‘1’ to enable the UTMI internal regulator.
Wait 10 µs.
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SAM9X60
Clock Generator
8.
9.
10.
11.
12.
13.
Set PMC_PLL_UPDT.UPDATE to ‘1’. PMC_PLL_UPDT.ID must equal the one written during Step 1.,
otherwise the update is cancelled.
In PMC_PLL_CTRL0, write a ‘1’ to ENLOCK and to ENPLL and configure DIVPMC (for PLLA only, as UPLL
has a fixed divider value) and ENPLLCK.
Set PMC_PLL_UPDT.UPDATE to ‘1’. PMC_PLL_UPDT.ID must equal the one written during Step 1. otherwise
the update is cancelled.
Wait for the lock bit to rise by polling the PMC_PLL_ISR0 or by enabling the corresponding interrupt in
PMC_PLL_IER.
Disable the interrupt (if enabled).
Enable the unlock interrupt to quickly detect a failure on the generation of the PLL clock.
Once enabled (PMC_PLL_CTRL0.ENPLL=1), the PLL core generates its core clock (COREPLLCK).
Once the PLL has been enabled and has locked, the PLL configuration can be modified without switching off the cell.
The clock generated by the PLL is sent to the PMC if ENPLLCK has been set to ‘1’ and the
PMC_PLL_UPDT.UPDATE bit has then been written to ‘1’.
To disable a PLL, the following sequence must be applied:
1.
2.
3.
4.
5.
6.
7.
28.6.2
If the PLL drives a section of the system that is active, modify the source clock of the system.
Define the ID (ID=n) of the PLL to be switched off in PMC_UPDT. The bit UPDATE in this register must be set
at 0 in this step.
In PMC_PLL_CTRL0, set ENPLLCK to 0 and leave ENPLL at ‘1’.
Set PMC_PLL_UPDT.UPDATE to ‘1’. PMC_PLL_UPDT.ID must equal the one written during step 2, otherwise
the update is cancelled.
Write a ‘0’ to PMC_PLL_CTRL0.ENPLL.
In case a UPLL is being powered down, write a ‘0’ to PMC_PLL_ACR.UTMIBG and PMC_PLL_ACR.UTMIVR.
Set PMC_PLL_UPDT.UPDATE to ‘1’. PMC_PLL_UPDT.ID must equal the one written during Step 2.,
otherwise the update is cancelled.
PLL Unlock
Each PLL has an unlock flag. It is recommended to set the UNLOCK interrupt by setting the corresponding
PMC_PLL_IER.UNLOCK bit to quickly detect a failure on PLL clock generation.
The rise of a PLL unlock signal implies a failure in the normal operation of the PLL (e.g., input clock loss). In this
case, the PLL keeps operating but stops trying to lock the input clock. A manual clock switching to a stable clock
should be performed to ensure CPU_CLK integrity
28.6.3
Spread Spectrum
Spread spectrum is obtained by slightly modifying the PLL target frequency. Two parameters are used to configure
the spread spectrum:
•
•
STEP—the frequency step
NSTEP—the number of times the STEP will be applied
The spread spectrum can be applied only if the PLL is already enabled and locked. Once the spread spectrum has
been enabled, it is no longer possible to modify the target frequency of the PLL. Prior to change the PLL frequency,
the spread spectrum must be disabled and a period of 2 x NSTEP cycles of the PLL source clock must elapse.
When enabled, the spread spectrum logic modifies the fractional part of the PLL. The fractional factor applied to the
PLL is in the following range: FRACR - (64 x STEP x NSTEP) up to FRACR.
Starting from the base frequency of the PLL configured in PMC_PLL_CTRL1 (MUL, FRACR), the spread spectrum
mechanism decreases the PLL frequency, and when the minimum is reached, the PLL frequency is increased up to
the value configured through the PMC_PLL_CTRL1 register (the PLL frequency never overpasses that value).
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SAM9X60
Clock Generator
Figure 28-5. Spread Spectrum Mechanism
Reference clock
fPLL
fref(MUL+1+
FRACR
)
222
fref
STEP.26
222
fref
FRACR-NSTEP.STEP.26
)
fref(MUL+1+
222
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SAM9X60
Power Management Controller (PMC)
29.
Power Management Controller (PMC)
29.1
Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user
peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and to the processor.
The Slow Clock Controller (SCKC) selects the source of TD_SLCK (drives the real-time part (RTT/RTC)). The source
of MD_SLCK (drives the rest of the system controller: wakeup logic, watchdog, PMC, etc.) is always the slow RC
oscillator.
By default, at startup, the chip runs out of MCK using the main RC oscillator.
29.2
Embedded Characteristics
The Power Management Controller provides the following clocks:
•
•
•
•
•
•
•
Master Clock (MCK)—programmable from a few hundred Hz to the maximum operating frequency of the device.
It is available to the modules running permanently.
Processor Clock (CPU_CLK)—can be tuned through a frequency scaler module and automatically switched off
when entering the processor in Sleep mode.
Free-running Processor Clock (FCLK)—the source clock of CPU_CLK. Is not affected when Sleep mode is
activated.
UHDP Clocks (UHP48M and UHP12M)—required by USB Host Device Port operations.
Peripheral Clocks with independent on/off control, provided to the peripherals. Each peripheral clock is inherited
from MCK.
Programmable Clock Outputs (PCKx), selected from the clock generator outputs to drive the device PCKx pins.
Generic Clock (GCLK) with controllable division and on/off control, independent of MCK and CPU_CLK.
Provided to selected peripherals. Refer to the table “Peripheral Identifiers” for more details on GCLK availability
per peripheral.
The Power Management Controller also provides the following features on clocks:
•
•
•
•
A main crystal oscillator failure detector
A 32.768 kHz crystal oscillator frequency monitor
A frequency counter on main crystal oscillator or main RC oscillator
An MCK failure detector
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Power Management Controller (PMC)
29.3
Block Diagram
Figure 29-1. General Clock Distribution Block Diagram
Free Running Clock (FCLK)
2X Master Clock (MCK_2X)
Divider
/1,/1.5,/2
Timing Domain
Slow Clock
(TD_SLCK)
to RTT, RTC
XOUT32
XIN32
Monitoring Domain
Slow Clock
(MD_SLCK)
QSPI 2x MCK
QSPICLK
MDIV
(PMC_SCER/SCDR/SCSR)
(see note)
MD_SLCK
MAINCK
PLLACK
UPLLCK
Prescaler
/1,/2,/3,/4,/8,
/16,/32,/64
CSS
Clock
Generator
DDR 2x MCK
DDRCLK
Processor Clock Controller
(PMC_CPU_CKR)
Divider
/1,/2,/3,/4
Processor
Clock
Controller
Interrupt
Sleep Mode
Master Clock (MCK)
PRES
Peripheral Clock Controller
(PMC_PCR)
Main Clock
(MAINCK)
periph_clk[PID]
(to peripherals)
PLLACK
UPLLCK
TD_SLCK
MD_SLCK
MAINCK
MCK
XOUT
XIN
Processor Clock (CPU_CLK)
EN(PID)
GCLK[PID]
(to peripherals)
Prescaler
/1,/2,/3,...,/256
GCLKEN(PID)
GCLKDIV(PID)
GCLKCSS(PID)
PLLACK
Status
Control
Power
Management
Controller
User Interface
Programmable Clock Controller
(PMC_PCKx)
MD_SLCK
TD_SLCK
MAINCK
Prescaler
/1 to /256
granularity=1
MCK
PLLACK
PCKx
UPLLCK
PRES
CSS
USB Clock Controller (PMC_USB)
PLLACK
Divider
/1,/2,/3...,/16
UPLLCK
MAINXTALCK
USBDIV
UHP48M
UHP12M
/4
USBS
PCK[..]
(to I/O pins)
(PMC_SCER/SCDR)
UPLLCK
UHP
periph_clk[UHPHS]
periph_clk[UDPHS]
UHPHS
UDPHS
Note: MDIV should always be different from 0 when using DDR memories. If MDIV must be set to 0, first switch the DDR memories to Self-refresh mode and disable DDRCLK.
29.4
Processor Clock Controller
The PMC features a Processor Clock (CPU_CLK) controller that implements the processor Sleep mode. CPU_CLK
can be disabled by executing the WFI (WaitForInterrupt) processor instruction.
CPU_CLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The processor Sleep
mode is entered by disabling CPU_CLK, which is automatically re-enabled by any enabled interrupt, or by the reset
of the product.
When processor Sleep mode is entered, the current instruction is finished before the CPU_CLK is stopped, but this
does not prevent data transfers from other masters of the system bus.
The clock selection is done in PMC_CPU_CKR.CSS.
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The prescaler is configured in PMC_CPU_CKR.PRES.
The Processor Clock Controller also generates a master clock, MCK, which is a subdivision of the CPU_CLK.
Only one of CSS, PRES and MDIV fields can be modified at a time. When one of these parameters is modified, no
other modification can be performed on these fields as long as the MCKRDY status flag is low.
Any modification in CSS, PRES or MDIV fields must never lead to generate a MCK frequency that is greater than the
maximum allowed system frequency. When changing the source clock of the system to a faster clock, the fields must
be modified using the following order: MDIV, PRES and then CSS. When changing the source clock of the system to
a slower clock, the fields must be modified using the following order: CSS, PRES and then MDIV.
If the destination clock does not exist, the switching is not performed. The CPU_CLK keeps running with the previous
clock and the system must be reset to run correctly again.
29.5
USB Clock Controller
The user can select the PLLA, the UPLL or the main Crystal Oscillator output as the USB source clock by writing the
PMC_USB.USBS field. If using the USB, the user must program the PLL to generate an appropriate frequency
depending on the PMC_USB.USBDIV field.
When the PLL output is stable, i.e., the LOCK bit is set, the USB device and host clocks can be enabled by setting
the UHP bits in the System Clock Enable register (PMC_SCER). To save power on this peripheral when it is not
used, the user can set the UHP bits in the System Clock Disable register (PMC_SCDR). The UHP bits in the System
Clock Status register (PMC_SCSR) gives the activity of this clock. The USB device and host ports requires both the
48 MHz signal and the peripheral clock. The USB peripheral clock may be controlled by means of the Peripheral
Clock Controller.
29.6
Free-running Processor Clock
The free-running Processor clock (FCLK) used for sampling interrupts and clocking debug blocks ensures that
interrupts can be sampled, and sleep events can be traced, while the processor is sleeping.
29.7
Peripheral and Generic Clock Controller
The PMC controls the clocks of the embedded peripherals by means of the Peripheral Control register (PMC_PCR).
With this register, the user can enable and disable the different clocks used by the peripherals:
•
•
Peripheral clocks (periph_clk[PID]), routed to every peripheral and derived from MCK. It is mandatory to enable
this clock before using a peripheral.
Generic clocks (GCLK[PID]), routed to selected peripherals only (refer to the Peripheral Identifiers table in
section Peripherals). These clocks are independent of the core and bus clocks (CPU_CLK, MCK and
periph_clk[PID]). They are generated by selection and division of available sources. The list of available source
clocks depends on the peripheral. Refer to the description of each peripheral to know available sources and
limitations to be applied to GCLK[PID] compared to periph_clk[PID].
To configure a peripheral’s clocks, PMC_PCR.CMD must be written to ‘1’ and PMC_PCR.PID must be written with
the index of the corresponding peripheral. All other configuration fields must be correctly set.
To read the current clock configuration of a peripheral, PMC_PCR must be first accessed with PMC_PCR.CMD bit
written to ‘0’ and PMC_PCR.PID field written with the index of the corresponding peripheral. This write does not
modify the configuration of the peripheral. The PMC_PCR can then be read to know the configuration status of the
corresponding PID.
The status of the peripheral clock activity can be read in the Peripheral Clock Status registers (PMC_CSRx).
The status of the peripheral generic clock activity can be read in the Generic Clock Status registers (PMC_GCSRx).
When a peripheral or a generic clock is disabled, it is immediately stopped. These clocks are disabled after a reset.
The source and the division ratio of generic clocks must not be modified while the peripheral is enabled. The generic
clock configuration must be set before the peripheral is enabled.
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SAM9X60
Power Management Controller (PMC)
To stop a peripheral clock, it is recommended that the system software wait until the peripheral has executed its last
programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the
system.
29.8
Programmable Clock Output Controller
The PMC controls two signals to be output on the external pins PCKx. Each signal can be independently
programmed via the Programmable Clock registers (PMC_PCKx).
PCKx can be independently selected between MD_SLCK, TD_SLCK, MAINCK, MCK and any PLLCK by configuring
PMC_PCKx.CSS. Each output signal can also be divided by 1 to 256 by configuring PMC_PCKx.PRES.
Each output signal can be enabled and disabled by writing a ‘1’ to the corresponding bits PMC_SCER.PCKx and
PMC_SCDR.PCKx, respectively. The status of the active programmable output clocks is given in PMC_SCSR.PCKx.
The status flag PMC_SR.PCKRDYx indicates that the clock configured through the PMC_PCKx register is correctly
established.
As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly
recommended to disable PCKx before any configuration change and to re-enable it once the change is performed.
29.9
Ultra-Low Power Mode and Fast Startup
The following sections give a brief description of the Ultra-Low Power mode features of the device as seen from the
PMC. A more detailed description, including power consumption and wake-up time figures, can be found in the
section “Electrical Characteristics”.
29.9.1
ULP Mode 1
When the system is in Ultra-Low Power (ULP) mode 1, all clocks of the system except MD_SLCK are stopped. The
source clock of all MCKx must be set to the main clock, and the source of the main clock must be set to main RC
oscillator.
Prior to instructing the device to enter ULP mode 1:
1.
2.
3.
4.
5.
6.
Select main RC as the source of MAINCK by configuring CKGR_MOR.MOSCSEL to ‘0’.
Select MAINCK as the source of MCK by configuring PMC_CPU_CKR.CSS to ‘1’.
Disable the PLL if enabled and disable the main crystal oscillator by setting CKGR_MOR.MOSCXTEN to ‘0’.
Wait for two SLCK clock cycles.
Clear the internal wakeup sources.
Verify that none of the enabled external wakeup inputs (WKUP) hold an active polarity.
The system enters ULP mode 1 by setting CKGR_MOR.ULP1. The PMC registers must not be accessed
immediately after this access.
29.9.2
Fast Startup
At exit from ULP mode 1, the device allows the processor to restart in several microseconds only if the C-code
function that manages the ULP mode 1 entry and exit is linked to and executed from on-chip SRAM.
A fast startup occurs upon the detection of a programmed level on one of the wakeup inputs (WKUP) or upon an
active alarm from the RTC, RTT and USB Controller. The polarity of each of the wakeup inputs is programmable in
the PMC Wakeup Control Register (PMC_WCR).
WARNING
The duration of the WKUPx pins active level must be greater than four MAINCK cycles.
The fast startup circuitry, as shown in the following figure, is fully asynchronous and provides a fast startup signal to
the PMC. As soon as the fast startup signal is asserted, the main RC oscillator restarts automatically.
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Figure 29-2. Fast Startup Circuitry
FSTT0
WKUP0
FSTP0
FSTTx
WKUPx
FSTPx
fast_restart
RTTAL
RTT Alarm
RTCAL
RTC Alarm
USBAL
USBHS Interrupt Line
Each wakeup input pin can be configured to generate a fast startup event by setting the corresponding bits in
PMC_WCR.
To configure a wakeup pin, a write access must be performed in PMC_WCR (CMD=’1’). Field PID must be written
with the ID of the wakeup pin, FSTP set to the polarity of the wakeup pin and EN set to enable/disable the wakeup
pin.
To read the configuration status of a wakeup pin, PMC_WCR.PID must be written with the ID of the wakeup pin and
the CMD bit set to ‘0’. Then the next read access to PMC_WCR sends the configuration status of the wakeup pin
specified in PID.
Each alarm can be enabled to generate a fast startup event by setting the corresponding bit in PMC_FSMR.
The user interface does not provide any status for fast startup. The status can be read in the PIO Controller and the
status registers of the RTC, RTT and USB Controller.
29.10
Main Crystal Oscillator Failure Detection
The main crystal oscillator failure detector monitors the main crystal oscillator against the slow RC oscillator and
provides an automatic switchover of the MAINCK source to the main RC oscillator in case of failure detection.
The failure detector can be enabled or disabled by configuring CKGR_MOR.CFDEN. It cannot be enabled if the main
crystal oscillator is disabled. It must be disabled before disabling the main crystal oscillator.
It is also disabled in either of the following cases:
•
•
after a VDDCORE reset
when the main crystal oscillator is disabled (MOSCXTEN = 0)
A failure is detected by means of a counter incrementing on the main crystal oscillator output and detection logic is
triggered by the slow RC oscillator which is automatically enabled when CFDEN = 1.
The counter is cleared when the slow RC oscillator clock signal is low and enabled when the signal is high. Thus, the
failure detection time is one slow RC oscillator period. If, during the high level period of the slow RC oscillator clock
signal, less than eight main crystal oscillator clock periods have been counted, then a failure is reported. Note that
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Power Management Controller (PMC)
when enabling the failure detector, up to two cycles of the slow RC oscillator are needed to detect a failure of the
main crystal oscillator.
If a main crystal oscillator failure is detected, PMC_SR.CFDEV and PMC_SR.FOS both indicate a failure event.
PMC_SR.CFDEV is cleared on read of PMC_SR, and PMC_SR.FOS is cleared by writing a ‘1’ to the FOCLR bit in
the PMC Fault Output Clear register (PMC_FOCR).
Only PMC_SR.CFDEV can generate an interrupt if the corresponding interrupt source is enabled in PMC_IER. The
current status of the clock failure detection can be read at any time from PMC_SR.CFDS.
Figure 29-3. Clock Failure Detection Example
Main Crystal Oscillator Output
Slow
Clock
Read PMC_SR
CFDEV
CFDS
Note: Ratio of clock periods is for illustration purposes only.
If the CKGR_MOR.AUTOMAINSW bit is set to'1', the source of MAINCK automatically switches to the MAIN RC
oscillator. If the main RC oscillator was previously powered off, it is first powered on before switching. If the
CKGR_MOR.AUTOCPUSW bit is set to'1', the source of MCK automatically switches to MAINCK.
If the main crystal oscillator is selected as the source of MAINCK, the PMC can be configured to automatically select
the main RC oscillator as the source of MAINCK in case of a main crystal oscillator failure detection by setting the
CKGR_MOR.AUTOMAINSW to '1'. Additionally, if the source of CPU_CLK is a PLL driven by the main crystal
oscillator, the PMC can be configured to automatically select the MAINCK as the source of CPU_CLK in case of a
main crystal oscillator failure detection by setting the CKGR_MOR.AUTOCPUSW to '1'. CKGR_MOR.AUTOMAINSW
must be set to '1' prior to setting CKGR_MOR.AUTOCPUSW to '1'.
Two slow RC oscillator clock cycles are necessary to detect and switch from the main crystal oscillator to the main
RC oscillator if the source of MCK is MAINCK, or three slow RC oscillator clock cycles if the source of MCK is a PLL.
29.11
32.768 kHz Crystal Oscillator Frequency Monitor
The frequency of the 32.768 kHz crystal oscillator can be monitored by configuring CKGR_MOR.XT32KFME. Prior to
enabling the monitoring, the 32.768 kHz crystal oscillator must be started and its startup time be elapsed. Refer to the
section “Slow Clock Controller (SCKC)” for details on the slow clock generator.
An error flag (PMC_SR.XT32KERR) is asserted when the 32.768 kHz crystal oscillator frequency is out of its nominal
frequency value (i.e., 32.768 kHz). The error flag can be cleared only if the monitoring is disabled.
The frequency drift is computed with the main RC oscillator. The permitted drift of the crystal is 10000 ppm (1%),
which allows any standard crystal to be used.
The monitored clock frequency is declared invalid if at least four consecutive 32.768 kHz crystal oscillator clock
period measurement results are over the nominal period. Note that modifying the trimming values of the main RC
oscillator (PMC_OCR) may impact the monitor accuracy and lead to inappropriate failure detection.
The error flag can be defined as an interrupt source of the PMC by setting PMC_IER.XT32KERR. This flag is also
routed to the Reset Controller (RSTC) and may generate a reset of the device.
29.12
MCK Frequency Monitor
The frequency of MCK can be monitored with the main RC oscillator. This monitoring can only be performed if the
MCK frequency is at least three times faster than the embedded main RC oscillator. This function is enabled by
writing a ‘1’ to PMC_IER.MCKMON.
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Power Management Controller (PMC)
An error on the MCK frequency can lead to a PMC interrupt.
When the corresponding PMC interrupt is enabled, the status of the MCK monitoring can be read on
PMC_SR.MCKMON. This status is cleared on read.
Once enabled, the monitor continuously counts the number of MCK cycles within 15 cycles of the embedded main
RC oscillator. The result is then compared to threshold values defined in the PMC_MCKLIM register. Two levels of
threshold can be defined to generate a reset of the system.
Figure 29-4. MCK Frequency Monitor
MCK Monitor Limits
(PMC_MCKLIM)
PMC_IER.MCKMON
Main RC Oscillator
MCK
29.13
Counter
MCK_LOW_INT
< counter <
MCK_HIGH_INT
To PMC interrupt line
Recommended Programming Sequence
Follow the steps below to program the PMC:
1.
If the main crystal oscillator is not required, the PLL can be directly configured (step 5) else this oscillator must
be started (step 2).
2. Verify the existence and frequency value of the main crystal oscillator following the sequence defined in
28.5.6 Main Frequency Counter
3. If the main crystal oscillator is enabled and valid, the source of MAINCK can be switched to the main crystal
oscillator by writing CKGR_MOR.MOSCSEL to 1 else the PLL can be directly configured.
4. Wait for the end of the MAINCK source switching by either polling the MOSCSELS or setting the
corresponding interrupt
5. Configure the PLLs by following the setup defined in 28.6.1 Divider and Phase Lock Loop Programming (if not
required, proceed to step 6):
6. Configure the MCK division ratio by setting PMC_CPU_CKR.MDIV. Available values are 0, 1, 2, 3. MCK output
is the CPU_CLK frequency divided by 1, 2, 3 or 4, depending on the value programmed in MDIV.
By default, MDIV is cleared, which indicates that the CPU_CLK is equal to MCK.
7. Wait for the end of the MCK ratio switching by either polling the MCKRDY or setting the corresponding
interrupt.
8. Select the division ratio of CPU_CLK by setting PMC_CPU_CKR.PRES.
PRES is used to define the CPU_CLK and MCK prescaler. The user can choose between different values (1,
2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value.
9. Wait for the end of the CPU_CLK ratio switching by either polling the MCKRDY or setting the corresponding
interrupt.
10. Select the source clock of CPU_CLK by setting PMC_CPU_CKR.CSS.
CSS is used to select the clock source of MCK and CPU_CLK. By default, the selected clock source is
MAINCK.
11. Wait for the end of the CPU_CLK source switching by either polling the MCKRDY or setting the corresponding
interrupt.
PMC_CPU_CKR must not be programmed in a single write operation.
Reconfiguring MDIV, PRES and CSS fields must always be done by following the right order of operation
described above (steps 6 to 11).
12. Configure the programmable clocks (PCKx):
PCKx are controlled via registers PMC_SCER, PMC_SCDR and PMC_SCSR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 371
SAM9X60
Power Management Controller (PMC)
PCKx can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Two PCKx can be used.
PMC_SCSR indicates which PCKx is enabled. By default all PCKx are disabled.
PMC_PCKx registers are used to configure PCKx as described in 29.8 Programmable Clock Output
Controller.
13. Enable the peripheral and generic clocks.
Once all of the previous steps have been completed, the peripheral and generic clocks can be configured via
register PMC_PCR as described in 29.7 Peripheral and Generic Clock Controller.
29.14
Clock Switching Details
29.14.1 CPU Clock Switching Timings
The glitch-free clock switcher implemented to control the sources of CPU_CLK and MCK performs clock switching in
5 clock cycles of the currently used clock plus 5 cycles of the target clock.
The clock switching is effective once MCKRDY rises. See the following figure.
Figure 29-5. Switch CPU Clock (CPU_CLK) from Source Clock to Destination Clock
Source
clock
Destination
clock
Clock
selection
source
destination
MCKRDY
CPU_CLK
5 source clock cycles
29.15
4 to 5 destination clock
cycles
Register Write Protection
To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit or the WPITEN bit in the PMC Write Protection Mode Register
(PMC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the PMC Write Protection Status Register
(PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the PMC_WPSR.
The following registers are write-protected when the WPEN bit is set in PMC_WPMR:
•
•
•
•
•
•
•
PMC System Clock Enable Register
PMC System Clock Disable Register
PMC PLL Control Register 0
PMC PLL Control Register 1
PMC PLL Spread Spectrum Register
PMC PLL Analog Control Register
PMC PLL Update Register
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 372
SAM9X60
Power Management Controller (PMC)
•
•
•
•
•
•
•
•
•
•
PMC Clock Generator Main Oscillator Register
PMC Clock Generator Main Clock Frequency Register
PMC CPU Clock Register
PMC_USB
PMC Programmable Clock Register
PMC Fast Startup Mode Register
PMC Wakeup Control Register
PMC Peripheral Control Register
PMC Oscillator Calibration Register
PMC MCK0 Monitor Limits Register
The following interrupt registers are write-protected when the WPITEN bit is set in PMC_WPMR:
•
•
•
•
PMC Interrupt Enable Register
PMC Interrupt Disable Register
PMC PLL Interrupt Enable Register
PMC PLL Interrupt Disable Register
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 373
SAM9X60
Power Management Controller (PMC)
29.16
Register Summary
Offset
Name
0x00
PMC_SCER
0x04
0x08
0x0C
PMC_SCDR
PMC_SCSR
PMC_PLL_CTRL0
0x10
PMC_PLL_CTRL1
0x14
PMC_PLL_SSR
0x18
PMC_PLL_ACR
0x1C
PMC_PLL_UPDT
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
CKGR_MOR
0x24
CKGR_MCFR
0x28
PMC_CPU_CKR
0x2C
...
0x37
0x38
0x3C
...
0x3F
5
4
3
2
1
0
PCK1
PCK0
PCK1
PCK0
PCK1
PCK0
QSPICLK
UHP
DDRCK
QSPICLK
UHP
DDRCK
QSPICLK
UHP
ENLOCK
31:24
0x20
6
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
DDRCK
ENPLLCK
ENPLL
DIVPMC[7:0]
MUL[7:0]
FRACR[21:16]
FRACR[15:8]
FRACR[7:0]
ENSPREAD
NSTEP[7:0]
STEP[15:8]
STEP[7:0]
LOOP_FILTER[5:0]
UTMIBG
UTMIVR
CONTROL[7:0]
LOCK_THR[2:0]
CONTROL[11:8]
STUPTIM[7:0]
UPDATE
ID
AUTOCPUSW
AUTOMAINS
W
XT32KFME
KEY[7:0]
MOSCXTST[7:0]
MOSCRCEN
CFDEN
ULP1
MOSCXTEN
CCSS
MAINFRDY
RCMEAS
MAINF[15:8]
MAINF[7:0]
PRES[2:0]
MOSCSEL
MDIV[2:0]
CSS[1:0]
Reserved
PMC_USB
31:24
23:16
15:8
7:0
USBDIV[3:0]
USBS[1:0]
Reserved
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Power Management Controller (PMC)
...........continued
Offset
Name
0x40
PMC_PCK0
0x44
0x48
...
0x5F
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
...
0x7F
0x80
0x84
0x88
0x8C
PMC_PCK1
Bit Pos.
7
6
5
4
3
2
1
0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
PRES[7:0]
CSS[4:0]
PRES[7:0]
CSS[4:0]
Reserved
PMC_IER
PMC_IDR
PMC_SR
PMC_IMR
PMC_FSMR
PMC_WCR
PMC_FOCR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
MCKMON
XT32KERR
CFDEV
PLL_INT
MOSCRCS
PCKRDY1
CFDEV
PLL_INT
MOSCRCS
PCKRDY1
CFDEV
PLL_INT
MOSCRCS
PCKRDY1
CFDEV
PLL_INT
MOSCRCS
PCKRDY1
MCKRDY
MCKMON
XT32KERR
MCKRDY
MCKMON
XT32KERR
FOS
CFDS
MCKRDY
MCKMON
XT32KERR
MOSCSELS
PCKRDY0
MOSCXTS
GCLKRDY
MOSCSELS
PCKRDY0
MOSCXTS
WLAN1
RTCAL
MOSCSELS
PCKRDY0
MOSCXTS
WLAN0
RTTAL
WIP
CMD
EN
MCKRDY
USBAL
MOSCSELS
PCKRDY0
MOSCXTS
WKPIONB[3:0]
FOCLR
Reserved
PMC_WPMR
PMC_WPSR
PMC_PCR
PMC_OCR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WPITEN
WPEN
WPVSRC[15:8]
WPVSRC[7:0]
WPVS
CMD
GCLKEN
GCLKDIV[3:0]
EN
GCLKDIV[7:4]
GCLKCSS[4:0]
PID[6:0]
SEL12
© 2020 Microchip Technology Inc.
CAL12[6:0]
Complete Datasheet
DS60001579C-page 375
SAM9X60
Power Management Controller (PMC)
...........continued
Offset
Name
0x90
...
0x9B
Reserved
0x9C
PMC_MCKLIM
0xA0
PMC_CSR0
0xA4
PMC_CSR1
0xA8
...
0xBF
PMC_GCSR0
0xC4
PMC_GCSR1
0xE0
0xE4
0xE8
0xEC
0xF0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
PID23
PID15
PID7
PID47
PID39
6
PID30
PID22
PID14
PID6
PID38
5
2
1
0
PID13
PID5
MCK_HIGH_IT[7:0]
MCK_LOW_IT[7:0]
PID28
PID27
PID20
PID19
PID12
PID11
PID4
PID3
PID26
PID18
PID10
PID2
PID25
PID17
PID9
PID24
PID16
PID8
PID45
PID37
PID44
PID36
PID43
PID35
PID42
PID34
PID49
PID41
PID33
PID40
PID32
GPID12
GPID19
GPID11
GPID10
GPID25
GPID17
GPID9
GPID16
GPID8
GPID42
GPID34
GPID33
GPID32
UNLOCKU
UNLOCKA
LOCKU
LOCKA
UNLOCKU
UNLOCKA
LOCKU
LOCKA
UNLOCKU
UNLOCKA
LOCKU
LOCKA
UNLOCKU
UNLOCKA
LOCKU
LOCKA
OVRU
OVRA
UDRU
UDRA
PID29
4
3
Reserved
0xC0
0xC8
...
0xDF
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
GPID26
GPID15
GPID7
GPID47
GPID14
GPID6
GPID13
GPID5
GPID45
GPID37
Reserved
PMC_PLL_IER
PMC_PLL_IDR
PMC_PLL_IMR
PMC_PLL_ISR0
PMC_PLL_ISR1
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 376
SAM9X60
Power Management Controller (PMC)
29.16.1 PMC System Clock Enable Register
Name:
Offset:
Reset:
Property:
PMC_SCER
0x0000
–
Write-only
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
QSPICLK
W
–
18
17
16
15
14
13
12
11
10
9
PCK1
W
–
8
PCK0
W
–
7
6
UHP
W
–
5
4
3
2
DDRCK
W
–
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 19 – QSPICLK QSPI 2x Clock Enable
Value
Description
0
No effect.
1
Enables the QSPI 2x clock.
Bits 8, 9 – PCKx Programmable Clock x Output Enable
Value
Description
0
No effect.
1
Enables the corresponding Programmable Clock output.
Bit 6 – UHP USB Host OHCI Clocks Enable
Value
Description
0
No effect.
1
Enables the UHP48M and UHP12M OHCI clocks.
Bit 2 – DDRCK MPDDRC/SDRAMC Clock Enable
Value
Description
0
No effect.
1
Enables the MPDDRC or SDRAMC clock.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 377
SAM9X60
Power Management Controller (PMC)
29.16.2 PMC System Clock Disable Register
Name:
Offset:
Reset:
Property:
PMC_SCDR
0x0004
–
Write-only
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
QSPICLK
W
–
18
17
16
15
14
13
12
11
10
9
PCK1
W
–
8
PCK0
W
–
7
6
UHP
W
–
5
4
3
2
DDRCK
W
–
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 19 – QSPICLK QSPI 2x Clock Disable
Value
Description
0
No effect.
1
Disables the QSPI 2x clock.
Bits 8, 9 – PCKx Programmable Clock x Output Disable
Value
Description
0
No effect.
1
Disables the corresponding Programmable Clock output.
Bit 6 – UHP USB Host OHCI Clocks Disable
Value
Description
0
No effect.
1
Disables the UHP48M and UHP12M OHCI clocks.
Bit 2 – DDRCK MPDDRC/SDRAMC Clock Disable
Value
Description
0
No effect.
1
Disables the MPDDRC or SDRAMC clock.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 378
SAM9X60
Power Management Controller (PMC)
29.16.3 PMC System Clock Status Register
Name:
Offset:
Reset:
Property:
Bit
PMC_SCSR
0x0008
0x00000001
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
QSPICLK
R
0
18
17
16
15
14
13
12
11
10
9
PCK1
R
0
8
PCK0
R
0
7
6
UHP
R
0
5
4
3
2
DDRCK
R
0
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 19 – QSPICLK QSPI 2x Clock Status
Value
Description
0
The QSPI 2x clock is disabled.
1
The QSPI 2x clock is enabled.
Bits 8, 9 – PCKx Programmable Clock x Output Status
Value
Description
0
The corresponding Programmable Clock output is disabled.
1
The corresponding Programmable Clock output is enabled.
Bit 6 – UHP USB Host OHCI Clocks Status
Value
Description
0
The UHP48M and UHP12M OHCI clocks are disabled.
1
The UHP48M and UHP12M OHCI clocks are enabled.
Bit 2 – DDRCK MPDDRC/SDRAMC Clock Status
Value
Description
0
The MPDDRC or SDRAMC clock is disabled.
1
The MPDDRC or SDRAMC clock is enabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 379
SAM9X60
Power Management Controller (PMC)
29.16.4 PMC PLL Control Register 0
Name:
Offset:
Reset:
Property:
PMC_PLL_CTRL0
0x000C
0x00000000
Read/Write
All fields defined here are applied to the PLL defined by the last ID field written in the PMC_PLL_UPDT register.
Bit
Access
Reset
Bit
31
ENLOCK
R/W
0
30
29
ENPLLCK
R/W
0
28
ENPLL
R/W
0
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
3
DIVPMC[7:0]
R/W
R/W
0
0
Bit 31 – ENLOCK Enable PLL Lock
Value
Description
0
The lock signal sent by the PLL is ignored. The PLL is considered as locked once the startup time
defined by PMC_PLL_UPDT.STUPTIM has elapsed.
1
The PLL is considered as locked once the startup time defined by PMC_PLL_UPDT.STUPTIM has
elapsed and the lock signal sent by the PLL has risen.
Bit 29 – ENPLLCK Enable PLL Clock for PMC
Value
Description
0
The clock generated by the PLL is not send to the PMC.
1
The clock generated by the PLL is sent to the PMC.
Bit 28 – ENPLL Enable PLL
Value
Description
0
The PLL is off.
1
The PLL is on.
Bits 7:0 – DIVPMC[7:0] Divider for PMC
Specifies the division ratio applied to the internal PLL clock before being sent to the PMC. The frequency is defined
by the following formula:
�COREPLLCK
�PLL Clock =
DIVPMC + 1
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 380
SAM9X60
Power Management Controller (PMC)
29.16.5 PMC PLL Control Register 1
Name:
Offset:
Reset:
Property:
PMC_PLL_CTRL1
0x0010
0x00000000
Read/Write
All fields defined here are applied to the PLL defined by the last ID field written in the PMC_PLL_UPDT register.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
17
16
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
MUL[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
R/W
0
R/W
0
12
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
19
18
FRACR[21:16]
R/W
R/W
0
0
11
FRACR[15:8]
R/W
R/W
0
0
4
3
FRACR[7:0]
R/W
R/W
0
0
Bits 31:24 – MUL[7:0] Multiplier Factor Value
Configures the internal clock frequency. See Divider and Phase Lock Loop Programming.
Bits 21:0 – FRACR[21:0] Fractional Loop Divider Setting
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 381
SAM9X60
Power Management Controller (PMC)
29.16.6 PMC PLL Spread Spectrum Register
Name:
Offset:
Reset:
Property:
PMC_PLL_SSR
0x0014
0x00000000
Read/Write
All fields defined here are applied to the PLL defined by the last ID field written in the PMC_PLL_UPDT register.
Bit
31
30
29
28
ENSPREAD
R/W
0
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
NSTEP[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
STEP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
STEP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 28 – ENSPREAD Spread Spectrum Enable
Value
Description
0
The spread spectrum is not applied to the PLL.
1
The spread spectrum is applied to the PLL.
Bits 23:16 – NSTEP[7:0] Spread Spectrum Number of Steps
Specifies how many times STEP is applied to the PLL ratio. The value of NSTEP must be equal to or greater than 1.
Bits 15:0 – STEP[15:0] Spread Spectrum Step Size
When the spread spectrum is active, this field defines the step size that will be applied the
PMC_PLL_CTRL1.FRACR factor. The step is applied on the LSB of PMC_PLL_CTRL1.FRACR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 382
SAM9X60
Power Management Controller (PMC)
29.16.7 PMC PLL Analog Control Register
Name:
Offset:
Reset:
Property:
PMC_PLL_ACR
0x0018
0x00020033
Read/Write
All fields defined here are applied to the PLL defined by the last ID field written in the PMC_PLL_UPDT register.
Bit
31
30
Access
Reset
Bit
23
22
29
28
R/W
0
R/W
0
21
20
27
26
LOOP_FILTER[5:0]
R/W
R/W
0
0
19
Access
Reset
R/W
0
Bit
15
14
Access
Reset
Bit
Access
Reset
18
13
UTMIBG
R/W
0
7
6
5
R/W
0
R/W
0
R/W
1
12
UTMIVR
R/W
0
11
R/W
0
4
3
CONTROL[7:0]
R/W
R/W
1
0
25
24
R/W
0
R/W
0
17
LOCK_THR[2:0]
R/W
1
16
10
9
CONTROL[11:8]
R/W
R/W
0
0
R/W
0
8
R/W
0
2
1
0
R/W
0
R/W
1
R/W
1
Bits 29:24 – LOOP_FILTER[5:0] LOOP Filter Selection
Recommended value for this field = 0x1B.
Bits 18:16 – LOCK_THR[2:0] PLL Lock Threshold Value Selection
Recommended value for this field = 0x4
Bit 13 – UTMIBG UPLL Bandgap Control
This bit has no effect when applied to PLLA.
Value
Description
0
The UPLL bandgap is switched off.
1
The UPLL bandgap is switched on.
Bit 12 – UTMIVR UPLL Voltage Regulator Control
This bit has no effect when applied to PLLA.
Value
Description
0
The UPLL voltage regulator is switched off.
1
The UPLL voltage regulator is switched on.
Bits 11:0 – CONTROL[11:0] PLL CONTROL Value Selection
Recommended value for this field = 0x010.
On PLLA, this field controls the DCO analog filters:
Field
Description
CONTROL[1:0]
CONTROL[4:2]
CONTROL[6:5]
CONTROL[7]
CONTROL[8]
Analog VCO Filter Selection
Process Configuration
VCO Gain Configuration
Offset Frequency Adjustment
External Pad Connection
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 383
SAM9X60
Power Management Controller (PMC)
...........continued
Field
Description
CONTROL[9]
CONTROL[10]
CONTROL[11]
Test Mode dedicated
DAC Mode
Enable Output Phases
On UPLL, this field controls the following PLL ports:
Field
Description
CONTROL[1:0]
CONTROL[4:2]
CONTROL[6:5]
CONTROL[7]
CONTROL[11:8]
Not used
Process Configuration
VCO Gain Configuration
Offset Frequency Adjustment
Not used
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 384
SAM9X60
Power Management Controller (PMC)
29.16.8 PMC PLL Update Register
Name:
Offset:
Reset:
Property:
Bit
PMC_PLL_UPDT
0x001C
0x00030000
Read/Write
31
30
29
28
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
12
7
6
5
4
27
26
25
24
18
17
16
R/W
0
R/W
1
R/W
1
11
10
9
8
UPDATE
R/W
0
3
2
1
0
ID
R/W
0
Access
Reset
Bit
Access
Reset
Bit
20
19
STUPTIM[7:0]
R/W
R/W
0
0
Access
Reset
Bit
Access
Reset
Bits 23:16 – STUPTIM[7:0] Startup Time
0: Only the lock of the PLL is considered to know the lock status of the PLL. If the lock of the PLL is not enabled, the
lock never rises.
Other values: If PMC_PLL_CTRL0.ENLOCK is low, specifies the startup time of the PLL. If
PMC_PLL_CTRL0.ENLOCK is high, specifies how long the LOCK signal of the PLL is masked before being read.
The startup time is defined as a number of MD_SLCK cycles and is the same for all PLLs.
Bit 8 – UPDATE PLL Setting Update (write-only)
Value
Description
0
No effect.
1
The PLL configuration written in PMC_PLL_CTRL0 and PMC_PLL_CTRL1 are applied to the PLL
defined by the last ID written in the PMC_PLL_CTRL0 register.
Bit 0 – ID PLL ID
When writing a PLL control register (PMC_PLL_CTRLx), this ID specifies which PLL is impacted by written fields.
When reading a PLL control register (PMC_PLL_CTRLx), this ID specifies which PLL fields are read.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 385
SAM9X60
Power Management Controller (PMC)
29.16.9 PMC Clock Generator Main Oscillator Register
Name:
Offset:
Reset:
Property:
CKGR_MOR
0x0020
0x00000008
Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Note: Bit 5 is always read at 1.
Bit
31
Access
Reset
Bit
23
30
29
AUTOCPUSW AUTOMAINSW
R/W
R/W
0
0
22
21
28
20
27
26
XT32KFME
R/W
0
25
CFDEN
R/W
0
24
MOSCSEL
R/W
0
19
18
17
16
W
0
W
0
W
0
W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
ULP1
W
0
1
0
MOSCXTEN
R/W
0
KEY[7:0]
Access
Reset
W
0
W
0
W
0
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
Access
Reset
Bit
W
0
12
11
MOSCXTST[7:0]
R/W
R/W
0
0
4
Access
Reset
3
MOSCRCEN
R/W
1
Bit 30 – AUTOCPUSW Automatic Processor Clock Source Switching
Value
Description
0
A main crystal oscillator failure detection has no effect on the processor clock source selection.
1
If a main crystal oscillator failure is detected, the processor clock source selection automatically
switches to the main clock.
Bit 29 – AUTOMAINSW Automatic Main Clock Source Switching
Value
Description
0
A main crystal oscillator failure detection has no effect on the main clock source selection.
1
If a main crystal oscillator failure is detected, the main clock source selection automatically switches to
the main RC.
Bit 26 – XT32KFME 32.768 kHz Crystal Oscillator Frequency Monitoring Enable
Value
Description
0
The 32.768 kHz crystal oscillator frequency monitoring is disabled.
1
The 32.768 kHz crystal oscillator frequency monitoring is enabled.
Bit 25 – CFDEN Clock Failure Detector Enable
Value
Description
0
The clock failure detector is disabled.
1
The clock failure detector is enabled.
Bit 24 – MOSCSEL Main Clock Oscillator Selection
Value
Description
0
The main RC oscillator is selected.
1
The main crystal oscillator is selected.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 386
SAM9X60
Power Management Controller (PMC)
Bits 23:16 – KEY[7:0] Write Access Password
Value
Name
Description
0x37
PASSWD
Writing any other value in this field aborts the write operation.
Always reads as 0.
Bits 15:8 – MOSCXTST[7:0] Main Crystal Oscillator Startup Time
Specifies the number of MD_SLCK cycles multiplied by 8 for the main crystal oscillator startup time.
Bit 3 – MOSCRCEN Main RC Oscillator Enable
When MOSCRCEN is set, the MOSCRCS flag is set once the main RC oscillator startup time is achieved.
Value
Description
0
The main RC oscillator is disabled.
1
The main RC oscillator is enabled.
Bit 2 – ULP1 ULP Mode 1 Command
Value
Description
0
No effect.
1
Puts the device in ULP mode 1.
Bit 0 – MOSCXTEN Main Crystal Oscillator Enable
A crystal must be connected between XIN and XOUT or a clock signal must be provided on XIN with XOUT
grounded.
When MOSCXTEN is set, the MOSCXTS flag is set once the main crystal oscillator startup time is achieved.
Value
Description
0
The main crystal oscillator is disabled.
1
The main crystal oscillator is enabled or in bypass.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 387
SAM9X60
Power Management Controller (PMC)
29.16.10 PMC Clock Generator Main Clock Frequency Register
Name:
Offset:
Reset:
Property:
CKGR_MCFR
0x0024
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
CCSS
R/W
0
23
22
21
20
RCMEAS
R/W
0
19
18
17
16
MAINFRDY
R/W
0
15
14
13
12
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
11
MAINF[15:8]
R/W
R/W
0
0
4
MAINF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 24 – CCSS Counter Clock Source Selection
Value
Description
0
The measured clock of the MAINF counter is the main RC oscillator.
1
The measured clock of the MAINF counter is the main crystal oscillator.
Bit 20 – RCMEAS RC Oscillator Frequency Measure (write-only)
The measurement is performed on the main frequency (i.e., not limited to the main RC oscillator only). If the source
of MAINCK is the main crystal oscillator, the restart of measurement may not be required because of the stability of
crystal oscillators.
Value
Description
0
No effect.
1
Restarts measuring of the frequency of MAINCK. MAINF carries the new frequency as soon as a lowto-high transition occurs on the MAINFRDY flag.
Bit 16 – MAINFRDY Main Clock Frequency Measure Ready
To ensure that a correct value is read on the MAINF field, the MAINFRDY flag must be read at ‘1’ then another read
access must be performed on the register to get a stable value on the MAINF field.
Value
Description
0
MAINF value is not valid or the measured oscillator is disabled or a measure has just been started by
means of RCMEAS.
1
The measured oscillator has been enabled previously and MAINF value is available.
Bits 15:0 – MAINF[15:0] Main Clock Frequency
Gives the number of cycles of the clock selected by the bit CCSS within 16 MD_SLCK periods. To calculate the
frequency of the measured clock:
fSELCLK = (MAINF x fMD_SLCK)/16
where frequency is in MHz.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 388
SAM9X60
Power Management Controller (PMC)
29.16.11 PMC CPU Clock Register
Name:
Offset:
Reset:
Property:
PMC_CPU_CKR
0x0028
0x00000001
Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
The CSS, PRES and MDIV fields cannot be modified simultaneously. If more than one field modification is required,
proceed sequentially: modify the first field and wait for PMC_SR.MCKRDY low, then modify the second field and wait
for PMC_SR.MCKRDY low, etc.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
8
R/W
0
9
MDIV[2:0]
R/W
0
R/W
0
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
R/W
0
5
PRES[2:0]
R/W
0
4
3
CSS[1:0]
R/W
0
R/W
0
R/W
1
Bits 10:8 – MDIV[2:0] MCK Division
Value
Name
Description
0
EQ_PCK
MCK is FCLK divided by 1. MCK_2X is FCLK divided by 1.
1
PCK_DIV2
MCK is FCLK divided by 2. MCK_2X is FCLK divided by 1.
2
PCK_DIV4
MCK is FCLK divided by 4. MCK_2X is FCLK divided by 2.
3
PCK_DIV3
MCK is FCLK divided by 3. MCK_2X is FCLK divided by 1.5.
Bits 6:4 – PRES[2:0] Processor Clock Prescaler
Value
Name
Description
0
CLK_1
Selected clock
1
CLK_2
Selected clock divided by 2
2
CLK_4
Selected clock divided by 4
3
CLK_8
Selected clock divided by 8
4
CLK_16
Selected clock divided by 16
5
CLK_32
Selected clock divided by 32
6
CLK_64
Selected clock divided by 64
7
CLK_3
Selected clock divided by 3
Bits 1:0 – CSS[1:0] MCK Source Selection
Value
Name
0
SLOW_CLK
1
MAIN_CLK
2
PLLACK
3
UPLLCK
© 2020 Microchip Technology Inc.
Description
MD_SLCK is selected.
MAINCK is selected.
PLLACK is selected.
UPLL is selected.
Complete Datasheet
DS60001579C-page 389
SAM9X60
Power Management Controller (PMC)
29.16.12 PMC USB Clock Register
Name:
Offset:
Reset:
Property:
PMC_USB
0x0038
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
R/W
0
7
6
5
4
3
9
USBDIV[3:0]
R/W
R/W
0
0
2
8
R/W
0
1
0
USBS[1:0]
Access
Reset
R/W
0
R/W
0
Bits 11:8 – USBDIV[3:0] Divider for USB OHCI Clock
USB Clock is Input clock divided by USBDIV + 1.
Bits 1:0 – USBS[1:0] USB OHCI/EHCI Input Clock Selection
Value
Name
Description
0
PLLA
USB Clock Input is PLLACK.
1
UPLL
USB Clock Input is UPLLCK.
2
MAINXTAL
USB Clock Input is MAINXTALCK.
3
Reserved
–
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 390
SAM9X60
Power Management Controller (PMC)
29.16.13 PMC Programmable Clock Register
Name:
Offset:
Reset:
Property:
PMC_PCKx
0x40 + x*0x04 [x=0..1]
0
Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
PRES[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
1
0
R/W
0
R/W
0
2
CSS[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bits 15:8 – PRES[7:0] Programmable Clock Prescaler
Value
Description
0–255
Selected clock is divided by PRES+1.
Bits 4:0 – CSS[4:0] Programmable Clock Source Selection
Values not listed are considered “reserved”.
Value
Name
0
MD_SLOW_CLK
1
TD_SLOW_CLOCK
2
MAINCK
3
MCK
4
PLLA
5
UPLL
© 2020 Microchip Technology Inc.
Description
MD_SLCK is selected
TD_SLCK is selected
MAINCK is selected
MCK is selected
PLLA is selected.
UPLL is selected.
Complete Datasheet
DS60001579C-page 391
SAM9X60
Power Management Controller (PMC)
29.16.14 PMC Interrupt Enable Register
Name:
Offset:
Reset:
Property:
PMC_IER
0x0060
–
Write-only
This register can only be written if the WPITEN bit is cleared in the PMC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
PLL_INT
W
–
24
23
MCKMON
W
–
22
21
XT32KERR
W
–
20
19
18
CFDEV
W
–
17
MOSCRCS
W
–
16
MOSCSELS
W
–
15
14
13
12
11
10
9
PCKRDY1
W
–
8
PCKRDY0
W
–
7
6
5
4
3
MCKRDY
W
–
2
1
0
MOSCXTS
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 25 – PLL_INT PLL Interrupt Enable
Bit 23 – MCKMON Master Clock Clock Monitor Interrupt Enable
Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Enable
Bit 18 – CFDEV Clock Failure Detector Event Interrupt Enable
Bit 17 – MOSCRCS Main RC Oscillator Status Interrupt Enable
Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Enable
Bits 8, 9 – PCKRDYx Programmable Clock Ready x Interrupt Enable
Bit 3 – MCKRDY Master Clock Ready Interrupt Enable
Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 392
SAM9X60
Power Management Controller (PMC)
29.16.15 PMC Interrupt Disable Register
Name:
Offset:
Reset:
Property:
PMC_IDR
0x0064
–
Write-only
This register can only be written if the WPITEN bit is cleared in the PMC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
PLL_INT
W
–
24
23
MCKMON
W
–
22
21
XT32KERR
W
–
20
19
18
CFDEV
W
–
17
MOSCRCS
W
–
16
MOSCSELS
W
–
15
14
13
12
11
10
9
PCKRDY1
W
–
8
PCKRDY0
W
–
7
6
5
4
3
MCKRDY
W
–
2
1
0
MOSCXTS
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 25 – PLL_INT PLL Interrupt Disable
Bit 23 – MCKMON Master Clock Clock Monitor Interrupt Disable
Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Disable
Bit 18 – CFDEV Clock Failure Detector Event Interrupt Disable
Bit 17 – MOSCRCS Main RC Status Interrupt Disable
Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Disable
Bits 8, 9 – PCKRDYx Programmable Clock Ready x Interrupt Disable
Bit 3 – MCKRDY Master Clock Ready Interrupt Disable
Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 393
SAM9X60
Power Management Controller (PMC)
29.16.16 PMC Status Register
Name:
Offset:
Reset:
Property:
Bit
PMC_SR
0x0068
0x00030008
Read-only
31
30
29
28
27
26
25
PLL_INT
R
0
24
GCLKRDY
R
0
23
MCKMON
R
0
22
21
XT32KERR
R
0
20
FOS
R
0
19
CFDS
R
0
18
CFDEV
R
0
17
MOSCRCS
R
1
16
MOSCSELS
R
1
15
14
13
12
11
10
9
PCKRDY1
R
0
8
PCKRDY0
R
0
7
6
5
4
3
MCKRDY
R
1
2
1
0
MOSCXTS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 25 – PLL_INT PLL Interrupt Status
Value
Description
0
No PLL interrupt has occurred.
1
A PLL interrupt has occurred. PLL interrupt is defined by the configuration of the PMC_IMR register.
Bit 24 – GCLKRDY GCLK Ready
Value
Description
0
A GCLK is not ready to use (clock switching in progress).
1
All GCLKs are switched to their selected source clock and ready to use.
Bit 23 – MCKMON Master Clock Clock Monitor Error
This status is cleared on read.
Value
Description
0
The Master Clock is correct or the CPU clock monitor is disabled.
1
The Master Clock is incorrect or has been incorrect for an elapsed period of time since the monitoring
has been enabled.
Bit 21 – XT32KERR Slow Crystal Oscillator Error
Value
Description
0
The frequency of the 32.768 kHz crystal oscillator is correct (32.768 kHz ±1%) or the monitoring is
disabled.
1
The frequency of the 32.768 kHz crystal oscillator is incorrect or has been incorrect for an elapsed
period of time since the monitoring has been enabled.
Bit 20 – FOS Clock Failure Detector Fault Output Status
Value
Description
0
The fault output of the clock failure detector is inactive.
1
The fault output of the clock failure detector is active. This status is cleared by writing a ‘1’ to FOCLR in
PMC_FOCR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 394
SAM9X60
Power Management Controller (PMC)
Bit 19 – CFDS Clock Failure Detector Status
Value
Description
0
A clock failure of the main crystal oscillator clock is not detected.
1
A clock failure of the main crystal oscillator clock is detected.
Bit 18 – CFDEV Clock Failure Detector Event
Value
Description
0
No clock failure detection of the main crystal oscillator clock has occurred since the last read of
PMC_SR.
1
At least one clock failure detection of the main crystal oscillator clock has occurred since the last read
of PMC_SR.
Bit 17 – MOSCRCS Main RC Oscillator Status
Value
Description
0
Main RC oscillator is not stabilized.
1
Main RC oscillator is stabilized.
Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status
Value
Description
0
Selection is in progress.
1
Selection is done.
Bits 8, 9 – PCKRDYx Programmable Clock Ready Status
Value
Description
0
Programmable Clock x is not ready.
1
Programmable Clock x is ready.
Bit 3 – MCKRDY Master Clock Status
Value
Description
0
Master Clock is not ready.
1
Master Clock is ready.
Bit 0 – MOSCXTS Main Crystal Oscillator Status
Value
Description
0
Main crystal oscillator is not stabilized.
1
Main crystal oscillator is stabilized.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 395
SAM9X60
Power Management Controller (PMC)
29.16.17 PMC Interrupt Mask Register
Name:
Offset:
Reset:
Property:
PMC_IMR
0x006C
0x00000000
Read-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
PLL_INT
W
0
24
23
MCKMON
R
0
22
21
XT32KERR
R
0
20
19
18
CFDEV
R
0
17
MOSCRCS
R
0
16
MOSCSELS
R
0
15
14
13
12
11
10
9
PCKRDY1
R
0
8
PCKRDY0
R
0
7
6
5
4
3
MCKRDY
R
0
2
1
0
MOSCXTS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 25 – PLL_INT PLL Interrupt Mask
Bit 23 – MCKMON Master Clock Monitor Error Interrupt Mask
Bit 21 – XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Mask
Bit 18 – CFDEV Clock Failure Detector Event Interrupt Mask
Bit 17 – MOSCRCS Main RC Status Interrupt Mask
Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Mask
Bits 8, 9 – PCKRDYx Programmable Clock Ready x Interrupt Mask
Bit 3 – MCKRDY Master Clock Ready Interrupt Mask
Bit 0 – MOSCXTS Main Crystal Oscillator Status Interrupt Mask
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 396
SAM9X60
Power Management Controller (PMC)
29.16.18 PMC Fast Startup Mode Register
Name:
Offset:
Reset:
Property:
PMC_FSMR
0x0070
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
WLAN1
R/W
0
24
WLAN0
R/W
0
23
22
21
20
19
18
USBAL
R/W
0
17
RTCAL
R/W
0
16
RTTAL
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 24, 25 – WLANx Wakeup on LAN[x]
Value
Description
0
The Wakeup on LAN[x] alarm has no effect on the PMC.
1
The Wakeup on LAN[x] alarm enables a fast restart signal to the PMC.
Bit 18 – USBAL USB Alarm Enable
Value
Description
0
The USB alarm has no effect on the PMC.
1
The USB alarm enables a fast restart signal to the PMC.
Bit 17 – RTCAL RTC Alarm Enable
Value
Description
0
The RTC alarm has no effect on the PMC.
1
The RTC alarm enables a fast restart signal to the PMC.
Bit 16 – RTTAL RTT Alarm Enable
Value
Description
0
The RTT alarm has no effect on the PMC.
1
The RTT alarm enables a fast restart signal to the PMC.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 397
SAM9X60
Power Management Controller (PMC)
29.16.19 PMC Wakeup Control Register
Name:
Offset:
Reset:
Property:
Bit
PMC_WCR
0x0074
0x00000000
Read/Write
31
30
29
28
27
26
25
24
CMD
R/W
0
23
22
21
20
19
18
17
WIP
R/W
0
16
EN
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
1
WKPIONB[3:0]
R/W
R/W
0
0
0
R/W
0
Bit 24 – CMD Command
Value
Description
0
Read mode.
1
Write mode.
Bit 17 – WIP Wakeup Input Polarity
Defines the active polarity of the selected wakeup input. If the corresponding wakeup input is enabled at the FSTP
level, it enables a fast restart signal.
Bit 16 – EN Wakeup Input Enable
Value
Description
0
The selected wakeup input has no effect on the PMC.
1
The selected wakeup input enables a fast restart signal to the PMC.
Bits 3:0 – WKPIONB[3:0] Wakeup Input Number
Defines which wakeup source is to be modified during a write access (CMD is set to ‘1’) or which wakeup source
status is read on the next read access to this register (CMD is set to ‘0’).
Primary Signal Name
WKPIONB
PA2
PA9
PA10
PA28
PB0
PB3
PB18
PB25
PC24
PC25
0
1
2
3
4
5
6
7
8
9
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 398
SAM9X60
Power Management Controller (PMC)
...........continued
Primary Signal Name
WKPIONB
PC31
PD17
PD18
10
11
12
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 399
SAM9X60
Power Management Controller (PMC)
29.16.20 PMC Fault Output Clear Register
Name:
Offset:
Reset:
Property:
Bit
PMC_FOCR
0x0078
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FOCLR
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – FOCLR Fault Output Clear
Clears the clock failure detector fault output.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 400
SAM9X60
Power Management Controller (PMC)
29.16.21 PMC Write Protection Mode Register
Name:
Offset:
Reset:
Property:
PMC_WPMR
0x0080
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
WPITEN
R/W
0
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x504D43 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
Bit 1 – WPITEN Write Protection Interrupt Enable
See Register Write Protection for the list of registers that can be write-protected.
Value
Description
0
Disables the write protection on interrupt registers if WPKEY corresponds to 0x504D43 (“PMC” in
ASCII).
1
Enables the write protection on interrupt registers if WPKEY corresponds to 0x504D43 (“PMC” in
ASCII).
Bit 0 – WPEN Write Protection Enable
See Register Write Protection for the list of registers that can be write-protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 401
SAM9X60
Power Management Controller (PMC)
29.16.22 PMC Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
PMC_WPSR
0x0084
0x00000000
Read-only
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
WPVSRC[15:8]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
4
2
1
0
WPVS
R
0
Access
Reset
3
Access
Reset
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 0 – WPVS Write Protection Violation Status
Value
Description
0
No write protection violation has occurred since the last read of the PMC_WPSR.
1
A write protection violation has occurred since the last read of the PMC_WPSR. If this violation is an
unauthorized attempt to write a protected register, the associated violation is reported into field
WPVSRC.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 402
SAM9X60
Power Management Controller (PMC)
29.16.23 PMC Peripheral Control Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
31
CMD
R/W
0
23
R/W
0
15
PMC_PCR
0x0088
0x00000000
Read/Write
30
29
GCLKEN
R/W
0
22
21
GCLKDIV[3:0]
R/W
R/W
0
0
14
13
Access
Reset
Bit
Access
Reset
7
28
EN
R/W
0
27
26
25
GCLKDIV[7:4]
R/W
R/W
0
0
24
R/W
0
20
19
18
17
16
12
11
9
8
R/W
0
R/W
0
10
GCLKCSS[4:0]
R/W
0
R/W
0
R/W
0
3
PID[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
Bit 31 – CMD Command
Value
Description
0
Read mode.
1
Write mode.
Bit 29 – GCLKEN Generic Clock Enable
Value
Description
0
The selected generic clock is disabled.
1
The selected generic clock is enabled.
Bit 28 – EN Enable
Value
Description
0
Selected Peripheral clock is disabled.
1
Selected Peripheral clock is enabled.
Bits 27:20 – GCLKDIV[7:0] Generic Clock Division Ratio
Generic clock is the selected clock period divided by GCLKDIV + 1.
GCLKDIV must not be changed while the peripheral selects GCLKx (e.g., bit rate, etc.).
Bits 12:8 – GCLKCSS[4:0] Generic Clock Source Selection
Value
Name
0
MD_SLOW_CLK
1
TD_SLOW_CLOCK
2
MAINCK
3
MCK
4
PLLA
5
UPLL
© 2020 Microchip Technology Inc.
Description
MD_SLCK is selected
TD_SLCK is selected
MAINCK is selected
MCK is selected
PLLA is selected.
UPLL is selected.
Complete Datasheet
DS60001579C-page 403
SAM9X60
Power Management Controller (PMC)
Bits 6:0 – PID[6:0] Peripheral ID
Peripheral ID selection.
Refer to the identifiers as defined in the section “Peripheral Identifiers”.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 404
SAM9X60
Power Management Controller (PMC)
29.16.24 PMC Oscillator Calibration Register
Name:
Offset:
Reset:
Property:
PMC_OCR
0x008C
0x00404040
Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
SEL12
R/W
0
22
21
20
18
17
16
R/W
1
R/W
0
R/W
0
19
CAL12[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 23 – SEL12 Selection of Main RC Oscillator Calibration Bits
Value
Description
0
Factory-defined value.
1
Value written by user in CAL12 field of this register.
Bits 22:16 – CAL12[6:0] Main RC Oscillator Calibration Bits
Calibration bits applied to the RC Oscillator. Refer to the section “Electrical Characteristics”.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 405
SAM9X60
Power Management Controller (PMC)
29.16.25 PMC MCK Monitor Limits Register
Name:
Offset:
Reset:
Property:
Bit
PMC_MCKLIM
0x009C
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
12
11
MCK_HIGH_IT[7:0]
R/W
R/W
0
0
4
3
MCK_LOW_IT[7:0]
R/W
R/W
0
0
Bits 15:8 – MCK_HIGH_IT[7:0] MCK Monitoring High IT Limit
Beyond this limit, the MCK frequency monitor generates an interrupt.
Bits 7:0 – MCK_LOW_IT[7:0] MCK Monitoring Low IT Limit
Below this limit, the MCK frequency monitor generates an interrupt.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 406
SAM9X60
Power Management Controller (PMC)
29.16.26 PMC Peripheral Clock Status Register 0
Name:
Offset:
Reset:
Property:
PMC_CSR0
0x00A0
0x00000000
Read-only
“PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding peripheral clock is disabled.
1: The corresponding peripheral clock is enabled.
Bit
31
30
PID30
R
0
29
PID29
R
0
28
PID28
R
0
27
PID27
R
0
26
PID26
R
0
25
PID25
R
0
24
PID24
R
0
23
PID23
R
0
22
PID22
R
0
21
20
PID20
R
0
19
PID19
R
0
18
PID18
R
0
17
PID17
R
0
16
PID16
R
0
15
PID15
R
0
14
PID14
R
0
13
PID13
R
0
12
PID12
R
0
11
PID11
R
0
10
PID10
R
0
9
PID9
R
0
8
PID8
R
0
7
PID7
R
0
6
PID6
R
0
5
PID5
R
0
4
PID4
R
0
3
PID3
R
0
2
PID2
R
0
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 22, 23, 24, 25, 26, 27, 28, 29, 30 – PIDx Peripheral Clock x Status
Bits 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 – PIDx Peripheral Clock x Status
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 407
SAM9X60
Power Management Controller (PMC)
29.16.27 PMC Peripheral Clock Status Register 1
Name:
Offset:
Reset:
Property:
PMC_CSR1
0x00A4
0x00000000
Read-only
“PIDx” refers to identifiers as defined in the section “Peripheral Identifiers”.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding peripheral clock is disabled.
1: The corresponding peripheral clock is enabled.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PID49
R
0
16
15
PID47
R
0
14
13
PID45
R
0
12
PID44
R
0
11
PID43
R
0
10
PID42
R
0
9
PID41
R
0
8
PID40
R
0
7
PID39
R
0
6
PID38
R
0
5
PID37
R
0
4
PID36
R
0
3
PID35
R
0
2
PID34
R
0
1
PID33
R
0
0
PID32
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 17 – PIDx Peripheral Clock x Status
Bit 15 – PIDx Peripheral Clock x Status
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 – PIDx Peripheral Clock x Status
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 408
SAM9X60
Power Management Controller (PMC)
29.16.28 PMC Generic Clock Status Register 0
Name:
Offset:
Reset:
Property:
PMC_GCSR0
0x00C0
0x00000000
Read-only
“PIDx” refers to identifiers as defined in the section “Peripheral Identifiers".
The following configuration values are valid for all listed bit names of this register:
0: The corresponding generic clock is disabled.
1: The corresponding generic clock is enabled.
Bit
31
30
29
28
27
26
GPID26
R
0
25
GPID25
R
0
24
23
22
21
20
19
GPID19
R
0
18
17
GPID17
R
0
16
GPID16
R
0
15
GPID15
R
0
14
GPID14
R
0
13
GPID13
R
0
12
GPID12
R
0
11
GPID11
R
0
10
GPID10
R
0
9
GPID9
R
0
8
GPID8
R
0
7
GPID7
R
0
6
GPID6
R
0
5
GPID5
R
0
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26 – GPIDx Generic Clock x Status
Bit 19 – GPIDx Generic Clock x Status
Bits 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 – GPIDx Generic Clock x Status
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 409
SAM9X60
Power Management Controller (PMC)
29.16.29 PMC Generic Clock Status Register 1
Name:
Offset:
Reset:
Property:
PMC_GCSR1
0x00C4
0x00000000
Read-only
“PIDx” refers to identifiers as defined in the section “Peripheral Identifiers".
The following configuration values are valid for all listed bit names of this register:
0: The corresponding generic clock is disabled.
1: The corresponding generic clock is enabled.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GPID47
R
0
14
13
GPID45
R
0
12
11
10
GPID42
R
0
9
8
7
6
5
GPID37
R
0
4
3
2
GPID34
R
0
1
GPID33
R
0
0
GPID32
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 15 – GPIDx Generic Clock x Status
Bit 13 – GPIDx Generic Clock x Status
Bit 10 – GPIDx Generic Clock x Status
Bit 5 – GPIDx Generic Clock x Status
Bits 0, 1, 2 – GPIDx Generic Clock x Status
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 410
SAM9X60
Power Management Controller (PMC)
29.16.30 PMC PLL Interrupt Enable Register
Name:
Offset:
Reset:
Property:
PMC_PLL_IER
0x00E0
–
Write-only
This register can only be written if the WPITEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
UNLOCKU
W
–
16
UNLOCKA
W
–
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LOCKU
W
–
0
LOCKA
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 17 – UNLOCKU UPLL Unlock Interrupt Enable
Bit 16 – UNLOCKA PLLA Unlock Interrupt Enable
Bit 1 – LOCKU UPLL Lock Interrupt Enable
Bit 0 – LOCKA PLLA Lock Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 411
SAM9X60
Power Management Controller (PMC)
29.16.31 PMC PLL Interrupt Disable Register
Name:
Offset:
Reset:
Property:
PMC_PLL_IDR
0x00E4
–
Write-only
This register can only be written if the WPITEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
UNLOCKU
W
–
16
UNLOCKA
W
–
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LOCKU
W
–
0
LOCKA
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 17 – UNLOCKU UPLL Unlock Interrupt Disable
Bit 16 – UNLOCKA PLLA Unlock Interrupt Disable
Bit 1 – LOCKU UPLL Lock Interrupt Disable
Bit 0 – LOCKA PLLA Lock Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 412
SAM9X60
Power Management Controller (PMC)
29.16.32 PMC PLL Interrupt Mask Register
Name:
Offset:
Reset:
Property:
PMC_PLL_IMR
0x00E8
0x00000000
Read-only
This register can only be written if the WPITEN bit is cleared in the PMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
UNLOCKU
R
0
16
UNLOCKA
R
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LOCKU
R
0
0
LOCKA
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 17 – UNLOCKU UPLL Unlock Interrupt Mask
Bit 16 – UNLOCKA PLLA Unlock Interrupt Mask
Bit 1 – LOCKU UPLL Lock Interrupt Mask
Bit 0 – LOCKA PLLA Lock Interrupt Mask
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 413
SAM9X60
Power Management Controller (PMC)
29.16.33 PMC PLL Interrupt Status Register 0
Name:
Offset:
Reset:
Property:
Bit
PMC_PLL_ISR0
0x00EC
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
UNLOCKU
R
0
16
UNLOCKA
R
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LOCKU
R
0
0
LOCKA
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 17 – UNLOCKU UPLL Unlock Interrupt Status
Value
Description
0
UPLL is not unlocked.
1
UPLL is unlocked. To know the unlock type, the PMC_PISR1 register can be read.
Bit 16 – UNLOCKA PLLA Unlock Interrupt Status
Value
Description
0
PLLA is not unlocked.
1
PLLA is unlocked. To know the unlock type, the PMC_PISR1 register can be read.
Bit 1 – LOCKU UPLL Lock Interrupt Status
Value
Description
0
UPLL is not locked.
1
UPLL is locked.
Bit 0 – LOCKA PLLA Lock Interrupt Status
Value
Description
0
PLLA is not locked.
1
PLLA is locked.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 414
SAM9X60
Power Management Controller (PMC)
29.16.34 PMC PLL Interrupt Status Register 1
Name:
Offset:
Reset:
Property:
Bit
PMC_PLL_ISR1
0x00F0
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OVRU
R
0
16
OVRA
R
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
UDRU
R
0
0
UDRA
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 17 – OVRU UPLL Overflow
Value
Description
0
UPLL is not in overflow state.
1
UPLL has encountered an overflow.
Bit 16 – OVRA PLLA Overflow
Value
Description
0
PLLA is not in overflow state.
1
PLLA has encountered an overflow.
Bit 1 – UDRU UPLL Underflow
Value
Description
0
UPLL is not in underflow state.
1
UPLL has encountered an underflow.
Bit 0 – UDRA PLLA Underflow
Value
Description
0
PLLA is not in underflow state.
1
PLLA has encountered an underflow.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 415
SAM9X60
Parallel Input/Output Controller (PIO)
30.
30.1
Parallel Input/Output Controller (PIO)
Description
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may
be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This ensures
effective optimization of the pins of the product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface.
Each I/O line of the PIO Controller features the following:
•
•
•
•
•
•
•
An input change interrupt enabling level change detection on any I/O line
Additional Interrupt modes enabling rising edge, falling edge, low-level or high-level detection on any I/O line
A glitch filter providing rejection of glitches lower than one-half of peripheral clock cycle
A debouncing filter providing rejection of unwanted pulses from key or push button operations
Multi-drive capability similar to an open drain I/O line
Control of the I/O line pullup and pulldown
Input visibility and output control
The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write
operation.
30.2
Embedded Characteristics
•
•
•
•
•
•
•
•
•
Up to 32 Programmable I/O Lines
Fully Programmable through Set/Clear Registers
Multiplexing of Four Peripheral Functions per I/O Line
For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
– Input Change Interrupt
– Programmable Glitch Filter
– Programmable Debouncing Filter
– Multi-drive Option Enables Driving in Open Drain
– Programmable Pullup on Each I/O Line
– Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
– Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High-Level
Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write
Register Write Protection
Programmable Schmitt Trigger Inputs
Programmable Slewrate per I/O Line
Programmable I/O Drive
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SAM9X60
Parallel Input/Output Controller (PIO)
30.3
Block Diagram
Figure 30-1. Block Diagram
PIO Controller
Interrupt Controller
PMC
PIO Interrupt
Peripheral Clock
Data, Enable
Up to x
peripheral IOs
Embedded
Peripheral
PIN 0
Data, Enable
PIN 1
Up to x
peripheral IOs
Embedded
Peripheral
PIN x-1
x is an integer representing the maximum number
of IOs managed by one PIO controller.
30.4
Product Dependencies
30.4.1
Pin Multiplexing
APB
Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line
multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the
hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by
their application. When an I/O line is general-purpose only, i.e., not multiplexed with any peripheral I/O, programming
of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control
how the pin is driven by the product.
30.4.2
External Interrupt Lines
The interrupt signals FIQ and IRQ0 to IRQn are generally multiplexed through the PIO Controllers. However, it is not
necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the external
interrupt lines are used only as inputs.
When the WKUPx input pins must be used as external interrupt lines, the PIO Controller must be configured to
disable the peripheral control on these IOs, and the corresponding IO lines must be set to Input mode.
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SAM9X60
Parallel Input/Output Controller (PIO)
30.4.3
Power Management
The Power Management Controller controls the peripheral clock in order to save power. Writing any of the registers
of the user interface does not require the peripheral clock to be enabled. This means that the configuration of the I/O
lines does not require the peripheral clock to be enabled.
However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch
filtering. Note that the input change interrupt, the interrupt modes on a programmable event and the read of the pin
level require the clock to be validated.
After a hardware reset, the peripheral clock is disabled by default.
The user must configure the Power Management Controller before any access to the input line information.
30.4.4
Interrupt Sources
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller
interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in the
Peripheral Identifiers table to identify the interrupt sources dedicated to the PIO Controllers. Using the PIO Controller
requires the Interrupt Controller to be programmed first.
The PIO Controller interrupt can be generated only if the peripheral clock is enabled.
30.5
Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is
represented in the following figure. In this description each signal shown represents one of up to 32 possible indexes.
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SAM9X60
Parallel Input/Output Controller (PIO)
Figure 30-2. I/O Line Control Logic
PIO_OER[0]
VDD
PIO_OSR[0]
PIO_PUER[0]
PIO_ODR[0]
PIO_PUSR[0]
PIO_PUDR[0]
1
Peripheral A Output Enable
00
01
10
11
Peripheral B Output Enable
Peripheral C Output Enable
Peripheral D Output Enable
0
0
PIO_PER[0]
PIO_ABCDSR1[0]
PIO_PDR[0]
00
01
10
11
Peripheral B Output
Peripheral C Output
Peripheral D Output
1
PIO_PSR[0]
PIO_ABCDSR2[0]
Peripheral A Output
Integrated
Pull-Up
Resistor
PIO_MDER[0]
PIO_MDSR[0]
0
PIO_MDDR[0]
0
PIO_SODR[0]
1
PIO_ODSR[0]
Pad
PIO_CODR[0]
1
PIO_PPDER[0]
Integrated
Pull-Down
Resistor
PIO_PPDSR[0]
PIO_PPDDR[0]
GND
Peripheral A Input
Peripheral B Input
Peripheral C Input
Peripheral D Input
PIO_PDSR[0]
PIO_ISR[0]
0
D
Peripheral Clock
0
Slow Clock
PIO_SCDR
Clock
Divider
div_slck
1
Programmable
Glitch
or
Debouncing
Filter
Q
DFF
1
D
Q
DFF
EVENT
DETECTOR
PIO Interrupt
Peripheral Clock
Resynchronization
Stage
PIO_IER[0]
PIO_IMR[0]
PIO_IDR[0]
PIO_IFER[0]
PIO_IFSR[0]
PIO_IFSCER[0]
(Up to 32 possible inputs)
PIO_ISR[31]
PIO_IFDR[0]
PIO_IFSCSR[0]
PIO_IER[31]
PIO_IFSCDR[0]
PIO_IMR[31]
PIO_IDR[31]
30.5.1
Pullup and Pulldown Resistor Control
Each I/O line is designed with an embedded pullup resistor and an embedded pulldown resistor. The pullup resistor
can be enabled or disabled by writing to the Pull-Up Enable Register (PIO_PUER) or Pull-Up Disable Register
(PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in the Pull-Up
Status Register (PIO_PUSR). Reading a one in PIO_PUSR means the pullup is disabled and reading a zero means
the pullup is enabled. The pulldown resistor can be enabled or disabled by writing the Pull-Down Enable Register
(PIO_PPDER) or the Pull-Down Disable Register (PIO_PPDDR), respectively. Writing in these registers results in
setting or clearing the corresponding bit in the Pull-Down Status Register (PIO_PPDSR). Reading a one in
PIO_PPDSR means the pullup is disabled and reading a zero means the pulldown is enabled.
Enabling the pulldown resistor while the pullup resistor is still enabled is not possible. In this case, the write of
PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pullup resistor while the pulldown resistor is
still enabled is not possible. In this case, the write of PIO_PUER for the relevant I/O line is discarded.
Control of the pullup resistor is possible regardless of the configuration of the I/O line.
After reset, depending on the I/O, pullup or pulldown can be set.
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SAM9X60
Parallel Input/Output Controller (PIO)
30.5.2
I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable Register
(PIO_PER) and the Disable Register (PIO_PDR). The Status Register (PIO_PSR) is the result of the set and clear
registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value
of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the Peripheral ABCD
Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A value of one indicates the pin is controlled by the PIO
Controller.
If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR
have no effect and PIO_PSR returns a one for the corresponding bit.
After reset, the I/O lines are controlled by the PIO Controller, i.e., PIO_PSR resets at one. However, in some events,
it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be
driven inactive after reset, or for address lines that must be driven low for booting out of an external memory). Thus,
the reset value of PIO_PSR is defined at the product level and depends on the multiplexing of the device.
30.5.3
Peripheral A or B or C or D Selection
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed
by writing PIO_ABCDSR1 and PIO_ABCDSR2.
For each pin:
•
•
•
•
The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2
means peripheral A is selected.
The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2
means peripheral B is selected.
The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2
means peripheral C is selected.
The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2
means peripheral D is selected.
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are
always connected to the pin input (see Figure 30-2).
Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin.
However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2 in
addition to a write in PIO_PDR.
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating that all the PIO lines are configured on
peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O Line mode.
If the software selects a peripheral A, B, C or D which does not exist for a pin, no alternate functions are enabled for
this pin and the selection is taken into account. The PIO Controller does not carry out checks to prevent selection of a
peripheral which does not exist.
30.5.4
Output Control
When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of
the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and
PIO_ABCDSR2 determines whether the pin is driven or not.
When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing
the Output Enable Register (PIO_OER) and Output Disable Register (PIO_ODR). The results of these write
operations are detected in the Output Status Register (PIO_OSR). When a bit in this register is at zero, the
corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the PIO
Controller.
The level driven on an I/O line can be determined by writing in the Set Output Data Register (PIO_SODR) and the
Clear Output Data Register (PIO_CODR). These write operations, respectively, set and clear the Output Data Status
Register (PIO_ODSR), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR
manages PIO_OSR whether the pin is configured to be controlled by the PIO Controller or assigned to a peripheral
function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller.
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SAM9X60
Parallel Input/Output Controller (PIO)
Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level
driven on the I/O line.
30.5.5
Synchronous Data Output
Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by using
PIO_SODR and PIO_CODR. It requires two successive write operations into two different registers. To overcome
this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR. Only bits
unmasked by the Output Write Status Register (PIO_OWSR) are written. The mask bits in PIO_OWSR are set by
writing to the Output Write Enable Register (PIO_OWER) and cleared by writing to the Output Write Disable Register
(PIO_OWDR).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
30.5.6
Multi-Drive Control (Open Drain)
Each I/O can be independently programmed in open drain by using the multi-drive feature. This feature permits
several drivers to be connected on the I/O line which is driven low only by each device. An external pullup resistor (or
enabling of the internal one) is generally required to guarantee a high level on the line.
The multi-drive feature is controlled by the Multi-driver Enable Register (PIO_MDER) and the Multi-driver Disable
Register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or
assigned to a peripheral function. The Multi-driver Status Register (PIO_MDSR) indicates the pins that are configured
to support external drivers.
After reset, the multi-drive feature is disabled on all pins, i.e., PIO_MDSR resets at value 0x0.
30.5.7
Output Line Timings
The following figure shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly
writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. The Output Line Timings
figure also shows when the feedback in the Pin Data Status Register (PIO_PDSR) is available.
Figure 30-3. Output Line Timings
Peripheral clock
Write PIO_SODR
Write PIO_ODSR at 1
APB Access
Write PIO_CODR
Write PIO_ODSR at 0
APB Access
PIO_ODSR
2 cycles
2 cycles
PIO_PDSR
30.5.8
Inputs
The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless
of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the
levels present on the I/O line at the time the clock was disabled.
30.5.9
Input Glitch and Debouncing Filters
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 peripheral clock and the debouncing filter can filter a
pulse of less than 1/2 period of a programmable divided slow clock.
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SAM9X60
Parallel Input/Output Controller (PIO)
The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock
Disable Register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable Register (PIO_IFSCER). Writing
PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status Register
(PIO_IFSCSR).
The current selection status can be checked by reading the PIO_IFSCSR.
•
•
If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period.
If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable
divided slow clock period.
For the debouncing filter, the period of the divided slow clock is defined by writing in the DIV field of the Slow Clock
Divider Debouncing Register (PIO_SCDR):
tdiv_slck = ((DIV + 1) × 2) × tslck
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle
(selected clock represents peripheral clock or divided slow clock depending on PIO_IFSCDR and PIO_IFSCER
programming) is automatically rejected, while a pulse with a duration of one selected clock (peripheral clock or
divided slow clock) cycle or more is accepted. For pulse durations between 1/2 selected clock cycle and one selected
clock cycle, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus
for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch to be reliably filtered out, its
duration must not exceed 1/2 selected clock cycle.
The filters also introduce some latencies, illustrated in the following two figures.
The glitch filters are controlled by the Input Filter Enable Register (PIO_IFER), the Input Filter Disable Register
(PIO_IFDR) and the Input Filter Status Register (PIO_IFSR). Writing PIO_IFER and PIO_IFDR respectively sets and
clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It
acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing
filters require that the peripheral clock is enabled.
Figure 30-4. Input Glitch Filter Timing
PIO_IFCSR = 0
Peripheral clcok
up to 1.5 cycles
Pin Level
1 cycle
1 cycle
1 cycle
1 cycle
PIO_PDSR
if PIO_IFSR = 0
2 cycles
1 cycle
up to 2.5 cycles
PIO_PDSR
if PIO_IFSR = 1
up to 2 cycles
Figure 30-5. Input Debouncing Filter Timing
PIO_IFCSR = 1
Divided Slow Clock
(div_slck)
Pin Level
PIO_PDSR
if PIO_IFSR = 0
up to 2 cycles tperipheral clock
up to 2 cycles tperipheral clock
1 cycle tdiv_slck
PIO_PDSR
if PIO_IFSR = 1
up to 1.5 cycles tdiv_slck
up to 2 cycles tperipheral clock
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1 cycle tdiv_slck
up to 1.5 cycles tdiv_slck
Complete Datasheet
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DS60001579C-page 422
SAM9X60
Parallel Input/Output Controller (PIO)
30.5.10 Input Edge/Level Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The
Input Edge/Level interrupt is controlled by writing the Interrupt Enable Register (PIO_IER) and the Interrupt Disable
Register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and clearing the
corresponding bit in the Interrupt Mask Register (PIO_IMR). As input change detection is possible only by comparing
two successive samplings of the input of the I/O line, the peripheral clock must be enabled. The Input Change
interrupt is available regardless of the configuration of the I/O line, i.e., configured as an input only, controlled by the
PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable
Register (PIO_AIMER) and Additional Interrupt Modes Disable Register (PIO_AIMDR). The current state of this
selection can be read through the Additional Interrupt Modes Mask Register (PIO_AIMMR).
These additional modes are:
•
•
•
•
Rising edge detection
Falling edge detection
Low-level detection
High-level detection
In order to select an additional interrupt mode:
•
•
The type of event detection (edge or level) must be selected by writing in the Edge Select Register (PIO_ESR)
and Level Select Register (PIO_LSR) which select, respectively, the edge and level detection. The current status
of this selection is accessible through the Edge/Level Status Register (PIO_ELSR).
The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the Falling
Edge/Low-Level Select Register (PIO_FELLSR) and Rising Edge/High-Level Select Register (PIO_REHLSR)
which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high- or low-level detection
(if level is selected in PIO_ELSR). The current status of this selection is accessible through the Fall/Rise - Low/
High Status Register (PIO_FRLHSR).
When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status Register
(PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The interrupt
signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts
that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
Figure 30-6. Event Detector on Input Lines (Figure Represents Line 0)
Event Detector
Rising Edge
Detector
1
Falling Edge
Detector
0
0
PIO_REHLSR[0]
1
PIO_FRLHSR[0]
1
PIO_FELLSR[0]
Resynchronized input on line 0
Event detection on line 0
0
High Level
Detector
1
Low Level
Detector
0
PIO_LSR[0]
PIO_ELSR[0]
PIO_AIMER[0]
PIO_ESR[0]
PIO_AIMMR[0]
PIO_AIMDR[0]
Edge
Detector
Example of interrupt generation on following lines:
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SAM9X60
Parallel Input/Output Controller (PIO)
•
•
•
•
•
•
•
•
•
Rising edge on PIO line 0
Falling edge on PIO line 1
Rising edge on PIO line 2
Low-level on PIO line 3
High-level on PIO line 4
High-level on PIO line 5
Falling edge on PIO line 6
Rising edge on PIO line 7
Any edge on the other lines
The following table provides the required configuration for this example.
Table 30-1. Configuration for Example Interrupt Generation
Configuration
Description
Interrupt Mode
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Then the additional Interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in
PIO_AIMER.
Edge or Level
Detection
Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in edge detection by default, if they have not been
previously configured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge
detection by writing 32’h0000_00C7 in PIO_ESR.
Falling/Rising Edge or
Low/High-Level
Detection
Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writing
32’h0000_00B5 in PIO_REHLSR.
The other lines are configured in falling edge or low-level detection by default if they have
not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in falling
edge/low-level detection by writing 32’h0000_004A in PIO_FELLSR.
Figure 30-7. Input Change Interrupt Timings When No Additional Interrupt Modes
Peripheral clock
Pin Level
PIO_ISR
Read PIO_ISR
APB Access
APB Access
30.5.11 Programmable Schmitt Trigger
It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the
Schmitt trigger is requested when using the QTouch® Library.
30.5.12 I/O Lines Programming Example
The programming example shown in the following table is used to obtain the following configuration:
•
•
•
4-bit output port on I/O lines 0 to 3 (should be written in a single write operation), open-drain, with pullup resistor
Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pullup resistor, no
pulldown resistor
Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pullup resistors, glitch filters
and input change interrupts
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SAM9X60
Parallel Input/Output Controller (PIO)
•
Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt),
no pullup resistor, no glitch filter
• I/O lines 16 to 19 assigned to peripheral A functions with pullup resistor
• I/O lines 20 to 23 assigned to peripheral B functions with pulldown resistor
• I/O lines 24 to 27 assigned to peripheral C with input change interrupt, no pullup resistor and no pulldown
resistor
• I/O lines 28 to 31 assigned to peripheral D, no pullup resistor and no pulldown resistor
Table 30-2. Programming Example
Register
Value to be Written
PIO_PER
0x0000_FFFF
PIO_PDR
0xFFFF_0000
PIO_OER
0x0000_00FF
PIO_ODR
0xFFFF_FF00
PIO_IFER
0x0000_0F00
PIO_IFDR
0xFFFF_F0FF
PIO_SODR
0x0000_0000
PIO_CODR
0x0FFF_FFFF
PIO_IER
0x0F00_0F00
PIO_IDR
0xF0FF_F0FF
PIO_MDER
0x0000_000F
PIO_MDDR
0xFFFF_FFF0
PIO_PUDR
0xFFF0_00F0
PIO_PUER
0x000F_FF0F
PIO_PPDDR
0xFF0F_FFFF
PIO_PPDER
0x00F0_0000
PIO_ABCDSR1
0xF0F0_0000
PIO_ABCDSR2
0xFF00_0000
PIO_OWER
0x0000_000F
PIO_OWDR
0x0FFF_FFF0
30.5.13 Register Write Protection
To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the PIO Write Protection Mode Register (PIO_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the PIO Write Protection Status Register
(PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the PIO_WPSR.
The following registers can be write-protected:
•
•
•
•
•
PIO Enable Register
PIO Disable Register
PIO Output Enable Register
PIO Output Disable Register
PIO Input Filter Enable Register
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SAM9X60
Parallel Input/Output Controller (PIO)
•
•
•
•
•
•
•
•
•
•
•
PIO Input Filter Disable Register
PIO Multi-driver Enable Register
PIO Multi-driver Disable Register
PIO Pull-Up Disable Register
PIO Pull-Up Enable Register
PIO Peripheral ABCD Select Register 1
PIO Peripheral ABCD Select Register 2
PIO Output Write Enable Register
PIO Output Write Disable Register
PIO Pad Pull-Down Disable Register
PIO Pad Pull-Down Enable Register
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Parallel Input/Output Controller (PIO)
30.6
Register Summary
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface
registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no
effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the
PIO Controller and PIO_PSR returns one systematically.
Offset
Name
0x00
PIO_PER
0x04
PIO_PDR
0x08
PIO_PSR
0x0C
...
0x0F
Reserved
0x10
PIO_OER
0x14
PIO_ODR
0x18
PIO_OSR
0x1C
...
0x1F
Reserved
0x20
PIO_IFER
0x24
PIO_IFDR
0x28
PIO_IFSR
0x2C
...
0x2F
Reserved
0x30
PIO_SODR
Bit Pos.
7
6
5
4
3
2
1
0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
31:24
23:16
15:8
7:0
P31
P23
P15
P7
P30
P22
P14
P6
P29
P21
P13
P5
P28
P20
P12
P4
P27
P19
P11
P3
P26
P18
P10
P2
P25
P17
P9
P1
P24
P16
P8
P0
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 427
SAM9X60
Parallel Input/Output Controller (PIO)
...........continued
Offset
Name
0x34
PIO_CODR
0x38
PIO_ODSR
0x3C
PIO_PDSR
0x40
PIO_IER
0x44
PIO_IDR
0x48
PIO_IMR
0x4C
PIO_ISR
0x50
PIO_MDER
0x54
PIO_MDDR
0x58
PIO_MDSR
0x5C
...
0x5F
Reserved
0x60
PIO_PUDR
0x64
PIO_PUER
0x68
PIO_PUSR
0x6C
...
0x6F
Reserved
Bit Pos.
7
6
5
4
3
2
1
0
31:24
23:16
P31
P23
P30
P22
P29
P21
P28
P20
P27
P19
P26
P18
P25
P17
P24
P16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 428
SAM9X60
Parallel Input/Output Controller (PIO)
...........continued
Offset
Name
0x70
PIO_ABCDSR1
0x74
PIO_ABCDSR2
0x78
...
0x7F
Reserved
0x80
PIO_IFSCDR
0x84
PIO_IFSCER
0x88
PIO_IFSCSR
0x8C
PIO_SCDR
0x90
PIO_PPDDR
0x94
PIO_PPDER
0x98
PIO_PPDSR
0x9C
...
0x9F
Reserved
0xA0
PIO_OWER
0xA4
PIO_OWDR
0xA8
PIO_OWSR
0xAC
...
0xAF
Reserved
Bit Pos.
7
6
5
4
3
2
1
0
31:24
23:16
P31
P23
P30
P22
P29
P21
P28
P20
P27
P19
P26
P18
P25
P17
P24
P16
15:8
7:0
31:24
23:16
15:8
7:0
P15
P7
P31
P23
P15
P7
P14
P6
P30
P22
P14
P6
P13
P5
P29
P21
P13
P5
P12
P4
P28
P20
P12
P4
P11
P3
P27
P19
P11
P3
P10
P2
P26
P18
P10
P2
P9
P1
P25
P17
P9
P1
P8
P0
P24
P16
P8
P0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
DIV[13:8]
DIV[7:0]
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 429
SAM9X60
Parallel Input/Output Controller (PIO)
...........continued
Offset
Name
0xB0
PIO_AIMER
0xB4
PIO_AIMDR
0xB8
PIO_AIMMR
0xBC
...
0xBF
Reserved
0xC0
PIO_ESR
0xC4
PIO_LSR
0xC8
PIO_ELSR
0xCC
...
0xCF
Reserved
0xD0
PIO_FELLSR
0xD4
PIO_REHLSR
0xD8
PIO_FRLHSR
0xDC
...
0xE3
Reserved
0xE4
0xE8
0xEC
...
0xFF
PIO_WPMR
PIO_WPSR
Bit Pos.
7
6
5
4
3
2
1
0
31:24
23:16
P31
P23
P30
P22
P29
P21
P28
P20
P27
P19
P26
P18
P25
P17
P24
P16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P31
P23
P15
P7
P31
P23
P15
P7
P31
P23
P15
P7
P30
P22
P14
P6
P30
P22
P14
P6
P30
P22
P14
P6
P29
P21
P13
P5
P29
P21
P13
P5
P29
P21
P13
P5
P28
P20
P12
P4
P28
P20
P12
P4
P28
P20
P12
P4
P27
P19
P11
P3
P27
P19
P11
P3
P27
P19
P11
P3
P26
P18
P10
P2
P26
P18
P10
P2
P26
P18
P10
P2
P25
P17
P9
P1
P25
P17
P9
P1
P25
P17
P9
P1
P24
P16
P8
P0
P24
P16
P8
P0
P24
P16
P8
P0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WPEN
WPVSRC[15:8]
WPVSRC[7:0]
WPVS
Reserved
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 430
SAM9X60
Parallel Input/Output Controller (PIO)
...........continued
Offset
Name
0x0100
PIO_SCHMITT
0x0104
...
0x010F
Reserved
0x0110
PIO_SLEWR
0x0114
...
0x0117
Reserved
0x0118
PIO_DRIVER1
Bit Pos.
7
6
5
4
3
2
1
0
31:24
23:16
SCHMITT31
SCHMITT23
SCHMITT30
SCHMITT22
SCHMITT29
SCHMITT21
SCHMITT28
SCHMITT20
SCHMITT27
SCHMITT19
SCHMITT26
SCHMITT18
SCHMITT25
SCHMITT17
SCHMITT24
SCHMITT16
15:8
7:0
SCHMITT15
SCHMITT7
SCHMITT14
SCHMITT6
SCHMITT13
SCHMITT5
SCHMITT12
SCHMITT4
SCHMITT11
SCHMITT3
SCHMITT10
SCHMITT2
SCHMITT9
SCHMITT1
SCHMITT8
SCHMITT0
31:24
23:16
15:8
7:0
SR31
SR23
SR15
SR7
SR30
SR22
SR14
SR6
SR29
SR21
SR13
SR5
SR28
SR20
SR12
SR4
SR27
SR19
SR11
SR3
SR26
SR18
SR10
SR2
SR25
SR17
SR9
SR1
SR24
SR16
SR8
SR0
31:24
23:16
15:8
7:0
DR31
DR23
DR15
DR7
DR30
DR22
DR14
DR6
DR29
DR21
DR13
DR5
DR28
DR20
DR12
DR4
DR27
DR19
DR11
DR3
DR26
DR18
DR10
DR2
DR25
DR17
DR9
DR1
DR24
DR16
DR8
DR0
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 431
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.1
PIO Enable Register
Name:
Offset:
Reset:
Property:
PIO_PER
0x0000
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Enable
Value
Description
0
No effect.
1
Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 432
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.2
PIO Disable Register
Name:
Offset:
Reset:
Property:
PIO_PDR
0x0004
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Disable
Value
Description
0
No effect.
1
Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 433
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.3
PIO Status Register
Name:
Offset:
Property:
PIO_PSR
0x0008
Read-only
Reset values depend on the product implementation.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
R
30
P30
R
29
P29
R
28
P28
R
27
P27
R
26
P26
R
25
P25
R
24
P24
R
23
P23
R
22
P22
R
21
P21
R
20
P20
R
19
P19
R
18
P18
R
17
P17
R
16
P16
R
15
P15
R
14
P14
R
13
P13
R
12
P12
R
11
P11
R
10
P10
R
9
P9
R
8
P8
R
7
P7
R
6
P6
R
5
P5
R
4
P4
R
3
P3
R
2
P2
R
1
P1
R
0
P0
R
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Status
Value
Description
0
PIO is inactive on the corresponding I/O line (peripheral is active).
1
PIO is active on the corresponding I/O line (peripheral is inactive).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 434
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.4
PIO Output Enable Register
Name:
Offset:
Reset:
Property:
PIO_OER
0x0010
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Output Enable
Value
Description
0
No effect.
1
Enables the output on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 435
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.5
PIO Output Disable Register
Name:
Offset:
Reset:
Property:
PIO_ODR
0x0014
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Output Disable
Value
Description
0
No effect.
1
Disables the output on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 436
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.6
PIO Output Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_OSR
0x0018
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Output Status
Value
Description
0
The I/O line is a pure input.
1
The I/O line is enabled in output.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 437
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.7
PIO Input Filter Enable Register
Name:
Offset:
Reset:
Property:
PIO_IFER
0x0020
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Input Filter Enable
Value
Description
0
No effect.
1
Enables the input glitch filter on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 438
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.8
PIO Input Filter Disable Register
Name:
Offset:
Reset:
Property:
PIO_IFDR
0x0024
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Input Filter Disable
Value
Description
0
No effect.
1
Disables the input glitch filter on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 439
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.9
PIO Input Filter Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_IFSR
0x0028
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Input Filter Status
Value
Description
0
The input glitch filter is disabled on the I/O line.
1
The input glitch filter is enabled on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 440
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.10 PIO Set Output Data Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_SODR
0x0030
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Set Output Data
Value
Description
0
No effect.
1
Sets the data to be driven on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 441
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.11 PIO Clear Output Data Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_CODR
0x0034
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Clear Output Data
Value
Description
0
No effect.
1
Clears the data to be driven on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 442
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.12 PIO Output Data Status Register
Name:
Offset:
Reset:
Property:
PIO_ODSR
0x0038
–
Read-only
or Read/Write
PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
R or R/W
–
30
P30
R or R/W
–
29
P29
R or R/W
–
28
P28
R or R/W
–
27
P27
R or R/W
–
26
P26
R or R/W
–
25
P25
R or R/W
–
24
P24
R or R/W
–
23
P23
R or R/W
–
22
P22
R or R/W
–
21
P21
R or R/W
–
20
P20
R or R/W
–
19
P19
R or R/W
–
18
P18
R or R/W
–
17
P17
R or R/W
–
16
P16
R or R/W
–
15
P15
R or R/W
–
14
P14
R or R/W
–
13
P13
R or R/W
–
12
P12
R or R/W
–
11
P11
R or R/W
–
10
P10
R or R/W
–
9
P9
R or R/W
–
8
P8
R or R/W
–
7
P7
R or R/W
–
6
P6
R or R/W
–
5
P5
R or R/W
–
4
P4
R or R/W
–
3
P3
R or R/W
–
2
P2
R or R/W
–
1
P1
R or R/W
–
0
P0
R or R/W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Output Data Status
Value
Description
0
The data to be driven on the I/O line is 0.
1
The data to be driven on the I/O line is 1.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 443
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.13 PIO Pin Data Status Register
Name:
Offset:
Property:
PIO_PDSR
0x003C
Read-only
Reset values depend on the level of the I/O lines.
Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the
levels present on the I/O line at the time the clock was disabled.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
R
30
P30
R
29
P29
R
28
P28
R
27
P27
R
26
P26
R
25
P25
R
24
P24
R
23
P23
R
22
P22
R
21
P21
R
20
P20
R
19
P19
R
18
P18
R
17
P17
R
16
P16
R
15
P15
R
14
P14
R
13
P13
R
12
P12
R
11
P11
R
10
P10
R
9
P9
R
8
P8
R
7
P7
R
6
P6
R
5
P5
R
4
P4
R
3
P3
R
2
P2
R
1
P1
R
0
P0
R
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Output Data Status
Value
Description
0
The I/O line is at level 0.
1
The I/O line is at level 1.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 444
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.14 PIO Interrupt Enable Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_IER
0x0040
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Input Change Interrupt Enable
Value
Description
0
No effect.
1
Enables the input change interrupt on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 445
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.15 PIO Interrupt Disable Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_IDR
0x0044
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Input Change Interrupt Disable
Value
Description
0
No effect.
1
Disables the input change interrupt on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 446
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.16 PIO Interrupt Mask Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_IMR
0x0048
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Input Change Interrupt Mask
Value
Description
0
Input change interrupt is disabled on the I/O line.
1
Input change interrupt is enabled on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 447
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.17 PIO Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_ISR
0x004C
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Input Change Interrupt Status
Value
Description
0
No input change has been detected on the I/O line since PIO_ISR was last read or since reset.
1
At least one input change has been detected on the I/O line since PIO_ISR was last read or since
reset.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 448
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.18 PIO Multi-driver Enable Register
Name:
Offset:
Reset:
Property:
PIO_MDER
0x0050
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Multi-drive Enable
Value
Description
0
No effect.
1
Enables multi-drive on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 449
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.19 PIO Multi-driver Disable Register
Name:
Offset:
Reset:
Property:
PIO_MDDR
0x0054
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Multi-drive Disable
Value
Description
0
No effect.
1
Disables multi-drive on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 450
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.20 PIO Multi-driver Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_MDSR
0x0058
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Multi-drive Status
Value
Description
0
The multi-drive is disabled on the I/O line. The pin is driven at high- and low-level.
1
The multi-drive is enabled on the I/O line. The pin is driven at low-level only.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 451
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.21 PIO Pull-Up Disable Register
Name:
Offset:
Reset:
Property:
PIO_PUDR
0x0060
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Pull-Up Disable
Value
Description
0
No effect.
1
Disables the pullup resistor on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 452
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.22 PIO Pull-Up Enable Register
Name:
Offset:
Reset:
Property:
PIO_PUER
0x0064
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Pull-Up Enable
Value
Description
0
No effect.
1
Enables the pullup resistor on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 453
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.23 PIO Pull-Up Status Register
Name:
Offset:
Property:
PIO_PUSR
0x0068
Read-only
Reset values depend on the product implementation.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
R
30
P30
R
29
P29
R
28
P28
R
27
P27
R
26
P26
R
25
P25
R
24
P24
R
23
P23
R
22
P22
R
21
P21
R
20
P20
R
19
P19
R
18
P18
R
17
P17
R
16
P16
R
15
P15
R
14
P14
R
13
P13
R
12
P12
R
11
P11
R
10
P10
R
9
P9
R
8
P8
R
7
P7
R
6
P6
R
5
P5
R
4
P4
R
3
P3
R
2
P2
R
1
P1
R
0
P0
R
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Pull-Up Status
Value
Description
0
Pullup resistor is enabled on the I/O line.
1
Pullup resistor is disabled on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 454
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.24 PIO Peripheral ABCD Select Register 1
Name:
Offset:
Reset:
Property:
PIO_ABCDSR1
0x0070
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
R/W
0
30
P30
R/W
0
29
P29
R/W
0
28
P28
R/W
0
27
P27
R/W
0
26
P26
R/W
0
25
P25
R/W
0
24
P24
R/W
0
23
P23
R/W
0
22
P22
R/W
0
21
P21
R/W
0
20
P20
R/W
0
19
P19
R/W
0
18
P18
R/W
0
17
P17
R/W
0
16
P16
R/W
0
15
P15
R/W
0
14
P14
R/W
0
13
P13
R/W
0
12
P12
R/W
0
11
P11
R/W
0
10
P10
R/W
0
9
P9
R/W
0
8
P8
R/W
0
7
P7
R/W
0
6
P6
R/W
0
5
P5
R/W
0
4
P4
R/W
0
3
P3
R/W
0
2
P2
R/W
0
1
P1
R/W
0
0
P0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Peripheral Select
If the same bit is set to '0' in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral B function.
If the same bit is set to '1' in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral C function.
1: Assigns the I/O line to the Peripheral D function.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 455
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.25 PIO Peripheral ABCD Select Register 2
Name:
Offset:
Reset:
Property:
PIO_ABCDSR2
0x0074
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
R/W
0
30
P30
R/W
0
29
P29
R/W
0
28
P28
R/W
0
27
P27
R/W
0
26
P26
R/W
0
25
P25
R/W
0
24
P24
R/W
0
23
P23
R/W
0
22
P22
R/W
0
21
P21
R/W
0
20
P20
R/W
0
19
P19
R/W
0
18
P18
R/W
0
17
P17
R/W
0
16
P16
R/W
0
15
P15
R/W
0
14
P14
R/W
0
13
P13
R/W
0
12
P12
R/W
0
11
P11
R/W
0
10
P10
R/W
0
9
P9
R/W
0
8
P8
R/W
0
7
P7
R/W
0
6
P6
R/W
0
5
P5
R/W
0
4
P4
R/W
0
3
P3
R/W
0
2
P2
R/W
0
1
P1
R/W
0
0
P0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Peripheral Select
If the same bit is set to '0' in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral C function.
If the same bit is set to '1' in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral B function.
1: Assigns the I/O line to the Peripheral D function.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 456
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.26 PIO Input Filter Slow Clock Disable Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_IFSCDR
0x0080
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Peripheral Clock Glitch Filtering Select
Value
Description
0
No effect.
1
The glitch filter is able to filter glitches with a duration < tperipheral clock/2.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 457
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.27 PIO Input Filter Slow Clock Enable Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_IFSCER
0x0084
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Slow Clock Debouncing Filtering Select
Value
Description
0
No effect.
1
The debouncing filter is able to filter pulses with a duration < tdiv_slck/2.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 458
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.28 PIO Input Filter Slow Clock Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_IFSCSR
0x0088
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Glitch or Debouncing Filter Selection Status
Value
Description
0
The glitch filter is able to filter glitches with a duration < tperipheral clock/2.
1
The debouncing filter is able to filter pulses with a duration < tdiv_slck/2.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 459
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.29 PIO Slow Clock Divider Debouncing Register
Name:
Offset:
Reset:
Property:
Bit
PIO_SCDR
0x008C
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
DIV[13:8]
Access
Reset
Bit
7
6
R/W
0
R/W
0
5
4
DIV[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:0 – DIV[13:0] Slow Clock Divider Selection for Debouncing
tdiv_slck = ((DIV + 1) × 2) × tslck
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 460
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.30 PIO Pad Pull-Down Disable Register
Name:
Offset:
Reset:
Property:
PIO_PPDDR
0x0090
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Pull-Down Disable
Value
Description
0
No effect.
1
Disables the pull-down resistor on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 461
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.31 PIO Pad Pull-Down Enable Register
Name:
Offset:
Reset:
Property:
PIO_PPDER
0x0094
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Pull-Down Enable
Value
Description
0
No effect.
1
Enables the pull-down resistor on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 462
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.32 PIO Pad Pull-Down Status Register
Name:
Offset:
Property:
PIO_PPDSR
0x0098
Read-only
Reset values depend on the product implementation.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
R
30
P30
R
29
P29
R
28
P28
R
27
P27
R
26
P26
R
25
P25
R
24
P24
R
23
P23
R
22
P22
R
21
P21
R
20
P20
R
19
P19
R
18
P18
R
17
P17
R
16
P16
R
15
P15
R
14
P14
R
13
P13
R
12
P12
R
11
P11
R
10
P10
R
9
P9
R
8
P8
R
7
P7
R
6
P6
R
5
P5
R
4
P4
R
3
P3
R
2
P2
R
1
P1
R
0
P0
R
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Pull-Down Status
Value
Description
0
Pull-down resistor is enabled on the I/O line.
1
Pull-down resistor is disabled on the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 463
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.33 PIO Output Write Enable Register
Name:
Offset:
Reset:
Property:
PIO_OWER
0x00A0
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Output Write Enable
Value
Description
0
No effect.
1
Enables writing PIO_ODSR for the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 464
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.34 PIO Output Write Disable Register
Name:
Offset:
Reset:
Property:
PIO_OWDR
0x00A4
–
Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Output Write Disable
Value
Description
0
No effect.
1
Disables writing PIO_ODSR for the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 465
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.35 PIO Output Write Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_OWSR
0x00A8
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Output Write Status
Value
Description
0
Writing PIO_ODSR does not affect the I/O line.
1
Writing PIO_ODSR affects the I/O line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 466
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.36 PIO Additional Interrupt Modes Enable Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_AIMER
0x00B0
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Additional Interrupt Modes Enable
Value
Description
0
No effect.
1
The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 467
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.37 PIO Additional Interrupt Modes Disable Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_AIMDR
0x00B4
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Additional Interrupt Modes Disable
Value
Description
0
No effect.
1
The Interrupt mode is set to the default Interrupt mode (Both-edge Detection).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 468
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.38 PIO Additional Interrupt Modes Mask Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_AIMMR
0x00B8
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO I/O Line Index
Selects the I/O event type triggering an interrupt.
Value
Description
0
The interrupt source is a both-edge detection event.
1
The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 469
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.39 PIO Edge Select Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_ESR
0x00C0
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Edge Interrupt Selection
Value
Description
0
No effect.
1
The interrupt source is an edge-detection event.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 470
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.40 PIO Level Select Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_LSR
0x00C4
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Level Interrupt Selection
Value
Description
0
No effect.
1
The interrupt source is a level-detection event.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 471
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.41 PIO Edge/Level Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_ELSR
0x00C8
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Edge/Level Interrupt Source Selection
Value
Description
0
The interrupt source is an edge-detection event.
1
The interrupt source is a level-detection event.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 472
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.42 PIO Falling Edge/Low-Level Select Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_FELLSR
0x00D0
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Falling Edge/Low-Level Interrupt Selection
Value
Description
0
No effect.
1
The interrupt source is set to a falling edge detection or low-level detection event, depending on
PIO_ELSR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 473
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.43 PIO Rising Edge/High-Level Select Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_REHLSR
0x00D4
–
Write-only
31
P31
W
–
30
P30
W
–
29
P29
W
–
28
P28
W
–
27
P27
W
–
26
P26
W
–
25
P25
W
–
24
P24
W
–
23
P23
W
–
22
P22
W
–
21
P21
W
–
20
P20
W
–
19
P19
W
–
18
P18
W
–
17
P17
W
–
16
P16
W
–
15
P15
W
–
14
P14
W
–
13
P13
W
–
12
P12
W
–
11
P11
W
–
10
P10
W
–
9
P9
W
–
8
P8
W
–
7
P7
W
–
6
P6
W
–
5
P5
W
–
4
P4
W
–
3
P3
W
–
2
P2
W
–
1
P1
W
–
0
P0
W
–
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Rising Edge/High-Level Interrupt Selection
Value
Description
0
No effect.
1
The interrupt source is set to a rising edge detection or high-level detection event, depending on
PIO_ELSR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 474
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.44 PIO Fall/Rise - Low/High Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_FRLHSR
0x00D8
0x00000000
Read-only
31
P31
R
0
30
P30
R
0
29
P29
R
0
28
P28
R
0
27
P27
R
0
26
P26
R
0
25
P25
R
0
24
P24
R
0
23
P23
R
0
22
P22
R
0
21
P21
R
0
20
P20
R
0
19
P19
R
0
18
P18
R
0
17
P17
R
0
16
P16
R
0
15
P15
R
0
14
P14
R
0
13
P13
R
0
12
P12
R
0
11
P11
R
0
10
P10
R
0
9
P9
R
0
8
P8
R
0
7
P7
R
0
6
P6
R
0
5
P5
R
0
4
P4
R
0
3
P3
R
0
2
P2
R
0
1
P1
R
0
0
P0
R
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – P
PIO Edge/Level Interrupt Source Selection
Value
Description
0
The interrupt source is a falling edge detection (if PIO_ELSR = 0) or low-level detection event (if
PIO_ELSR = 1).
1
The interrupt source is a rising edge detection (if PIO_ELSR = 0) or high-level detection event (if
PIO_ELSR = 1).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 475
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.45 PIO Write Protection Mode Register
Name:
Offset:
Reset:
Property:
PIO_WPMR
0x00E4
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x50494F PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
Bit 0 – WPEN Write Protection Enable
See “Register Write Protection” for the list of registers that can be protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 476
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.46 PIO Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
PIO_WPSR
0x00E8
0x00000000
Read-only
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
WPVSRC[15:8]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
4
2
1
0
WPVS
R
0
Access
Reset
3
Access
Reset
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 0 – WPVS Write Protection Violation Status
Value
Description
0
No write protection violation has occurred since the last read of the PIO_WPSR.
1
A write protection violation has occurred since the last read of the PIO_WPSR. If this violation is an
unauthorized attempt to write a protected register, the associated violation is reported into field
WPVSRC.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 477
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.47 PIO Schmitt Trigger Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_SCHMITT
0x0100
0x00000000
Read/Write
31
SCHMITT31
R/W
0
30
SCHMITT30
R/W
0
29
SCHMITT29
R/W
0
28
SCHMITT28
R/W
0
27
SCHMITT27
R/W
0
26
SCHMITT26
R/W
0
25
SCHMITT25
R/W
0
24
SCHMITT24
R/W
0
23
SCHMITT23
R/W
0
22
SCHMITT22
R/W
0
21
SCHMITT21
R/W
0
20
SCHMITT20
R/W
0
19
SCHMITT19
R/W
0
18
SCHMITT18
R/W
0
17
SCHMITT17
R/W
0
16
SCHMITT16
R/W
0
15
SCHMITT15
R/W
0
14
SCHMITT14
R/W
0
13
SCHMITT13
R/W
0
12
SCHMITT12
R/W
0
11
SCHMITT11
R/W
0
10
SCHMITT10
R/W
0
9
SCHMITT9
R/W
0
8
SCHMITT8
R/W
0
7
SCHMITT7
R/W
0
6
SCHMITT6
R/W
0
5
SCHMITT5
R/W
0
4
SCHMITT4
R/W
0
3
SCHMITT3
R/W
0
2
SCHMITT2
R/W
0
1
SCHMITT1
R/W
0
0
SCHMITT0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 –
SCHMITTx PIO Schmitt Trigger Control
Value
Description
0
Schmitt trigger is enabled.
1
Schmitt trigger is disabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 478
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.48 PIO I/O Slewrate Control Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PIO_SLEWR
0x0110
0x00000000
Read/Write
31
SR31
R/W
0
30
SR30
R/W
0
29
SR29
R/W
0
28
SR28
R/W
0
27
SR27
R/W
0
26
SR26
R/W
0
25
SR25
R/W
0
24
SR24
R/W
0
23
SR23
R/W
0
22
SR22
R/W
0
21
SR21
R/W
0
20
SR20
R/W
0
19
SR19
R/W
0
18
SR18
R/W
0
17
SR17
R/W
0
16
SR16
R/W
0
15
SR15
R/W
0
14
SR14
R/W
0
13
SR13
R/W
0
12
SR12
R/W
0
11
SR11
R/W
0
10
SR10
R/W
0
9
SR9
R/W
0
8
SR8
R/W
0
7
SR7
R/W
0
6
SR6
R/W
0
5
SR5
R/W
0
4
SR4
R/W
0
3
SR3
R/W
0
2
SR2
R/W
0
1
SR1
R/W
0
0
SR0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 –
SRx Slewrate Control for IO line x
Refer to section “Electrical characteristics” for recommended usage of this bit.
Value
Name
Description
0
DISABLED
No slewrate control
1
ENABLED
Slewrate controlled
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 479
SAM9X60
Parallel Input/Output Controller (PIO)
30.6.49 PIO I/O Drive Register 1
Name:
Offset:
Reset:
Property:
PIO_DRIVER1
0x0118
0x00000000
Read/Write
Refer to section “Electrical characteristics” for recommended usage of the following bits.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
DR31
R/W
0
30
DR30
R/W
0
29
DR29
R/W
0
28
DR28
R/W
0
27
DR27
R/W
0
26
DR26
R/W
0
25
DR25
R/W
0
24
DR24
R/W
0
23
DR23
R/W
0
22
DR22
R/W
0
21
DR21
R/W
0
20
DR20
R/W
0
19
DR19
R/W
0
18
DR18
R/W
0
17
DR17
R/W
0
16
DR16
R/W
0
15
DR15
R/W
0
14
DR14
R/W
0
13
DR13
R/W
0
12
DR12
R/W
0
11
DR11
R/W
0
10
DR10
R/W
0
9
DR9
R/W
0
8
DR8
R/W
0
7
DR7
R/W
0
6
DR6
R/W
0
5
DR5
R/W
0
4
DR4
R/W
0
3
DR3
R/W
0
2
DR2
R/W
0
1
DR1
R/W
0
0
DR0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 –
DRx Drive of PIO Line
Value
Name
Description
0
LOW_DRIVE
Lowest drive
1
HIGH_DRIVE
Highest drive
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SAM9X60
External Bus Interface (EBI)
31.
31.1
External Bus Interface (EBI)
Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices
and the embedded Memory Controller of the SAM9X60.
The Static Memory, MPDDR, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI.
These external Memory Controllers are capable of handling several types of external memory and peripheral devices,
such as SRAM, PROM, EPROM, EEPROM, Flash and (DDR2-/LPDDR-/SDR-/LPSDR-) SDRAM. The EBI operates
with 1.8V or 3.3V Power Supplies (VDDIOM and VDDNF).
The EBI also supports the NAND Flash protocols via integrated circuitry that greatly reduces the requirements for
external components. Furthermore, the EBI handles data transfers with up to six external devices, each assigned to
six address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or
32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (NCS[5:0]) and several control pins that
are generally multiplexed between the different external Memory Controllers.
31.2
Embedded Characteristics
•
•
•
Integrates Four External Memory Controllers:
– Static memory controller
– MPDDR controller
– SDRAM controller
– 8-bit NAND Flash ECC controller
Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select)
Up to Six Chip Selects with Configurable Assignment:
– Static memory controller on NCS0, NCS1, NCS2, NCS3, NCS4, NCS5
– MPDDR / SDRAM controller (SDCS) or static memory controller on NCS1
– NAND Flash support on NCS3
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SAM9X60
External Bus Interface (EBI)
31.3
EBI Block Diagram
Figure 31-1. External Bus Interface Organization
Bus Matrix
System Bus
External Bus Interface
D[15:0]
A0/NBS0
MPDDR
Controller
A1/NWR2/NBS2/DQM2
A[15:2], A19
A16/BA0
A17/BA1
SDRAM
Controller
A18/BA2
NCS0
NCS1/SDCS
NRD
Static
Memory
Controller
NWR0/NWE
NWR1/NBS1
NWR3/NBS3/DQM3
SDCK, SDCK#, SDCKE
DQM[1:0]
DQS[1:0]
MUX
Logic
RAS, CAS
SDWE, SDA10
NAND Flash
Logic
NCS3/NANDCS
PMECC
PMERRLOC
Controllers
NANDOE
NANDWE
A21/NANDALE
Address Decoders
A22/NANDCLE
Chip Select
Assignor
PIO
D[31:16]
A[25:20]
NCS5
NCS4
User Interface
NCS2
NWAIT
Peripheral Bus
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SAM9X60
External Bus Interface (EBI)
31.4
I/O Lines Description
Table 31-1. EBI I/O Lines Description
Name
Function
Type
Active Level
EBI
EBI_D0–EBI_D31
Data Bus
I/O
–
EBI_A0–EBI_A25
Address Bus
Output
–
EBI_NWAIT
External Wait Signal
Input
Low
SMC
EBI_NCS0–EBI_NCS5
Chip Select Lines
Output
Low
EBI_NWR0–EBI_NWR3
Write Signals
Output
Low
EBI_NRD
Read Signal
Output
Low
EBI_NWE
Write Enable
Output
Low
EBI_NBS0–EBI_NBS3
Byte Mask Signals
Output
Low
EBI for NAND Flash Support
EBI_NANDCS
NAND Flash Chip Select Line
Output
Low
EBI_NANDOE
NAND Flash Output Enable
Output
Low
EBI_NANDWE
NAND Flash Write Enable
Output
Low
MPDDR / SDRAM Controllers
EBI_SDCK, EBI_SDCK#
MPDDR Differential Clock
Output
–
EBI_SDCK
SDRAM Clock
Output
–
EBI_SDCKE
MPDDR/SDRAM Clock Enable
Output
High
EBI_SDCS
MPDDR/SDRAM Chip Select Line
Output
Low
EBI_BA0–2
Bank Select
Output
–
EBI_SDWE
MPDDR/SDRAM Write Enable
Output
Low
EBI_RAS - EBI_CAS
Row and Column Signal
Output
Low
EBI_SDA10
SDRAM Address 10 Line
Output
–
The connection of some signals through the MUX logic is not direct and depends on the Memory Controller currently
in use.
The following table details the connections between the two Memory Controllers and the EBI pins.
Table 31-2. EBI Pins and Memory Controllers I/O Lines Connections
EBIx Pins
SDRAM I/O Lines
SMC I/O Lines
EBI_NWR1/NBS1/CFIOR
NBS1
NWR1
EBI_A0/NBS0
Not Supported
SMC_A0
EBI_A1/NBS2/NWR2
Not Supported
SMC_A1
EBI_A[11:2]
SDRAM_A[9:0]
SMC_A[11:2]
EBI_SDA10
SDRAM_A10
Not Supported
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SAM9X60
External Bus Interface (EBI)
...........continued
31.5
31.5.1
EBIx Pins
SDRAM I/O Lines
SMC I/O Lines
EBI_A12
Not Supported
SMC_A12
EBI_A[15:13]
SDRAM_A[13:11]
SMC_A[15:13]
EBI_A[25:16]
Not Supported
SMC_A[25:16]
EBI_D[31:0]
D[31:0]
D[31:0]
Application Examples
Hardware Interface
The following table details the connections to be applied between the EBI pins and the external devices for each
memory controller.
Table 31-3. EBI Pins and External Static Device Connections
Signals:
EBI_
Pins of the Interfaced Device
8-bit
Static
Device
2 x 8-bit
Static
Devices
16-bit
Static
Device
Controller
4 x 8-bit
Static
Devices
2 x 16-bit
Static
Devices
32-bit
Static Device
SMC
D0–D7
D0–D7
D0–D7
D0–D7
D0–D7
D0–D7
D0–D7
D8–D15
–
D8–D15
D8–D15
D8–D15
D8–15
D8–15
D16–D23
–
–
–
D16–D23
D16–D23
D16–D23
D24–D31(1)
–
–
–
D24–D31
D24–D31
D24–D31
BE0
A0/NBS0
A0
–
NLB
–
NLB(2)
A1/NWR2/NBS2/
DQM2
A1
A0
A0
WE(3)
NLB(4)
BE2
A2–A22(1)
A[2:22]
A[1:21]
A[1:21]
A[0:20]
A[0:20]
A[0:20]
A23–A25(1)
A[23:25]
A[22:24]
A[22:24]
A[21:23]
A[21:23]
A[21:23]
NCS0
CS
CS
CS
CS
CS
CS
NCS1/DDRSDCS
CS
CS
CS
CS
CS
CS
NCS2(1)
CS
CS
CS
CS
CS
CS
NCS3/NANDCS
CS
CS
CS
CS
CS
CS
NCS4(1)
CS
CS
CS
CS
CS
CS
NCS5(1)
CS
CS
CS
CS
CS
CS
NRD
OE
OE
OE
OE
OE
OE
NWR0/NWE
WE
WE(5)
WE
WE(3)
WE
WE
NWR1/NBS1
–
WE(5)
NUB
WE(3)
NUB(2)
BE1
NWR3/NBS3/
DQM3
–
–
–
WE(3)
NUB(4)
BE3
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SAM9X60
External Bus Interface (EBI)
Notes:
1. D24–31 and A20, A23–A25, NCS2, NCS4, NCS5 are multiplexed on PD15–PD21.
2. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
3. NWRx enables corresponding byte x writes (x = 0, 1, 2 or 3).
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
5. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
Table 31-4. EBI Pins and External Device Connections
Signals:
EBI_
Pins of the Interfaced Device
Power supply
DDR2/LPDDR
SDR/LPSDR
NAND Flash
MPDDRC
SDRAMC
NFC
Controller
D0–D7
VDDIOM
D0–D7
D0–D7
NFD0–NFD7(1)
D8–D15
VDDIOM
D8–D15
D8–D15
–
D16–D23
VDDNF
–
D16–D23
NFD0–NFD7(1)
D24–D31
VDDNF
–
D24–D31
–
A0/NBS0
VDDIOM
–
–
–
A1/NWR2/NBS2/DQM2
VDDIOM
–
DQM2
–
DQM0–DQM1
VDDIOM
DQM0–DQM1
DQM0–DQM1
–
DQS0–DQS1
VDDIOM
DQS0–DQS1
–
–
A2–A10
VDDIOM
A[0:8]
A[0:8]
–
A11
VDDIOM
A9
A9
–
SDA10
VDDIOM
A10
A10
–
A12
VDDIOM
–
–
–
A13–A14
VDDIOM
A[11:12]
A[11:12]
–
A15
VDDIOM
A13
A13
–
A16/BA0
VDDIOM
BA0
BA0
–
A17/BA1
VDDIOM
BA1
BA1
–
A18/BA2
VDDIOM
BA2
–
–
A19
VDDIOM
–
–
–
A20
VDDNF
–
–
–
A21/NANDALE
VDDNF
–
–
ALE
A22/NANDCLE
VDDNF
–
–
CLE
A23–A24
VDDNF
–
–
–
A25
VDDNF
–
–
–
NCS0
VDDIOM
–
–
–
NCS1/DDRSDCS
VDDIOM
DDRCS
SDCS
–
NCS2
VDDNF
–
–
–
NCS3/NANDCS
VDDNF
–
–
CE
NCS4
VDDNF
–
–
–
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SAM9X60
External Bus Interface (EBI)
...........continued
Signals:
EBI_
Pins of the Interfaced Device
Power supply
DDR2/LPDDR
SDR/LPSDR
NAND Flash
MPDDRC
SDRAMC
NFC
Controller
NCS5
VDDNF
–
–
–
NANDOE
VDDNF
–
–
OE
NANDWE
VDDNF
–
–
WE
NRD
VDDIOM
–
–
–
NWR0/NWE
VDDIOM
–
–
–
NWR1/NBS1
VDDIOM
–
–
–
NWR3/NBS3/DQM3
VDDNF
–
DQM3
–
SDCK
VDDIOM
CK
CK
–
SDCK#
VDDIOM
CK#
–
–
SDCKE
VDDIOM
CKE
CKE
–
RAS
VDDIOM
RAS
RAS
–
CAS
VDDIOM
CAS
CAS
–
SDWE
VDDIOM
WE
WE
–
Pxx
VDDNF
–
–
CE
NWAIT
VDDNF
–
–
RDY
Note: 1. The switch NFD0_ON_D16 is used to select NAND Flash path on D0–D7 or D16–D23 depending on
memory power supplies. This switch is located in the SFR_CCFG_EBICSA register in the Special Function Register.
31.5.2
Product Dependencies
31.5.2.1 I/O Lines
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must
first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the
External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.
31.5.3
Functional Description
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external devices
(memories, FPGA, etc.). It controls the waveforms and the parameters of the external address, data and control
buses and is composed of the following elements:
•
•
•
•
•
•
Static Memory Controller (SMC)
MPDDR and SDRAM Controllers (MPDDRC and SDRAMC)
Programmable Multibit ECC Controller (PMECC)
A chip select assignment feature that assigns an AHB address space to the external devices
A multiplex controller circuit that shares the pins between the different Memory Controllers
Programmable NAND Flash support logic
31.5.3.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and
the control signals through a multiplex logic operating in function of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at
a stable state while no external access is being performed. Multiplexing is also designed to respect the data float
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SAM9X60
External Bus Interface (EBI)
times defined in the Memory Controllers. Furthermore, refresh cycles of the DDR2, LP-DDR and SDRAM are
executed independently by the MPDDRC or SDRAMC without delaying the other external Memory Controller
accesses.
31.5.3.2 Pull-up and Pull-down Control
The SFR_CCFG_EBICSA register in the Special Function Register User Interface enable on-chip pull-up and pulldown resistors on data bus lines not multiplexed with the PIO Controller lines. The pull-down resistors are enabled
after reset. The bits, EBIx_DBPUC and EBI_DBPDC, control the pull-up and pull-down resistors on the D0–D15 lines.
Pull-up or pull-down resistors on the D16–D31 lines can be performed by programming the appropriate PIO
controller.
31.5.3.3 Voltage Level Control
The EBI I/Os accept two voltage level ranges: 1.7V to 1.9V range or 3.0V to 3.6V range. The EBI I/O circuits must be
programmed to accommodate the voltage level in each application:
•
•
1.7V to 1.9V range: the SFR_CCFG_EBICSA.EBI_DRIVE must be programmed to HIGH_DRIVE (1).
3.0V to 3.6V range: the SFR_CCFG_EBICSA.EBI_DRIVE must be programmed to LOW_DRIVE (0).
At reset output, the drive selection defaults to LOW_DRIVE.
This setting is applied to all the device I/Os with “DDRIO” type as defined in the Pin Description table (refer to 6.
Package and Pinout). Other EBI I/Os with “GPIO” type must be programmed according to the recommendations on
the GPIO DRIVE and SLEWRATE controls in the PIO user interface.
31.5.3.4 Power Supplies
The product embeds a dual power supply for the EBI: VDDNF for NAND Flash signals, and VDDIOM for other
signals. This makes it possible to use a 1.8V or 3.3V NAND Flash independently of the SDRAM power supply.
The switch NFD0_ON_D16 is used to select the NAND Flash path on D0–D7 or D16–D23 depending on memory
power supplies. This switch is located in the SFR_CCFG_EBICSA register (refer to 24. Special Function Registers
(SFR)).
The following figure illustrates an example of the NAND Flash and the external RAM (DDR2 or LP-DDR or 16-bit LPSDR) in the same power supply range (NFD0_ON_D16 = default).
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SAM9X60
External Bus Interface (EBI)
Figure 31-2. NAND Flash and External RAM in Same Power Supply Range (NFD0_ON_D16 = default)
16-bit
DDR2 or LP-DDR or
LP-SDR (1.8V)
D[15:0]
D[15:0]
NAND Flash (1.8V)
D[7:0]
A[22:21]
ALE
CLE
EBI
32bit SDRAM (3.3V)
D[15:0]
D[31:16]
D[15:0]
D[31:16]
NAND Flash (3.3V)
D[7:0]
A[22:21]
ALE
CLE
EBI
The following figure illustrates an example of the NAND Flash and the external RAM (DDR2 or LP-DDR or 16-bit LPSDR) NOT in the same power supply range (NFD0_ON_D16 = 1).
This can be used if the SMC connects to the NAND Flash only. Using this function with another device on the SMC
will lead to an unpredictable behavior of that device. In that case, the default value must be selected.
Figure 31-3. NAND Flash and External RAM Not in Same Power Supply Range (NFD0_ON_D16 = 1)
16-bit
DDR2 or LP-DDR or
LP-SDR (1.8V)
D[15:0]
D[15:0]
NAND Flash (3.3V)
D[23:16]
A[22:21]
EBI
D[7:0]
ALE
CLE
At reset NFD0_ON_D16 = 0 and the NAND Flash bus is connected to D0–D7.
31.5.3.5 Static Memory Controller
For information on the Static Memory Controller, refer to the section “Static Memory Controller (SMC)”.
31.5.3.6 Multi-Port DDR and SDRAM Controllers
The product embeds a multi-port DDR Controller. This allows to use three additional ports on the MPDDRC to lessen
the EBI load from a part of SDRAM accesses. This increases the bandwidth when DDR2 and NAND Flash devices
are used. This feature is used with DDR2, LPDDR1 and SDR-SDRAM devices in Address/data or Address/data/
command multiplexed mode.
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SAM9X60
External Bus Interface (EBI)
It is controlled by the DDR_MP_EN bit in EBI Chip Select Assignment Register.
Figure 31-4. Multi-Port Enabled MPDDRC (DDR_MP_EN = 1)
MPDDRC
Port 3
Port 2
Port 1
DDR2 or LP-DDR
Device
Bus Matrix
Port 0
NAND Flash
Device
EBI
When:
• a NAND Flash memory is connected to D16-D23 and
• a DDR2-SDRAM or LPDDR-SDRAM is connected to D0-D15,
the bits SFR_CCFG_EBICSA.DDR_MP_EN and SFR_CCFG_EBICSA.NFD0_ON_D16 must both be set before
performing the SDRAM initialization.
Figure 31-5. Multi-Port Disabled MPDDRC (DDR_MP_EN = 0)
MPDDRC
not used
not used
not used
DDR2 or LP-DDR
Device
Bus Matrix
Port 0
NAND Flash
Device
EBI
Set DQIEN_F to 1: force EBI D0-D15 data pads in Input mode. Mandatory when EBI D0-D15 is shared between
DDR-DRAM (LPDDR/DDR2) and static memory (via MPDDRC and SMC).
Figure 31-6. Multi-Port Disabled SDRAMC (DDR_MP_EN = 0)
SDRAMC
not used
not used
not used
(LP-)SDR
Device
Bus Matrix
Port 0
NAND Flash
Device
EBI
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SAM9X60
External Bus Interface (EBI)
Figure 31-7. Multiplexed Mode Multi-Port Enabled SDRAMC (DDR_MP_EN = 1) (With Addr/Data/Cmd
Multiplexed Mode)
MPDDRC
Port 3
Port 2
(LP-)SDR
Device
Port 1
Bus Matrix
Port 0
NCS0/2/3/4/5
NAND/FPGA ...
Devices
EBI
The product embeds a multi-port SDR Controller in Address/Data or Address/Data/Command multiplexed mode. This
allows to use three additional ports on the SDRAMC to remove SDRAM accesses from the EBI load. This increases
the bandwidth when SDR-SDRAM and a full SMC are used. This configuration allows to support up to five chip
selects on SMC.
31.5.3.7 Programmable Multibit ECC Controller
For information on the PMECC Controller, refer to 35. Programmable Multibit Error Correction Code Controller
(PMECC) and 36. Programmable Multibit ECC Error Location Controller (PMERRLOC). Also refer to 12.4.7.2 NAND
Flash Boot: PMECC Error Detection and Correction.
31.5.3.8 NAND Flash Support
External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices.
External Bus Interface
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the
EBI_CS3A field in the SFR_CCFG_EBICSA Register in the SFR User Interface to the appropriate value enables the
NAND Flash logic. For details on this register, refer to 24. Special Function Registers (SFR). Access to an external
NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and
0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE
signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails
to lie in the NCS3 address space. See the figure below for more information. For details on these waveforms, refer to
34. Static Memory Controller (SMC).
NAND Flash Signals
The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits
A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash
device are distinguished by using their addresses within the NCSx address space. The chip enable (CE) signal of the
device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when
NCSx is not selected, preventing the device from returning to Standby mode.
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SAM9X60
External Bus Interface (EBI)
Figure 31-8. NAND Flash Application Example
D[7:0] or D[23:16]
A[22:21]
AD[7:0]
ALE
CLE
EBI
NAND Flash
NANDOE
NANDWE
NCS3/NANDCS
NOE
NWE
CE
PIO
R/B
Note: The CE signal of the NAND Flash must be connected to PIOD4 (NCS3/NANDCS) if the user's system boots
out of NAND Flash.
31.5.4
Implementation Examples
The following hardware configurations are given for illustration only. The user should refer to the memory
manufacturer web site to check current device availability.
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SAM9X60
External Bus Interface (EBI)
31.5.4.1 2x8-bit DDR2 on EBI
31.5.4.1.1 Hardware Configuration
31.5.4.1.2 Software Configuration
• Assign EBI_CS1 to the MPDDRC controller by setting the EBI_CS1A bit in the SFR_CCFG_EBICSA register.
• Initialize the MPDDR Controller depending on the DDR2 device and system bus frequency.
The DDR2 initialization sequence is described in the subsection “DDR2 Device Initialization” of the MPDDRC section.
In this case, VDDNF can be different from VDDIOM. The NAND Flash device can be 3.3V or 1.8V and wired on the
D16–D23 data bus. NFD0_ON_D16 is to be set to 1.
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SAM9X60
External Bus Interface (EBI)
31.5.4.2 16-bit LPDDR on EBI
31.5.4.2.1 Hardware Configuration
31.5.4.2.2 Software Configuration
The following configuration must be performed:
•
•
Assign EBI_CS1 to the MPDDR controller by setting the bit EBI_CS1A bit in the SFR_CCFG_EBICSA register.
Initialize the MPDDR Controller depending on the LP-DDR device and system bus frequency.
The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initialization” in the
MPDDRC section.
In this case, VDDNF can be different from VDDIOM. The NAND Flash device can be 3.3V or 1.8V and wired on the
D16–D23 data bus. NFD0_ON_D16 is to be set to 1.
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SAM9X60
External Bus Interface (EBI)
31.5.4.3 16-bit SDRAM on EBI
31.5.4.3.1 Hardware Configuration
31.5.4.3.2 Software Configuration
The following configuration must be performed:
•
•
Assign the EBI CS1 to the SDRAM controller by setting the EBI_CS1A bit in the SFR_CCFG_EBICSA register.
Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
Program the Data Bus Width to 16 bits.
The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller
(SDRAMC)”.
In this case, VDDNF can be different from VDDIOM. The NAND Flash device can be 3.3V or 1.8V and wired on the
D16–D23 data bus. NFD0_ON_D16 is to be set to 1.
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SAM9X60
External Bus Interface (EBI)
31.5.4.4 2x16-bit SDRAM on EBI
31.5.4.4.1 Hardware Configuration
A[1..14]
D[0..31]
SDRAM
VDDIOM
R1
470K
SDCS
R2
0R
MN1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
SDA10
A13
23
24
25
26
29
30
31
32
33
34
22
35
BA0
BA1
20
21
A14
36
40
CKE
37
CLK
38
DQM0
DQM1
15
39
CAS
RAS
17
18
WE
16
19
A0 MT48LC16M16A2 DQ0
A1
DQ1
DQ2
A2
DQ3
A3
A4
DQ4
A5
DQ5
A6
DQ6
DQ7
A7
DQ8
A8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C1
VDD
VDD
VDD
CKE
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
28
41
54
6
12
46
52
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VDDIOM
C3
C5
C1
C7
100NF 100NF
100NF 100NF
C2
C4
C6
100NF 100NF 100NF
VDDIOM
MT48LC16M16A2P-75IT
256 Mbits
MN2
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
SDA10
A13
23
24
25
26
29
30
31
32
33
34
22
35
BA0
BA1
20
21
A14
36
40
CKE
37
CLK
38
DQM2
DQM3
15
39
CAS
RAS
17
18
WE
16
19
A0 MT48LC16M16A2 DQ0
DQ1
A1
A2
DQ2
DQ3
A3
A4
DQ4
A5
DQ5
DQ6
A6
A7
DQ7
DQ8
A8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C1
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
VDDQ
DQML
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
R3
470K
R4
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
28
41
54
6
12
46
52
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
VDDIOM
C10
C12
C8
C14
100NF 100NF
100NF 100NF
C9
C11
C13
100NF 100NF
100NF
256 Mbits
0R
31.5.4.4.2 Software Configuration
The following configuration must be performed:
•
•
Assign the EBI CS1 to the SDRAM controller by setting the EBI_CS1A bit in the SFR_CCFG_EBICSA register.
Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
Program the Data Bus Width to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the
dedicated PIOs must be programmed in Peripheral mode in the PIO controller.
The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller
(SDRAMC)”.
In this case, VDDNF must be equal to VDDIOM. The NAND Flash device must be 3.3V and wired on the D0–D7 data
bus. NFD0_ON_D16 is to be set to 0.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 495
SAM9X60
External Bus Interface (EBI)
31.5.4.5 8-bit NAND Flash with NFD0_ON_D16 = 0
31.5.4.5.1 Hardware Configuration
D[0..7]
16
17
8
18
9
CLE
ALE
NANDOE
NANDWE
(1)
(ANY PIO)
(ANY PIO)
3V3
R1
10K
R2
10K
U1
CLE
ALE
RE
WE
CE
7
R/B
19
WP
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
K9F2G08U0M
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
2 Gb
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
29
30
31
32
41
42
43
44
N.C
N.C
N.C
N.C
N.C
N.C
PRE
N.C
N.C
N.C
N.C
N.C
48
47
46
45
40
39
38
35
34
33
28
27
VCC
VCC
37
12
VSS
VSS
36
13
D0
D1
D2
D3
D4
D5
D6
D7
3V3
C2
100NF
C1
100NF
TSOP48 PACKAGE
(1)
The CE must be connected to NCS3 PIOD4 if the NAND Flash is used by the ROM code.
Note: The CE signal of the NAND Flash must be connected to PIOD4 (NCS3/NANDCS) if the user's system boots
out of NAND Flash.
31.5.4.5.2 Software Configuration
The following configuration has to be performed:
•
•
•
•
•
Set NFD0_ON_D16 = 0 in the SFR_CCFG_EBICSA register
Assign the EBI CS3 to the NAND Flash by setting the EBI_CS3A bit in the SFR_CCFG_EBICSA register
Reserve A21/A22 for ALE/CLE functions. Address and Command Latches are controlled respectively by setting
to 1 the address bits A21 and A22 during accesses.
Configure a PIO line as an input to manage the Ready/Busy signal.
Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, data
bus width and system bus frequency.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 496
SAM9X60
External Bus Interface (EBI)
31.5.4.6 8-bit NAND Flash with NFD0_ON_D16 = 1
31.5.4.6.1 Hardware Configuration
31.5.4.6.2 Software Configuration
The following configuration must be performed:
•
•
•
•
•
Set NFD0_ON_D16 = 1 in the SFR_CCFG_EBICSA register.
Assign the EBI CS3 to the NAND Flash by setting the EBI_CS3A bit in the SFR_CCFG_EBICSA register.
Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by
setting to 1 the address bits A21 and A22 during accesses.
Configure a PIO line as an input to manage the Ready/Busy signal.
Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, data
bus width and system bus frequency.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 497
SAM9X60
External Bus Interface (EBI)
31.5.4.7 NOR Flash on NCS0
31.5.4.7.1 Hardware Configuration
D[0..15]
A[1..22]
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
NRST
NWE
NCS0
NRD
3V3
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
15
10
9
12
11
14
13
26
28
U1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
RESET
WE
WP
VPP
CE
OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3V3
VCCQ
47
VCC
37
VSS
VSS
46
27
TSOP48 PACKAGE
C2
100NF
C1
100NF
31.5.4.7.2 Software Configuration
The default configuration for the Static Memory Controller, Byte Select mode, 16-bit data bus, Read/Write controlled
by Chip Select, allows boot on 16-bit non-volatile memory at slow clock.
For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on
Flash timings and system bus frequency.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 498
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.1
Description
The Multiport DDR-SDRAM Controller (MPDDRC) is a multiport memory controller. It comprises four slave AHB
interfaces. All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth
and minimize transaction latency due to DDR-SDRAM protocol.
The MPDDRC extends the memory capabilities of a chip by providing the interface to the external 16-bit DDRSDRAM device. The page size supports ranges from 2048 to 16384 rows and from 256 to 4096 columns. It supports
word (32-bit), half-word (16-bit), and byte (8-bit) accesses.
The MPDDRC supports a read or write burst length of eight locations. This enables the command and address bus to
anticipate the next command, thus reducing latency imposed by the DDR-SDRAM protocol and improving the DDRSDRAM bandwidth. Moreover, MPDDRC keeps track of the active row in each bank, thus maximizing DDR-SDRAM
performance, e.g., the application may be placed in one bank and data in other banks. To optimize performance,
avoid accessing different rows in the same bank. The MPDDRC supports a CAS latency of 2, 3 and optimizes the
read access depending on the frequency.
Self-refresh, Powerdown and Deep Powerdown modes minimize the consumption of the DDR-SDRAM device.
OCD (Off-chip Driver) and ODT (On-die Termination) modes are not supported.
32.2
Embedded Characteristics
•
•
•
•
•
•
•
•
•
•
•
•
Numerous Memory Devices Supported
– Low-power DDR1-SDRAM (LPDDR1)
– Low-cost LPDDR1 with 2 internal banks
– DDR2-SDRAM
Arbitration Policies: Round-Robin, On Request, Bandwidth, Quality of Service
Four Advanced High-Performance Bus (AHB) Interfaces, Management of all Accesses Maximizes Memory
Bandwidth and Minimizes Transaction Latency
Bus Transfer: word, half word, byte Access
Numerous Configurations Supported
– 2K, 4K, 8K, 16K row address memory parts
– DDR-SDRAM with two or four internal banks (low-power DDR1-SDRAM)
– DDR-SDRAM with four or eight internal banks (DDR2-SDRAM)
– DDR-SDRAM with 16-bit data path for system-oriented word access
– One chip select for SDRAM device (256-Mbyte address space)
Programming Facilities
– Multibank ping-pong access (up to four or eight banks opened at the same time = reduced average latency
of transactions)
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parameters (low-power DDR-SDRAM devices)
Energy-Saving Capabilities
– Self-refresh, Powerdown, Active Powerdown and Deep Powerdown modes supported
DDR-SDRAM Powerup Initialization by Software
CAS Latency of 2, 3 Supported
Reset Function Supported (DDR2-SDRAM)
Clock Frequency Change in Self-Refresh Mode Supported (Low-power DDR-SDRAM)
Autoprecharge Command Not Used
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 499
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
•
•
•
•
32.3
OCD (Off-chip Driver) Mode, ODT (On-die Termination), Are Not Supported
Abnormal Software Access and Sequencer Integrity Error Reports
Dynamic Scrambling with User Key (No Impact on Bandwidth)
Bus Monitor
Block Diagram
The MPDDRC is partitioned in two blocks (see figure below):
•
•
An Interconnect Matrix block that manages concurrent accesses on the AHB bus between four AHB masters
and integrates an arbiter
A DDR Controller that translates AHB requests (read/write) in the DDR-SDRAM protocol
Figure 32-1. Block Diagram
MultiPort DDR Controller
Interconnect Matrix
AHB Slave Interface 0
AHB Slave Interface 1
DDR Protocol Controller
Input
Stage
Power Management
DDRCK
Input
Stage
ras, cas,
we, cke
Memory Controller
Finite State Machine
Signal Management
Output
Stage
AHB Slave Interface 2
.
.
.
Input
Stage
clk/nclk
Arbiter
Addr, DQM
DQS
DDR Devices
Data
.
.
.
AHB Slave Interface n
Slave
Asynchronous Timing
Refresh Management
Input
Stage
odt
Configuration
Interface
32.4
Product Dependencies, Initialization Sequence
32.4.1
Low-power DDR1-SDRAM Initialization
The initialization sequence is generated by software.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 500
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
The low-power DDR1-SDRAM devices are initialized by the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Program the memory device type in the Memory Device register (MPDDRC_MD).
To comply with the LPDDR1 standard, DQS must be used in Single-ended mode. NDQS must be disabled in
the MPDDRC Configuration register (MPDDRC_CR).
Program the shift sampling value in the Read Data Path register (MPDDRC_RD_DATA_PATH).
Program the features of the low-power DDR1-SDRAM device in the MPDDRC Configuration register
(MPDDRC_CR) (number of columns, rows, banks, CAS latency and output drive strength) and in the Timing
Parameter 0 register/Timing Parameter 1 register (MPDDRC_TPR0/1) (asynchronous timing (TRC, TRAS,
etc.)).
Program Temperature Compensated Self-refresh (TCR), Partial Array Self-refresh (PASR) and Drive Strength
(DS) parameters in the Low-power register (MPDDRC_LPR).
A NOP command is issued to the low-power DDR1-SDRAM. Program the NOP command in the Mode register
(MPDDRC_MR). The application must configure the MODE field to 1 in the MPDDRC_MR. Read the
MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to
any low-power DDR1-SDRAM address to acknowledge this command. The clocks which drive the low-power
DDR1-SDRAM device are now enabled.
A pause of at least 200 μs must be observed before a signal toggle.
A NOP command is issued to the low-power DDR1-SDRAM. Program the NOP command in the
MPDDRC_MR. The application must configure the MODE field to 1 in the MPDDRC_MR. Read the
MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to
any low-power DDR1-SDRAM address to acknowledge this command. A calibration request is now made to
the I/O pad.
An All Banks Precharge command is issued to the low-power DDR1-SDRAM. Program All Banks Precharge
command in the MPDDRC_MR. The application must configure the MODE field to 2 in the MPDDRC_MR.
Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write
access to any low-power DDR1-SDRAM address to acknowledge this command.
Two autorefresh (CBR) cycles are provided. Program the Autorefresh command (CBR) in the MPDDRC_MR.
The application must configure the MODE field to 4 in the MPDDRC_MR. Read the MPDDRC_MR and add a
memory barrier assembler instruction just after the read. Perform a write access to any low-power DDR1SDRAM location twice to acknowledge these commands.
An Extended Mode Register Set (EMRS) cycle is issued to program the low-power DDR1-SDRAM parameters
(TCSR, PASR, DS). The application must configure the MODE field to 5 in the MPDDRC_MR. Read the
MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to
the SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 1
and BA[0] is set to 0. For example: with a 16-bit, 128-Mbit, low-power DDR1-SDRAM (12 rows, 9 columns, 4
banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00800000 In
the case of low-cost and low-density low-power DDR1-SDRAM (2 internal banks), the write address must be
chosen so that signal BA[0] is set to 1. BA[1] is not used.
Note: This address is given as an example only. The real address depends on implementation in the product.
A Mode Register Set (MRS) cycle is issued to program parameters of the low-power DDR1-SDRAM devices,
in particular CAS latency. The application must configure the MODE field to 3 in the MPDDRC_MR. Read the
MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to
the low-power DDR1-SDRAM to acknowledge this command. The write address must be chosen so that
signals BA[1:0] are set to 0. For example, the SDRAM write access should be done at the address:
BASE_ADDRESS_DDR.
The application must enter Normal mode, write a zero to the MODE field in the MPDDRC_MR. Read the
MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access at
any location in the low-power DDR1-SDRAM to acknowledge this command.
Write the refresh rate into the COUNT field in the Refresh Timer register (MPDDRC_RTR). To compute the
value, see MPDDRC Refresh Timer Register.
After initialization, the low-power DDR1-SDRAM device is fully functional.
32.4.2
DDR2-SDRAM Initialization
The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following
sequence:
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 501
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Program the memory device type in the Memory Device register (MPDDRC_MD).
Program the shift sampling value in the Read Data Path register (MPDDRC_RD_DATA_PATH).
Program features of the DDR2-SDRAM device in the Configuration register (MPDDRC_CR) (number of
columns, rows, banks, CAS latency and output driver impedance control) and in the Timing Parameter 0
register/Timing Parameter 1 register (MPDDRC_TPR0/1) (asynchronous timing: TRC, TRAS, etc.).
A NOP command is issued to the DDR2-SDRAM. Program the NOP command in the Mode register
(MPDDRC_MR). The application must configure the MODE field to 1 in the MPDDRC_MR. Read the
MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to
any DDR2-SDRAM address to acknowledge this command. The clocks which drive the DDR2-SDRAM device
are now enabled.
A pause of at least 200 μs must be observed before a signal toggle.
A NOP command is issued to the DDR2-SDRAM. Program the NOP command in the MPDDRC_MR. The
application must configure the MODE field to 1 in the MPDDRC_MR. Read the MPDDRC_MR and add a
memory barrier assembler instruction just after the read. Perform a write access to any DDR2-SDRAM
address to acknowledge this command. CKE is now driven high.
An All Banks Precharge command is issued to the DDR2-SDRAM. Program All Banks Precharge command in
the MPDDRC_MR. The application must configure the MODE field to 2 in the MPDDRC_MR. Read the
MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to
any DDR2-SDRAM address to acknowledge this command.
An Extended Mode Register Set (EMRS2) cycle is issued to choose between commercial or high temperature
operations. The application must configure the MODE field to 5 in the MPDDRC_MR. Read the MPDDRC_MR
and add a memory barrier assembler instruction just after the read. Perform a write access to the DDR2SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 1 and
signal BA[0] is set to 0. For example: with a 16-bit, 128-Mbit, DDR2-SDRAM (12 rows, 9 columns, 4 banks),
the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00800000.
Note: This address is given as an example only. The real address depends on implementation in the product.
An Extended Mode Register Set (EMRS3) cycle is issued to set the Extended Mode register to 0. The
application must configure the MODE field to 5 in the MPDDRC_MR. Read the MPDDRC_MR and add a
memory barrier assembler instruction just after the read. Perform a write access to the DDR2-SDRAM to
acknowledge this command. The write address must be chosen so that signal BA[1] is set to 1 and signal
BA[0] is set to 1. For example: with a 16-bit, 128-Mbit, DDR2-SDRAM (12 rows, 9 columns, 4 banks), the
DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00C00000
An Extended Mode Register Set (EMRS1) cycle is issued to enable DLL and to program D.I.C. (Output Driver
Impedance Control). The application must configure the MODE field to 5 in the MPDDRC_MR. Read the
MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to
the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is
set to 0 and signal BA[0] is set to 1. For example: with a 16-bit, 128-Mbit, DDR2-SDRAM (12 rows, 9 columns,
4 banks), the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR
+ 0x00400000.
An additional 200 cycles of clock are required for locking DLL.
Write a ‘1’ to the DLL bit (enable DLL reset) in the Configuration register (MPDDRC_CR).
A Mode Register Set (MRS) cycle is issued to reset DLL. The application must configure the MODE field to 3
in the MPDDRC_MR. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the
read. Perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be
chosen so that signals BA[1:0] are set to 0. For example, the SDRAM write access should be done at the
address: BASE_ADDRESS_DDR.
An All Banks Precharge command is issued to the DDR2-SDRAM. Program the All Banks Precharge
command in the MPDDRC_MR. The application must configure the MODE field to 2 in the MPDDRC_MR.
Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write
access to any DDR2-SDRAM address to acknowledge this command.
Two autorefresh (CBR) cycles are provided. Program the Autorefresh command (CBR) in the MPDDRC_MR.
The application must configure the MODE field to 4 in the MPDDRC_MR. Read the MPDDRC_MR and add a
memory barrier assembler instruction just after the read. Perform a write access to any DDR2-SDRAM
location twice to acknowledge these commands. TRFC must be checked between two autorefreshes (see
MPDDRC_TPR1).
Write a ‘0’ to the DLL bit (disable DLL reset) in the MPDDRC_CR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 502
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
17. A Mode Register Set (MRS) cycle is issued to program parameters of the DDR2-SDRAM device, in particular
CAS latency and to disable DLL reset. The application must configure the MODE field to 3 in the
MPDDRC_MR. Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read.
Perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be
chosen so that signals BA[1:0] are set to 0. For example: with a 16-bit, 128-Mbit, DDR2-SDRAM (12 rows, 9
columns, 4 banks) bank address, the SDRAM write access should be done at the address:
BASE_ADDRESS_DDR.
18. Configure the OCD field (default OCD calibration) to 7 in the MPDDRC_CR.
19. An Extended Mode Register Set (EMRS1) cycle is issued to the default OCD value. The application must
configure the MODE field to 5 in the MPDDRC_MR. Read the MPDDRC_MR and add a memory barrier
assembler instruction just after the read. Perform a write access to the DDR2-SDRAM to acknowledge this
command. The write address must be chosen so that signal BA[1] is set to 0 and signal BA[0] is set to 1. For
example: with a 16-bit, 128-Mbit, DDR2-SDRAM (12 rows, 9 columns, 4 banks), the DDR2-SDRAM write
access should be done at the address: BASE_ADDRESS_DDR + 0x00400000.
20. Configure the OCD field (exit OCD calibration mode) to 0 in the MPDDRC_CR.
21. An Extended Mode Register Set (EMRS1) cycle is issued to enable OCD exit. The application must configure
the MODE field to 5 in the MPDDRC_MR. Read the MPDDRC_MR and add a memory barrier assembler
instruction just after the read. Perform a write access to the DDR2-SDRAM to acknowledge this command.
The write address must be chosen so that signal BA[1] is set to 0 and signal BA[0] is set to 1. For example:
with a 16-bit, 128-Mbit, DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write
access should be done at the address: BASE_ADDRESS_DDR + 0x00400000.
22. A Normal Mode command is provided. Program the Normal mode in the MPDDRC_MR. Read the
MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to
any DDR2-SDRAM address to acknowledge this command.
23. Write the refresh rate into the COUNT field in the Refresh Timer register (MPDDRC_RTR). To compute the
value, see MPDDRC Refresh Timer Register.
After initialization, the DDR2-SDRAM devices are fully functional.
32.5
32.5.1
Functional Description
DDR-SDRAM Controller Write Cycle
The MPDDRC provides burst access or single access in Normal mode (MPDDRC_MR.MODE = 0). Whatever the
access type, the MPDDRC keeps track of the active row in each bank, thus maximizing performance.
The DDR-SDRAM device is programmed with a burst length (bl) equal to 8. This determines the length of a
sequential data input by the write command that is set to 8. The latency from write command to data input depends
on the memory type, as shown in the following table.
Table 32-1. CAS Write Latency
Memory Devices
CAS Write Latency (CWL)
Low-power DDR1-SDRAM
1
DDR2-SDRAM
2
To initiate a single access, the MPDDRC checks if the page access is already open. If row/bank addresses match
with the previous row/bank addresses, the controller generates a write command. If the bank addresses are not
identical or if bank addresses are identical but the row addresses are not identical, the controller generates a
precharge command, activates the new row and initiates a write command. To comply with DDR-SDRAM timing
parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD)
commands. As the burst length is set to 8, in case of single access, it has to stop the burst, otherwise seven invalid
values may be written. In case of the DDR-SDRAM device, the burst stop command is not supported for the burst
write operation. Thus, in order to interrupt the write operation, the DM (data mask) input signal must be set to 1 to
mask invalid data (see Figures Single Write Access, Row Closed, DDR-SDRAM Devices and Burst Write Access,
Row Closed, DDR-SDRAM Devices), and DQS must continue to toggle.
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
To initiate a burst access, the MPDDRC uses the transfer type signal provided by the master requesting the access. If
the next access is a sequential write access, writing to the DDR-SDRAM device is carried out. If the next access is a
write non-sequential access, then an automatic access break is inserted, the MPDDRC generates a precharge
command, activates the new row and initiates a write command. To comply with DDR-SDRAM timing parameters,
additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD) commands.
For the definition of timing parameters, see MPDDRC Timing Parameter 0 Register.
Write accesses to the DDR-SDRAM device are burst oriented and the burst length is programmed to 8. It determines
the maximum number of column locations that can be accessed for a given write command. When the write
command is issued, eight columns are selected. All accesses for that burst take place within these eight columns,
thus the burst wraps within these eight columns if a boundary is reached. These eight columns are selected by
addr[13:3]. addr[2:0] is used to select the starting location within the block.
In case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the
DDR-SDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but
since the burst length is programmed to 8, the next access is at 0x00. Since the boundary is reached, the burst is
wrapped. The MPDDRC takes this feature of the DDR-SDRAM device into account. In case of a transfer starting at
address 0x04/0x08/0x0C or starting at address 0x10/0x14/0x18/0x1C, two write commands are issued to avoid
wrapping when the boundary is reached. The last write command is subject to DM input logic level. If DM is
registered high, the corresponding data input is ignored and the write access is not done. This avoids additional
writing.
Figure 32-2. Single Write Access, Row Closed, DDR-SDRAM Devices
DDRCK
Row a
A[12:0]
COMMAND
BA[1:0]
NOP
PRCHG
NOP
Col a
ACT
NOP
WRITE
NOP
00
DQS[1:0]
DM[1:0]
3
DATA
0
Da
tRP = 2
3
Db
tRCD = 2
Figure 32-3. Single Write Access, Row Closed, DDR2-SDRAM Devices
DDRCK
Row a
A[12:0]
COMMAND
BA[1:0]
NOP
PRCHG
NOP
ACT
Col a
NOP
WRITE
NOP
00
DQS[1:0]
DM[1:0]
3
DATA
Da
tRP = 2
© 2020 Microchip Technology Inc.
0
3
Db
tRCD = 2
Complete Datasheet
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Figure 32-4. Burst Write Access, Row Closed, DDR-SDRAM Devices
DDRCK
A[12:0]
Row a
COMMAND
BA[1:0]
NOP
PRCHG
NOP
Col a
ACT
NOP
WRITE
NOP
0
DQS[1:0]
DM[1:0]
3
0
DATA
Da
tRP = 2
Db
Dc
Dd
3
De
Df
Dg
Dh
tRCD = 2
Figure 32-5. Burst Write Access, Row Closed, DDR2-SDRAM Devices
DDRCK
A[12:0]
Row a
COMMAND
BA[1:0]
NOP
PRCHG
NOP
Col a
ACT
NOP
WRITE
NOP
0
DQS[1:0]
DM[1:0]
3
0
DATA
Da
tRP = 2
Db
Dc
Dd
3
De
Df
Dg
Dh
tRCD = 2
A write command can be followed by a read command. To avoid breaking the current write burst, tWTR/tWRD (bl/2 + 2
= 6 cycles) should be met. See the figure below.
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Figure 32-6. Write Command Followed by a Read Command without Burst Write Interrupt, DDR-SDRAM
Devices
DDRCK
A[12:0]
col a
COMMAND
NOP
BA[1:0]
Col a
WRITE
NOP
READ
BST
NOP
0
DQS[1:0]
DM[1:0]
3
0
DATA
Da
3
Db Dc
Dd
De
Df
Dg
Dh
Da Db
tWRD = bl/2 + 2 = 8/2 + 2 = 6
tWR = 1
In case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle
prior to the read command to avoid writing invalid data. See the figure below.
Figure 32-7. Single Write Access Followed by a Read Access, DDR-SDRAM Devices
DDRCK
A[12:0]
COMMAND
BA[1:0]
Col a
Row a
NOP
PRCHG
NOP
ACT
NOP
WRITE
NOP
READ
BST
NOP
0
DQS[1:0]
DM[1:0]
3
0
DATA
3
Da Db
Db
Da
Data masked
Figure 32-8. Single Write Access Followed by a Read Access, DDR2-SDRAM Devices
DDRCK
A[12:0]
Row a
COMMAND
NOP PRCHG NOP
BA[1:0]
Col a
ACT
NOP
WRITE
NOP
READ
NOP
0
DQS[1:0]
DM[1:0]
3
DATA
0
Da
3
Da Db
Db
Data masked
tWTR
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.5.2
DDR-SDRAM Controller Read Cycle
The MPDDRC provides burst access or single access in Normal mode (MPDDRC_MR.MODE = 0). Whatever the
access type, the MPDDRC keeps track of the active row in each bank, thus maximizing performance of the
MPDDRC.
The DDR-SDRAM devices are programmed with a burst length equal to 8 which determines the length of a
sequential data output by the read command that is set to 8. The latency from read command to data output depends
on the memory type, as shown in the following table. This value is programmed during the initialization phase (see
Product Dependencies, Initialization Sequence).
Table 32-2. CAS Read Latency
Memory Devices
CAS Read Latency
Low-power DDR1-SDRAM
2/3
DDR2-SDRAM
3
To initiate a single access, the MPDDRC checks if the page access is already open. If row/bank addresses match
with the previous row/bank addresses, the controller generates a read command. If the bank addresses are not
identical or if bank addresses are identical but the row addresses are not identical, the controller generates a
precharge command, activates the new row and initiates a read command. To comply with DDR-SDRAM timing
parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/read (tRCD)
commands. After a read command, additional wait states are generated to comply with CAS latency. The MPDDRC
supports a CAS latency delay of 2, 3 clock cycles. As the burst length is set to 8, in case of a single access or a burst
access inferior to 8 data requests, it has to stop the burst, otherwise an additional seven or X values could be read.
The Burst Stop command (BST) is used to stop output during a burst read. If the DDR2-SDRAM Burst Stop
command is not supported by the JEDEC standard, in a single read access, an additional seven unwanted data will
be read.
To initiate a burst access, the MPDDRC checks the transfer type signal. If the next accesses are sequential read
accesses, reading to the SDRAM device is carried out. If the next access is a read non-sequential access, then an
automatic page break can be inserted. If the bank addresses are not identical or if bank addresses are identical but
the row addresses are not identical, the controller generates a precharge command, activates the new row and
initiates a read command. If page access is already open, a read command is generated.
To comply with DDR-SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP)
commands and active/read (tRCD) commands. The MPDDRC supports a CAS latency delay of 2, 3 clock cycles.
During this delay, the controller uses internal signals to anticipate the next access and improve the performance of
the controller. Depending on the latency, the MPDDRC anticipates 2, 3 read accesses. In case of burst of specified
length, accesses are not anticipated, but if the burst is broken (border, Busy mode, etc.), the next access is treated as
an incrementing burst of unspecified length, and depending on the latency, the MPDDRC anticipates 2, 3 read
accesses.
For the definition of timing parameters, see MPDDRC Configuration Register.
Read accesses to the DDR-SDRAM are burst oriented and the burst length is programmed to 8. The burst length
determines the maximum number of column locations that can be accessed for a given read command. When the
read command is issued, eight columns are selected. All accesses for that burst take place within these eight
columns, meaning that the burst wraps within these eight columns if the boundary is reached. These eight columns
are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block.
In case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the
DDR-SDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but
since the burst length is programmed to 8, the next access is 0x00. Since the boundary is reached, the burst wraps.
The MPDDRC takes into account this feature of the SDRAM device. In case of the DDR-SDRAM device, transfers
start at address 0x04/0x08/0x0C. Two read commands are issued to avoid wrapping when the boundary is reached.
The last read command may generate additional reading (1 read cmd = 4 DDR words).
To avoid additional reading, it is possible to use the burst stop command to truncate the read burst and to decrease
power consumption. The DDR2-SDRAM devices do not support the burst stop command.
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AHB Multiport DDR-SDRAM Controller (MPDDRC)
Figure 32-9. Single Read Access, Row Closed, Latency = 2, DDR-SDRAM Devices
DDRCK
A[12:0]
Row a
COMMAND
NOP
BA[1:0]
0
DM[3:0]
3
PRCHG
NOP
ACT
col a
NOP
READ
BST
D[31:0]
NOP
DaDb
tRP
tRCD
Latency = 2
Figure 32-10. Single Read Access, Row Closed, Latency = 3, DDR2-SDRAM Devices
DDRCK
A[12:0]
COMMAND
BA[1:0]
NOP
PRCHG
NOP
Row a
Col a
ACT
NOP
READ
0
DQS[1]
DQS[0]
DM[1:0]
3
D[15:0]
Da
tRP
tRCD
Db
Latency = 3
Figure 32-11. Burst Read Access, Latency = 2, DDR-SDRAM Devices
DDRCKN
DDRCK
A[12:0]
COMMAND
BA[1:0]
Col a
NOP
READ
NOP
0
DQS[1:0]
DM[1:0]
3
D[15:0]
Da
Db
Dc
Dd
De
Df
Dg
Dh
Latency = 2
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Figure 32-12. Burst Read Access, Latency = 3, DDR2-SDRAM Devices
DDRCKN
DDRCK
A[12:0]
COMMAND
BA[1:0]
Col a
NOP
READ
NOP
0
DQS[1:0]
DM[1:0]
3
D[15:0]
Da
Db
Dc
Dd
De
Df
Dg
Dh
Latency = 3
32.5.3
Refresh (Autorefresh Command)
An Autorefresh command is used to refresh the external SDRAM devices. Refresh addresses are generated
internally by the DDR-SDRAM device and incremented automatically after each autorefresh. The MPDDRC
generates these autorefresh commands periodically. A timer is loaded in the MPDDRC_RTR with the value which
indicates the number of clock cycles between refresh cycles (see MPDDRC Refresh Timer Register). When the
MPDDRC initiates a refresh of the DDR-SDRAM device, internal memory accesses are not delayed. However, if the
CPU tries to access the DDR-SDRAM device, the slave indicates that the device is busy. A refresh request does not
interrupt a burst transfer in progress.
32.5.4
Power Management
32.5.4.1 Self-refresh Mode
This mode is activated by configuring the Low-power Command bit (LPCB) to 1 in the MPDDRC Low-Power Register
(MPDDRC_LPR).
Self-refresh mode is used in Powerdown mode, i.e., when no access to the DDR-SDRAM device is possible. In this
case, power consumption is very low. In Self-refresh mode, the DDR-SDRAM device retains data without external
clocking and provides its own internal clocking, thus performing its own autorefresh cycles. During the self-refresh
period, CKE is driven low. As soon as the DDR-SDRAM device is selected, the MPDDRC provides a sequence of
commands and exits Self-refresh mode.
The MPDDRC reenables Self-refresh mode as soon as the DDR-SDRAM device is not selected. It is possible to
define when Self-refresh mode is to be enabled by configuring the TIMEOUT field in the MPDDRC_LPR:
0: Self-refresh mode is enabled as soon as the DDR-SDRAM device is not selected.
1: Self-refresh mode is enabled 64 clock cycles after completion of the last access.
2: Self-refresh mode is enabled 128 clock cycles after completion of the last access.
This controller also interfaces the low-power DDR-SDRAM. To optimize power consumption, the Low Power DDR
SDRAM provides programmable self-refresh options comprised of Partial Array Self Refresh (full, half, quarter and
1/8 and 1/16 array).
Disabled banks are not refreshed in Self-refresh mode. This feature permits to reduce the self-refresh current. In
case of low-power DDR1-SDRAM, the Extended Mode register controls this feature. It includes Temperature
Compensated Self-refresh (TSCR) and Partial Array Self-refresh (PASR) parameters and the drive strength (DS)
(see MPDDRC Low-Power Register). These parameters are set during the initialization phase. After initialization, as
soon as the PASR/DS/TCSR fields are modified, the memory device Extended Mode register are automatically
accessed. Thus if MPDDRC does not share an external bus with another controller, PASR/DS/TCSR bits are updated
before entering Self-refresh mode or during a refresh command. If MPDDRC does share an external bus with another
controller, PASR/DS/TCSR bits are also updated during a pending read or write access. This type of update depends
on the UPD_MR bit (see MPDDRC Low-Power Register).
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
The low-power DDR1-SDRAM must remain in Self-refresh mode during the minimum of TRFC periods (see
MPDDRC Timing Parameter 1 Register), and may remain in Self-refresh mode for an indefinite period.
The DDR2-SDRAM must remain in Self-refresh mode during the minimum of tCKE periods (see the memory device
datasheet), and may remain in Self-refresh mode for an indefinite period.
Figure 32-13. Self-refresh Mode Entry, TIMEOUT = 0
DDRCK
A[12:0]
COMMAND
NOP READ
BST
NOP
PRCHG
NOP
ARFSH
NOP
CKE
BA[1:0]
0
DQS[0:1]
DM[1:0]
3
D[15:0]
Da
Db
Enter Self-refresh
Mode
tRP
Figure 32-14. Self-refresh Mode Entry, TIMEOUT = 1 or 2
DDRCK
A[12:0]
COMMAND
NOP READ
BST
NOP
PRCHG
NOP
ARFSH NOP
CKE
BA[1:0]
0
DQS[1:0]
DM[1:0]
3
D[15:0]
Da
Db
64 or 128
Wait states
Enter Self-refresh
Mode
tRP
Figure 32-15. Self-refresh Mode Exit
DDRCK
A[12:0]
COMMAND
NOP
VALID
NOP
CKE
BA[1:0]
0
DQS[1:0]
DM[1:0]
3
D[15:0]
Exit Self-refresh Mode
Clock must be stable
before exiting self-refresh mode
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tXSR
Complete Datasheet
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.5.4.2 Powerdown Mode
This mode is activated by configuring the Low-power Command bit (LPCB) to 2 in the MPDDRC Low-Power Register
(MPDDRC_LPR).
Powerdown mode is used when no access to the DDR-SDRAM device is possible. In this mode, power consumption
is greater than in Self-refresh mode. This state is similar to Normal mode (no Low-power mode/no Self-refresh
mode), but the CKE pin is low and the input and output buffers are deactivated as soon the DDR-SDRAM device is
no longer accessible. In contrast to Self-refresh mode, the DDR-SDRAM device cannot remain in Low-power mode
longer than one refresh period (64 ms/32 ms). As no autorefresh operations are performed in this mode, the
MPDDRC carries out the refresh operation. For the low-power DDR-SDRAM devices, a NOP command must be
generated for a minimum period defined in the TXP field of the Timing Parameter 1 register (MPDDRC_TPR1). For
DDR-SDRAM devices, a NOP command must be generated for a minimum period defined in the TXP field of
MPDDRC_TPR1 (see MPDDRC Timing Parameter 1 Register) and in the TXARD and TXARDS fields of
MPDDRC_TPR2 (see MPDDRC Timing Parameter 2 Register) for DDR2_SDRAM devices. In addition, low-power
DDR-SDRAM and DDR-SDRAM must remain in Powerdown mode for a minimum period corresponding to tCKE, tPD,
etc. (refer to the memory device datasheet).
The exit procedure is faster than in Self-refresh mode. See the following figure. The MPDDRC returns to Powerdown
mode as soon as the DDR-SDRAM device is not selected. It is possible to define when Powerdown mode is enabled
by configuring the TIMEOUT field in the MPDDRC_LPR:
0: Powerdown mode is enabled as soon as the DDR-SDRAM device is not selected.
1: Powerdown mode is enabled 64 clock cycles after completion of the last access.
2: Powerdown mode is enabled 128 clock cycles after completion of the last access.
Figure 32-16. Powerdown Entry/Exit, TIMEOUT = 0
DDRCK
A[12:0]
COMMAND
READ
BST
NOP
READ
CKE
BA[1:0]
0
DQS[1:0]
DM[1:0]
3
D[15:0]
Da
Db
Enter Powerdown Mode
Exit Powerdown Mode
32.5.4.3 Deep Powerdown Mode
The Deep Powerdown mode is a feature of low-power DDR-SDRAM. When this mode is activated, all internal voltage
generators inside the device are stopped and all data is lost.
Deep Powerdown mode is activated by configuring the Low-power Command bit (LPCB) to 3 in the MPDDRC LowPower Register (MPDDRC_LPR). When this mode is enabled, the MPDDRC leaves Normal mode
(MPDDRC_MR.MODE = 0) and the controller is frozen. The clock can be stopped during Deep Powerdown mode by
setting the CLK_FR field to 1.
Before enabling this mode, the user must make sure there is no access in progress. To exit Deep Powerdown mode,
the Low-power Command bit (LPCB) and Clock Frozen bit (CLK_FR) must be 0 and the initialization sequence must
be generated by software. See Low-power DDR1-SDRAM Initialization.
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AHB Multiport DDR-SDRAM Controller (MPDDRC)
Figure 32-17. Deep Powerdown Mode Entry
DDRCK
A[12:0]
COMMAND
NOP READ
BST
NOP
PRCHG
NOP
DEEPOWER
NOP
CKE
BA[1:0]
0
DQS[1:0]
DM[1:0]
3
D[15:0]
Da
Db
tRP
Enter Deep
Powerdown
Mode
32.5.4.4 Change Frequency During Self-Refresh Mode with Low-power DDR-SDRAM Devices
To change frequency, Self-refresh mode must be activated. This is done by configuring the Low-power Command bit
(LPCB) to 1 and writing a ‘1’ to the Change Frequency Command bit (CHG_FR) in the Low-power register
(MPDDRC_LPR).
Once the low-power DDR-SDRAM is in Self-refresh mode, the user must make sure there is no access in progress.
Then, the user can change the clock frequency. The device input clock frequency changes only within minimum and
maximum operating frequencies as specified by the low-power DDR-SDRAM providers. Once the input clock
frequency is changed, new stable clocks must be provided to the device before exiting from Self-refresh mode.
To exit from Self-refresh mode, the DDR-SDRAM device must be selected. The MPDDRC provides a sequence of
commands and exits Self-refresh mode.
During a change frequency procedure, the Change Frequency Command bit (CHG_FR) is set to 0 automatically.
It is not possible to change the frequency with DDR2-SDRAM devices.
Before changing frequency, make sure the processor clock (PCK) value is twice the system bus clock (MCK) value.
32.5.4.5 Reset Mode
The Reset mode is a feature of DDR2-SDRAM. This mode is activated by configuring the Low-power Command bit
(LPCB) to 3 and writing a ‘1’ to the Clock Frozen Command bit (CLK_FR) in the Low-power register
(MPDDRC_LPR).
When this mode is enabled, the MPDDRC leaves Normal mode (MPDDRC_MR.MODE = 0) and the controller is
frozen. Before enabling this mode, the user must make sure there is no access in progress.
To exit Reset mode, the Low-power Command bit (LPCB) must be configured to 0, the Clock Frozen Command bit
(CLK_FR) must be written to ‘0’ and the initialization sequence must be generated by software (see DDR2-SDRAM
Initialization).
32.5.5
Multiport Functionality
The DDR-SDRAM protocol imposes a check of timings prior to performing a read or a write access, thus decreasing
system performance. An access to DDR-SDRAM is performed if banks and rows are open (or active). To activate a
row in a particular bank, the last open row must be deactivated and a new row must be open. Two DDR-SDRAM
commands must be performed to open a bank: Precharge command and Activate command with respect to TRP
timing. Before performing a read or write command, TRCD timing must be checked.
This operation generates a significant bandwidth loss (see the following figure).
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Figure 32-18. TRP and TRCD Timings
DDRCK
A[12:0]
COMMAND
NOP
BA[1:0]
PRCHG
NOP
ACT
NOP
READ
BST
NOP
0
DQS[1:0]
DM1:0]
3
D[15:0]
Da
tRP
tRCD
Db
Latency = 2
4 cycles before performing a read command
The multiport controller is designed to mask these timings and thus improve the system bandwidth.
The MPDDRC is a multiport controller whereby four masters can simultaneously reach the controller. This feature
improves the bandwidth of the system because it can detect four requests on the AHB slave inputs and thus
anticipate the commands that follow, Precharge command and Activate command in bank X during the current
access in bank Y. This masks tRP and tRCD timings (see the following figure). In the best case, all accesses are done
as if the banks and rows were already open. The best condition is met when the four masters work in different banks.
In the case of four simultaneous read accesses, when the four or eight banks and associated rows are open, the
controller reads with a continuous flow and masks the CAS latency for each access. To allow a continuous flow, the
read command must be set at 2, 3 cycles (CAS latency) before the end of the current access. The arbitration scheme
must be changed since the round-robin arbitration cannot be respected. If the controller anticipates a read access,
and thus a master with a high priority arises before the end of the current access, then this master will not be
serviced.
Figure 32-19. Anticipate Precharge/Activate Command in Bank 2 during Read Access in Bank 1
DDRCK
A[12:0]
COMMAND
BA[1:0]
NOP
0
READ
PRECH
1
NOP
ACT
READ
2
NOP
1
DQS[1:0]
DM1:0]
3
D[15:0]
Da
Db
Dc
Dd
De
Df
Dg
Dh
Di
Dj
Dk
Dl
tRP
Anticipate command, Precharge/Active Bank 2
Read Access in Bank 1
MPDDRC is a multiport controller that embeds three arbitration mechanisms based on round-robin arbitration which
allows to share the external device between different masters when two or more masters try to access the DDRSDRAM device at the same time.
The three arbitration types are round-robin arbitration and two weighted round-robin arbitrations. For weighted roundrobin arbitrations, the priority can be given either depending on the number of requests or words per port, or
depending on the required bandwidth per port. The type of arbitration can be chosen by setting the ARB field in the
Configuration Arbiter register (MPDDRC_CONF_ARBITER) (see MPDDRC Configuration Arbiter Register).
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Complete Datasheet
DS60001579C-page 513
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.5.5.1 Round-robin Arbitration
Round-robin arbitration is used when the ARB field is set to 0 (see MPDDRC Configuration Arbiter Register). This
algorithm dispatches the requests from different masters to the DDR-SDRAM device in a round-robin manner. If two
or more master requests arise at the same time, the master with the lowest number is serviced first, then the others
are serviced in a round-robin manner.
To avoid burst breaking and to provide the maximum throughput for the DDR-SDRAM device, arbitration must only
take place during the following cycles:
1.
2.
3.
4.
Idle cycles: when no master is connected to the DDR-SDRAM device.
Single cycles: when a slave is currently doing a single access.
End of Burst cycles: when the current cycle is the last cycle of a burst transfer:
– For bursts of defined length, predicted end of burst matches the size of the transfer.
– For bursts of undefined length, predicted end of burst is generated at the end of each four-beat boundary
inside the INCR transfer.
Anticipated Access: when an anticipated read access is done while the current access is not complete, the
arbitration scheme can be changed if the anticipated access is not the next access serviced by the arbitration
scheme.
32.5.5.2 Request-word Weighted Round-robin Arbitration
In request-word weighted round-robin arbitration, the weight is the number of requests or the number of words per
port.
This arbitration scheme is enabled by configuring the ARB field to 1 (see MPDDRC Configuration Arbiter Register).
This algorithm grants a port for X(1) consecutive first transfer (htrans = NON SEQUENTIAL) of a burst or X single
transfer, or for X word transfers. It is possible to choose between an arbitration scheme by request or by word per
port by setting the RQ_WD_Px field (see MPDDRC Configuration Arbiter Register).
Note: 1. X is an integer value provided by some master modules to the arbiter.
It is also possible for the user to provide the number of requests or words (by overwriting the information provided by
a master) on master basis by configuring the MA_PR_Px field. Depending on the application, it is possible to reduce
or increase the number of these requests or words by configuring the NRD_NWD_BDW_Px fields (see MPDDRC
Configuration Arbiter Register).
The TIMEOUT_Px field defines the delay between two accesses on the same port in number of cycles before
rearbitrating the access to another port. This field allows to avoid a timeout on the system because some masters
have the particularity to add idle cycles between two consecutive accesses (see MPDDRC Configuration Arbiter
Register).
This algorithm dispatches the requests from different masters to the DDR-SDRAM device in a round-robin manner. If
two or more master requests arise at the same time, the master with the lowest number is serviced first, then the
others are serviced in a round-robin manner when the number of requests or words is reached or when the timeout
value is reached.
To avoid burst breaking and to provide the maximum throughput for the DDR-SDRAM device, arbitration must only
take place during the following cycles:
1.
2.
Timeout is reached: the delay between two accesses is equal to TIMEOUT_Px.
Number of requests or words is reached: when the current cycle is the last cycle of a transfer.
32.5.5.3 Bandwidth Weighted Round-robin Arbitration
In bandwidth weighted round-robin arbitration, a minimum bandwidth is guaranteed per port.
This arbitration scheme is enabled when the ARB field is set to 2 (see MPDDRC Configuration Arbiter Register).
This algorithm grants to each port a percentage of the bandwidth. The NRD_NWD_BDW_Px field defines the
percentage allocated to each port.
The percentage of the bandwidth is programmed with the NRD_NWD_BDW_Px fields (see MPDDRC Configuration
Arbiter Register).
The TIMEOUT_Px field defines the delay between two accesses on the same port in number of cycles rearbitrating
the access to another port. This field allows to avoid a timeout on the system because some masters have the
particularity to add idle cycles between two consecutive accesses (see MPDDRC Configuration Arbiter Register).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 514
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
This algorithm dispatches the requests from different masters to the DDR-SDRAM device in a round-robin manner. If
two or more master requests arise at the same time, the master with the lowest number is serviced first, then the
others are serviced in a round-robin manner when the allocated bandwidth is reached or when the timeout value is
reached.
The BDW_BURST field allows to arbitrate either when the current master reaches exactly the programmed
bandwidth, or when the current master reaches exactly the programmed bandwidth and the current access is ended
(see MPDDRC Configuration Arbiter Register).
To provide the maximum throughput for the DDR-SDRAM device, arbitration must only take place during the following
cycles:
1.
2.
3.
Timeout is reached: the delay between two accesses is equal to TIMEOUT_Px.
Allocated Bandwidth is reached although the current cycle is not ended.
Allocated Bandwidth is reached and the current cycle is the last cycle of a transfer.
32.5.5.4 Quality Of Service Arbitration
This arbitration scheme is enabled when the ARB field is set to 3 (see MPDDRC Configuration Arbiter Register).
The arbitration scheme is organized in priority pools corresponding each to an access criticality class as shown in the
corresponding Latency Quality of Service column in the following table. When the Latency Quality of Service is
enabled for a master-slave pair through the Bus Matrix (refer to AHB Bus Matrix section), the priority pool number to
use for arbitration at the slave port is determined from the master. When the Latency Quality of Service is disabled, it
is determined through the Bus Matrix user interface. Refer to “Bus Matrix Priority Registers A For Slaves” in AHB Bus
Matrix section.
Table 32-3. Arbitration Priority Pools
Priority pool
Latency Quality of Service
3
Latency Critical
2
Latency Sensitive
1
Bandwidth Sensitive
0
Background Transfers
Round-robin priority is used in the highest and lowest priority pools 3 and 0, whereas fixed level priority is used
between priority pools and in the intermediate priority pools 2 and 1.
For each slave, each master is assigned to one of the slave priority pools based on the Latency Quality of Service
inputs or to the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS, refer to AHB Bus
Matrix section). When evaluating master requests, this priority pool level always takes precedence.
After reset, most of the masters belong to the lowest priority pool (MxPR = 0, Background Transfer) and are therefore
granted bus access in a true round-robin order.
The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than one
master belong to this pool, those masters are granted bus access in a biased round-robin manner which enables tight
and deterministic maximum access latency from AHB bus requests. In the worst case, any currently occurring highpriority master request is granted after the current bus master access has ended and any other high priority pool
master requests have been granted once each.
The lowest priority pool shares the remaining bus bandwidth between AHB masters.
Intermediate priority pools enable fine priority tuning. Typically, a latency-sensitive master or a bandwidth-sensitive
master uses such a priority level. The higher the priority level (MxPR value, refer to AHB Bus Matrix section), the
higher the master priority.
All combinations of MxPR values are allowed for all masters and slaves. For example, some masters might be
assigned the highest priority pool (round-robin), and remaining masters the lowest priority pool (round-robin), with no
master for intermediate fixed priority levels.
Some masters, such as LCD or DMA, drive a signal named HNBREQ on the system bus to indicate the number of
transfers to be performed. When the field MPDDRC_CONF_ARBITER.KEEP_LAYER is set to 1, the master with the
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Complete Datasheet
DS60001579C-page 515
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
highest LQOS value and a HNBREQ value different from 0 continues to be granted, even during a last data phase
with IDLE cycles.
32.5.6
Scrambling/Unscrambling Function
The external data bus can be scrambled in order to prevent intellectual property data located in off-chip memories
from being easily recovered by analyzing data at the package pin level of either the microcontroller or the memory
device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling method depends on two user-configurable key registers, KEY1 in the “MPDDRC OCMS KEY1
Register” and KEY2 in the “MPDDRC OCMS KEY2 Register”. These key registers are only accessible in Write mode.
The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory.
Any data scrambled with a given key cannot be recovered if the key is lost.
The scrambling/unscrambling function can be enabled or disabled by programming the “MPDDRC OCMS Register”.
32.5.7
Clearing Scrambling Keys on Tamper Event
On tamper detection event on WKUP pins, it is possible to perform an immediate clear of the scrambling keys
(MPDDRC_OCMS_KEY1 and MPDDRC_OCMS_KEY2) if bit MPDDRC_OCMS.TAMPCLR = 1.
32.5.8
Register Write Protection
To prevent any single software error from corrupting MPDDRC behavior, certain registers in the address space can
be write-protected by setting the WPEN bit in the MPDDRC Write Protection Mode Register (MPDDRC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the MPDDRC Write Protection Status
Register (MPDDRC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading MPDDRC_WPSR.
The following registers are write-protected when the bit WPEN is set:
•
•
•
•
•
•
•
•
•
MPDDRC Mode Register
MPDDRC Refresh Timer Register
MPDDRC Configuration Register
MPDDRC Timing Parameter 0 Register
MPDDRC Timing Parameter 1 Register
MPDDRC Memory Device Register
MPDDRC OCMS Register
MPDDRC OCMS KEY1 Register
MPDDRC OCMS KEY2 Register
The following registers are write-protected when the bit WPITEN is set:
•
•
32.5.9
MPDDRC Interrupt Enable Register
MPDDRC Interrupt Disable Register
Monitor
The MPDDRC embeds a monitor which collects bus transaction information from four MPDDRC ports. This
information, such as accumulated latency (MPDDRC_MINFOx (TOTAL_LATENCY) or number of transfers
(MPDDRC_MINFOx (NB_TRANSFERS), can be used to calculate the average latency for each port.
Configuration registers (MPDDRRC_MCFGR, MPDDRRC_MADDRx) are used to define the type of transaction
collected (read, write or read/write) and the address range snooped.
By default, the monitor is enabled and the address range is 0x3FFFFFFF (address high = 0xFFFF) to 0x20000000
(address low = 0000).
Monitor use example:
1.
Clear the configuration register: write 0x00000000 in MPDDRRC_MCFGR.
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Complete Datasheet
DS60001579C-page 516
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
2.
3.
4.
5.
6.
7.
8.
Enable the monitor: write 0x00000001 in MPDDRRC_MCFGR.
Reset the monitor: write 0x00000003 in MPDDRRC_MCFGR.
Enable the monitor: write 0x00000001 in MPDDRRC_MCFGR.
Start profiling: write 0x00000011 in MPDDRRC_MCFGR.
Profiling is launched. An event can be used to stop monitoring.
Stop profiling: write 0x00000001 in MPDDRRC_MCFGR.
To know the number of tranfers per port, write 0x00000801 in MPDDRRC_MCFGR and read
MPDDRC_MINFOx (NB_TRANSFERS).
32.5.10 Security and Safety Analysis and Reports
Several types of checks are performed when the MPDDRC is accessing the memory device.
The peripheral clock of the MPDDRC is monitored by specific circuitry to detect abnormal waveforms on the internal
clock net that may affect the behavior of the MPDDRC. Corruption on the triggering edge of the clock or a pulse with
a minimum duration may be identified. If the flag MPDDRC_WPSR.CGD is set, an abnormal condition occurred on
the peripheral clock. This flag is not set under normal operating conditions.
The internal sequencer of the MPDDRC is also monitored and if an abnormal state is detected, the flag
MPDDRC_WPSR.SEQE is set. This flag is not set under normal operating conditions.
If the flag MPDDRC_WPSR.CGD = 1, a clock glitch has been detected. This flag is not set under normal operating
conditions.
The software accesses to the MPDDRC are monitored and if an incorrect access is performed, the flag
MPDDRC_WPSR.SWE is set. The type of incorrect/abnormal software access is reported in the
MPDDRC_WPSR.SWETYP field (see MPDDRC Write Protection Status Register (MPDDRC_WPSR) for details),
e.g., writing a new configuration (MPDDRC_CR, MPDDRC_TPR0/1/2, MPDDRC_MD, MPDDRC_OCMS,
MPDDRC_OCMS_KEY1/2) after the initialization of the MPDDRC (i.e., if MPDDRC_TR.COUNT > 0) is an error.
MPDDRC_WPSR.ECLASS is an indicator reporting the criticality of the SWETYP report.
The flags CGD, SEQE, SWE and WPVS are automatically cleared when MPDDRC_WPSR is read.
If one of these flags is set, the flag MPDDRC_ISR.SECE is set and can trigger an interrupt if the
MPDDRC_IMR.SECE bit is ‘1’. SECE is cleared by reading MPDDRC_ISR.
The MPDDRC embeds an automatic periodic check of an address of the memory device. This function can be
enabled by writing a 1 to the MPDDRC_SAFETY.EN bit. The address to be checked can be configured by writing the
field MPDDRC_SAFETY.ADDRESS. When MPDDRC_SAFETY.EN = 1, the MPDDRC performs read and write
accesses with specific, predetermined, data patterns to the configured address, with no impact for the application
software,
32.6
Software Interface/SDRAM Organization, Address Mapping
The DDR-SDRAM address space is organized into banks, rows and columns. The MPDDRC maps different memory
types depending on values set in the Configuration register (MPDDRC_CR) (see MPDDRC Configuration Register).
The tables that follow illustrate the relation between CPU addresses and columns, rows and banks addresses for 16bit memory data bus widths.
The MPDDRC supports address mapping in Linear mode.
Sequential mode is a method for address mapping where banks alternate at each last DDR-SDRAM page of the
current bank.
Interleaved mode is a method for address mapping where banks alternate at each DDR-SDRAM end of page of the
current bank.
The MPDDRC makes the DDR-SDRAM device access protocol transparent to the user. The tables that follow
illustrate the DDR-SDRAM device memory mapping seen by the user in correlation with the device structure. Various
configurations are illustrated.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 517
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.6.1
DDR-SDRAM Address Mapping for 16-bit Memory Data Bus Width
Table 32-4. Sequential Mapping for DDR-SDRAM Configuration, 2K Rows, 256/512/1024/2048/4096 Columns,
4 Banks
CPU Address Line
27 26 25 24
23
22
21
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[10:0]
Column[7:0]
Row[10:0]
Column[8:0]
Row[10:0]
Column[9:0]
Row[10:0]
M0
M0
Column[10:0]
Row[10:0]
M0
M0
Column[11:0]
M0
Table 32-5. Interleaved Mapping for DDR-SDRAM Configuration, 2K Rows, 256/512/1024/2048/4096 Columns,
4 Banks
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
12
11
Row[10:0]
Bk[1:0]
Row[10:0]
Bk[1:0]
Bk[1:0]
Row[10:0]
9
Bk[1:0]
Row[10:0]
Row[10:0]
10
Bk[1:0]
8 7 6 5 4 3 2 1 0
Column[7:0]
Column[8:0]
Column[9:0]
M0
M0
M0
Column[10:0]
M0
Column[11:0]
M0
Table 32-6. Sequential Mapping for DDR-SDRAM Configuration: 4K Rows, 256/512/1024/2048/4096 Columns,
4 Banks
CPU Address Line
27 26 25
24
23
22
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[11:0]
Column[7:0]
Row[11:0]
Column[8:0]
Row[11:0]
Column[9:0]
Row[11:0]
M0
M0
Column[10:0]
Row[11:0]
M0
M0
Column[11:0]
M0
Table 32-7. Interleaved Mapping for DDR-SDRAM Configuration: 4K Rows, 256/512/1024/2048/4096 Columns,
4 Banks
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
12
11
Row[11:0]
Row[11:0]
© 2020 Microchip Technology Inc.
9
Bk[1:0]
Row[11:0]
Row[11:0]
10
Bk[1:0]
Bk[1:0]
Bk[1:0]
Complete Datasheet
8 7 6 5 4 3 2 1 0
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
M0
M0
M0
M0
DS60001579C-page 518
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
...........continued
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
Row[11:0]
Bk[1:0]
12
11
10
9
8 7 6 5 4 3 2 1 0
Column[11:0]
M0
Table 32-8. Sequential Mapping for DDR-SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns,
4 Banks
CPU Address Line
27
26
25
24
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[12:0]
Column[8:0]
Row[12:0]
Column[9:0]
Row[12:0]
M0
Column[10:0]
Row[12:0]
M0
M0
Column[11:0]
M0
Table 32-9. Interleaved Mapping for DDR-SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns,
4 Banks
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14
13
12
Row[12:0]
Bk[1:0]
Bk[1:0]
Row[12:0]
10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Row[12:0]
Row[12:0]
11
Bk[1:0]
Column[8:0]
Column[9:0]
M0
M0
Column[10:0]
M0
Column[11:0]
M0
Table 32-10. Sequential Mapping for DDR-SDRAM Configuration: 16K Rows, 512/1024/2048 Columns,
4 Banks
CPU Address Line
27
26
25
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[13:0]
Column[8:0]
Row[13:0]
Column[9:0]
Row[13:0]
M0
M0
Column[10:0]
M0
Table 32-11. Interleaved Mapping for DDR-SDRAM Configuration: 16K Rows, 512/1024/2048 Columns,
4 Banks
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
12
Row[13:0]
Row[13:0]
Row[13:0]
© 2020 Microchip Technology Inc.
11
10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Bk[1:0]
Bk[1:0]
Complete Datasheet
Column[8:0]
Column[9:0]
Column[10:0]
M0
M0
M0
DS60001579C-page 519
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Table 32-12. Sequential Mapping for DDR-SDRAM Configuration: 8K Rows, 1024 Columns, 8 Banks
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[2:0]
Row[12:0]
Column[9:0]
M0
Table 32-13. Interleaved Mapping for DDR-SDRAM Configuration: 8K Rows, 1024 Columns, 8 Banks
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[12:0]
Bk[2:0]
Column[9:0]
M0
Table 32-14. Sequential Mapping for DDR-SDRAM Configuration: 16K Rows, 1024 Columns, 8 Banks
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[2:0]
Row[13:0]
Column[9:0]
M0
Table 32-15. Interleaved Mapping for DDR-SDRAM Configuration: 16K Rows, 1024 Columns, 8 Banks
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[13:0]
32.6.2
Bk[2:0]
Column[9:0]
M0
DDR-SDRAM Address Mapping for Low-cost Memories
Table 32-16. Sequential Mapping for DDR-SDRAM Configuration, 2K Rows, 512 Columns, 2 Banks, 16 Bits
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk Row[10:0]
Column[8:0]
M0
Table 32-17. Interleaved Mapping for DDR-SDRAM Configuration, 2K Rows, 512 Columns, 2 Banks, 16 Bits
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row[10:0]
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Bk Column[8:0]
Complete Datasheet
M0
DS60001579C-page 520
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7
Register Summary
The User Interface is connected to the APB bus. The MPDDRC is programmed using the registers listed in the
following table.
Offset
0x00
0x04
0x08
Name
MPDDRC_MR
MPDDRC_RTR
MPDDRC_CR
0x0C
MPDDRC_TPR0
0x10
MPDDRC_TPR1
0x14
MPDDRC_TPR2
0x18
...
0x1B
Reserved
0x1C
0x20
MPDDRC_LPR
MPDDRC_MD
0x24
...
0x33
Reserved
0x34
MPDDRC_IO_CALI
BR
0x38
MPDDRC_OCMS
0x3C
MPDDRC_OCMS_K
EY1
0x40
MPDDRC_OCMS_K
EY2
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
5
4
3
2
1
0
MODE[2:0]
COUNT[11:8]
COUNT[7:0]
UNAL
DLL
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
DECOD
NDQS
OCD[2:0]
CAS[2:0]
TMRD[3:0]
TRRD[3:0]
TRC[3:0]
TRCD[3:0]
NB
LC_LPDDR1
NR[1:0]
DQMS
DIS_DLL
DIC_DS
NC[1:0]
TWTR[2:0]
TRP[3:0]
TWR[3:0]
TRAS[3:0]
TXP[3:0]
TXSRD[7:0]
TXSNR[7:0]
TRFC[6:0]
TFAW[3:0]
TRPA[3:0]
TXARD[3:0]
TRTP[2:0]
TXARDS[3:0]
SELF_DONE
SELFAUTO
UPD_MR[1:0]
TIMEOUT[1:0]
PASR[2:0]
CLK_FR
DBW
CHG_FRQ
APDE
DS[2:0]
LPCB[1:0]
MD[2:0]
CALCODEN[3:0]
CALCODEP[3:0]
TZQIO[6:0]
CK_F_RANGE[2:0]
TAMPCLR
KEY1[31:24]
KEY1[23:16]
KEY1[15:8]
KEY1[7:0]
KEY2[31:24]
KEY2[23:16]
KEY2[15:8]
KEY2[7:0]
Complete Datasheet
SCR_EN
DS60001579C-page 521
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
...........continued
Offset
Name
Bit Pos.
7
6
5
4
MPDDRC_CONF_A
RBITER
23:16
15:8
0x48
0x4C
MPDDRC_REQ_PO
RT_0123
0x50
...
0x53
Reserved
0x54
MPDDRC_BDW_P
ORT_0123
0x58
...
0x5B
Reserved
0x5C
MPDDRC_RD_DAT
A_PATH
0x60
MPDDRC_MCFGR
0x64
MPDDRC_MADDR0
0x68
MPDDRC_MADDR1
0x6C
MPDDRC_MADDR2
0x70
MPDDRC_MADDR3
0x74
...
0x83
Reserved
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
TIMEOUT_P3[3:0]
TIMEOUT_P1[3:0]
MPDDRC_MINFO0
(MAX_WAIT)
MA_PR_P0
RQ_WD_P0
ARB[1:0]
BDW_P3[6:0]
BDW_P2[6:0]
BDW_P1[6:0]
BDW_P0[6:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
INFO[2:0]
7:0
RUN
SHIFT_SAMPLING[1:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
MA_PR_P1
RQ_WD_P1
NRQ_NWD_BDW_P3[7:0]
NRQ_NWD_BDW_P2[7:0]
NRQ_NWD_BDW_P1[7:0]
NRQ_NWD_BDW_P0[7:0]
31:24
23:16
15:8
7:0
23:16
15:8
7:0
0
TIMEOUT_P2[3:0]
TIMEOUT_P0[3:0]
REFR_CALIB
READ_WRITE[1:0]
SOFT_RESE
EN_MONI
T
ADDR_HIGH_PORT0[15:8]
ADDR_HIGH_PORT0[7:0]
ADDR_LOW_PORT0[15:8]
ADDR_LOW_PORT0[7:0]
ADDR_HIGH_PORT1[15:8]
ADDR_HIGH_PORT1[7:0]
ADDR_LOW_PORT1[15:8]
ADDR_LOW_PORT1[7:0]
ADDR_HIGH_PORT2[15:8]
ADDR_HIGH_PORT2[7:0]
ADDR_LOW_PORT2[15:8]
ADDR_LOW_PORT2[7:0]
ADDR_HIGH_PORT3[15:8]
ADDR_HIGH_PORT3[7:0]
ADDR_LOW_PORT3[15:8]
ADDR_LOW_PORT3[7:0]
31:24
0x84
1
MA_PR_P3 MA_PR_P2
RQ_WD_P3 RQ_WD_P2
BDW_MAX_C
UR
7:0
MPDDRC_TIMEOU
T
2
BDW_BURST BDW_BURST BDW_BURST BDW_BURST
_P3
_P2
_P1
_P0
31:24
0x44
3
LQOS[1:0]
SIZE[2:0]
READ_WRIT
E
BURST[2:0]
MAX_PORT0_WAITING[15:8]
MAX_PORT0_WAITING[7:0]
Complete Datasheet
DS60001579C-page 522
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
...........continued
Offset
Name
0x84
MPDDRC_MINFO0
(NB_TRANSFERS)
0x84
MPDDRC_MINFO0
(TOTAL_LATENCY)
0x84
MPDDRC_MINFO0
(TOTAL_LATENCY_
QOS01)
0x84
MPDDRC_MINFO0
(TOTAL_LATENCY_
QOS23)
0x88
MPDDRC_MINFO1
(MAX_WAIT)
Bit Pos.
7
6
5
4
3
31:24
23:16
P0_NB_TRANSFERS[31:24]
P0_NB_TRANSFERS[23:16]
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
P0_NB_TRANSFERS[15:8]
P0_NB_TRANSFERS[7:0]
P0_TOTAL_LATENCY[31:24]
P0_TOTAL_LATENCY[23:16]
P0_TOTAL_LATENCY[15:8]
P0_TOTAL_LATENCY[7:0]
P_TOTAL_LATENCY_QOS1[15:8]
P_TOTAL_LATENCY_QOS1[7:0]
P_TOTAL_LATENCY_QOS0[15:8]
P_TOTAL_LATENCY_QOS0[7:0]
P0_TOTAL_LATENCY_QOS3[15:8]
P0_TOTAL_LATENCY_QOS3[7:0]
P0_TOTAL_LATENCY_QOS2[15:8]
P0_TOTAL_LATENCY_QOS2[7:0]
31:24
0x88
MPDDRC_MINFO1
(NB_TRANSFERS)
0x88
MPDDRC_MINFO1
(TOTAL_LATENCY)
0x88
MPDDRC_MINFO1
(TOTAL_LATENCY_
QOS01)
0x88
MPDDRC_MINFO1
(TOTAL_LATENCY_
QOS23)
0x8C
MPDDRC_MINFO2
(MAX_WAIT)
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
0x8C
MPDDRC_MINFO2
(NB_TRANSFERS)
0x8C
MPDDRC_MINFO2
(TOTAL_LATENCY)
0x8C
MPDDRC_MINFO2
(TOTAL_LATENCY_
QOS01)
0x8C
MPDDRC_MINFO2
(TOTAL_LATENCY_
QOS23)
© 2020 Microchip Technology Inc.
1
LQOS[1:0]
SIZE[2:0]
0
READ_WRIT
E
BURST[2:0]
MAX_PORT1_WAITING[15:8]
MAX_PORT1_WAITING[7:0]
P1_NB_TRANSFERS[31:24]
P1_NB_TRANSFERS[23:16]
P1_NB_TRANSFERS[15:8]
P1_NB_TRANSFERS[7:0]
P1_TOTAL_LATENCY[31:24]
P1_TOTAL_LATENCY[23:16]
P1_TOTAL_LATENCY[15:8]
P1_TOTAL_LATENCY[7:0]
P_TOTAL_LATENCY_QOS1[15:8]
P_TOTAL_LATENCY_QOS1[7:0]
P_TOTAL_LATENCY_QOS0[15:8]
P_TOTAL_LATENCY_QOS0[7:0]
P1_TOTAL_LATENCY_QOS3[15:8]
P1_TOTAL_LATENCY_QOS3[7:0]
P1_TOTAL_LATENCY_QOS2[15:8]
P1_TOTAL_LATENCY_QOS2[7:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
2
LQOS[1:0]
SIZE[2:0]
READ_WRIT
E
BURST[2:0]
MAX_PORT2_WAITING[15:8]
MAX_PORT2_WAITING[7:0]
P2_NB_TRANSFERS[31:24]
P2_NB_TRANSFERS[23:16]
P2_NB_TRANSFERS[15:8]
P2_NB_TRANSFERS[7:0]
P2_TOTAL_LATENCY[31:24]
P2_TOTAL_LATENCY[23:16]
P2_TOTAL_LATENCY[15:8]
P2_TOTAL_LATENCY[7:0]
P2_TOTAL_LATENCY_QOS1[15:8]
P2_TOTAL_LATENCY_QOS1[7:0]
P2_TOTAL_LATENCY_QOS0[15:8]
P2_TOTAL_LATENCY_QOS0[7:0]
P_TOTAL_LATENCY_QOS3[15:8]
P_TOTAL_LATENCY_QOS3[7:0]
P_TOTAL_LATENCY_QOS2[15:8]
P_TOTAL_LATENCY_QOS2[7:0]
Complete Datasheet
DS60001579C-page 523
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
...........continued
Offset
Name
0x90
MPDDRC_MINFO3
(MAX_WAIT)
Bit Pos.
7
6
5
4
3
31:24
0x90
MPDDRC_MINFO3
(NB_TRANSFERS)
0x90
MPDDRC_MINFO3
(TOTAL_LATENCY)
0x90
MPDDRC_MINFO3
(TOTAL_LATENCY_
QOS01)
0x90
MPDDRC_MINFO3
(TOTAL_LATENCY_
QOS23)
0x94
...
0xBF
Reserved
0xC0
0xC4
0xC8
0xCC
MPDDRC_IER
MPDDRC_IDR
MPDDRC_IMR
MPDDRC_ISR
0xD0
MPDDRC_SAFETY
0xD4
...
0xE3
Reserved
0xE4
0xE8
MPDDRC_WPMR
MPDDRC_WPSR
1
LQOS[1:0]
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
SIZE[2:0]
0
READ_WRIT
E
BURST[2:0]
MAX_PORT3_WAITING[15:8]
MAX_PORT3_WAITING[7:0]
P3_NB_TRANSFERS[31:24]
P3_NB_TRANSFERS[23:16]
P3_NB_TRANSFERS[15:8]
P3_NB_TRANSFERS[7:0]
P3_TOTAL_LATENCY[31:24]
P3_TOTAL_LATENCY[23:16]
P3_TOTAL_LATENCY[15:8]
P3_TOTAL_LATENCY[7:0]
P3_TOTAL_LATENCY_QOS1[15:8]
P3_TOTAL_LATENCY_QOS1[7:0]
P3_TOTAL_LATENCY_QOS0[15:8]
P3_TOTAL_LATENCY_QOS0[7:0]
P_TOTAL_LATENCY_QOS3[15:8]
P_TOTAL_LATENCY_QOS3[7:0]
P_TOTAL_LATENCY_QOS2[15:8]
P_TOTAL_LATENCY_QOS2[7:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
2
EN
ADDRESS[23:16]
ADDRESS[15:8]
ADDRESS[7:0]
RD_ERR
SEC
RD_ERR
SEC
RD_ERR
SEC
RD_ERR
ADDRESS[27:24]
SEC
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
FIRSTE
WPITEN
WPEN
SWETYP[1:0]
ECLASS
© 2020 Microchip Technology Inc.
WPVSRC[15:8]
WPVSRC[7:0]
SWE
Complete Datasheet
SEQE
CGD
WPVS
DS60001579C-page 524
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.1
MPDDRC Mode Register
Name:
Offset:
Reset:
Property:
MPDDRC_MR
0x00
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MODE[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bits 2:0 – MODE[2:0] MPDDRC Command Mode
This field defines the command issued by the MPDDRC when the SDRAM device is accessed. This register is used
to initialize the SDRAM device and to activate Deep Powerdown mode.
Value
Name
Description
0
NORMAL_CMD Normal Mode. Any access to the MPDDRC is decoded normally. To activate this
mode, the command must be followed by a write to the DDR-SDRAM.
1
NOP_CMD
The MPDDRC issues a NOP command when the DDR-SDRAM device is accessed
regardless of the cycle. To activate this mode, the command must be followed by a
write to the DDR-SDRAM.
2
PRCGALL_CMD The MPDDRC issues the All Banks Precharge command when the DDR-SDRAM
device is accessed regardless of the cycle. To activate this mode, the command
must be followed by a write to the SDRAM.
3
LMR_CMD
The MPDDRC issues a Load Mode Register command when the DDR-SDRAM
device is accessed regardless of the cycle. To activate this mode, the command
must be followed by a write to the DDR-SDRAM.
4
RFSH_CMD
The MPDDRC issues an Autorefresh command when the DDR-SDRAM device is
accessed regardless of the cycle. Previously, an All Banks Precharge command
must be issued. To activate this mode, the command must be followed by a write to
the DDR-SDRAM.
5
EXT_LMR_CMD The MPDDRC issues an Extended Load Mode Register command when the
SDRAM device is accessed regardless of the cycle. To activate this mode, the
command must be followed by a write to the DDR-SDRAM. The write in the DDRSDRAM must be done in the appropriate bank.
6
DEEP_MD
Deep Power mode: Access to Deep Powerdown mode
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 525
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.2
MPDDRC Refresh Timer Register
Name:
Offset:
Reset:
Property:
MPDDRC_RTR
0x04
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
4
3
COUNT[7:0]
R/W
R/W
0
0
9
COUNT[11:8]
R/W
R/W
0
0
8
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – COUNT[11:0] MPDDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a
refresh sequence is initiated.
The SDRAM requires autorefresh cycles at an average periodic interval of Trefi. The value to be loaded depends on
the MPDDRC clock frequency MCK (Master Clock) and average periodic interval of Trefi.
For example, for an SDRAM with Trefi = 7.8 μs and a 133 MHz (7.5 ns) Master clock, the value of the COUNT field is
configured: ((7.8 × 10-6) / (7.5 × 10-9)) = 1040 or 0x0410.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 526
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.3
MPDDRC Configuration Register
Name:
Offset:
Reset:
Property:
MPDDRC_CR
0x08
0x00207024
Read/Write
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
UNAL
R/W
0
22
DECOD
R/W
0
21
NDQS
R/W
1
20
NB
R/W
0
19
LC_LPDDR1
R/W
0
18
17
16
DQMS
R/W
0
15
14
13
OCD[2:0]
R/W
1
12
11
10
9
DIS_DLL
R/W
0
8
DIC_DS
R/W
0
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
1
7
DLL
R/W
0
6
R/W
0
5
CAS[2:0]
R/W
1
R/W
1
4
3
NR[1:0]
R/W
0
R/W
0
NC[1:0]
R/W
1
R/W
0
R/W
0
Bit 23 – UNAL This bit must always be written to 1.
Bit 22 – DECOD Type of Decoding
Value
Name
Description
0
SEQUENTIAL Method for address mapping where banks alternate at each last DDR-SDRAM page
of the current bank.
1
INTERLEAVED Method for address mapping where banks alternate at each DDR-SDRAM end of
page of the current bank.
Bit 21 – NDQS Not DQS.
This bit is found in DDR2-SDRAM devices, in Extended Mode register 1. DQS may be used in Single-ended mode or
paired with optional complementary signal NDQS.
To comply with the LPDDR1 standard, DQS must be used in Single-ended mode. NDQS must be disabled.
Value
Name
Description
0
ENABLED
'Not DQS' is enabled.
1
DISABLED
'Not DQS' is disabled.
Bit 20 – NB Number of Banks
LC_LPDDR1 is set to 1, NB is not relevant.
Value
Name
Description
0
4_BANKS
4-bank memory devices
1
8_BANKS
8 banks. Only possible when using DDR2-SDRAM devices.
Bit 19 – LC_LPDDR1 Low-cost Low-power DDR1
Value
Name
Description
0
NOT_2_BANKS
Any type of memory devices except of low cost, low density Low Power DDR1.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 527
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Value
1
Name
Description
2_BANKS_LPDDR1 Low-cost and low-density low-power DDR1. These devices have a density of 32
Mbits and are organized as two internal banks. To use this feature, the user has
to define the type of memory and the data bus width (see 32.7.8
MPDDRC_MD).
The 16-bit memory device is organized as 2 banks, 9 columns and 11 rows.
Bit 16 – DQMS Mask Data is Shared
Value
Name
0
NOT_SHARED
1
SHARED
Description
DQM is not shared with another controller
DQM is shared with another controller
Bits 14:12 – OCD[2:0] Off-chip Driver
SDRAM Controller supports only two values for OCD (default calibration and exit from calibration). These values
MUST always be programmed during the initialization sequence. The default calibration must be programmed first,
after which the exit calibration and maintain settings must be programmed.
This field is found only in the DDR2-SDRAM devices.
Value
Name
Description
0
DDR2_EXITCALIB
Exit from OCD Calibration mode and maintain settings
7
DDR2_DEFAULT_CALIB
OCD calibration default
Bit 9 – DIS_DLL Disable DLL
This value is used during the powerup sequence. It is only found in the DDR2-SDRAM devices.
Value
Description
0
Enable DLL.
1
Disable DLL.
Bit 8 – DIC_DS Output Driver Impedance Control (Drive Strength)
This bit name is described as “DS” in some memory datasheets. It defines the output drive strength. This value is
used during the powerup sequence.
This bit is found only in the DDR2-SDRAM devices.
Value
Name
Description
0
DDR2_NORMALSTRENGTH
Normal drive strength (DDR2)
1
DDR2_WEAKSTRENGTH
Weak drive strength (DDR2)
Bit 7 – DLL Reset DLL
This bit defines the value of Reset DLL. It is found only in DDR2-SDRAM devices.
This value is used during the powerup sequence.
Value
Name
Description
0
RESET_DISABLED
Disable DLL reset
1
RESET_ENABLED
Enable DLL reset
Bits 6:4 – CAS[2:0] CAS Latency
Value
Name
2
DDR_CAS2
3
DDR_CAS3
Description
LPDDR1 CAS Latency 2
DDR2/LPDDR1 CAS Latency 3
Bits 3:2 – NR[1:0] Number of Row Bits
Value
Name
Description
0
11_ROW_BITS
11 bits to define the row number, up to 2048 rows
1
12_ROW_BITS
12 bits to define the row number, up to 4096 rows
2
13_ROW_BITS
13 bits to define the row number, up to 8192 rows
3
14_ROW_BITS
14 bits to define the row number, up to 16384 rows
Bits 1:0 – NC[1:0] Number of Column Bits
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 528
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Value
0
1
2
3
Name
DDR9_MDDR8_COL_BITS
DDR10_MDDR9_COL_BITS
Description
9 bits to define the column number, up to 512 columns, for DDR2SDRAM
8 bits to define the column number, up to 256 columns, for LPDDR1SDRAM
10 bits to define the column number, up to 512 columns, for DDR2SDRAM
9 bits to define the column number, up to 256 columns, for LPDDR1SDRAM
DDR11_MDDR10_COL_BITS 11 bits to define the column number, up to 512 columns, for DDR2SDRAM
10 bits to define the column number, up to 256 columns, for LPDDR1SDRAM
DDR12_MDDR11_COL_BITS 12 bits to define the column number, up to 512 columns, for DDR2SDRAM
11 bits to define the column number, up to 256 columns, for LPDDR1SDRAM
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 529
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.4
MPDDRC Timing Parameter 0 Register
Name:
Offset:
Reset:
Property:
MPDDRC_TPR0
0x0C
0x20227225
Read/Write
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
Bit
31
30
29
28
R/W
1
R/W
0
21
20
27
26
TMRD[3:0]
Access
Reset
Bit
R/W
0
R/W
0
23
22
R/W
0
19
Bit
R/W
0
R/W
0
15
14
Bit
R/W
0
R/W
1
7
6
R/W
1
R/W
0
R/W
0
R/W
0
13
12
11
10
R/W
0
R/W
0
17
16
R/W
1
R/W
0
9
8
R/W
1
R/W
0
1
0
R/W
0
R/W
1
TWR[3:0]
R/W
1
R/W
1
R/W
0
R/W
0
5
4
3
2
TRCD[3:0]
Access
Reset
24
TRP[3:0]
TRC[3:0]
Access
Reset
R/W
0
18
TRRD[3:0]
Access
Reset
25
TWTR[2:0]
R/W
0
TRAS[3:0]
R/W
1
R/W
0
R/W
0
R/W
1
Bits 31:28 – TMRD[3:0] Load Mode Register Command to Activate or Refresh Command
This field defines the delay between a Load mode register command and an Activate or Refresh command in number
of DDRCK clock cycles. The number of cycles is between 0 and 15.
Bits 26:24 – TWTR[2:0] Internal Write to Read Delay
This field defines the internal Write to Read command time in number of DDRCK clock cycles. The number of cycles
is between 1 and 7.
Bits 23:20 – TRRD[3:0] Active BankA to Active BankB
This field defines the delay between an Activate command in BankA and an Activate command in BankB in number
of DDRCK clock cycles. The number of cycles is between 1 and 15.
Bits 19:16 – TRP[3:0] Row Precharge Delay
This field defines the delay between a Precharge command and another command in number of DDRCK clock
cycles. The number of cycles is between 0 and 15.
Bits 15:12 – TRC[3:0] Row Cycle Delay
This field defines the delay between an Activate command and a Refresh command in number of DDRCK clock
cycles. The number of cycles is between 0 and 15.
Bits 11:8 – TWR[3:0] Write Recovery Delay
This field defines the Write Recovery Time in number of DDRCK clock cycles. The number of cycles is between 1
and 15.
Bits 7:4 – TRCD[3:0] Row to Column Delay
This field defines the delay between an Activate command and a Read/Write command in number of DDRCK clock
cycles. The number of cycles is between 0 and 15.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 530
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Bits 3:0 – TRAS[3:0] Active to Precharge Delay
This field defines the delay between an Activate command and a Precharge command in number of DDRCK clock
cycles. The number of cycles is between 0 and 15.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 531
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.5
MPDDRC Timing Parameter 1 Register
Name:
Offset:
Reset:
Property:
MPDDRC_TPR1
0x10
0x03C80808
Read/Write
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
TXP[3:0]
Access
Reset
Bit
23
22
21
20
R/W
0
R/W
0
R/W
1
R/W
1
19
18
17
16
R/W
1
R/W
0
R/W
0
R/W
0
11
10
9
8
TXSRD[7:0]
Access
Reset
Bit
R/W
1
R/W
1
R/W
0
R/W
0
15
14
13
12
TXSNR[7:0]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
7
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
3
TRFC[6:0]
R/W
1
R/W
0
R/W
0
R/W
0
Bits 27:24 – TXP[3:0] Exit Powerdown Delay to First Command
This field defines the delay between CKE set high and a valid command in number of DDRCK clock cycles. The
number of cycles is between 0 and 15.
Bits 23:16 – TXSRD[7:0] Exit Self-refresh Delay to Read Command
This field defines the delay between CKE set high and a Read command in number of DDRCK clock cycles. The
number of cycles is between 0 and 255.
This field is found only in DDR2-SDRAM devices.
Bits 15:8 – TXSNR[7:0] Exit Self-refresh Delay to Non-Read Command
This field defines the delay between CKE set high and a Non Read command in number of DDRCK clock cycles. The
number of cycles is between 0 and 255. This field is used by the DDR-SDRAM devices. In case of low-power DDRSDRAM, this field is equivalent to tXSR.
Bits 6:0 – TRFC[6:0] Row Refresh Cycle
This field defines the delay between a Refresh command or a Refresh and Activate command in number of DDRCK
clock cycles. The number of cycles is between 0 and 127.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 532
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.6
MPDDRC Timing Parameter 2 Register
Name:
Offset:
Reset:
Property:
Bit
MPDDRC_TPR2
0x14
0x00042062
Read/Write
31
30
29
28
27
26
23
22
21
20
19
18
25
24
17
16
R/W
0
R/W
0
9
8
R/W
0
R/W
0
1
0
R/W
1
R/W
0
Access
Reset
Bit
TFAW[3:0]
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
14
R/W
0
7
R/W
0
6
13
TRTP[2:0]
R/W
1
5
TXARDS[3:0]
R/W
R/W
1
1
12
R/W
0
R/W
1
11
10
TRPA[3:0]
R/W
0
R/W
0
R/W
0
4
3
2
TXARD[3:0]
R/W
0
R/W
0
R/W
0
Bits 19:16 – TFAW[3:0] Four Active Windows
DDR2 devices with eight banks (1 Gbit or larger) have an additional requirement concerning tFAW timing. This
requires that no more than four Activate commands may be issued in any given tFAW (MIN) period.
The number of cycles is between 0 and 15.
This field is found only in DDR2-SDRAM.
Bits 14:12 – TRTP[2:0] Read to Precharge
This field defines the delay between a Read command and a Precharge command in number of DDRCK clock
cycles.
The number of cycles is between 0 and 7.
Bits 11:8 – TRPA[3:0] Row Precharge All Delay
This field defines the delay between a Precharge All Banks command and another command in number of DDRCK
clock cycles. The number of cycles is between 0 and 15.
This field is found only in the DDR2-SDRAM devices.
Bits 7:4 – TXARDS[3:0] Exit Active Power Down Delay to Read Command in Mode “Slow Exit”
This field defines the delay between CKE set high and a Read command in number of DDRCK clock cycles. The
number of cycles is between 0 and 15.
This field is found only in the DDR2-SDRAM devices.
Bits 3:0 – TXARD[3:0] Exit Active Power Down Delay to Read Command in Mode “Fast Exit”
This field defines the delay between CKE set high and a Read command in number of DDRCK clock cycles. The
number of cycles is between 0 and 15.
This field is found only in the DDR2-SDRAM devices.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 533
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.7
MPDDRC Low-Power Register
Name:
Offset:
Reset:
Property:
Bit
MPDDRC_LPR
0x1C
0x00010000
Read/Write
31
30
29
23
22
21
15
14
SELFAUTO
R/W
0
28
27
26
25
SELF_DONE
R
0
24
CHG_FRQ
R/W
0
20
UPD_MR[1:0]
R/W
R/W
0
0
19
18
17
16
APDE
R/W
1
13
12
TIMEOUT[1:0]
R/W
R/W
0
0
11
10
9
DS[2:0]
R/W
0
8
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
R/W
0
5
PASR[2:0]
R/W
0
4
R/W
0
3
R/W
0
2
CLK_FR
R/W
0
LPCB[1:0]
R/W
0
R/W
0
Bit 25 – SELF_DONE Self-refresh is Done
This bit indicates that external device is in Self-refresh mode.
Bit 24 – CHG_FRQ Change Clock Frequency During Self-refresh Mode
This mode allows to change the low-power DDR-DRAM input clock frequency. This mode is unique to the low-power
DDR-DRAM devices.
Bits 21:20 – UPD_MR[1:0] Update Load Mode Register and Extended Mode Register
This bit is used to enable or disable automatic update of the Load Mode Register and Extended Mode Register. This
update depends on the MPDDRC integration in a system. MPDDRC can either share or not an external bus with
another controller.
Value
Name
Description
0
NO_UPDATE
Update of Load Mode and Extended Mode registers is disabled.
1
UPDATE_SHAREDBUS
MPDDRC shares an external bus. Automatic update is done during a
refresh command and a pending read or write access in the SDRAM
device.
2
UPDATE_NOSHAREDBUS MPDDRC does not share an external bus. Automatic update is done
before entering Self-refresh mode.
3
–
Reserved
Bit 16 – APDE Active Power Down Exit Time
This mode is unique to the DDR2-SDRAM devices.
This mode manages the active Powerdown mode which determines performance versus power saving.
After the initialization sequence, as soon as the APDE field is modified, the Extended Mode Register (located in the
memory of the external device) is accessed automatically and APDE bits are updated. Depending on the UPD_MR
bit, update is done before entering Self-refresh mode or during a refresh command and a pending read or write
access
Value
Name
Description
0
DDR2_FAST_EXIT
Fast Exit from Power Down. DDR2-SDRAM devices only.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 534
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Value
1
Name
DDR2_SLOW_EXIT
Description
Slow Exit from Power Down. DDR2-SDRAM devices only.
Bit 14 – SELFAUTO Self-refresh Exit Autorefresh
Value
Description
1
Upon exiting Self-refresh mode, autorefresh command is immediately performed after tXSNR.
0
Upon exiting Self-refresh mode, active command is immediately performed after tXSNR. The
autorefresh command is issued every 15.6 µs or less.
Bits 13:12 – TIMEOUT[1:0] Time Between Last Transfer and Low-Power Mode
This field defines when Low-power mode is activated.
Value
Name
Description
0
NONE
SDRAM Low-power mode is activated immediately after the end of the last transfer.
1
DELAY_64_CLK SDRAM Low-power mode is activated 64 clock cycles after the end of the last
transfer.
2
DELAY_128_CLK SDRAM Low-power mode is activated 128 clock cycles after the end of the last
transfer.
3
–
Reserved
Bits 10:8 – DS[2:0] Drive Strength
This field is unique to low-power DDR1-SDRAM. It selects the output drive strength.
After the initialization sequence, as soon as the DS field is modified, the Extended Mode Register is accessed
automatically and DS bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh
mode or during a refresh command and a pending read or write access.
Value
Name
Description
0
DS_FULL
Full drive strength
1
DS_HALF
Half drive strength
2
DS_QUARTER
Quarter drive strength
3
DS_OCTANT
Octant drive strength
4–7
–
Reserved
Bits 6:4 – PASR[2:0] Partial Array Self-refresh
This field is unique to low-power DDR1-SDRAM. It is used to specify whether only one-quarter, one-half or all banks
of the DDR-SDRAM array are enabled. Disabled banks are not refreshed in Self-refresh mode.
The values of this field are dependent on the low-power DDR-SDRAM devices.
After the initialization sequence, as soon as the PASR field is modified, the Extended Mode Register in the external
device memory is accessed automatically and PASR bits are updated. Depending on the UPD_MR bit, update is
done before entering Self-refresh mode or during a refresh command and a pending read or write access.
Bit 2 – CLK_FR Clock Frozen Command Bit
This field sets the clock low during Powerdown mode. Some DDR-SDRAM devices do not support freezing the clock
during Powerdown mode. Refer to the relevant DDR-SDRAM device datasheet for details.
Value
Name
Description
0
DISABLED
Clock(s) is/are not frozen.
1
ENABLED
Clock(s) is/are frozen.
Bits 1:0 – LPCB[1:0] Low-power Command Bit
Value
Name
Description
0
NOLOWPOWER
Low-power feature is inhibited. No Powerdown, Self-refresh and Deep power
modes are issued to the DDR-SDRAM device.
1
SELFREFRESH
The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the
clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM
device leaves the Self-refresh mode when accessed and reenters it after the
access.
2
POWERDOWN
The MPDDRC issues a Powerdown command to the DDR-SDRAM device after
each access, the CKE signal is set low. The DDR-SDRAM device leaves the
Powerdown mode when accessed and reenters it after the access.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 535
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Value
3
Name
Description
DEEPPOWERDOWN The MPDDRC issues a Deep Powerdown command to the low-power DDRSDRAM device.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 536
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.8
MPDDRC Memory Device Register
Name:
Offset:
Reset:
Property:
MPDDRC_MD
0x20
0x00000013
Read/Write
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DBW
R/W
1
3
2
1
MD[2:0]
R/W
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – DBW Data Bus Width
Value
Name
0
RESERVED
1
DBW_16_BITS
Bits 2:0 – MD[2:0] Memory Device
Value
Name
3
LPDDR_SDRAM
6
DDR2_SDRAM
© 2020 Microchip Technology Inc.
R/W
0
R/W
1
Description
Reserved
Data bus width is 16 bits.
Description
Low-power DDR1-SDRAM
DDR2-SDRAM
Complete Datasheet
DS60001579C-page 537
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.9
MPDDRC I/O Calibration Register
Name:
Offset:
Reset:
Property:
Bit
MPDDRC_IO_CALIBR
0x34
0x00870000
Read/Write
31
30
29
28
27
26
25
24
Bit
23
20
19
R
1
R
0
R
0
18
17
CALCODEP[3:0]
R
R
1
1
16
Access
Reset
22
21
CALCODEN[3:0]
R
R
0
0
Bit
15
14
13
12
10
9
8
R/W
0
R/W
0
R/W
0
11
TZQIO[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
2
1
CK_F_RANGE[2:0]
R/W
0
0
Access
Reset
Access
Reset
Bit
7
Access
Reset
R/W
0
R
1
R/W
0
Bits 23:20 – CALCODEN[3:0] Number of N-type Transistors
This value gives the number of N-type transistors to perform the calibration.
Bits 19:16 – CALCODEP[3:0] Number of P-type Transistors
This value gives the number of P-type transistors to perform the calibration.
Bits 14:8 – TZQIO[6:0] IO Calibration
This field defines the delay between the start up of the amplifier and the beginning of the calibration in number of
DDRCK clock cycles. The value of this field must be set to 600 ns.
The number of cycles is between 0 and 127.
The TZQIO configuration code must be set correctly depending on the clock frequency using the following formula:
TZQIO = (DDRCK × 600e-9) + 1
where DDRCK frequency is in Hz.
For example, for a frequency of 176 MHz, the value of the TZQIO field is configured (176 × 10e6) × (600e-9) + 1.
Bits 2:0 – CK_F_RANGE[2:0] DDRCK Maximum Clock Frequency Range Indicator
This field must always be written to 7.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 538
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.10 MPDDRC OCMS Register
Name:
Offset:
Reset:
Property:
MPDDRC_OCMS
0x38
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
TAMPCLR
R/W
0
3
2
1
0
SCR_EN
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – TAMPCLR Tamper Clear Enable
Value
Description
0
A tamper detection event has no effect on MPDDRC scrambling keys.
1
A tamper detection event immediately clears MPDDRC scrambling keys.
Bit 0 – SCR_EN Scrambling Enable
Value
Description
0
Disables “Off-chip” scrambling for SDRAM access.
1
Enables “Off-chip” scrambling for SDRAM access.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 539
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.11 MPDDRC OCMS KEY1 Register
Name:
Offset:
Reset:
Property:
MPDDRC_OCMS_KEY1
0x3C
–
Write-only
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register. The
register can only be written once.
Bit
31
30
29
28
27
26
25
24
W
–
W
–
W
–
W
–
19
18
17
16
W
–
W
–
W
–
W
–
11
10
9
8
W
–
W
–
W
–
W
–
3
2
1
0
W
–
W
–
W
–
W
–
KEY1[31:24]
Access
Reset
W
–
W
–
W
–
W
–
Bit
23
22
21
20
KEY1[23:16]
Access
Reset
W
–
W
–
W
–
W
–
Bit
15
14
13
12
KEY1[15:8]
Access
Reset
W
–
W
–
W
–
W
–
Bit
7
6
5
4
KEY1[7:0]
Access
Reset
W
–
W
–
W
–
W
–
Bits 31:0 – KEY1[31:0] Off-chip Memory Scrambling (OCMS) Key Part 1
When Off-chip Memory Scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 540
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.12 MPDDRC OCMS KEY2 Register
Name:
Offset:
Reset:
Property:
MPDDRC_OCMS_KEY2
0x40
–
Write-only
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register. The
register can only be written once.
Bit
31
30
29
28
27
26
25
24
W
–
W
–
W
–
W
–
19
18
17
16
W
–
W
–
W
–
W
–
11
10
9
8
W
–
W
–
W
–
W
–
3
2
1
0
W
–
W
–
W
–
W
–
KEY2[31:24]
Access
Reset
W
–
W
–
W
–
W
–
Bit
23
22
21
20
KEY2[23:16]
Access
Reset
W
–
W
–
W
–
W
–
Bit
15
14
13
12
KEY2[15:8]
Access
Reset
W
–
W
–
W
–
W
–
Bit
7
6
5
4
KEY2[7:0]
Access
Reset
W
–
W
–
W
–
W
–
Bits 31:0 – KEY2[31:0] Off-chip Memory Scrambling (OCMS) Key Part 2
When Off-chip Memory Scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 541
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.13 MPDDRC Configuration Arbiter Register
Name:
Offset:
Reset:
Property:
Bit
MPDDRC_CONF_ARBITER
0x44
0x00000000
Read/Write
31
30
29
28
23
22
21
20
19
MA_PR_P3
R/W
0
18
MA_PR_P2
R/W
0
17
MA_PR_P1
R/W
0
16
MA_PR_P0
R/W
0
15
14
13
12
11
RQ_WD_P3
R/W
0
10
RQ_WD_P2
R/W
0
9
RQ_WD_P1
R/W
0
8
RQ_WD_P0
R/W
0
7
6
5
4
3
BDW_MAX_CU
R
R/W
0
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
27
26
25
24
BDW_BURST_ BDW_BURST_ BDW_BURST_ BDW_BURST_
P3
P2
P1
P0
R/W
R/W
R/W
R/W
0
0
0
0
ARB[1:0]
R/W
0
R/W
0
Bits 24, 25, 26, 27 – BDW_BURST_Px Bandwidth Arbitration Mode on Port X
Value
Description
0
The arbitration is done when the bandwidth limit defined in MPDDRC_BDW_PORT_0123.BDW_Px is
reached. If the bandwidth limit is reached during a burst access, the burst is completed.
1
The arbitration is done when the bandwidth limit defined in MPDDRC_BDW_PORT_0123.BDW_Px is
reached. If the bandwidth limit is reached during a burst access, the burst is broken.
Bits 16, 17, 18, 19 – MA_PR_Px Master or Software Provide Information
Value
Description
0
Number of requests or words is provided by the master, if the master supports this feature.
1
Number of requests or words is provided by software, see “NRQ_NWD_BDW_Px: Number of
Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3”.
Bits 8, 9, 10, 11 – RQ_WD_Px Request or Word from Port X
Value
Description
0
Number of requests is selected.
1
Number of words is selected.
Bit 3 – BDW_MAX_CUR Bandwidth Max or Current
This field displays the maximum of the bandwidth or the current bandwidth for each port.
The maximum of the bandwidth is computed when at least two ports of MPDDRC are used.
That information is given in MPDDRC Current/Maximum Bandwidth Port 0-1-2-3 Register.
Value
Description
0
Current bandwidth is displayed.
1
Maximum of the bandwidth is displayed.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 542
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Bits 1:0 – ARB[1:0] Type of Arbitration
This field allows to choose the type of arbitration: round-robin, number of requests per port or bandwidth per port.
Value
Name
Description
0
ROUND
Round-Robin Policy
1
NB_REQUEST
Request Policy
2
BANDWIDTH
Bandwidth Policy
3
LQOS
Quality of Service Policy
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 543
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.14 MPDDRC Timeout Register
Name:
Offset:
Reset:
Property:
Bit
MPDDRC_TIMEOUT
0x48
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
12
11
R/W
0
R/W
0
4
3
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
15
R/W
0
7
R/W
0
14
13
TIMEOUT_P3[3:0]
R/W
R/W
0
0
6
5
TIMEOUT_P1[3:0]
R/W
R/W
0
0
10
9
TIMEOUT_P2[3:0]
R/W
R/W
0
0
2
1
TIMEOUT_P0[3:0]
R/W
R/W
0
0
8
R/W
0
0
R/W
0
Bits 0:3, 4:7, 8:11, 12:15 – TIMEOUT_Px Timeout for Ports 0, 1, 2, 3
Some masters have the particularity to insert idle state between two accesses. This field defines the delay between
two accesses on the same port in number of DDRCK clock cycles before arbitration and handling the access over to
another port.
This field is not used with round-robin and bandwidth arbitrations.
The number of cycles is between 1 and 15.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 544
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.15 MPDDRC Request Port 0-1-2-3 Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
MPDDRC_REQ_PORT_0123
0x4C
0x00000000
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
NRQ_NWD_BDW_P3[7:0]
R/W
R/W
0
0
20
19
NRQ_NWD_BDW_P2[7:0]
R/W
R/W
0
0
12
11
NRQ_NWD_BDW_P1[7:0]
R/W
R/W
0
0
4
3
NRQ_NWD_BDW_P0[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 0:7, 8:15, 16:23, 24:31 – NRQ_NWD_BDW_Px Number of Requests, Number of Words or Bandwidth
Allocation from Port 0-1-2-3
The number of requests corresponds to the number of start transfers. For example, setting this field to 2 performs two
burst accesses regardless of the burst type (INCR4, INCR8, etc.). The number of words corresponds exactly to the
number of accesses; setting this field to 2 performs two accesses. In this example, burst accesses will be broken.
These values depend on scheme arbitration (see MPDDRC Configuration Arbiter Register).
In case of round-robin arbitration, this field is not used. In case of “bandwidth arbitration”, this field corresponds to
percentage allocated for each port. In case of “request” arbitration, this field corresponds to number of start transfers
or to number of accesses allocated for each port.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 545
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.16 MPDDRC Current/Maximum Bandwidth Port 0-1-2-3 Register
Name:
Offset:
Reset:
Property:
Bit
31
Access
Reset
Bit
23
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
MPDDRC_BDW_PORT_0123
0x54
0x00000000
Read-only
30
29
28
R
0
R
0
R
0
22
21
20
R
0
R
0
R
0
14
13
12
R
0
R
0
R
0
6
5
4
R
0
R
0
R
0
27
BDW_P3[6:0]
R
0
26
25
24
R
0
R
0
R
0
19
BDW_P2[6:0]
R
0
18
17
16
R
0
R
0
R
0
11
BDW_P1[6:0]
R
0
10
9
8
R
0
R
0
R
0
3
BDW_P0[6:0]
R
0
2
1
0
R
0
R
0
R
0
Bits 0:6, 8:14, 16:22, 24:30 – BDW_Px Current/Maximum Bandwidth from Port 0-1-2-3
This field displays the current bandwidth or the maximum bandwidth for each port. This information is given in the
“BDW_MAX_CUR: Bandwidth Max or Current” field description.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 546
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.17 MPDDRC Read Data Path Register
Name:
Offset:
Reset:
Property:
Bit
MPDDRC_RD_DATA_PATH
0x5C
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
SHIFT_SAMPLING[1:0]
R/W
R/W
0
0
Bits 1:0 – SHIFT_SAMPLING[1:0] Shift Sampling Point of Data
Shifts the sampling point of data coming from the memory device. The higher the memory device clock frequency, the
higher the SHIFT_SAMPLING value. Refer to the section "Electrical Characteristics".
Value
Name
Description
0
NO_SHIFT
Initial sampling point.
1
SHIFT_ONE_CYCLE
Sampling point is shifted by one cycle.
2
SHIFT_TWO_CYCLES
Sampling point is shifted by two cycles.
3
SHIFT_THREE_CYCLES
Not applicable for DDR2 and LPDDR1 devices.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 547
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.18 MPDDRC Monitor Configuration Register
Name:
Offset:
Reset:
Property:
Bit
MPDDRC_MCFGR
0x60
0x00000011
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
INFO[2:0]
11
10
REFR_CALIB
0
0
0
0
5
4
RUN
R/W
1
3
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
Access
Reset
9
8
READ_WRITE[1:0]
R/W
R/W
0
0
1
SOFT_RESET
R/W
0
0
EN_MONI
R/W
1
Bits 13:11 – INFO[2:0] Information Type
This field reports information such as latency and the number of transfers monitored on port x [x = 0..3].
Value
Name
Description
0
MAX_WAIT
Information concerning the transfer with the longest waiting time
1
NB_TRANSFERS
Number of transfers on the port
2
TOTAL_LATENCY
Total latency on the port
3
–
Reserved
4
MAX_WAIT_QOS01 Information concerning the transfer with the longest waiting time, depending on
QOS values (0 and 1)
5
MAX_WAIT_QOS23 Information concerning the transfer with the longest waiting time, depending on
QOS values (2 and 3)
Bit 10 – REFR_CALIB Refresh Calibration
Value
Description
0
Monitoring does not depend on Autorefresh mode, Self-refresh mode, Powerdown mode, DLL nor
calibration impact.
1
Monitoring depends on Autorefresh mode, Self-refresh mode, Powerdown mode, DLL and calibration
impact.
Bits 9:8 – READ_WRITE[1:0] Read/Write Access
This field is used to monitor different types of access.
Value
Name
Description
0
TRIG_RD_WR
Read and Write accesses are triggered.
1
TRIG_WR
Only Write accesses are triggered.
2
TRIG_RD
Only Read accesses are triggered.
3
–
Reserved
Bit 4 – RUN Control Monitor
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 548
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Value
0
1
Description
Monitoring is halted. All counters are stopped.
Monitoring is launched.
Bit 1 – SOFT_RESET Soft Reset
Value
Description
0
Soft reset is not performed.
1
Soft reset is performed.
Bit 0 – EN_MONI Enable Monitor
Value
Description
0
Monitor is disabled.
1
Monitor is enabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 549
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.19 MPDDRC Monitor Address High/Low Port x Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
MPDDRC_MADDRx
0x64 + x*0x04 [x=0..3]
0xFFFF0000
Read/Write
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
ADDR_HIGH_PORTx[15:8]
R/W
R/W
1
1
20
19
ADDR_HIGH_PORTx[7:0]
R/W
R/W
1
1
12
11
ADDR_LOW_PORTx[15:8]
R/W
R/W
0
0
4
3
ADDR_LOW_PORTx[7:0]
R/W
R/W
0
0
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:16 – ADDR_HIGH_PORTx[15:0] Address High on Port x
Address high which defines the interval to be monitored on port x [x = 0..3]. This address must be programmed
according to the memory mapping of the product.
Bits 15:0 – ADDR_LOW_PORTx[15:0] Address Low on Port x
Address low which defines the interval to be monitored on port x [x = 0..3]. This address must be programmed
according to the memory mapping of the product.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 550
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.20 MPDDRC Monitor Information Port x Register (MAX_WAIT)
Name:
Offset:
Reset:
Property:
MPDDRC_MINFOx (MAX_WAIT)
0x84 + x*0x04 [x=0..3]
0x00000000
Read-only
The following fields can be read if the INFO field in the MPDDRC Monitor Configuration register is set to 0.
Bit
31
30
29
28
27
26
25
LQOS[1:0]
Access
Reset
Bit
23
Access
Reset
22
R
0
21
SIZE[2:0]
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
24
READ_WRITE
R
0
R
0
R
0
18
16
R
0
17
BURST[2:0]
R
0
12
11
MAX_PORTx_WAITING[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
MAX_PORTx_WAITING[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
20
19
R
0
R
0
Bits 26:25 – LQOS[1:0] Value of Quality Of Service on Port x
This field reports the value of quality of service for the maximum waiting time.
Value
Name
Description
0
BACKGROUND
Background transfers
1
BANDWIDTH
Bandwidth sensitive
2
SENSITIVE_LAT
Latency sensitive
3
CRITICAL_LAT
Latency critical
Bit 24 – READ_WRITE Read or Write Access on Port x
This field reports the transfer direction for the maximum waiting time.
Value
Description
0
Read transfer
1
Write transfer
Bits 22:20 – SIZE[2:0] Transfer Size on Port x
This field reports the size of the transfer for the maximum waiting time.
Value
Name
Description
0
8BITS
Byte transfer
1
16BITS
Halfword transfer
2
32BITS
Word transfer
3
64BITS
Dword transfer
Bits 18:16 – BURST[2:0] Type of Burst on Port x
This field reports the type of burst for the maximum waiting time.
Value
Name
Description
0
SINGLE
Single transfer
1
INCR
Incrementing burst of unspecified length
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 551
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Value
2
3
4
5
6
7
Name
WRAP4
INCR4
WRAP8
INCR8
WRAP16
INCR16
Description
4-beat wrapping burst
4-beat incrementing burst
8-beat wrapping burst
8-beat incrementing burst
16-beat wrapping burst
16-beat incrementing burst
Bits 15:0 – MAX_PORTx_WAITING[15:0] Address High on Port x
This field reports the maximum waiting time and the associated type of transfer (burst, size, read or write).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 552
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.21 MPDDRC Monitor Information Port x Register (NB_TRANSFERS)
Name:
Offset:
Reset:
Property:
MPDDRC_MINFOx (NB_TRANSFERS)
0x84 + x*0x04 [x=0..3]
0x00000000
Read-only
The following fields can be read if the INFO field in the MPDDRC Monitor Configuration register is set to 1.
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
28
27
Px_NB_TRANSFERS[31:24]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
Px_NB_TRANSFERS[23:16]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
Px_NB_TRANSFERS[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
Px_NB_TRANSFERS[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 31:0 – Px_NB_TRANSFERS[31:0] Number of Transfers on Port x
This field can be read if the INFO field is set to 1. This field reports the number of transfers performed within an
interval (ADDR_HIGH_PORT and ADDR_LOW_PORT) when the port is used.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 553
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.22 MPDDRC Monitor Information Port x Register (TOTAL_LATENCY)
Name:
Offset:
Reset:
Property:
MPDDRC_MINFOx (TOTAL_LATENCY)
0x84 + x*0x04 [x=0..3]
0x00000000
Read-only
The following fields can be read if the INFO field in the MPDDRC Monitor Configuration register is set to 2.
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
28
27
Px_TOTAL_LATENCY[31:24]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
Px_TOTAL_LATENCY[23:16]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
Px_TOTAL_LATENCY[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
Px_TOTAL_LATENCY[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 31:0 – Px_TOTAL_LATENCY[31:0] Total Latency on Port x
This field can be read if the INFO field is set to 2. This field reports the total latency within an interval
(ADDR_HIGH_PORT and ADDR_LOW_PORT) when the port is used.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 554
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.23 MPDDRC Monitor Information Port x Register (TOTAL_LATENCY_QOS01)
Name:
Offset:
Reset:
Property:
MPDDRC_MINFOx (TOTAL_LATENCY_QOS01)
0x84 + x*0x04 [x=0..3]
0x00000000
Read-only
The following fields can be read if the INFO field in the MPDDRC Monitor Configuration register is set to 4.
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
28
27
Px_TOTAL_LATENCY_QOS1[15:8]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
Px_TOTAL_LATENCY_QOS1[7:0]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
Px_TOTAL_LATENCY_QOS0[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
Px_TOTAL_LATENCY_QOS0[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 31:16 – Px_TOTAL_LATENCY_QOS1[15:0] Total Latency on Port x when value of qos is 1
This field can be read if the INFO field is set to 4. This field reports the total latency within an interval
(ADDR_HIGH_PORT and ADDR_LOW_PORT) when the port is used with qos = 1.
Bits 15:0 – Px_TOTAL_LATENCY_QOS0[15:0] Total Latency on Port x when value of qos is 0
This field can be read if the INFO field is set to 4. This field reports the total latency within an interval
(ADDR_HIGH_PORT and ADDR_LOW_PORT) when the port is used with qos = 0.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 555
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.24 MPDDRC Monitor Information Port x Register (TOTAL_LATENCY_QOS23)
Name:
Offset:
Reset:
Property:
MPDDRC_MINFOx (TOTAL_LATENCY_QOS23)
0x84 + x*0x04 [x=0..3]
0x00000000
Read-only
The following fields can be read if the INFO field in the MPDDRC Monitor Configuration register is set to 5.
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
28
27
Px_TOTAL_LATENCY_QOS3[15:8]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
Px_TOTAL_LATENCY_QOS3[7:0]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
Px_TOTAL_LATENCY_QOS2[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
Px_TOTAL_LATENCY_QOS2[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 31:16 – Px_TOTAL_LATENCY_QOS3[15:0] Total Latency on Port x when value of qos is 3
This field can be read if the INFO field is set to 5. This field reports the total latency within an interval
(ADDR_HIGH_PORT and ADDR_LOW_PORT) when the port is used with qos = 3.
Bits 15:0 – Px_TOTAL_LATENCY_QOS2[15:0] Total Latency on Port x when value of qos is 2
This field can be read if the INFO field is set to 5. This field reports the total latency within an interval
(ADDR_HIGH_PORT and ADDR_LOW_PORT) when the port is used with qos = 2.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 556
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.25 MPDDRC Interrupt Enable Register
Name:
Offset:
Reset:
Property:
MPDDRC_IER
0xC0
–
Write-only
This register can only be written if the WPITEN bit is cleared in the MPDDRC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RD_ERR
W
–
0
SEC
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – RD_ERR Read Error Interrupt Enable
Bit 0 – SEC Security and /or Safety Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 557
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.26 MPDDRC Interrupt Disable Register
Name:
Offset:
Reset:
Property:
MPDDRC_IDR
0xC4
–
Write-only
This register can only be written if the WPITEN bit is cleared in the MPDDRC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RD_ERR
W
–
0
SEC
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – RD_ERR Read Error Interrupt Disable
Bit 0 – SEC Security and /or Safety Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 558
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.27 MPDDRC Interrupt Mask Register
Name:
Offset:
Reset:
Property:
MPDDRC_IMR
0xC8
–
Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RD_ERR
R
–
0
SEC
R
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – RD_ERR Read Error Interrupt Mask
Bit 0 – SEC Security and /or Safety Interrupt Mask
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 559
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.28 MPDDRC Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
MPDDRC_ISR
0xCC
–
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RD_ERR
R
–
0
SEC
R
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – RD_ERR Read Error
Value
Description
0
There is no error during memory check.
1
There is one error during memory check.
Bit 0 – SEC Security and /or Safety Event
Value
Description
0
There is no security report in MPDDRC_WPSR.
1
One security flag is set in MPDDRC_WPSR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 560
SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.29 MPDDRC Safety Register
Name:
Offset:
Reset:
Property:
Bit
31
MPDDRC_SAFETY
0xD0
0x00000000
Read/Write
30
29
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
EN
R/W
0
27
R/W
0
20
19
ADDRESS[23:16]
R/W
R/W
0
0
12
11
ADDRESS[15:8]
R/W
R/W
0
0
4
3
ADDRESS[7:0]
R/W
R/W
0
0
26
25
ADDRESS[27:24]
R/W
R/W
0
0
24
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 28 – EN Enable Periodic Check of Memory Device
Value
Description
0
Memory check is disabled.
1
Memory check is enabled.
Bits 27:0 – ADDRESS[27:0] Memory Device Address
Memory device address to be checked.
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.30 MPDDRC Write Protection Mode Register
Name:
Offset:
Reset:
Property:
MPDDRC_WPMR
0xE4
0x00000000
Read/Write
See 32.5.8 Register Write Protection for the list of registers that can be protected.
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
FIRSTE
R/W
0
3
2
1
WPITEN
R/W
0
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x444452 PASSWD Writing any other value in this field aborts the write operation of the WPEN and WPITEN
bits.
Always reads as 0.
Bit 4 – FIRSTE First Error Report Enable
Value
Description
0
The last write protection violation source is reported in MPDDRC_WPSR.WPVSRC and the last
software control error type is reported in MPDDRC_WPSR.SWETYP. The MPDDRC_ISR.SEC flag is
set at the first error occurrence within a series.
1
Only the first write protection violation source is reported in MPDDRC_WPSR.WPVSRC and only the
first software control error type is reported in MPDDRC_WPSR.SWETYP. The MPDDRC_ISR.SEC flag
is set at the first error occurrence within a series.
Bit 1 – WPITEN Write Protection Interruption Enable
Value
Description
0
Disables the write protection on interrupt registers if WPKEY corresponds to 0x444452 (“DDR” in
ASCII).
1
Enables the write protection on interrupt registers if WPKEY corresponds to 0x444452 (“DDR” in
ASCII).
Bit 0 – WPEN Write Protection Enable
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
32.7.31 MPDDRC Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
MPDDRC_WPSR
0xE8
0x00000000
Read-only
31
ECLASS
R
0
30
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
Bit
7
6
Access
Reset
29
28
27
26
25
24
SWETYP[1:0]
Access
Reset
R
0
R
0
20
19
WPVSRC[15:8]
R
R
0
0
18
17
16
R
0
R
0
R
0
10
9
8
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
5
4
2
SEQE
R
0
1
CGD
R
0
0
WPVS
R
0
3
SWE
R
0
Bit 31 – ECLASS Software Error Class (cleared on read)
0 (WARNING): An abnormal access that does not affect system functionality is performed.
1 (ERROR): An access is performed into some registers after memory device initialization sequence.
Bits 25:24 – SWETYP[1:0] Software Error Type (cleared on read)
Value
Name
Description
0
READ_WO
A write-only register has been read (warning).
1
WRITE_RO
MPDDRC is enabled and a write access has been performed on a read-only register
(warning).
2
UNDEF_RW
Access to an undefined address (warning).
3
W_AFTER_INIT Abnormal use of MPDDRC user interface when memory device is already configured
and initialized, i.e., if MPDDRC_RTR.COUNT > 0 (error).
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 3 – SWE Software Control Error (cleared on read)
Value
Description
0
No software error has occurred since the last read of MPDDRC_WPSR.
1
A software error has occurred since the last read of MPDDRC_WPSR. The field SWE details the type
of software error. The associated incorrect software access is reported in the field WPVSRC (if
WPVS=0).
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
Value
Description
0
No peripheral internal sequencer error has occurred since the last read of MPDDRC_WPSR.
1
A peripheral internal sequencer error has occurred since the last read of MPDDRC_WPSR. This flag
can only be set under abnormal operating conditions.
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SAM9X60
AHB Multiport DDR-SDRAM Controller (MPDDRC)
Bit 1 – CGD Clock Glitch Detected (cleared on read)
Value
Description
0
The clock monitoring circuitry has not been corrupted since the last read of MPDDRC_WPSR. Under
normal operating conditions, this bit is always cleared.
1
The clock monitoring circuitry has been corrupted since the last read of MPDDRC_WPSR. This flag
can only be set in case of an abnormal clock signal waveform (glitch).
Bit 0 – WPVS Write Protection Enable
Value
Description
0
No write protection violation occurred since the last read of this register (MPDDRC_WPSR).
1
A write protection violation occurred since the last read of this register (MPDDRC_WPSR). If this
violation is an unauthorized attempt to write a control register, the associated violation is reported into
the WPVSRC field.
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SAM9X60
SDRAM Controller (SDRAMC)
33.
SDRAM Controller (SDRAMC)
33.1
Description
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to external
16-bit and 32-bit DRAM devices. The page size supports ranges from 2048 to 8192 and the number of columns from
256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The SDRAMC supports a read or write burst length of one location. It keeps track of the active row in each bank, thus
maximizing SDRAM performance, for example, the application may be placed in one bank and data in the other
banks. For optimized performance, it is advisable to avoid accessing different rows in the same bank.
The SDRAMC supports a CAS latency of 2 or 3 and optimizes the read access depending on the frequency.
The different modes available – Self-refresh, Powerdown and Deep Powerdown modes – minimize power
consumption on the SDRAM device.
33.2
Embedded Characteristics
•
•
•
•
•
•
•
•
•
•
•
33.3
Numerous Configurations Supported
– 2K, 4K, 8K row address memory parts
– SDRAM with two or four internal banks
– SDRAM with 16-bit and 32-bit data path
Programming Facilities
– Word, half-word, byte access
– Automatic Page break when memory boundary has been reached
– Multibank ping-pong access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices)
Energy-Saving Capabilities
– Self-refresh, Powerdown and Deep Power modes Supported
– Supports mobile SDRAM devices
Error Detection
– Refresh error interrupt
SDRAM Power-up Initialization by Software
CAS Latency of 2, 3 Supported
Auto Precharge Command Not Used
256-Mbyte address space with 32-bit data path, 128-Mbyte address space with 16-bit data path
Zero Wait State Scrambling/Unscrambling Function with User Key
Multiplexed Address/Data Lines or Address/Data/Command Lines for Reduced Pin Count
Abnormal Software Access and Internal Sequencer Integrity Check Reports
Signal Description
Table 33-1. Signal Description
Name
Description
Type
Active Level
SDCK
SDRAM Clock
Output
–
SDCKE
SDRAM Clock Enable
Output
High
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SAM9X60
SDRAM Controller (SDRAMC)
...........continued
33.4
Name
Description
Type
Active Level
SDCS
SDRAMC Chip Select
Output
Low
BA[1:0]
Bank Select Signals
Output
–
RAS
Row Signal
Output
Low
CAS
Column Signal
Output
Low
SDWE
SDRAM Write Enable
Output
Low
NBS[3:0]
Data Mask Enable Signals
Output
Low
SDRAMC_A[12:0]
Address Bus
Output
–
D[31:0]
Data Bus
I/O
–
Software Interface/SDRAM Organization, Address Mapping
The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows mapping different
memory types according to the values set in the Configuration register (SDRAMC_CR).
The SDRAMC makes the SDRAM device access protocol transparent to the user. The following tables illustrate the
SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are
illustrated.
33.4.1
SDRAM Address Mapping for 32-bit Memory Data Bus Width
Table 33-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24
23
22
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[10:0]
Column[7:0]
Row[10:0]
Column[8:0]
Row[10:0]
Row[10:0]
0
M[1:0]
M[1:0]
Column[9:0]
M[1:0]
Column[10:0]
M[1:0]
Note: M[1:0] is the byte address inside a 32-bit word and Bk[1] = BA1, Bk[0] = BA0.
Table 33-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25
24
23
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[11:0]
Column[7:0]
Row[11:0]
Column[8:0]
Row[11:0]
Row[11:0]
Column[9:0]
Column[10:0]
0
M[1:0]
M[1:0]
M[1:0]
M[1:0]
Note: M[1:0] is the byte address inside a 32-bit word and Bk[1] = BA1, Bk[0] = BA0.
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SAM9X60
SDRAM Controller (SDRAMC)
Table 33-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26
25
24
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[12:0]
Column[7:0]
Row[12:0]
Column[8:0]
Row[12:0]
M[1:0]
M[1:0]
Column[9:0]
Row[12:0]
0
M[1:0]
Column[10:0]
M[1:0]
Note: M[1:0] is the byte address inside a 32-bit word and Bk[1] = BA1, Bk[0] = BA0.
33.4.2
SDRAM Address Mapping for 16-bit Memory Data Bus Width
Table 33-5. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24
23
22
21
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[10:0]
Column[7:0]
Row[10:0]
Column[8:0]
Row[10:0]
Column[9:0]
Row[10:0]
M0
M0
M0
Column[10:0]
M0
Note: M0 is the byte address inside a 16-bit half-word and Bk[1] = BA1, Bk[0] = BA0.
Table 33-6. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25
24
23
22
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[11:0]
Column[7:0]
Row[11:0]
Column[8:0]
Row[11:0]
Column[9:0]
Row[11:0]
M0
M0
M0
Column[10:0]
M0
Note: M0 is the byte address inside a 16-bit half-word and Bk[1] = BA1, Bk[0] = BA0.
Table 33-7. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26
25
24
23
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
Row[12:0]
Column[7:0]
Row[12:0]
Column[8:0]
Row[12:0]
Column[9:0]
Row[12:0]
Column[10:0]
M0
M0
M0
M0
Note: M0 is the byte address inside a 16-bit half-word and Bk[1] = BA1, Bk[0] = BA0.
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SAM9X60
SDRAM Controller (SDRAMC)
33.5
33.5.1
Product Dependencies
SDRAM Device Initialization
The initialization sequence is generated by software. The sequence to initialize SDRAM devices is the following:
1.
Set the SDRAM features in the SDRAMC_CR: asynchronous timings (TRC, TRAS, etc.), number of columns,
number of rows, CAS latency and data bus width. Set UNAL bit in SDRAMC_CFR1.
2. For mobile SDRAM, configure temperature-compensated self-refresh (TCSR), drive strength (DS) and partial
array self-refresh (PASR) in the Low Power register (SDRAMC_LPR).
3. Select the SDRAM memory device type and the shift sampling value in the Memory Device register
(SDRAMC_MDR).
4. A pause of at least 200 μs must be observed before a signal toggle.
5. A NOP command is issued to the SDRAM devices. The application must write a 1 to the MODE field in the
Mode register (SDRAMC_MR) (see Note). Read the SDRAMC_MR and add a memory barrier assembler
instruction just after the read. Perform a write access to any SDRAM address.
6. An All Banks Precharge command is issued to the SDRAM. The application must write a 2 to the MODE field
in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the
read. Perform a write access to any SDRAM address.
7. Eight autorefresh (CBR) cycles are provided. The application must set the MODE field to 4 in the
SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read.
Perform a write access to any SDRAM location eight times.
8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM, in particular CAS
latency and burst length. The application must write a 3 to the MODE field in the SDRAMC_MR. Read the
SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to
the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128
MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the
address 0x20000000.
9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the
SDRAM parameters (TCSR, PASR, DS). The application must set the MODE field to 5 in the SDRAMC_MR.
Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write
access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to 1. For example,
with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should
be done at address 0x20800000 or 0x20400000.
10. The application must go into Normal mode. Configure MODE to 0 in the SDRAMC_MR. Read the
SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access at
any location in the SDRAM.
11. Write the refresh rate into the COUNT field in the Refresh Timer register (SDRAMC_TR). (Refresh rate = delay
between refresh cycles). The SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz
frequency, the Refresh Timer register must be set with the value 1562 (15.625 μs x 100 MHz) or 781 (7.81 μs
x 100 MHz).
After initialization, the SDRAM devices are fully functional.
Note: The instructions stated in Step 5 of the initialization process must be respected to make sure the subsequent
commands issued by the SDRAMC are taken into account.
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SAM9X60
SDRAM Controller (SDRAMC)
Figure 33-1. SDRAM Device Initialization Sequence
SDCKE
tRP
tRFC
tMRD
SDCK
SDRAMC_A[9:0]
A10
SDRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
NBS
Inputs stable for
200 μs
33.5.2
Precharge All Banks
1st Autorefresh
8th Autorefresh
MRS Command
Valid Command
I/O Lines
The pins used for interfacing the SDRAMC may be multiplexed with the PIO lines. The programmer must first
program the PIO controller to assign the SDRAMC pins to their peripheral function. If I/O lines of the SDRAMC are
not used by the application, they can be used for other purposes by the PIO Controller.
33.5.3
Power Management
The SDRAMC may be clocked through the Power Management Controller (PMC), thus the programmer must first
configure the PMC to enable the SDRAMC clock.
The SDRAM clock on pin SDCK is output as soon as the first access to the SDRAM is made during the initialization
phase. To stop the SDRAM clock signal, the SDRAMC_LPR must be programmed with the self-refresh command.
33.5.4
Interrupt Sources
Using the SDRAMC interrupt requires the interrupt controller to be programmed first.
The SDRAMC interrupt line (Refresh Error notification) is connected to the interrupt controller through the memory
controller (external bus interface) interrupt line.
SDRAMC refresh error notification interrupt line is ORed with other system peripheral interrupt lines and is finally
provided as the system interrupt source to the interrupt controller.
33.6
Functional Description
33.6.1
SDRAM Controller Write Cycle
The SDRAMC allows burst access or single access. In both cases, the SDRAMC keeps track of the active row in
each bank, thus maximizing performance. To initiate a burst access, the SDRAMC uses the transfer type signal
provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM
device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or
if the next access is in another row, then the SDRAMC generates a precharge command, activates the new row and
initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between
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SAM9X60
SDRAM Controller (SDRAMC)
precharge and active commands (tRP), and between active and write commands (tRCD). For definition of these timing
parameters, refer to the SDRAMC Configuration Register. Refer to the following figure.
Figure 33-2. Write Burst SDRAM Access
tRCD
SDCS
SDCK
SDRAMC_A[12:0]
Row n
col a
col b
col c
col d
col e
col f
col g
col h
col i
col j
col k
col l
Dnb
Dnc
Dnd
Dne
Dnf
Dng
Dnh
Dni
Dnj
Dnk
Dnl
RAS
CAS
SDWE
DATA
33.6.2
Dna
SDRAM Controller Read Cycle
The SDRAMC allows burst access, incremental burst of unspecified length or single access. In all cases, the
SDRAMC keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank
addresses do not match the previous row/bank address, then the SDRAMC automatically generates a precharge
command, activates the new row and starts the read command. To comply with the SDRAM timing parameters,
additional clock cycles on SDCK are inserted between precharge and active commands (tRP), and between active
and read commands (tRCD). These two parameters are set in the SDRAMC_CR. After a read command, additional
wait states are generated to comply with the CAS latency ( 2 or 3 clock delays specified in the SDRAMC_CR).
For a single access or an incremented burst of unspecified length, the SDRAMC anticipates the next access. While
the last value of the column is returned by the SDRAMC on the bus, the SDRAMC anticipates the read to the next
column and thus anticipates the CAS latency. This reduces the effect of the CAS latency on the internal bus.
For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads to the best
performance. If the burst is broken (border, Busy mode, etc.), the next access is handled as an incrementing burst of
unspecified length.
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Figure 33-3. Read Burst SDRAM Access
tRCD
CAS
SDCS
SDCK
SDRAMC_A[12:0]
Row n
col a
col b
col c
col d
col e
col f
RAS
CAS
SDWE
DATA
(Input)
33.6.3
Dna
Dnb
Dnc
Dne
Dnd
Dnf
Border Management
When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAMC
generates a precharge command, activates the new row and initiates a read or write command. To comply with
SDRAM timing parameters, an additional clock cycle is inserted between the precharge and the active command
(tRP) and between the active and the read command (tRCD). Refer to the following figure.
Figure 33-4. Read Burst with Boundary Row Access
tRCD
tRP
CAS
SDCS
SDCK
Row n
SDRAMC_A[12:0]
col a
col b
col c
col d
Row m
col a
col b
col c
col d
col e
RAS
CAS
SDWE
DATA
33.6.4
Dna
Dnb
Dnc
Dma
Dnd
Dmb
Dmc
Dmd
Dme
SDRAM Controller Refresh Cycles
An autorefresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the
SDRAM device and incremented after each autorefresh automatically. The SDRAMC generates these autorefresh
commands periodically. An internal timer is loaded with the value in SDRAMC_TR that indicates the number of clock
cycles between refresh cycles.
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SAM9X60
SDRAM Controller (SDRAMC)
A refresh error interrupt is generated when the previous autorefresh command did not perform. It is acknowledged by
reading the Interrupt Status register (SDRAMC_ISR).
When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if
the processor tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait
signal. Refer to the following figure.
Figure 33-5. Refresh Cycle Followed by a Read Access
tRP
tRFC
tRCD
CAS
SDCS
SDCK
Row n
SDRAMC_A[12:0]
col c
Row m
col d
col a
RAS
CAS
SDWE
DATA
(input)
33.6.5
Dnb
Dnc
Dma
Dnd
Power Management
Three low-power modes are available:
•
•
•
Self-refresh mode: The SDRAM executes its own Autorefresh cycle without control of the SDRAMC. Current
drained by the SDRAM is very low.
Powerdown mode: Autorefresh cycles are controlled by the SDRAMC. Between autorefresh cycles, the SDRAM
is in powerdown. Current drained in Powerdown mode is higher than in Self-refresh Mode.
Deep Powerdown mode (only available with Mobile SDRAM): The SDRAM contents are lost, but the SDRAM
does not drain any current.
The SDRAMC activates one low-power mode as soon as the SDRAM device is not selected. It is possible to delay
the entry in Self-refresh and Powerdown modes after the last access by programming a timeout value in the
SDRAMC_LPR.
33.6.5.1 Self-refresh Mode
This mode is selected by configuring SDRAMC_LPR.LPCB to 1. In Self-refresh mode, the SDRAM device retains
data without external clocking and provides its own internal clocking, thus performing its own autorefresh cycles. All
the inputs to the SDRAM device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM
device is selected, the SDRAMC provides a sequence of commands and exits Self-refresh mode.
Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one-quarter or a half quarter or all banks of the
SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated
Self-Refresh (TCSR), Partial Array Self-Refresh (PASR) and Drive Strength (DS) must be set in the SDRAMC_LPR
and transmitted to the low-power SDRAM during initialization.
After initialization, as soon as the PASR/DS/TCSR fields are modified and Self-refresh mode is activated, the
Extended Mode register is accessed automatically and the PASR/DS/TCSR bits are updated before entry into Selfrefresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.
The SDRAM device must remain in Self-refresh mode for a minimum period of tRAS and may remain in Self-refresh
mode for an indefinite period. Refer to the following figure.
Upon exiting Self-refresh mode, an autorefresh command can be issued immediately after tXSR by setting the bit
SELFAUTO to 1 (refer to the SDRAMC Low-Power Register). Otherwise, an active command is issued immediately
after tXSR and an autorefresh command is issued every 7.81 μs or 15.6 μs.
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Complete Datasheet
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SAM9X60
SDRAM Controller (SDRAMC)
Note: Some SDRAM providers impose some cycles of burst autorefresh immediately before self-refresh entry and
immediately after self-refresh exit. For example, a SDRAM with 4096 rows will impose 4096 cycles of burst
autorefresh. This constraint is not supported.
Figure 33-6. Self-refresh Mode Behavior
Self-refresh Mode
tXSR
LPCB = 1
Write
SDRAMC_LPR
Row
SDRAMC_A[12:0]
SDCK
SDCKE
SDCS
RAS
CAS
SDWE
Access Request
to the SDRAM Controller
33.6.5.2 Low-power Mode
This mode is selected by configuring SDRAMC_LPR.LPCB to 2. Power consumption is greater than in Self-refresh
mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In
contrast to Self-refresh mode, the SDRAM device cannot remain in Low-power mode longer than the refresh period
(64 ms for a whole device refresh operation). As no autorefresh operations are performed by the SDRAM itself, the
SDRAMC carries out the refresh operation. The exit procedure is faster than in Self-refresh mode.
Refer to the following figure.
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SAM9X60
SDRAM Controller (SDRAMC)
Figure 33-7. Low-power Mode Behavior
CAS
tRCD
Low-power Mode
SDCS
SDCK
SDRAMC_A[12:0]
Row n
col a
col b
col c
col d
col e
col f
RAS
CAS
SDCKE
DATA
(input)
Dna
Dnb
Dnc
Dnd
Dne
Dnf
33.6.5.3 Deep Powerdown Mode
This mode is selected by configuring SDRAMC_LPR.LPCB to 3. When this mode is activated, all internal voltage
generators inside the SDRAM are stopped and all data is lost.
When this mode is enabled, the application must not access the SDRAM until a new initialization sequence is done
(see “SDRAM Device Initialization”).
Refer to the following figure.
Figure 33-8. Deep Powerdown Mode Behavior
tRP
SDCS
SDCK
Row n
SDRAMC_A[12:0]
col c
col d
RAS
CAS
SDWE
CKE
DATA
(input)
© 2020 Microchip Technology Inc.
Dnb
Dnc
Dnd
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SAM9X60
SDRAM Controller (SDRAMC)
33.6.6
Scrambling/Unscrambling Function
The external data bus can be scrambled in order to prevent intellectual property data located in off-chip memories
from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling/unscrambling function can be enabled or disabled by configuring the SDR_SE bit in the OCMS
register (SDRAMC_OCMS). This bit cannot be reconfigured as long as the external memory device is powered.
The scrambling method depends on two user-configurable key registers, SDRAMC_OCMS_KEY1 and
SDRAMC_OCMS_KEY2 plus a random value depending on device processing characteristics. These key registers
are only accessible in Write mode.
The scrambling user key or the seed for key generation must be securely stored in a reliable nonvolatile memory in
order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key
is lost.
When multiple chip selects are handled, it is possible to configure the scrambling function per chip select using the
OCMS field in the SDRAMC_OCMS registers.
33.6.7
Clearing Scrambling Keys on Tamper Event
On tamper detection event on WKUP pins, it is possible to perform an immediate clear of the scrambling keys
(SDRAMC_OCMS_KEY1 and SDRAMC_OCMS_KEY2) if bit SDRAMC_OCMS.TAMPCLR = 1.
33.6.8
Interface with Multiplexed Data/Address Lines and Data/Address/Command Lines
This feature takes advantage of the SDRAM protocol to reduce the pin count by multiplexing address and data lines
or address, data and command lines. Up to 16 lines can be reduced depending on the configuration of the SDRAM.
Using this feature reduces the efficiency of the SDRAM by adding one clock cycle during write access.
When address, data and command lines are multiplexed, as SDA10 is multiplexed, refresh operations increase the
latency. It is not possible to perform an access to another device during auto-refresh process.
Figure 33-9. Multiplexed Address/Data, Connection to 1x16 SDRAM Interface
SDRAM
Device
DQM[0]
DQML
DQM[1]
DQMH
D[15:0]
DQ[15:0]/ADDR/BA
RAS/CAS/WE/SDA10
RAS/CAS/WE/A10
CLK/CKE/SDCS
CLK/CKE/CS
Figure 33-10. Multiplexed Address/Data/Command, Connection to 1x16 SDRAM Interface
SDRAM
Device
DQM[0]
DQML
DQM[1]
DQMH
D[15:0]
DQ[15:0]/ADDR/BA
RAS/CAS/WE/A10
CLK/CKE/SDCS
CLK/CKE/CS
Table 33-8. 16-Mbit SDR-SDRAM, 512k*16* 2 Banks: Multiplexed Address/Data
D15 D14 D13 D12
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D11
D10
D9
D8
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D7
D6
D5
D4
D3
D2
D1
D0
DS60001579C-page 575
SAM9X60
SDRAM Controller (SDRAMC)
CLK, CKE, SDCS, DM[1:0], RAS, CAS, WE
–
–
–
–
BK
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Table 33-9. 16-Mbit SDR-SDRAM, 512k*16* 2 Banks: Multiplexed Address/Data/Command
CLK, CKE, SDCS, DM[1:0]
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RAS CAS WE
BK
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
–
Table 33-10. 64-Mbit SDR-SDRAM, 1 Meg*16* 4 Banks, 128-Mbit SDR-SDRAM, 2 Meg*16* 4 Banks:
Multiplexed Address/Data
D15 D14 D13 D12
CLK, CKE, SDCS, DM[1:0], RAS, CAS, WE
–
–
BK
BK
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Table 33-11. 64-Mbit SDR-SDRAM, 1 Meg*16* 4 Banks, 128-Mbit SDR-SDRAM, 2 Meg*16* 4 Banks: Multiplexed
Address/Data/ Command
CLK, CKE, SDCS, DM[1:0], RAS
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CAS WE
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BK
BK
Table 33-12. 256-Mbit SDR-SDRAM, 4 Meg*16* 4 Banks: Multiplexed Address/Data
D15 D14 D13 D12
CLK, CKE, SDCS, DM[1:0], RAS, CAS, WE
–
BK
BK
A12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Table 33-13. 256-Mbit SDR-SDRAM, 4 Meg*16* 4 Banks: Multiplexed Address/Data/Command
CLK, CKE, SDCS, DM[1:0], RAS, CAS
33.6.9
D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WE
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BK
A13
A12
Register Write Protection
To prevent any single software error from corrupting SDRAMC behavior, some registers in the address space can be
write-protected by setting the WPEN and WPITEN bits in the SDRAMC Write Protection Mode Register
(SDRAMC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the SDRAMC Write Protection Status
Register (SDRAMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the SDRAMC_WPSR.
The following registers can be write-protected:
•
•
•
•
•
•
•
•
SDRAMC Mode Register
SDRAMC Refresh Timer Register
SDRAMC Configuration Register
SDRAMC Memory Device Register
SDRAMC Configuration Register 1
SDRAMC OCMS Register
SDRAMC OCMS KEY1 Register
SDRAMC OCMS KEY2 Register
The following registers can be write-protected when WPITEN is enabled:
• SDRAMC Interrupt Enable Register
• SDRAMC Interrupt Disable Register
33.6.10 Security and Safety Analysis and Reports
Several types of checks are performed when the SDRAMC is accessing the memory device.
The peripheral clock of the SDRAMC is monitored by specific circuitry to detect abnormal waveforms on the internal
clock net that may affect the behavior of the SDRAMC. Corruption on the triggering edge of the clock or a pulse with
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Complete Datasheet
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SAM9X60
SDRAM Controller (SDRAMC)
a minimum duration may be identified. If the flag SDRAMC_WPSR.CGD is set, an abnormal condition occurred on
the peripheral clock. This flag is not set under normal operating conditions.
The internal sequencer of the SDRAMC is also monitored and if an abnormal state is detected, the flag
SDRAMC_WPSR.SEQE is set. This flag is not set under normal operating conditions.
The software accesses to the SDRAMC are monitored and if an incorrect access is performed, the flag
SDRAMC_WPSR.SWE is set. The type of incorrect/abnormal software access is reported in the
SDRAMC_WPSR.SWETYP field (see 33.7.15 SDRAMC_WPSR for details) , e.g. , writing a new configuration
(SDRAMC_CR, SDRAMC_CFR1, SDRAMC_HSR, SDRAMC_OCMS, SDRAMC_KEY1/2) after the initializat ion of
the SDRAMC ( i .e. , i f SDRAMC_TR.COUNT > 0) i s an er ror . SDRAMC_WPSR.ECLASS is an indicator reporting
the criticality of the SWETYP report.
The flags CGD, SEQE, SWE and WPVS are automatically cleared when SDRAMC_WPSR is read.
If one of these flags is set, the flag SDRAMC_ISR.SECE is set and can trigger an interrupt if the
SDRAMC_IMR.SECE bit is ‘1’. SECE is cleared by reading SDRAMC_ISR.
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SAM9X60
SDRAM Controller (SDRAMC)
33.7
Register Summary
Offset
Name
0x00
SDRAMC_MR
0x04
0x08
0x0C
...
0x0F
SDRAMC_TR
SDRAMC_CR
SDRAMC_LPR
0x14
SDRAMC_IER
0x1C
0x20
0x24
0x28
0x2C
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
5
4
3
2
1
0
MODE[2:0]
COUNT[11:8]
COUNT[7:0]
DBW
TXSR[3:0]
TRCD[3:0]
TRC_TRFC[3:0]
CAS[1:0]
TRAS[3:0]
TRP[3:0]
TWR[3:0]
NB
NR[1:0]
NC[1:0]
Reserved
0x10
0x18
Bit Pos.
SDRAMC_IDR
SDRAMC_IMR
SDRAMC_ISR
SDRAMC_MDR
SDRAMC_CFR1
SDRAMC_OCMS
0x30
SDRAMC_OCMS_K
EY1
0x34
SDRAMC_OCMS_K
EY2
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
SELFAUTO
TIMEOUT[1:0]
PASR[2:0]
SELFDONE
TCSR[1:0]
LPCB[1:0]
DS[1:0]
SECE
RES
SECE
RES
SECE
RES
SECE
RES
SHIFT_SAMPLING[1:0]
MD[1:0]
CMD_MUX
TAMPCLR
KEY1[31:24]
KEY1[23:16]
KEY1[15:8]
KEY1[7:0]
KEY2[31:24]
KEY2[23:16]
KEY2[15:8]
KEY2[7:0]
Complete Datasheet
ADD_DATA_
MUX
TMRD[3:0]
UNAL
SDR_SE
DS60001579C-page 578
SAM9X60
SDRAM Controller (SDRAMC)
...........continued
Offset
Name
0x38
...
0x3B
Reserved
0x3C
0x40
SDRAMC_WPMR
SDRAMC_WPSR
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
5
4
3
2
1
0
WPITEN
SWETYP[2:0]
WPEN
CGD
WPEN
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
ECLASS
© 2020 Microchip Technology Inc.
WPVSRC[7:0]
SWE
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DS60001579C-page 579
SAM9X60
SDRAM Controller (SDRAMC)
33.7.1
SDRAMC Mode Register
Name:
Offset:
Reset:
Property:
SDRAMC_MR
0x00
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MODE[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
Bits 2:0 – MODE[2:0] SDRAMC Command Mode
This field defines the command issued by the SDRAMC when the SDRAM device is accessed.
Value
Name
Description
0
NORMAL
Normal mode. Any access to the SDRAM is decoded normally. To activate
this mode, the command must be followed by a write to the SDRAM.
1
NOP
The SDRAMC issues a NOP command when the SDRAM device is
accessed regardless of the cycle. To activate this mode, the command
must be followed by a write to the SDRAM.
2
ALLBANKS_PRECHARGE The SDRAMC issues an “All Banks Precharge” command when the
SDRAM device is accessed regardless of the cycle. To activate this mode,
the command must be followed by a write to the SDRAM.
3
LOAD_MODEREG
The SDRAMC issues a “Load Mode Register” command when the
SDRAM device is accessed regardless of the cycle. To activate this mode,
the command must be followed by a write to the SDRAM.
4
AUTO_REFRESH
The SDRAMC issues an “Autorefresh” Command when the SDRAM
device is accessed regardless of the cycle. Previously, an “All Banks
Precharge” command must be issued. To activate this mode, the
command must be followed by a write to the SDRAM.
5
EXT_LOAD_MODEREG
The SDRAMC issues an “Extended Load Mode Register” command when
the SDRAM device is accessed regardless of the cycle. To activate this
mode, the “Extended Load Mode Register” command must be followed by
a write to the SDRAM. The write in the SDRAM must be done in the
appropriate bank; most low-power SDRAM devices use the bank 1.
6
DEEP_POWERDOWN
Deep Powerdown mode. Enters Deep Powerdown mode.
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SAM9X60
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33.7.2
SDRAMC Refresh Timer Register
Name:
Offset:
Reset:
Property:
SDRAMC_TR
0x04
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
4
3
COUNT[7:0]
R/W
R/W
0
0
9
COUNT[11:8]
R/W
R/W
0
0
8
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – COUNT[11:0] SDRAMC Refresh Timer Count
This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a
refresh burst is initiated. The SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz
frequency, the Refresh Timer Counter Register must be set with the value 1562 (15.625 μs x 100 MHz) or 781 (7.81
μs x 100 MHz).
To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is
issued and no refresh of the SDRAM device is carried out.
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Complete Datasheet
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SAM9X60
SDRAM Controller (SDRAMC)
33.7.3
SDRAMC Configuration Register
Name:
Offset:
Reset:
Property:
SDRAMC_CR
0x08
0x852372C0
Read/Write
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
1
17
16
R/W
1
R/W
1
9
8
R/W
0
R/W
1
R/W
0
2
1
TXSR[3:0]
Access
Reset
Bit
R/W
1
R/W
0
23
22
TRAS[3:0]
R/W
0
R/W
0
R/W
0
R/W
1
21
20
19
18
TRCD[3:0]
Access
Reset
Bit
R/W
0
15
Access
Reset
R/W
0
Bit
7
DBW
R/W
1
Access
Reset
R/W
0
TRP[3:0]
R/W
1
14
13
TRC_TRFC[3:0]
R/W
R/W
1
1
6
5
CAS[1:0]
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
12
11
10
TWR[3:0]
R/W
1
R/W
0
4
NB
R/W
0
3
NR[1:0]
R/W
0
0
NC[1:0]
R/W
0
R/W
0
R/W
0
Bits 31:28 – TXSR[3:0] Exit Self-Refresh to Active Delay
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles
is between 0 and 15.
Bits 27:24 – TRAS[3:0] Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number
of cycles is between 0 and 15.
Bits 23:20 – TRCD[3:0] Row to Column Delay
Reset value is two cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles.
Number of cycles is between 0 and 15.
Bits 19:16 – TRP[3:0] Row Precharge Delay
Reset value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of
cycles is between 0 and 15.
Bits 15:12 – TRC_TRFC[3:0] Row Cycle Delay and Row Refresh Cycle
Reset value is seven cycles.
This field defines two timings:
• the delay (tRFC) between two Refresh commands and between a Refresh command and an Activate command
• the delay (tRC) between two Active commands in number of cycles.
The number of cycles is between 0 and 15. The end user must program max {tRC, tRFC}.
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Complete Datasheet
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SAM9X60
SDRAM Controller (SDRAMC)
Bits 11:8 – TWR[3:0] Write Recovery Delay
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
Bit 7 – DBW Data Bus Width
Reset value is 16 bits.
Value
Description
0
Data bus width is 32 bits.
1
Data bus width is 16 bits.
Bits 6:5 – CAS[1:0] CAS Latency
Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles is managed.
Value
Name
Description
0
–
Reserved
1
–
Reserved
2
LATENCY2
2-cycle latency
3
LATENCY3
3-cycle latency
Bit 4 – NB Number of Banks
Reset value is two banks.
Value
Name
0
BANK2
1
BANK4
Description
2 banks
4 banks
Bits 3:2 – NR[1:0] Number of Row Bits
Reset value is 11 row bits.
Value
Name
Description
0
ROW11
11 bits to define the row number, up to 2048 rows
1
ROW12
12 bits to define the row number, up to 4096 rows
2
ROW13
13 bits to define the row number, up to 8192 rows
3
Reserved
Bits 1:0 – NC[1:0] Number of Column Bits
Reset value is 8 column bits.
Value
Name
Description
0
COL8
8 bits to define the column number, up to 256 columns.
1
COL9
9 bits to define the column number, up to 512 columns.
2
COL10
10 bits to define the column number, up to 1024 columns.
3
COL11
11 bits to define the column number, up to 2048 columns.
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Complete Datasheet
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SAM9X60
SDRAM Controller (SDRAMC)
33.7.4
SDRAMC Low-Power Register
Name:
Offset:
Reset:
Property:
Bit
SDRAMC_LPR
0x10
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SELFDONE
R/W
0
15
14
SELFAUTO
R/W
0
10
9
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
R/W
0
13
12
TIMEOUT[1:0]
R/W
R/W
0
0
5
PASR[2:0]
R/W
0
11
DS[1:0]
R/W
0
R/W
0
R/W
0
3
2
1
4
8
TCSR[1:0]
R/W
0
0
LPCB[1:0]
R/W
0
R/W
0
R/W
0
Bit 16 – SELFDONE Self-refresh Done (read-only)
This bit indicates that the external device is in Self-refresh mode.
Bit 14 – SELFAUTO Self-refresh Exit Autorefresh
Value
Description
1
Upon exiting Self-refresh mode, autorefresh command is immediately performed after tXSR.
0
Upon exiting Self-refresh mode, active command is immediately performed after tXSR. The autorefresh
command is issued every 15.6 μs or less.
Bits 13:12 – TIMEOUT[1:0] Time to Define When Low-power Mode Is Enabled
Value
Name
Description
0
LP_LAST_XFER
The SDRAMC activates the SDRAM Low-power mode immediately after the
end of the last transfer.
1
LP_LAST_XFER_64 The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the
end of the last transfer.
2
LP_LAST_XFER_128 The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after
the end of the last transfer.
3
Reserved
Bits 11:10 – DS[1:0] Drive Strength (only for low-power SDRAM)
DS is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter
must be set according to the SDRAM device specification.
After initialization, as soon as the DS field is modified and Self-refresh mode is activated, the Extended Mode
Register is accessed automatically and DS bits are updated before entry in Self-refresh mode. This feature is not
supported when SDRAMC shares an external bus with another controller.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 584
SAM9X60
SDRAM Controller (SDRAMC)
Bits 9:8 – TCSR[1:0] Temperature Compensated Self-Refresh (only for low-power SDRAM)
TCSR is transmitted to the SDRAM during initialization to set the refresh interval during Self-refresh mode depending
on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device
specification.
After initialization, as soon as the TCSR field is modified and Self-refresh mode is activated, the Extended Mode
Register is accessed automatically and TCSR bits are updated before entry in Self-refresh mode. This feature is not
supported when SDRAMC shares an external bus with another controller.
Bits 6:4 – PASR[2:0] Partial Array Self-refresh (only for low-power SDRAM)
PASR is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of
the SDRAM array are enabled. Disabled banks are not refreshed in Self-refresh mode. This parameter must be set
according to the SDRAM device specification.
After initialization, as soon as the PASR field is modified and Self-refresh mode is activated, the Extended Mode
Register is accessed automatically and PASR bits are updated before entry in Self-refresh mode. This feature is not
supported when SDRAMC shares an external bus with another controller.
Bits 1:0 – LPCB[1:0] Low-power Configuration Bits
Value
Name
Description
0
DISABLED
The low-power feature is inhibited: no Powerdown, Self-refresh or Deep
Powerdown command is issued to the SDRAM device.
1
SELF_REFRESH
The SDRAMC issues a Self-refresh command to the SDRAM device, the
SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM
device leaves the Self-refresh mode when accessed and enters it after the
access.
2
POWER_DOWN
The SDRAMC issues a Powerdown Command to the SDRAM device after
each access, the SDCKE signal is set to low. The SDRAM device leaves the
Powerdown mode when accessed and enters it after the access.
3
DEEP_POWER_DOWN The SDRAMC issues a Deep Powerdown command to the SDRAM device.
This mode is unique to low-power SDRAM.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 585
SAM9X60
SDRAM Controller (SDRAMC)
33.7.5
SDRAMC Interrupt Enable Register
Name:
Offset:
Reset:
Property:
SDRAMC_IER
0x14
–
Write-only
This register can only be written if the WPITEN bit is cleared in the SDRAMC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SECE
W
–
0
RES
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – SECE Security and/or Safety Event Interrupt Enable
Bit 0 – RES Refresh Error Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 586
SAM9X60
SDRAM Controller (SDRAMC)
33.7.6
SDRAMC Interrupt Disable Register
Name:
Offset:
Property:
SDRAMC_IDR
0x18
Write-only
This register can only be written if the WPITEN bit is cleared in the SDRAMC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SECE
W
0
RES
W
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – SECE Security and/or Safety Event Interrupt Disable
Bit 0 – RES Refresh Error Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 587
SAM9X60
SDRAM Controller (SDRAMC)
33.7.7
SDRAMC Interrupt Mask Register
Name:
Offset:
Reset:
Property:
Bit
SDRAMC_IMR
0x1C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SECE
W
0
0
RES
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – SECE Security and/or Safety Event Interrupt Mask
Value
Description
0
The security and/or safety event interrupt is disabled.
1
The security and/or safety event interrupt is enabled.
Bit 0 – RES Refresh Error Interrupt Mask
Value
Description
0
The refresh error interrupt is disabled.
1
The refresh error interrupt is enabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 588
SAM9X60
SDRAM Controller (SDRAMC)
33.7.8
SDRAMC Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
SDRAMC_ISR
0x20
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SECE
W
0
0
RES
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – SECE Security and/or Safety Event Event (cleared on read)
Value
Description
0
There is no security report in SDRAMC_WPSR.
1
One security flag is set in SDRAMC_WPSR.
Bit 0 – RES Refresh Error Status (cleared on read)
Value
Description
0
No refresh error has been detected since the register was last read.
1
A refresh error has been detected since the register was last read.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 589
SAM9X60
SDRAM Controller (SDRAMC)
33.7.9
SDRAMC Memory Device Register
Name:
Offset:
Reset:
Property:
SDRAMC_MDR
0x24
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
3
2
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
5
4
SHIFT_SAMPLING[1:0]
R/W
R/W
0
0
0
MD[1:0]
R/W
0
R/W
0
Bits 5:4 – SHIFT_SAMPLING[1:0] Shift Sampling Point of Data
Shifts the sampling point of data coming from the memory device. The higher the memory device clock frequency, the
higher the SHIFT_SAMPLING value. Refer to the section "Electrical Characteristics".
Value
Name
Description
0
–
Reserved.
1
SHIFT_ONE_CYCLE
Sampling point is shifted by one cycle.
2
SHIFT_TWO_CYCLES
Sampling point is shifted by two cycles.
3
SHIFT_THREE_CYCLES
Sampling point is shifted by three cycles.
Bits 1:0 – MD[1:0] Memory Device Type
Value
Name
0
SDRAM
1
LPSDRAM
2
–
3
–
© 2020 Microchip Technology Inc.
Description
SDRAM
Low-power SDRAM
Reserved
Reserved
Complete Datasheet
DS60001579C-page 590
SAM9X60
SDRAM Controller (SDRAMC)
33.7.10 SDRAMC Configuration Register 1
Name:
Offset:
Reset:
Property:
SDRAMC_CFR1
0x28
0x00000002
Read/Write
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
CMD_MUX
9
8
UNAL
R/W
0
10
ADD_DATA_M
UX
R/W
0
3
2
1
0
R/W
1
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
5
4
R/W
0
TMRD[3:0]
Access
Reset
R/W
0
R/W
0
Bit 11 – CMD_MUX Commands are Multiplexed with Address and Data
To use this feature, ADD_DATA_MUX must be set to ‘1’. This feature allows to reduce the number of pins.
Value
Name
Description
0
UNSUPPORTED
Commands are not multiplexed with address and data.
1
SUPPORTED
Commands are multiplexed with address and data.
Bit 10 – ADD_DATA_MUX Multiplexed Address and Data
.This feature allows to reduce the number of pins.
Value
Name
Description
0
UNSUPPORTED
Data and address are not multiplexed
1
SUPPORTED
Data and address are multiplexed
Bit 8 – UNAL Always written to 1
This bit must be always written to 1.
Bits 3:0 – TMRD[3:0] Load Mode Register Command to Active or Refresh Command
This field defines the delay between a “Load Mode Register” command and an active or refresh command in number
of cycles. Number of cycles is between 0 and 15.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 591
SAM9X60
SDRAM Controller (SDRAMC)
33.7.11 SDRAMC OCMS Register
Name:
Offset:
Reset:
Property:
SDRAMC_OCMS
0x2C
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
TAMPCLR
R/W
0
3
2
1
0
SDR_SE
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – TAMPCLR Tamper Clear Enable
Value
Description
0
A tamper detection event has no effect on SDRAMC scrambling keys.
1
A tamper detection event immediately clears SDRAMC scrambling keys.
Bit 0 – SDR_SE SDRAM Memory Controller Scrambling Enable
Value
Description
0
Disables off-chip scrambling for SDR-SDRAM access.
1
Enables off-chip scrambling for SDR-SDRAM access.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 592
SAM9X60
SDRAM Controller (SDRAMC)
33.7.12 SDRAMC OCMS KEY1 Register
Name:
Offset:
Property:
SDRAMC_OCMS_KEY1
0x30
Write-only
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
W
W
W
W
19
18
17
16
W
W
W
W
11
10
9
8
W
W
W
W
3
2
1
0
W
W
W
W
KEY1[31:24]
Access
Reset
W
W
W
W
Bit
23
22
21
20
KEY1[23:16]
Access
Reset
W
W
W
W
Bit
15
14
13
12
KEY1[15:8]
Access
Reset
W
W
W
W
Bit
7
6
5
4
KEY1[7:0]
Access
Reset
W
W
W
W
Bits 31:0 – KEY1[31:0] Off-chip Memory Scrambling (OCMS) Key Part 1
When off-chip memory scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 593
SAM9X60
SDRAM Controller (SDRAMC)
33.7.13 SDRAMC OCMS KEY2 Register
Name:
Offset:
Reset:
Property:
SDRAMC_OCMS_KEY2
0x34
–
Write-only
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
W
–
W
–
W
–
W
–
19
18
17
16
W
–
W
–
W
–
W
–
11
10
9
8
W
–
W
–
W
–
W
–
3
2
1
0
W
–
W
–
W
–
W
–
KEY2[31:24]
Access
Reset
W
–
W
–
W
–
W
–
Bit
23
22
21
20
KEY2[23:16]
Access
Reset
W
–
W
–
W
–
W
–
Bit
15
14
13
12
KEY2[15:8]
Access
Reset
W
–
W
–
W
–
W
–
Bit
7
6
5
4
KEY2[7:0]
Access
Reset
W
–
W
–
W
–
W
–
Bits 31:0 – KEY2[31:0] Off-chip Memory Scrambling (OCMS) Key Part 2
When off-chip memory scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 594
SAM9X60
SDRAM Controller (SDRAMC)
33.7.14 SDRAMC Write Protection Mode Register
Name:
Offset:
Reset:
Property:
SDRAMC_WPMR
0x3C
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
WPITEN
R/W
0
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x534452 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads
as 0.
Bit 1 – WPITEN Write Protection Interrupt Enable
Value
Description
0
Disables the write protection of SDRAMC_IER/IDR if WPKEY corresponds to 0x534452 (SDR in
ASCII).
1
Enables the write protection of SDRAMC_IER/IDR if WPKEY corresponds to 0x534452 (SDR in
ASCII).
Bit 0 – WPEN Write Protection Enable
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x534452 ("SDR" in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x534452 ("SDR" in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 595
SAM9X60
SDRAM Controller (SDRAMC)
33.7.15 SDRAMC Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
SDRAMC_WPSR
0x40
0x00000000
Read-only
31
ECLASS
R
0
30
23
22
21
20
Bit
15
14
13
Access
Reset
R
0
R
0
Bit
7
6
Access
Reset
Bit
29
28
27
26
24
R
0
25
SWETYP[2:0]
R
0
19
18
17
16
10
9
8
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
5
4
2
SEQE
R
0
1
CGD
R
0
0
WPEN
R
0
R
0
Access
Reset
Access
Reset
3
SWE
R
0
Bit 31 – ECLASS Software Error Class (cleared on read)
Value
Name
Description
0
WARNING An abnormal access is performed but it does not affect system functionality.
1
ERROR
An access is performed into some registers after memory device initialization sequence.
Bits 26:24 – SWETYP[2:0] Software Error Type (cleared on read)
Value
Name
Description
0
READ_WO
A write-only register has been read (Warning).
1
WRITE_RO
A write access has been performed on a read-only register (Warning).
2
UNDEF_RW
Access to an undefined address (Warning).
3
W_AFTER_INIT Write access performed into some configuration registers after memory device
initialization, i.e. if SDRAMC_TR.COUNT > 0 (Error).
Bits 15:8 – WPVSRC[7:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
When WPVS=0 and SWE=1, WPVSRC reports the address of the incorrect software access. As soon as WPVS=1,
WPVSRC returns the address of the write-protected violation.
Bit 3 – SWE Software Control Error (cleared on read)
Value
Description
0
No software error has occurred since the last read of SDRAMC_WPSR.
1
A software error has occurred since the last read of SDRAMC_WPSR. The field SWETYP details the
type of software error; the associated incorrect software access is reported in the field WPVSRC (if
WPVS=0).
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
Value
Description
0
No peripheral internal sequencer error has occurred since the last read of SDRAMC_WPSR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 596
SAM9X60
SDRAM Controller (SDRAMC)
Value
1
Description
A peripheral internal sequencer error has occurred since the last read of SDRAMC_WPSR. This flag
can only be set under abnormal operating conditions.
Bit 1 – CGD Clock Glitch Detected (cleared on read)
Value
Description
0
The clock monitoring circuitry has not been corrupted since the last read of SDRAMC_WPSR. Under
normal operating conditions, this bit is always cleared.
1
The clock monitoring circuitry has been corrupted since the last read of SDRAMC_WPSR. This flag
can only be set in case of an abnormal clock signal waveform (glitch).
Bit 0 – WPEN Write Protection Violation Status
Value
Description
0
No write protection violation has occurred since the last read of the QSPI_WPSR.
1
A write protection violation has occurred since the last read of the QSPI_WPSR. If this violation is an
unauthorized attempt to write a protected register, the associated violation is reported into field
WPVSRC.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 597
SAM9X60
Static Memory Controller (SMC)
34.
Static Memory Controller (SMC)
34.1
Description
The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or
peripheral devices. It has six Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to
interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and
peripheral interfacing. Read and write signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with
an automatic Slow Clock mode. In Slow Clock mode, it switches from user-programmed waveforms to slow-rate
specific waveforms on read and write signals. The SMC supports asynchronous burst read in Page mode access for
page size up to 32 bytes.
34.2
Embedded Characteristics
•
•
•
•
•
•
•
•
•
•
•
•
34.3
Six Chip Selects Available
64-Mbyte Address Space per Chip Select
8-, 16- or 32-bit Data Bus
Word, Halfword, Byte Transfers
Byte Write or Byte Select Lines
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
Compliant with LCD Module
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
I/O Lines Description
Table 34-1. I/O Lines Description
Name
Description
Type
Active Level
NCS[5:0]
Static Memory Controller Chip Select Lines
Output
Low
NRD
Read Signal
Output
Low
NWR0/NWE
Write 0/Write Enable Signal
Output
Low
A0/NBS0
Address Bit 0/Byte 0 Select Signal
Output
Low
NWR1/NBS1
Write 1/Byte 1 Select Signal
Output
Low
A1/NWR2/NBS2
Address Bit 1/Write 2/Byte 2 Select Signal
Output
Low
NWR3/NBS3
Write 3/Byte 3 Select Signal
Output
Low
A[25:2]
Address Bus
Output
–
D[31:0]
Data Bus
I/O
–
NWAIT
External Wait Signal
Input
Low
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 598
SAM9X60
Static Memory Controller (SMC)
34.4
Interrupt Source
The SMC has an interrupt line connected to the interrupt line of the external bus interface. The external bus interface
(SMC, SDRAMC, MPDDRC) interrupt line is connected to the interrupt controller. The external bus interface interrupt
line can be triggered by SMC or SDRAMC/MPDDRC.
34.5
Multiplexed Signals
Table 34-2. Static Memory Controller (SMC) Multiplexed Signals
34.6
34.6.1
Multiplexed Signals
Related Function
NWR0
NWE
–
Byte-write or byte-select access, see Byte Write or Byte Select Access
A0
NBS0
–
8-bit or 16-/32-bit data bus, see Data Bus Width
NWR1
NBS1
–
Byte-write or byte-select access, see Byte Write or Byte Select Access
A1
NWR2
NBS2
8-/16-bit or 32-bit data bus, see Data Bus Width.
Byte-write or byte-select access, see Byte Write or Byte Select Access
NWR3
NBS3
–
Byte-write or byte-select access, see Byte Write or Byte Select Access
Application Example
Hardware Interface
Figure 34-1. SMC Connections to Static Memory Devices
D0-D31
A0/NBS0
NWR0/NWE
NWR1/NBS1
A1/NWR2/NBS2
NWR3/NBS3
D0 - D7
128K x 8
SRAM
D8-D15
D0 - D7
CS
NRD
D0-D7
CS
A0 - A16
NWR0/NWE
128K x 8
SRAM
A2 - A18
A0 - A16
NRD
OE
NWR1/NBS1
WE
A2 - A18
OE
WE
NCS[n..0]
128K x 8
SRAM
D16 - D23
A2 - A25
D24-D31
D0 - D7
A0 - A16
NRD
Static Memory
Controller
© 2020 Microchip Technology Inc.
D0-D7
CS
CS
A1/NWR2/NBS2
128K x 8
SRAM
A2 - A18
A2 - A18
A0 - A16
NRD
OE
WE
OE
NWR3/NBS3
Complete Datasheet
WE
DS60001579C-page 599
SAM9X60
Static Memory Controller (SMC)
34.7
34.7.1
Product Dependencies
I/O Lines
The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer
must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O
Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller.
34.8
External Memory Mapping
The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of
memory.
If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears
to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page
(see the figure below).
A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for 32-bit memory.
Figure 34-2. Memory Connections for Eight External Devices
NCS[0] - NCS[n]
NRD
SMC
NCSn
NWE
NCS...
A[25:0]
NCS3
D[31:0]
NCS2
NCS1
NCS0
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[25:0]
8 or 16 or 32
34.9
Connection to External Devices
34.9.1
Data Bus Width
D[31:0] or D[15:0] or
D[7:0]
A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is controlled by the field DBW in
SMC_MODE (Mode register) for the corresponding chip select.
•
•
•
34.9.2
Figure 34-3 illustrates how to connect a 512K x 8-bit memory on NCS2.
Figure 34-4 illustrates how to connect a 512K x 16-bit memory on NCS2.
Figure 34-5 shows two 16-bit memories connected as a single 32-bit memory.
Byte Write or Byte Select Access
Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write
or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip
select.
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SAM9X60
Static Memory Controller (SMC)
Figure 34-3. Memory Connection for an 8-bit Data Bus
D[7:0]
D[7:0]
A[18:2]
A[18:2]
SMC
A0
A0
A1
A1
NWE
Write Enable
NRD
Output Enable
NCS[2]
Memory Enable
Figure 34-4. Memory Connection for a 16-bit Data Bus
D[15:0]
D[15:0]
A[19:2]
A[18:1]
A1
SMC
A[0]
NBS0
Low Byte Enable
NBS1
High Byte Enable
NWE
Write Enable
NRD
Output Enable
Memory Enable
NCS[2]
Figure 34-5. Memory Connection for a 32-bit Data Bus
D[31:16]
D[31:16]
SMC
D[15:0]
D[15:0]
A[20:2]
A[18:0]
NBS0
Byte 0 Enable
NBS1
Byte 1 Enable
NBS2
Byte 2 Enable
NBS3
Byte 3 Enable
NWE
Write Enable
NRD
Output Enable
NCS[2]
Memory Enable
34.9.2.1 Byte Write Access
Byte write access supports one byte write signal per byte of the data bus and a single read signal.
Note that the SMC does not allow boot in Byte Write Access mode.
•
•
For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and
byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided.
Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
For 32-bit devices: NWR0, NWR1, NWR2 and NWR3, are the write signals of byte0 (lower byte), byte1, byte2
and byte 3 (upper byte) respectively. One single read signal (NRD) is provided.
Byte Write Access is used to connect 4 x 8-bit devices as a 32-bit memory.
The Byte Write option is illustrated in Figure 34-6.
34.9.2.2 Byte Select Access
In this mode, read/write operations can be enabled/disabled at a byte level. One byte-select line per byte of the data
bus is provided. One NRD and one NWE signal control read and write.
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SAM9X60
Static Memory Controller (SMC)
•
•
For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and
byte1 (upper byte) of a 16-bit bus.
Byte Select Access is used to connect one 16-bit device.
For 32-bit devices: NBS0, NBS1, NBS2 and NBS3, are the selection signals of byte0 (lower byte), byte1, byte2
and byte 3 (upper byte) respectively. Byte Select Access is used to connect two 16-bit devices.
Figure 34-7 shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access mode, on NCS3
(BAT = Byte Select Access).
Figure 34-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option
D[7:0]
D[7:0]
D[15:8]
A[24:2]
SMC
A[23:1]
A[0]
A1
NWR0
Write Enable
NWR1
NRD
Read Enable
Memory Enable
NCS[3]
D[15:8]
A[23:1]
A[0]
Write Enable
Read Enable
Memory Enable
34.9.2.3 Signal Multiplexing
Depending on the byte access type (BAT), only the write signals or the byte select signals are used. To save IOs at
the external bus interface, control signals at the SMC interface are multiplexed. The table below shows signal
multiplexing depending on the data bus width and the byte access type.
Table 34-3. SMC Multiplexed Signal Translation
Signal Name
32-bit Bus
16-bit Bus
8-bit Bus
Device Type
1 x 32-bit
2 x 16-bit
4 x 8-bit
1 x 16-bit
2 x 8-bit
1 x 8-bit
Byte Access Type (BAT)
Byte Select
Byte Select
Byte Write
Byte Select
Byte Write
–
NBS0_A0
NBS0
NBS0
–
NBS0
–
A0
NWE_NWR0
NWE
NWE
NWR0
NWE
NWR0
NWE
NBS1_NWR1
NBS1
NBS1
NWR1
NBS1
NWR1
–
NBS2_NWR2_A1
NBS2
NBS2
NWR2
A1
A1
A1
NBS3_NWR3
NBS3
NBS3
NWR3
–
–
–
For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When the Byte Select
option is selected, NWR1 to NWR3 are unused. When the Byte Write option is selected, NBS0 to NBS3 are unused.
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SAM9X60
Static Memory Controller (SMC)
Figure 34-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option)
D[15:0]
D[15:0]
D[31:16]
A[25:2]
SMC
A[23:0]
NWE
Write Enable
NBS0
Low Byte Enable
NBS1
High Byte Enable
NBS2
NBS3
Read Enable
NRD
Memory Enable
NCS[3]
D[31:16]
A[23:0]
Write Enable
Low Byte Enable
High Byte Enable
Read Enable
Memory Enable
34.10
Standard Read and Write Protocols
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the
same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the
byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as
NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines.
34.10.1 Read Waveforms
The following figure shows the read cycle. The read cycle starts with the address setting on the memory address bus:
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices
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Figure 34-8. Standard Read Cycle
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NRD
NCS
D[31:0]
NRD_SETUP
NCS_RD_SETUP
NRD_PULSE
NRD_HOLD
NCS_RD_PULSE
NCS_RD_HOLD
NRD_CYCLE
34.10.1.1 NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing:
•
•
•
NRD_SETUP—NRD setup time is defined as the setup of address before the NRD falling edge.
NRD_PULSE—NRD pulse length is the time between NRD falling edge and NRD rising edge.
NRD_HOLD—NRD hold time is defined as the hold time of address after the NRD rising edge.
34.10.1.2 NCS Waveform
Similar to the NRD signal, the NCS signal can be divided into a setup time, pulse length and hold time:
•
•
•
NCS_RD_SETUP—NCS setup time is defined as the setup time of address before the NCS falling edge.
NCS_RD_PULSE—NCS pulse length is the time between NCS falling edge and NCS rising edge;
NCS_RD_HOLD—NCS hold time is defined as the hold time of address after the NCS rising edge.
34.10.1.3 Read Cycle
The NRD_CYCLE time is defined as the total duration of the read cycle, that is, from the time where address is set on
the address bus to the point where address may change. The total read cycle time is defined as:
•
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD
as well as
•
NRD_CYCLE = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles.
The NRD_CYCLE field is common to both the NRD and NCS signals, thus the timing period is of the same duration.
NRD_CYCLE, NRD_SETUP, and NRD_PULSE implicitly define the NRD_HOLD value as:
•
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NRD_CYCLE, NCS_RD_SETUP, and NCS_RD_PULSE implicitly define the NCS_RD_HOLD value as:
• NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
34.10.1.4 Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in
case of consecutive read cycles in the same memory. See the following figure.
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Static Memory Controller (SMC)
Figure 34-9. No Setup, No Hold On NRD and NCS Read Signals
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NRD
NCS
D[31:0]
NRD_PULSE
NRD_PULSE
NRD_PULSE
NCS_RD_PULSE
NCS_RD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_CYCLE
NRD_CYCLE
34.10.1.5 Null Pulse
Programming a null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
34.10.2 Read Mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is
available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The
READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD
and NCS controls the read operation.
34.10.2.1 Read is Controlled by NRD (READ_MODE = 1)
The following figure shows the waveforms of a read operation of a typical asynchronous RAM. The read data is
available tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the
READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of
NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of
NRD, whatever the programmed waveform of NCS may be.
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Figure 34-10. READ_MODE = 1 (Data sampled by SMC before rising edge of NRD)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NRD
NCS
tPACC
D[31:0]
Data Sampling
34.10.2.2 Read is Controlled by NCS (READ_MODE = 0)
The following figure shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge
of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that
case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the
rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may
be.
Figure 34-11. READ_MODE = 0 (Data sampled by SMC before rising edge of NCS)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NRD
NCS
tPACC
D[31:0]
Data Sampling
34.10.3 Write Waveforms
The write protocol (depicted in Figure 34-12) is similar to the read protocol. The write cycle starts with the address
setting on the memory address bus.
34.10.3.1 NWE Waveforms
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
•
NWE_SETUP—NWE setup time is defined as the setup of address and data before the NWE falling edge.
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•
•
NWE_PULSE—NWE pulse length is the time between NWE falling edge and NWE rising edge.
NWE_HOLD—NWE hold time is defined as the hold time of address and data after the NWE rising edge.
The NWE waveforms apply to all byte-write lines in Byte Write Access mode: NWR0 to NWR3.
34.10.3.2 NCS Waveforms
The NCS signal waveforms in write operation are not the same that those applied in read operations, but are
separately defined:
•
•
•
NCS_WR_SETUP—NCS setup time is defined as the setup time of address before the NCS falling edge.
NCS_WR_PULSE—NCS pulse length is the time between NCS falling edge and NCS rising edge.
NCS_WR_HOLD—NCS hold time is defined as the hold time of address after the NCS rising edge.
Figure 34-12. Write Cycle
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE
NCS
NWE_SETUP
NCS_WR_SETUP
NWE_PULSE
NWE_HOLD
NCS_WR_PULSE
NCS_WR_HOLD
NWE_CYCLE
34.10.3.3 Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on
the address bus to the point where address may change. The total write cycle time is defined as:
•
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
as well as
•
NWE_CYCLE = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock
cycles. The NWE_CYCLE field is common to both the NWE and NCS signals, thus the timing period is of the same
duration.
NWE_CYCLE, NWE_SETUP, and NWE_PULSE implicitly define the NWE_HOLD value as:
•
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NWE_CYCLE, NCS_WR_SETUP, and NCS_WR_PULSE implicitly define the NCS_WR_HOLD value as:
•
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
34.10.3.4 Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case
of consecutive write cycles in the same memory (see the following figure). However, for devices that perform write
operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
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SAM9X60
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Figure 34-13. Null Setup and Hold Values of NCS and NWE in Write Cycle
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
NWE_PULSE
NWE_PULSE
NWE_PULSE
NCS_WR_PULSE
NCS_WR_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_CYCLE
NWE_CYCLE
34.10.3.5 Null Pulse
Programming a null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
34.10.4 Write Mode
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
controls the write operation.
34.10.4.1 Write is Controlled by NWE (WRITE_MODE = 1)
The following figure shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the
bus during the pulse and hold steps of the NWE signal. The internal data buffers are switched to Output mode after
the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
Figure 34-14. WRITE_MODE = 1 (Write Operation Controlled by NWE)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
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34.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0)
The following figure shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the
bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to Output mode after
the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
Figure 34-15. WRITE_MODE = 0 (Write Operation Controlled by NCS)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
34.10.5 Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to
their type.
The SMC_SETUP register groups the definition of all setup parameters:
•
NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
•
NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
•
NRD_CYCLE, NWE_CYCLE
The following table shows how the timing parameters are coded and their permitted range.
Table 34-4. Coding and Range of Timing Parameters
Coded Value
Number of Bits
Effective Value
Permitted Range
Coded Value
Effective Value
setup [5:0]
6
128 x setup[5] + setup[4:0]
0 ≤ 31
0 ≤ 128 + 31
pulse [6:0]
7
256 x pulse[6] + pulse[5:0]
0 ≤ 63
0 ≤ 256 + 63
cycle [8:0]
9
256 x cycle[8:7] + cycle[6:0]
0 ≤ 127
0 ≤ 256 + 127
0 ≤ 512 +1 27
0 ≤ 768 + 127
34.10.6 Reset Values of Timing Parameters
For the default values of timing parameters at reset, see 34.20.1 SMC_SETUPx, 34.20.2 SMC_PULSEx and
34.20.3 SMC_CYCLEx.
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34.10.7 Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE
parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
•
•
•
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory
interface because of the propagation delay of theses signals through external logic and pads. If positive setup
and hold values must be verified, then it is strictly recommended to program non-null values so as to cover
possible skews between address, NCS and NRD signals.
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines,
and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See Early Read Wait
State.
For read and write operations:
A null value for pulse parameters is forbidden and may lead to unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For
external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and
NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the
address bus.
34.11
Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or
operation conflict.
34.11.1 Chip Select Wait States
The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that
there is no bus contention between the de-activation of one device and the activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..5], NRD
lines are all set to 1.
The following figure illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
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Figure 34-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NRD
NWE
NCS0
NCS2
NWE_CYCLE
NRD_CYCLE
D[31:0]
Read to Write Chip Select
Wait State
Wait State
34.11.2 Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the
write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip
select wait state. The early read cycle thus only occurs between a write and read access to the same memory device
(same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is valid:
•
•
•
the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 34-17).
in NCS Write Controlled mode (WRITE_MODE = 0), there is no hold timing on the NCS signal and the
NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 34-18). The write operation must
end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.
in NWE Controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of
the write control signal is used to control address, data, chip select and byte select lines. If the external write
control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and
address, data and control signals are maintained one more cycle. See Figure 34-19.
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Figure 34-17. Early Read Wait State: Write with No Hold Followed by Read with No Setup
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE
NRD
no hold
no setup
D[31:0]
write cycle
read cycle
Early Read
wait state
Figure 34-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS
Setup
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NCS
NRD
no hold
no setup
D[31:0]
write cycle
(WRITE_MODE = 0)
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Early Read
wait state
read cycle
(READ_MODE = 0 or READ_MODE = 1)
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Figure 34-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up
Cycle
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
internal write controlling signal
external write controlling signal
(NWE)
no hold
read setup = 1
NRD
D[31:0]
write cycle
(WRITE_MODE = 1)
Early Read
wait state
read cycle
(READ_MODE = 0 or READ_MODE = 1)
34.11.3 Reload User Configuration Wait State
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state
before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the
new set of parameters to apply to next accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and
after re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select
Wait State is applied.
On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload
Configuration Wait State is inserted, even if the change does not concern the current Chip Select.
34.11.3.1 User Procedure
To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the user
interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user
interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode
parameters.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if
accesses are performed on this CS during the modification. Any change of the Chip Select parameters, while fetching
the code from a memory connected on this CS, may lead to unpredictable behavior. The instructions used to modify
the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to
another CS.
34.11.3.2 Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slow Clock mode is entered or exited, after the end of
the current transfer (see 34.14 Slow Clock Mode).
34.11.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
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This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be
inserted. See Figure 34-16.
34.12
Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data
float wait states) after a read access:
•
•
before starting a read access to a different external memory
before starting a write access to the same device or to a different external one.
The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the
SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data
float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for
the data output to go to high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with
long tDF will not slow down the execution of a program from internal memory.
The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the SMC_MODE
register for the corresponding chip select.
34.12.1 READ_MODE
Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state
buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and
lasts TDF_CYCLES MCK cycles.
When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK
cycles during which the data bus remains busy after the rising edge of NCS.
Figure 34-20 illustrates the Data Float Period in NRD-controlled mode (READ_MODE = 1), assuming a data float
period of two cycles (TDF_CYCLES = 2). Figure 34-21 shows the read operation when controlled by NCS
(READ_MODE = 0) and the TDF_CYCLES parameter equals 3.
Figure 34-20. TDF Period in NRD Controlled Read Access (TDF = 2)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NRD
NCS
tpacc
D[31:0]
TDF = 2 clock cycles
NRD controlled read operation
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SAM9X60
Static Memory Controller (SMC)
Figure 34-21. TDF Period in NCS Controlled Read Operation (TDF = 3)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NRD
NCS
tpacc
D[31:0]
TDF = 3 clock cycles
NCS controlled read operation
34.12.2 TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
The following figure shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip
Select 0. Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
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SAM9X60
Static Memory Controller (SMC)
Figure 34-22. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next
access begins
MCK
A[25:2]
NRD
NRD_HOLD = 4
NWE
NWE_SETUP = 3
NCS0
TDF_CYCLES = 6
D[31:0]
read access on NCS0 (NRD controlled)
Read to Write
Wait State
write access on NCS0 (NWE controlled)
34.12.3 TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, TDF wait states are inserted at the end of the read transfer, so that the data float
period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data
float period, no additional TDF wait states will be inserted.
The three figures below illustrate the following cases, respectively:
•
•
•
read access followed by a read access on another chip select,
read access followed by a write access on another chip select,
read access followed by a write access on the same chip select,
with no TDF optimization.
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SAM9X60
Static Memory Controller (SMC)
Figure 34-23. TDF Optimization Disabled (TDF Mode = 0): TDF wait states between 2 read accesses on
different chip selects
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
read1 controlling signal
(NRD)
read1 hold = 1
read2 controlling signal
(NRD)
read2 setup = 1
TDF_CYCLES = 6
D[31:0]
5 TDF WAIT STATES
read 2 cycle
TDF_MODE = 0
(optimization disabled)
read1 cycle
TDF_CYCLES = 6
Chip Select Wait State
Figure 34-24. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
read1 controlling signal
(NRD)
read1 hold = 1
write2 controlling signal
(NWE)
write2 setup = 1
TDF_CYCLES = 4
D[31:0]
2 TDF WAIT STATES
read1 cycle
TDF_CYCLES = 4
Read to Write Chip Select
Wait State Wait State
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write2 cycle
TDF_MODE = 0
(optimization disabled)
DS60001579C-page 617
SAM9X60
Static Memory Controller (SMC)
Figure 34-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
read1 controlling signal
(NRD)
write2 setup = 1
read1 hold = 1
write2 controlling signal
(NWE)
TDF_CYCLES = 5
D[31:0]
4 TDF WAIT STATES
read1 cycle
TDF_CYCLES = 5
34.13
Read to Write
Wait State
write2 cycle
TDF_MODE = 0
(optimization disabled)
External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE
field of the SMC_MODE register on the corresponding chip select must be set to either to ‘10’ (frozen mode) or ‘11’
(ready mode). When the EXNW_MODE is set to ‘00’ (disabled), the NWAIT signal is simply ignored on the
corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write
controlling signal, depending on the read and write modes of the corresponding chip select.
34.13.1 Restriction
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write
controlling signal. For that reason, the NWAIT signal cannot be used in Page mode (see 34.15 Asynchronous Page
Mode), or in Slow Clock mode (see 34.14 Slow Clock Mode).
The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then
NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the
NWAIT signal outside the expected period has no impact on SMC behavior.
34.13.2 Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the
SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the
resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point
where it was stopped. See the following figure. This mode must be selected when the external device uses the
NWAIT signal to delay the access and to freeze the SMC.
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SAM9X60
Static Memory Controller (SMC)
Figure 34-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
FROZEN STATE
4
3
2
1
1
1
1
0
3
2
2
2
2
1
NWE
6
5
4
0
NCS
D[31:0]
NWAIT
internally synchronized
NWAIT signal
Write cycle
EXNW_MODE = 10 (Frozen)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in the figure below.
Figure 34-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NCS
NRD
FROZEN STATE
4
3
1
0
2
5
2
5
2
5
1
4
0
3
2
1
0
2
1
0
NWAIT
internally synchronized
NWAIT signal
Read cycle
EXNW_MODE = 10 (Frozen)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 2, NRD_HOLD = 6
NCS_RD_PULSE = 5, NCS_RD_HOLD = 3
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Assertion is ignored
DS60001579C-page 619
SAM9X60
Static Memory Controller (SMC)
34.13.3 Ready Mode
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down
counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the
resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 34-28 and Figure 34-29. After deassertion, the access
is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to
complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling
read/write signal, it has no impact on the access length as shown in Figure 34-29.
Figure 34-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
Wait STATE
4
3
2
1
0
0
0
3
2
1
1
1
NWE
6
5
4
0
NCS
D[31:0]
NWAIT
internally synchronized
NWAIT signal
Write cycle
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
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SAM9X60
Static Memory Controller (SMC)
Figure 34-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11)
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
Wait STATE
6
5
4
3
2
1
0
0
6
5
4
3
2
1
1
NCS
NRD
0
NWAIT
internally synchronized
NWAIT signal
Read cycle
EXNW_MODE = 11(Ready mode)
READ_MODE = 0 (NCS_controlled)
Assertion is ignored
Assertion is ignored
NRD_PULSE = 7
NCS_RD_PULSE =7
34.13.4 NWAIT Latency and Read/Write Timings
There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT
signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this
latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access
without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated
in the following figure.
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write
controlling signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
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SAM9X60
Static Memory Controller (SMC)
Figure 34-30. NWAIT Latency
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
WAIT STATE
4
3
2
1
0
0
0
NRD
minimal pulse length
NWAIT
intenally synchronized
NWAIT signal
NWAIT latency 2 cycle resynchronization
Read cycle
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
34.14
Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal
driven by the Power Management Controller is asserted because MCK has been configured to a very slow clock rate
(typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode
waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate
waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects.
34.15
Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the
SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8,
16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always
aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the
address of the page in memory, the LSB of address define the address of the data in the page as detailed in the table
below.
With page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to
the page (tsa) as shown in Figure 34-31. When in page mode, the SMC enables the user to define different read
timings for the first access within one page, and next accesses within the page.
Table 34-5. Page Address and Data Address within a Page
Page Size
Page Address (1)
Data Address in the Page (2)
4 bytes
A[25:2]
A[1:0]
8 bytes
A[25:3]
A[2:0]
16 bytes
A[25:4]
A[3:0]
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SAM9X60
Static Memory Controller (SMC)
...........continued
Page Size
Page Address (1)
Data Address in the Page (2)
32 bytes
A[25:5]
A[4:0]
Notes:
1. ‘A’ denotes the address bus of the memory device.
2. For 16-bit devices, bit 0 of the address is ignored. For 32-bit devices, bits [1:0] are ignored.
34.15.1 Protocol and Timings in Page Mode
The following figure shows the NRD and NCS timings in Page mode access. Note that address MSB and LSB are
defined in Table 34-5.
Figure 34-31. Page Mode Read Protocol
MCK
A[MSB]
A[LSB]
NRD
tpa
NCS
tsa
tsa
D[31:0]
NRD_PULSE
NCS_RD_PULSE
NRD_PULSE
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and
hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the
first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of
subsequent accesses within the page are defined using the NRD_PULSE parameter.
Programming of the read timings in Page mode is described in the following table.
Table 34-6. Programming of Read Timings in Page Mode
Parameter
Value
Definition
READ_MODE
‘x’
No impact
NCS_RD_SETUP
‘x’
No impact
NCS_RD_PULSE
tpa
Access time of first access to the page
NRD_SETUP
‘x’
No impact
NRD_PULSE
tsa
Access time of subsequent accesses in the page
NRD_CYCLE
‘x’
No impact
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access
timing (tpa) and the NRD_PULSE for accesses to the page (tsa), even if the programmed value for tpa is shorter than
the programmed value for tsa.
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SAM9X60
Static Memory Controller (SMC)
34.15.2 Byte Access Type in Page Mode
The byte access type (BAT) configuration remains active in page mode. For 16-bit or 32-bit page mode devices that
require byte selection signals, write a 0 to the BAT bit in the SMC Mode Register (SMC_MODE) to select the byte
select access type.
34.15.3 Page Mode Restriction
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may
lead to unpredictable behavior.
34.15.4 Sequential and Non-sequential Accesses
If the chip select and the MSB of addresses as defined in Table 34-5 are identical, then the current access lies in the
same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum
access time (tsa). The following figure illustrates access to an 8-bit memory device in page mode, with 8-byte pages.
Access to D1 causes a page access with a long access time (tpa). Accesses to D3 and D7, though they are not
sequential accesses, only require a short access time (tsa).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip
select is different from the previous access, a page break occurs. If two sequential accesses are made to the page
mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second
access because the chip select of the device was deasserted between both accesses.
Figure 34-32. Access to Non-sequential Data within the Same Page
MCK
Page address
A[25:3]
A[2], A1, A0
A1
A3
A7
NRD
NCS
D[7:0]
D1
NCS_RD_PULSE
34.16
D3
NRD_PULSE
D7
NRD_PULSE
Register Write Protection
To prevent any single software error from corrupting SMC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the SMC Write Protection Mode Register (SMC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the SMC Write Protection Status Register
(SMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the SMC_WPSR.
The following registers can be write-protected:
•
•
•
•
SMC Setup Register
SMC Pulse Register
SMC Cycle Register
SMC Mode Register
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 624
SAM9X60
Static Memory Controller (SMC)
•
•
34.17
SMC Off-Chip Memory Scrambling Register
SMC Safety Report Interrupt Enable Register
Security and Safety Analysis and Reports
Several types of checks are performed when the SMC is reading or writing an external memory. The internal
sequencer of the SMC is monitored for integrity and if an abnormal state is detected, the flag SMC_WPSR.SEQE is
set. This flag is not set under normal operating conditions. The software accesses to the SMC are monitored and if
an incorrect access is performed, the flag SMC_WPSR.SWE is set. The type of incorrect/abnormal software access
is reported in the SMC_WPSR.SWETYP field (see SMC Write Protection Status Register for details). The flags
SEQE, SWE and WPVS are automatically cleared when SMC_WPSR is read. If one of these flags is set, an interrupt
can be triggered if the SMC_SRIER.SRIE bit is ‘1’.
34.18
Scrambling/Unscrambling Function
The external data bus can be scrambled to make more difficult the recovery of intellectual property data located in offchip memories by means of data analysis at the package pin level of either the microcontroller or the memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling/unscrambling function can be enabled or disabled by configuring the CSxSE bits in the SMC Off-Chip
Memory Scrambling Register (SMC_OCMS).
When multiple chip selects are handled, the scrambling function per chip select is configurable using the CSxSE bits
in the SMC_OCMS register.
The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2 plus a random
value depending on device processing characteristics. These key registers cannot be read. They can be written once
after a system reset.
The scrambling user key or the seed for key generation must be securely stored in a reliable non-volatile memory in
order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key
is lost.
34.19
Clearing Scrambling Keys on a Tamper Event
On tamper detection event on WKUP pins, it is possible to perform an immediate clear of the scrambling keys
(SMC_KEY1 and SMC_KEY2) is performed if SMC_OCMS.TAMPCLR is set.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 625
SAM9X60
Static Memory Controller (SMC)
34.20
Register Summary
The SMC is programmed using the registers listed below. For each chip select, a set of four registers is used to
program the parameters of the external device connected on it. The number of SMC_SETUP, SMC_PULSE,
SMC_CYCLE and SMC_MODE registers depends on the number of chip selects. Sixteen bytes (0x10) are required
per chip select.
Note: The user must confirm the SMC configuration by writing any one of the SMC_MODE registers.
Offset
Name
0x00
SMC_SETUP0
0x04
SMC_PULSE0
Bit Pos.
7
6
5
4
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
3
2
1
NRD_CYCLE[
8]
31:24
0x08
SMC_CYCLE0
23:16
NRD_CYCLE[7:0]
NWE_CYCLE[
8]
15:8
0x0C
SMC_MODE0
7:0
31:24
23:16
15:8
7:0
0x10
SMC_SETUP1
0x14
SMC_PULSE1
NWE_CYCLE[7:0]
PS[1:0]
TDF_MODE
DBW[1:0]
PMEN
TDF_CYCLES[3:0]
BAT
WRITE_MOD
READ_MODE
E
EXNW_MODE[1:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
NCS_RD_SETUP[5:0]
NRD_SETUP[5:0]
NCS_WR_SETUP[5:0]
NWE_SETUP[5:0]
NCS_RD_PULSE[6:0]
NRD_PULSE[6:0]
NCS_WR_PULSE[6:0]
NWE_PULSE[6:0]
NRD_CYCLE[
8]
31:24
0x18
SMC_CYCLE1
23:16
NRD_CYCLE[7:0]
NWE_CYCLE[
8]
15:8
0x1C
SMC_MODE1
7:0
31:24
23:16
15:8
7:0
0x20
SMC_SETUP2
0x24
SMC_PULSE2
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
0
NCS_RD_SETUP[5:0]
NRD_SETUP[5:0]
NCS_WR_SETUP[5:0]
NWE_SETUP[5:0]
NCS_RD_PULSE[6:0]
NRD_PULSE[6:0]
NCS_WR_PULSE[6:0]
NWE_PULSE[6:0]
NWE_CYCLE[7:0]
PS[1:0]
TDF_MODE
DBW[1:0]
PMEN
TDF_CYCLES[3:0]
EXNW_MODE[1:0]
BAT
WRITE_MOD
READ_MODE
E
NCS_RD_SETUP[5:0]
NRD_SETUP[5:0]
NCS_WR_SETUP[5:0]
NWE_SETUP[5:0]
NCS_RD_PULSE[6:0]
NRD_PULSE[6:0]
NCS_WR_PULSE[6:0]
NWE_PULSE[6:0]
Complete Datasheet
DS60001579C-page 626
SAM9X60
Static Memory Controller (SMC)
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
NRD_CYCLE[
8]
31:24
0x28
SMC_CYCLE2
23:16
NRD_CYCLE[7:0]
NWE_CYCLE[
8]
15:8
0x2C
SMC_MODE2
7:0
31:24
23:16
15:8
7:0
0x30
SMC_SETUP3
0x34
SMC_PULSE3
NWE_CYCLE[7:0]
PS[1:0]
TDF_MODE
DBW[1:0]
PMEN
TDF_CYCLES[3:0]
BAT
WRITE_MOD
READ_MODE
E
EXNW_MODE[1:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
NCS_RD_SETUP[5:0]
NRD_SETUP[5:0]
NCS_WR_SETUP[5:0]
NWE_SETUP[5:0]
NCS_RD_PULSE[6:0]
NRD_PULSE[6:0]
NCS_WR_PULSE[6:0]
NWE_PULSE[6:0]
NRD_CYCLE[
8]
31:24
0x38
SMC_CYCLE3
23:16
NRD_CYCLE[7:0]
NWE_CYCLE[
8]
15:8
0x3C
SMC_MODE3
7:0
31:24
23:16
15:8
7:0
0x40
SMC_SETUP4
0x44
SMC_PULSE4
NWE_CYCLE[7:0]
PS[1:0]
TDF_MODE
DBW[1:0]
PMEN
TDF_CYCLES[3:0]
BAT
WRITE_MOD
READ_MODE
E
EXNW_MODE[1:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
NCS_RD_SETUP[5:0]
NRD_SETUP[5:0]
NCS_WR_SETUP[5:0]
NWE_SETUP[5:0]
NCS_RD_PULSE[6:0]
NRD_PULSE[6:0]
NCS_WR_PULSE[6:0]
NWE_PULSE[6:0]
NRD_CYCLE[
8]
31:24
0x48
SMC_CYCLE4
23:16
NRD_CYCLE[7:0]
NWE_CYCLE[
8]
15:8
0x4C
SMC_MODE4
7:0
31:24
23:16
15:8
7:0
0x50
SMC_SETUP5
0x54
SMC_PULSE5
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
0
NWE_CYCLE[7:0]
PS[1:0]
TDF_MODE
DBW[1:0]
PMEN
TDF_CYCLES[3:0]
EXNW_MODE[1:0]
BAT
WRITE_MOD
READ_MODE
E
NCS_RD_SETUP[5:0]
NRD_SETUP[5:0]
NCS_WR_SETUP[5:0]
NWE_SETUP[5:0]
NCS_RD_PULSE[6:0]
NRD_PULSE[6:0]
NCS_WR_PULSE[6:0]
NWE_PULSE[6:0]
Complete Datasheet
DS60001579C-page 627
SAM9X60
Static Memory Controller (SMC)
...........continued
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
NRD_CYCLE[
8]
31:24
0x58
SMC_CYCLE5
23:16
NRD_CYCLE[7:0]
NWE_CYCLE[
8]
15:8
0x5C
SMC_MODE5
7:0
31:24
23:16
15:8
7:0
0x60
...
0x7F
SMC_OCMS
0x84
SMC_KEY1
0x88
SMC_KEY2
0x8C
...
0x8F
Reserved
0x94
...
0xE3
0xE4
0xE8
NWE_CYCLE[7:0]
PS[1:0]
TDF_MODE
DBW[1:0]
PMEN
TDF_CYCLES[3:0]
BAT
WRITE_MOD
READ_MODE
E
EXNW_MODE[1:0]
Reserved
0x80
0x90
0
SMC_SRIER
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
CS5SE
CS4SE
CS3SE
TAMPCLR
KEY1[31:24]
KEY1[23:16]
KEY1[15:8]
KEY1[7:0]
KEY2[31:24]
KEY2[23:16]
KEY2[15:8]
KEY2[7:0]
CS2SE
31:24
23:16
15:8
7:0
CS1SE
CS0SE
SMSE
SRIE
Reserved
SMC_WPMR
SMC_WPSR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WPEN
SWETYP[1:0]
WPVSRC[15:8]
WPVSRC[7:0]
SWE
Complete Datasheet
SEQE
WPVS
DS60001579C-page 628
SAM9X60
Static Memory Controller (SMC)
34.20.1 SMC Setup Register
Name:
Offset:
Reset:
Property:
SMC_SETUPx
0x00 + x*0x10 [x=0..5]
0x01010101
Read/Write
This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register.
Note: The number of SMC_SETUP registers depends on the chip select number.
Bit
31
30
Access
Reset
Bit
23
22
Access
Reset
Bit
15
14
Access
Reset
Bit
7
6
Access
Reset
29
28
R/W
0
R/W
0
21
20
R/W
0
R/W
0
13
12
R/W
0
R/W
0
5
4
R/W
0
R/W
0
27
26
NCS_RD_SETUP[5:0]
R/W
R/W
0
0
19
18
NRD_SETUP[5:0]
R/W
R/W
0
0
11
10
NCS_WR_SETUP[5:0]
R/W
R/W
0
0
3
2
NWE_SETUP[5:0]
R/W
R/W
0
0
25
24
R/W
0
R/W
1
17
16
R/W
0
R/W
1
9
8
R/W
0
R/W
1
1
0
R/W
0
R/W
1
Bits 29:24 – NCS_RD_SETUP[5:0] NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS setup length = (128 * NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles
Bits 21:16 – NRD_SETUP[5:0] NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD setup length = (128 * NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles
Bits 13:8 – NCS_WR_SETUP[5:0] NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
NCS setup length = (128 * NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles
Bits 5:0 – NWE_SETUP[5:0] NWE Setup Length
The NWE signal setup length is defined as:
NWE setup length = (128 * NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 629
SAM9X60
Static Memory Controller (SMC)
34.20.2 SMC Pulse Register
Name:
Offset:
Reset:
Property:
SMC_PULSEx
0x04 + x*0x10 [x=0..5]
0x01010101
Read/Write
This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register.
Note: The number of SMC_PULSE registers depends on the chip select number.
Bit
31
Access
Reset
Bit
23
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
30
29
28
R/W
0
R/W
0
R/W
0
22
21
20
R/W
0
R/W
0
R/W
0
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
27
NCS_RD_PULSE[6:0]
R/W
0
19
NRD_PULSE[6:0]
R/W
0
11
NCS_WR_PULSE[6:0]
R/W
0
3
NWE_PULSE[6:0]
R/W
0
26
25
24
R/W
0
R/W
0
R/W
1
18
17
16
R/W
0
R/W
0
R/W
1
10
9
8
R/W
0
R/W
0
R/W
1
2
1
0
R/W
0
R/W
0
R/W
1
Bits 30:24 – NCS_RD_PULSE[6:0] NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
NCS pulse length = (256 * NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page.
Bits 22:16 – NRD_PULSE[6:0] NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as:
NRD pulse length = (256 * NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles
The NRD pulse length must be at least 1 clock cycle.
In page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the
page.
Bits 14:8 – NCS_WR_PULSE[6:0] NCS Pulse Length in WRITE Access
In write access, the NCS signal pulse length is defined as:
NCS pulse length = (256 * NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
Bits 6:0 – NWE_PULSE[6:0] NWE Pulse Length
The NWE signal pulse length is defined as:
NWE pulse length = (256 * NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles
The NWE pulse length must be at least 1 clock cycle.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 630
SAM9X60
Static Memory Controller (SMC)
34.20.3 SMC Cycle Register
Name:
Offset:
Reset:
Property:
SMC_CYCLEx
0x08 + x*0x10 [x=0..5]
0x00030003
Read/Write
This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register.
Note: The number of SMC_CYCLE registers depends on the chip select number.
Bit
31
30
29
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
7
6
5
R/W
0
R/W
0
R/W
0
28
27
26
25
24
NRD_CYCLE[8]
R/W
0
18
17
16
R/W
0
R/W
1
R/W
1
10
9
8
NWE_CYCLE[8
]
R/W
0
2
1
0
R/W
0
R/W
1
R/W
1
Access
Reset
Bit
Access
Reset
Bit
20
19
NRD_CYCLE[7:0]
R/W
R/W
0
0
12
11
Access
Reset
Bit
Access
Reset
4
3
NWE_CYCLE[7:0]
R/W
R/W
0
0
Bits 24:16 – NRD_CYCLE[8:0] Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup,
pulse and hold steps of the NRD and NCS signals. It is defined as:
Read cycle length = (NRD_CYCLE[8:7] * 256 + NRD_CYCLE[6:0]) clock cycles
Bits 8:0 – NWE_CYCLE[8:0] Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup,
pulse and hold steps of the NWE and NCS signals. It is defined as:
Write cycle length = (NWE_CYCLE[8:7] * 256 + NWE_CYCLE[6:0]) clock cycles
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 631
SAM9X60
Static Memory Controller (SMC)
34.20.4 SMC Mode Register
Name:
Offset:
Reset:
Property:
SMC_MODEx
0x0C + x*0x10 [x=0..5]
0x10001000
Read/Write
This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register.
The user must confirm the SMC configuration by writing any one of the SMC_MODE registers.
Note: The number of SMC_MODE registers depends on the chip select number.
Bit
31
30
29
28
27
26
25
PS[1:0]
Access
Reset
Bit
23
22
R/W
0
R/W
1
21
20
TDF_MODE
R/W
0
R/W
0
12
11
10
3
2
Access
Reset
Bit
15
14
13
19
18
17
TDF_CYCLES[3:0]
R/W
R/W
0
0
9
DBW[1:0]
Access
Reset
Bit
R/W
0
7
6
Access
Reset
R/W
1
5
4
EXNW_MODE[1:0]
R/W
R/W
0
0
24
PMEN
R/W
0
16
R/W
0
8
BAT
R/W
0
1
0
WRITE_MODE READ_MODE
R/W
R/W
0
0
Bits 29:28 – PS[1:0] Page Size
If page mode is enabled, this field indicates the size of the page in bytes.
Value
Name
Description
0
BYTE_4
4-byte page
1
BYTE_8
8-byte page
2
BYTE_16
16-byte page
3
BYTE_32
32-byte page
Bit 24 – PMEN Page Mode Enabled
Value
Description
1
Asynchronous burst read in page mode is applied on the corresponding chip select.
0
Standard read is applied.
Bit 20 – TDF_MODE TDF Optimization
Value
Description
1
TDF optimization enabled—The number of TDF wait states is optimized using the setup period of the
next read/write access.
0
TDF optimization disabled—The number of TDF wait states is inserted before the next access begins.
Bits 19:16 – TDF_CYCLES[3:0] Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising
edge of the read controlling signal. The SMC always provides one full cycle of bus turnaround after the
TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles.
From 0 up to 15 TDF_CYCLES can be set.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 632
SAM9X60
Static Memory Controller (SMC)
Bits 13:12 – DBW[1:0] Data Bus Width
Value
Name
0
BIT_8
1
BIT_16
2
BIT_32
3
—
Description
8-bit bus
16-bit bus
32-bit bus
Reserved
Bit 8 – BAT Byte Access Type
This field is used only if DBW defines a 16- or 32-bit data bus.
Value
Name
Description
0
BYTE_SELECT Byte select access type:
- Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3
1
BYTE_WRITE
- Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3
Byte write access type:
- Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3
- Read operation is controlled using NCS and NRD
Bits 5:4 – EXNW_MODE[1:0] NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse
phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration
must be programmed for the read and write controlling signal.
Value
Name
Description
0
DISABLED Disabled Mode—The NWAIT input signal is ignored on the corresponding Chip Select.
1
—
Reserved
2
FROZEN
Frozen Mode—If asserted, the NWAIT signal freezes the current read or write cycle. After
deassertion, the read/write cycle is resumed from the point where it was stopped.
3
READY
Ready Mode—The NWAIT signal indicates the availability of the external device at the
end of the pulse of the controlling read or write signal, to complete the access. If high, the
access normally completes. If low, the access is extended until NWAIT returns high.
Bit 1 – WRITE_MODE Selection of the Control Signal for Write Operation
Value
Name
Description
0
NCS_CTRL Write operation controlled by NCS signal—If TDF optimization is enabled (TDF_MODE =
1), TDF wait states will be inserted after the setup of NCS.
1
NWE_CTRL Write operation controlled by NWE signal—If TDF optimization is enabled (TDF_MODE =
1), TDF wait states will be inserted after the setup of NWE.
Bit 0 – READ_MODE Selection of the Control Signal for Read Operation
Value
Name
Description
0
NCS_CTRL Read operation controlled by NCS signal
- If TDF cycles are programmed, the external bus is marked busy after the rising edge of
NCS.
1
- If TDF optimization is enabled (TDF_MODE = 1), TDF wait states are inserted after the
setup of NCS.
NRD_CTRL Read operation controlled by NRD signal
- If TDF cycles are programmed, the external bus is marked busy after the rising edge of
NRD.
- If TDF optimization is enabled (TDF_MODE = 1), TDF wait states are inserted after the
setup of NRD.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 633
SAM9X60
Static Memory Controller (SMC)
34.20.5 SMC Off-Chip Memory Scrambling Register
Name:
Offset:
Reset:
Property:
SMC_OCMS
0x80
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
CS5SE
R/W
0
12
CS4SE
R/W
0
11
CS3SE
R/W
0
10
CS2SE
R/W
0
9
CS1SE
R/W
0
8
CS0SE
R/W
0
7
6
5
4
TAMPCLR
R/W
0
3
2
1
0
SMSE
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 8, 9, 10, 11, 12, 13 – CSSE Chip Select Scrambling Enable
Value
Description
0
Disables scrambling for CSx.
1
Enables scrambling for CSx.
Bit 4 – TAMPCLR Tamper Clear Enable
Value
Description
0
A tamper detection event has no effect on SMC scrambling keys.
1
A tamper detection event immediately clears SMC scrambling keys.
Bit 0 – SMSE Static Memory Controller Scrambling Enable
Value
Description
0
Disables scrambling for SMC access.
1
Enables scrambling for SMC access.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 634
SAM9X60
Static Memory Controller (SMC)
34.20.6 SMC Off-Chip Memory Scrambling Key1 Register
Name:
Offset:
Reset:
Property:
SMC_KEY1
0x84
0x00000000
Write-only
This register is a ‘Write-once’ register: the first write access after a system reset prevents any further modification of
the register value.
This register is erased if a tamper is detected on fast wakeup pins and bit SMC_OCMS.TAMPCLR = 1.
Bit
31
30
29
28
27
26
25
24
W
0
W
0
W
0
W
0
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
W
0
W
0
W
0
W
0
3
2
1
0
W
0
W
0
W
0
W
0
KEY1[31:24]
Access
Reset
W
0
W
0
W
0
W
0
Bit
23
22
21
20
KEY1[23:16]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
KEY1[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
7
6
5
4
KEY1[7:0]
Access
Reset
W
0
W
0
W
0
W
0
Bits 31:0 – KEY1[31:0] Off-Chip Memory Scrambling (OCMS) Key Part 1
When off-chip memory scrambling is enabled, KEY1 and KEY2 values determine data scrambling.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 635
SAM9X60
Static Memory Controller (SMC)
34.20.7 SMC Off-Chip Memory Scrambling Key2 Register
Name:
Offset:
Reset:
Property:
SMC_KEY2
0x88
0x00000000
Write-only
This register is a ‘Write-once’ register: the first write access after a system reset prevents any further modification of
the register value.
This register is erased if a tamper is detected on fast wakeup pins and bit SMC_OCMS.TAMPCLR = 1.
Bit
31
30
29
28
27
26
25
24
W
0
W
0
W
0
W
0
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
W
0
W
0
W
0
W
0
3
2
1
0
W
0
W
0
W
0
W
0
KEY2[31:24]
Access
Reset
W
0
W
0
W
0
W
0
Bit
23
22
21
20
KEY2[23:16]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
KEY2[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
7
6
5
4
KEY2[7:0]
Access
Reset
W
0
W
0
W
0
W
0
Bits 31:0 – KEY2[31:0] Off-Chip Memory Scrambling (OCMS) Key Part 2
When off-chip memory scrambling is enabled, KEY1 and KEY2 values determine data scrambling.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 636
SAM9X60
Static Memory Controller (SMC)
34.20.8 SMC Safety Report Interrupt Enable Register
Name:
Offset:
Reset:
Property:
SMC_SRIER
0x90
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRIE
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – SRIE Safety Report Interrupt Enable
Value
Description
0
Disables the SMC safety report interrupt from External Bus Interface.
1
Enables the SMC safety report interrupt from External Bus Interface.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 637
SAM9X60
Static Memory Controller (SMC)
34.20.9 SMC Write Protection Mode Register
Name:
Offset:
Reset:
Property:
SMC_WPMR
0xE4
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x534D43
PASSWD
Writing any other value in this field aborts the write operation of bit WPEN.
Always reads as 0.
Bit 0 – WPEN Write Protection Enable
See list of write-protected registers in Coding Timing Parameters.
Value
Description
0
Disables write protection if WPKEY value corresponds to 0x534D43 (“SMC” in ASCII).
1
Enables write protection if WPKEY value corresponds to 0x534D43 (“SMC” in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 638
SAM9X60
Static Memory Controller (SMC)
34.20.10 SMC Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
31
SMC_WPSR
0xE8
0x00000000
Read-only
30
29
28
27
26
25
24
SWETYP[1:0]
Access
Reset
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
Bit
7
6
Access
Reset
R
0
R
0
20
19
WPVSRC[15:8]
R
R
0
0
18
17
16
R
0
R
0
R
0
10
9
8
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
5
4
2
SEQE
R
0
1
0
WPVS
R
0
3
SWE
R
0
Bits 25:24 – SWETYP[1:0] Software Error Type (Cleared on read)
Value
Name
Description
0
READ_WO
A write-only register has been read.
1
WRITE_WO
A write access has been performed on a read-only register.
2
UNDEF_RW
Access to an undefined address.
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 3 – SWE Software Control Error (Cleared on read)
Value
Description
0
No software error has occurred since the last read of SMC_WPSR.
1
A software error has occurred since the last read of SMC_WPSR. The field SWETYP details the type
of software error; the associated incorrect software access is reported in the field WPVSRC (if
WPVS=0).
Bit 2 – SEQE Internal Sequencer Error (Cleared on read)
Value
Description
0
No internal sequencer error has occurred since the last read of SMC_WPSR.
1
An internal sequencer error has occurred since the last read of SMC_WPSR. This flag can only be set
under abnormal operating conditions.
Bit 0 – WPVS Write Protection Violation Status
Value
Description
0
No write protection violation has occurred since the last read of the SMC_WPSR.
1
A write protection violation occurred since the last read of the SMC_WPSR. If this violation is an
unauthorized attempt to write a protected register, the associated violation is reported into field
WPVSRC.
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SAM9X60
Programmable Multibit Error Correction Code Contro...
35.
Programmable Multibit Error Correction Code Controller (PMECC)
35.1
Description
The Programmable Multibit Error Correction Code Controller (PMECC) is a programmable binary BCH (Bose,
Chaudhuri and Hocquenghem) encoder/decoder. This controller can be used to generate redundancy information for
both Single-Level Cell (SLC) and Multi-level Cell (MLC) NAND Flash devices. It supports redundancy for correction of
2, 4, 8, 12 or 24 bits of error per sector of data.
35.2
Embedded Characteristics
•
•
•
•
•
•
•
•
•
•
•
8-bit NAND Flash Data Bus Support
Multibit Error Correcting Code
Algorithm Based on Binary Shortened Bose, Chaudhuri and Hocquenghem (BCH) Codes
Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 Bits of Error per Sector
Programmable Sector Size: 512 Bytes or 1024 Bytes
Programmable Number of Sectors per Page: 1, 2, 4 or 8 Sectors of Data per Page
Programmable Spare Area Size
Supports Spare Area ECC Protection
Supports 8 Kbytes Page Size Using 1024 Bytes per Sector and 4 Kbytes Page Size Using 512 Bytes per Sector
Configurable through APB Interface
Interrupt-Driven Multibit Error Detection
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Programmable Multibit Error Correction Code Contro...
35.3
Block Diagram
Figure 35-1. Block Diagram
MLC/SLC
NAND Flash
device
Static
Memory
Controller
8-bit
Data Bus
Control Bus
PMECC
Controller
Programmable BCH Algorithm
User Interface
APB
35.4
Functional Description
The NAND Flash sector size is programmable and can be set to 512 bytes or 1024 bytes. The PMECC module
generates redundancy at encoding time, when a NAND write page operation is performed. The redundancy is
appended to the page and written in the spare area. This operation is performed by the processor. It moves the
content of the PMECCx registers into the NAND Flash memory. The number of registers depends on the selected
error correction capability, refer to the table “Relevant Redundancy Registers”. This operation is executed for each
sector. At decoding time, the PMECC module generates the remainder of the received codeword by minimal
polynomials. When all polynomial remainders for a given sector are set to zero, no error occurred. When the
polynomial remainders are other than zero, the codeword is corrupted and further processing is required.
The PMECC generates an interrupt indicating that an error occurred. The processor must read the PMECC Interrupt
Status Register (PMECC_ISR). This register indicates which sector is corrupted.
To find the error location within a sector, the processor must execute the following decoding steps:
1.
2.
3.
Syndrome computation
Find the error locator polynomials
Find the roots of the error locator polynomial
All decoding steps involve finite field computation, for which a library of finite field arithmetic must be available to
perform addition, multiplication and inversion. The finite field arithmetic operations can be performed through the use
of a memory mapped lookup table, or direct software implementation. The software implementation presented is
based on lookup tables. Two tables named gf_log and gf_antilog are used. If alpha is the primitive element of the
field, then a power of alpha is in the field. Assume beta = alpha ^ index, then beta belongs to the field, and
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Programmable Multibit Error Correction Code Contro...
gf_log(beta) = gf_log(alpha ^ index) = index. The gf_antilog tables provide exponent inverse of the element, if beta =
alpha ^ index, then gf_antilog(index) = beta.
The first step consists of the syndrome computation. The PMECC computes the remainders and software must
substitute the power of the primitive element.
The procedure implementation is given in “Remainder Substitution Procedure”.
The second step is the most software intensive. It is the Berlekamp’s iterative algorithm for finding the error-location
polynomial.
The procedure implementation is given in “Find the Error Location Polynomial Sigma(x)”.
The last step is finding the root of the error location polynomial. This step can be very software intensive, as there is
no straightforward method of finding the roots, except by evaluating each element of the field in the error location
polynomial. However, a hardware accelerator can be used to find the roots of the polynomial. The Programmable
Multibit Error Correction Code Location (PMERRLOC) module provides this kind of hardware acceleration.
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SAM9X60
Programmable Multibit Error Correction Code Contro...
Figure 35-2. Software/Hardware Multibit Error Correction Dataflow
NAND Flash
PROGRAM PAGE
Operation
Software
NAND Flash
READ PAGE
Operation
Hardware
Accelerator
Software
Configure PMECC :
error correction capability
sector size/page size
NAND write field set to true
spare area desired layout
Move the NAND Page
to external Memory
whether using DMA or
Processor
Hardware
Accelerator
Configure PMECC :
error correction capability
sector size/page size
NAND write field set to false
spare area desired layout
PMECC computes
redundancy as the
data is written into
external memory
Move the NAND Page
from external Memory
whether using DMA or
Processor
PMECC computes
polynomial remainders
as the data is read
from external memory
PMECC modules
indicate if at least one
error is detected.
Copy redundancy from
PMECC user interface
to user defined spare area.
using DMA or Processor.
If a sector is corrupted
use the substitute()
function to determine
the syndromes.
When the table of
syndromes is completed,
use the get_sigma()
function to get the
error location polynomial.
Find the error positions
finding the roots of the
error location polynomial.
And correct the bits.
35.4.1
This step can
be hardware assisted
using the PMERRLOC
module.
MLC/SLC Write Page Operation using PMECC
When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR bit in the
PMECC Configuration Register (PMECC_CFG) set to one. When the NAND spare area contains file system
information and redundancy (PMECCx), the spare area is error protected, then PMECC_CFG.SPAREEN is set to ‘1’.
When the NAND spare area contains only redundancy information, SPAREEN is set to ‘0’.
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Programmable Multibit Error Correction Code Contro...
When the write page operation is terminated, the user writes the redundancy in the NAND spare area. This operation
can be done with DMA assistance.
Table 35-1. Relevant Redundancy Registers
BCH_ERR field Sector size set to 512 bytes
Sector size set to 1024 bytes
0
PMECC_ECC0
PMECC_ECC0
1
PMECC_ECC0, PMECC_ECC1
PMECC_ECC0, PMECC_ECC1
2
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3
3
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5, PMECC_ECC6
4
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6, PMECC_ECC7,
PMECC_ECC8, PMECC_ECC9
PMECC_ECC0, PMECC_ECC1,
PMECC_ECC2, PMECC_ECC3,
PMECC_ECC4, PMECC_ECC5,
PMECC_ECC6, PMECC_ECC7,
PMECC_ECC8, PMECC_ECC9,
PMECC_ECC10
Table 35-2. Number of Relevant ECC bytes per Sector, copied from LSbyte to MSbyte
BCH_ERR field
Sector size set to 512 bytes
Sector size set to 1024 bytes
0
4 bytes
4 bytes
1
7 bytes
7 bytes
2
13 bytes
14 bytes
3
20 bytes
21 bytes
4
39 bytes
42 bytes
35.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set
When PMECC_CFG.SPAREEN is set to ‘1’, the spare area of the page is encoded with the stream of data of the last
sector of the page. This mode is entered by writing one in the DATA bit in the PMECC Control Register
(PMECC_CTRL). When the encoding process is over, the redundancy is written to the spare area in user mode,
PMECC_CTRL.USER must be set to ‘1’.
Figure 35-3. NAND Write Operation with Spare Encoding
Write NAND operation with SPAREEN set to one
pagesize = n * sectorsize
Sector 0
Sector 1
Sector 2
512 or 1024 bytes
sparesize
Sector 3
Spare
ecc_area
start_addr
end_addr
ECC computation enable signal
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Programmable Multibit Error Correction Code Contro...
35.4.1.2 MLC/SLC Write Operation with Spare Area Disabled
When PMECC_CFG.SPAREEN is set to ‘0’, the spare area is not encoded with the stream of data. This mode is
entered by writing ‘1’to PMECC_CTRL.DATA.
Figure 35-4. NAND Write Operation
Write NAND operation with SPAREEN set to zero
pagesize = n * sectorsize
Sector 0
Sector 1
Sector 2
Sector 3
512 or 1024 bytes
ECC computation enable signal
35.4.2
MLC/SLC Read Page Operation using PMECC
Table 35-3. Relevant Remainders Registers
BCH_ERR field Sector size set to 512 bytes
Sector size set to 1024 bytes
0
PMECC_REM0
PMECC_REM0
1
PMECC_REM0, PMECC_REM1
PMECC_REM0, PMECC_REM1
2
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3
3
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7
4
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7,
PMECC_REM8, PMECC_REM9,
PMECC_REM10, PMECC_REM11
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7,
PMECC_REM8, PMECC_REM9,
PMECC_REM10, PMECC_REM11
35.4.2.1 MLC/SLC Read Operation with Spare Decoding
When the spare area is protected, the spare area contains valid data. As the redundancy may be included in the
middle of the information stream, the user programs the start address and the end address of the ECC area. The
controller will automatically skip the ECC area. This mode is entered by writing a ‘1’ to PMECC_CTRL.DATA. When
the page has been fully retrieved from NAND, the ECC area is read using the user mode by writing a ‘1’ to
PMECC_CTRL.USER.
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Programmable Multibit Error Correction Code Contro...
Figure 35-5. Read Operation with Spare Decoding
Read NAND operation with SPAREEN set to One and AUTO set to Zero
pagesize = n * sectorsize
Sector 0
Sector 1
Sector 2
sparesize
Sector 3
Spare
512 or 1024 bytes
ecc_area
end_addr
start_addr
Remainder computation enable signal
35.4.2.2 MLC/SLC Read Operation
If the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. This mode
is entered by writing a ‘1’ to PMECC_CTRL.DATA. When PMECC_CFG.AUTO is set to ‘1’, the ECC is retrieved
automatically, otherwise the ECC must be read using user mode.
Figure 35-6. Read Operation
Read NAND operation with SPAREEN set to Zero and AUTO set to One
pagesize = n * sectorsize
Sector 1
Sector 2
Sector 3
Spare
512 or 1024 bytes
ecc_area
end_addr
ECC_SEC2
ECC_SEC1
ECC_SEC0
start_addr
ECC_SEC3
Sector 0
sparesize
Remainder computation enable signal
35.4.2.3 MLC/SLC User Read ECC Area
This mode allows a manual retrieve of the ECC.
This mode is entered by writing a ‘1’ to PMECC_CTRL.USER.
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Programmable Multibit Error Correction Code Contro...
Figure 35-7. User Read Mode
ecc_area_size
ECC
ecc_area
end_addr
addr = 0
Partial Syndrome computation enable signal
35.5
Software Implementation
35.5.1
Remainder Substitution Procedure
The substitute function evaluates the polynomial remainder, with different values of the field primitive elements. The
finite field arithmetic addition operation is performed with the Exclusive or. The finite field arithmetic multiplication
operation is performed through the gf_log, gf_antilog lookup tables.
The REM2NP1 and REMN2NP3 fields of the PMECC Remainder x registers (PMECC_REMx) contain only odd
remainders. Each bit indicates whether the coefficient of the polynomial remainder is set to zero or not.
NB_ERROR_MAX defines the maximum value of the error correcting capability.
NB_ERROR defines the error correcting capability selected at encoding/decoding time.
NB_FIELD_ELEMENTS defines the number of elements in the field.
si[] is a table that holds the current syndrome value, an element of that table belongs to the field. This is also a
shared variable for the next step of the decoding operation.
oo[] is a table that contains the degree of the remainders.
int substitute()
{
int i;
int j;
for (i = 1; i < 2 * NB_ERROR_MAX;
i++)
{
si[i] = 0;
}
for (i = 1; i < 2*NB_ERROR;
i++)
{
for (j = 0; j < oo[i];
j++)
{
if (REM2NPX[i][j])
{
si[i] = gf_antilog[(i *
j)%NB_FIELD_ELEMENTS] ^ si[i];
}
}
}
return 0;
}
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SAM9X60
Programmable Multibit Error Correction Code Contro...
35.5.2
Find the Error Location Polynomial Sigma(x)
The sample code below gives a Berlekamp iterative procedure for finding the value of the error location polynomial.
The input of the procedure is the si[] table defined in the remainder substitution procedure.
The output of the procedure is the error location polynomial named smu (sigma mu). The polynomial coefficients
belong to the field. The smu[NB_ERROR+1][] is a table that contains all these coefficients.
NB_ERROR_MAX defines the maximum value of the error correcting capability.
NB_ERROR defines the error correcting capability selected at encoding/decoding time.
NB_FIELD_ELEMENTS defines the number of elements in the field.
int get_sigma()
{
int i;
int j;
int k;
/* mu
*/
int
mu[NB_ERROR_MAX+2];
/* sigma ro
*/
int
sro[2*NB_ERROR_MAX+1];
/* discrepancy */
int
dmu[NB_ERROR_MAX+2];
/* delta order
*/
int
delta[NB_ERROR_MAX+2];
/* index of largest delta
*/
int ro;
int largest;
int diff;
/*
*/
/*
First Row
*/
/*
*/
/* Mu */
mu[0] = -1; /* Actually -1/2
*/
/* Sigma(x) set to 1
*/
for (i = 0; i <
(2*NB_ERROR_MAX+1); i++)
smu[0][i] = 0;
smu[0][0] = 1;
/* discrepancy set to 1
*/
dmu[0] = 1;
/* polynom order set to 0
*/
lmu[0] = 0;
/* delta set to -1 */
delta[0] = (mu[0] * 2 - lmu[0])
>> 1;
/*
*/
/*
Second Row
*/
/*
*/
/* Mu */
mu[1] = 0;
/* Sigma(x) set to 1
*/
for (i = 0; i <
(2*NB_ERROR_MAX+1); i++)
smu[1][i] = 0;
smu[1][0] = 1;
/* discrepancy set to Syndrome 1
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Programmable Multibit Error Correction Code Contro...
*/
dmu[1] = si[1];
/* polynom order set to 0
*/
lmu[1] = 0;
/* delta set to 0 */
delta[1] = (mu[1] * 2 - lmu[1])
>> 1;
for (i=1; i XMEMSIZE
XFACTOR = XFACTO�1stotherwise
38.6.9.3 Vertical Scaler
The YMEMSIZE field of the LCDC_HEOCFG4 register indicates the vertical size minus one of the image in the
system memory. The YSIZE field of the LCDC_HEOCFG3 register contains the vertical size minus one of the
window. The SCALEN bit of the LCDC_HEOCFG13 register is set to one. The scaling factor is programmed in the
YFACTOR field of the LCDC_HEOCFG13 register.
YFACTO�1st = floor
8 × 256 × YMEMSIZE − 256 × YPHIDEF
YSIZE
YFACTO�1st = YFACTO�1st + 1
YMEMSIZEmax = floor
YFACTO�1st × YSIZE + 256 × YPHIDEF
2048
YFACTOR = YFACTO�1st − 1when YMEMSIZEmax > YMEMSIZE
YFACTOR = YFACTO�1stotherwise
38.6.10 Color Combine Unit
38.6.10.1 Window Overlay
The LCD module provides hardware support for multiple “overlay plane” that can be used to display windows on top
of the image without destroying the image located below. The overlay image can use any color depth. Using the
overlay alleviates the need to re-render the occluded portion of the image. When pixels are combined together
through the alpha blending unit, a new color is created. This new pixel is called an iterated pixel and is passed to the
next blending stage. Then, this pixel may be combined again with another pixel. The VIDPRI bit located in the
LCDC_HEOCFG12 register configures the video priority algorithm used to display the layers. When the VIDPRI bit is
written to ‘0’, the OVR1 layer is located above the HEO layer. When the VIDPRI bit is written to ‘1’, OVR1 is located
below the HEO layer.
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LCD Controller (LCDC)
Figure 38-10. Overlay Example with Two Different Video Prioritization Algorithms
HEO width
OVR1 width
Base width
Base
height
o0(x,y)
HEO
o1(x,y)
HEO
height
Overlay1
OVR1
OVR1
height
OVR2
Base Image
Video Prioritization Algorithm 1 : OVR2 > OVR1 > HEO > BASE
Base Image
HEO
OVR2
Overlay1
OVR1
Video Prioritization Algorithm 2 : OVR2 > HEO > OVR1 > BASE
38.6.10.2 Base Layer with Window Overlay Optimization
When the base layer is combined with at least one active overlay (100% opacity overlay), by default, the whole base
layer frame is retrieved from the memory though it is not visible.
To optimize the system bandwidth, the LCDC can be configured to prevent the unuseful data from being fetched from
system memory.
The following registers are used to disable an invisible area of the base layer:
•
•
•
LCDC_BASECFG5:
– field DISCXPOS (Discard Area Horizontal Position)
– field DISCYPOS (Discard Area Vertical Position)
LCDC_BASECFG6:
– field DISCXSIZE (Discard Area Horizontal Size)
– field DISCYSIZE (Discard Area Vertical Size)
LCDC_BASECFG4: bit DISCEN (Discard Area Enable)
Each time the overlay window is resized and/or moved, these configuration registers must be reconfigured according
to the new overlay window features.
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LCD Controller (LCDC)
Figure 38-11. Base Layer Discard Area
Base width
Base
height
Base Image
DISCXSIZE
Base width
Base
height
{DISCXPOS,
DISCYPOS}
Overlay1
DISCYSIZE
Discarded Area
Base Image
HEO width
Base width
Base
height
HEO Video
HEO
height
Base Image
38.6.10.3 Overlay Blending
The blending function requires two pixels (one iterated from the previous blending stage and one from the current
overlay color) and a set of blending configuration parameters. These parameters define the color operation.
Figure 38-12. Alpha Blender Function
iter[n-1]
GA
OVR
From
LAEN
Shadow
REVALPHA
Registers ITER
ITER2BL
CRKEY
INV
DMA
GAEN
RGBKEY
RGBMASK
OVRDEF
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la
ovr
Blending
Function
iter[n]
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LCD Controller (LCDC)
Figure 38-13. Alpha Blender Database
la
ovr
iter[n-1]
OVR
ITER
OVRDEF
GA
"0"
"0"
GAEN
0
0
0
DMA
"0"
LAEN
0
0
Alpha * ovr + (1 - Alpha) * iter[n-1]
REVALPHA
ovr
RGBKEY
ovr iter[n-1]
0
MATCH
LOGIC
RGBMASK
CRKEY
0
Inverted
INV
0
iter[n]
38.6.10.4 Window Blending
Figure 38-14. 256-level Alpha Blending
Base Image
OVR1 25 %
HEO 75 %
Video Prioritization Algorithm 1: OVR1 > HEO > BASE
38.6.10.5 Color Keying
Color keying involves a method of bit-block image transfer (Blit). This entails blitting one image onto another where
not all the pixels are copied. Blitting usually involves two bitmaps: a source bitmap and a destination bitmap. A raster
operation (ROP) is performed to define whether the iterated color or the overlay color is to be visible or not.
38.6.10.5.1 Source Color Keying
If the masked overlay color matches the color key, the iterated color is selected and Source Color Keying is activated
using the following configuration sequence:
1.
2.
Select the overlay to blit.
Write a ‘0’ to DSTKEY.
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LCD Controller (LCDC)
3.
4.
5.
Activate Color Keying by writing a ‘1’ to CRKEY.
Configure the Color Key by writing RKEY, GKEY and BKEY fields.
Configure the Color Mask by writing RKEY, GKEY and BKEY fields.
When the field RMASK, GMASK, or BMASK is configured to ‘0’, the comparison is disabled and the raster operation
is activated.
38.6.10.5.2 Destination Color Keying
If the iterated masked color matches the color key then the overlay color is selected, Destination Color Keying is
activated using the following configuration sequence:
1.
2.
3.
4.
5.
Select the overlay to blit.
Write a ‘1’ to DSTKEY.
Activate Color Keying by writing a ‘1’ to CRKEY bit
Configure the Color Key by writing RKEY, GKEY and BKEY fields.
Configure the Color Mask by writing RKEY, GKEY and BKEY fields.
When the field RMASK, GMASK, or BMASK is configured to ‘0’, the comparison is disabled and the raster operation
is activated.
38.6.11 LCDC PWM Controller
Figure 38-15. PWM Controller Block Diagram
0
1
3
7
15
31
63
slow_clock
PWMCVAL
==0
8-bit counter
PWMPS
6-bit prescaler
CLKPWMSEL
PWMPOL
counter 1 then it is High Bandwidth.
Example:
•
•
•
If NB_TRANS = 3, the sequence should be either
– MData0
– MData0/Data1
– MData0/Data1/Data2
If NB_TRANS = 2, the sequence should be either
– MData0
– MData0/Data1
If NB_TRANS = 1, the sequence should be
– Data0
Figure 41-15. Bank Management, Example of Three Transactions per Microframe
USB Bus
Transactions
MDATA0
MDATA1
DATA2
MDATA0
MDATA1
DATA2
USB line
RXRDY
Microcontroller FIFO
(DPR) Access
t = 125 μs
t = 52.5 μs
(40% of 125 μs)
t=0
Read Bank 1
Read Bank 2
Read Bank 3
RXRDY
Read Bank 1
• Isochronous Endpoint Handling: OUT Example
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USB High Speed Device Port (UDPHS)
The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank
with the UDPHS_EPTSTAx register in the three fields as follows:
•
•
•
TOGGLESQ_STA: PID of the data stored in the current bank
CURBK: Number of the bank currently being accessed by the microcontroller.
BUSY_BANK_STA: Number of busy bank
This is particularly useful in case of a missing data packet.
If the inter-packet delay between the OUT token and the Data is greater than the USB standard, then the ISO-OUT
transaction is ignored. (Payload data is not written, no interrupt is generated to the CPU.)
If there is a data CRC (Cyclic Redundancy Check) error, the payload is, none the less, written in the endpoint. The
ERR_CRC_NTR flag is set in UDPHS_EPTSTAx register.
If the endpoint is already full, the packet is not written in the DPRAM. The ERR_FL_ISO flag is set in
UDPHS_EPTSTAx.
If the payload data is greater than the maximum size of the endpoint, then the ERR_OVFLW flag is set. It is the task
of the CPU to manage this error. The data packet is written in the endpoint (except the extra data).
If the host sends a Zero Length Packet, and the endpoint is free, no data is written in the endpoint, the RXRDY_TXKL
flag is set, and the BYTE_COUNT field in UDPHS_EPTSTAx register is null.
The FRCESTALL command bit is unused for an isochronous endpoint.
Otherwise, payload data is written in the endpoint, the RXRDY_TXKL interrupt is generated and the BYTE_COUNT
in UDPHS_EPTSTAx register is updated.
41.6.10.5 STALL
STALL is returned by a function in response to an IN token or after the data phase of an OUT or in response to a
PING transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request
is not supported.
•
OUT
To stall an endpoint, set the FRCESTALL bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has
been set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register.
•
IN
Set the FRCESTALL bit in UDPHS_EPTSETSTAx register.
Figure 41-16. Stall Handshake Data OUT Transfer
USB Bus
Packets
Token OUT
Data OUT
Stall PID
FRCESTALL
Set by firmware
Cleared by firmware
Interrupt Pending
STALL_SNT
Set by hardware
© 2020 Microchip Technology Inc.
Complete Datasheet
Cleared by firmware
DS60001579C-page 1106
SAM9X60
USB High Speed Device Port (UDPHS)
Figure 41-17. Stall Handshake Data IN Transfer
USB Bus
Packets
Token IN
Stall PID
FRCESTALL
Cleared by firmware
Set by firmware
Interrupt Pending
STALL_SNT
Set by hardware
Cleared by firmware
41.6.11 Speed Identification
The high speed reset is managed by hardware.
At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset.
At the end of the reset process (full or high), the ENDRESET interrupt is generated.
Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device.
41.6.12 USB V2.0 High Speed Global Interrupt
Interrupts are defined in UDPHS Interrupt Enable Register (UDPHS_IEN) and in UDPHS Interrupt Status Register
(UDPHS_INTSTA).
41.6.13 Endpoint Interrupts
Interrupts are enabled in UDPHS_IEN (see UDPHS Interrupt Enable Register) and individually masked in
UDPHS_EPTCTLENBx (see UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)).
Table 41-4. Endpoint Interrupt Source Masks
SHRT_PCKT
Short Packet Interrupt
BUSY_BANK
Busy Bank Interrupt
NAK_OUT
NAKOUT Interrupt
NAK_IN/ERR_FLUSH
NAKIN/Error Flush Interrupt
STALL_SNT/ERR_CRC_NTR
Stall Sent/CRC error/Number of Transaction Error Interrupt
RX_SETUP/ERR_FL_ISO
Received SETUP/Error Flow Interrupt
TXRDY_TRER
TX Packet Read/Transaction Error Interrupt
TX_COMPLT
Transmitted IN Data Complete Interrupt
RXRDY_TXKL
Received OUT Data Interrupt
ERR_OVFLW
Overflow Error Interrupt
MDATA_RX
MDATA Interrupt
DATAX_RX
DATAx Interrupt
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1107
SAM9X60
USB High Speed Device Port (UDPHS)
Figure 41-18. UDPHS Interrupt Control Interface
(UDPHS_IEN)
Global IT mask
Global IT sources
DET_SUSPD
MICRO_SOF
USB Global
IT Sources
INT_SOF
ENDRESET
WAKE_UP
ENDOFRSM
UPSTR_RES
(UDPHS_EPTCTLENBx)
SHRT_PCKT
EP mask
BUSY_BANK
(UDPHS_IEN)
EPT_0
EP sources
NAK_OUT
husb2dev
interrupt
NAK_IN/ERR_FLUSH
STALL_SNT/ER_CRC_NTR
EPT0 IT
Sources
RX_SETUP/ERR_FL_ISO
TXRDY_TRER
TX_COMPLT
RXRDY_TXKL
ERR_OVFLW
MDATA_RX
DATAX_RX
(UDPHS_IEN)
EPT_x
EP mask
EP sources
(UDPHS_EPTCTLx)
INTDIS_DMA
EPT1-6 IT
Sources
disable DMA
channelx request
(UDPHS_DMACONTROLx)
mask
(UDPHS_IEN)
DMA_x
END_BUFFIT
mask
DMA CH x
END_TR_IT
mask
DESC_LD_IT
41.6.14 Power Modes
41.6.14.1 Controlling Device States
A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus
Specification, Rev 2.0.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1108
SAM9X60
USB High Speed Device Port (UDPHS)
Figure 41-19. UDPHS Device State Diagram
Attached
Hub Reset
Hub
or
Configured
Deconfigured
Bus Inactive
Powered
Suspended
Bus Activity
Power
Interruption
Reset
Bus Inactive
Suspended
Default
Bus Activity
Reset
Address
Assigned
Bus Inactive
Address
Suspended
Bus Activity
Device
Deconfigured
Device
Configured
Bus Inactive
Configured
Suspended
Bus Activity
Movement from one state to another depends on the USB bus state or on standard requests sent through control
transactions via the default endpoint (endpoint 0).
After a period of bus inactivity, the USB device enters Suspend mode. Accepting Suspend/Resume requests from the
USB host is mandatory. Constraints in Suspend mode are very strict for bus-powered applications; devices may not
consume more than 500 μA on the USB bus.
While in Suspend mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device
may send a wakeup request to the host, e.g., waking up a PC by moving a USB mouse.
The wakeup feature is not mandatory for all devices and must be negotiated with the host.
41.6.14.2 Not Powered State
Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a host, device power
consumption can be reduced by the DETACH bit in UDPHS_CTRL. Disabling the transceiver is automatically done.
HSDM, HSDP, FSDP and FSDP lines are tied to GND pulldowns integrated in the hub downstream ports.
41.6.14.3 Entering Attached State
When no device is connected, the USB FSDP and FSDM signals are tied to GND by 15 KΩ pulldowns integrated in
the hub downstream ports. When a device is attached to an hub downstream port, the device connects a 1.5 KΩ
pullup on FSDP. The USB bus line goes into IDLE state, FSDP is pulled up by the device 1.5 KΩ resistor to 3.3V and
FSDM is pulled down by the 15 KΩ resistor to GND of the host.
After pullup connection, the device enters the powered state. The transceiver remains disabled until bus activity is
detected.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1109
SAM9X60
USB High Speed Device Port (UDPHS)
In case of low power consumption need, the device can be stopped. When the device detects the VBUS, the
software must enable the USB transceiver by enabling the EN_UDPHS bit in UDPHS_CTRL register.
The software can detach the pullup by setting DETACH bit in UDPHS_CTRL register.
41.6.14.4 From Powered State to Default State (Reset)
After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmasked flag ENDRESET is
set in the UDPHS_IEN register and an interrupt is triggered.
Once the ENDRESET interrupt has been triggered, the device enters Default State. In this state, the UDPHS
software must:
•
•
•
Enable the default endpoint, setting the EPT_ENABL flag in the UDPHS_EPTCTLENB[0] register and,
optionally, enabling the interrupt for endpoint 0 by writing 1 in EPT_0 of the UDPHS_IEN register. The
enumeration then begins by a control transfer.
Configure the Interrupt Mask Register which has been reset by the USB reset detection
Enable the transceiver.
In this state, the EN_UDPHS bit in UDPHS_CTRL register must be enabled.
41.6.14.5 From Default State to Address State (Address Assigned)
After a Set Address standard device request, the USB host peripheral enters the address state.
WARNING
Before the device enters address state, it must achieve the Status IN transaction of the control transfer,
i.e., the UDPHS device sets its new address once the TX_COMPLT flag in the UDPHS_EPTCTL[0]
register has been received and cleared.
To move to address state, the driver software sets the DEV_ADDR field and the FADDR_EN flag in the
UDPHS_CTRL register.
41.6.14.6 From Address State to Configured State (Device Configured)
Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints
corresponding to the current configuration. This is done by setting the BK_NUMBER, EPT_TYPE, EPT_DIR and
EPT_SIZE fields in the UDPHS_EPTCFGx registers and enabling them by setting the EPT_ENABL flag in the
UDPHS_EPTCTLENBx registers, and, optionally, enabling corresponding interrupts in the UDPHS_IEN register.
41.6.14.7 Entering Suspend State (Bus Activity)
When a Suspend (no bus activity on the USB bus) is detected, the DET_SUSPD signal in the UDPHS_STA register
is set. This triggers an interrupt if the corresponding bit is set in the UDPHS_IEN register. This flag is cleared by
writing to the UDPHS_CLRINT register. Then the device enters Suspend mode.
In this state bus powered devices must drain less than 500 μA from the 5V VBUS. As an example, the microcontroller
switches to slow clock, disables the PLL and main oscillator, and goes into Idle mode. It may also switch off other
devices on the board.
The UDPHS device peripheral clocks can be switched off. Resume event is asynchronously detected.
41.6.14.8 Receiving a Host Resume
In Suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks disabled
(however, the pullup should not be removed).
Once the resume is detected on the bus, the signal WAKE_UP in the UDPHS_INTSTA is set. It may generate an
interrupt if the corresponding bit in the UDPHS_IEN register is set. This interrupt may be used to wake up the core,
enable PLL and main oscillators and configure clocks.
41.6.14.9 Sending an External Resume
In Suspend State it is possible to wake up the host by sending an external resume.
The device waits at least 5 ms after being entered in Suspend State before sending an external resume.
The device must force a K state from 1 to 15 ms to resume the host.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1110
SAM9X60
USB High Speed Device Port (UDPHS)
41.6.15 Test Mode
A device must support the TEST_MODE feature when in the Default, Address or Configured High Speed device
states.
TEST_MODE can be:
•
•
•
•
Test_J
Test_K
Test_Packet
Test_SEO_NAK
(See UDPHS Test Register for definitions of each test mode.)
const char test_packet_buffer[] = {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,
0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,
0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,
0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E
};
© 2020 Microchip Technology Inc.
Complete Datasheet
//
//
//
//
//
//
JKJKJKJK * 9
JJKKJJKK * 8
JJKKJJKK * 8
JJJJJJJKKKKKKK * 8
JJJJJJJK * 8
{JKKKKKKK * 10}, JK
DS60001579C-page 1111
SAM9X60
USB High Speed Device Port (UDPHS)
41.7
Register Summary
Notes: The registers below have two modes: Control, Bulk, Interrupt Endpoints mode and Isochronous Endpoints
mode. In this register summary, both modes are displayed at the same offset.
• UDPHS_EPTCTLENB
• UDPHS_EPTCTLDIS
• UDPHS_EPTCTL
• UDPHS_EPTSETSTA
• UDPHS_EPTCLRSTA
• UDPHS_EPTSTA
Offset
0x00
0x04
0x08
...
0x0F
Name
UDPHS_CTRL
UDPHS_FNUM
UDPHS_IEN
0x14
UDPHS_INTSTA
0x18
UDPHS_CLRINT
0x1C
UDPHS_EPTRST
0x20
...
0xDF
Reserved
0xE4
...
0xFF
0x0100
0x0104
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
FADDR_EN
FNUM_ERR
6
5
4
3
2
PULLD_DIS REWAKEUP
DEV_ADDR[6:0]
FRAME_NUMBER[4:0]
1
0
DETACH
EN_UDPHS
FRAME_NUMBER[10:5]
MICRO_FRAME_NUM[2:0]
Reserved
0x10
0xE0
Bit Pos.
UDPHS_TST
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
DMA_7
DMA_6
EPT_15
EPT_14
EPT_7
EPT_6
UPSTR_RES ENDOFRSM
DMA_7
DMA_6
EPT_15
EPT_14
EPT_7
EPT_6
UPSTR_RES ENDOFRSM
DMA_5
EPT_13
EPT_5
WAKE_UP
DMA_5
EPT_13
EPT_5
WAKE_UP
DMA_4
EPT_12
EPT_4
ENDRESET
DMA_4
EPT_12
EPT_4
ENDRESET
DMA_3
EPT_11
EPT_3
INT_SOF
DMA_3
EPT_11
EPT_3
INT_SOF
DMA_2
DMA_1
EPT_10
EPT_9
EPT_2
EPT_1
MICRO_SOF DET_SUSPD
DMA_2
DMA_1
EPT_10
EPT_9
EPT_2
EPT_1
MICRO_SOF DET_SUSPD
UPSTR_RES ENDOFRSM
WAKE_UP
ENDRESET
INT_SOF
MICRO_SOF DET_SUSPD
EPT_13
EPT_5
EPT_12
EPT_4
EPT_11
EPT_3
EPT_10
EPT_2
OPMODE2
TST_PKT
TST_K
TST_J
EPT_15
EPT_7
EPT_14
EPT_6
31:24
23:16
15:8
7:0
EPT_9
EPT_1
EPT_8
EPT_0
EPT_8
EPT_0
SPEED
EPT_8
EPT_0
SPEED_CFG[1:0]
Reserved
UDPHS_EPTCFG0
UDPHS_EPTCTLE
NB0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
EPT_MAPD
BK_NUMBER[1:0]
SHRT_PCKT
EPT_TYPE[1:0]
NB_TRANS[1:0]
EPT_SIZE[2:0]
EPT_DIR
BUSY_BANK
NAK_OUT
7:0
© 2020 Microchip Technology Inc.
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
Complete Datasheet
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
DS60001579C-page 1112
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
Name
0x0104
UDPHS_EPTCTLE
NB0
0x0108
0x0108
0x010C
0x010C
UDPHS_EPTCTLDI
S0
UDPHS_EPTCTLDI
S0
UDPHS_EPTCTL0
UDPHS_EPTCTL0
Bit Pos.
7
31:24
23:16
SHRT_PCKT
0x0114
0x0114
0x0118
0x0118
0x011C
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
4
3
2
1
0
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
BUSY_BANK
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_DISABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_DISABL
BUSY_BANK
15:8
MDATA_RX
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
Reserved
UDPHS_EPTSETS
TA0
UDPHS_EPTSETS
TA0
UDPHS_EPTCLRS
TA0
UDPHS_EPTCLRS
TA0
UDPHS_EPTSTA0
31:24
23:16
UDPHS_EPTSTA0
TXRDY
RXRDY_TXK
L
TXRDY_TRE
R
RXRDY_TXK
L
15:8
7:0
31:24
23:16
FRCESTALL
15:8
7:0
31:24
23:16
15:8
NAK_OUT
NAK_IN
STALL_SNT
7:0
31:24
23:16
TOGGLESQ FRCESTALL
15:8
ERR_FLUSH
7:0
31:24
23:16
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
0x011C
5
BUSY_BANK
15:8
7:0
0x0110
...
0x0113
6
15:8
7:0
RX_SETUP
ERR_CRC_N
ERR_FL_ISO
TR
TX_COMPLT
RXRDY_TXK
L
TX_COMPLT
RXRDY_TXK
L
TOGGLESQ
BYTE_COUNT[3:0]
NAK_IN
STALL_SNT
BYTE_COUNT[10:4]
BUSY_BANK_STA[1:0]
RX_SETUP
TXRDY
CURBK_CTLDIR[1:0]
RXRDY_TXK
TX_COMPLT
ERR_OVFLW
L
TOGGLESQ_STA[1:0]
FRCESTALL
SHRT_PCKT
BYTE_COUNT[10:4]
BYTE_COUNT[3:0]
BUSY_BANK_STA[1:0]
CURBK[1:0]
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
TOGGLESQ_STA[1:0]
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1113
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
Name
0x0120
UDPHS_EPTCFG1
0x0124
0x0124
0x0128
0x0128
0x012C
0x012C
UDPHS_EPTCTLE
NB1
UDPHS_EPTCTLE
NB1
UDPHS_EPTCTLDI
S1
UDPHS_EPTCTLDI
S1
UDPHS_EPTCTL1
UDPHS_EPTCTL1
Bit Pos.
7
31:24
23:16
EPT_MAPD
15:8
7:0
31:24
23:16
0x0134
0x0134
0x0138
0x0138
BK_NUMBER[1:0]
SHRT_PCKT
5
4
EPT_TYPE[1:0]
3
2
1
0
NB_TRANS[1:0]
EPT_SIZE[2:0]
EPT_DIR
BUSY_BANK
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
BUSY_BANK
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_DISABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_DISABL
BUSY_BANK
15:8
7:0
0x0130
...
0x0133
6
MDATA_RX
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
Reserved
UDPHS_EPTSETS
TA1
UDPHS_EPTSETS
TA1
UDPHS_EPTCLRS
TA1
UDPHS_EPTCLRS
TA1
31:24
23:16
TXRDY
RXRDY_TXK
L
TXRDY_TRE
R
RXRDY_TXK
L
15:8
7:0
31:24
23:16
FRCESTALL
15:8
7:0
31:24
23:16
15:8
NAK_OUT
NAK_IN
STALL_SNT
7:0
31:24
23:16
TOGGLESQ FRCESTALL
15:8
ERR_FLUSH
7:0
TOGGLESQ
© 2020 Microchip Technology Inc.
RX_SETUP
ERR_CRC_N
ERR_FL_ISO
TR
Complete Datasheet
TX_COMPLT
RXRDY_TXK
L
TX_COMPLT
RXRDY_TXK
L
DS60001579C-page 1114
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
0x013C
Name
UDPHS_EPTSTA1
Bit Pos.
7
31:24
23:16
SHRT_PCKT
15:8
7:0
31:24
23:16
0x013C
0x0140
0x0144
0x0144
0x0148
0x0148
0x014C
UDPHS_EPTSTA1
UDPHS_EPTCFG2
UDPHS_EPTCTLE
NB2
UDPHS_EPTCTLE
NB2
UDPHS_EPTCTLDI
S2
UDPHS_EPTCTLDI
S2
UDPHS_EPTCTL2
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
6
5
NAK_OUT
NAK_IN
STALL_SNT
UDPHS_EPTCTL2
BK_NUMBER[1:0]
SHRT_PCKT
0x0154
0x0154
RX_SETUP
TXRDY
1
0
CURBK_CTLDIR[1:0]
RXRDY_TXK
TX_COMPLT
ERR_OVFLW
L
EPT_TYPE[1:0]
NB_TRANS[1:0]
EPT_SIZE[2:0]
EPT_DIR
BUSY_BANK
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
BUSY_BANK
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_DISABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_DISABL
BUSY_BANK
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
SHRT_PCKT
15:8
7:0
0x0150
...
0x0153
2
TOGGLESQ_STA[1:0]
FRCESTALL
SHRT_PCKT
BYTE_COUNT[10:4]
BYTE_COUNT[3:0]
BUSY_BANK_STA[1:0]
CURBK[1:0]
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
TOGGLESQ_STA[1:0]
EPT_MAPD
7:0
0x014C
3
BYTE_COUNT[10:4]
BUSY_BANK_STA[1:0]
BYTE_COUNT[3:0]
15:8
31:24
23:16
4
MDATA_RX
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
Reserved
UDPHS_EPTSETS
TA2
UDPHS_EPTSETS
TA2
31:24
23:16
TXRDY
RXRDY_TXK
L
TXRDY_TRE
R
RXRDY_TXK
L
15:8
7:0
31:24
23:16
15:8
FRCESTALL
7:0
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1115
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
Name
0x0158
UDPHS_EPTCLRS
TA2
0x0158
0x015C
UDPHS_EPTCLRS
TA2
UDPHS_EPTSTA2
Bit Pos.
0x0160
0x0164
0x0164
0x0168
UDPHS_EPTSTA2
UDPHS_EPTCFG3
UDPHS_EPTCTLE
NB3
UDPHS_EPTCTLE
NB3
UDPHS_EPTCTLDI
S3
6
5
4
15:8
NAK_OUT
NAK_IN
STALL_SNT
RX_SETUP
7:0
31:24
23:16
TOGGLESQ FRCESTALL
15:8
ERR_FLUSH
7:0
31:24
23:16
SHRT_PCKT
15:8
NAK_OUT
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
ERR_CRC_N
ERR_FL_ISO
TR
0x016C
0x016C
UDPHS_EPTCTLDI
S3
UDPHS_EPTCTL3
UDPHS_EPTCTL3
1
TX_COMPLT
RXRDY_TXK
L
TX_COMPLT
RXRDY_TXK
L
0
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
CURBK_CTLDIR[1:0]
RXRDY_TXK
TX_COMPLT
ERR_OVFLW
L
TOGGLESQ_STA[1:0]
FRCESTALL
SHRT_PCKT
BYTE_COUNT[10:4]
BYTE_COUNT[3:0]
BUSY_BANK_STA[1:0]
CURBK[1:0]
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
TOGGLESQ_STA[1:0]
EPT_MAPD
BK_NUMBER[1:0]
SHRT_PCKT
EPT_TYPE[1:0]
NB_TRANS[1:0]
EPT_SIZE[2:0]
EPT_DIR
BUSY_BANK
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
31:24
23:16
BYTE_COUNT[10:4]
BUSY_BANK_STA[1:0]
BYTE_COUNT[3:0]
15:8
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
BUSY_BANK
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_DISABL
SHRT_PCKT
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_DISABL
BUSY_BANK
15:8
7:0
0x0170
...
0x0173
2
TOGGLESQ
7:0
0x0168
3
31:24
23:16
7:0
31:24
23:16
0x015C
7
MDATA_RX
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
Reserved
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1116
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
Name
0x0174
UDPHS_EPTSETS
TA3
0x0174
0x0178
0x0178
0x017C
UDPHS_EPTSETS
TA3
UDPHS_EPTCLRS
TA3
UDPHS_EPTCLRS
TA3
UDPHS_EPTSTA3
Bit Pos.
0x0180
0x0184
UDPHS_EPTSTA3
UDPHS_EPTCFG4
UDPHS_EPTCTLE
NB4
6
5
0x0188
0x0188
0x018C
UDPHS_EPTCTLE
NB4
UDPHS_EPTCTLDI
S4
UDPHS_EPTCTLDI
S4
UDPHS_EPTCTL4
3
2
1
TXRDY
RXRDY_TXK
L
TXRDY_TRE
R
RXRDY_TXK
L
15:8
7:0
31:24
23:16
0
FRCESTALL
15:8
7:0
31:24
23:16
15:8
NAK_OUT
NAK_IN
STALL_SNT
7:0
31:24
23:16
TOGGLESQ FRCESTALL
15:8
ERR_FLUSH
7:0
31:24
23:16
SHRT_PCKT
15:8
NAK_OUT
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
31:24
23:16
RX_SETUP
ERR_CRC_N
ERR_FL_ISO
TR
TX_COMPLT
RXRDY_TXK
L
TX_COMPLT
RXRDY_TXK
L
TOGGLESQ
BYTE_COUNT[10:4]
BUSY_BANK_STA[1:0]
BYTE_COUNT[3:0]
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
CURBK_CTLDIR[1:0]
RXRDY_TXK
TX_COMPLT
ERR_OVFLW
L
TOGGLESQ_STA[1:0]
FRCESTALL
SHRT_PCKT
BYTE_COUNT[10:4]
BYTE_COUNT[3:0]
BUSY_BANK_STA[1:0]
CURBK[1:0]
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
TOGGLESQ_STA[1:0]
EPT_MAPD
BK_NUMBER[1:0]
SHRT_PCKT
EPT_TYPE[1:0]
NB_TRANS[1:0]
EPT_SIZE[2:0]
EPT_DIR
BUSY_BANK
NAK_OUT
NAK_IN
STALL_SNT
7:0
0x0184
4
31:24
23:16
7:0
31:24
23:16
0x017C
7
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
SHRT_PCKT
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
BUSY_BANK
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_DISABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_DISABL
BUSY_BANK
7:0
© 2020 Microchip Technology Inc.
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
Complete Datasheet
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
DS60001579C-page 1117
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
0x018C
Name
UDPHS_EPTCTL4
Bit Pos.
7
31:24
23:16
SHRT_PCKT
0x0194
0x0194
0x0198
0x0198
0x019C
0x01A0
0x01A4
0x01A4
0x01A8
4
3
2
1
0
MDATA_RX
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
Reserved
UDPHS_EPTSETS
TA4
UDPHS_EPTSETS
TA4
UDPHS_EPTCLRS
TA4
UDPHS_EPTCLRS
TA4
UDPHS_EPTSTA4
31:24
23:16
UDPHS_EPTSTA4
UDPHS_EPTCFG5
UDPHS_EPTCTLE
NB5
UDPHS_EPTCTLE
NB5
UDPHS_EPTCTLDI
S5
TXRDY
RXRDY_TXK
L
TXRDY_TRE
R
RXRDY_TXK
L
15:8
7:0
31:24
23:16
FRCESTALL
15:8
7:0
31:24
23:16
15:8
NAK_OUT
NAK_IN
STALL_SNT
7:0
31:24
23:16
TOGGLESQ FRCESTALL
15:8
ERR_FLUSH
7:0
31:24
23:16
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
0x019C
5
BUSY_BANK
15:8
7:0
0x0190
...
0x0193
6
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
RX_SETUP
ERR_CRC_N
ERR_FL_ISO
TR
TX_COMPLT
RXRDY_TXK
L
TX_COMPLT
RXRDY_TXK
L
TOGGLESQ
BYTE_COUNT[10:4]
BUSY_BANK_STA[1:0]
BYTE_COUNT[3:0]
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
CURBK_CTLDIR[1:0]
RXRDY_TXK
TX_COMPLT
ERR_OVFLW
L
TOGGLESQ_STA[1:0]
FRCESTALL
SHRT_PCKT
BYTE_COUNT[10:4]
BYTE_COUNT[3:0]
BUSY_BANK_STA[1:0]
CURBK[1:0]
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
TOGGLESQ_STA[1:0]
EPT_MAPD
BK_NUMBER[1:0]
SHRT_PCKT
EPT_TYPE[1:0]
NB_TRANS[1:0]
EPT_SIZE[2:0]
EPT_DIR
BUSY_BANK
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
BUSY_BANK
7:0
© 2020 Microchip Technology Inc.
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
Complete Datasheet
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_DISABL
DS60001579C-page 1118
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
Name
0x01A8
UDPHS_EPTCTLDI
S5
0x01AC
0x01AC
UDPHS_EPTCTL5
UDPHS_EPTCTL5
Bit Pos.
7
31:24
23:16
SHRT_PCKT
0x01B4
0x01B4
0x01B8
0x01B8
0x01BC
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
0x01C0
0x01C4
4
3
2
1
0
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_DISABL
BUSY_BANK
15:8
MDATA_RX
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
Reserved
UDPHS_EPTSETS
TA5
UDPHS_EPTSETS
TA5
UDPHS_EPTCLRS
TA5
UDPHS_EPTCLRS
TA5
UDPHS_EPTSTA5
31:24
23:16
UDPHS_EPTSTA5
UDPHS_EPTCFG6
UDPHS_EPTCTLE
NB6
TXRDY
RXRDY_TXK
L
TXRDY_TRE
R
RXRDY_TXK
L
15:8
7:0
31:24
23:16
FRCESTALL
15:8
7:0
31:24
23:16
15:8
NAK_OUT
NAK_IN
STALL_SNT
7:0
31:24
23:16
TOGGLESQ FRCESTALL
15:8
ERR_FLUSH
7:0
31:24
23:16
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
0x01BC
5
BUSY_BANK
15:8
7:0
0x01B0
...
0x01B3
6
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
RX_SETUP
ERR_CRC_N
ERR_FL_ISO
TR
TX_COMPLT
RXRDY_TXK
L
TX_COMPLT
RXRDY_TXK
L
TOGGLESQ
BYTE_COUNT[10:4]
BUSY_BANK_STA[1:0]
BYTE_COUNT[3:0]
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
CURBK_CTLDIR[1:0]
RXRDY_TXK
TX_COMPLT
ERR_OVFLW
L
TOGGLESQ_STA[1:0]
FRCESTALL
SHRT_PCKT
BYTE_COUNT[10:4]
BYTE_COUNT[3:0]
BUSY_BANK_STA[1:0]
CURBK[1:0]
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
TOGGLESQ_STA[1:0]
EPT_MAPD
BK_NUMBER[1:0]
SHRT_PCKT
EPT_TYPE[1:0]
NB_TRANS[1:0]
EPT_SIZE[2:0]
EPT_DIR
BUSY_BANK
NAK_OUT
7:0
© 2020 Microchip Technology Inc.
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
Complete Datasheet
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
DS60001579C-page 1119
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
Name
0x01C4
UDPHS_EPTCTLE
NB6
0x01C8
0x01C8
0x01CC
0x01CC
UDPHS_EPTCTLDI
S6
UDPHS_EPTCTLDI
S6
UDPHS_EPTCTL6
UDPHS_EPTCTL6
Bit Pos.
7
31:24
23:16
SHRT_PCKT
0x01D4
0x01D4
0x01D8
0x01D8
0x01DC
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
4
3
2
1
0
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
BUSY_BANK
15:8
7:0
31:24
23:16
MDATA_RX
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
SHRT_PCKT
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_DISABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_DISABL
BUSY_BANK
15:8
MDATA_RX
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
NYET_DIS
INTDIS_DMA
TX_COMPLT
RXRDY_TXK
ERR_OVFLW
L
AUTO_VALID EPT_ENABL
BUSY_BANK
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
DATAX_RX
INTDIS_DMA
AUTO_VALID EPT_ENABL
Reserved
UDPHS_EPTSETS
TA6
UDPHS_EPTSETS
TA6
UDPHS_EPTCLRS
TA6
UDPHS_EPTCLRS
TA6
UDPHS_EPTSTA6
31:24
23:16
UDPHS_EPTSTA6
TXRDY
RXRDY_TXK
L
TXRDY_TRE
R
RXRDY_TXK
L
15:8
7:0
31:24
23:16
FRCESTALL
15:8
7:0
31:24
23:16
15:8
NAK_OUT
NAK_IN
STALL_SNT
7:0
31:24
23:16
TOGGLESQ FRCESTALL
15:8
ERR_FLUSH
7:0
31:24
23:16
SHRT_PCKT
15:8
NAK_OUT
7:0
31:24
23:16
0x01DC
5
BUSY_BANK
15:8
7:0
0x01D0
...
0x01D3
6
15:8
7:0
RX_SETUP
ERR_CRC_N
ERR_FL_ISO
TR
TX_COMPLT
RXRDY_TXK
L
TX_COMPLT
RXRDY_TXK
L
TOGGLESQ
BYTE_COUNT[3:0]
NAK_IN
STALL_SNT
BYTE_COUNT[10:4]
BUSY_BANK_STA[1:0]
RX_SETUP
TXRDY
CURBK_CTLDIR[1:0]
RXRDY_TXK
TX_COMPLT
ERR_OVFLW
L
TOGGLESQ_STA[1:0]
FRCESTALL
SHRT_PCKT
BYTE_COUNT[10:4]
BYTE_COUNT[3:0]
BUSY_BANK_STA[1:0]
CURBK[1:0]
ERR_CRC_N
TXRDY_TRE
RXRDY_TXK
ERR_FLUSH
ERR_FL_ISO
TX_COMPLT
ERR_OVFLW
TR
R
L
TOGGLESQ_STA[1:0]
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1120
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
Name
0x01E0
...
0x030F
Reserved
0x0310
UDPHS_DMANXTD
SC1
0x0314
UDPHS_DMAADDR
ESS1
0x0318
UDPHS_DMACONT
ROL1
0x031C
UDPHS_DMASTAT
US1
0x0320
UDPHS_DMANXTD
SC2
0x0324
UDPHS_DMAADDR
ESS2
0x0328
UDPHS_DMACONT
ROL2
0x032C
UDPHS_DMASTAT
US2
0x0330
UDPHS_DMANXTD
SC3
0x0334
UDPHS_DMAADDR
ESS3
0x0338
UDPHS_DMACONT
ROL3
0x033C
UDPHS_DMASTAT
US3
0x0340
UDPHS_DMANXTD
SC4
0x0344
UDPHS_DMAADDR
ESS4
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
5
4
3
2
1
0
NXT_DSC_ADD[31:24]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[7:0]
BUFF_ADD[31:24]
BUFF_ADD[23:16]
BUFF_ADD[15:8]
BUFF_ADD[7:0]
BUFF_LENGTH[15:8]
BUFF_LENGTH[7:0]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_COUNT[15:8]
BUFF_COUNT[7:0]
DESC_LDST END_BF_ST END_TR_ST
NXT_DSC_ADD[31:24]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[7:0]
BUFF_ADD[31:24]
BUFF_ADD[23:16]
BUFF_ADD[15:8]
BUFF_ADD[7:0]
BUFF_LENGTH[15:8]
BUFF_LENGTH[7:0]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_COUNT[15:8]
BUFF_COUNT[7:0]
DESC_LDST END_BF_ST END_TR_ST
NXT_DSC_ADD[31:24]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[7:0]
BUFF_ADD[31:24]
BUFF_ADD[23:16]
BUFF_ADD[15:8]
BUFF_ADD[7:0]
BUFF_LENGTH[15:8]
BUFF_LENGTH[7:0]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_COUNT[15:8]
BUFF_COUNT[7:0]
© 2020 Microchip Technology Inc.
DESC_LDST END_BF_ST END_TR_ST
NXT_DSC_ADD[31:24]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[7:0]
BUFF_ADD[31:24]
BUFF_ADD[23:16]
BUFF_ADD[15:8]
BUFF_ADD[7:0]
Complete Datasheet
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
DS60001579C-page 1121
SAM9X60
USB High Speed Device Port (UDPHS)
...........continued
Offset
Name
0x0348
UDPHS_DMACONT
ROL4
0x034C
UDPHS_DMASTAT
US4
0x0350
UDPHS_DMANXTD
SC5
0x0354
UDPHS_DMAADDR
ESS5
0x0358
UDPHS_DMACONT
ROL5
0x035C
UDPHS_DMASTAT
US5
0x0360
UDPHS_DMANXTD
SC6
0x0364
UDPHS_DMAADDR
ESS6
0x0368
UDPHS_DMACONT
ROL6
0x036C
UDPHS_DMASTAT
US6
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
6
5
4
3
2
1
0
BUFF_LENGTH[15:8]
BUFF_LENGTH[7:0]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_COUNT[15:8]
BUFF_COUNT[7:0]
DESC_LDST END_BF_ST END_TR_ST
NXT_DSC_ADD[31:24]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[7:0]
BUFF_ADD[31:24]
BUFF_ADD[23:16]
BUFF_ADD[15:8]
BUFF_ADD[7:0]
BUFF_LENGTH[15:8]
BUFF_LENGTH[7:0]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_COUNT[15:8]
BUFF_COUNT[7:0]
DESC_LDST END_BF_ST END_TR_ST
NXT_DSC_ADD[31:24]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[7:0]
BUFF_ADD[31:24]
BUFF_ADD[23:16]
BUFF_ADD[15:8]
BUFF_ADD[7:0]
BUFF_LENGTH[15:8]
BUFF_LENGTH[7:0]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_COUNT[15:8]
BUFF_COUNT[7:0]
© 2020 Microchip Technology Inc.
DESC_LDST END_BF_ST END_TR_ST
Complete Datasheet
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
DS60001579C-page 1122
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.1
UDPHS Control Register
Name:
Offset:
Reset:
Property:
Bit
UDPHS_CTRL
0x00
0x00000200
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
PULLD_DIS
R/W
0
10
REWAKEUP
R/W
0
9
DETACH
R/W
1
8
EN_UDPHS
R/W
0
7
FADDR_EN
R/W
0
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
3
DEV_ADDR[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – PULLD_DIS Pulldown Disable (cleared upon USB reset)
When set, there is no pulldown on DP & DM. (DM Pulldown = DP Pulldown = 0).
Note: If the DETACH bit is also set, device DP & DM are left in high impedance state.
(See description of bit “DETACH”.)
DETACH
PULLD_DIS
DP
DM
Condition
0
0
1
1
0
1
0
1
Pullup
Pullup
Pulldown
High impedance state
Pulldown
High impedance state
Pulldown
High impedance state
Not recommended
VBUS present
No VBUS
VBUS present & software disconnect
Bit 10 – REWAKEUP Send Remote Wakeup (cleared upon USB reset)
An Upstream Resume is sent only after the UDPHS bus has been in SUSPEND state for at least 5 ms.
This bit is automatically cleared by hardware at the end of the Upstream Resume.
Value
Description
0
Remote Wakeup is disabled (read), or this bit has no effect (write).
1
Remote Wakeup is enabled (read), or this bit forces an external interrupt on the UDPHS controller for
Remote Wakeup purposes.
Bit 9 – DETACH Detach Command
See description of bit “PULL_DIS”.
Value
Description
0
UDPHS is attached (read), or this bit pulls up the DP line (attach command) (write).
1
UDPHS is detached, UTMI transceiver is suspended (read), or this bit simulates a detach on the
UDPHS line and forces the UTMI transceiver into suspend state (Suspend M = 0) (write).
Bit 8 – EN_UDPHS UDPHS Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1123
SAM9X60
USB High Speed Device Port (UDPHS)
Value
0
1
Description
UDPHS is disabled (read), or this bit disables and resets the UDPHS controller (write). Switch the host
to UTMI.
UDPHS is enabled (read), or this bit enables the UDPHS controller (write). Switch the host to UTMI.
Bit 7 – FADDR_EN Function Address Enable (cleared upon USB reset)
Value
Description
0
Device is not in address state (read), or only the default function address is used (write).
1
Device is in address state (read), or this bit is set by the device firmware after a successful status
phase of a SET_ADDRESS transaction (write). When set, the only address accepted by the UDPHS
controller is the one stored in the UDPHS Address field. It will not be cleared afterwards by the device
firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received.
Bits 6:0 – DEV_ADDR[6:0] UDPHS Address (cleared upon USB reset)
This field contains the default address (0) after power-up or UDPHS bus reset (read), or it is written with the value set
by a SET_ADDRESS request received by the device firmware (write).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1124
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.2
UDPHS Frame Number Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
UDPHS_FNUM
0x04
0x00000000
Read-only
31
FNUM_ERR
R
0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
9
8
R
0
R
0
R
0
R
0
5
FRAME_NUMBER[4:0]
R
0
4
3
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
7
6
Access
Reset
R
0
R
0
11
10
FRAME_NUMBER[10:5]
R
R
0
0
2
1
0
MICRO_FRAME_NUM[2:0]
R
R
R
0
0
0
Bit 31 – FNUM_ERR Frame Number CRC Error (cleared upon USB reset)
This bit is set by hardware when a corrupted Frame Number in Start of Frame packet (or Micro SOF) is received.
This bit and the INT_SOF (or MICRO_SOF) interrupt are updated at the same time.
Bits 13:3 – FRAME_NUMBER[10:0] Frame Number as defined in the Packet Field Formats (cleared upon USB
reset)
This field is provided in the last received SOF packet (see INT_SOF in the UDPHS Interrupt Status Register).
Bits 2:0 – MICRO_FRAME_NUM[2:0] Microframe Number (cleared upon USB reset)
Number of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1
ms).
One microframe is received each 125 microseconds (1 ms/8).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1125
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.3
UDPHS Interrupt Enable Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
UDPHS_IEN
0x10
0x00000010
Read/Write
31
DMA_7
R/W
0
30
DMA_6
R/W
0
29
DMA_5
R/W
0
28
DMA_4
R/W
0
27
DMA_3
R/W
0
26
DMA_2
R/W
0
25
DMA_1
R/W
0
24
23
EPT_15
R/W
0
22
EPT_14
R/W
0
21
EPT_13
R/W
0
20
EPT_12
R/W
0
19
EPT_11
R/W
0
18
EPT_10
R/W
0
17
EPT_9
R/W
0
16
EPT_8
R/W
0
15
EPT_7
R/W
0
14
EPT_6
R/W
0
13
EPT_5
R/W
0
12
EPT_4
R/W
0
11
EPT_3
R/W
0
10
EPT_2
R/W
0
9
EPT_1
R/W
0
8
EPT_0
R/W
0
6
ENDOFRSM
R/W
0
5
WAKE_UP
R/W
0
4
ENDRESET
R/W
1
3
INT_SOF
R/W
0
2
MICRO_SOF
R/W
0
1
DET_SUSPD
R/W
0
0
7
UPSTR_RES
Access
R/W
Reset
0
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_x DMA Channel x Interrupt Enable (cleared upon USB reset)
Value
Description
0
Disable the interrupts for this channel.
1
Enable the interrupts for this channel.
Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – EPT_x Endpoint x Interrupt Enable (cleared upon
USB reset)
Value
Description
0
Disable the interrupts for this endpoint.
1
Enable the interrupts for this endpoint.
Bit 7 – UPSTR_RES Upstream Resume Interrupt Enable (cleared upon USB reset)
Value
Description
0
Disable Upstream Resume Interrupt.
1
Enable Upstream Resume Interrupt.
Bit 6 – ENDOFRSM End Of Resume Interrupt Enable (cleared upon USB reset)
Value
Description
0
Disable Resume Interrupt.
1
Enable Resume Interrupt.
Bit 5 – WAKE_UP Wake Up CPU Interrupt Enable (cleared upon USB reset)
Value
Description
0
Disable Wake-up CPU Interrupt.
1
Enable Wake-up CPU Interrupt.
Bit 4 – ENDRESET End Of Reset Interrupt Enable (cleared upon USB reset)
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1126
SAM9X60
USB High Speed Device Port (UDPHS)
Value
0
1
Description
Disable End Of Reset Interrupt.
Enable End Of Reset Interrupt. Automatically enabled after USB reset.
Bit 3 – INT_SOF SOF Interrupt Enable (cleared upon USB reset)
Value
Description
0
Disable SOF Interrupt.
1
Enable SOF Interrupt.
Bit 2 – MICRO_SOF Micro-SOF Interrupt Enable (cleared upon USB reset)
Value
Description
0
Disable Micro-SOF Interrupt.
1
Enable Micro-SOF Interrupt.
Bit 1 – DET_SUSPD Suspend Interrupt Enable (cleared upon USB reset)
Value
Description
0
Disable Suspend Interrupt.
1
Enable Suspend Interrupt.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1127
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.4
UDPHS Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
UDPHS_INTSTA
0x14
0x00000000
Read-only
31
DMA_7
R
0
30
DMA_6
R
0
29
DMA_5
R
0
28
DMA_4
R
0
27
DMA_3
R
0
26
DMA_2
R
0
25
DMA_1
R
0
24
23
EPT_15
R
0
22
EPT_14
R
0
21
EPT_13
R
0
20
EPT_12
R
0
19
EPT_11
R
0
18
EPT_10
R
0
17
EPT_9
R
0
16
EPT_8
R
0
15
EPT_7
R
0
14
EPT_6
R
0
13
EPT_5
R
0
12
EPT_4
R
0
11
EPT_3
R
0
10
EPT_2
R
0
9
EPT_1
R
0
8
EPT_0
R
0
6
ENDOFRSM
R
0
5
WAKE_UP
R
0
4
ENDRESET
R
0
3
INT_SOF
R
0
2
MICRO_SOF
R
0
1
DET_SUSPD
R
0
0
SPEED
R
0
7
UPSTR_RES
Access
R
Reset
0
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_x DMA Channel x Interrupt
Value
Description
0
Reset when the UDPHS_DMASTATUSx interrupt source is cleared.
1
Set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is
enabled by the DMA_x bit in UDPHS_IEN.
Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – EPT_x Endpoint x Interrupt (cleared upon USB
reset)
Value
Description
0
Reset when the UDPHS_EPTSTAx interrupt source is cleared.
1
Set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint
interrupt is enabled by the EPT_x bit in UDPHS_IEN.
Bit 7 – UPSTR_RES Upstream Resume Interrupt
Value
Description
0
Cleared by setting the UPSTR_RES bit in UDPHS_CLRINT.
1
Set by hardware when the UDPHS controller is sending a resume signal called “upstream resume”.
This triggers a UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN.
Bit 6 – ENDOFRSM End Of Resume Interrupt
Value
Description
0
Cleared by setting the ENDOFRSM bit in UDPHS_CLRINT.
1
Set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host.
This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN.
Bit 5 – WAKE_UP Wake Up CPU Interrupt
Value
Description
0
Cleared by setting the WAKE_UP bit in UDPHS_CLRINT.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1128
SAM9X60
USB High Speed Device Port (UDPHS)
Value
1
Description
Set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered nonidle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when
the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable
the device controller clock prior to operation.
Note: this interrupt is generated even if the device controller clock is disabled.
Bit 4 – ENDRESET End Of Reset Interrupt
Value
Description
0
Cleared by setting the ENDRESET bit in UDPHS_CLRINT.
1
Set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a
UDPHS interrupt when the ENDRESET bit is set in UDPHS_IEN.
Bit 3 – INT_SOF Start Of Frame Interrupt
Note: The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not
generated at the same time.
Value
0
1
Description
Cleared by setting the INT_SOF bit in UDPHS_CLRINT.
Set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or
synthesized by the macro. This triggers a UDPHS interrupt when the INT_SOF bit is set in
UDPHS_IEN register. In case of detected SOF, in High Speed mode, the MICRO_FRAME_NUMBER
field is cleared in UDPHS_FNUM register and the FRAME_NUMBER field is updated.
Bit 2 – MICRO_SOF Micro Start Of Frame Interrupt
Note: The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not
generated at the same time.
Value
0
1
Description
Cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register.
Set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or
synthesized by the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in
UDPHS_IEN. In case of detected SOF, the MICRO_FRAME_NUM field in UDPHS_FNUM register is
incremented and the FRAME_NUMBER field does not change.
Bit 1 – DET_SUSPD Suspend Interrupt
Value
Description
0
Cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register.
1
Set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is
detected. This triggers a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register.
Bit 0 – SPEED Speed Status
Value
Description
0
Reset by hardware when the hardware is in Full Speed mode.
1
Set by hardware when the hardware is in High Speed mode.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1129
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.5
UDPHS Clear Interrupt Register
Name:
Offset:
Reset:
Property:
Bit
UDPHS_CLRINT
0x18
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
6
ENDOFRSM
W
–
5
WAKE_UP
W
–
4
ENDRESET
W
–
3
INT_SOF
W
–
2
MICRO_SOF
W
–
1
DET_SUSPD
W
–
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
UPSTR_RES
Access
W
Reset
–
Bit 7 – UPSTR_RES Upstream Resume Interrupt Clear
Value
Description
0
No effect.
1
Clear the UPSTR_RES bit in UDPHS_INTSTA.
Bit 6 – ENDOFRSM End Of Resume Interrupt Clear
Value
Description
0
No effect.
1
Clear the ENDOFRSM bit in UDPHS_INTSTA.
Bit 5 – WAKE_UP Wake Up CPU Interrupt Clear
Value
Description
0
No effect.
1
Clear the WAKE_UP bit in UDPHS_INTSTA.
Bit 4 – ENDRESET End Of Reset Interrupt Clear
Value
Description
0
No effect.
1
Clear the ENDRESET bit in UDPHS_INTSTA.
Bit 3 – INT_SOF Start Of Frame Interrupt Clear
Value
Description
0
No effect.
1
Clear the INT_SOF bit in UDPHS_INTSTA.
Bit 2 – MICRO_SOF Micro Start Of Frame Interrupt Clear
Value
Description
0
No effect.
1
Clear the MICRO_SOF bit in UDPHS_INTSTA.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1130
SAM9X60
USB High Speed Device Port (UDPHS)
Bit 1 – DET_SUSPD Suspend Interrupt Clear
Value
Description
0
No effect.
1
Clear the DET_SUSPD bit in UDPHS_INTSTA.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1131
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.6
UDPHS Endpoints Reset Register
Name:
Offset:
Reset:
Property:
Bit
UDPHS_EPTRST
0x1C
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
EPT_15
W
–
14
EPT_14
W
–
13
EPT_13
W
–
12
EPT_12
W
–
11
EPT_11
W
–
10
EPT_10
W
–
9
EPT_9
W
–
8
EPT_8
W
–
7
EPT_7
W
–
6
EPT_6
W
–
5
EPT_5
W
–
4
EPT_4
W
–
3
EPT_3
W
–
2
EPT_2
W
–
1
EPT_1
W
–
0
EPT_0
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EPT_x Endpoint x Reset
Setting this bit clears all bits in Endpoint Status register (UDPHS_EPTSTAx ), except the TOGGLESQ_STA field.
Value
Description
0
No effect.
1
Reset the Endpointx state.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1132
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.7
UDPHS Test Register
Name:
Offset:
Reset:
Property:
Bit
UDPHS_TST
0xE0
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
OPMODE2
R/W
0
4
TST_PKT
R/W
0
3
TST_K
R/W
0
2
TST_J
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
1
0
SPEED_CFG[1:0]
R/W
R/W
0
0
Bit 5 – OPMODE2 OpMode2
Note: For the Test mode, Test_SE0_NAK (refer to Universal Serial Bus Specification, Revision 2.0: 7.1.20, Test
Mode Support). Force the device in High Speed mode, and configure a bulk-type endpoint. Do not fill this endpoint for
sending NAK to the host.
Upon command, a port’s transceiver must enter the High Speed Receive mode and remain in that mode until the exit
action is taken. This enables the testing of output impedance, low level output voltage and loading characteristics. In
addition, while in this mode, upstream facing ports (and only upstream facing ports) must respond to any IN token
packet with a NAK handshake (only if the packet CRC is determined to be correct) within the normal allowed device
response time. This enables testing of the device squelch level circuitry and, additionally, provides a general purpose
stimulus/response test for basic functional testing.
Value
0
1
Description
No effect.
Set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI
encoding.
Bit 4 – TST_PKT Test Packet Mode
Value
Description
0
No effect.
1
Set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall
times, eye patterns, jitter, and any other dynamic waveform specifications.
Bit 3 – TST_K Test K Mode
Value
Description
0
No effect.
1
Set to send the K state on the UDPHS line. This enables the testing of the high output drive level on
the D- line.
Bit 2 – TST_J Test J Mode
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1133
SAM9X60
USB High Speed Device Port (UDPHS)
Value
0
1
Description
No effect.
Set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the
D+ line.
Bits 1:0 – SPEED_CFG[1:0] Speed Configuration
Value
Name
Description
0
NORMAL
Normal mode: The macro is in Full Speed mode, ready to make a High Speed
identification, if the host supports it and then to automatically switch to High Speed
mode.
1
–
Reserved
2
HIGH_SPEED Force High Speed: Set this value to force the hardware to work in High Speed mode.
Only for debug or test purpose.
3
FULL_SPEED Force Full Speed: Set this value to force the hardware to work only in Full Speed
mode. In this configuration, the macro will not respond to a High Speed reset
handshake.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1134
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.8
UDPHS Endpoint Configuration Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
UDPHS_EPTCFGx
0x0100 + x*0x20 [x=0..6]
0x00000000
Read/Write
31
EPT_MAPD
R/W
0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
3
EPT_DIR
R/W
0
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
BK_NUMBER[1:0]
R/W
R/W
0
0
5
4
EPT_TYPE[1:0]
R/W
R/W
0
0
R/W
0
9
8
NB_TRANS[1:0]
R/W
R/W
0
0
1
EPT_SIZE[2:0]
R/W
0
0
R/W
0
Bit 31 – EPT_MAPD Endpoint Mapped (cleared upon USB reset)
Value
Description
0
The user should reprogram the register with correct values.
1
Set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are
correct regarding:
– The max endpoint size for this endpoint
– The number of allowed banks for this endpoint
Bits 9:8 – NB_TRANS[1:0] Number Of Transactions per Microframe (cleared upon USB reset)
The number of transactions per microframe is set by software.
Note: Meaningful for high bandwidth isochronous endpoint only.
Bits 7:6 – BK_NUMBER[1:0] Number of Banks (cleared upon USB reset)
Set this field according to the endpoint’s number of banks (see section Endpoint Configuration).
Value
Name
Description
0
0
Zero bank, the endpoint is not mapped in memory
1
1
One bank (bank 0)
2
2
Double bank (Ping-Pong: bank0/bank1)
3
3
Triple bank (bank0/bank1/bank2)
Bits 5:4 – EPT_TYPE[1:0] Endpoint Type (cleared upon USB reset)
Set this field according to the endpoint type (see section Endpoint Configuration).
(Endpoint 0 should always be configured as control).
Value
Name
Description
0
CTRL8
Control endpoint
1
ISO
Isochronous endpoint
2
BULK
Bulk endpoint
3
INT
Interrupt endpoint
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1135
SAM9X60
USB High Speed Device Port (UDPHS)
Bit 3 – EPT_DIR Endpoint Direction (cleared upon USB reset)
For Control endpoints this bit has no effect and should be left at zero.
Value
Description
0
Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
1
Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Bits 2:0 – EPT_SIZE[2:0] Endpoint Size (cleared upon USB reset)
Set this field according to the endpoint size in bytes (see the section Endpoint Configuration). Note that 1024 bytes is
only for isochronous endpoints.
Value
Name
Description
0
8
8 bytes
1
16
16 bytes
2
32
32 bytes
3
64
64 bytes
4
128
128 bytes
5
256
256 bytes
6
512
512 bytes
7
1024
1024 bytes
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1136
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.9
UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
UDPHS_EPTCTLENBx
0x0104 + x*0x20 [x=0..6]
–
Write-only
This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in UDPHS Endpoint Configuration Register.
For additional information, see UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints).
Bit
31
SHRT_PCKT
Access
W
Reset
–
Bit
30
29
28
27
26
25
24
23
22
21
20
19
18
BUSY_BANK
W
–
17
16
15
NAK_OUT
W
–
14
NAK_IN
W
–
13
STALL_SNT
W
–
12
RX_SETUP
W
–
11
TXRDY
W
–
10
TX_COMPLT
W
–
7
6
5
4
NYET_DIS
W
–
3
INTDIS_DMA
W
–
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
9
8
RXRDY_TXKL ERR_OVFLW
W
W
–
–
1
AUTO_VALID
W
–
0
EPT_ENABL
W
–
Bit 31 – SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable
For IN endpoints: Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register
END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set.
For OUT endpoints:
Value
Description
0
No effect.
1
Enable Short Packet Interrupt.
Bit 18 – BUSY_BANK Busy Bank Interrupt Enable
Value
Description
0
No effect.
1
Enable Busy Bank Interrupt.
Bit 15 – NAK_OUT NAKOUT Interrupt Enable
Value
Description
0
No effect.
1
Enable NAKOUT Interrupt.
Bit 14 – NAK_IN NAKIN Interrupt Enable
Value
Description
0
No effect.
1
Enable NAKIN Interrupt.
Bit 13 – STALL_SNT Stall Sent Interrupt Enable
Value
Description
0
No effect.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1137
SAM9X60
USB High Speed Device Port (UDPHS)
Value
1
Description
Enable Stall Sent Interrupt.
Bit 12 – RX_SETUP Received SETUP
Value
Description
0
No effect.
1
Enable RX_SETUP Interrupt.
Bit 11 – TXRDY TX Packet Ready Interrupt Enable
Value
Description
0
No effect.
1
Enable TX Packet Ready/Transaction Error Interrupt.
Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Enable
Value
Description
0
No effect.
1
Enable Transmitted IN Data Complete Interrupt.
Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Enable
Value
Description
0
No effect.
1
Enable Received OUT Data Interrupt.
Bit 8 – ERR_OVFLW Overflow Error Interrupt Enable
Value
Description
0
No effect.
1
Enable Overflow Error Interrupt.
Bit 4 – NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints)
Value
Description
0
No effect.
1
Forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.
Bit 3 – INTDIS_DMA Interrupts Disable DMA
Value
Description
0
No effect.
1
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.
Bit 1 – AUTO_VALID Packet Auto-Valid Enable
Value
Description
0
No effect.
1
Enable this bit to automatically validate the current packet and switch to the next bank for both IN and
OUT transfers.
Bit 0 – EPT_ENABL Endpoint Enable
Value
Description
0
No effect.
1
Enable endpoint according to the device configuration.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1138
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints)
Name:
Offset:
Reset:
Property:
UDPHS_EPTCTLENBx
0x0104 + x*0x20 [x=0..6]
–
Write-only
This register view is relevant only if EPT_TYPE = 0x1 in UDPHS Endpoint Configuration Register.
For additional information, see UDPHS Endpoint Control Register (Isochronous Endpoint).
Bit
31
SHRT_PCKT
Access
W
Reset
–
Bit
23
30
29
28
27
26
25
24
22
21
20
19
18
BUSY_BANK
W
–
17
16
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
MDATA_RX
W
–
14
13
12
11
ERR_FLUSH ERR_CRC_NT ERR_FL_ISO TXRDY_TRER
R
W
W
W
W
–
–
–
–
6
DATAX_RX
W
–
5
4
3
INTDIS_DMA
W
–
10
TX_COMPLT
9
8
RXRDY_TXKL ERR_OVFLW
W
–
W
–
W
–
2
1
AUTO_VALID
W
–
0
EPT_ENABL
W
–
Bit 31 – SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable
For IN endpoints: Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register
END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set.
For OUT endpoints:
Value
Description
0
No effect.
1
Enable Short Packet Interrupt.
Bit 18 – BUSY_BANK Busy Bank Interrupt Enable
Value
Description
0
No effect.
1
Enable Busy Bank Interrupt.
Bit 14 – ERR_FLUSH Bank Flush Error Interrupt Enable
Value
Description
0
No effect.
1
Enable Bank Flush Error Interrupt.
Bit 13 – ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable
Value
Description
0
No effect.
1
Enable Error CRC ISO/Error Number of Transaction Interrupt.
Bit 12 – ERR_FL_ISO Error Flow Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1139
SAM9X60
USB High Speed Device Port (UDPHS)
Value
0
1
Description
No effect.
Enable Error Flow ISO Interrupt.
Bit 11 – TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable
Value
Description
0
No effect.
1
Enable TX Packet Ready/Transaction Error Interrupt.
Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Enable
Value
Description
0
No effect.
1
Enable Transmitted IN Data Complete Interrupt.
Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Enable
Value
Description
0
No effect.
1
Enable Received OUT Data Interrupt.
Bit 8 – ERR_OVFLW Overflow Error Interrupt Enable
Value
Description
0
No effect.
1
Enable Overflow Error Interrupt.
Bit 7 – MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value
Description
0
No effect.
1
Enable MDATA Interrupt.
Bit 6 – DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
Value
Description
0
No effect.
1
Enable DATAx Interrupt.
Bit 3 – INTDIS_DMA Interrupts Disable DMA
Value
Description
0
No effect.
1
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.
Bit 1 – AUTO_VALID Packet Auto-Valid Enable
Value
Description
0
No effect.
1
Enable this bit to automatically validate the current packet and switch to the next bank for both IN and
OUT transfers.
Bit 0 – EPT_ENABL Endpoint Enable
Value
Description
0
No effect.
1
Enable endpoint according to the device configuration.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1140
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
UDPHS_EPTCTLDISx
0x0108 + x*0x20 [x=0..6]
–
Write-only
This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in UDPHS Endpoint Configuration Register.
For additional information, see UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints).
Bit
31
SHRT_PCKT
Access
W
Reset
–
Bit
30
29
28
27
26
25
24
23
22
21
20
19
18
BUSY_BANK
W
–
17
16
15
NAK_OUT
W
–
14
NAK_IN
W
–
13
STALL_SNT
W
–
12
RX_SETUP
W
–
11
TXRDY
W
–
10
TX_COMPLT
W
–
7
6
5
4
NYET_DIS
W
–
3
INTDIS_DMA
W
–
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
9
8
RXRDY_TXKL ERR_OVFLW
W
W
–
–
1
AUTO_VALID
W
–
0
EPT_DISABL
W
–
Bit 31 – SHRT_PCKT Short Packet Interrupt Disable
For IN endpoints: Never automatically add a zero length packet at end of DMA transfer.
For OUT endpoints:
Value
Description
0
No effect.
1
Disable Short Packet Interrupt.
Bit 18 – BUSY_BANK Busy Bank Interrupt Disable
Value
Description
0
No effect.
1
Disable Busy Bank Interrupt.
Bit 15 – NAK_OUT NAKOUT Interrupt Disable
Value
Description
0
No effect.
1
Disable NAKOUT Interrupt.
Bit 14 – NAK_IN NAKIN Interrupt Disable
Value
Description
0
No effect.
1
Disable NAKIN Interrupt.
Bit 13 – STALL_SNT Stall Sent Interrupt Disable
Value
Description
0
No effect.
1
Disable Stall Sent Interrupt.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1141
SAM9X60
USB High Speed Device Port (UDPHS)
Bit 12 – RX_SETUP Received SETUP Interrupt Disable
Value
Description
0
No effect.
1
Disable RX_SETUP Interrupt.
Bit 11 – TXRDY TX Packet Ready Interrupt Disable
Value
Description
0
No effect.
1
Disable TX Packet Ready/Transaction Error Interrupt.
Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Disable
Value
Description
0
No effect.
1
Disable Transmitted IN Data Complete Interrupt.
Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Disable
Value
Description
0
No effect.
1
Disable Received OUT Data Interrupt.
Bit 8 – ERR_OVFLW Overflow Error Interrupt Disable
Value
Description
0
No effect.
1
Disable Overflow Error Interrupt.
Bit 4 – NYET_DIS NYET Enable (Only for High Speed Bulk OUT endpoints)
Value
Description
0
No effect.
1
Let the hardware handle the handshake response for the High Speed Bulk OUT transfer.
Bit 3 – INTDIS_DMA Interrupts Disable DMA
Value
Description
0
No effect.
1
Disable the “Interrupts Disable DMA”.
Bit 1 – AUTO_VALID Packet Auto-Valid Disable
Value
Description
0
No effect.
1
Disable this bit to not automatically validate the current packet.
Bit 0 – EPT_DISABL Endpoint Disable
Value
Description
0
No effect.
1
Disable endpoint.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1142
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint)
Name:
Offset:
Reset:
Property:
UDPHS_EPTCTLDISx
0x0108 + x*0x20 [x=0..6]
–
Write-only
This register view is relevant only if EPT_TYPE = 0x1 in UDPHS Endpoint Configuration Register.
For additional information, see “UDPHS Endpoint Control Register (Isochronous Endpoint)”.
Bit
31
SHRT_PCKT
Access
W
Reset
–
Bit
23
30
29
28
27
26
25
24
22
21
20
19
18
BUSY_BANK
W
–
17
16
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
MDATA_RX
W
–
14
13
12
11
ERR_FLUSH ERR_CRC_NT ERR_FL_ISO TXRDY_TRER
R
W
W
W
W
–
–
–
–
6
DATAX_RX
W
–
5
4
3
INTDIS_DMA
W
–
10
TX_COMPLT
9
8
RXRDY_TXKL ERR_OVFLW
W
–
W
–
W
–
2
1
AUTO_VALID
W
–
0
EPT_DISABL
W
–
Bit 31 – SHRT_PCKT Short Packet Interrupt Disable
For IN endpoints: Never automatically add a zero length packet at end of DMA transfer.
For OUT endpoints:
Value
Description
0
No effect.
1
Disable Short Packet Interrupt.
Bit 18 – BUSY_BANK Busy Bank Interrupt Disable
Value
Description
0
No effect.
1
Disable Busy Bank Interrupt.
Bit 14 – ERR_FLUSH bank flush error Interrupt Disable
Value
Description
0
No effect.
1
Disable Bank Flush Error Interrupt.
Bit 13 – ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable
Value
Description
0
No effect.
1
Disable Error CRC ISO/Error Number of Transaction Interrupt.
Bit 12 – ERR_FL_ISO Error Flow Interrupt Disable
Value
Description
0
No effect.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1143
SAM9X60
USB High Speed Device Port (UDPHS)
Value
1
Description
Disable Error Flow ISO Interrupt.
Bit 11 – TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable
Value
Description
0
No effect.
1
Disable TX Packet Ready/Transaction Error Interrupt.
Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Disable
Value
Description
0
No effect.
1
Disable Transmitted IN Data Complete Interrupt.
Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Disable
Value
Description
0
No effect.
1
Disable Received OUT Data Interrupt.
Bit 8 – ERR_OVFLW Overflow Error Interrupt Disable
Value
Description
0
No effect.
1
Disable Overflow Error Interrupt.
Bit 7 – MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value
Description
0
No effect.
1
Disable MDATA Interrupt.
Bit 6 – DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)
Value
Description
0
No effect.
1
Disable DATAx Interrupt.
Bit 3 – INTDIS_DMA Interrupts Disable DMA
Value
Description
0
No effect.
1
Disable the “Interrupts Disable DMA”.
Bit 1 – AUTO_VALID Packet Auto-Valid Disable
Value
Description
0
No effect.
1
Disable this bit to not automatically validate the current packet.
Bit 0 – EPT_DISABL Endpoint Disable
Value
Description
0
No effect.
1
Disable endpoint.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1144
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
UDPHS_EPTCTLx
0x010C + x*0x20 [x=0..6]
0x00000000
Read-only
This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in UDPHS Endpoint Configuration Register.
The reset value for UDPHS_EPTCTL0 is 0x00000001.
Bit
31
SHRT_PCKT
Access
R
Reset
0
Bit
30
29
28
27
26
25
24
23
22
21
20
19
18
BUSY_BANK
R
0
17
16
15
NAK_OUT
R
0
14
NAK_IN
R
0
13
STALL_SNT
R
0
12
RX_SETUP
R
0
11
TXRDY
R
0
10
TX_COMPLT
R
0
7
6
5
4
NYET_DIS
R
0
3
INTDIS_DMA
R
0
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
9
8
RXRDY_TXKL ERR_OVFLW
R
R
0
0
1
AUTO_VALID
R
0
0
EPT_ENABL
R
0
Bit 31 – SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset)
For OUT endpoints: sends an Interrupt when a Short Packet has been received.
For IN endpoints: a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling a BULK or
INTERRUPT end of transfer, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx
register AUTO_VALID bits are also set.
Value
Description
0
Short Packet Interrupt is masked.
1
Short Packet Interrupt is enabled.
Bit 18 – BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset)
For OUT endpoints: an interrupt is sent when all banks are busy.
For IN endpoints: an interrupt is sent when all banks are free.
Value
Description
0
BUSY_BANK Interrupt is masked.
1
BUSY_BANK Interrupt is enabled.
Bit 15 – NAK_OUT NAKOUT Interrupt Enabled (cleared upon USB reset)
Value
Description
0
NAKOUT Interrupt is masked.
1
NAKOUT Interrupt is enabled.
Bit 14 – NAK_IN NAKIN Interrupt Enabled (cleared upon USB reset)
Value
Description
0
NAKIN Interrupt is masked.
1
NAKIN Interrupt is enabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1145
SAM9X60
USB High Speed Device Port (UDPHS)
Bit 13 – STALL_SNT Stall Sent Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Stall Sent Interrupt is masked.
1
Stall Sent Interrupt is enabled.
Bit 12 – RX_SETUP Received SETUP Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Received SETUP is masked.
1
Received SETUP is enabled.
Bit 11 – TXRDY TX Packet Ready Interrupt Enabled (cleared upon USB reset)
CAUTION
Value
0
1
Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY flag remains
low. If there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/
TXRDY for the last transmit packet, then the interrupt source remains inactive until the first bank becomes
free again to transmit at UDPHS_EPTSTAx/TXRDY hardware clear.
Description
TX Packet Ready Interrupt is masked.
TX Packet Ready Interrupt is enabled.
Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Transmitted IN Data Complete Interrupt is masked.
1
Transmitted IN Data Complete Interrupt is enabled.
Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Received OUT Data Interrupt is masked.
1
Received OUT Data Interrupt is enabled.
Bit 8 – ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Overflow Error Interrupt is masked.
1
Overflow Error Interrupt is enabled.
Bit 4 – NYET_DIS NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset)
Note: According to the Universal Serial Bus Specification, Rev 2.0 (8.5.1.1 NAK Responses to OUT/DATA During
PING Protocol), a NAK response to an HS Bulk OUT transfer is expected to be an unusual occurrence.
Value
0
1
Description
Lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.
Forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.
Bit 3 – INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset)
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the
UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source
or clear this bit if transfer completion is needed.
If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is
normally completed, but the new DMA packet transfer is not started (not requested).
If the exception raised is not associated to a new system bank packet (NAK_IN, NAK_OUT, etc.), then the request
cancellation may happen at any time and may immediately stop the current DMA transfer.
This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to
complete a DMA buffer by software after reception of a short packet.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1146
SAM9X60
USB High Speed Device Port (UDPHS)
Bit 1 – AUTO_VALID Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset)
Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints.
For IN Transfer:
If this bit is set, the UDPHS_EPTSTAx register TXRDY bit is set automatically when the current bank is full and at the
end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set.
The user may still set the UDPHS_EPTSTAx register TXRDY bit if the current bank is not full, unless the user needs
to send a Zero Length Packet by software.
For OUT Transfer:
If this bit is set, the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when the
last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx
register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is
reached.
The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA
buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of
the remaining data bank(s).
Bit 0 – EPT_ENABL Endpoint Enable (cleared upon USB reset)
Value
Description
0
The endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled
after a hardware or UDPHS bus reset and participate in the device configuration.
1
The endpoint is enabled according to the device configuration.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1147
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint)
Name:
Offset:
Reset:
Property:
UDPHS_EPTCTLx
0x010C + x*0x20 [x=0..6]
0x00000000
Read-only
This register view is relevant only if EPT_TYPE = 0x1 in UDPHS Endpoint Configuration Register.
The reset value for UDPHS_EPTCTL0 is 0x00000001.
Bit
31
SHRT_PCKT
Access
R
Reset
0
Bit
23
30
29
28
27
26
25
24
22
21
20
19
18
BUSY_BANK
R
0
17
16
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
MDATA_RX
R
0
14
13
12
11
ERR_FLUSH ERR_CRC_NT ERR_FL_ISO TXRDY_TRER
R
R
R
R
R
0
0
0
0
6
DATAX_RX
R
0
5
4
10
TX_COMPLT
3
INTDIS_DMA
R
0
9
8
RXRDY_TXKL ERR_OVFLW
R
0
R
0
R
0
2
1
AUTO_VALID
R
0
0
EPT_ENABL
R
0
Bit 31 – SHRT_PCKT Short Packet Interrupt Enabled (cleared upon USB reset)
For OUT endpoints: Send an Interrupt when a Short Packet has been received.
For IN endpoints: A Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling an end of
isochronous (micro-)frame data, but only if the UDPHS_DMACONTROLx register END_B_EN and
UDPHS_EPTCTLx register AUTO_VALID bits are also set.
Value
Description
0
Short Packet Interrupt is masked.
1
Short Packet Interrupt is enabled.
Bit 18 – BUSY_BANK Busy Bank Interrupt Enabled (cleared upon USB reset)
For OUT endpoints: An interrupt is sent when all banks are busy.
For IN endpoints: An interrupt is sent when all banks are free.
Value
Description
0
BUSY_BANK Interrupt is masked.
1
BUSY_BANK Interrupt is enabled.
Bit 14 – ERR_FLUSH Bank Flush Error Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Bank Flush Error Interrupt is masked.
1
Bank Flush Error Interrupt is enabled.
Bit 13 – ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset)
Value
Description
0
ISO CRC error/number of Transaction Error Interrupt is masked.
1
ISO CRC error/number of Transaction Error Interrupt is enabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1148
SAM9X60
USB High Speed Device Port (UDPHS)
Bit 12 – ERR_FL_ISO Error Flow Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Error Flow Interrupt is masked.
1
Error Flow Interrupt is enabled.
Bit 11 – TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset)
CAUTION
Value
0
1
Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY_TRER flag
remains low. If there are no more banks available for transmitting after the software has set
UDPHS_EPTSTAx/TXRDY_TRER for the last transmit packet, then the interrupt source remains inactive
until the first bank becomes free again to transmit at UDPHS_EPTSTAx/TXRDY_TRER hardware clear.
Description
TX Packet Ready/Transaction Error Interrupt is masked.
TX Packet Ready/Transaction Error Interrupt is enabled.
Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Transmitted IN Data Complete Interrupt is masked.
1
Transmitted IN Data Complete Interrupt is enabled.
Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Received OUT Data Interrupt is masked.
1
Received OUT Data Interrupt is enabled.
Bit 8 – ERR_OVFLW Overflow Error Interrupt Enabled (cleared upon USB reset)
Value
Description
0
Overflow Error Interrupt is masked.
1
Overflow Error Interrupt is enabled.
Bit 7 – MDATA_RX MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon
USB reset)
Value
Description
0
No effect.
1
Send an interrupt when an MDATA packet has been received and so at least one packet of the
microframe data payload has been received.
Bit 6 – DATAX_RX DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon
USB reset)
Value
Description
0
No effect.
1
Send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole
microframe data payload has been received.
Bit 3 – INTDIS_DMA Interrupt Disables DMA (cleared upon USB reset)
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the
UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source
or clear this bit if transfer completion is needed.
If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is
normally completed, but the new DMA packet transfer is not started (not requested).
If the exception raised is not associated to a new system bank packet (ex: ERR_FL_ISO), then the request
cancellation may happen at any time and may immediately stop the current DMA transfer.
This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to
complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO
interrupt for adaptive rate.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1149
SAM9X60
USB High Speed Device Port (UDPHS)
Bit 1 – AUTO_VALID Packet Auto-Valid Enabled (cleared upon USB reset)
Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints.
For IN Transfer:
If this bit is set, the UDPHS_EPTSTAx register TXRDY_TRER bit is set automatically when the current bank is full
and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set.
The user may still set the UDPHS_EPTSTAx register TXRDY_TRER bit if the current bank is not full, unless the user
needs to send a Zero Length Packet by software.
For OUT Transfer:
If this bit is set, the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when the
last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx
register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is
reached.
The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA
buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of
the remaining data bank(s).
Bit 0 – EPT_ENABL Endpoint Enable (cleared upon USB reset)
Value
Description
0
The endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled
after a hardware or UDPHS bus reset and participate in the device configuration.
1
The endpoint is enabled according to the device configuration.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1150
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
UDPHS_EPTSETSTAx
0x0114 + x*0x20 [x=0..6]
–
Write-only
This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in UDPHS Endpoint Configuration Register.
For additional information, see UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
TXRDY
W
–
10
9
RXRDY_TXKL
W
–
8
7
6
5
FRCESTALL
W
–
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – TXRDY TX Packet Ready Set
Value
Description
0
No effect.
1
Set this bit after a packet has been written into the endpoint FIFO for IN data transfers
– This flag is used to generate a Data IN transaction (device to host).
– Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY is cleared.
– Transfer to the FIFO is done by writing in the “Buffer Address” register.
– Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device
setting TXRDY to one.
– UDPHS bus transactions can start.
– TXCOMP is set once the data payload has been received by the host.
– Data should be written into the endpoint FIFO only after this bit has been cleared.
– Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.
Bit 9 – RXRDY_TXKL KILL Bank Set (for IN Endpoint)
Value
Description
0
No effect.
1
Kill the last written bank.
Bit 5 – FRCESTALL Stall Handshake Request Set
Refer to chapters 8.4.5 (Handshake Packets) and 9.4.5 (Get Status) of the Universal Serial Bus Specification, Rev
2.0 for more information on the STALL handshake.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1151
SAM9X60
USB High Speed Device Port (UDPHS)
Value
0
1
Description
No effect.
Set this bit to request a STALL answer to the host for the next handshake
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1152
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint)
Name:
Offset:
Reset:
Property:
UDPHS_EPTSETSTAx
0x0114 + x*0x20 [x=0..6]
–
Write-only
This register view is relevant only if EPT_TYPE = 0x1 in UDPHS Endpoint Configuration Register.
For additional information, see UDPHS Endpoint Status Register (Isochronous Endpoint).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
TXRDY_TRER
W
–
10
9
RXRDY_TXKL
W
–
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – TXRDY_TRER TX Packet Ready Set
Value
Description
0
No effect.
1
Set this bit after a packet has been written into the endpoint FIFO for IN data transfers
– This flag is used to generate a Data IN transaction (device to host).
– Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY_TRER is
cleared.
– Transfer to the FIFO is done by writing in the “Buffer Address” register.
– Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device
setting TXRDY_TRER to one.
– UDPHS bus transactions can start.
– TXCOMP is set once the data payload has been sent.
– Data should be written into the endpoint FIFO only after this bit has been cleared.
– Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.
Bit 9 – RXRDY_TXKL KILL Bank Set (for IN Endpoint)
Value
Description
0
No effect.
1
Kill the last written bank.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1153
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
UDPHS_EPTCLRSTAx
0x0118 + x*0x20 [x=0..6]
–
Write-only
This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in UDPHS Endpoint Configuration Register.
For additional information, see UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NAK_OUT
W
–
14
NAK_IN
W
–
13
STALL_SNT
W
–
12
RX_SETUP
W
–
11
10
TX_COMPLT
W
–
9
RXRDY_TXKL
W
–
8
7
6
TOGGLESQ
W
–
5
FRCESTALL
W
–
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 15 – NAK_OUT NAKOUT Clear
Value
Description
0
No effect.
1
Clear the NAK_OUT flag of UDPHS_EPTSTAx.
Bit 14 – NAK_IN NAKIN Clear
Value
Description
0
No effect.
1
Clear the NAK_IN flags of UDPHS_EPTSTAx.
Bit 13 – STALL_SNT Stall Sent Clear
Value
Description
0
No effect.
1
Clear the STALL_SNT flags of UDPHS_EPTSTAx.
Bit 12 – RX_SETUP Received SETUP Clear
Value
Description
0
No effect.
1
Clear the RX_SETUP flags of UDPHS_EPTSTAx.
Bit 10 – TX_COMPLT Transmitted IN Data Complete Clear
Value
Description
0
No effect.
1
Clear the TX_COMPLT flag of UDPHS_EPTSTAx.
Bit 9 – RXRDY_TXKL Received OUT Data Clear
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1154
SAM9X60
USB High Speed Device Port (UDPHS)
Value
0
1
Description
No effect.
Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx.
Bit 6 – TOGGLESQ Data Toggle Clear
For OUT endpoints, the next received packet should be a DATA0.
For IN endpoints, the next packet will be sent with a DATA0 PID.
Value
Description
0
No effect.
1
Clear the PID data of the current bank
Bit 5 – FRCESTALL Stall Handshake Request Clear
Value
Description
0
No effect.
1
Clear the STALL request. The next packets from host will not be STALLed.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1155
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint)
Name:
Offset:
Reset:
Property:
UDPHS_EPTCLRSTAx
0x0118 + x*0x20 [x=0..6]
–
Write-only
This register view is relevant only if EPT_TYPE = 0x1 in UDPHS Endpoint Configuration Register.
For additional information, see UDPHS Endpoint Status Register (Isochronous Endpoint).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
13
12
ERR_FLUSH ERR_CRC_NT ERR_FL_ISO
R
W
W
W
–
–
–
11
10
TX_COMPLT
9
RXRDY_TXKL
8
W
–
W
–
6
TOGGLESQ
W
–
3
2
1
Access
Reset
Bit
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
5
4
0
Bit 14 – ERR_FLUSH Bank Flush Error Clear
Value
Description
0
No effect.
1
Clear the ERR_FLUSH flags of UDPHS_EPTSTAx.
Bit 13 – ERR_CRC_NTR Number of Transaction Error Clear
Value
Description
0
No effect.
1
Clear the ERR_CRC_NTR flags of UDPHS_EPTSTAx.
Bit 12 – ERR_FL_ISO Error Flow Clear
Value
Description
0
No effect.
1
Clear the ERR_FL_ISO flags of UDPHS_EPTSTAx.
Bit 10 – TX_COMPLT Transmitted IN Data Complete Clear
Value
Description
0
No effect.
1
Clear the TX_COMPLT flag of UDPHS_EPTSTAx.
Bit 9 – RXRDY_TXKL Received OUT Data Clear
Value
Description
0
No effect.
1
Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1156
SAM9X60
USB High Speed Device Port (UDPHS)
Bit 6 – TOGGLESQ Data Toggle Clear
For OUT endpoints, the next received packet should be a DATA0.
For IN endpoints, the next packet will be sent with a DATA0 PID.
Value
Description
0
No effect.
1
Clear the PID data of the current bank
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1157
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
UDPHS_EPTSTAx
0x011C + x*0x20 [x=0..6]
0x00000040
Read-only
This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in UDPHS Endpoint Configuration Register.
Bit
31
SHRT_PCKT
Access
R
Reset
0
Bit
23
Access
Reset
R
0
Bit
Access
Reset
Bit
Access
Reset
15
NAK_OUT
R
0
30
29
28
R
0
R
0
R
0
22
21
BYTE_COUNT[3:0]
R
R
0
0
14
NAK_IN
R
0
7
6
TOGGLESQ_STA[1:0]
R
R
0
1
20
R
0
27
BYTE_COUNT[10:4]
R
0
26
25
24
R
0
R
0
R
0
19
18
BUSY_BANK_STA[1:0]
R
R
0
0
13
STALL_SNT
R
0
12
RX_SETUP
R
0
11
TXRDY
R
0
10
TX_COMPLT
R
0
5
FRCESTALL
R
0
4
3
2
17
16
CURBK_CTLDIR[1:0]
R
R
0
0
9
8
RXRDY_TXKL ERR_OVFLW
R
R
0
0
1
0
Bit 31 – SHRT_PCKT Short Packet (cleared upon USB reset)
An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register
EPT_Size.
This bit is updated at the same time as the BYTE_COUNT field.
It is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
Bits 30:20 – BYTE_COUNT[10:0] UDPHS Byte Count (cleared upon USB reset)
Byte count of a received data packet.
This field is incremented after each write into the endpoint (to prepare an IN transfer). It is decremented after each
reading into the endpoint (OUT transfer).
This field is also updated at RXRDY_TXKL flag clear with the next bank, and at TXRDY flag set with the next bank.
This field is reset by UDPHS_EPTRST.EPT_x.
Bits 19:18 – BUSY_BANK_STA[1:0] Busy Bank Number (cleared upon USB reset)
These bits are set by hardware to indicate the number of busy banks.
IN endpoint: Indicates the number of busy banks filled by the user, ready for IN transfer.
OUT endpoint: Indicates the number of busy banks filled by OUT transaction from the Host.
Value
Name
Description
0
0BUSYBANK
All banks are free
1
1BUSYBANK
1 busy bank
2
2BUSYBANKS
2 busy banks
3
3BUSYBANKS
3 busy banks
Bits 17:16 – CURBK_CTLDIR[1:0] Current Bank/Control Direction (cleared upon USB reset)
Control Direction (for Control endpoint only):
0: A Control Write is requested by the Host.
1: A Control Read is requested by the Host.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1158
SAM9X60
USB High Speed Device Port (UDPHS)
Notes:
1. Corresponds to the the 7th bit of the bmRequestType (Byte 0 of the Setup Data).
2. Updated after receiving new setup data.
Current Bank (not relevant for Control endpoint):
• Set by hardware to indicate the number of the current bank.
• Reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
• The current bank is updated each time the user:
– Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.
– Clears the received OUT data bit to access the next bank.
Value
0
1
2
Name
BANK0
BANK1
BANK2
Description
Bank 0 (or single bank)
Bank 1
Bank 2
Bit 15 – NAK_OUT NAK OUT (cleared upon USB reset)
This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the
Host.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
Bit 14 – NAK_IN NAK IN (cleared upon USB reset)
This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host.
This bit is cleared by software.
Bit 13 – STALL_SNT Stall Sent (cleared upon USB reset)
For Control, Bulk and Interrupt endpoints.
This bit is set by hardware after a STALL handshake has been sent as requested by the UDPHS_EPTSTAx register
FRCESTALL bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable
endpoint).
Bit 12 – RX_SETUP Received SETUP (cleared upon USB reset)
For Control endpoint only.
This bit is set by hardware when a valid SETUP packet has been received from the host.
It is cleared by the device firmware after reading the SETUP data from the endpoint FIFO.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable
endpoint).
Bit 11 – TXRDY TX Packet Ready (cleared upon USB reset)
This bit is cleared by hardware after the host has acknowledged the packet.
For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit.
Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable
endpoint).
Bit 10 – TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset)
This bit is set by hardware after an IN packet has been accepted (ACK’ed) by the host.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable
endpoint).
Bit 9 – RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset)
Received OUT Data (for OUT endpoint or Control endpoint):
• This bit is set by hardware after a new packet has been stored in the endpoint FIFO.
• This bit is cleared by the device firmware after reading the OUT data from the endpoint.
• For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other
packet has been received meanwhile.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1159
SAM9X60
USB High Speed Device Port (UDPHS)
•
•
Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register
RXRDY_TXKL bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable
endpoint).
KILL Bank (for IN endpoint):
• The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented.
• The bank is not cleared but sent on the IN transfer, TX_COMPLT
• The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear
another packet.
Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent
on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are
ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the
current bank is sent (IN transfer) and the last bank is killed.
Bit 8 – ERR_OVFLW Overflow Error (cleared upon USB reset)
This bit is set by hardware when a new too-long packet is received.
Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the
Overflow Error bit is set.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable
endpoint).
Bits 7:6 – TOGGLESQ_STA[1:0] Toggle Sequencing (cleared upon USB reset)
In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).
This field is updated for OUT transfer:
• A new data has been written into the current bank.
• The user has just cleared the Received OUT Data bit to switch to the next bank.
This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx
(disable endpoint).
Toggle Sequencing:
• IN endpoint: Indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the
current bank.
• CONTROL and OUT endpoints: Set by hardware to indicate the PID data of the current bank.
Value
0
1
2
3
Name
DATA0
DATA1
DATA2
MDATA
Description
DATA0
DATA1
Reserved for High Bandwidth Isochronous Endpoint
Reserved for High Bandwidth Isochronous Endpoint
Bit 5 – FRCESTALL Stall Handshake Request (cleared upon USB reset)
This bit is reset by hardware upon received SETUP.
Value
Description
0
No effect.
1
If set a STALL answer will be done to the host for the next handshake.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1160
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint)
Name:
Offset:
Reset:
Property:
UDPHS_EPTSTAx
0x011C + x*0x20 [x=0..6]
0x00000040
Read-only
This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register”.
Bit
31
SHRT_PCKT
Access
R
Reset
0
Bit
23
Access
Reset
R
0
Bit
15
Access
Reset
Bit
Access
Reset
30
29
28
R
0
R
0
R
0
22
21
BYTE_COUNT[3:0]
R
R
0
0
20
R
0
27
BYTE_COUNT[10:4]
R
0
5
4
25
24
R
0
R
0
R
0
19
18
BUSY_BANK_STA[1:0]
R
R
0
0
14
13
12
11
ERR_FLUSH ERR_CRC_NT ERR_FL_ISO TXRDY_TRER
R
R
R
R
R
0
0
0
0
7
6
TOGGLESQ_STA[1:0]
R
R
0
1
26
3
10
TX_COMPLT
17
16
CURBK[1:0]
R
0
R
0
9
8
RXRDY_TXKL ERR_OVFLW
R
0
R
0
R
0
2
1
0
Bit 31 – SHRT_PCKT Short Packet (cleared upon USB reset)
An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register
EPT_Size.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable
endpoint).
Bits 30:20 – BYTE_COUNT[10:0] UDPHS Byte Count (cleared upon USB reset)
Byte count of a received data packet.
This field is incremented after each write into the endpoint (to prepare an IN transfer).
This field is decremented after each reading into the endpoint (OUT transfer).
This field is also updated at RXRDY_TXKL flag clear with the next bank.
This field is also updated at TXRDY_TRER flag set with the next bank.
This field is reset by EPT_x of UDPHS_EPTRST register.
Bits 19:18 – BUSY_BANK_STA[1:0] Busy Bank Number (cleared upon USB reset)
These bits are set by hardware to indicate the number of busy banks.
IN endpoint: It indicates the number of busy banks filled by the user, ready for IN transfer.
OUT endpoint: It indicates the number of busy banks filled by OUT transaction from the Host.
Value
Name
Description
0
0BUSYBANK
All banks are free
1
1BUSYBANK
1 busy bank
2
2BUSYBANKS
2 busy banks
3
3BUSYBANKS
3 busy banks
Bits 17:16 – CURBK[1:0] Current Bank (cleared upon USB reset)
These bits are set by hardware to indicate the number of the current bank.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1161
SAM9X60
USB High Speed Device Port (UDPHS)
The current bank is updated each time the user:
• Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.
• Clears the received OUT data bit to access the next bank.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable
endpoint).
Value
Name
Description
0
BANK0
Bank 0 (or single bank)
1
BANK1
Bank 1
2
BANK2
Bank 2
Bit 14 – ERR_FLUSH Bank Flush Error (cleared upon USB reset)
For High Bandwidth Isochronous IN endpoints.
This bit is set when flushing unsent banks at the end of a microframe.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
Bit 13 – ERR_CRC_NTR CRC ISO Error/Number of Transaction Error (cleared upon USB reset)
CRC ISO Error (for Isochronous OUT endpoints) (Read-only):
This bit is set by hardware if the last received data is corrupted (CRC error on data).
This bit is updated by hardware when new data is received (Received OUT Data bit).
Number of Transaction Error (for High Bandwidth Isochronous IN endpoints):
This bit is set at the end of a microframe in which at least one data bank has been transmitted, if less than the
number of transactions per micro-frame banks (UDPHS_EPTCFGx register NB_TRANS) have been validated for
transmission inside this microframe.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable
endpoint).
Bit 12 – ERR_FL_ISO Error Flow (cleared upon USB reset)
This bit is set by hardware when a transaction error occurs.
• Isochronous IN transaction is missed, the micro has no time to fill the endpoint (underflow).
• Isochronous OUT data is dropped because the bank is busy (overflow).
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable
endpoint).
Bit 11 – TXRDY_TRER TX Packet Ready/Transaction Error (cleared upon USB reset)
TX Packet Ready
This bit is cleared by hardware, as soon as the packet has been sent.
For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit.
Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY_TRER bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable
endpoint).
Transaction Error (for high bandwidth isochronous OUT endpoints) (Read-Only):
This bit is set by hardware when a transaction error occurs inside one microframe.
If one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe, then this bit is
still set as long as the current bank contains one “bad” n-transaction (see CURBK field description). As soon as the
current bank is relative to a new “good” n-transactions, then this bit is reset.
Notes:
1. A transaction error occurs when the toggle sequencing does not comply with the Universal Serial Bus
Specification, Rev 2.0 (5.9.2 High Bandwidth Isochronous endpoints) (Bad PID, missing data, etc.)
2. When a transaction error occurs, the user may empty all the “bad” transactions by clearing the Received OUT
Data flag (RXRDY_TXKL).
If this bit is reset, then the user should consider that a new n-transaction is coming.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable
endpoint).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1162
SAM9X60
USB High Speed Device Port (UDPHS)
Bit 10 – TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset)
This bit is set by hardware after an IN packet has been sent.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable
endpoint).
Bit 9 – RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset)
Received OUT Data (for OUT endpoint or Control endpoint):
• This bit is set by hardware after a new packet has been stored in the endpoint FIFO.
• This bit is cleared by the device firmware after reading the OUT data from the endpoint.
• For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other
packet has been received meanwhile.
• Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register
RXRDY_TXKL bit.
• This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable
endpoint).
KILL Bank (for IN endpoint):
• The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented.
• The bank is not cleared but sent on the IN transfer, TX_COMPLT
• The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear
another packet.
Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent
on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are
ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the
current bank is sent (IN transfer) and the last bank is killed.
Bit 8 – ERR_OVFLW Overflow Error (cleared upon USB reset)
This bit is set by hardware when a new too-long packet is received.
Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the
Overflow Error bit is set.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable
endpoint).
Bits 7:6 – TOGGLESQ_STA[1:0] Toggle Sequencing (cleared upon USB reset)
In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).
This field is updated for OUT transfer:
• A new data has been written into the current bank.
• The user has just cleared the Received OUT Data bit to switch to the next bank.
For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/TXRDY_TRER bit
to know if the toggle sequencing is correct or not.
This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx
(disable endpoint).
Toggle Sequencing:
• IN endpoint: Indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the
current bank.
• OUT endpoint: Set by hardware to indicate the PID data of the current bank:
Value
0
1
2
3
Name
DATA0
DATA1
DATA2
MDATA
Description
DATA0
DATA1
Data2 (only for High Bandwidth Isochronous Endpoint)
MData (only for High Bandwidth Isochronous Endpoint)
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1163
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.21 UDPHS DMA Channel Transfer Descriptor
The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer. The
structure of the DMA channel transfer descriptor is defined by three parameters as described below:
•
•
•
Offset 0:
– The address must be aligned: 0xXXXX0
– Next Descriptor Address Register: UDPHS_DMANXTDSCx
Offset 4:
– The address must be aligned: 0xXXXX4
– DMA Channelx Address Register: UDPHS_DMAADDRESSx
Offset 8:
– The address must be aligned: 0xXXXX8
– DMA Channelx Control Register: UDPHS_DMACONTROLx
To use the DMA channel transfer descriptor, fill the structures with the correct value (as described in the following
pages). Then write directly in UDPHS_DMANXTDSCx the address of the descriptor to be used first. Then write '1' in
the LDNXT_DSC bit of UDPHS_DMACONTROLx (load next channel transfer descriptor). The descriptor is
automatically loaded upon Endpointx request for packet transfer.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1164
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.22 UDPHS DMA Next Descriptor Address Register
Name:
Offset:
Reset:
Property:
UDPHS_DMANXTDSCx
0x0310 + (x-1)*0x10 [x=1..6]
0x00000000
Read/Write
Channel 0 is not used.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
NXT_DSC_ADD[31:24]
R/W
R/W
0
0
20
19
NXT_DSC_ADD[23:16]
R/W
R/W
0
0
12
11
NXT_DSC_ADD[15:8]
R/W
R/W
0
0
4
3
NXT_DSC_ADD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – NXT_DSC_ADD[31:0] Next Descriptor Address
This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to
3 of the address must be equal to zero.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1165
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.23 UDPHS DMA Channel Address Register
Name:
Offset:
Reset:
Property:
UDPHS_DMAADDRESSx
0x0314 + (x-1)*0x10 [x=1..6]
0x00000000
Read/Write
Channel 0 is not used.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
BUFF_ADD[31:24]
R/W
R/W
0
0
20
19
BUFF_ADD[23:16]
R/W
R/W
0
0
12
11
BUFF_ADD[15:8]
R/W
R/W
0
0
4
3
BUFF_ADD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – BUFF_ADD[31:0] Buffer Address
This field determines the AHB bus starting address of a DMA channel transfer.
Channel start and end addresses may be aligned on any byte boundary.
The firmware may write this field only when the UDPHS_DMASTATUS.CHANN_ENB bit is clear.
This field is updated at the end of the address phase of the current access to the AHB bus. It is incrementing of the
access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not
aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the
channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel
buffer.
The channel start address is written by software or loaded from the descriptor, whereas the channel end address is
either determined by the end of buffer or the UDPHS device, USB end of transfer if the
UDPHS_DMACONTROL.END_TR_EN bit is set.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1166
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.24 UDPHS DMA Channel Control Register
Name:
Offset:
Reset:
Property:
UDPHS_DMACONTROLx
0x0318 + (x-1)*0x10 [x=1..6]
0x00000000
Read/Write
Channel 0 is not used.
Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”.
For reliability it is highly recommended to wait for both UDPHS_DMASTATUS.CHAN_ACT and CHAN_ENB flags at
0, thus ensuring the channel has been stopped before issuing a command other than “Stop Now”.
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
28
27
BUFF_LENGTH[15:8]
R/W
R/W
0
0
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
12
6
DESC_LD_IT
R/W
0
5
END_BUFFIT
R/W
0
4
END_TR_IT
R/W
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
3
END_B_EN
R/W
0
2
END_TR_EN
R/W
0
1
LDNXT_DSC
R/W
0
0
CHANN_ENB
R/W
0
20
19
BUFF_LENGTH[7:0]
R/W
R/W
0
0
Access
Reset
Bit
7
BURST_LCK
Access
R/W
Reset
0
Bits 31:16 – BUFF_LENGTH[15:0] Buffer Byte Length (Write-only)
This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size
(64 Kbytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0,
but the transfer end may occur earlier under UDPHS device control.
When this field is written, the UDPHS_DMASTATUS.BUFF_COUNT field is updated with the write value.
Bit 7 – BURST_LCK Burst Lock Enable
Value
Description
0
The DMA never locks bus access.
1
USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and
maximization of fly-by AHB burst duration.
Bit 6 – DESC_LD_IT Descriptor Loaded Interrupt Enable
Value
Description
0
UDPHS_DMASTATUS.DESC_LDST rising will not trigger any interrupt.
1
An interrupt is generated when a descriptor has been loaded from the bus.
Bit 5 – END_BUFFIT End of Buffer Interrupt Enable
Value
Description
0
UDPHS_DMASTATUS.END_BF_ST rising will not trigger any interrupt.
1
An interrupt is generated when the UDPHS_DMASTATUS.BUFF_COUNT reaches zero.
Bit 4 – END_TR_IT End of Transfer Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1167
SAM9X60
USB High Speed Device Port (UDPHS)
Value
0
1
Description
UDPHS device initiated buffer transfer completion will not trigger any interrupt at
UDPHS_STATUS.END_TR_ST rising.
An interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer
transfer.
Use when the receive size is unknown.
Bit 3 – END_B_EN End of Buffer Enable (Control)
Value
Description
0
DMA Buffer End has no impact on USB packet transfer.
1
Endpoint can validate the packet (according to the values programmed in the
UDPHS_EPTCTL.AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e., when the
UDPHS_DMASTATUS.BUFF_COUNT reaches 0.
This is mainly for short packet IN validation initiated by the DMA reaching end of buffer, but could be
used for OUT packet truncation (discarding of unwanted packet data) at the end of DMA buffer.
Bit 2 – END_TR_EN End of Transfer Enable (Control)
Used for OUT transfers only.
Value
Description
0
USB end of transfer is ignored.
1
UDPHS device can put an end to the current buffer transfer.
When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame
(DATAX) will close the current buffer and the UDPHS_DMASTATUS.END_TR_ST flag will be raised.
This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or
ISOCHRONOUS microframe data buffer closure.
Bit 1 – LDNXT_DSC Load Next Channel Transfer Descriptor Enable (Command)
If the CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request.
DMA Channel Control Command Summary:
LDNXT_DSC
CHANN_ENB
0
0
1
1
Value
0
1
Description
0
1
0
1
Stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
Description
No channel register is loaded after the end of the channel transfer.
The channel controller loads the next descriptor after the end of the current transfer, i.e., when the
UDPHS_DMASTATUS.CHANN_ENB bit is reset.
Bit 0 – CHANN_ENB (Channel Enable Command)
Value
Description
0
DMA channel is disabled at and no transfer will occur upon request. This bit is also cleared by
hardware when the channel source bus is disabled at end of buffer.
If the UDPHS_DMACONTROL.LDNXT_DSC bit has been cleared by descriptor loading, the firmware
will have to set the corresponding CHANN_ENB bit to start the described transfer, if needed.
If the LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read
and/or written reliably as soon as both UDPHS_DMASTATUS.CHANN_ENB and CHANN_ACT flags
read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it
is empty, then the UDPHS_DMASTATUS.CHANN_ENB bit is cleared.
If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped
(no data transfer occurs) and the next descriptor is immediately loaded.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1168
SAM9X60
USB High Speed Device Port (UDPHS)
Value
1
Description
The UDPHS_DMASTATUS.CHANN_ENB bit will be set, thus enabling DMA channel data transfer.
Then, any pending request will start the transfer. This may be used to start or resume any requested
transfer.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1169
SAM9X60
USB High Speed Device Port (UDPHS)
41.7.25 UDPHS DMA Channel Status Register
Name:
Offset:
Reset:
Property:
UDPHS_DMASTATUSx
0x031C + (x-1)*0x10 [x=1..6]
0x00000000
Read/Write
Channel 0 is not used.
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
28
27
BUFF_COUNT[15:8]
R/W
R/W
0
0
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
12
7
6
DESC_LDST
R/W
0
5
END_BF_ST
R/W
0
4
END_TR_ST
R/W
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
3
2
1
CHANN_ACT
R/W
0
0
CHANN_ENB
R/W
0
20
19
BUFF_COUNT[7:0]
R/W
R/W
0
0
Access
Reset
Bit
Access
Reset
Bits 31:16 – BUFF_COUNT[15:0] Buffer Byte Count
This field determines the current number of bytes still to be transferred for this buffer. It is decremented from the AHB
source bus access byte width at the end of this bus address phase.
The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word
boundary.
At the end of buffer, the DMA accesses the UDPHS device only for the number of bytes needed to complete it.
This field value is reliable (stable) only if the channel has been stopped or frozen (the
UDPHS_EPTCTLx.NT_DIS_DMA bit is used to disable the channel request) and the channel is no longer active
(CHANN_ACT flag is 0).
Note: For OUT endpoints, if the receive buffer byte length (BUFF_LENGTH) has been defaulted to zero because
the USB transfer length is unknown, the actual buffer byte length received is 0x10000-BUFF_COUNT.
Bit 6 – DESC_LDST Descriptor Loaded Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
Value
Description
0
Cleared automatically when read by software.
1
Set by hardware when a descriptor has been loaded from the system bus.
Bit 5 – END_BF_ST End of Channel Buffer Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
Value
Description
0
Cleared automatically when read by software.
1
Set by hardware when the BUFF_COUNT countdown reaches zero.
Bit 4 – END_TR_ST End of Channel Transfer Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
Value
Description
0
Cleared automatically when read by software.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1170
SAM9X60
USB High Speed Device Port (UDPHS)
Value
1
Description
Set by hardware when the last packet transfer is complete, if the UDPHS device has ended the
transfer.
Bit 1 – CHANN_ACT Channel Active Status
When a packet transfer is ended, this bit is automatically reset.
When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel
descriptor load (if any) and potentially until UDPHS packet transfer completion, if allowed by the new descriptor.
Value
Description
0
The DMA channel is no longer trying to source the packet data.
1
The DMA channel is currently trying to source packet data, i.e., selected as the highest-priority
requesting channel.
Bit 0 – CHANN_ENB Channel Enable Status
When any transfer is ended either due to an elapsed byte count or a UDPHS device initiated transfer end, this bit is
automatically reset.
This bit is normally set or cleared by writing into the UDPHS_DMACONTROLx.CHANN_ENB bit either by software or
descriptor loading.
If a channel request is currently serviced when the CHANN_ENB bit is cleared, the DMA FIFO buffer is drained until it
is empty, then this status bit is cleared.
Value
Description
0
The DMA channel no longer transfers data, and may load the next descriptor if the
UDPHS_DMACONTROLx.LDNXT_DSC bit is set.
1
The DMA channel is currently enabled and transfers data upon request.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1171
SAM9X60
USB Host High Speed Port (UHPHS)
42.
USB Host High Speed Port (UHPHS)
42.1
Description
The USB Host High Speed Port (UHPHS) interfaces the USB with the host application. It handles Open HCI protocol
(Open Host Controller Interface) as well as Enhanced HCI protocol (Enhanced Host Controller Interface).
42.2
Embedded Characteristics
•
•
•
•
•
•
Block Diagram
System Bus
System Bus
Figure 42-1. Block Diagram
HCI
Slave Block
Slave
OHCI
Registers
Root
Hub Registers
List Processor
Block
Control
ED & TD
Registers
Embedded USB
v2.0 Transceiver
Root Hub
and
Host SIE
Master
HCI
Master Block
Data
System Bus
HCI
Slave Block
Slave
EHCI
Registers
PORT S/M 2
USB High-speed
Transceiver
HHSDPC
HHSDMC
FIFO 64 x 8
SOF
generator
System Bus
42.3
Compliant with Enhanced HCI Rev 1.0 Specification
– Compliant with USB V2.0 High-speed Specification
– Supports High-speed 480 Mbps
Compliant with Open HCI Rev 1.0 Specification
– Compliant with USB V2.0 Full-speed and Low-speed Specification
– Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices
Root Hub Integrated with 2 Downstream USB HS Ports and 1 FS Port
Embedded USB Transceivers
Supports Power Management
3 Hosts (A, B, and C) High Speed (EHCI), Port A shared with UDPHS
PORT S/M 1
USB High-speed
Transceiver
PORT S/M 0
USB High-speed
Transceiver
HHSDPB
HHSDMB
HHSDPA
HHSDMA
Packet
Buffer
FIFO
Control
List
Processor
Master
HCI
Master Block
Data
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1172
SAM9X60
USB Host High Speed Port (UHPHS)
Access to the USB host operational registers is achieved through the system bus slave interface. The Open HCI host
controller and Enhanced HCI host controller initialize master DMA transfers through the system bus master interface
as follows:
•
•
•
•
Fetches endpoint descriptors and transfer descriptors
Accesses endpoint data from system memory
Accesses HC communication area
Writes status and retires transfer descriptor
Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the corresponding flag in
the host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of
downstream ports can be determined by the software driver reading the root hub’s operational registers. Device
connection is automatically detected by the USB host port logic.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
42.4
Typical Connection
Figure 42-2. Board Schematic to Interface UHP High-speed Host Controller
PIO (VBUS ENABLE)
+5V
"A" Receptacle
1 = VBUS
2 = D3 = D+
4 = GND
HHSDM
3 4
Shell = Shield
1 2
HHSDP
5K62 ± 1% W
RTUNE
10 pF
(DNP)
42.5
42.5.1
Product Dependencies
I/O Lines
HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High Speed physical
transceivers are controlled by the USB host controller.
One transceiver is shared with the USB High Speed Device (port A). The selection between Host Port A and USB
Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL register.
In the case the port A is driven by the USB High Speed Device, the output signals are DHSDP and DHSDM. The
transceiver is automatically selected for Device operation once the USB High Speed Device is enabled.
In the case the port A is driven by the USB High Speed Host, the output signals are HHSDPA and HHSDMA.
42.5.2
Power Management
The system embeds 3 transceivers.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1173
SAM9X60
USB Host High Speed Port (UHPHS)
The USB Host High Speed requires a 480 MHz clock for the embedded High-speed transceivers. This clock
(UPLLCK) is provided by the UTMI PLL.
In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not possible.
Nevertheless, OHCI Full-speed operations remain possible by selecting PLLACK as the input clock of OHCI.
The High-speed transceiver returns a 30 MHz clock to the USB Host controller.
The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations. These clocks must be
generated by a PLL with a correct accuracy of +/-0.25% using the USBDIV field.
Thus the USB Host peripheral receives three clocks from the Power Management Controller (PMC): the Peripheral
Clock (MCK domain), the UHP48M and the UHP12M (built-in UHP48M divided by four) used by the OHCI to interface
with the bus USB signals (recovered 12 MHz domain) in Full-speed operations.
For High-speed operations, the user has to perform the following:
• Enable UHPHS peripheral clock in the PMC.
• Start the UPLL with a 480 MHz output frequency following the recommendation provided in section "USB Clock
Controller" in chapter "Power Management Controller (PMC)".
• Select UPLLCK as Input clock of OHCI part (USBS bit in PMC_USB register).
• Program OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV must be 9
(division by 10) if UPLLCK is selected.
• Enable OHCI clocks with UHP bit in PMC_SCER.
For OHCI Full-speed operations only, the user can use the PLLA, and in this case has to perform the following:
• Enable UHPHS peripheral clock in the PMC.
• Select PLLACK as Input clock of OHCI part (USBS bit in PMC_USB register).
• Program OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV value is to be
calculated according to the PLLACK value and USB Full-speed accuracy.
• Enable the OHCI clocks with UHP bit in PMC_SCER.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1174
SAM9X60
USB Host High Speed Port (UHPHS)
Figure 42-3. UHP Clock Trees
System Bus
EHCI
Master
Interface
EHCI
User
Interface
System Bus
System Bus
UPLL (480 MHz)
OHCI
Master
Interface
30 MHz
Port
Router
USB 2.0 EHCI
Host Controller
30 MHz
30 MHz
UTMI transceiver
UTMI transceiver
UTMI transceiver
UHP48M
OHCI
User
Interface
Root Hub
and
Host SIE
USB 1.1 OHCI
Host Controller
UHP12M
System Bus
MCK
OHCI clocks
42.5.3
Interrupt Sources
The USB host interface has an interrupt line connected to the interrupt controller.
Handling USB host interrupts requires programming the interrupt controller before configuring the UHPHS.
42.6
Functional Description
42.6.1
UTMI Transceivers Sharing
The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second
UTMI transceiver. The selection between Host Port A and USB device is controlled by the UDPHS enable bit
(EN_UDPHS) located in the UDPHS_CTRL register.
Figure 42-4. USB Selection
Other
Transceiver
HS
Transceiver
EN_UDPHS
0
Other Ports
PA
HS USB Host
HS EHCI
FS OHCI
DMA
© 2020 Microchip Technology Inc.
1
HS
USB
Device
DMA
Complete Datasheet
DS60001579C-page 1175
SAM9X60
USB Host High Speed Port (UHPHS)
42.6.2
EHCI
The USB Host Port controller is fully compliant with the Enhanced HCI specification. The USB Host Port User
Interface (registers description) can be found in the Enhanced HCI Rev 1.0 Specification available on www.usb.org
42.6.3
OHCI
The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several Full-speed halfduplex serial communication ports at a baud rate of 12 Mbps. Up to 127 USB devices (printer, camera, mouse,
keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB “tiered star” topology.
The USB Host Port controller is fully compliant with the Open HCI specification. The USB Host Port User Interface
(registers description) can be found in the Open HCI Rev 1.0 Specification available on www.usb.org.
All standard class devices are automatically detected and available to the user’s application. As an example,
integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and
mouses.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1176
SAM9X60
USB Host High Speed Port (UHPHS)
42.7
Register Summary
The Enhanced USB Host Controller contains two sets of software-accessible hardware registers: memory-mapped
Host Controller Registers and optional PCI configuration registers. Note that the PCI configuration registers are only
needed for PCI devices that implement the Host Controller.
•
•
Memory-mapped USB Host Controller Registers—This block of registers is memory-mapped into non-cacheable
memory. This memory space must begin on a DWord (32-bit) boundary. This register space is divided into two
sections: a set of read-only capability registers and a set of read/write operational registers. The table below
describes each register space.
Note: Host controllers are not required to support exclusive-access mechanisms (such as PCI LOCK) for
accesses to the memory-mapped register space. Therefore, if software attempts exclusive-access mechanisms
to the host controller memory-mapped register space, the results are undefined.
PCI Configuration Registers (for PCI devices)—In addition to the normal PCI header, power management, and
device-specific registers, two registers are needed in the PCI configuration space to support USB. The normal
PCI header and device-specific registers are beyond the scope of this document (the UHPHS_CLASSC register
is shown in this document). Note that HCD does not interact with the PCI configuration space. This space is
used only by the PCI enumerator to identify the USB Host Controller, and assign the appropriate system
resources.
The table below summarizes the enhanced interface register sets.
Offset
Register Set
Explanation
0 to N-1
Capability Registers
The capability registers specify the limits, restrictions, and capabilities of a host
controller implementation.
These values are used as parameters to the host controller driver.
N to N+M-1 Operational Registers The operational registers are used by system software to control and monitor
the operational state of the host controller.
Note: Software must not modify reserved bits in Read/Write registers.
Offset
0x00
0x04
0x08
0x0C
...
0x0F
0x10
0x14
Name
UHPHS_HCCAPBA
SE
UHPHS_HCSPARA
MS
UHPHS_HCCPARA
MS
Bit Pos.
7
6
5
31:24
23:16
15:8
7:0
31:24
4
3
2
1
0
HCIVERSION[15:8]
HCIVERSION[7:0]
CAPLENGTH[7:0]
P_INDICATO
R
23:16
N_DP[3:0]
15:8
7:0
31:24
23:16
15:8
7:0
N_CC[3:0]
N_PCC[3:0]
N_PORTS[3:0]
PPC
EECP[7:0]
IST[3:0]
ASPC
PFLF
AC
Reserved
UHPHS_USBCMD
UHPHS_USBSTS
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
LHCR
IAAD
ASE
ASS
PSS
RCM
IAA
© 2020 Microchip Technology Inc.
ITC[7:0]
ASPME
PSE
FLS[1:0]
HCHLT
HSE
Complete Datasheet
FLR
ASPMC[1:0]
HCRESET
RS
PCD
USBERRINT
USBINT
DS60001579C-page 1177
SAM9X60
USB Host High Speed Port (UHPHS)
...........continued
Offset
Name
0x18
UHPHS_USBINTR
0x1C
UHPHS_FRINDEX
0x20
...
0x23
Reserved
0x24
UHPHS_PERIODIC
LISTBASE
0x28
UHPHS_ASYNCLIS
TADDR
0x2C
...
0x4F
Reserved
0x50
UHPHS_CONFIGFL
AG
0x54
UHPHS_PORTSC0
Bit Pos.
UHPHS_PORTSC1
15:8
7:0
31:24
23:16
15:8
7:0
UHPHS_PORTSC2
Reserved
0xA8
UHPHS_INSNREG0
6
0xAC
UHPHS_INSNREG0
7
4
3
2
1
0
IAAE
HSEE
FLRE
PCIE
USBEIE
USBIE
FI[13:8]
BA[19:12]
BA[11:4]
BA[3:0]
LPL[26:19]
LPL[18:11]
LPL[10:3]
LPL[2:0]
31:24
23:16
15:8
7:0
31:24
CF
23:16
WKOC_E
PIC[1:0]
SUS
FPR
23:16
WKOC_E
PIC[1:0]
SUS
FPR
23:16
15:8
7:0
0x60
...
0xA7
5
FI[7:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
15:8
7:0
31:24
0x5C
6
31:24
23:16
15:8
7:0
31:24
0x58
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
WKOC_E
PIC[1:0]
SUS
FPR
WKDSCNNT_
WKCNNT_E
E
PO
PP
OCC
OCA
WKDSCNNT_
WKCNNT_E
E
PO
PP
OCC
OCA
WKDSCNNT_
WKCNNT_E
E
PO
PP
OCC
OCA
PTC[3:0]
LS[1:0]
PEDC
PED
CSC
PR
CCS
CSC
PR
CCS
CSC
PR
CCS
PTC[3:0]
LS[1:0]
PEDC
PED
PTC[3:0]
LS[1:0]
PEDC
PED
AHB_ERR
© 2020 Microchip Technology Inc.
HBURST[2:0]
Nb_Success_Burst[3:0]
Nb_Burst[3:0]
Nb_Burst[4]
AHB_ADDR[31:24]
AHB_ADDR[23:16]
AHB_ADDR[15:8]
AHB_ADDR[7:0]
Complete Datasheet
DS60001579C-page 1178
SAM9X60
USB Host High Speed Port (UHPHS)
42.7.1
UHPHS Host Controller Capability Register
Name:
Offset:
Reset:
Property:
UHPHS_HCCAPBASE
0x00
0x01000010
Read-only
Bit
31
30
29
28
27
HCIVERSION[15:8]
R
R
0
0
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
1
Bit
23
22
21
18
17
16
R
0
20
19
HCIVERSION[7:0]
R
R
0
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
Bit
7
6
5
2
1
0
R
0
R
0
R
0
4
3
CAPLENGTH[7:0]
R
R
1
0
Access
Reset
R
0
R
0
R
0
Access
Reset
Bits 31:16 – HCIVERSION[15:0] Host Controller Interface Version Number
This is a two-byte field containing a BCD encoding of the EHCI revision number supported by this host controller. The
most significant byte of this field represents the major revision and the least significant byte the minor revision.
Bits 7:0 – CAPLENGTH[7:0] Capability Registers Length
This field is used as an offset to add to the register base to find the beginning of the Operational Register Space.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1179
SAM9X60
USB Host High Speed Port (UHPHS)
42.7.2
UHPHS Host Controller Structural Parameters Register
Name:
Offset:
Reset:
Property:
UHPHS_HCSPARAMS
0x04
0x00001116
Read-only
These fields define structural parameters: number of downstream ports, etc.
Bit
31
30
23
22
29
28
27
26
25
24
21
20
19
18
17
R
0
R
0
16
P_INDICATOR
R
0
13
12
11
10
9
8
R
0
R
1
1
N_PORTS[3:0]
R
R
1
1
0
Access
Reset
Bit
N_DP[3:0]
Access
Reset
R
0
R
0
Bit
15
14
N_CC[3:0]
N_PCC[3:0]
Access
Reset
R
0
R
0
R
0
R
1
R
0
R
0
Bit
7
6
5
4
PPC
R
1
3
2
Access
Reset
R
0
R
0
Bits 23:20 – N_DP[3:0] Debug Port Number
Optional. This register identifies which of the host controller ports is the debug port. The value is the port number (1based) of the debug port. A non-zero value in this field indicates the presence of a debug port. The value in this
register must not be greater than N_PORTS.
Bit 16 – P_INDICATOR Port Indicators
This bit indicates whether the ports support port indicator control. When this bit is a 1, the port status and control
registers include a read/writeable field for controlling the state of the port indicator. See UHPHS Port Status and
Control Register for a definition of the port indicator control field.
Bits 15:12 – N_CC[3:0] Number of Companion Controllers
This field indicates the number of companion controllers associated with this USB 2.0 host controller.
A zero in this field indicates there are no companion host controllers. Port-ownership hand-off is not supported. Only
high-speed devices are supported on the host controller root ports.
A value larger than zero in this field indicates there are companion USB 1.1 host controller(s). Port-ownership handoffs are supported. High, Full- and Low-speed devices are supported on the host controller root ports.
Bits 11:8 – N_PCC[3:0] Number of Ports per Companion Controller
This field indicates the number of ports supported per companion host controller. It is used to indicate the port routing
configuration to system software.
For example, if N_PORTS has a value of 6 and N_CC has a value of 2, then N_PCC could have a value of 3. The
convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports
to companion controller 2, etc. In the previous example, the N_PCC could have been 4, where the first four are
routed to companion controller 1 and the last two are routed to companion controller 2.
The number in this field must be consistent with N_PORTS and N_CC.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1180
SAM9X60
USB Host High Speed Port (UHPHS)
Bit 4 – PPC Port Power Control
This field indicates whether the host controller implementation includes port power control. A one in this bit indicates
the ports have port power switches. A zero in this bit indicates the ports do not have port power switches. The value
of this field affects the functionality of the Port Power field in each port status and control register (see UHPHS Port
Status and Control Register).
Bits 3:0 – N_PORTS[3:0] Number of Ports
This field specifies the number of physical downstream ports implemented on this host controller. The value of this
field determines how many port registers are addressable in the Operational Register Space. Valid values are in the
range of 1 to 15.
A zero in this field is undefined.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1181
SAM9X60
USB Host High Speed Port (UHPHS)
42.7.3
UHPHS Host Controller Capability Parameters Register
Name:
Offset:
Reset:
Property:
UHPHS_HCCPARAMS
0x08
0x0000A010
Read-only
These fields define capability parameters: Multiple Mode control (time-base bit functionality), addressing capability,
etc.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
EECP[7:0]
Access
Reset
R
1
R
0
Bit
7
6
R
1
R
0
R
0
R
0
R
0
R
0
5
4
3
R
0
R
1
2
ASPC
R
0
1
PFLF
R
0
0
AC
R
0
IST[3:0]
Access
Reset
R
0
R
0
Bits 15:8 – EECP[7:0] EHCI Extended Capabilities Pointer
Indicates the existence of a capabilities list. A value of 0 indicates no extended capabilities are implemented. A nonzero value in this register indicates the offset in the PCI configuration space of the first EHCI extended capability. The
pointer value must be 64 or greater if implemented to maintain the consistency of the PCI header defined for this
class of device.
Bits 7:4 – IST[3:0] Isochronous Scheduling Threshold
Indicates, relative to the current position of the executing host controller, where software can reliably update the
isochronous schedule. When bit [7] is 0, the value of the least significant three bits indicates the number of
microframes a host controller can hold a set of isochronous data structures (one or more) before flushing the state.
When bit [7] is set to 1, the host software assumes the host controller may cache an isochronous data structure for
an entire frame.
Bit 2 – ASPC Asynchronous Schedule Park Capability
The park capability can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park
Mode Enable and Asynchronous Schedule Park Mode Count fields in the UHPHS_USBCMD register.
Value
Description
0
Host controller does not supports the park feature for high-speed queue.
1
Host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.
Bit 1 – PFLF Programmable Frame List Flag
Value
Description
0
System software must use a frame list length of 1024 elements with this host controller. The
UHPHS_USBCMD register Frame List Size field is a read-only register and must be set to 0.
1
System software can specify and use a smaller frame list and configure the host controller via the
UHPHS_USBCMD register Frame List Size field. The frame list must always be aligned on a 4-Kbyte
page boundary. This requirement ensures that the frame list is always physically contiguous.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1182
SAM9X60
USB Host High Speed Port (UHPHS)
Bit 0 – AC 64-bit Addressing Capability
This field documents the addressing range capability of this implementation. The value of this field determines
whether software should use 32-bit or 64-bit data structures.
This information is not tightly coupled with the UHPHS_USBBASE address register mapping control. The 64-bit
Addressing Capability bit indicates whether the host controller can generate 64-bit addresses as a master. The
UHPHS_USBBASE register indicates the host controller only needs to decode 32-bit addresses as a slave.
Value
Description
0
Data structures using 32-bit address memory pointers
1
Data structures using 64-bit address memory pointers
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1183
SAM9X60
USB Host High Speed Port (UHPHS)
42.7.4
UHPHS USB Command Register
Name:
Offset:
Reset:
Property:
UHPHS_USBCMD
0x10
0x00080B00
Read/Write
The Command Register indicates the command to be executed by the serial bus host controller. Writing to the
register causes a command to be executed.
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
R/W
0
Access
Reset
Bit
ITC[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
15
14
13
12
11
ASPME
R-R/W
1
10
9
7
LHCR
R/W
0
6
IAAD
R/W
0
5
ASE
R/W
0
4
PSE
R/W
0
3
Access
Reset
Bit
Access
Reset
2
FLS[1:0]
R-R/W
0
R-R/W
0
8
ASPMC[1:0]
R-R/W
R-R/W
1
1
1
HCRESET
R/W
0
0
RS
R/W
0
Bits 23:16 – ITC[7:0] Interrupt Threshold Control
This field is used by system software to select the maximum rate at which the host controller will issue interrupts. The
only valid values are defined below. If software writes an invalid value to this register, the results are undefined.
Value
Maximum Interrupt Interval
0
1
2
4
8
16
32
64
Reserved
1 microframe
2 microframes
4 microframes
8 microframes (1 ms)
16 microframes (2 ms)
32 microframes (4 ms)
64 microframes (8 ms)
Any other value in this register yields undefined results.
Software modifications to this field while HCHLT=0 results in undefined behavior.
Bit 11 – ASPME Asynchronous Schedule Park Mode Enable (optional)
If the Asynchronous Park Capability bit in the UHPHS_HCCPARAMS register is set to 1, then this bit is set to 1 and is
Read/Write. Otherwise the bit must be 0 and is read-only.
Value
Description
0
Park mode is enabled.
1
Park mode is disabled.
Bits 9:8 – ASPMC[1:0] Asynchronous Schedule Park Mode Count (optional)
If the Asynchronous Park Capability bit in the UHPHS_HCCPARAMS register is set to 1, then this field defaults to 3
and is read/write. Otherwise it defaults to 0 and is read-only. It contains a count of the number of successive
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule
before continuing traversal of the Asynchronous schedule. Valid values are 1 to 3. Software must not write a 0 to this
bit when Park Mode Enable is set to 1 as this will result in undefined behavior.
Bit 7 – LHCR Light Host Controller Reset (optional)
This control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the
state of the ports or the relationship to the companion host controllers. For example, the UHPHS_PORTSC registers
should not be reset to their default values and the CF bit setting should not go to 0 (retaining port ownership
relationships).
A host software read of this bit as 0 indicates the Light Host Controller Reset has completed and it is safe for host
software to re-initialize the host controller. A host software read of this bit as 1 indicates the Light Host Controller
Reset has not yet completed.
If not implemented, a read of this field will always return a 0.
Bit 6 – IAAD Interrupt on Async Advance Doorbell
This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances
asynchronous schedule. Software must write a 1 to this bit to ring the doorbell.
When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance
status bit in the UHPHS_USBSTS register. If the Interrupt on Async Advance Enable bit in the UHPHS_USBINTR
register is set to 1, then the host controller will assert an interrupt at the next interrupt threshold.
The host controller sets this bit to 0 after it has set the Interrupt on Async Advance status bit in the UHPHS_USBSTS
register to 1.
Software should not write a 1 to this bit when the asynchronous schedule is disabled. Doing so will yield undefined
results.
Bit 5 – ASE Asynchronous Schedule Enable
This bit controls whether the host controller skips processing the Asynchronous Schedule.
Value
Description
0
Do not process the Asynchronous Schedule.
1
Use the UHPHS_ASYNCLISTADDR register to access the Asynchronous Schedule.
Bit 4 – PSE Periodic Schedule Enable
This bit controls whether the host controller skips processing the Periodic Schedule.
Value
Description
0
Do not process the Periodic Schedule.
1
Use the UHPHS_PERIODICLISTBASE register to access the Periodic Schedule.
Bits 3:2 – FLS[1:0] Frame List Size
This field is read-only with one exception: it is read/write if the Programmable Frame List flag, in the
UHPHS_HCCPARAMS register, is set to 1. This field specifies the size of the frame list. The size of the frame list
controls which bits in the Frame Index Register should be used for the Frame List Current index.
Value
Description
0
1024 elements (4096 bytes).
1
512 elements (2048 bytes).
2
256 elements (1024 bytes), for resource-constrained environments.
3
Reserved.
Bit 1 – HCRESET Host Controller Reset
This control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to
a Chip Hardware Reset.
When software writes a 1 to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines,
etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not
driven on downstream ports.
PCI Configuration registers are not affected by this reset. All operational registers, including port registers and port
state machines, are set to their initial values. Port ownership reverts to the companion host controller(s) with side
effects. Software must reinitialize the host controller in order to return the host controller to an operational state.
This bit is set to 0 by the Host Controller when the reset process is complete. Software cannot terminate the reset
process early by writing a 0 to this register.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
Software must not set this bit to 1 when HCHLT in the UHPHS_USBSTS register is 0. Attempting to reset an actively
running host controller results in undefined behavior.
Bit 0 – RS Run/Stop
The Host Controller must halt within 16 microframes after software clears the bit RS. The HCHLT bit in the status
register indicates when the Host Controller has finished its pending pipelined transactions and has entered the
stopped state. Software must not write 1 to this field unless the host controller is in the halted state (i.e., HCHLT in
the UHPHS_USBSTS register is 1). Doing so yields undefined results.
Value
Description
0
Host Controller completes the current and any actively pipelined transactions on the USB and then
halts.
1
Host Controller proceeds with execution of the schedule.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
42.7.5
UHPHS USB Status Register
Name:
Offset:
Reset:
Property:
UHPHS_USBSTS
0x14
0x00001000
Read/Write
This register indicates pending interrupts and various states of the Host Controller. The status resulting from a
transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by writing a 1 to it.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ASS
R
0
14
PSS
R
0
13
RCM
R
0
12
HCHLT
R
1
11
10
9
8
7
6
5
IAA
R/W
0
4
HSE
R/W
0
3
FLR
R/W
0
2
PCD
R/W
0
1
USBERRINT
R/W
0
0
USBINT
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 15 – ASS Asynchronous Schedule Status
The bit reports the current real status of the Asynchronous Schedule.
The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software
transitions the Asynchronous Schedule Enable bit in the UHPHS_USBCMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled or disabled.
Value
Description
0
Asynchronous Schedule is disabled.
1
Asynchronous Schedule is enabled.
Bit 14 – PSS Periodic Schedule Status
The bit reports the current real status of the Periodic Schedule. If this bit is set to 0, then the status of the Periodic
Schedule is disabled. If this bit is set to 1, then the status of the Periodic Schedule is enabled. The Host Controller is
not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule
Enable bit in the UHPHS_USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value,
the Periodic Schedule is either enabled or disabled.
Bit 13 – RCM Reclamation
This is a read-only status bit used to detect any empty asynchronous schedule.
Bit 12 – HCHLT HCHalted
This bit is 0 whenever the Run/Stop bit is 1. The Host Controller sets this bit to 1 after it has stopped executing as a
result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. internal error).
Bit 5 – IAA Interrupt on Async Advance (Cleared on write)
System software can force the host controller to issue an interrupt the next time the host controller advances the
asynchronous schedule by writing 1 to the Interrupt on the Async Advance Doorbell bit in the UHPHS_USBCMD
register. This status bit indicates the assertion of that interrupt source.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
Bit 4 – HSE Host System Error (Cleared on write)
The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host
Controller module. In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and
PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to
prevent further execution of the scheduled TDs.
Bit 3 – FLR Frame List Rollover (Cleared on write)
The Host Controller sets this bit to 1 when the Frame List Index (see UHPHS USB Frame Index Register) rolls over
from its maximum value to 0. The exact value at which the rollover occurs depends on the frame list size. For
example, if the frame list size (as programmed in the Frame List Size field of the UHPHS_USBCMD register) is 1024,
the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host Controller
sets this bit to 1 every time FRINDEX[12] toggles.
Bit 2 – PCD Port Change Detect (Cleared on write)
The Host Controller sets this bit to 1 when any port for which the Port Owner bit is set to 0 (see UHPHS Port Status
and Control Register) has a change bit transition from 0 to 1 or a Force Port Resume bit transition from 0 to 1 as a
result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status
Change being set to 1 after system software has relinquished ownership of a connected port by writing 1 to a port's
Port Owner bit.
This bit is allowed to be maintained in the Auxiliary power well. Alternatively, it is also acceptable that on a D3 to D0
transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force
Port Resume, Overcurrent Change, Enable/Disable Change and Connect Status Change).
Bit 1 – USBERRINT USB Error Interrupt (Cleared on write)
The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error
counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT
bit are set.
Bit 0 – USBINT USB Interrupt (Cleared on write)
The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a
Transfer Descriptor that had its IOC bit set.
The Host Controller also sets this bit to 1 when a short packet is detected (the actual number of bytes received was
less than the expected number of bytes).
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
42.7.6
UHPHS USB Interrupt Enable Register
Name:
Offset:
Reset:
Property:
UHPHS_USBINTR
0x18
0x00000000
Read/Write
This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the
corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in the UHPHS_USBSTS to allow the software to poll for events.
For all bits, 1=Enabled, 0=Disabled.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
IAAE
R/W
0
4
HSEE
R/W
0
3
FLRE
R/W
0
2
PCIE
R/W
0
1
USBEIE
R/W
0
0
USBIE
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – IAAE Interrupt on Async Advance Enable
The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit UHPHS_USBSTS.
Bit 4 – HSEE Host System Error Enable
The interrupt is acknowledged by software clearing the Host System Error bit in UHPHS_USBSTS.
Bit 3 – FLRE Frame List Rollover Enable
The interrupt is acknowledged by software clearing the Frame List Rollover in UHPHS_USBSTS.
Bit 2 – PCIE Port Change Interrupt Enable
The interrupt is acknowledged by software clearing the Port Change Detect bit in UHPHS_USBSTS.
Bit 1 – USBEIE USB Error Interrupt Enable
The interrupt is acknowledged by software clearing the USBERRINT in UHPHS_USBSTS.
Bit 0 – USBIE USB Interrupt Enable
The interrupt is acknowledged by software clearing the USBINT in UHPHS_USBSTS.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
42.7.7
UHPHS USB Frame Index Register
Name:
Offset:
Reset:
Property:
UHPHS_FRINDEX
0x1C
0x00000000
Read/Write
This register is used by the host controller to index into the periodic frame list. The register updates every 125 μs
(once each microframe). Bits [N:3] are used to select a particular entry in the Periodic Frame List during periodic
schedule execution. The number of bits used for the index depends on the size of the frame list as set by system
software in the Frame List Size field in the UHPHS_USBCMD register).
This register must be written as a DWord. Byte writes produce undefined results. This register cannot be written
unless the Host Controller is in the Halted state as indicated by the HCHLT bit (UHPHS_USBSTS register). A write to
this register while the Run/Stop bit is set to 1 (UHPHS_USBCMD register) produces undefined results. Writes to this
register also affect the SOF value.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
FI[13:8]
Access
Reset
Bit
7
6
R/W
0
R/W
0
5
4
FI[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:0 – FI[13:0] Frame Index
The value in this register increments at the end of each time frame (e.g., microframe). Bits [N:3] are used for the
Frame List current index. This means that each location of the frame list is accessed eight times (frames or
microframes) before moving to the next index. The following illustrates values of N based on the value of FLS (Frame
List Size) in the UHPHS_USBCMD register.
UHPHS_USBCMD.FLS
Number Elements
N
0
1
2
3
1024
512
256
Reserved
12
11
10
–
The SOF frame number value for the bus SOF token is derived or alternatively managed from this register. The value
of FRINDEX must be 125 μs (1 microframe) ahead of the SOF token value. The SOF value may be implemented as
an 11-bit shadow register. For this discussion, this shadow register is 11 bits and is named SOFV. SOFV updates
every eight microframes (1 millisecond). An example implementation to achieve this behavior is to increment SOFV
each time the FRINDEX[2:0] increments from 0 to 1.
Software must use the value of FRINDEX to derive the current microframe number, both for high-speed isochronous
scheduling purposes and to provide the “get microframe number” function required for client drivers. Therefore, the
value of FRINDEX and the value of SOFV must be kept consistent if chip is reset or software writes to FRINDEX.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
Writes to FRINDEX must also write-through FRINDEX[13:3] to SOFV[10:0]. In order to keep the update as simple as
possible, software should never write a FRINDEX value where the three least significant bits are 7 or 0.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
42.7.8
UHPHS Periodic Frame List Base Address Register
Name:
Offset:
Reset:
Property:
UHPHS_PERIODICLISTBASE
0x24
0x00000000
Read/Write
This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. If the host
controller is in 64-bit mode (as indicated by a 1 in the 64-bit Addressing Capability field in the
UHPHS_HCCSPARAMS register), then the most significant 32 bits of every control data structure address comes
from the UHPHS_CTRLDSSEGMENT register. System software loads this register prior to starting the schedule
execution by the Host Controller. The memory structure referenced by this physical memory pointer is assumed to be
4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (UHPHS_FRINDEX) to
enable the Host Controller to step through the Periodic Frame List in sequence. This register must be written as a
DWord. Byte writes produce undefined results.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
BA[19:12]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
BA[11:4]
Access
Reset
Bit
R/W
0
R/W
0
15
14
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
12
11
10
9
8
3
2
1
0
BA[3:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
Access
Reset
Bits 31:12 – BA[19:0] Base Address (Low)
These bits correspond to memory address signals [31:12], respectively.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
42.7.9
UHPHS Asynchronous List Address Register
Name:
Offset:
Reset:
Property:
UHPHS_ASYNCLISTADDR
0x28
0x00000000
Read/Write
This 32-bit register contains the address of the next asynchronous queue head to be executed. If the host controller
is in 64-bit mode (as indicated by a 1 in the 64-bit Addressing Capability field in the UHPHS_HCCPARAMS register),
then the most significant 32 bits of every control data structure address comes from the UHPHS_CTRLDSSEGMENT
register. Bits [4:0] of this register cannot be modified by system software and will always return a zero when read.
The memory structure referenced by this physical memory pointer is assumed to be 32-byte (cache line) aligned.
This register must be written as a DWord. Byte writes produce undefined results.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
LPL[26:19]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
LPL[18:11]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
LPL[10:3]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
LPL[2:0]
R/W
0
5
4
3
2
1
0
R/W
0
R/W
0
Bits 31:5 – LPL[26:0] Link Pointer Low
These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head
(QH).
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Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
42.7.10 UHPHS Configure Flag Register
Name:
Offset:
Reset:
Property:
UHPHS_CONFIGFLAG
0x50
0x00000000
Read/Write
This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially applied or
in response to a host controller reset.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – CF Configure Flag
Host software sets this bit as the last action in its process of configuring the Host Controller. This bit controls the
default port-routing control logic. Bit values and side-effects are listed below.
Value
Description
0
Port routing control logic default-routes each port to an implementation-dependent classic host
controller (default value).
1
Port routing control logic default-routes all ports to this host controller.
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Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
42.7.11 UHPHS Port Status and Control Register
Name:
Offset:
Reset:
Property:
UHPHS_PORTSCx
0x54 + x*0x04 [x=0..2]
0x00002000
Read/Write
The number of port registers is documented in the UHPHS_HCSPARAMS register. Software uses this information as
an input parameter to determine how many ports need to be serviced. All ports have the structure defined below.
This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially applied or
in response to a host controller reset. The initial conditions of a port are:
•
•
No device connected
Port disabled
If the port has port power control, software cannot change the state of the port until after it applies power to the port
by setting port power to a 1. Software must not attempt to change the state of the port until after power is stable on
the port. The host is required to have power stable to the port within 20 milliseconds of the 0 to 1 transition.
Notes:
1. When a device is attached, the port state transitions to the connected state and system software will process
this as with any status change notification.
2. If a port is being used as the Debug Port, then the port may report device connected and enabled when the
Configured Flag is set to 0.
Bit
31
30
23
22
WKOC_E
R/W
0
29
28
27
26
25
24
19
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
PR
R/W
0
1
CSC
R/W
0
0
CCS
R
0
Access
Reset
Bit
Access
Reset
Bit
15
21
20
WKDSCNNT_E WKCNNT_E
R/W
R/W
0
0
14
Access
Reset
R/W
0
R/W
0
13
PO
R/W
1
Bit
7
SUS
R/W
0
6
FPR
R/W
0
5
OCC
R/W
0
PIC[1:0]
Access
Reset
PTC[3:0]
R/W
0
12
PP
R-R/W
0
11
R
0
R
0
4
OCA
R
0
3
PEDC
R/W
0
2
PED
R/W
0
LS[1:0]
Bit 22 – WKOC_E Wake on Overcurrent Enable
This field is 0 if Port Power is 0.
Value
Description
0
Disables the port to be sensitive to overcurrent conditions as wake-up events.
1
Enables the port to be sensitive to overcurrent conditions as wake-up events.
Bit 21 – WKDSCNNT_E Wake on Disconnect Enable
This field is 0 if Port Power is 0.
Value
Description
0
Disables the port to be sensitive to device disconnects as wake-up events.
1
Enables the port to be sensitive to device disconnects as wake-up events.
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Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
Bit 20 – WKCNNT_E Wake on Connect Enable
This field is 0 if Port Power is 0.
Value
Description
0
Disables the port to be sensitive to device connects as wake-up events.
1
Enables the port to be sensitive to device connects as wake-up events.
Bits 19:16 – PTC[3:0] Port Test Control
When this field is set to 0, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in
test mode and the specific test mode is indicated by the specific value.
Test mode bits are encoded as follows (6 to 15 are reserved):
Value
Test Mode
0
1
2
3
4
5
Test mode not enabled
Test J_STATE
Test K_STATE
Test SE0_NAK
Test Packet
Test FORCE_ENABLE
Refer to the USB Specification Revision 2.0, Chapter 7, for details on each test mode.
Bits 15:14 – PIC[1:0] Port Indicator Control
Writing to these bits has no effect if the P_INDICATOR bit in the UHPHS_HCSPARAMS register is set to 0. If the
P_INDICATOR bit is set to 1, then the bits are encoded as follows:
Value
Meaning
0
1
2
3
Port indicators are off
Amber
Green
Undefined
Refer to the USB Specification Revision 2.0 for a description of how these bits are to be used.
This field is 0 if Port Power is 0.
Bit 13 – PO Port Owner
System software uses this field to release ownership of the port to a selected host controller (in the event that the
attached device is not a high-speed device). Software writes 1 to this bit when the attached device is not a highspeed device. A 1 in this bit means that a companion host controller owns and controls the port.
Value
Description
0
This bit unconditionally goes to a 0 when the bit UHPHS_CONFIGFLAG.CF makes a 0 to 1 transition.
1
This bit unconditionally goes to 1 whenever the bit UHPHS_CONFIGFLAG.CF=0.
Bit 12 – PP Port Power
The function of this bit depends on the value of the Port Power Control (PPC) field in the UHPHS_HCSPARAMS
register. When host controller has port power control switches (PPC=0), PP is in read-only mode:
Value
Description
1
Each port is hard-wired to power.
When host controller has port power control switches (PPC=1), PP is in read/write mode:
Value Description
0
Host port power switch is OFF.
When power is not available on a port (i.e., PP at 0), the port is non-functional and does not report attaches,
detaches, etc.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
...........continued
Value Description
1
Host port power switch is ON.
When power is not available on a port (i.e., PP at 0), the port is non-functional and does not report attaches,
detaches, etc.
When an overcurrent condition is detected on a powered port and PPC is set to 1, the PP bit in each affected port
may be transitioned by the host controller from 1 to 0 (removing power from the port).
Bits 11:10 – LS[1:0] Line Status
These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for
detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port
enable bit is 0 and the current connect status bit is set to 1.
This value of this field is undefined if Port Power is 0.
Value
Name
Description
0
SE0
Not a low-speed device, perform EHCI reset
1
K-STATE
Low-speed device, release ownership of port
2
J-STATE
Not a low-speed device, perform EHCI reset
3
Undefined
Not a low-speed device, perform EHCI reset
Bit 8 – PR Port Reset
When software writes a 1 to this bit (from 0), the bus reset sequence as defined in the USB Specification Revision 2.0
is started. Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep this bit set to 1 long
enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes.
Note: When software writes this bit to 1, it must also write 0 to the Port Enable bit.
When software writes a 0 to this bit, there may be a delay before the bit status changes to 0. The bit status will not
read as 0 until after the reset has completed. If the port is in High-Speed mode after reset is complete, the host
controller will automatically enable this port (e.g., set the Port Enable bit to 1). A host controller must terminate the
reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from 1 to 0. For example:
if the port detects that the attached device is high-speed during reset, then the host controller must have the port in
the enabled state within 2 ms of software writing this bit to 0.
The HCHLT bit in the UHPHS_USBSTS register should be set to 0 before software attempts to use this bit. The host
controller may hold Port Reset asserted to 1 when the HCHLT bit is 1.
This field is 0 if Port Power is 0.
Value
Description
0
Port is not in Reset.
1
Port is in Reset.
Bit 7 – SUS Suspend
Value
Description
0
Port not in suspend state.
1
Port in suspend state.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
Note:
Port Enabled Bit and Suspend bit of this register define the port states as follows:
Bits [Port Enabled, Suspend]
Port State
0X
10
11
Disable
Enable
Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking
occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the
suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is
suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the
USB.
A write of 0 to this bit is ignored by the host controller. The host controller will unconditionally set this bit to 0 when:
• Software sets the Force Port Resume bit to 0 (from 1).
• Software sets the Port Reset bit to 1 (from 0).
If host software sets this bit to 1 when the port is not enabled (i.e., Port Enabled bit set to 0), the results are
undefined.
This field is 0 if Port Power is set to 0.
Bit 6 – FPR Force Port Resume
This functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is
not suspended (Suspend and Enabled bits are set to 1) and software transitions this bit to 1, then the effects on the
bus are undefined.
Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to 1 if a J-to-K transition is
detected while the port is in the Suspend state. When this bit transitions to 1 because a J-to-K transition is detected,
the Port Change Detect bit in the UHPHS_USBSTS register is also set to 1. If software sets this bit to 1, the host
controller must not set the Port Change Detect bit.
Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in
the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit
remains set to 1. Software must appropriately time the Resume and set this bit to 0 when the appropriate amount of
time has elapsed. Writing a 0 (from 1) causes the port to return to High-Speed mode (forcing the bus below the port
into a high-speed idle). This bit will remain set to 1 until the port has switched to the high-speed idle. The host
controller must complete this transition within 2 milliseconds of software setting this bit to 0.
This field is 0 if Port Power is 0.
Value
Description
0
No resume (K-state) detected/driven on port.
1
Resume detected/driven on port.
Bit 5 – OCC Overcurrent Change (Cleared on write)
Software clears this bit by writing 1.
Value
Description
0
No change to Overcurrent Active.
1
Changes to Overcurrent Active.
Bit 4 – OCA Overcurrent Active
This bit will automatically transition from 1 to 0 when the overcurrent condition is removed.
Value
Description
0
This port does not have an overcurrent condition.
1
This port currently has an overcurrent condition.
Bit 3 – PEDC Port Enable/Disable Change (Cleared on write)
For the root hub, this bit gets set to 1 only when a port is disabled due to the appropriate conditions existing at the
EOF2 point (refer to Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by
writing a 1 to it.
This field is 0 if Port Power bit is 0.
© 2020 Microchip Technology Inc.
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SAM9X60
USB Host High Speed Port (UHPHS)
Value
0
1
Description
No change in port enabled/disabled status.
Port enabled/disabled status has changed.
Bit 2 – PED Port Enabled/Disabled
Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by
writing a 1 to this field. The host controller will only set this bit to 1 when the reset sequence determines that the
attached device is a high-speed device.
Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note
that the bit status does not change until the port state actually changes. There may be a delay in disabling or
enabling a port due to other host controller and bus events.
When the port is disabled (0b), downstream propagation of data is blocked on this port, except for reset.
This field is 0 if Port Power bit is 0.
Value
Description
0
Disable.
1
Enable.
Bit 1 – CSC Connect Status Change (Cleared on write)
Indicates a change has occurred in the port’s Current Connect Status. The host controller sets this bit for all changes
to the port device connect status, even if system software has not cleared an existing connect status change. For
example, the insertion status changes twice before system software has cleared the changed condition, hub
hardware will be “setting” an already-set bit (i.e., the bit remains set). Software sets this bit to 0 by writing a 1 to it.
This field is 0 if Port Power bit is 0.
Value
Description
0
No change.
1
Change in Current Connect Status.
Bit 0 – CCS Current Connect Status
This value reflects the current state of the port, and may not correspond directly to the event that caused the CSC bit
to be 1.
This bit is 0 if Port Power is 0.
Value
Description
0
No device is present.
1
Device is present on port.
© 2020 Microchip Technology Inc.
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SAM9X60
USB Host High Speed Port (UHPHS)
42.7.12 EHCI: REG06 - AHB Error Status
Name:
Offset:
Reset:
Property:
UHPHS_INSNREG06
0xA8
0x00000000
Read/Write
Control and Status Register, used to read the UTMI registers from the signals below.
Bit
Access
Reset
Bit
31
AHB_ERR
R/W
0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
HBURST[2:0]
R
0
9
8
Nb_Burst[4]
R
0
Access
Reset
Bit
Access
Reset
Bit
R
0
7
6
5
4
3
R
0
R
0
R
0
Nb_Burst[3:0]
Access
Reset
R
0
R
0
R
0
2
1
Nb_Success_Burst[3:0]
R
R
0
0
0
R
0
Bit 31 – AHB_ERR AHB Error
System bus error was encountered and erroneous burst characteristics are captured. To clear this field the
application must write a 0.
EHCI:
• When no error, 0 is written to INSNREG06[8:4].
• When INCR4 and an error occurs, 4 is written to INSNREG06[8:4].
• When INCR8 and an error occurs, 8 is written to INSNREG06[8:4].
• When INCR16 and an error occurs, 16 is written to INSNREG06[8:4].
• Other values except 4, 8, and 16 are not written to INSNREG06[8:4].
OHCI:
• When no error, 0 is written to INSNREG06[8:4].
• When INCR4 and error occurs, 4 is written to INSNREG06[8:4].
• Other values except 4 are not written to INSNREG06[8:4].
Bits 11:9 – HBURST[2:0] Burst Value
Value of the control phase at which the AHB error occurred.
This field applies to enabled incremental bursts only.
Bits 8:4 – Nb_Burst[4:0] Number of Bursts
Number of beats expected in the burst at which the AHB error occurred. Valid values are 0 to 16.
This field applies to enabled incremental bursts only.
Bits 3:0 – Nb_Success_Burst[3:0] Number of Successful Bursts
Number of successfully completed beats in the current burst before the AHB error occurred.
This field applies to enabled incremental bursts only.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
USB Host High Speed Port (UHPHS)
42.7.13 EHCI: REG07 - AHB Master Error Address
Name:
Offset:
Reset:
Property:
UHPHS_INSNREG07
0xAC
0x00000000
Read-only
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
28
27
AHB_ADDR[31:24]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
AHB_ADDR[23:16]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
AHB_ADDR[15:8]
R
R
0
0
10
9
8
R
0
R
0
R
0
4
3
AHB_ADDR[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 31:0 – AHB_ADDR[31:0] AHB Address
System bus address of the control phase at which the system bus error occurred.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Audio Class D Amplifier (CLASSD)
43.
43.1
Audio Class D Amplifier (CLASSD)
Description
The Audio Class D Amplifier (CLASSD) is a digital input, Pulse Width Modulated (PWM) output stereo Class D
amplifier. It features a high-quality interpolation filter embedding a digitally-controlled gain, an equalizer and a deemphasis filter.
On its input side, the CLASSD is compatible with most common audio data rates. On the output side, its PWM output
can drive either:
•
•
high-impedance single-ended or differential output loads (Audio DAC application) or,
external MOSFETs through an integrated non-overlapping circuit (Class D power amplifier application).
Note:
• CLASSD is stereo but depending on the available I/O at the product level, only one (right or left) channel may be
accessed. Refer to the product pin description table.
43.2
Embedded Characteristics
•
•
•
•
•
•
•
•
•
•
PWM Class D Amplifier
16-bit Audio Data
DSP Clocks: 12.288 and 11.2896 MHz
Input Sampling Rates: 8, 16, 32, 48, 96, 22.05, 44.1, 88.2 kHz
3-band Equalizer
De-emphasis Filter
Digital Volume Control
Differential or Single-ended Outputs
Non-overlapping Circuit to Control External MOSFETs
Supports DMA
© 2020 Microchip Technology Inc.
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SAM9X60
Audio Class D Amplifier (CLASSD)
43.3
Block Diagram
Figure 43-1. CLASSD Block Diagram
GCLK
CLASSD
/8
DSP Clock (DSPCLK)
CLASSD_L0
dB
Equalization
DMA
RDATA
Interpolation
LDATA
trigger
event
PWM
nonoverlap
CLASSD_L1
CLASSD_L2
0
Attenuator
dB
Signal
Routing
CLASSD_L3
PIO
PWM
CLASSD_R0
CLASSD_R1
CLASSD_R2
CLASSD_R3
nonoverlap
0
See Note below.
EQCFG
SWAP
MONO
FRAME
ATTL
CLKSEL
ATTR
NON_OVERLAP
NOVRVAL
LMUTE
MONOMODE
Bridge
PWMTYP
RMUTE
User Interface + Control Logic
Peripheral Clock
Bus Clock
PMC
Note:
CLASSD is stereo but depending on the available I/O at the product level, only one (right or left) channel may be accessed.
Refer to the product pin description table.
43.4
Pin Name List
Table 43-1. Output Pins Assignment Versus Application Use Cases
External MOS Driver (NON_OVERLAP = 1)
Pin
Direct Load (NON_OVERLAP = 0)
Full H-Bridge
(PWMTYP = 1)
Half H-Bridge
(PWMTYP = 0)
Differential Load
(PWMTYP = 1)
Single-Ended Load
(PWMTYP = 0)
Use Case
1
Use Case
2
Use Cases
3A & 3B
Use Cases
4A & 4B
Type
CLASSD_L0
gate_pmos_leftp
gate_pmos_left
leftp
left
Output
CLASSD_L1
gate_nmos_leftp
gate_nmos_left
Not used (fixed to 0)
Not used (fixed to 0)
Output
CLASSD_L2
gate_pmos_leftn
Not used (fixed to 1)
leftn
Not used (fixed to 0)
Output
CLASSD_L3
gate_nmos_leftn
Not used (fixed to 1)
Not used (fixed to 0)
Not used (fixed to 0)
Output
CLASSD_R0
gate_pmos_rightp
gate_pmos_right
rightp
right
Output
CLASSD_R1
gate_nmos_rightp
gate_nmos_right
Not used (fixed to 0)
Not used (fixed to 0)
Output
CLASSD_R2
gate_pmos_rightn
Not used (fixed to 1)
rightn
Not used (fixed to 0)
Output
CLASSD_R3
gate_nmos_rightn
Not used (fixed to 1)
Not used (fixed to 0)
Not used (fixed to 0)
Output
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SAM9X60
Audio Class D Amplifier (CLASSD)
43.5
Product Dependencies
43.5.1
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer
must first program the PIO controllers to assign the CLASSD pins to their peripheral functions.
43.5.2
Power Management
The CLASSD is clocked through the Power Management Controller (PMC), thus the programmer must first configure
the PMC to enable the CLASSD Peripheral Clock and provide a generic clock (GCLK).
The fields NOVRVAL, NON_OVERLAP and PWMTYP in CLASSD_MR, and DSPCLKFREQ and FREQ in
CLASSD_INTPMR, must be configured prior to applying the GCLK.
43.5.3
Interrupt
The CLASSD has an interrupt line connected to the interrupt controller. Handling the CLASSD interrupt requires
programming the interrupt controller before configuring the CLASSD.
43.6
Functional Description
43.6.1
Interpolator
43.6.1.1 Clock Configuration
The interpolator accepts input sampling frequencies (fs) and the input DSP clock (DSPCLK) that can be configured in
the CLASSD Interpolator Mode Register. GCLK must be configured in the PMC according to the desired DSPCLK so
that DSPCLK = GCLK / 8.
The following table provides authorized DSPCLK / fs ratios and associated filter types.
Table 43-2. Authorized DSPCLK / fs Ratios & Filter Types
fs
DSPCLK
12.288 MHz
11.2896 MHz
8 kHz
2
–
16 kHz
2
–
32 kHz
2
–
48 kHz
1
–
96 kHz
3
–
22.05 kHz
–
1
44.1 kHz
–
1
88.2 kHz
–
3
Note: Each dash (–) indicates a configuration that is not authorized and that raises the CFGERR flag in
CLASSD_INTSR.
43.6.1.2 CLASSD Frequency Response
Interpolation is performed with a combination of Infinite Impulse Response (IIR) and Cascaded Integrator-Comb
(CIC) filters. Given the input configuration, the coefficients of the filters are redefined to optimize their transfer
function to optimize the audio bandwidth. The different types of filters are defined in section Clock Configuration.
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SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-2. Type 1 Frequency Response
dB
dB
Overall
fs
fs
Ripple
Figure 43-3. Type 2 Frequency Response
dB
dB
Overall
fs
fs
Ripple
Figure 43-4. Type 3 Frequency Response
dB
dB
Overall
43.6.2
fs
fs
Ripple
Equalizer
The CLASSD offers 12 pre-programmed equalization filters.
A zero-cross detection system is used to modify the equalizer on-the-fly with minimum disturbance on the output
signal.
Programming of the equalization filter is detailed in section CLASSD Interpolator Mode Register.
The following figures show the frequency response of the equalizer function implemented in the D/A channels.
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Complete Datasheet
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SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-5. Bass Filters Response
dB
fs
Figure 43-6. Medium Filters Response
dB
fs
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SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-7. Treble Filters Response
dB
fs
De-emphasis Filter Frequency Response
The CLASSD includes a de-emphasis filter which can be enabled for 32, 44.1 or 48 kHz sampling frequencies.
The response and the error generated by the digital approximation of the filter are illustrated in the following figures.
Figure 43-8. De-emphasis Filter: Frequency Response & Error (fs = 32 kHz)
Error
Response (dB)
Response (dB)
Response
Frequency (Hz)
Frequency (Hz)
Figure 43-9. De-emphasis Filter: Frequency Response & Error (fs = 44.1 kHz)
Error
Response (dB)
Response
Response (dB)
43.6.3
Frequency (Hz)
© 2020 Microchip Technology Inc.
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SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-10. De-emphasis Filter: Frequency Response & Error (fs = 48 kHz)
Response (dB)
Error
Response (dB)
Response
Frequency (Hz)
43.6.4
Frequency (Hz)
Attenuator and Recommended Input Levels
The CLASSD features a digital attenuator with an attenuation range of 0–77 dB and a step size of 1 dB. When
attenuation greater than 77 dB is programmed, the attenuator mutes the channel.
To avoid saturations in the PWM stage, it is recommended to avoid input levels greater than 1 dB below the digital full
scale (-1 dBFS). This can done by programming a minimum attenuation of 1 dB.
43.6.5
Pulse Width Modulator (PWM)
The CLASSD Pulse Width Modulator generates fixed frequency pulse width modulated output signals. For the 44.1
kS/s and 48 kS/s standard audio sample rates, the PWM output frequency is set to 16 × fs: 705.6 kHz and 768 kHz
respectively. For 8, 16, 24 and 96 kS/s, the 16× (interpolation) ratio is adapted to keep the output frequency at 768
kHz. In the same way, the output frequency is 705.6 kHz for the 22.05 and 88.2 kS/s cases.
The CLASSD functions either as a DAC loaded by a medium-to-high resistive load (e.g., 1 kΩ to 100 kΩ) or as a
Class D power amplifier controller driving an external power stage. Depending on the value of
CLASSD_MR.NON_OVERLAP, the CLASSD drives:
•
•
Single-ended or differential resistive loads (NON_OVERLAP = 0)
Full or Half MOSFET H-bridges (NON_OVERLAP = 1)
When driving an external power stage (NON_OVERLAP = 1), the CLASSD generates the signals to control
complementary MOSFET pairs (PMOS and NMOS) with a non-overlapping delay between the NMOS and PMOS
controls to avoid short circuit current. The non-overlapping delay can be adjusted in the CLASSD_MR.NOVRVAL
field.
The CLASSD can have a single-ended or a differential output. A specific pulse width modulation type is associated to
each case. For single-ended output (CLASSD_MR.PWMTYP = 0), the PWM acts only on the falling edge of the
PWM waveform (trailing edge PWM). For differential output (CLASSD_MR.PWMTYP = 1), both the rising and the
falling edges of the PWM waveform are modulated (symmetric PWM). Modulation principles are illustrated in the
following figures for both types of PWM. In particular, when describing a null input, if PWMTYP = 0 (trailing edge
PWM), the output waveform is a square wave with 50% duty cycle. With the same input and PWMTYP = 1, the
differential output waveform is zero. This difference removes the classical L-C low-pass filter when PWMTYP = 1.
Figure 43-11. Output Waveform Modulation Principle for PWMTYP = 0
PWM
Output
VDD
CLASSD_L0
0
time
1/fPWM
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Complete Datasheet
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SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-12. Output Waveform Modulation Principle for PWMTYP = 1 (Only Left Channel Pins Shown)
PWM
Outputs
VDD
CLASSD_L0
0
VDD
CLASSD_L2
0
VDD
CLASSD_L0
- CLASSD_L2
0
1/fPWM
-VDD
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SAM9X60
Audio Class D Amplifier (CLASSD)
43.6.6
Application Schematics For Use Case Examples
Figure 43-13. Use Case 1: Stereo Class D Amplifier With External Differential Power Stage
VDDHV (> VDDIO)
D1
R9
CLASSD_L0
R1
C5
GND
C1
CLASSD_L1
leftp
Q1
R2
LEFT CHANNEL
R10
VDDHV (> VDDIO)
CLASSD_L2
SPEAKER
LEFT
D2
GND
R11
R3
CLASSD_L3
C2
Q2
leftn
VDDIO
CLASSD
VDDIO
R4
C7
R12
GND
VDDHV (> VDDIO)
GND
D3
R13
CLASSD_R0
R5
C6
GND
C3
CLASSD_R1
rightp
Q3
RIGHT CHANNEL
R6
R14
VDDHV (> VDDIO)
CLASSD_R2
SPEAKER
RIGHT
D4
GND
R15
R7
CLASSD_R3
C4
Q4
rightn
Use case example:
R8
R16
D1..D4 = e.g., 1N4148
Q1..Q4 = e.g., DMC2400UV
R1..R8 = 10 ohm
R9..R16 = 10 kohm
C1..C4 = 10 nF
C5..C6 = 10 µF
C7 = 1 µF
© 2020 Microchip Technology Inc.
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SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-14. Use Case 1: Waveforms
CLASSD_MR.PWMTYP = 1, CLASSD_MR.NON_OVERLAP = 1
CLASSD_MR.NOVRVAL = 0
GCLK
CLASSD_L0
CLASSD_L1
CLASSD_L2
CLASSD_L3
NOVRVAL = 0
PWM period
CLASSD_MR.NOVRVAL = 3
GCLK
CLASSD_L0
CLASSD_L1
CLASSD_L2
CLASSD_L3
NOVRVAL = 3
PWM period
In Use Case 1, the external power stages are made of complementary low-cost MOSFETs. In addition to the RDSON
and drain breakdown voltage characteristics, the choice of these components is driven by a low gate threshold
voltage, a low input capacitance, a low total gate charge and a fast turn-on time characteristics. Series resistance (10
Ω) added to the gates of the MOSFETs are optional and may be adjusted to optimize the gate drive. They help to limit
the output current peaks driven by the I/Os into the MOSFET gates in some cases. The 10k resistors ensure an OFF
condition when not driven and the capacitor / diode network (C1..C2 / D1..D2) shifts the PMOS drive from the typical
VDDIO level (3.3V) to a higher supply voltage (e.g., a 5V power domain).
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SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-15. Use Case 2: Stereo Class D Amplifier With External Single-ended Power Stage
VDDHV (> VDDIO)
D1
C3
R5
CLASSD_L0
R1
GND
C1
LF
CLASSD_L1
Q1
LEFT CHANNEL
CC
CF
R2
VDDIO
left
R6
VDDIO
C4
CLASSD
GND
GND
GND
VDDHV (> VDDIO)
D2
R7
CLASSD_R0
CLASSD_R1
R3
C2
LF
Q2
RIGHT CHANNEL
CC
CF
R4
Use case example:
D1..D2 = e.g., 1N4148
Q1..Q2 = e.g., DMC2400UV
R1..R4 = 10 ohm
R5..R8 = 10 kohm
C1..C2 = 10 nF
C3 = 10 µF
C4 = 1 µF
right
R8
GND
GND
In the Use Case 2 application schematic, the drive network of the MOSFETs gates follows the principles described in
Use Case 1.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1212
SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-16. Use Case 2: Waveforms
CLASSD_MR.PWMTYP = 0, CLASSD_MR.NON_OVERLAP = 1
CLASSD_MR.NOVRVAL = 0
GCLK
CLASSD_L0
CLASSD_L1
NOVRVAL = 0
PWM period
CLASSD_MR.NOVRVAL = 3
GCLK
CLASSD_L0
CLASSD_L1
NOVRVAL = 3
A coupling capacitor (CC) and an L-C low-pass filter (LF, CF) are added to the output of the power stage to remove
both the DC and the high frequency components of the PWM signal. CC with the resistive part of the speaker (RSPK)
forms a C-R high pass filter with a corner frequency of fHP = 1 / (2 × PI × CC × RSPK).
LF, CF and RSPK form a second-order low-pass filter of corner frequency fC = 1 / (2 × PI × sqrt (LF × CF)) and of
quality factor Q = RSPK × sqrt (CF / LF). As a numerical example, consider the case fHP = 200 Hz, fC = 30 kHz, Q =
0.707 (maximum flat response) with RSPK = 8 Ω. This leads to CC = 100 µF, LF = 60 µH, CF = 470 nF.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1213
SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-17. Use Case 3A: Stereo Audio DAC With Active Differential-to-Single Low-Pass Filter
9.31k
470pF
4.7µF
649
8.66k
12.4k
AVDD (> VDDIO)
1nF
CLASSD_L0
4.7nF
1nF
4.7µF
100
4.7µF
IC1
10nF
CLASSD_L2
-
4.7nF
+
100k
10nF
LEFT CHANNEL
649
8.66k
left
12.4k
9.31k
470pF
CLASSD
AVDD/2
VDDIO
VDDIO
9.31k
1µF
GND
470pF
4.7µF
649
8.66k
12.4k
AVDD (> VDDIO)
1nF
CLASSD_R0
4.7nF
4.7nF
1nF
4.7µF
100
IC2
10nF
CLASSD_R2
-
649
8.66k
right
+
10nF
RIGHT CHANNEL
4.7µF
100k
12.4k
9.31k
470 pF
Use case example:
AVDD/2
IC1..IC2 = e.g., 1/2 LMV356
Figure 43-18. Use Case 3B: Stereo Audio DAC With Simple Passive Low-Pass Filter and Differential Outputs
4.7µF
CLASSD_L0
CLASSD_L2
4.7µF
4.7µF
CLASSD_R0
100k
1nF
100k
649
leftn
649
rightp
1nF
100k
1nF
100k
4.7nF
CLASSD_R2
4.7µF
RIGHT CHANNEL
649
© 2020 Microchip Technology Inc.
1nF
4.7nF
LEFT CHANNEL
CLASSD
leftp
649
Complete Datasheet
rightn
DS60001579C-page 1214
SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-19. Use Cases 3A and 3B: Waveforms
CLASSD_MR.PWMTYP = 1, CLASSD_MR.NON_OVERLAP = 0
DSPCLK
CLASSD_L0
CLASSD_L2
PWM period
In Use Case 3A, the CLASSD is used as an audio DAC. In this case, the differential outputs of the CLASSD are
used. The application schematic suggested in figure "Use Case 3A: Stereo Audio DAC With Active differential to
Single Low-Pass Filter" above implements a third order 10 kHz low-pass Butterworth filter and makes the differential
to single-ended conversion. Note that in this schematic, the AVDD/2 point needs to be fed at low impedance (e.g., a
buffered voltage). A simpler schematic (Use Case 3B) may also be possible, as shown in figure "Use Case 3B:
Stereo Audio DAC With Simple Passive Low-Pass Filter and Differential Outputs" above, at the cost of higher out-ofband noise and differential outputs which may be acceptable in some applications.
Figure 43-20. Use Case 4A: Stereo Audio DAC With Active Low-Pass Filter and Single-ended Outputs
10k
220pF
4.7µF
909
9.09k
13k
CLASSD_L0
AVDD (> VDDIO)
-
LEFT CHANNEL
10nF
AVDD/2
CLASSD
100
left
+
10nF
VDDIO
VDDIO
4.7µF
IC1
2.2nF
100k
10k
1µF
GND
220pF
4.7µF
909
9.09k
13k
CLASSD_R0
LEFT CHANNEL
AVDD (> VDDIO)
10nF
100
IC2
2.2nF
AVDD/2
4.7µF
right
+
10nF
100k
Use case example:
IC1..IC2 = e.g., 1/2 LMV356
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1215
SAM9X60
Audio Class D Amplifier (CLASSD)
Figure 43-21. Use Case 4B: Stereo Audio DAC With Passive Low-Pass Filter and Single-ended Outputs
4.7 µF
820
left
CLASSD_L0
LEFT CHANNEL
10 nF
100k
10 nF
100k
CLASSD
CLASSD_R0
4.7 µF
RIGHT CHANNEL
820
right
Figure 43-22. Use Cases 4A and 4B: Waveforms
CLASSD_MR.PWMTYP = 0, CLASSD_MR.NON_OVERLAP = 0
DSPCLK
CLASSD_L0
PWM period
In Use Case 4A, the CLASSD is used as an audio DAC with active low-pass filter. In this case, the single-ended
outputs of the CLASSD are selected (PWMTYP = 0, trailing edge PWM) which leaves more I/Os to the application. A
third-order 30 kHz low-pass Butterworth filter is shown in figure "Use Case 4A: Stereo Audio DAC With Active LowPass Filter and Single-ended Outputs". The AVDD/2 point can be fed at relatively high impedance as no current is
drawn from this point (a simple resistive divider properly decoupled is acceptable). A reduced complexity schematic is
presented in figure "Use Case 4B: Stereo Audio DAC With Passive Low-Pass Filter and Single-ended Outputs"
above for less constrained applications.
43.6.7
Register Write Protection
To prevent any single software error from corrupting CLASSD behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the CLASSD Write Protection Mode Register (CLASSD_WPMR).
The following registers can be write-protected:
•
•
CLASSD Mode Register
CLASSD Interpolator Mode Register
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1216
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7
Register Summary
Offset
Name
0x00
CLASSD_CR
0x04
CLASSD_MR
Bit Pos.
7
0x0C
CLASSD_INTPMR
CLASSD_INTSR
0x10
CLASSD_THR
0x14
CLASSD_IER
0x18
0x1C
0x20
0x24
...
0xE3
0xE4
CLASSD_IDR
CLASSD_IMR
CLASSD_ISR
5
4
3
2
1
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
0x08
6
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
0
SWRST
NOVRVAL[1:0]
RMUTE
MONOMODE[1:0]
REN
MONO
LMUTE
EQCFG[3:0]
FRAME[2:0]
SWAP
DEEMP
NON_OVERL
AP
PWMTYP
LEN
DSPCLKFRE
Q
ATTR[6:0]
ATTL[6:0]
CFGERR
RDATA[15:8]
RDATA[7:0]
LDATA[15:8]
LDATA[7:0]
DATRDY
DATRDY
DATRDY
DATRDY
Reserved
CLASSD_WPMR
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WPEN
Complete Datasheet
DS60001579C-page 1217
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.1
CLASSD Control Register
Name:
Offset:
Reset:
Property:
Bit
CLASSD_CR
0x00
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SWRST
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – SWRST Software Reset
Value
Description
0
No effect.
1
Resets CLASSD, simulating a hardware reset.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1218
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.2
CLASSD Mode Register
Name:
Offset:
Reset:
Property:
CLASSD_MR
0x04
0x00010022
Read/Write
This register can only be written if the WPEN bit is cleared in the CLASSD Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
NOVRVAL[1:0]
19
18
17
16
NON_OVERLA
P
R/W
1
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
15
14
13
12
11
10
9
8
PWMTYP
R/W
0
7
6
5
RMUTE
R/W
1
4
REN
R/W
0
3
2
1
LMUTE
R/W
1
0
LEN
R/W
0
Access
Reset
Bit
Access
Reset
Bits 21:20 – NOVRVAL[1:0] Non-Overlapping Value
This field has no effect when NON_OVERLAP = 0.
Value
Name
Description
0
5NS
Non-overlapping time is 5 ns
1
10NS
Non-overlapping time is 10 ns
2
15NS
Non-overlapping time is 15 ns
3
20NS
Non-overlapping time is 20 ns
Bit 16 – NON_OVERLAP Non-Overlapping Enable
Value
Description
0
Non-overlapping circuit is disabled.
1
Non-overlapping circuit is enabled.
Bit 8 – PWMTYP PWM Modulation Type
0 (TRAILING_EDGE): The signal is single-ended.
If NON_OVERLAP is cleared, the signal is sent to CLASSD_L0 and CLASSD_R0 (see figure Use Case 4A or figure
Use Case 4B).
If NON_OVERLAP is set, the signal is sent to CLASSD_L0/L1 and CLASSD_R0/R1 (see figure Use Case 2).
1 (UNIFORM): The signal is differential.
If NON_OVERLAP is cleared, the signal is sent to CLASSD_L0/L2 and CLASSD_R0/R2 (see figure Use Case 3A or
figure Use Case 3B).
If NON_OVERLAP is set, the signal is sent to CLASSD_L0/L1/L2/L3 and CLASSD_R0/R1/R2/R3 (see figure Use
Case 1).
Bit 5 – RMUTE Right Channel Mute
Value
Description
0
Right channel is unmuted.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1219
SAM9X60
Audio Class D Amplifier (CLASSD)
Value
1
Description
Right channel is muted.
Bit 4 – REN Right Channel Enable
Value
Description
0
Right channel is disabled.
1
Right channel is enabled.
Bit 1 – LMUTE Left Channel Mute
Value
Description
0
Left channel is unmuted.
1
Left channel is muted.
Bit 0 – LEN Left Channel Enable
Value
Description
0
Left channel is disabled.
1
Left channel is enabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1220
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.3
CLASSD Interpolator Mode Register
Name:
Offset:
Reset:
Property:
CLASSD_INTPMR
0x08
0x00304E4E
Read/Write
This register can only be written if the WPEN bit is cleared in the CLASSD Write Protection Mode Register.
Bit
31
Access
Reset
Bit
23
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
30
29
MONOMODE[1:0]
R/W
R/W
0
0
22
28
MONO
R/W
0
R/W
0
21
FRAME[2:0]
R/W
1
20
R/W
1
14
13
12
R/W
1
R/W
0
R/W
0
6
5
4
R/W
1
R/W
0
R/W
0
27
R/W
0
26
25
EQCFG[3:0]
R/W
R/W
0
0
24
R/W
0
19
SWAP
R/W
0
18
DEEMP
R/W
0
17
16
DSPCLKFREQ
R/W
0
11
ATTR[6:0]
R/W
1
10
9
8
R/W
1
R/W
1
R/W
0
2
1
0
R/W
1
R/W
1
R/W
0
3
ATTL[6:0]
R/W
1
Bits 30:29 – MONOMODE[1:0] Mono Mode Selection
Defines which signal is sent to both channels when the MONO bit is set.
Value
Name
Description
0
MONOMIX
(left + right) / 2 is sent to both channels
1
MONOSAT
(left + right) is sent to both channels. If the sum is too high, the result is saturated.
2
MONOLEFT
THR[15:0] is sent to both the left and the right channels
3
MONORIGHT THR[31:16] is sent to both the left and the right channels
Bit 28 – MONO Mono Signal
0 (DISABLED): The signal is sent stereo to the left and right channels.
1 (ENABLED): The same signal is sent to both the left and the right channels. The sent signal is defined by the
MONOMODE field value.
Bits 27:24 – EQCFG[3:0] Equalization Selection
EQCFG field values 13–15 = flat response
Value
Name
0
FLAT
1
BBOOST12
2
BBOOST6
3
BCUT12
4
BCUT6
5
MBOOST3
6
MBOOST8
7
MCUT3
8
MCUT8
9
TBOOST12
10
TBOOST6
11
TCUT12
© 2020 Microchip Technology Inc.
Description
Flat response
Bass boost +12 dB
Bass boost +6 dB
Bass cut -12 dB
Bass cut -6 dB
Medium boost +3 dB
Medium boost +8 dB
Medium cut -3 dB
Medium cut -8 dB
Treble boost +12 dB
Treble boost +6 dB
Treble cut -12 dB
Complete Datasheet
DS60001579C-page 1221
SAM9X60
Audio Class D Amplifier (CLASSD)
Value
12
Name
TCUT6
Description
Treble cut -6 dB
Bits 22:20 – FRAME[2:0] CLASSD Incoming Data Sampling Frequency
Value
Name
Description
0
FRAME_8K
8 kHz
1
FRAME_16K
16 kHz
2
FRAME_32K
32 kHz
3
FRAME_48K
48 kHz
4
FRAME_96K
96 kHz
5
FRAME_22K
22.05 kHz
6
FRAME_44K
44.1 kHz
7
FRAME_88K
88.2 kHz
Bit 19 – SWAP Swap Left and Right Channels
0 (LEFT_ON_LSB): Left channel is on CLASSD_THR[15:0], right channel is on CLASSD_THR[31:16].
1 (RIGHT_ON_LSB): Right channel is on CLASSD_THR[15:0], left channel is on CLASSD_THR[31:16].
Bit 18 – DEEMP Enable De-emphasis Filter
0 (DISABLED): De-emphasis filter is disabled.
1 (ENABLED): De-emphasis filter is enabled.
Bit 16 – DSPCLKFREQ DSP Clock Frequency
0 (12M288): DSP Clock (DSPCLK) is 12.288 MHz.
1 (11M2896): DSP Clock (DSPCLK) is 11.2896 MHz.
Bits 14:8 – ATTR[6:0] Right Channel Attenuation
Right channel attenuation is defined as follows:
– if ATTR ≤ 77 the attenuation is -ATTR dB
– else the right signal is muted
Bits 6:0 – ATTL[6:0] Left Channel Attenuation
Left channel attenuation is defined as follows:
– if ATTL ≤ 77 the attenuation is -ATTL dB
– else the left signal is muted
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1222
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.4
CLASSD Interpolator Status Register
Name:
Offset:
Reset:
Property:
Bit
CLASSD_INTSR
0x0C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFGERR
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – CFGERR Configuration Error
Value
Description
0
The frame and clock configurations are correct.
1
The frame and clock configurations are incorrect (see Clock Configuration for information about
allowed configurations).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1223
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.5
CLASSD Transmit Holding Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
CLASSD_THR
0x10
0x00000000
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
28
27
RDATA[15:8]
R/W
R/W
0
0
20
26
25
24
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
RDATA[7:0]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
R/W
0
R/W
0
R/W
0
7
6
5
11
LDATA[15:8]
R/W
R/W
0
0
4
LDATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:16 – RDATA[15:0] Right Channel Data
Bits 15:0 – LDATA[15:0] Left Channel Data
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1224
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.6
CLASSD Interrupt Enable Register
Name:
Offset:
Reset:
Property:
Bit
CLASSD_IER
0x14
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATRDY
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – DATRDY Data Ready
Value
Description
0
No effect.
1
Enables the interrupt when CLASSD is ready to receive new data to convert.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1225
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.7
CLASSD Interrupt Disable Register
Name:
Offset:
Reset:
Property:
Bit
CLASSD_IDR
0x18
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATRDY
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – DATRDY Data Ready
Value
Description
0
No effect.
1
Disables the interrupt when CLASSD is ready to receive new data to convert.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1226
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.8
CLASSD Interrupt Mask Register
Name:
Offset:
Reset:
Property:
Bit
CLASSD_IMR
0x1C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATRDY
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – DATRDY Data Ready
Value
Description
0
The interrupt is disabled.
1
The interrupt is enabled.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1227
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.9
CLASSD Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
CLASSD_ISR
0x20
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATRDY
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – DATRDY Data Ready
Value
Description
0
CLASSD has not been ready to convert a value since the last read of CLASSD_ISR.
1
CLASSD has been ready to convert a value since the last read of CLASSD_ISR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1228
SAM9X60
Audio Class D Amplifier (CLASSD)
43.7.10 CLASSD Write Protection Mode Register
Name:
Offset:
Reset:
Property:
CLASSD_WPMR
0xE4
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x434C44 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
Bit 0 – WPEN Write Protection Enable
See Register Write Protection for the list of registers that can be write-protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x434C44 (“CLD” in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x434C44 (“CLD” in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1229
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.
44.1
Inter-IC Sound Multi-Channel Controller (I2SMCC)
Description
The Inter-IC Sound Controller (I2SMCC) provides a 5-wire, bidirectional, synchronous, digital audio link to external
audio devices: I2SMCC_DIN, I2SMCC_DOUT, I2SMCC_WS, I2SMCC_CK, and I2SMCC_MCK pins.
The I2SMCC complies with the Inter-IC Sound (I2S) bus specification and supports a Time Division Multiplexed
(TDM) interface with external multi-channel audio codecs.
The I2SMCC consists of a receiver, a transmitter and a common clock generator that can be enabled separately to
provide Master, Slave or Controller modes with receiver and/or transmitter active.
DMA Controller channels, separate for the receiver and for the transmitter, allow a continuous high bit rate data
transfer without processor intervention to the following:
•
•
•
Audio CODECs in Master, Slave, or Controller mode
Stereo DAC or ADC through a dedicated I2S serial interface
Multi-channel or multiple stereo DACs or ADCs, using the TDM format
The I2SMCC uses a single DMA Controller channel for all audio channels.
The 8- and 16-bit compact stereo formats reduce the required DMA Controller bandwidth by transferring the left and
right samples within the same data word.
In Master mode, the I2SMCC can produce a 16 fs to 1024 fs master clock that provides an over-sampling clock to an
external audio codec or digital signal processor (DSP).
44.2
Embedded Characteristics
•
•
•
•
•
•
•
•
Compliant with Inter-IC Sound (I2S) Bus Specification
Master, Slave, and Controller Modes
– Slave: Data Received/Transmitted
– Master: Data Received/Transmitted And Clocks Generated
– Controller: Clocks Generated
Individual Enable and Disable of Receiver, Transmitter and Clocks
Configurable Clock Generator Common to Receiver and Transmitter
– Suitable for a Wide Range of Sample Frequencies (fs), Including 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96
kHz, and 192 kHz
– 16 fs to 1024 fs Master Clock Generated for External Oversampling Data Converters
Support for Multiple Data Formats
– 32-, 24-, 20-, 18-, 16-, and 8-bit Mono or Stereo Format
– 16- and 8-bit Compact Stereo Format, with Left and Right Samples Packed in the Same Word to Reduce
Data Transfers
Support for Multiple Data Frame Formats
– 2-channel I2S with Word Select
– 1- to 8-channel Time Division Multiplexed (TDM) with Frame Synchronization
DMA Controller Interfaces the Receiver and Transmitter to Reduce Processor Overhead
Smart Holding Registers Management to Avoid Audio Channel Mix After Overrun or Underrun
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1230
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.3
Block Diagram
Figure 44-1. I2SMCC Block Diagram
I2SMCC
Power
Managment
Controller
GCLKx
Peripheral
Clock
PIO
I2SMCC_MCK
I2SMCC_CK
Clocks
I2SMCC_WS
Peripheral
Bus Bridge
DMA
Controller
Bus
Interface
Interrupt
Controller
44.4
Receiver
I2SMCC_DIN
Events
I2SMCC_DOUT
Transmitter
I/O Lines Description
Table 44-1. I/O Lines Description
44.5
Pin Name
Pin Description
Type
I2SMCC_MCK
Master Clock
Output
I2SMCC_CK
Serial Clock
Input/Output
I2SMCC_WS
I2S
Input/Output
I2SMCC_DIN
Serial Data Input
Input
I2SMCC_DOUT
Serial Data Output
Output
Word Select or TDM Frame Synchronization
Product Dependencies
To use the I2SMCC, other parts of the system must be configured correctly, as described below.
44.5.1
I/O Lines
The I2SMCC pins may be multiplexed with I/O Controller lines. The user must first program the PIO Controller to
assign the required I2SMCC pins to their peripheral function. If the I2SMCC I/O lines are not used by the application,
they can be used for other purposes by the PIO Controller. The user must enable the I2SMCC inputs and outputs that
are used.
44.5.2
Power Management
If the processor enters a Sleep mode that disables clocks used by the I2SMCC, the I2SMCC stops functioning and
resumes operation after the system wakes up from Sleep mode.
44.5.3
Clocks
The I2SMCC runs from the peripheral clock and the generic clock (GCLK), both generated by the Power
Management Controller (PMC). Prior to using the I2SMCC, the user must first program the PMC. The I2S master and
serial clock can be generated either from the peripheral clock or the generic clock.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1231
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
In a similar way, the I2SMCC must be disabled before removing its clock source to avoid freezing it in an undefined
state.
44.5.4
DMA Controller
The I2SMCC interfaces to the DMA Controller. Using the I2SMCC DMA functionality requires the DMA Controller to
be programmed first.
44.5.5
Interrupt Sources
The I2SMCC interrupt line is connected to the Interrupt Controller. Using the I2SMCC interrupt requires the Interrupt
Controller to be programmed first.
44.6
Functional Description
44.6.1
Initialization
The I2SMCC features a receiver, a transmitter and a clock generator for Master and Controller modes. Receiver and
transmitter share the same serial clock and word select.
Before enabling the I2SMCC, the selected configuration must be written to the I2SMCC Mode Register A
(I2SMCC_MRA). If I2SMCC_MRA.FORMAT is configured in one of the TDM formats, then the
I2SMCC_MRA.NBCHAN and I2SMCC_MRA.TDMFS fields must also be written.
Once the I2SMCC_MRA has been written, the I2SMCC clock generator, receiver, and transmitter can be enabled by
writing a ‘1’ to the CKEN, RXEN, and TXEN bits in the Control Register (I2SMCC_CR). The clock generator can be
enabled alone in Controller mode to output clocks to the I2SMCC_MCK, I2SMCC_CK, and I2SMCC_WS pins. The
clock generator must also be enabled if the receiver or the transmitter is enabled.
The clock generator, receiver, and transmitter can be disabled independently by writing a ‘1’ to I2SMCC_CR.CXDIS,
I2SMCC_CR.RXDIS and/or I2SMCC_CR.TXDIS, respectively. Once requested to stop, they stop only when the
transmission of the pending frame transmission is completed.
44.6.2
Basic Operation
The receiver can be operated by reading the Receiver Holding Register (I2SMCC_RHR), whenever the Receive Left
x Ready (RXLRDYx) bit or the Receive Right Ready (RXRRDYx) bit in the Interrupt Status Register A
(I2SMCC_ISRA) is set. Successive values read from I2SMCC_RHR correspond to the samples from the first left
audio channel to the last left audio channel enabled then from the first right audio channel to the last right audio
channel enabled, or from channels 0 to I2SMCC_MRA.NBCHAN in TDM mode for the successive frames.
The transmitter can be operated by writing to the Transmitter Holding Register (I2SMCC_THR), whenever the
Transmit Left x Ready (TXLRDYx) bit or the Transmit Right x Ready (TXRRDYx) bit in the I2SMCC_ISRA is set.
Successive values written to I2SMCC_THR correspond to the samples from the first left audio channel to the last left
audio channel enabled, then from the first right audio channel to the last right audio channel enabled, or from
channels 0 to I2SMCC_MRA.NBCHAN in TDM mode for the successive frames.
The RXLRDYx, RXRRDYx, TXLRDYx and TXRRDYx bits can be polled by reading the I2SMCC_ISRA.
The I2SMCC processor load can be reduced by enabling interrupt-driven operation. The RXLRDYx, RXRRDYx,
TXLRDYx and/or TXRRDYx interrupt requests can be enabled by writing a ‘1’ to the corresponding bit in the Interrupt
Enable Register A (I2SMCC_IERA). The interrupt service routine associated to the I2SMCC interrupt request is
executed when at least one of the RXLRDYx, RXRRDYx, TXLRDYx and TXRRDYx status bits is set.
44.6.3
Master, Controller and Slave Modes
In Master and Controller modes, the I2SMCC provides the master clock, the serial clock and the word select.
I2SMCC_MCK, I2SMCC_CK, and I2SMCC_WS pins are outputs.
In Controller mode, the I2SMCC receiver and transmitter are disabled. Only the clocks are enabled and used by an
external receiver and/or transmitter.
In Slave mode, the I2SMCC receives the serial clock and the word select from an external master. I2SMCC_CK and
I2SMCC_WS pins are inputs.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1232
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
The mode is selected by writing the MODE field in the I2SMCC_MRA. Since the MODE field changes the direction of
the I2SMCC_WS and I2SSCK pins, the I2SMCC_MRA must only be written when the I2SMCC is stopped in order to
avoid unwanted glitches on the I2SMCC_WS and I2SMCC_CK pins.
44.6.4
I2S Reception and Transmission Sequence
As specified in the I2S protocol, data bits are left-justified in the word select time slot, with the MSB transmitted first,
starting one clock period after the transition on the word select line.
Figure 44-2. I2S Reception and Transmission Sequence
Serial clock
I2SMCC_CK
Word Select
I2SMCC_WS
Data
I2SMCC_DIN/
I2SMCC_DOUT
MSB
LSB
Left Channel
MSB
Right Channel
Data bits are sent on the falling edge of the serial clock and sampled on the rising edge of the serial clock. The word
select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing
I2SMCC_MRA.DATALENGTH.
If the time slot allows for more data bits than written in I2SMCC_MRA.DATALENGTH, zeroes are appended to the
transmitted data word or extra received bits are discarded.
The slot length is defined in the following table.
Table 44-2. Slot Length (I2S format)
44.6.5
I2SMCC_MRA.DATALENGTH
Word Length
Slot Length
0
32 bits
32
1
24 bits
2
20 bits
32 if I2SMCC_MRA.IWS = 0
24 if I2SMCC_MRA.IWS = 1
3
18 bits
4
16 bits
5
16 bits compact stereo
6
8 bits
7
8 bits compact stereo
16
8
Left-Justified Reception and Transmission Sequence
As specified in the I2S protocol, data bits are left-justified in the word select time slot, with the MSB transmitted first,
starting at the same clock period as the transition on the word select line.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1233
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
Figure 44-3. Left-Justified Reception and Transmission Sequence
Serial clock
I2SMCC_CK
Word Select
I2SMCC_WS
Data
I2SMCC_DIN/
I2SMCC_DOUT
MSB
LSB
MSB
Left Channel
Right Channel
Data bits are sent on the falling edge of the serial clock and sampled on the rising edge of the serial clock. The word
select line indicates the channel in transmission, a low level for the right channel and a high level for the left channel.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing
I2SMCC_MRA.DATALENGTH.
If the time slot allows for more data bits than written in I2SMCC_MRA.DATALENGTH, zeroes are appended to the
transmitted data word or extra received bits are discarded.
The Slot Length is defined in the following table.
Table 44-3. Slot Length (Left-Justified format)
44.6.6
I2SMCC_MRA.DATALENGTH
Word Length
Slot Length
0
32 bits
32
1
24 bits
2
20 bits
32 if I2SMCC_MRA.IWS = 0
24 if I2SMCC_MRA.IWS = 1
3
18 bits
4
16 bits
5
16 bits compact stereo
6
8 bits
7
8 bits compact stereo
16
8
TDM Reception and Transmission Sequence
In Time Division Multiplexed (TDM) format, one to eight data words are sent or received within each frame. As
specified in the I2S protocol, data bits are left-justified in the channel time slot, with the MSB transmitted first, starting
one clock period after the transition on the word select line. Each time slot is 32 bits long.
Figure 44-4. TDM Reception and Transmission Sequence
Frame Sync
I2SMCC_WS
Serial Clock
I2SMCC_CK
Data
I2SMCC_DIN/
I2SMCC_DOUT
MSB
LSB
Channel 0
MSB
LSB
Channel 1
MSB
LSB
Channel 2
MSB
LSB
Channel 3
I2SMCC_MR.DATALENGTH
32 bits
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1234
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
Data bits are sent on the falling edge of the serial clock and sampled on the rising edge of the serial clock. The
I2SMCC_WS pin provides a frame synchronization signal, starting one I2SMCC_CK period before the MSB of
channel 0.
The TDM format is selected by writing a ’2’ to I2SMCC_MRA.FORMAT.
The Frame Synchronization pulse can be either one I2SMCC_CK period, 16-bit I2SMCC_CK period (half time slot) or
one 32-bit time slot. This selection is done by writing the I2SMCC_MRA.TDMFS bit.
The number of channels is selected by writing the I2SMCC_MRA.NBCHAN field.
The Frame Synchronization pulse set to 32-bit time slot with the number of channel set to 1 configuration is not
supported.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the
I2SMCC_MRA.DATALENGTH field.
If the time slot allows for more data bits than programmed in the I2SMCC_MRA.DATALENGTH field, zeroes are
appended to the transmitted data word or extra received bits are discarded.
44.6.7
Serial Clock and Word Select Generation
The generation of clocks in the I2SMCC is described in the following figure.
In Slave mode, the word select clock is driven by an external master and the serial clock is driven by either an
external master or the internal clock circuitry. I2SMCC_CK and I2SMCC_WS pins are inputs.
In Master mode, the user configures the master clock, serial clock, and word select clock through the I2SMCC_MRA.
I2SMCC_MCK, I2SMCC_CK, and I2SMCC_WS pins are outputs, MCK and SCK frequencies are configured
independently using IMCKDIV and ISCKDIV bits of I2SMCC_MRA, respectively.
If a master clock output is not required, the MCK clock is used as I2SMCC_CK by clearing
I2SMCC_MRA.IMCKMODE.
The I2SMCC_WS pin is used as word select in I2S format and as frame synchronization in TDM format, as described
in I2S Reception and Transmission Sequence and TDM Reception and Transmission Sequence, respectively.
Figure 44-5. I2SMCC Clock Generation
I2SMCC
I2SMCC_CR.CKEN/CKDIS I2SMCC_MRA.IMCKMODE
I2SMCC_MRA.SRCCLK
I2SMCC_MRA.IMCKDIV
Peripheral
Clock
0
Selected Clock
Clock
Divider
Clock
Enable
1
I2SMCC_MCK
PMC.GCLKx
I2SMCC_MRA.ISCKDIV
Clock
Divider
I2SMCC_CK
1
0
I2SMCC_CK_in
I2SMCC_CK_in
Clock
Enable
internal
bit clock
I2SMCC_MRB.CLKSEL
I2SMCC_CR.CKEN/CKDIS
Clock
Divider
I2SMCC_MRA.MODE
I2SMCC_MRA.DATALENGTH
I2SMCC_WS
master
I2SMCC_WS_in
1
0
I2SMCC_WS_in
internal
word clock
slave
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1235
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.6.8
Mono
When the Transmit Mono bit (TXMONO) in I2SMCC_MRA is set, data written to the left channel is duplicated to the
right output channel. In TDM mode, with more than two channels numbered from 0, data written to the evennumbered channels is duplicated to the following odd-numbered channel. When TXMONO is set, TXRRDYx bits of
I2SMCC_ISRA are always read as ‘0’ and the behavior of TXRUNFx bits is unchanged.
When the Receive Mono bit (RXMONO) in I2SMCC_MRA is set, data received from the left channel is duplicated to
the right input channel. In TDM mode, with more than two channels numbered from 0, data received from the evennumbered channels is duplicated to the following odd-numbered channel. When RXMONO is set, the behavior of
RXRRDYx and RXROVFx bits is unchanged.
44.6.9
Holding Registers
The I2SMCC user interface includes two common holding registers—the Receive Holding Register (I2SMCC_RHR)
and the Transmit Holding Register (I2SMCC_THR). The common registers are used to access audio samples for all
audio channels.
Each I2S or TDM channel has its own register. The register depth depending on the configuration is available in the
following table.
Table 44-4. Registers Depth
I2SMCC_MRA.FORMAT
I2SMCC_MRA.NBCHAN
Register Depth
0 or 1
(I2S or LJ)
NA
4 words
0 or 1
4 words
2 or 3
2 words
4, 5, 6 or 7
1 word
2 or 3
(TDM or TDMLJ)
44.6.9.1 Common Registers
The Receiver Holding Register (I2SMCC_RHR) and the Transmitter Holding Register (I2SMCC_THR) provide an
access to all channels enabled through a single location.
When a new data word is available, the corresponding RXLRDYx bit or RXRRDYx bit in I2SMCC_ISRA is set.
Reading I2SMCC_RHR clears this bit. In I2S or Left-Justified mode, consecutive access to I2SMCC_RHR reads first
the left channel then the right channel. In TDM or TDM Left-Justified mode, consecutive access to I2SMCC_RHR
reads the TDM channels enabled.
A receive overrun condition occurs if a new data word becomes available for the left channel x or right channel x
before the previous data word has been read from I2SMCC_RHR. In this case, the corresponding RXLOVFx or
RXROVFx bit in I2SMCC_ISRA is set. Reading I2SMCC_ISRA clears this bit.
When a data can be written in I2SMCC_THR, the corresponding TXLRDYx bit or TXRRDYx bit in I2SMCC_ISRA is
set. Writing to I2SMCC_THR clears this bit. In I2S or Left-Justified mode, consecutive access to I2SMCC_THR writes
first the left channel then the right channel. In TDM or TDM Left-Justified mode, consecutive access to I2SMCC_THR
writes the TDM channels enabled.
A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to
I2SMCC_THR. In this case, the corresponding TXLUNFx or TXRUNFx bit in I2SMCC_ISRA is set. Reading
I2SMCC_ISRA clears this bit.
In case of transmit underrun, if the value of I2SMCC_MRA.TXSAME is ‘0’, then a ‘0’ is transmitted. If the value of
I2SMCC_MRA.TXSAME is ‘1’, then the previous data word for the current transmit channel number is transmitted.
After a transmit underrun, the data written in I2SMCC_THR is discarded to keep the left and right channels
synchronized.
Data words are right-justified in the common registers (I2SMCC_RHR and I2SMCC_THR). For the 16-bit compact
stereo data format, the left sample uses bits [15:0] and the right sample uses bits [31:16] of the same data word. For
the 8-bit compact stereo data format, the left sample uses bits [7:0] and the right sample uses bits [15:8] of the same
data word.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1236
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.6.10 DMA Controller Operation
All receiver audio channels and all transmitter audio channels are each assigned to a single DMA Controller channel.
The DMA Controller reads from the I2SMCC_RHR and writes to the I2SMCC_THR for all audio channels
successively.
The DMA Controller transfers may use 32-bit word, 16-bit halfword, or 8-bit byte depending on the value of the
I2SMCC_MRA.DATALENGTH field.
The DMA chunk size field (DMACHUNK) of the Mode Register B(I2SMCC_MRB) should correspond to the DMA
channel configuration. The supported chunk according to the configuration is available in the two tables below
Table 44-5. TX DMA Chunk Configurations
FORMAT
TXMONO
DATALENGTH
NBCHAN
0
(Stereo)
0, 1, 2, 3, 4 or 6
(32, 24, 20, 18, 16 or 8 bits)
0 or 1
or LJ)
(I2S
1
(Mono)
NA
DMACHUNK Description
0
1-word chunk
1
2-word chunk
2
4-word chunk
3
8-word chunk
0
1-word chunk
1
2-word chunk
2
3
0 or 1
(Stereo or
Mono)
5 or 7
(16 bits compact or 8 bits
compact)
0
1-word chunk
1
2-word chunk
2
3
© 2020 Microchip Technology Inc.
Complete Datasheet
4-word chunk
4-word chunk
DS60001579C-page 1237
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
...........continued
FORMAT
TXMONO
NA
DATALENGTH
NA
NBCHAN
0
(1 channel)
DMACHUNK Description
0
1-word chunk
1
2-word chunk
2
3
1, 3 or 7
(2, 4 or 8
channels)
0
(Stereo)
2, 4, 5 or 6
(3, 5, 6 or 7
channels)
1, 3 or 7
(2, 4 or 8
channels)
2 or 3
(TDM or TDMLJ)
0
1-word chunk
1
2-word chunk
2
4-word chunk
3
8-word chunk
0
1-word chunk
1
2-word chunk
2
3
0, 1, 2, 3, 4 or 6
(32, 24, 20, 18, 16 or 8 bits)
1-word chunk
1
2-word chunk
2
0
2, 4, 5 or 6
(3, 5, 6 or 7
channels)
4-word chunk
0
3
1
(Mono)
4-word chunk
4-word chunk
1-word chunk
1
2
2-word chunk
3
1, 3 or 7
(2, 4 or 8
channels)
0 or 1
(Stereo or
Mono)
5 or 7
(16 bits compact or 8 bits
compact)
0
1-word chunk
1
2-word chunk
2
3
0
2, 4, 5 or 6
(3, 5, 6 or 7
channels)
4-word chunk
1-word chunk
1
2
2-word chunk
3
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1238
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
Table 44-6. RX DMA Chunk Configurations
FORMAT
DATALENGTH
NBCHAN
0, 1, 2, 3, 4 or 6
(32, 24, 20, 18, 16 or 8 bits)
0 or 1
(I2S or LJ)
NA
5 or 7
(16 bits compact or 8 bits compact)
DMACHUNK
Description
0
1-word chunk
1
2-word chunk
2
4-word chunk
3
8-word chunk
0
1-word chunk
1
2-word chunk
2
3
0
(1 channel)
NA
0
1-word chunk
1
2-word chunk
2
3
1, 3 or 7
(2, 4 or 8 channels)
0, 1, 2, 3, 4 or 6
(32, 24, 20, 18, 16 or 8 bits)
2, 4, 5 or 6
(3, 5, 6 or 7 channels)
2 or 3
(TDM or TDMLJ)
1-word chunk
1
2-word chunk
2
4-word chunk
3
8-word chunk
0
1-word chunk
1
2-word chunk
2
1-word chunk
1
2-word chunk
2
0
2, 4, 5 or 6
(3, 5, 6 or 7 channels)
4-word chunk
0
3
5 or 7
(16 bits compact or 8 bits compact)
4-word chunk
0
3
1, 3 or 7
(2, 4 or 8 channels)
4-word chunk
4-word chunk
1-word chunk
1
2
2-word chunk
3
44.6.11 Loop-back Mode
For debug purposes, the I2SMCC can be configured to loop back the transmitter to the receiver. Writing a ’1’ to the
I2SMCC_MRA.RXLOOP bit internally connects I2SMCC_DOUTx to I2SMCC_DINx, so that the transmitted data is
also received. Writing a ’0’ to I2SMCC_MRA.RXLOOP restores the normal behavior with independent receiver and
transmitter. As for other changes to the receiver or transmitter configuration, the I2SMCC receiver and transmitter
must be disabled before writing to I2SMCC_MRA to update I2SMCC_MRA.RXLOOP.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1239
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.6.12 Interrupts
An I2SMCC interrupt request can be triggered whenever one or several of the following bits are set in I2SMCC_ISRA
and/or I2SMCC_ISRB:
•
•
•
•
•
•
•
•
•
Receive Left x Ready (RXLRDYx)
Receive Right x Ready (RXRRDYx)
Receive Left x Overrun (RXLOVFx)
Receive Right x Overrun (RXROVFx)
Transmit Left x Ready (TXLRDYx)
Transmit Right x Ready (TXRRDYx)
Transmit Left x Underrun (TXLUNFx)
Transmit Right x Underrun (TXRUNFx)
Write Error (WERR)
The interrupt request is generated if the corresponding bit in the Interrupt Mask registers (I2SMCC_IMRA and
I2SMCC_IMRB) is set. Bits in I2SMCC_IMRx are set by writing a ’1’ to the corresponding bit in I2SMCC_IERx and
cleared by writing a ’1’ to the corresponding bit in I2SMCC_IDRx. The interrupt request remains active until the
corresponding bit in I2SMCC_ISRx is cleared.
Figure 44-6. Interrupt Block Diagram
Set
I2SMCC_IERx
Transmitter
Receiver
TXLRDYx
TXLUNFx
TXRRDYx
TXRUNFx
Clear
I2SMCC_IMRx
Interrupt
Logic
I2SMCC_IDRx
I2SMCC interrupt line
RXLRDYx
RXLOVFx
RXRRDYx
RXROVFx
Bus Interface
WERR
44.6.13 Register Write Protection
To prevent any single software error from corrupting I2SMCC behavior, certain registers in the address space can be
write-protected by setting the Write Protection Configuration Enable (WPCFEN), Write Protection Interrupt Enable
(WPITEN) and/or Write Protection Control Enable (WPCTEN) bit(s) in the Write Protection Mode register
(I2SMCC_WPMR).
If a write access to the protected registers is detected, the Write Protection Violation Status (WPVS) flag in the Write
Protection Status register (I2SMCC_WPSR) is set and the field Write Protection Violation Source (WPVSRC)
indicates the register in which the write access has been attempted. An interrupt can be raised if the Write Error
(WERR) interrupt is set in I2SMCC_IMRB.
The WPVS flag is automatically reset by reading I2SMCC_WPSR.
The following register can be write-protected with the I2SMCC_WPMR.WPCFEN bit:
•
•
Inter-IC Sound Multi Channel Controller Mode Register A
Inter-IC Sound Multi Channel Controller Mode Register B
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1240
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
The following registers can be write-protected with the I2SMCC_WPMR.WPITEN bit:
•
•
•
•
Inter-IC Sound Multi Channel Controller Interrupt Enable Register A
Inter-IC Sound Multi Channel Controller Interrupt Disable Register A
Inter-IC Sound Multi Channel Controller Interrupt Enable Register B
Inter-IC Sound Multi Channel Controller Interrupt Disable Register B
The following register can be write-protected with the I2SMCC_WPMR.WPCTEN bit:
•
Inter-IC Sound Multi Channel Controller Control Register
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1241
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7
Register Summary
Offset
Name
0x00
I2SMCC_CR
0x04
I2SMCC_MRA
0x08
I2SMCC_MRB
0x0C
I2SMCC_SR
0x10
I2SMCC_IERA
0x14
I2SMCC_IDRA
0x18
I2SMCC_IMRA
0x1C
I2SMCC_ISRA
0x20
I2SMCC_IERB
0x24
0x28
0x2C
I2SMCC_IDRB
I2SMCC_IMRB
I2SMCC_ISRB
0x30
I2SMCC_RHR
0x34
I2SMCC_THR
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
SWRST
IWS
IMCKMODE
TDMFS[1:0]
NBCHAN[2:0]
FORMAT[1:0]
5
4
3
TXDIS
TXEN
SRCCLK
ZERO[1:0]
2
1
CKDIS
CKEN
RXDIS
ISCKDIV[5:0]
IMCKDIV[5:0]
TXSAME
TXMONO
RXLOOP
DATALENGTH[2:0]
0
RXEN
RXMONO
MODE
CLKSEL
DMACHUNK[1:0]
RXROVF3
RXRRDY3
TXRUNF3
TXRRDY3
RXROVF3
RXRRDY3
TXRUNF3
TXRRDY3
RXROVF3
RXRRDY3
TXRUNF3
TXRRDY3
RXROVF3
RXRRDY3
TXRUNF3
TXRRDY3
© 2020 Microchip Technology Inc.
RXLOVF3
RXLRDY3
TXLUNF3
TXLRDY3
RXLOVF3
RXLRDY3
TXLUNF3
TXLRDY3
RXLOVF3
RXLRDY3
TXLUNF3
TXLRDY3
RXLOVF3
RXLRDY3
TXLUNF3
TXLRDY3
RXROVF2
RXRRDY2
TXRUNF2
TXRRDY2
RXROVF2
RXRRDY2
TXRUNF2
TXRRDY2
RXROVF2
RXRRDY2
TXRUNF2
TXRRDY2
RXROVF2
RXRRDY2
TXRUNF2
TXRRDY2
TXEN
RXLOVF2
RXLRDY2
TXLUNF2
TXLRDY2
RXLOVF2
RXLRDY2
TXLUNF2
TXLRDY2
RXLOVF2
RXLRDY2
TXLUNF2
TXLRDY2
RXLOVF2
RXLRDY2
TXLUNF2
TXLRDY2
RXROVF1
RXRRDY1
TXRUNF1
TXRRDY1
RXROVF1
RXRRDY1
TXRUNF1
TXRRDY1
RXROVF1
RXRRDY1
TXRUNF1
TXRRDY1
RXROVF1
RXRRDY1
TXRUNF1
TXRRDY1
RXLOVF1
RXLRDY1
TXLUNF1
TXLRDY1
RXLOVF1
RXLRDY1
TXLUNF1
TXLRDY1
RXLOVF1
RXLRDY1
TXLUNF1
TXLRDY1
RXLOVF1
RXLRDY1
TXLUNF1
TXLRDY1
RXROVF0
RXRRDY0
TXRUNF0
TXRRDY0
RXROVF0
RXRRDY0
TXRUNF0
TXRRDY0
RXROVF0
RXRRDY0
TXRUNF0
TXRRDY0
RXROVF0
RXRRDY0
TXRUNF0
TXRRDY0
RXEN
RXLOVF0
RXLRDY0
TXLUNF0
TXLRDY0
RXLOVF0
RXLRDY0
TXLUNF0
TXLRDY0
RXLOVF0
RXLRDY0
TXLUNF0
TXLRDY0
RXLOVF0
RXLRDY0
TXLUNF0
TXLRDY0
WERR
WERR
WERR
WERR
RHR[31:24]
RHR[23:16]
RHR[15:8]
RHR[7:0]
THR[31:24]
THR[23:16]
THR[15:8]
THR[7:0]
Complete Datasheet
DS60001579C-page 1242
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
...........continued
Offset
Name
0x38
...
0xE3
Reserved
0xE4
0xE8
I2SMCC_WPMR
I2SMCC_WPSR
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
6
5
4
3
2
1
0
WPCTEN
WPITEN
WPCFEN
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WPVSRC[23:16]
WPVSRC[15:8]
WPVSRC[7:0]
WPVS
Complete Datasheet
DS60001579C-page 1243
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.1
Inter-IC Sound Multi Channel Controller Control Register
Name:
Offset:
Reset:
Property:
I2SMCC_CR
0x00
–
Write-only
This register can only be written if the WPCTEN bit is cleared in the Inter-IC Sound Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
SWRST
W
–
6
5
TXDIS
W
–
4
TXEN
W
–
3
CKDIS
W
–
2
CKEN
W
–
1
RXDIS
W
–
0
RXEN
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 7 – SWRST Software Reset
Value
Description
0
No effect.
1
Resets all the registers in the I2SMCC. The I2SMCC is disabled after the reset.
Bit 5 – TXDIS Transmitter Disable
Value
Description
0
No effect.
1
Disables the I2SMCC transmitter. Bit I2SMCC_SR.TXEN is cleared when the Transmitter is stopped.
Bit 4 – TXEN Transmitter Enable
Value
Description
0
No effect.
1
Enables the I2SMCC transmitter, if TXDIS is not ‘1’. Bit I2SMCC_SR.TXEN is set when the Transmitter
is started.
Bit 3 – CKDIS Clocks Disable
Value
Description
0
No effect.
1
Disables the I2SMCC clock generation.
Bit 2 – CKEN Clocks Enable
Value
Description
0
No effect.
1
Enables the I2SMCC clock generation, if CKDIS is not ‘1’.
Bit 1 – RXDIS Receiver Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1244
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
Value
0
1
Description
No effect.
Disables the I2SMCC receiver. Bit I2SMCC_SR.RXEN is cleared when the receiver is stopped.
Bit 0 – RXEN Receiver Enable
Value
Description
0
No effect.
1
Enables the I2SMCC receiver, if RXDIS is not ‘1’. Bit I2SMCC_SR.RXEN is set when the receiver is
activated.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1245
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.2
Inter-IC Sound Multi Channel Controller Mode Register A
Name:
Offset:
Reset:
Property:
I2SMCC_MRA
0x04
0x00000000
Read/Write
This register can only be written if the WPCFEN bit is cleared in the Inter-IC Sound Write Protection Mode Register.
The I2SMCC_MRA must only be written when the I2SMCC is stopped in order to avoid unexpected behavior on the
I2SMCC_WS, I2SMCC_CK and I2SMCC_DOUT outputs. The proper sequence is to write to I2SMCC_MRA, then
write to I2SMCC_CR to enable the I2SMCC or to disable the I2SMCC before writing a new value to I2SMCC_MRA.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
IWS
R/W
0
30
IMCKMODE
R/W
0
23
22
TDMFS[1:0]
R/W
R/W
0
0
15
R/W
0
14
NBCHAN[2:0]
R/W
0
7
6
FORMAT[1:0]
R/W
R/W
0
0
29
28
R/W
0
R/W
0
21
20
R/W
0
R/W
0
13
12
SRCCLK
R/W
0
11
TXSAME
R/W
0
4
3
R/W
0
R/W
0
R/W
0
5
27
26
ISCKDIV[5:0]
R/W
R/W
0
0
24
R/W
0
R/W
0
17
16
R/W
0
R/W
0
10
TXMONO
R/W
0
9
RXLOOP
R/W
0
8
RXMONO
R/W
0
2
DATALENGTH[2:0]
R/W
0
1
0
MODE
R/W
0
19
18
IMCKDIV[5:0]
R/W
R/W
0
0
ZERO[1:0]
R/W
0
25
R/W
0
Bit 31 – IWS I2SMCC_WS Slot Length
See tables Slot Length (I2S format) and Slot Length (Left-Justified format).
Value
Description
0
I2SMCC_WS slot is 32 bits long for DATALENGTH = 18/20/24 bits.
1
I2SMCC_WS slot is 24 bits long for DATALENGTH = 18/20/24 bits.
Bit 30 – IMCKMODE Master Clock Mode
Value
Description
0
No master clock generated.
1
Master clock generated.
Bits 29:24 – ISCKDIV[5:0] Selected Clock to I2SMCC Serial Clock Ratio
I2SMCC_CK Serial clock output frequency is Selected Clock divided by (2 * ISCKDIV). If ISCKDIV is 0, the
I2SMCC_CK Serial clock output frequency is equal to the Selected Clock frequency.
Bits 23:22 – TDMFS[1:0] TDM Frame Synchronization
Value
Name Description
0
SLOT I2SMCC_WS pulse is high for one time slot at beginning of frame.
1
HALF I2SMCC_WS pulse is high for half the time slots at beginning of frame.
2
BIT
I2SMCC_WS pulse is high for one bit period at beginning of frame, i.e., one ISCK period.
Bits 21:16 – IMCKDIV[5:0] Selected Clock to I2SMCC Master Clock Ratio
I2SMCC_MCK Master clock output frequency is Selected Clock divided by (2 * IMCKDIV). If IMCKDIV is 0, the
I2SMCC_MCK Master clock output frequency is equal to the Selected Clock frequency.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1246
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
Bits 15:13 – NBCHAN[2:0] Number of TDM Channels-1
Must be written with the number of TDM channels minus one.
Bit 12 – SRCCLK Source Clock Selection
Value
Description
0
The Peripheral clock is selected as source clock.
1
The PMC.GCLKx clock is selected as source clock.
Bit 11 – TXSAME Transmit Data when Underrun
Value
Description
0
‘0’ is transmitted when underrun.
1
Previous sample transmitted when underrun.
Bit 10 – TXMONO Transmit Mono
Value
Description
0
Stereo
1
Mono, with left audio samples duplicated to right audio channel by the I2SMCC.
Bit 9 – RXLOOP Loop-back Test Mode
Value
Description
0
Normal mode
1
I2SMCC_DOUT output of I2SMCC are internally connected to I2SMCC_DIN inputs.
Bit 8 – RXMONO Receive Mono
Value
Description
0
Stereo
1
Mono, with left audio samples duplicated to right audio channel by the I2SMCC.
Bits 7:6 – FORMAT[1:0] Data Format
Value
Name Description
0
I2S
I2S format, stereo with I2SMCC_WS low for left channel, and MSB of sample starting one
I2SMCC_CK period after I2SMCC_WS edge.
1
LJ
Left-justified format, stereo with I2SMCC_WS high for left channel, and MSB of sample
starting on I2SMCC_WS edge.
2
TDM
TDM format, with (NBCHAN + 1) channels, I2SMCC_WS high at beginning of first channel,
and MSB of sample starting one I2SMCC_CK period after I2SMCC_WS edge.
3
TDMLJ TDM format, left-justified, with (NBCHAN + 1) channels, I2SMCC_WS high at beginning of
first channel, and MSB of sample starting on I2SMCC_WS edge.
Bits 5:4 – ZERO[1:0] Must always be written to 0
Bits 3:1 – DATALENGTH[2:0] Data Word Length
Value
Name
Description
0
32_BITS
Data length is set to 32 bits.
1
24_BITS
Data length is set to 24 bits.
2
20_BITS
Data length is set to 20 bits.
3
18_BITS
Data length is set to 18 bits.
4
16_BITS
Data length is set to 16 bits.
5
16_BITS_COMPACT Data length is set to 16-bit compact stereo. Left sample in bits [15:0] and right
sample in bits [31:16] of same word.
6
8_BITS
Data length is set to 8 bits.
7
8_BITS_COMPACT Data length is set to 8-bit compact stereo. Left sample in bits [7:0] and right
sample in bits [15:8] of the same word.
Bit 0 – MODE Inter-IC Sound Multi Channel Controller Mode
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1247
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
Value
0
1
Name
SLAVE
Description
I2SMCC_CK and I2SMCC_WS pin inputs used as bit clock and word select/frame
synchronization.
MASTER Bit clock and word select/frame synchronization generated by I2SMCC from MCK and
output to I2SMCC_CK and I2SMCC_WS pins. MCK is output as master clock on
I2SMCC_MCK if I2SMCC_MRA.IMCKMODE is set.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1248
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.3
Inter-IC Sound Multi Channel Controller Mode Register B
Name:
Offset:
Reset:
Property:
I2SMCC_MRB
0x08
0x00000000
Read/Write
This register can only be written if the WPCFEN bit is cleared in the Inter-IC Sound Write Protection Mode Register.
The I2SMCC_MRB must only be written when the I2SMCC is stopped in order to avoid unexpected behavior on the
I2SMCC_WS, I2SMCC_CK and I2SMCC_DOUT outputs. The proper sequence is to write to I2SMCC_MRB, then
write to I2SMCC_CR to enable the I2SMCC or to disable the I2SMCC before writing a new value to I2SMCC_MRB.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLKSEL
R/W
0
15
14
13
12
11
10
7
6
5
4
3
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
9
8
DMACHUNK[1:0]
R/W
R/W
0
0
1
0
Access
Reset
Bit 16 – CLKSEL Serial Clock Selection
Value
Description
0
The I2SMCC_CK clock (provided by the external I2S master) is selected as serial clock.
1
The internal clock (generated from source clock) is selected as serial clock.
Bits 9:8 – DMACHUNK[1:0] DMA Chunk Size
Value
Name
Description
0
1_WORD
Each DMA transfer contains 1 word.
1
2_WORDS
Each DMA transfer contains 2 words.
2
4_WORDS
Each DMA transfer contains 4 words.
3
8_WORDS
Each DMA transfer contains 8 words.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1249
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.4
Inter-IC Sound Multi Channel Controller Status Register
Name:
Offset:
Reset:
Property:
Bit
I2SMCC_SR
0x0C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
TXEN
R
0
3
2
1
0
RXEN
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – TXEN Transmitter Enabled
Value
Description
0
Cleared when the transmitter is disabled, following a I2SMCC_CR.TXDIS or I2SMCC_CR.SWRST
request.
1
Set when the transmitter is enabled, following a I2SMCC_CR.TXEN request.
Bit 0 – RXEN Receiver Enabled
Value
Description
0
Cleared when the receiver is disabled, following a RXDIS or SWRST request in I2SMCC_CR.
1
Set when the receiver is enabled, following a RXEN request in I2SMCC_CR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1250
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.5
Inter-IC Sound Multi Channel Controller Interrupt Enable Register A
Name:
Offset:
Reset:
Property:
I2SMCC_IERA
0x10
–
Write-only
This register can only be written if the WPITEN bit is cleared in the Inter-IC Sound Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
RXROVF3
W
–
30
RXLOVF3
W
–
29
RXROVF2
W
–
28
RXLOVF2
W
–
27
RXROVF1
W
–
26
RXLOVF1
W
–
25
RXROVF0
W
–
24
RXLOVF0
W
–
23
RXRRDY3
W
–
22
RXLRDY3
W
–
21
RXRRDY2
W
–
20
RXLRDY2
W
–
19
RXRRDY1
W
–
18
RXLRDY1
W
–
17
RXRRDY0
W
–
16
RXLRDY0
W
–
15
TXRUNF3
W
–
14
TXLUNF3
W
–
13
TXRUNF2
W
–
12
TXLUNF2
W
–
11
TXRUNF1
W
–
10
TXLUNF1
W
–
9
TXRUNF0
W
–
8
TXLUNF0
W
–
7
TXRRDY3
W
–
6
TXLRDY3
W
–
5
TXRRDY2
W
–
4
TXLRDY2
W
–
3
TXRRDY1
W
–
2
TXLRDY1
W
–
1
TXRRDY0
W
–
0
TXLRDY0
W
–
Bits 25, 27, 29, 31 – RXROVFx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Enable
Bits 24, 26, 28, 30 – RXLOVFx I2S Receive Left x (x=0 only) or TDM Channel 2x Overrun Interrupt Enable
Bits 17, 19, 21, 23 – RXRRDYx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable
Bits 16, 18, 20, 22 – RXLRDYx I2S Receive Left x (x=0 only) or TDM Channel 2x Ready Interrupt Enable
Bits 9, 11, 13, 15 – TXRUNFx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Enable
Bits 8, 10, 12, 14 – TXLUNFx I2S Transmit Left x (x=0 only) or TDM Channel 2x Underrun Interrupt Enable
Bits 1, 3, 5, 7 – TXRRDYx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Enable
Bits 0, 2, 4, 6 – TXLRDYx I2S Transmit Left x (x=0 only) or TDM Channel 2x Ready Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1251
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.6
Inter-IC Sound Multi Channel Controller Interrupt Disable Register A
Name:
Offset:
Reset:
Property:
I2SMCC_IDRA
0x14
–
Write-only
This register can only be written if the WPITEN bit is cleared in the Inter-IC Sound Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
RXROVF3
W
–
30
RXLOVF3
W
–
29
RXROVF2
W
–
28
RXLOVF2
W
–
27
RXROVF1
W
–
26
RXLOVF1
W
–
25
RXROVF0
W
–
24
RXLOVF0
W
–
23
RXRRDY3
W
–
22
RXLRDY3
W
–
21
RXRRDY2
W
–
20
RXLRDY2
W
–
19
RXRRDY1
W
–
18
RXLRDY1
W
–
17
RXRRDY0
W
–
16
RXLRDY0
W
–
15
TXRUNF3
W
–
14
TXLUNF3
W
–
13
TXRUNF2
W
–
12
TXLUNF2
W
–
11
TXRUNF1
W
–
10
TXLUNF1
W
–
9
TXRUNF0
W
–
8
TXLUNF0
W
–
7
TXRRDY3
W
–
6
TXLRDY3
W
–
5
TXRRDY2
W
–
4
TXLRDY2
W
–
3
TXRRDY1
W
–
2
TXLRDY1
W
–
1
TXRRDY0
W
–
0
TXLRDY0
W
–
Bits 25, 27, 29, 31 – RXROVFx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Disable
Bits 24, 26, 28, 30 – RXLOVFx I2S Receive Left x (x=0 only) or TDM Channel 2x Overrun Interrupt Disable
Bits 17, 19, 21, 23 – RXRRDYx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable
Bits 16, 18, 20, 22 – RXLRDYx I2S Receive Left x (x=0 only) or TDM Channel 2x Ready Interrupt Disable
Bits 9, 11, 13, 15 – TXRUNFx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Disable
Bits 8, 10, 12, 14 – TXLUNFx I2S Transmit Left x (x=0 only) or TDM Channel 2x Underrun Interrupt Disable
Bits 1, 3, 5, 7 – TXRRDYx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable
Bits 0, 2, 4, 6 – TXLRDYx I2S Transmit Left x (x=0 only) or TDM Channel 2x Ready Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1252
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.7
Inter-IC Sound Multi Channel Controller Interrupt Mask Register A
Name:
Offset:
Reset:
Property:
I2SMCC_IMRA
0x18
0x00000000
Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding source of interrupt is disabled.
1: The corresponding source of interrupt is enabled.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
RXROVF3
R
0
30
RXLOVF3
R
0
29
RXROVF2
R
0
28
RXLOVF2
R
0
27
RXROVF1
R
0
26
RXLOVF1
R
0
25
RXROVF0
R
0
24
RXLOVF0
R
0
23
RXRRDY3
R
0
22
RXLRDY3
R
0
21
RXRRDY2
R
0
20
RXLRDY2
R
0
19
RXRRDY1
R
0
18
RXLRDY1
R
0
17
RXRRDY0
R
0
16
RXLRDY0
R
0
15
TXRUNF3
R
0
14
TXLUNF3
R
0
13
TXRUNF2
R
0
12
TXLUNF2
R
0
11
TXRUNF1
R
0
10
TXLUNF1
R
0
9
TXRUNF0
R
0
8
TXLUNF0
R
0
7
TXRRDY3
R
0
6
TXLRDY3
R
0
5
TXRRDY2
R
0
4
TXLRDY2
R
0
3
TXRRDY1
R
0
2
TXLRDY1
R
0
1
TXRRDY0
R
0
0
TXLRDY0
R
0
Bits 25, 27, 29, 31 – RXROVFx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Mask
Bits 24, 26, 28, 30 – RXLOVFx I2S Receive Left x (x=0 only) or TDM Channel 2x Overrun Interrupt Mask
Bits 17, 19, 21, 23 – RXRRDYx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask
Bits 16, 18, 20, 22 – RXLRDYx I2S Receive Left x (x=0 only) or TDM Channel 2x Ready Interrupt Mask
Bits 9, 11, 13, 15 – TXRUNFx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Mask
Bits 8, 10, 12, 14 – TXLUNFx I2S Transmit Left x (x=0 only) or TDM Channel 2x Underrun Interrupt Mask
Bits 1, 3, 5, 7 – TXRRDYx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask
Bits 0, 2, 4, 6 – TXLRDYx I2S Transmit Left x (x=0 only) or TDM Channel 2x Ready Interrupt Mask
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1253
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.8
Inter-IC Sound Multi Channel Controller Interrupt Status Register A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
I2SMCC_ISRA
0x1C
0x00000000
Read-only
31
RXROVF3
R
0
30
RXLOVF3
R
0
29
RXROVF2
R
0
28
RXLOVF2
R
0
27
RXROVF1
R
0
26
RXLOVF1
R
0
25
RXROVF0
R
0
24
RXLOVF0
R
0
23
RXRRDY3
R
0
22
RXLRDY3
R
0
21
RXRRDY2
R
0
20
RXLRDY2
R
0
19
RXRRDY1
R
0
18
RXLRDY1
R
0
17
RXRRDY0
R
0
16
RXLRDY0
R
0
15
TXRUNF3
R
0
14
TXLUNF3
R
0
13
TXRUNF2
R
0
12
TXLUNF2
R
0
11
TXRUNF1
R
0
10
TXLUNF1
R
0
9
TXRUNF0
R
0
8
TXLUNF0
R
0
7
TXRRDY3
R
0
6
TXLRDY3
R
0
5
TXRRDY2
R
0
4
TXLRDY2
R
0
3
TXRRDY1
R
0
2
TXLRDY1
R
0
1
TXRRDY0
R
0
0
TXLRDY0
R
0
Bits 25, 27, 29, 31 – RXROVFx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Overrun Flag (Cleared on
read)
Value
Description
0
Cleared when I2SMCC_ISRA is read.
1
Set when an overrun error occurs in I2SMCC_RHR.
Bits 24, 26, 28, 30 – RXLOVFx I2S Receive Left x (x=0 only) or TDM Channel 2x Overrun Flag (Cleared on read)
Value
Description
0
Cleared when I2SMCC_ISRA is read.
1
Set when an overrun error occurs in I2SMCC_RHR.
Bits 17, 19, 21, 23 – RXRRDYx I2S Receive Right x (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by
reading I2SMCC_RHR)
Value
Description
0
Cleared when the corresponding data has been read through I2SMCC_RHR.
1
Set when received data is available in I2SMCC_RHR.
Bits 16, 18, 20, 22 – RXLRDYx I2S Receive Left x (x=0 only) or TDM Channel 2x Ready Flag (Cleared by reading
I2SMCC_RHR)
Value
Description
0
Cleared when the corresponding data has been read in I2SMCC_RHR.
1
Set when received data is available in I2SMCC_RHR.
Bits 9, 11, 13, 15 – TXRUNFx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Underrun Flag (Cleared on
read)
Value
Description
0
Cleared when the I2SMCC_ISRA is read.
1
Set when an underrun error occurs in I2SMCC_THR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1254
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
Bits 8, 10, 12, 14 – TXLUNFx I2S Transmit Left x (x=0 only) or TDM Channel 2x Underrun (Cleared on read)
Value
Description
0
Cleared when I2SMCC_ISRA is read.
1
Set when an underrun error occurs in I2SMCC_THR.
Bits 1, 3, 5, 7 – TXRRDYx I2S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Ready Flag (Cleared by writing
I2SMCC_THR)
Value
Description
0
Cleared the corresponding data has been written in I2SMCC_THR.
1
Set when I2SMCC_THR is empty.
Bits 0, 2, 4, 6 – TXLRDYx I2S Transmit Left x (x=0 only) or TDM Channel 2x Ready Flag (Cleared by writing
I2SMCC_THR)
Value
Description
0
Cleared when the corresponding data has been written in I2SMCC_THR.
1
Set when I2SMCC_THR is empty.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1255
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.9
Inter-IC Sound Multi Channel Controller Interrupt Enable Register B
Name:
Offset:
Reset:
Property:
I2SMCC_IERB
0x20
–
Write-only
This register can only be written if the WPITEN bit is cleared in the Inter-IC Sound Write Protection Mode Register.
The following configuration values are valid for the listed bit of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WERR
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – WERR Write Error Interrupt Enable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1256
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.10 Inter-IC Sound Multi Channel Controller Interrupt Disable Register B
Name:
Offset:
Reset:
Property:
I2SMCC_IDRB
0x24
–
Write-only
This register can only be written if the WPITEN bit is cleared in the Inter-IC Sound Write Protection Mode Register.
The following configuration values are valid for the listed bit of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WERR
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – WERR Write Error Interrupt Disable
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1257
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.11 Inter-IC Sound Multi Channel Controller Interrupt Mask Register B
Name:
Offset:
Reset:
Property:
I2SMCC_IMRB
0x28
0x00000000
Read-only
The following configuration values are valid for the listed bit of this register:
0: The corresponding source of interrupt is disabled.
1: The corresponding source of interrupt is enabled.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WERR
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – WERR Write Error Interrupt Mask
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1258
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.12 Inter-IC Sound Multi Channel Controller Interrupt Status Register B
Name:
Offset:
Reset:
Property:
Bit
I2SMCC_ISRB
0x2C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WERR
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – WERR Write Error Flag (Cleared on read)
Value
Description
0
Cleared when the I2SMCC_ISRB is read.
1
Set when a write occurs in a protected register.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1259
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.13 Inter-IC Sound Multi Channel Controller Receiver Holding Register
Name:
Offset:
Reset:
Property:
Bit
31
I2SMCC_RHR
0x30
0x00000000
Read-only
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RHR[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
RHR[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RHR[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RHR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – RHR[31:0] Receiver Holding Register
Set by hardware to the last received data word. If I2SMCC_MRA.DATALENGTH specifies fewer than 32 bits, data is
right justified in the RHR field.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1260
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.14 Inter-IC Sound Multi Channel Controller Transmitter Holding Register
Name:
Offset:
Reset:
Property:
Bit
31
I2SMCC_THR
0x34
–
Write-only
30
29
28
27
26
25
24
W
–
W
–
W
–
W
–
19
18
17
16
W
–
W
–
W
–
W
–
11
10
9
8
W
–
W
–
W
–
W
–
3
2
1
0
W
–
W
–
W
–
W
–
THR[31:24]
Access
Reset
W
–
W
–
W
–
W
–
Bit
23
22
21
20
THR[23:16]
Access
Reset
W
–
W
–
W
–
W
–
Bit
15
14
13
12
THR[15:8]
Access
Reset
W
–
W
–
W
–
W
–
Bit
7
6
5
4
THR[7:0]
Access
Reset
W
–
W
–
W
–
W
–
Bits 31:0 – THR[31:0] Transmitter Holding Register
Next data word to be transmitted after the current word if TXLRDYx or TXRRDYx is not set. If
I2SMCC_MRA.DATALENGTH specifies fewer than 32 bits, data is right-justified in the THR field.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1261
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.15 Inter-IC Sound Write Protection Mode Register
Name:
Offset:
Reset:
Property:
I2SMCC_WPMR
0xE4
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
WPCTEN
R/W
0
1
WPITEN
R/W
0
0
WPCFEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x493253
PASSWD
Writing any other value in this field aborts the write operation.
Always reads as 0.
Bit 2 – WPCTEN Write Protection Control Enable
Value
Description
0
Disables the write protection of the control if WPKEY matches to 0x493253 (I2S in ASCII).
1
Enables the write protection of the control if WPKEY matches to 0x493253 (I2S in ASCII).
Bit 1 – WPITEN Write Protection Interrupt Enable
Value
Description
0
Disables the write protection of the interruption if WPKEY matches to 0x493253 (I2S in ASCII).
1
Enables the write protection of the interruption if WPKEY matches to 0x493253 (I2S in ASCII).
Bit 0 – WPCFEN Write Protection Configuration Enable
Value
Description
0
Disables the write protection of the configuration if WPKEY matches to 0x493253 (I2S in ASCII).
1
Enables the write protection of the configuration if WPKEY matches to 0x493253 (I2S in ASCII).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1262
SAM9X60
Inter-IC Sound Multi-Channel Controller (I2SMCC)
44.7.16 Inter-IC Sound Write Protection Status Register
Name:
Offset:
Reset:
Property:
I2SMCC_WPSR
0xE8
0x00000000
Read-only
Bit
31
30
29
28
27
WPVSRC[23:16]
R
R
0
0
26
25
24
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Bit
23
22
21
20
19
WPVSRC[15:8]
R
R
0
0
18
17
16
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
R
0
12
11
WPVSRC[7:0]
R
R
0
0
Access
Reset
R
0
R
0
R
0
R
0
R
0
Bit
7
6
5
4
2
1
0
WPVS
R
0
3
Access
Reset
Bits 31:8 – WPVSRC[23:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 0 – WPVS Write Protection Violation Status
Value
Description
0
No write protection violation has occurred since the last read of the I2SMCC_WPSR.
1
A write protection violation has occurred since the last read of the I2SMCC_WPSR. If this violation is
an unauthorized attempt to write a protected register, the associated violation is reported into field
WPVSRC.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1263
SAM9X60
Synchronous Serial Controller (SSC)
45.
45.1
Synchronous Serial Controller (SSC)
Description
The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It
supports many serial synchronous communication protocols generally used in audio and telecom applications such
as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the
transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF
signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on
the Frame Sync signal.
The SSC high-level of programmability and its use of DMA enable a continuous high bit rate data transfer without
processor intervention.
Featuring connection to the DMA, the SSC enables interfacing with low processor overhead to:
•
•
•
45.2
Codecs in Master or Slave mode
DAC through dedicated serial interface, particularly I2S
Magnetic card reader
Embedded Characteristics
•
•
•
•
•
•
Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications
Contains an Independent Receiver and Transmitter and a Common Clock Divider
Interfaced with the DMA Controller (DMAC) to Reduce Processor Overhead
Offers a Configurable Frame Sync and Data Length
Receiver and Transmitter Can be Programmed to Start Automatically or on Detection of Different Events on the
Frame Sync Signal
Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Sync Signal
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1264
SAM9X60
Synchronous Serial Controller (SSC)
45.3
Block Diagram
Figure 45-1. SSC Block Diagram
System
Bus
Peripheral Bridge
DMA
Bus Clock
Peripheral
Bus
TF
TK
TD
Peripheral Clock
PMC
PIO
SSC Interface
RF
RK
Interrupt Control
RD
SSC Interrupt
45.4
Application Block Diagram
Figure 45-2. Application Block Diagram
OS or RTOS Driver
Power
Management
Interrupt
Management
Test
Management
SSC
Serial AUDIO
45.5
Codec
Time Slot
Management
Frame
Management
Line Interface
SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial links. Some standard
applications are shown in the following figures. All serial link applications supported by the SSC are not listed here.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1265
SAM9X60
Synchronous Serial Controller (SSC)
Figure 45-3. Audio Application Block Diagram
Clock SCK
TK
Word Select WS
I2S
RECEIVER
TF
SSC
Data SD
TD
RD
Clock SCK
RF
Word Select WS
RK
MSB
Data SD
LSB
Left Channel
MSB
Right Channel
Figure 45-4. Codec Application Block Diagram
Serial Data Clock (SCLK)
TK
Frame Sync (FSYNC)
TF
SSC
TD
CODEC
Serial Data Out
Serial Data In
RD
RF
RK
Serial Data Clock (SCLK)
Frame Sync (FSYNC)
First Time Slot
Dstart
Dend
Serial Data Out
Serial Data In
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1266
SAM9X60
Synchronous Serial Controller (SSC)
Figure 45-5. Time Slot Application Block Diagram
SCLK
TK
FSYNC
TF
CODEC
First
Time Slot
Data Out
TD
SSC
Data In
RD
RF
RK
CODEC
Second
Time Slot
Serial Data Clock (SCLK)
First Time Slot
Frame Sync (FSYNC)
Dstart
Second Time Slot
Dend
Serial Data Out
Serial Data in
45.6
Pin Name List
Table 45-1. I/O Lines Description
45.7
45.7.1
Pin Name
Pin Description
Type
RF
Receive Frame Synchronization
Input/Output
RK
Receive Clock
Input/Output
RD
Receive Data
Input
TF
Transmit Frame Synchronization
Input/Output
TK
Transmit Clock
Input/Output
TD
Transmit Data
Output
Product Dependencies
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the
SSC Peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to
the SSC Peripheral mode.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1267
SAM9X60
Synchronous Serial Controller (SSC)
45.7.2
Power Management
The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller
(PMC), therefore the programmer must first configure the PMC to enable the SSC clock.
45.7.3
Interrupt
The SSC interface has an interrupt line connected to the interrupt controller. Handling interrupts requires
programming the interrupt controller before configuring the SSC.
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt Mask Register. Each pending and
unmasked SSC interrupt asserts the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin
by reading the SSC Interrupt Status Register.
45.8
Functional Description
This section contains the functional description of the following: SSC Functional Block, Clock Management, Data
Format, Start, Transmit, Receive and Frame Synchronization.
The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver
to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by
programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The
transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK
pins. This allows the SSC to support many Slave mode data transfers. The maximum clock speed allowed on the TK
and RK pins is the peripheral clock divided by 2.
Figure 45-6. SSC Functional Block Diagram
Transmitter
Peripheral
Clock
TK Input
Clock
Divider
Transmit Clock
Controller
RX clock
TXEN
RX Start Start
Selector
TF
TK
Frame Sync
Controller
TF
Data
Controller
TD
TX Start
Transmit Shift Register
Transmit Holding
Register
APB
TX clock
Clock Output
Controller
Transmit Sync
Holding Register
User
Interface
Receiver
RK Input
RK
Frame Sync
Controller
RF
Data
Controller
RD
Receive Clock RX Clock
Controller
TX Clock
RXEN
TX Start Start
RF
Selector
RC0R
Interrupt Control
Clock Output
Controller
RX Start
Receive Shift Register
Receive Holding
Register
Receive Sync
Holding Register
To Interrupt Controller
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
45.8.1
Clock Management
The transmit clock can be generated by:
•
•
•
an external clock received on the TK I/O pad
the receive clock
the internal clock divider
The receive clock can be generated by:
•
•
•
an external clock received on the RK I/O pad
the transmit clock
the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receive block can
generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave mode data transfers.
45.8.1.1 Clock Divider
Figure 45-7. Divided Clock Block Diagram
Clock Divider
SSC_CMR
Peripheral Clock
/2
12-bit Counter
Divided Clock
The peripheral clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is
4095) in the Clock Mode Register (SSC_CMR), allowing a peripheral clock division by up to 8190. The Divided Clock
is provided to both the receiver and the transmitter. When this field is programmed to 0, the Clock Divider is not used
and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of peripheral clock divided
by 2 times DIV. Each level of the Divided Clock has a duration of the peripheral clock multiplied by DIV. This ensures
a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd.
Figure 45-8. Divided Clock Generation
Peripheral Clock
Divided Clock
DIV = 1
Divided Clock Frequency = fperipheral clock/2
Peripheral Clock
Divided Clock
DIV = 3
Divided Clock Frequency = fperipheral clock/6
45.8.1.2 Transmit Clock Management
The transmit clock is generated from the receive clock or the divider clock or an external clock scanned on the TK I/O
pad. The transmit clock is selected by the CKS field in the Transmit Clock Mode Register (SSC_TCMR). Transmit
Clock can be inverted independently by the CKI bits in the SSC_TCMR.
The transmitter can also drive the TK I/O pad continuously or be limited to the current data transfer. The clock output
is configured by the SSC_TCMR. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the SSC_TCMR to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO
field) can lead to unpredictable results.
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Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
Figure 45-9. Transmit Clock Management
TK (pin)
Receive
Clock
Tri_state
Controller
Clock
Output
MUX
Divider
Clock
CKO
CKS
Data Transfer
INV
MUX
Tri_state
Controller
CKI
CKG
Transmit
Clock
45.8.1.3 Receive Clock Management
The receive clock is generated from the transmit clock or the divider clock or an external clock scanned on the RK I/O
pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks
can be inverted independently by the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the current data transfer. The clock output is
configured by the SSC_RCMR. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the SSC_RCMR to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO
field) can lead to unpredictable results.
Figure 45-10. Receive Clock Management
RK (pin)
Transmit
Clock
Tri_state
Controller
Clock
Output
MUX
Divider
Clock
CKO
CKS
Data Transfer
INV
MUX
Tri_state
Controller
CKI
CKG
Receive
Clock
45.8.1.4 Serial Clock Ratio Considerations
The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or
RK pins. This allows the SSC to support many Slave mode data transfers. In this case, the maximum clock speed
allowed on the RK pin is:
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Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
•
•
Peripheral clock divided by 2 if Receive Frame Synchronization is input
Peripheral clock divided by 3 if Receive Frame Synchronization is output
In addition, the maximum clock speed allowed on the TK pin is:
• Peripheral clock divided by 6 if Transmit Frame Synchronization is input
• Peripheral clock divided by 2 if Transmit Frame Synchronization is output
These are only theoretical speed limits for first order calculations. Exact speed limits on TK and RK are provided in
the "Electrical Characteristics" chapter.
45.8.2
Transmit Operations
A transmit frame is triggered by a start event and can be followed by synchronization data before data transmission.
The start event is configured by setting the SSC_TCMR. See Start.
The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See Frame
Synchronization.
To transmit data, the transmitter uses a shift register clocked by the transmit clock signal and the start mode selected
in the SSC_TCMR. Data is written by the application to the Transmit Holding register (SSC_THR) then transferred to
the transmit shift register according to the data format selected.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in the Status
register (SSC_SR). When the Transmit Holding register is transferred in the transmit shift register, the status flag
TXRDY is set in the SSC_SR and additional data can be loaded in the Transmit Holding register.
Figure 45-11. Transmit Block Diagram
SSC_CRTXEN
TXEN
SSC_SRTXEN
SSC_CRTXDIS
SSC_RCMR.START SSC_TCMR.START
RXEN
TXEN
TX Start
RX Start
Start
RF
Selector
RF
RC0R
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
SSC_TFMR.DATDEF
SSC_TFMR.MSBF
TX Controller
TX Start
Start
Selector
TD
Transmit Shift Register
SSC_TFMR.FSDEN
SSC_TCMR.STTDLY != 0
SSC_TFMR.DATLEN
0
SSC_THR
Transmit Clock
1
SSC_TSHR
SSC_TFMR.FSLEN
TX Controller counter reached STTDLY
45.8.3
Receive Operations
A receive frame is triggered by a start event and can be followed by synchronization data before data transmission.
The start event is configured by setting the Receive Clock Mode Register (SSC_RCMR). See Start.
The frame synchronization is configured by setting the Receive Frame Mode Register (SSC_RFMR). See Frame
Synchronization.
The receiver uses a shift register clocked by the receive clock signal and the start mode selected in the SSC_RCMR.
The data is transferred from the shift register depending on the data format selected.
When the receive shift register is full, the SSC transfers the data into the Receive Holding register (SSC_RHR), the
status flag RXRDY is set in the SSC_SR and the data can be read in the Receive Holding register. If another transfer
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
occurs before read of the Receive Holding register, the status flag OVRUN is set in the SSC_SR and the receive shift
register is transferred in the SSC_RHR. The old unread data is then lost.
Figure 45-12. Receive Block Diagram
SSC_CR.RXEN
SSC_SR.RXEN
SSC_CR.RXDIS
SSC_TCMR.START
SSC_RCMR.START
TXEN
RX Start
RF
Start
Selector
RXEN
RF
RC0R
Start
Selector
SSC_RFMR.MSBF
SSC_RFMR.DATNB
RX Start
RX Controller
RD
Receive Shift Register
SSC_RCMR.STTDLY != 0
load SSC_RSHR
SSC_RFMR.FSLEN
load
SSC_RHR
Receive Clock
SSC_RFMR.DATLEN
RX Controller counter reached STTDLY
45.8.4
Start
The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in
the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of
SSC_RCMR.
Under the following conditions the start event is independently programmable:
•
•
•
•
•
Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception
starts as soon as the receiver is enabled.
Synchronously with the transmitter/receiver
On detection of a falling/rising edge on TF/RF
On detection of a low level/high level on TF/RF
On detection of a level change or an edge on TF/RF
A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (SSC_RCMR/
SSC_TCMR). Thus, the start could be on TF (Transmit) or RF (Receive).
Moreover, the receiver can start when data is detected in the bit stream with the Compare Functions.
Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register
(SSC_TFMR/SSC_RFMR).
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
Figure 45-13. Transmit Start Mode
TK
TF
(Input)
Start = Low Level on TF
Start = Falling Edge on TF
Start = High Level on TF
Start = Rising Edge on TF
TD
(Output)
TD
(Output)
X
BO
X
TD
(Output)
TD
(Output)
B1
STTDLY
BO
X
BO
B1
STTDLY
BO
B1
BO
B1
BO
B1
BO
B1
BO
B1
X
X
STTDLY
B1
X
TD
(Output)
TD
Start = Level Change on TF
(Output)
Start = Any Edge on TF
BO
STTDLY
B1
STTDLY
STTDLY
Figure 45-14. Receive Pulse/Edge Start Modes
RK
RF
(Input)
Start = Low Level on RF
RD
(Input)
Start = Falling Edge on RF
RD
(Input)
Start = High Level on RF
Start = Rising Edge on RF
45.8.5
X
BO
X
RD
(Input)
Start = Level Change on RF
RD
(Input)
Start = Any Edge on RF
RD
(Input)
B1
STTDLY
BO
X
RD
(Input)
X
BO
B1
STTDLY
BO
B1
BO
B1
BO
B1
BO
B1
X
X
STTDLY
STTDLY
B1
STTDLY
STTDLY
Frame Synchronization
The Transmit and Receive Frame Sync pins, TF and RF, can be programmed to generate different kinds of Frame
Sync signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR)
and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform.
•
•
Programmable low or high levels during data transfer are supported.
Programmable high levels before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the
length of the pulse, from 1 bit time up to 256 bit times.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider
Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.
45.8.5.1 Frame Sync Data
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
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Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
During the Frame Sync signal, the receiver can sample the RD line and store the data in the Receive Sync Holding
Register and the transmitter can transfer Transmit Sync Holding Register in the shift register. The data length to be
sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR
and has a maximum value of 256.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay
between the start event and the current data reception, the data sampling operation is performed in the Receive Sync
Holding Register through the receive shift register.
The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN)
in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the
current data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding
Register is transferred in the Transmit Register, then shifted out.
45.8.5.2 Frame Sync Edge Detection
The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the
corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on Frame Sync Edge detection (signals
RF/TF).
45.8.6
Receive Compare Modes
Figure 45-15. Receive Compare Modes
RK
RD
(Input)
CMP0
CMP1
CMP2
CMP3
Ignored
B0
B1
B2
Start
FSLEN
STTDLY
DATLEN
45.8.6.1 Compare Functions
The length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is
defined by FSLEN, but with a maximum value of 256 bits. Comparison is always done by comparing the last bits
received with the comparison pattern. Compare 0 can be one start event of the receiver. In this case, the receiver
compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register
(SSC_RC0R). When this start event is selected, the user can program the receiver to start a new data transfer either
by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the
STOP bit in the SSC_RCMR.
45.8.7
Data Format
The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame
Mode Register (SSC_TFMR) and the Receive Frame Mode Register (SSC_RFMR). In either case, the user can
independently select the following parameters:
•
•
•
•
•
•
Event that starts the data transfer (START)
Delay in number of bit periods between the start event and the first data bit (STTDLY)
Length of the data (DATLEN)
Number of data to be transferred for each start event (DATNB)
Length of synchronization transferred for each start event (FSLEN)
Bit sense: most or least significant bit first (MSBF)
Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while
not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data
Default Value (DATDEF) bits in SSC_TFMR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1274
SAM9X60
Synchronous Serial Controller (SSC)
Table 45-2. Data Frame Registers
Transmitter
Receiver
Field
Length
Comment
SSC_TFMR
SSC_RFMR
DATLEN
Up to 32
Size of word
SSC_TFMR
SSC_RFMR
DATNB
Up to 16
Number of words transmitted in frame
SSC_TFMR
SSC_RFMR
MSBF
–
Most significant bit first
SSC_TFMR
SSC_RFMR
FSLEN
Up to 256
Size of Synchro data register
SSC_TFMR
–
DATDEF
0 or 1
Data default value ended
SSC_TFMR
–
FSDEN
–
Enable send SSC_TSHR
SSC_TCMR
SSC_RCMR
PERIOD
Up to 512
Frame size
SSC_TCMR
SSC_RCMR
STTDLY
Up to 255
Size of transmit start delay
Figure 45-16. Transmit and Receive Frame Format in Edge/Pulse Start Modes
Start
Start
PERIOD
(1)
TF/RF
FSLEN
TD
(If FSDEN = 1)
Sync Data
Data
Default
From SSC_THR
From DATDEF
Default
TD
(If FSDEN = 0)
RD
Data
From SSC_THR
Default
From SSC_TSHR From DATDEF
From DATDEF
Sync Data
Data
Data
From SSC_THR
Ignored
To SSC_RSHR
Default
From SSC_THR
Data
From DATDEF
Ignored
Data
To SSC_RHR
To SSC_RHR
DATLEN
DATLEN
STTDLY
Sync Data
Sync Data
DATNB
Note: 1. Example of input on falling edge of TF/RF.
In the example illustrated above, the SSC_THR is loaded twice. The FSDEN value has no effect on the transmission.
SyncData cannot be output in Continuous mode.
Figure 45-17. Transmit Frame Format in Continuous Mode (STTDLY = 0)
Start
TD
Data
Data
From SSC_THR
Default
From SSC_THR
DATLEN
DATLEN
Start: 1. TXEMPTY set to 1
2. Write into the SSC_THR
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Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
Figure 45-18. Receive Frame Format in Continuous Mode (STTDLY = 0)
Start = Enable Receiver
Data
Data
To SSC_RHR
To SSC_RHR
DATLEN
DATLEN
RD
45.8.8
Loop Mode
The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop
Mode (LOOP) bit in the SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is
connected to TK.
45.8.9
Interrupt
Most bits in the SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing
the Interrupt Enable Register (SSC_IER) and Interrupt Disable Register (SSC_IDR). These registers enable and
disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in the Interrupt Mask
Register (SSC_IMR), which controls the generation of interrupts by asserting the SSC interrupt line connected to the
interrupt controller.
Figure 45-19. Interrupt Block Diagram
SSC_IMR
SSC_IER
SSC_IDR
Set
Clear
Transmitter
TXRDY
TXEMPTY
TXSYN
Interrupt
Control
SSC Interrupt
Receiver
RXRDY
OVRUN
RXSYN
45.8.10 Register Write Protection
To prevent any single software error from corrupting SSC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the SSC Write Protection Mode Register (SSC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the SSC Write Protection Status Register
(SSC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading the SSC_WPSR.
The following registers can be write-protected:
•
•
•
SSC Clock Mode Register
SSC Receive Clock Mode Register
SSC Receive Frame Mode Register
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Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
•
•
•
•
SSC Transmit Clock Mode Register
SSC Transmit Frame Mode Register
SSC Receive Compare 0 Register
SSC Receive Compare 1 Register
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SAM9X60
Synchronous Serial Controller (SSC)
45.9
Register Summary
Note: Offsets 0x100–0x128 are reserved for PDC registers.
Offset
Name
0x00
SSC_CR
0x04
SSC_CMR
0x08
...
0x0F
0x10
0x14
0x18
0x1C
Bit Pos.
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
7
6
5
4
3
SWRST
2
1
0
TXDIS
RXDIS
TXEN
RXEN
DIV[11:8]
DIV[7:0]
Reserved
SSC_RCMR
SSC_RFMR
SSC_TCMR
SSC_TFMR
0x20
SSC_RHR
0x24
SSC_THR
0x28
...
0x2F
Reserved
0x30
SSC_RSHR
0x34
SSC_TSHR
0x38
SSC_RC0R
0x3C
SSC_RC1R
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
CKG[1:0]
MSBF
CKI
FSLEN_EXT[3:0]
FSOS[2:0]
PERIOD[7:0]
STTDLY[7:0]
STOP
CKO[2:0]
START[3:0]
CKS[1:0]
FSEDGE
FSLEN[3:0]
DATNB[3:0]
DATLEN[4:0]
LOOP
PERIOD[7:0]
STTDLY[7:0]
START[3:0]
CKG[1:0]
FSDEN
MSBF
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
CKI
FSLEN_EXT[3:0]
FSOS[2:0]
CKO[2:0]
CKS[1:0]
FSEDGE
FSLEN[3:0]
DATNB[3:0]
DATLEN[4:0]
DATDEF
RDAT[31:24]
RDAT[23:16]
RDAT[15:8]
RDAT[7:0]
TDAT[31:24]
TDAT[23:16]
TDAT[15:8]
TDAT[7:0]
RSDAT[15:8]
RSDAT[7:0]
TSDAT[15:8]
TSDAT[7:0]
CP0[15:8]
CP0[7:0]
CP1[15:8]
CP1[7:0]
Complete Datasheet
DS60001579C-page 1278
SAM9X60
Synchronous Serial Controller (SSC)
...........continued
Offset
Name
0x40
SSC_SR
0x44
0x48
0x4C
0x50
...
0xE3
0xE4
0xE8
SSC_IER
SSC_IDR
SSC_IMR
Bit Pos.
7
6
5
4
3
2
1
0
RXSYN
TXSYN
RXEN
TXEN
CP1
TXEMPTY
CP0
TXRDY
RXSYN
TXSYN
CP1
TXEMPTY
CP0
TXRDY
RXSYN
TXSYN
CP1
TXEMPTY
CP0
TXRDY
RXSYN
TXSYN
CP1
TXEMPTY
CP0
TXRDY
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
OVRUN
RXRDY
OVRUN
RXRDY
OVRUN
RXRDY
OVRUN
RXRDY
Reserved
SSC_WPMR
SSC_WPSR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
© 2020 Microchip Technology Inc.
WPKEY[23:16]
WPKEY[15:8]
WPKEY[7:0]
WPEN
WPVSRC[15:8]
WPVSRC[7:0]
WPVS
Complete Datasheet
DS60001579C-page 1279
SAM9X60
Synchronous Serial Controller (SSC)
45.9.1
SSC Control Register
Name:
Offset:
Reset:
Property:
Bit
SSC_CR
0x0
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SWRST
W
–
14
13
12
11
10
9
TXDIS
W
–
8
TXEN
W
–
7
6
5
4
3
2
1
RXDIS
W
–
0
RXEN
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 15 – SWRST Software Reset
Value
Description
0
No effect.
1
Performs a software reset. Has priority on any other bit in SSC_CR.
Bit 9 – TXDIS Transmit Disable
Value
Description
0
No effect.
1
Disables Transmit. If a character is currently being transmitted, disables at end of current character
transmission.
Bit 8 – TXEN Transmit Enable
Value
Description
0
No effect.
1
Enables Transmit if TXDIS is not set.
Bit 1 – RXDIS Receive Disable
Value
Description
0
No effect.
1
Disables Receive. If a character is currently being received, disables at end of current character
reception.
Bit 0 – RXEN Receive Enable
Value
Description
0
No effect.
1
Enables Receive if RXDIS is not set.
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Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
45.9.2
SSC Clock Mode Register
Name:
Offset:
Reset:
Property:
SSC_CMR
0x4
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
DIV[11:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DIV[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – DIV[11:0] Clock Divider
Value
Description
0
The Clock Divider is not active.
Any
The divided clock equals the peripheral clock divided by 2 times DIV.
other
The maximum bit rate is fperipheral clock/2. The minimum bit rate is fperipheral clock/2 × 4095 = fperipheral clock/
value
8190.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1281
SAM9X60
Synchronous Serial Controller (SSC)
45.9.3
SSC Receive Clock Mode Register
Name:
Offset:
Reset:
Property:
SSC_RCMR
0x10
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
Access
Reset
Bit
7
6
CKG[1:0]
Access
Reset
R/W
0
R/W
0
5
CKI
R/W
0
28
27
PERIOD[7:0]
R/W
R/W
0
0
20
19
STTDLY[7:0]
R/W
R/W
0
0
12
STOP
R/W
0
4
R/W
0
11
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
9
8
R/W
0
10
START[3:0]
R/W
0
R/W
0
R/W
0
3
CKO[2:0]
R/W
0
2
1
0
CKS[1:0]
R/W
0
R/W
0
R/W
0
Bits 31:24 – PERIOD[7:0] Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync signal. If
0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD + 1) Receive Clock.
Bits 23:16 – STTDLY[7:0] Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the current start of
reception. When the receiver is programmed to start synchronously with the transmitter, the delay is also applied.
Note:
STTDLY must be configured in relation to the receive synchronization data to be stored in SSC_RSHR.
Bit 12 – STOP Receive Stop Selection
Value
Description
0
After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer
and waits for a new compare 0.
1
After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare
1 is detected.
Bits 11:8 – START[3:0] Receive Start Selection
Value
Name
Description
0
CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
1
TRANSMIT
Transmit start
2
RF_LOW
Detection of a low level on RF signal
3
RF_HIGH
Detection of a high level on RF signal
4
RF_FALLING Detection of a falling edge on RF signal
5
RF_RISING
Detection of a rising edge on RF signal
6
RF_LEVEL
Detection of any level change on RF signal
7
RF_EDGE
Detection of any edge on RF signal
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1282
SAM9X60
Synchronous Serial Controller (SSC)
Value
8
Name
CMP_0
Description
Compare 0
Bits 7:6 – CKG[1:0] Receive Clock Gating Selection
Value
Name
Description
0
CONTINUOUS
None
1
EN_RF_LOW
Receive Clock enabled only if RF Low
2
EN_RF_HIGH
Receive Clock enabled only if RF High
Bit 5 – CKI Receive Clock Inversion
CKI affects only the Receive Clock and not the output clock signal.
Value
Description
0
The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame
Sync signal output is shifted out on Receive Clock rising edge.
1
The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame
Sync signal output is shifted out on Receive Clock falling edge.
Bits 4:2 – CKO[2:0] Receive Clock Output Mode Selection
Value
Name
Description
0
NONE
None, RK pin is an input
1
CONTINUOUS
Continuous Receive Clock, RK pin is an output
2
TRANSFER
Receive Clock only during data transfers, RK pin is an output
Bits 1:0 – CKS[1:0] Receive Clock Selection
Value
Name
Description
0
MCK
Divided Clock
1
TK
TK Clock signal
2
RK
RK pin
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1283
SAM9X60
Synchronous Serial Controller (SSC)
45.9.4
SSC Receive Frame Mode Register
Name:
Offset:
Reset:
Property:
SSC_RFMR
0x14
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
Bit
Access
Reset
Bit
31
R/W
0
23
Access
Reset
Bit
15
30
29
FSLEN_EXT[3:0]
R/W
R/W
0
0
22
28
27
26
19
18
25
24
FSEDGE
R/W
0
17
16
R/W
0
R/W
0
9
8
R/W
0
R/W
0
21
FSOS[2:0]
R/W
0
20
R/W
0
R/W
0
R/W
0
14
13
12
11
10
FSLEN[3:0]
DATNB[3:0]
Access
Reset
Bit
Access
Reset
7
MSBF
R/W
0
6
5
LOOP
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
DATLEN[4:0]
R/W
0
R/W
0
R/W
0
Bits 31:28 – FSLEN_EXT[3:0] FSLEN Field Extension
Extends FSLEN field. For details, see FSLEN: Receive Frame Sync Length.
Bit 24 – FSEDGE Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
Value
Name
Description
0
POSITIVE
Positive Edge Detection
1
NEGATIVE
Negative Edge Detection
Bits 22:20 – FSOS[2:0] Receive Frame Sync Output Selection
Value
Name
Description
0
NONE
None, RF pin is an input
1
NEGATIVE
Negative Pulse, RF pin is an output
2
POSITIVE
Positive Pulse, RF pin is an output
3
LOW
Driven Low during data transfer, RF pin is an output
4
HIGH
Driven High during data transfer, RF pin is an output
5
TOGGLING
Toggling at each start of data transfer, RF pin is an output
Bits 19:16 – FSLEN[3:0] Receive Frame Sync Length
This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is
selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to
be compared to the Compare 0 or Compare 1 register.
This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Receive Clock periods.
Bits 11:8 – DATNB[3:0] Data Number per Frame
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1284
SAM9X60
Synchronous Serial Controller (SSC)
Bit 7 – MSBF Most Significant Bit First
Value
Description
0
The lowest significant bit of the data register is sampled first in the bit stream.
1
The most significant bit of the data register is sampled first in the bit stream.
Bit 5 – LOOP Loop Mode
Value
Description
0
Normal operating mode.
1
RD is driven by TD, RF is driven by TF and TK drives RK.
Bits 4:0 – DATLEN[4:0] Data Length
Value
Description
0
Forbidden value (1-bit data length not supported).
Any
The bit stream contains DATLEN + 1 data bits.
other
value
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1285
SAM9X60
Synchronous Serial Controller (SSC)
45.9.5
SSC Transmit Clock Mode Register
Name:
Offset:
Reset:
Property:
SSC_TCMR
0x18
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
PERIOD[7:0]
R/W
R/W
0
0
20
19
STTDLY[7:0]
R/W
R/W
0
0
12
11
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
9
8
R/W
0
10
START[3:0]
Access
Reset
Bit
7
6
CKG[1:0]
Access
Reset
R/W
0
R/W
0
5
CKI
R/W
0
4
R/W
0
R/W
0
R/W
0
R/W
0
3
CKO[2:0]
R/W
0
2
1
0
CKS[1:0]
R/W
0
R/W
0
R/W
0
Bits 31:24 – PERIOD[7:0] Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync signal. If 0, no
period signal is generated. If not 0, a period signal is generated at each 2 × (PERIOD + 1) Transmit Clock.
Bits 23:16 – STTDLY[7:0] Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the current start of
transmission of data. When the transmitter is programmed to start synchronously with the receiver, the delay is also
applied.
Note:
If STTDLY is too short with respect to transmit synchronization data (SSC_TSHR), SSC_THR.TDAT is transmitted
instead of the end of SSC_TSHR.
Bits 11:8 – START[3:0] Transmit Start Selection
Value
Name
Description
0
CONTINUOUS Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled),
and immediately after the end of transfer of the previous data
1
RECEIVE
Receive start
2
TF_LOW
Detection of a low level on TF signal
3
TF_HIGH
Detection of a high level on TF signal
4
TF_FALLING
Detection of a falling edge on TF signal
5
TF_RISING
Detection of a rising edge on TF signal
6
TF_LEVEL
Detection of any level change on TF signal
7
TF_EDGE
Detection of any edge on TF signal
Bits 7:6 – CKG[1:0] Transmit Clock Gating Selection
Value
Name
Description
0
CONTINUOUS
None
1
EN_TF_LOW
Transmit Clock enabled only if TF Low
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1286
SAM9X60
Synchronous Serial Controller (SSC)
Value
2
Name
EN_TF_HIGH
Description
Transmit Clock enabled only if TF High
Bit 5 – CKI Transmit Clock Inversion
CKI affects only the Transmit Clock and not the Output Clock signal.
Value
Description
0
The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The
Frame Sync signal input is sampled on Transmit Clock rising edge.
1
The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The
Frame Sync signal input is sampled on Transmit Clock falling edge.
Bits 4:2 – CKO[2:0] Transmit Clock Output Mode Selection
Value
Name
Description
0
NONE
None, TK pin is an input
1
CONTINUOUS
Continuous Transmit Clock, TK pin is an output
2
TRANSFER
Transmit Clock only during data transfers, TK pin is an output
Bits 1:0 – CKS[1:0] Transmit Clock Selection
Value
Name
Description
0
MCK
Divided Clock
1
RK
RK Clock signal
2
TK
TK pin
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1287
SAM9X60
Synchronous Serial Controller (SSC)
45.9.6
SSC Transmit Frame Mode Register
Name:
Offset:
Reset:
Property:
SSC_TFMR
0x1C
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
Bit
Access
Reset
Bit
Access
Reset
Bit
31
R/W
0
23
FSDEN
R/W
0
15
30
29
FSLEN_EXT[3:0]
R/W
R/W
0
0
22
28
27
26
19
18
25
24
FSEDGE
R/W
0
17
16
0
0
9
8
R/W
0
R/W
0
21
FSOS[2:0]
R/W
0
20
R/W
0
0
0
14
13
12
11
10
FSLEN[3:0]
DATNB[3:0]
Access
Reset
Bit
Access
Reset
7
MSBF
R/W
0
6
5
DATDEF
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
3
1
0
R/W
0
R/W
0
2
DATLEN[4:0]
R/W
0
R/W
0
R/W
0
Bits 31:28 – FSLEN_EXT[3:0] FSLEN Field Extension
Extends FSLEN field. For details, seee FSLEN bit description below.
Bit 24 – FSEDGE Frame Sync Edge Detection
Determines which edge on frame synchronization will generate the interrupt TXSYN (Status Register).
Value
Name
Description
0
POSITIVE
Positive Edge Detection
1
NEGATIVE
Negative Edge Detection
Bit 23 – FSDEN Frame Sync Data Enable
Value
Description
0
The TD line is driven with the default value during the Transmit Frame Sync signal.
1
SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
Bits 22:20 – FSOS[2:0] Transmit Frame Sync Output Selection
Value
Name
Description
0
NONE
None, TF pin is an input
1
NEGATIVE
Negative Pulse, TF pin is an output
2
POSITIVE
Positive Pulse, TF pin is an output
3
LOW
Driven Low during data transfer
4
HIGH
Driven High during data transfer
5
TOGGLING
Toggling at each start of data transfer
Bits 19:16 – FSLEN[3:0] Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from SSC_TSHR if
FSDEN is 1.
This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Transmit Clock period.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1288
SAM9X60
Synchronous Serial Controller (SSC)
Bits 11:8 – DATNB[3:0] Data Number per Frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1).
Bit 7 – MSBF Most Significant Bit First
Value
Description
0
The lowest significant bit of the data register is shifted out first in the bit stream.
1
The most significant bit of the data register is shifted out first in the bit stream.
Bit 5 – DATDEF Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive
by the PIO Controller, the pin is enabled only if the SCC TD output is 1.
When the TD pin is configured in Multi-drive (Open-drain) mode by the PIO controller, a 0 is driven if SSC data output
equals 0 and the pin is in high-impedance when SSC data output is 1.
Bits 4:0 – DATLEN[4:0] Data Length
Value
Description
0
Forbidden value (1-bit data length not supported).
Any
The bit stream contains DATLEN + 1 data bits.
other
value
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1289
SAM9X60
Synchronous Serial Controller (SSC)
45.9.7
SSC Receive Holding Register
Name:
Offset:
Reset:
Property:
Bit
31
SSC_RHR
0x20
0x00000000
Read-only
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RDAT[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
RDAT[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RDAT[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RDAT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – RDAT[31:0] Receive Data
Right-aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1290
SAM9X60
Synchronous Serial Controller (SSC)
45.9.8
SSC Transmit Holding Register
Name:
Offset:
Reset:
Property:
Bit
31
SSC_THR
0x24
–
Write-only
30
29
28
27
26
25
24
W
–
W
–
W
–
W
–
19
18
17
16
W
–
W
–
W
–
W
–
11
10
9
8
W
–
W
–
W
–
W
–
3
2
1
0
W
–
W
–
W
–
W
–
TDAT[31:24]
Access
Reset
W
–
W
–
W
–
W
–
Bit
23
22
21
20
TDAT[23:16]
Access
Reset
W
–
W
–
W
–
W
–
Bit
15
14
13
12
TDAT[15:8]
Access
Reset
W
–
W
–
W
–
W
–
Bit
7
6
5
4
TDAT[7:0]
Access
Reset
W
–
W
–
W
–
W
–
Bits 31:0 – TDAT[31:0] Transmit Data
Right-aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1291
SAM9X60
Synchronous Serial Controller (SSC)
45.9.9
SSC Receive Synchronization Holding Register
Name:
Offset:
Reset:
Property:
Bit
SSC_RSHR
0x30
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
RSDAT[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RSDAT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – RSDAT[15:0] Receive Synchronization Data
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1292
SAM9X60
Synchronous Serial Controller (SSC)
45.9.10 SSC Transmit Synchronization Holding Register
Name:
Offset:
Reset:
Property:
Bit
SSC_TSHR
0x34
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
11
TSDAT[15:8]
R/W
R/W
0
0
4
TSDAT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TSDAT[15:0] Transmit Synchronization Data
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1293
SAM9X60
Synchronous Serial Controller (SSC)
45.9.11 SSC Receive Compare 0 Register
Name:
Offset:
Reset:
Property:
SSC_RC0R
0x38
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
CP0[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CP0[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CP0[15:0] Receive Compare Data 0
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1294
SAM9X60
Synchronous Serial Controller (SSC)
45.9.12 SSC Receive Compare 1 Register
Name:
Offset:
Reset:
Property:
SSC_RC1R
0x3C
0x00000000
Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
CP1[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CP1[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CP1[15:0] Receive Compare Data 1
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1295
SAM9X60
Synchronous Serial Controller (SSC)
45.9.13 SSC Status Register
Name:
Offset:
Reset:
Property:
Bit
SSC_SR
0x40
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RXEN
R
0
16
TXEN
R
0
15
14
13
12
11
RXSYN
R
0
10
TXSYN
R
0
9
CP1
R
0
8
CP0
R
0
7
6
5
OVRUN
R
0
4
RXRDY
R
0
3
2
1
TXEMPTY
R
0
0
TXRDY
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 17 – RXEN Receive Enable
Value
Description
0
Receive is disabled.
1
Receive is enabled.
Bit 16 – TXEN Transmit Enable
Value
Description
0
Transmit is disabled.
1
Transmit is enabled.
Bit 11 – RXSYN Receive Sync
Value
Description
0
An Rx Sync has not occurred since the last read of the Status Register.
1
An Rx Sync has occurred since the last read of the Status Register.
Bit 10 – TXSYN Transmit Sync
Value
Description
0
A Tx Sync has not occurred since the last read of the Status Register.
1
A Tx Sync has occurred since the last read of the Status Register.
Bit 9 – CP1 Compare 1
Value
Description
0
A compare 1 has not occurred since the last read of the Status Register.
1
A compare 1 has occurred since the last read of the Status Register.
Bit 8 – CP0 Compare 0
Value
Description
0
A compare 0 has not occurred since the last read of the Status Register.
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SAM9X60
Synchronous Serial Controller (SSC)
Value
1
Description
A compare 0 has occurred since the last read of the Status Register.
Bit 5 – OVRUN Receive Overrun
Value
Description
0
No data has been loaded in SSC_RHR while previous data has not been read since the last read of the
Status Register.
1
Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of
the Status Register.
Bit 4 – RXRDY Receive Ready
Value
Description
0
SSC_RHR is empty.
1
Data has been received and loaded in SSC_RHR.
Bit 1 – TXEMPTY Transmit Empty
Value
Description
0
Data remains in SSC_THR or is currently transmitted from TSR.
1
Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been
transmitted.
Bit 0 – TXRDY Transmit Ready
Value
Description
0
Data has been loaded in SSC_THR and is waiting to be loaded in the transmit shift register (TSR).
1
SSC_THR is empty.
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SAM9X60
Synchronous Serial Controller (SSC)
45.9.14 SSC Interrupt Enable Register
Name:
Offset:
Reset:
Property:
Bit
SSC_IER
0x44
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
RXSYN
W
–
10
TXSYN
W
–
9
CP1
W
–
8
CP0
W
–
7
6
5
OVRUN
W
–
4
RXRDY
W
–
3
2
1
TXEMPTY
W
–
0
TXRDY
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – RXSYN Rx Sync Interrupt Enable
Value
Description
0
No effect.
1
Enables the Rx Sync Interrupt.
Bit 10 – TXSYN Tx Sync Interrupt Enable
Value
Description
0
No effect.
1
Enables the Tx Sync Interrupt.
Bit 9 – CP1 Compare 1 Interrupt Enable
Value
Description
0
No effect.
1
Enables the Compare 1 Interrupt.
Bit 8 – CP0 Compare 0 Interrupt Enable
Value
Description
0
No effect.
1
Enables the Compare 0 Interrupt.
Bit 5 – OVRUN Receive Overrun Interrupt Enable
Value
Description
0
No effect.
1
Enables the Receive Overrun Interrupt.
Bit 4 – RXRDY Receive Ready Interrupt Enable
Value
Description
0
No effect.
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SAM9X60
Synchronous Serial Controller (SSC)
Value
1
Description
Enables the Receive Ready Interrupt.
Bit 1 – TXEMPTY Transmit Empty Interrupt Enable
Value
Description
0
No effect.
1
Enables the Transmit Empty Interrupt.
Bit 0 – TXRDY Transmit Ready Interrupt Enable
Value
Description
0
No effect.
1
Enables the Transmit Ready Interrupt.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Synchronous Serial Controller (SSC)
45.9.15 SSC Interrupt Disable Register
Name:
Offset:
Reset:
Property:
Bit
SSC_IDR
0x48
–
Write-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
RXSYN
W
–
10
TXSYN
W
–
9
CP1
W
–
8
CP0
W
–
7
6
5
OVRUN
W
–
4
RXRDY
W
–
3
2
1
TXEMPTY
W
–
0
TXRDY
W
–
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – RXSYN Rx Sync Interrupt Enable
Value
Description
0
No effect.
1
Disables the Rx Sync Interrupt.
Bit 10 – TXSYN Tx Sync Interrupt Enable
Value
Description
0
No effect.
1
Disables the Tx Sync Interrupt.
Bit 9 – CP1 Compare 1 Interrupt Disable
Value
Description
0
No effect.
1
Disables the Compare 1 Interrupt.
Bit 8 – CP0 Compare 0 Interrupt Disable
Value
Description
0
No effect.
1
Disables the Compare 0 Interrupt.
Bit 5 – OVRUN Receive Overrun Interrupt Disable
Value
Description
0
No effect.
1
Disables the Receive Overrun Interrupt.
Bit 4 – RXRDY Receive Ready Interrupt Disable
Value
Description
0
No effect.
© 2020 Microchip Technology Inc.
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SAM9X60
Synchronous Serial Controller (SSC)
Value
1
Description
Disables the Receive Ready Interrupt.
Bit 1 – TXEMPTY Transmit Empty Interrupt Disable
Value
Description
0
No effect.
1
Disables the Transmit Empty Interrupt.
Bit 0 – TXRDY Transmit Ready Interrupt Disable
Value
Description
0
No effect.
1
Disables the Transmit Ready Interrupt.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1301
SAM9X60
Synchronous Serial Controller (SSC)
45.9.16 SSC Interrupt Mask Register
Name:
Offset:
Reset:
Property:
Bit
SSC_IMR
0x4C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
RXSYN
R
0
10
TXSYN
R
0
9
CP1
R
0
8
CP0
R
0
7
6
5
OVRUN
R
0
4
RXRDY
R
0
3
2
1
TXEMPTY
R
0
0
TXRDY
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – RXSYN Rx Sync Interrupt Mask
Value
Description
0
The Rx Sync Interrupt is disabled.
1
The Rx Sync Interrupt is enabled.
Bit 10 – TXSYN Tx Sync Interrupt Mask
Value
Description
0
The Tx Sync Interrupt is disabled.
1
The Tx Sync Interrupt is enabled.
Bit 9 – CP1 Compare 1 Interrupt Mask
Value
Description
0
The Compare 1 Interrupt is disabled.
1
The Compare 1 Interrupt is enabled.
Bit 8 – CP0 Compare 0 Interrupt Mask
Value
Description
0
The Compare 0 Interrupt is disabled.
1
The Compare 0 Interrupt is enabled.
Bit 5 – OVRUN Receive Overrun Interrupt Mask
Value
Description
0
The Receive Overrun Interrupt is disabled.
1
The Receive Overrun Interrupt is enabled.
Bit 4 – RXRDY Receive Ready Interrupt Mask
Value
Description
0
The Receive Ready Interrupt is disabled.
© 2020 Microchip Technology Inc.
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SAM9X60
Synchronous Serial Controller (SSC)
Value
1
Description
The Receive Ready Interrupt is enabled.
Bit 1 – TXEMPTY Transmit Empty Interrupt Mask
Value
Description
0
The Transmit Empty Interrupt is disabled.
1
The Transmit Empty Interrupt is enabled.
Bit 0 – TXRDY Transmit Ready Interrupt Mask
Value
Description
0
The Transmit Ready Interrupt is disabled.
1
The Transmit Ready Interrupt is enabled.
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SAM9X60
Synchronous Serial Controller (SSC)
45.9.17 SSC Write Protection Mode Register
Name:
Offset:
Reset:
Property:
SSC_WPMR
0xE4
0x00000000
Read/Write
Bit
31
30
29
26
25
24
W
0
28
27
WPKEY[23:16]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
WPKEY[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
WPKEY[7:0]
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
WPEN
R/W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
Value
Name
Description
0x535343 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads
as 0.
Bit 0 – WPEN Write Protection Enable
See Register Write Protection for the list of registers that can be protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
© 2020 Microchip Technology Inc.
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SAM9X60
Synchronous Serial Controller (SSC)
45.9.18 SSC Write Protection Status Register
Name:
Offset:
Reset:
Property:
Bit
SSC_WPSR
0xE8
0x00000000
Read-only
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
WPVSRC[15:8]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
WPVSRC[7:0]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
4
2
1
0
WPVS
R
0
Access
Reset
3
Access
Reset
Bits 23:8 – WPVSRC[15:0] Write Protect Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 0 – WPVS Write Protection Violation Status
Value
Description
0
No write protection violation has occurred since the last read of the SSC_WPSR.
1
A write protection violation has occurred since the last read of the SSC_WPSR. If this violation is an
unauthorized attempt to write a protected register, the associated violation is reported into field
WPVSRC.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
46.
Flexible Serial Communication Controller (FLEXCOM)
46.1
Description
The Flexible Serial Communication Controller (FLEXCOM) offers several serial communication protocols that are
managed by the three submodules USART, SPI, and TWI.
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full-duplex universal
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error
detection. The receiver timeout enables handling variable-length frames and the transmitter timeguard facilitates
communications with slow remote devices. Multidrop communications are also supported through address bit
handling in reception and transmission.
The USART features three test modes: Remote Loopback, Local Loopback and Automatic Echo.
The USART supports specific operating modes providing interfaces on RS485, LIN, LON, , with ISO7816 T = 0 or T =
1 smart card slots, and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control
by automatic management of the pins RTS and CTS.
The USART supports the connection to the DMA Controller, which enables data transfers to the transmitter and from
the receiver. The DMAC provides chained buffer management without any intervention of the processor.
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with
external devices in Master or Slave mode. It also enables communication between processors if an external
processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a
data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as
“slaves” which have data shifted into and out by the master. Different CPUs can take turn being masters (multiple
master protocol, contrary to single master protocol where one CPU is always the master while all of the others are
always slaves). One master can simultaneously shift data into multiple slaves. However, only one slave can drive its
output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master
generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
•
•
•
•
Master Out Slave In (MOSI)—This data line supplies the output data from the master shifted into the input(s) of
the slave(s).
Master In Slave Out (MISO)—This data line supplies the output data from a slave to the input of the master.
There may be no more than one slave transmitting data during any particular transfer.
Serial Clock (SPCK)—This control line is driven by the master and regulates the flow of the data bits. The
master can transmit data at a variety of baud rates; there is one SPCK pulse for each bit that is transmitted.
Slave Select (NSS)—This control line allows slaves to be turned on and off by hardware.
The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and
one data line with speeds of up to 400 kbits per second in Fast mode and up to 3.4 Mbits per second in High-speed
Slave mode only, based on a byte-oriented transfer format. It can be used with any Two-wire Interface bus Serial
EEPROM and I2C-compatible devices, such as a Real-Time Clock (RTC), Dot Matrix/Graphic LCD Controller and
temperature sensor. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple
master capability is supported.
Arbitration of the bus is performed internally and puts the TWI in Slave mode automatically if the bus arbitration is
lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock
frequencies.
The following table lists the compatibility level of any Two-wire Interface in Master mode and a full I2C compatible
device.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Table 46-1. TWI Compatibility with I2C Standard
I2C Standard
TWI
Standard Mode Speed (100 kHz)
Supported
Fast Mode Speed (400 kHz)
Supported
Fast Mode Plus (1 MHz)
Supported
High-speed Mode (3.4 MHz)
Supported
7- or 10-bit(1) Slave Addressing
Supported
Repeated Start (Sr) Condition
Supported
ACK and NACK Management
Supported
Input Filtering
Supported
Slope Control
Not Supported
Clock Stretching
Supported
Multi Master Capability
Supported
Notes: 1. 10-bit support in Master mode only
46.2
Embedded Characteristics
46.2.1
USART/UART Characteristics
•
•
•
•
•
•
•
•
•
•
16-byte Transmit and Receive FIFOs
Programmable Baud Rate Generator
Baud Rate can be Independent of the Processor/Peripheral Clock
Comparison Function on Received Character
5-bit to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
– 1, 1.5 or 2 stop bits in Asynchronous mode or 1 or 2 stop bits in Synchronous mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– Digital filter on receive line
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by 16 oversampling receiver frequency
– Optional hardware handshaking RTS-CTS
– Receiver timeout and transmitter timeguard
– Optional Multidrop mode with address generation and detection
RS485 with Driver Control Signal
ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
– NACK handling, error counter with repetition and iteration limit
IrDA Modulation and Demodulation
– Communication at up to 115.2 kbit/s
Up to 16-bit data, Manchester-encoded Frame Support
LIN Mode
– Compliant with LIN 1.3 and LIN 2.0 specifications
– Master or slave
– Processing of frames with up to 256 data bytes
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
•
•
•
•
46.2.2
– Response data length can be configurable or defined automatically by the identifier
– Self-synchronization in slave node configuration
– Automatic processing and verification of the “synch break” and the “synch field”
– “Synch break” detection even when partially superimposed with a data byte
– Automatic identifier parity calculation/sending and verification
– Parity sending and verification can be disabled
– Automatic checksum calculation/sending and verification
– Checksum sending and verification can be disabled
– Support both “classic” and “enhanced” checksum types
– Full LIN error checking and reporting
– Frame Slot mode: master allocates slots to the scheduled frames automatically
– Generation of the wakeup signal
LON Mode
– Compliant with CEA-709 specification
– Full-layer 2 implementation
– Differential Manchester encoding/decoding (CDP)
– Preamble generation including bit- and byte-sync fields
– LON timings handling (beta1, beta2, IDT, etc.)
– CRC generation and checking
– Automated random number generation
– Backlog calculation and update
– Collision detection support
– Supports both comm_type = 1 and comm_type = 2 modes
– Clock drift tolerance up to 16%
– Optimal for node-to-node communication (no embedded digital line filter)
Test Modes
– Remote loopback, local loopback, automatic echo
Supports Connection of:
– Two DMA Controller (DMAC) channels
– Offers buffer transfer without processor intervention
Register Write Protection
SPI Characteristics
•
•
•
•
•
•
•
•
•
16-byte Transmit and Receive FIFOs
Master or Slave Serial Peripheral Bus Interface
– 8-bit to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delay between consecutive transfers and delay before SPI clock per chip select
– Programmable delay between chip selects
Selectable Mode Fault Detection
Master Mode Can Drive SPCK up to Peripheral Clock
Master Mode Bit Rate Can Be Independent of the Processor/Peripheral Clock
Slave Mode Operates on SPCK, Asynchronously with Core and Bus Clock
Four Chip Selects with External Decoder Support Allow Communication with up to 15Peripherals
Communication with Serial External Devices Supported
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and sensors
– External coprocessors
Connection to DMA Channel Capabilities, Optimizing Data Transfers
– One channel for the receiver
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Complete Datasheet
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
•
TWI/SMBus Characteristics
•
•
•
•
•
•
•
•
•
•
•
•
Block Diagram
Figure 46-1. FLEXCOM Block Diagram
FLEXCOM
Channel
PIO
Controller
TX trigger event
Pads
MR
RX trigger event
DMA Controller
USART
txd,rxd,
sck,
rts,cts
SPI
mosi,
miso,
spck,
npcs0/1
clock1
Channel
mux
FLEXCOM Interrupt
mux
Interrupt
Controller
MR
46.3
16-byte Transmit and Receive FIFOs
Bit Rate: 1 Mbit/s in Fast Mode Plus and 3.4 Mbit/s in High-Speed Mode
Bit Rate can be Independent of the Processor/Peripheral Clock
SMBus Support
Compatible with Two-wire Interface Serial Memory and I2C Compatible Devices(1)
Master and Multi-Master Operation (Standard and Fast Mode Only)
Slave Mode Operation (Standard, Fast and High-Speed Mode)
One, Two or Three Bytes for Slave Address
Sequential Read/Write Operations
General Call Supported in Slave Mode
Connection to DMA Controller Channels Optimizes Data Transfers
– One channel for the receiver
– One channel for the transmitter
Register Write Protection
(1) See table TWI Compatibility with I2C Standard for further details.
mux
46.2.3
– One channel for the transmitter
Register Write Protection
FLEXCOM
I/Os
clock2
twd,
twck
Bus clock
TWI
clock3
Peripheral Bridge
FLEX_MR = MR
FLEXCOM
User
Interface
MR=1
Peripheral clock
MR=2
MR=3
PMC
GCLK
bus-independent
clock
© 2020 Microchip Technology Inc.
to USART, SPI, and TWI
Complete Datasheet
DS60001579C-page 1309
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
46.4
I/O Lines Description
Table 46-2. I/O Lines Description
Name
Description
Type
USART/UART
SPI
TWI
FLEXCOM_IO0
TXD
MOSI
TWD
I/O
FLEXCOM_IO1
RXD
MISO
TWCK
I/O
FLEXCOM_IO2
SCK
SPCK
–
I/O
FLEXCOM_IO3
CTS
NPCS0/NSS
–
I/O
FLEXCOM_IO4
RTS
NPCS1
–
O
FLEXCOM_IO5
–
NPCS2
–
O
FLEXCOM_IO6
–
NPCS3
–
O
46.5
Product Dependencies
46.5.1
I/O Lines
The pins used for interfacing the FLEXCOM are multiplexed with the PIO lines. The programmer must first program
the PIO controller to assign the desired FLEXCOM pins to their peripheral function. If I/O lines of the FLEXCOM are
not used by the application, they can be used for other purposes by the PIO Controller.
46.5.2
Power Management
The peripheral clock is not continuously provided to the FLEXCOM. The programmer must first enable the FLEXCOM
Clock in the Power Management Controller (PMC) before using the USART or SPI or TWI.
46.5.3
Interrupt Sources
The FLEXCOM interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the
FLEXCOM interrupt requires the Interrupt Controller to be programmed first.
46.6
Register Accesses
Register accesses support 8-bit, 16-bit and 32-bit accesses, which means that only an 8-bit part of a 32-bit register
can be written in one access, for instance. For this the access must be done with the right size at the right address.
8-bit, 16-bit and 32-bit accesses are supported for register accesses. However, a field in a register cannot be partially
written (e.g., if a field is bigger than 8 bits, the whole field must be written).
This feature helps avoiding a read-modify-write process if only a small part of the register is to be modified.
46.7
USART Functional Description
46.7.1
Baud Rate Generator
The baud rate generator provides the bit period clock named “baud rate clock” to both the receiver and the
transmitter.
Configuring the USCLKS field in FLEX_US_MR selects the baud rate generator clock from one of the following
sources:
•
the peripheral clock
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
•
•
•
a division of the peripheral clock, the divider being product dependent, but generally set to 8
a fully programmable generic clock (GCLK) provided by PMC and independent of processor/peripheral clock
the external clock, available on the SCK pin
The baud rate generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate
Generator Register (FLEX_US_BRGR). If a zero is written to CD, the baud rate generator does not generate any
clock. If a one is written to CD, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin
must be longer than a peripheral clock period. The frequency of the signal provided on SCK must be at least three
times lower than peripheral clock .
If GCLK is selected, the baud rate is independent of the processor/peripheral clock and thus processor/peripheral
clock frequency can be changed without affecting the USART transfer. The GCLK frequency must be at least three
times lower than peripheral clock frequency.
If GCLK is selected (USCLKS = 2) and the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.
Figure 46-2. Baud Rate Generator
USCLKS
CD
CD
Peripheral clock
0
Peripheral clock/DIV
1
GCLK
2
16-bit Counter
FIDI
>1
3
SCK
SCK
1
0
SYNC
OVER
0
0
Sampling
Divider
0
Baud Rate Clock
1
1
SYNC
Sampling Clock
USCLKS = 3
46.7.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in Asynchronous mode, the selected clock is first divided by CD, which is
field-programmed in FLEX_US_BRGR. The resulting clock is provided to the receiver as a sampling clock and then
divided by 16 or 8, depending on the programming of FLEX_US_MR.OVER.
If OVER is set, the receiver sampling is eight times higher than the baud rate clock. If OVER is cleared, the sampling
is performed at 16 times the baud rate clock.
The baud rate is calculated as per the following formula:
Baud rate =
Selected Clock
8 2 − OVER CD
This gives a maximum baud rate of peripheral clock divided by 8, assuming that peripheral clock is the highest
possible clock and that the OVER bit is set.
46.7.1.1.1 Baud Rate Calculation Example
The following table shows calculations of CD to obtain a baud rate at 38,400 bit/s for different source clock
frequencies. It also shows the actual resulting baud rate and the error.
Table 46-3. Baud Rate Example (OVER = 0)
Source Clock
(MHz)
Expected Baud Rate
(bit/s)
Calculation Result
CD
Actual Baud Rate
(bit/s)
Error
3,686,400
38,400
6.00
6
38,400.00
0.00%
4,915,200
38,400
8.00
8
38,400.00
0.00%
5,000,000
38,400
8.14
8
39,062.50
1.70%
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1311
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
...........continued
Source Clock
(MHz)
Expected Baud Rate
(bit/s)
Calculation Result
CD
Actual Baud Rate
(bit/s)
Error
7,372,800
38,400
12.00
12
38,400.00
0.00%
8,000,000
38,400
13.02
13
38,461.54
0.16%
12,000,000
38,400
19.53
20
37,500.00
2.40%
12,288,000
38,400
20.00
20
38,400.00
0.00%
14,318,180
38,400
23.30
23
38,908.10
1.31%
14,745,600
38,400
24.00
24
38,400.00
0.00%
18,432,000
38,400
30.00
30
38,400.00
0.00%
24,000,000
38,400
39.06
39
38,461.54
0.16%
24,576,000
38,400
40.00
40
38,400.00
0.00%
25,000,000
38,400
40.69
40
38,109.76
0.76%
32,000,000
38,400
52.08
52
38,461.54
0.16%
32,768,000
38,400
53.33
53
38,641.51
0.63%
33,000,000
38,400
53.71
54
38,194.44
0.54%
40,000,000
38,400
65.10
65
38,461.54
0.16%
50,000,000
38,400
81.38
81
38,580.25
0.47%
The baud rate is calculated with the following formula:
Baud rate = MCK / CD × 16
The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than
5%.
Error = 1 −
Expected Baud Rate
Actual Baud Rate
46.7.1.2 Fractional Baud Rate in Asynchronous Mode
The baud rate generator previously defined is subject to the following limitation: the output frequency changes by only
integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator
that has a high resolution. The generator architecture is modified to obtain baud rate changes by a fraction of the
reference source clock. This fractional part is programmed with the FP field in FLEX_US_BRGR. If FP is not 0, the
fractional part is activated. The resolution is one eighth of the clock divider. The fractional baud rate is calculated
using the following formula:
Baud rate =
Selected Clock
FP
8 2 − OVER CD + 8
The modified architecture is presented in the following figure.
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-3. Fractional Baud Rate Generator
FP
USCLKS
CD
Modulus
Control
FP
SCK
(CLKO = 1)
CD
Peripheral clock
0
Peripheral clock/DIV
1
PMC.GCLK
2
SCK
3
16-bit Counter
Glitch-free
Logic
1
(CLKO = 0)
0
FIDI
>1
0
SYNC
OVER
0
Sampling
Divider
0
Baud Rate
Clock
1
1
SYNC
Sampling
Clock
USCLKS = 3
WARNING
When the value of field FP is greater than 0, the SCK (oversampling clock) generates nonconstant duty
cycles. The SCK high duration is increased by “selected clock” period from time to time. The duty cycle
depends on the value of the CD field.
46.7.1.3 Baud Rate in Synchronous Mode
If the USART is programmed to operate in Synchronous mode, the selected clock is simply divided by the CD field in
FLEX_US_BRGR:
Baud rate =
Selected Clock
CD
In Synchronous mode, if the external clock is selected (USCLKS = 3) and CLKO = 0 (Slave mode), the clock is
provided directly by the signal on the USART SCK pin. No division is active. The value written in FLEX_US_BRGR
has no effect. The external clock frequency must be at least three times lower than the system clock. In Synchronous
mode master (USCLKS = 0 or 1, CLKO = 1), the receive part limits the SCK maximum frequency to fperipheral clock/3 .
When either the external clock SCK or the internal clock divided (peripheral clock/DIV or GCLK) is selected, the value
programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the peripheral
clock is selected, the baud rate generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed
in CD is odd.
46.7.1.4 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
�=
Di
�
Fi
where:
•
•
•
•
B is the bit rate
Di is the bit rate adjustment factor
Fi is the clock frequency division factor
f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in the following table.
Table 46-4. Binary and Decimal Values for Di
DI field
0001
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0010
0011
0100
0101
Complete Datasheet
0110
1000
1001
DS60001579C-page 1313
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Di (decimal)
1
2
4
8
16
32
12
20
Fi is a binary value encoded on a 4-bit field, named FI, as represented in the following table.
Table 46-5. Binary and Decimal Values for Fi
FI field
0000
0001
0010
0011
0100
0101
0110
1001
1010
1011
1100
1101
Fi (decimal)
372
372
558
744
1116
1488
1860
512
768
1024
1536
2048
The following table shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate
clock.
Table 46-6. Possible Values for the Fi/Di Ratio
Fi/Di
372
558
744
1116
1488
1806
512
768
1024
1536
2048
1
372
558
744
1116
1488
1860
512
768
1024
1536
2048
2
186
279
372
558
744
930
256
384
512
768
1024
4
93
139.5
186
279
372
465
128
192
256
384
512
8
46.5
69.75
93
139.5
186
232.5
64
96
128
192
256
16
23.25
34.87
46.5
69.75
93
116.2
32
48
64
96
128
32
11.62
17.43
23.25
34.87
46.5
58.13
16
24
32
48
64
12
31
46.5
62
93
124
155
42.66
64
85.33
128
170.6
20
18.6
27.9
37.2
55.8
74.4
93
25.6
38.4
51.2
76.8
102.4
If the USART is configured in ISO7816 mode, the clock selected by the USCLKS field in FLEX_US_MR is first
divided by the value programmed in field CD field in FLEX_US_BRGR. The resulting clock can be provided to the
SCK pin to feed the smart card clock inputs. This means that FLEX_US_MR.CLKO can be set.
This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI DI Ratio Register
(FLEX_US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 65535 in ISO7816
mode. The noninteger values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field
to a value as close as possible to the expected value.
The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the
ISO7816 clock and the bit rate (Fi = 372, Di = 1).
The following figure shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO
7816 clock.
Figure 46-4. Elementary Time Unit (ETU)
FI_DI_RATIO
ISO7816 Clock Cycles
ISO7816 Clock
on SCK
ISO7816 I/O Line
on TXD
1 ETU
46.7.2
Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the USART Control
Register (FLEX_US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in FLEX_US_CR. However,
the transmitter registers can be programmed before being enabled.
The receiver and the transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the
corresponding bit, RSTRX and RSTTX respectively, in FLEX_US_CR. The software resets clear the status flag and
reset internal state machines but the user interface configuration registers hold the value configured prior to software
reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in
FLEX_US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of
the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART
waits the end of transmission of both the current character and character being stored in the USART Transmit
Holding Register (FLEX_US_THR). If a timeguard is programmed, it is handled normally.
46.7.3
Synchronous and Asynchronous Modes
46.7.3.1 Transmitter Operations
The transmitter performs the same in both Synchronous and Asynchronous operating modes (SYNC = 0 or SYNC =
1). One start bit, up to 9 data bits, 1 optional parity bit and up to 2 stop bits are successively shifted out on the TXD
pin at each falling edge of the programmed serial clock.
The number of data bits is selected by the CHRL field and the MODE9 bit in FLEX_US_MR. Nine bits are selected by
setting the MODE9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in FLEX_US_MR.
The even, odd, space, marked or none parity bit can be configured. The MSBF bit in FLEX_US_MR configures which
data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent first.
The number of stop bits is selected by the NBSTOP field in FLEX_US_MR. The 1.5 stop bit is supported in
Asynchronous mode only.
Figure 46-5. Character Transmit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
TXD
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
The characters are sent by writing in FLEX_US_THR. The transmitter reports two status bits in the USART Channel
Status Register (FLEX_US_CSR): TXRDY (Transmitter Ready), which indicates that FLEX_US_THR is empty and
TXEMPTY, which indicates that all the characters written in FLEX_US_THR have been processed. When the current
character processing is completed, the last character written in FLEX_US_THR is transferred into the shift register of
the transmitter and FLEX_US_THR is emptied, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in FLEX_US_THR
while TXRDY is low has no effect and the written character is lost.
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-6. Transmitter Status
Baud Rate
Clock
TXD
Start D0
Bit
Write
FLEX_US_THR
D1
D2
D3
D4
D5
D6
D7 Parity Stop Start D0
Bit Bit Bit
D1
D2
D3
D4
D5
D6
D7 Parity Stop
Bit Bit
1
1 bit time = USART internal resynchronization time
TXRDY
TXEMPTY
46.7.3.2 Manchester Encoder
When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase
Manchester II format. To enable this mode, set the FLEX_US_MR.MAN bit to 1. Depending on polarity configuration,
a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always
occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the
receiver has more error control since the expected input must show a change at the center of a bit cell. An example
of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the
default polarity of the encoder. The following figure illustrates this coding scheme.
Figure 46-7. NRZ to Manchester Encoding
NRZ
encoded
data
Manchester
encoded
data
1
0
1
1
0
0
0
1
Txd
The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start
frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a
predefined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble
waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences:
ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the FLEX_US_MAN.TX_PP field. The TX_PL field is
used to configure the preamble length. The following figure illustrates and defines the valid patterns. To improve
flexibility, the encoding scheme can be configured using the FLEX_US_MAN.TX_MPOL bit. If the TX_MPOL bit is set
to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero
transition. If the TX_MPOL bit is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is
encoded with a zero-to-one transition.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-8. Preamble Patterns, Default Polarity Assumed
Manchester
encoded
data
Txd
SFD
DATA
SFD
DATA
SFD
DATA
SFD
DATA
8-bit "ALL_ONE" Preamble
Manchester
encoded
data
Txd
8-bit "ALL_ZERO" Preamble
Manchester
encoded
data
Txd
8-bit "ZERO_ONE" Preamble
Manchester
encoded
data
Txd
8-bit "ONE_ZERO" Preamble
A start frame delimiter is to be configured using the FLEX_US_MR.ONEBIT bit. It consists of a user-defined pattern
that indicates the beginning of a valid data. The following figure illustrates these patterns. If the start frame delimiter,
also known as the start bit, is one bit, (ONEBIT = 1), a logic zero is Manchester encoded and indicates that a new
character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as
sync (ONEBIT = 0), a sequence of three bit times is sent serially on the line to indicate the start of a new character.
The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit
time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one
level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the
FLEX_US_MR.MODSYNC bit is set to 1, the next character is a command. If it is set to 0, the next character is a
data. When direct memory access is used, the MODSYNC bit can be immediately updated with a modified character
located in memory. To enable this mode, the FLEX_US_MR.VAR_SYNC bit must be set. In this case, the
FLEX_US_MR.MODSYNC bit is bypassed and the sync configuration is held in the FLEX_US_THR.TXSYNH bit.
The USART character format is modified and includes sync information.
Figure 46-9. Start Frame Delimiter
Preamble Length
is set to 0
Manchester
encoded
data
SFD
DATA
Txd
One bit start frame delimiter
Manchester
encoded
data
Manchester
encoded
data
SFD
DATA
Txd
SFD
Txd
Command Sync
start frame delimiter
DATA
Data Sync
start frame delimiter
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
46.7.3.2.1 Drift Compensation
Drift compensation is available only in 16X Oversampling mode. An hardware recovery system allows a larger clock
drift. To enable the hardware system, the bit in the FLEX_US_MAN register must be set. If the RXD edge is one 16X
clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD
event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock
cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is
lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically
taken.
Figure 46-10. Bit Resynchronization
Oversampling
16x Clock
RXD
Sampling
point
Expected edge
Synchro.
Error
Synchro.
Jump
Tolerance
Synchro.
Jump
Synchro.
Error
46.7.3.3 Asynchronous Receiver
If the USART is programmed in Asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input
line. The oversampling is either 16 or 8 times the baud rate clock, depending on the FLEX_US_MR.OVER bit.
The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected and
data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16 (OVER = 0), a start is detected at the eighth sample to 0. Data bits, parity bit and stop bit
are assumed to have a duration corresponding to 16 oversampling clock cycles. If the oversampling is 8 (OVER = 1),
a start bit is detected at the fourth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration
corresponding to 8 oversampling clock cycles.
The number of data bits, first bit sent and Parity mode are selected by the same fields and bits as the transmitter, i.e.,
respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has
no effect on the receiver as it considers only one stop bit, regardless of the NBSTOP field, so that resynchronization
between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts
looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with
one stop bit.
The following figures illustrate start detection and character reception when USART operates in Asynchronous mode.
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Complete Datasheet
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-11. Asynchronous Start Detection
Baud Rate
Clock
Sampling
Clock (x16)
RXD
Sampling
1
2
3
4
5
6
7
8
1
2
3
4
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
D0
Sampling
Start
Detection
RXD
Sampling
1
2
3
4
5
6
7
0 1
Start
Rejection
Figure 46-12. Asynchronous Character Reception
Example: 8-bit, Parity Enabled
Baud Rate
Clock
RXD
Start
Detection
16
16
16
16
16
16
16
16
16
16
samples samples samples samples samples samples samples samples samples samples
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
46.7.3.4 Manchester Decoder
When the FLEX_US_MR.MAN bit is set, the Manchester decoder is enabled. The decoder performs both preamble
and start frame delimiter detection. One input line is dedicated to Manchester encoded input data.
An optional preamble sequence can be defined. Its length is user-defined and totally independent of the transmitter
side. Use the FLEX_US_MAN.RX_PL field to configure the length of the preamble sequence. If the length is set to 0,
no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable
with the FLEX_US_MAN.RX_MPOL bit. Depending on the desired application, the preamble pattern matching is to
be defined via the FLEX_US_MAN.RX_PP field. See figure Preamble Patterns, Default Polarity Assumed for
available preamble patterns.
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT bit =
1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT = 0, only a sync
pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If
RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See the following figure. The sample
pulse rejection mechanism applies.
The FLEX_US_MAN.RXIDLEV bit informs the USART of the receiver line idle state value (receiver line inactive). The
user must define RXIDLEV to ensure reliable synchronization. By default, RXIDLEV is set to one (receiver line is at
level 1 when there is no activity).
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-13. Asynchronous Start Bit Detection
Sampling
Clock
(16 x)
Manchester
encoded
data
Txd
1
2
3
4
Start
Detection
The receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and
then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding
with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the
receiver resynchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters
of a bit time.
If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded
into NRZ data and passed to USART for processing. The following figure illustrates Manchester pattern mismatch.
When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A
code violation is a lack of transition in the middle of a bit cell. In this case, the MANE flag in FLEX_US_CSR is raised.
It is cleared by writing a one to FLEX_US_CR.RSTSTA. See figure "Manchester Error Flag" below for an example of
Manchester error detection during the data phase.
Figure 46-14. Preamble Pattern Mismatch
Preamble Mismatch
Manchester coding error
Manchester
encoded
data
Preamble Mismatch
invalid pattern
SFD
Txd
DATA
Preamble Length is set to 8
Figure 46-15. Manchester Error Flag
Preamble Length is set to 4
Manchester
encoded
data
SFD
Elementary character bit time
Txd
Entering USART character area
Sampling points
Preamble subpacket
and Start Frame Delimiter
were successfully
decoded
Manchester
Coding Error
detected
When the start frame delimiter is a sync pattern (ONEBIT = 0), both command and data delimiter are supported. If a
valid sync is detected, the received character is written as RXCHR field in the Receive Holding Register
(FLEX_US_RHR) and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it
is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as
the character contains its own sync field in the same register.
As the decoder is setup to be used in Unipolar mode, the first bit of the frame has to be a zero-to-one transition.
46.7.3.5 Radio Interface: Manchester Encoded USART Application
This section describes low data rate RF transmission systems and their integration with a Manchester encoded
USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes.
© 2020 Microchip Technology Inc.
Complete Datasheet
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
The goal is to perform full-duplex radio transmission of characters using two different frequency carriers. See
configuration in the following figure.
Figure 46-16. Manchester Encoded Characters RF Transmission
Fup frequency carrier
ASK/FSK
upstream receiver
Upstream
transmitter
LNA
VCO
RF filter
Demod
Control
Fdown frequency carrier
Serial
Configuration
Interface
bi-dir
line
ASK/FSK
downstream transmitter
Downstream
receiver
Manchester
decoder
USART
receiver
Manchester
encoder
USART
transmitter
PA
RF filter
Mod
VCO
Control
The USART peripheral is configured as a Manchester encoder/decoder. Looking at the downstream communication
channel, Manchester encoded characters are serially sent to the RF transmitter. This may also include a user defined
preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data
from a transmitter and signals due to noise. The Manchester stream is then modulated. See the following figure for
an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred
to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF
signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a
logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See
figure "FSK Modulator Output" below.
From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining
demodulated data stream. If a valid pattern is detected, the receiver switches to Receiving mode. The demodulated
stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the
microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in
accordance with the RF IC configuration.
Figure 46-17. ASK Modulator Output
1
0
0
1
NRZ stream
Manchester
encoded
data
default polarity
unipolar output
Txd
ASK Modulator
Output
Upstream Frequency F0
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-18. FSK Modulator Output
1
0
0
1
NRZ stream
Manchester
encoded
data
default polarity
unipolar output
Txd
FSK Modulator
Output
Uptstream Frequencies
[F0, F0+offset]
46.7.3.6 Synchronous Receiver
In Synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate clock. If
a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the
receiver waits for the next start bit. Synchronous mode operations provide a high-speed transfer capability.
Configuration fields and bits are the same as in Asynchronous mode.
The following figure illustrates a character reception in Synchronous mode.
Figure 46-19. Synchronous Mode Character Reception
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
RXD
Sampling
D0
Start
D1
D2
D3
D4
D5
D6
D7
Stop Bit
Parity Bit
46.7.3.7 Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding Register (FLEX_US_RHR) and the
FLEX_US_CSR.RXRDY bit is raised. If a character is completed while the RXRDY is set, the Overrun Error (OVRE)
bit is set. The last character is transferred into FLEX_US_RHR and overwrites the previous one. The OVRE bit is
cleared by writing a one to Reset Status bit FLEX_US_CR.RSTSTA.
Figure 46-20. Receiver Status
Baud Rate
Clock
RXD
Start D0
Bit
D1
D2
D3
D4
D5
D6
D7 Parity Stop Start D0
Bit Bit Bit
D1
D2
D3
D4
D5
D6
D7 Parity Stop
Bit Bit
RSTSTA = 1
Write
FLEX_US_CR
Read
FLEX_US_RHR
RXRDY
OVRE
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
46.7.3.8 Parity
The USART supports five parity modes that are selected by writing to the FLEX_US_MR.PAR field. The PAR field
also enables the Multidrop mode (see section Multidrop Mode). Even and odd parity bit generation and error
detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the
character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the
number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is
selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is
even, and to 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s
and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator
of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error if the parity
bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit to 0 for all
characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the
transmitter does not generate any parity bit and the receiver does not report any parity error.
The following table shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the
configuration of the USART. Because there are two bits set to 1 in the character value, the parity bit is set to 1 when
the parity is odd, or configured to 0 when the parity is even.
Table 46-7. Parity Bit Examples
Character
Hexadecimal
Binary
Parity Bit
Parity Mode
A
0x41
0100 0001
1
Odd
A
0x41
0100 0001
0
Even
A
0x41
0100 0001
1
Mark
A
0x41
0100 0001
0
Space
A
0x41
0100 0001
None
None
When the receiver detects a parity error, it sets the Parity Error bit FLEX_US_CSR.PARE. The PARE bit can be
cleared by writing a one to the FLEX_US_CR.RSTSTA bit. The following figure illustrates the parity bit status setting
and clearing.
Figure 46-21. Parity Error
Baud Rate
Clock
RXD
Start
D0
Bit
Write
FLEX_US_CR
PARE
D1
D2
D3
D4
D5
D6
D7
Bad Stop
Parity Bit
Bit
RSTSTA = 1
Parity Error
Detect
Time
Flags
Report
Time
RXRDY
46.7.3.9 Multidrop Mode
If the value 0x6 or 0x07 is written to the FLEX_US_MR.PAR field, the USART runs in Multidrop mode. This mode
differentiates the data characters and the address characters. Data are transmitted with the parity bit to 0 and
addresses are transmitted with the parity bit to 1.
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
If the USART is configured in Multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high
and the transmitter is able to send a character with the parity bit high when a one is written to the
FLEX_US_CR.SENDA bit.
To handle parity error, the PARE bit is cleared by writing a one to the FLEX_US_CR.RSTSTA bit.
The transmitter sends an address byte (parity bit set) when the FLEX_US_CR.SENDA bit is written to 1. In this case,
the next byte written to FLEX_US_THR is transmitted as an address. Any character written in FLEX_US_THR when
the SENDA command is not written is transmitted normally with parity to 0.
46.7.3.10 Transmitter Timeguard
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This
idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register
(FLEX_US_TTGR). When this field is written to zero, no timeguard is generated. Otherwise, the transmitter holds a
high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the
number of stop bits.
As illustrated in the following figure, the behavior of the TXRDY and TXEMPTY status bits is modified by the
programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains to 0
during the timeguard transmission if a character has been written in FLEX_US_THR. TXEMPTY remains low until the
timeguard transmission is completed as the timeguard is part of the current character being transmitted.
Figure 46-22. Timeguard Operations
TG = 4
TG = 4
Baud Rate
Clock
TXD
Start D0
Bit
D1
D2
D3
D4
D5
D6
D7 Parity Stop
Bit Bit
Start D0
Bit
D1
D2
D3
D4
D5
D6
D7 Parity Stop
Bit Bit
Write
FLEX_US_THR
TXRDY
TXEMPTY
The following table indicates the maximum length of a timeguard period that the transmitter can handle in relation to
the function of the baud rate.
Table 46-8. Maximum Timeguard Length Depending on Baud Rate
Baud Rate (bit/s)
Bit Time (μs)
Timeguard (ms)
1,200
833
212.50
9,600
104
26.56
14,400
69.4
17.71
19,200
52.1
13.28
28,800
34.7
8.85
38,400
26
6.63
56,000
17.9
4.55
57,600
17.4
4.43
115,200
8.7
2.21
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
46.7.3.11 Receiver Timeout
The Receiver Timeout provides support in handling variable-length frames. This feature detects an idle condition on
the RXD line. When a timeout is detected, the FLEX_US_CSR.TIMEOUT bit rises and can generate an interrupt,
thus indicating to the driver an end of frame.
The timeout delay period (during which the receiver waits for a new character) is programmed in the TO field of the
Receiver Timeout Register (FLEX_US_RTOR). If the TO field is written to 0, the Receiver Timeout is disabled and no
timeout is detected. The FLEX_US_CSR.TIMEOUT bit remains at 0. Otherwise, the receiver loads a 16-bit counter
with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new
character is received. If the counter reaches 0, the FLEX_US_CSR.TIMEOUT bit rises. Then, the user can either:
•
•
Stop the counter clock until a new character is received. This is performed by writing a ‘1’ to
FLEX_US_CR.STTTO. In this case, the idle state on RXD before a new character is received does not provide a
timeout. This prevents having to handle an interrupt before a character is received and enables waiting for the
next idle state on RXD after a frame is received.
Obtain an interrupt while no character is received. This is performed by writing a ‘1’ to FLEX_US_CR.RETTO. In
this case, the counter starts counting down immediately from the value TO. This generates a periodic interrupt
so that a user timeout can be handled, for example when no key is pressed on a keyboard.
The following figure shows the block diagram of the Receiver Timeout feature.
Figure 46-23. Receiver Timeout Block Diagram
TO
Baud Rate
Clock
1
D
Clock
Q
16-bit Timeout
Counter
16-bit
Value
=
STTTO
Character
Received
Load
Clear
TIMEOUT
0
RETTO
The following table gives the maximum timeout period for some standard baud rates.
Table 46-9. Maximum Timeout Period
Baud Rate (bit/s)
Bit Time (μs)
Timeout (ms)
600
1,667
109,225
1,200
833
54,613
2,400
417
27,306
4,800
208
13,653
9,600
104
6,827
14,400
69
4,551
19,200
52
3,413
28,800
35
2,276
38,400
26
1,704
56,000
18
1,170
57,600
17
1,138
200,000
5
328
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
46.7.3.12 Framing Error
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character
is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
A framing error is reported on the FLEX_US_CSR.FRAME bit. The FRAME bit is asserted in the middle of the stop
bit as soon as the framing error is detected. It is cleared by writing a one to the FLEX_US_CR.RSTSTA bit.
Figure 46-24. Framing Error Status
Baud Rate
Clock
RXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
RSTSTA = 1
Write
FLEX_US_CR
FRAME
RXRDY
46.7.3.13 Transmit Break
The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD
line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the
stop bits to 0. However, the transmitter holds the TXD line at least during one character until the user requests the
break condition to be removed.
A break is transmitted by setting the FLEX_US_CR.STTBRK bit. This can be done at any time, either while the
transmitter is empty (no character in either the shift register or in FLEX_US_THR) or when a character is being
transmitted. If a break is requested while a character is being shifted out, the character is first completed before the
TXD line is held low.
Once the Start Break command is requested, further Start Break commands are ignored until the end of the break is
completed.
The break condition is removed by setting the FLEX_US_CR.STPBRK bit. If the Stop Break command is requested
before the end of the minimum break duration (one character, including start, data, parity and stop bits), the
transmitter ensures that the break condition completes.
The transmitter considers the break as though it is a character, i.e., the Start Break and Stop Break commands are
processed only if the FLEX_US_CSR.TXRDY bit = 1 and the start of the break condition clears the TXRDY and
TXEMPTY bits as if a character was processed.
Setting both the FLEX_US_CR.STTBRK and FLEX_US_CR.STPBRK bits can lead to an unpredictable result. All
Stop Break commands requested without a previous Start Break command are ignored. A byte written into the
Transmit Holding register while a break is pending, but not started, is ignored.
After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter
ensures that the remote receiver detects correctly the end of break and the start of the next character. If the
timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
The following figure illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on
the TXD line.
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SAM9X60
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Figure 46-25. Break Transmission
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
STTBRK = 1
Break Transmission
End of Break
STPBRK = 1
Write
FLEX_US_CR
TXRDY
TXEMPTY
46.7.3.14 Receive Break
The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a
framing error with data to 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the FLEX_US_CSR.RXBRK bit. FLEX_US_CSR.RXBRK may
be cleared by setting the FLEX_US_CR.RSTSTA bit.
An end of receive break is detected by a high level for at least 2/16ths of a bit period in Asynchronous operating
mode or one sample at high level in Synchronous operating mode. The end of break detection also asserts the
RXBRK bit.
46.7.3.15 Hardware Handshaking
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect
with the remote device, as shown in the following figure.
Figure 46-26. Connection with a Remote Device for Hardware Handshaking
USART
Remote
Device
TXD
RXD
RXD
TXD
CTS
RTS
RTS
CTS
Setting the USART to operate with hardware handshaking is performed by writing the FLEX_US_MR.USART_MODE
field to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in standard Synchronous
or Asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin
modifies the behavior of the transmitter as described below. Using this mode requires using the DMAC channel for
reception. The transmitter can handle hardware handshaking in any case.
Figure 46-27. RTS Line Software Control when FLEX_US_MR.USART_MODE = 2
RXD
Write
FLEX_US_CR.RTSDIS
Write
FLEX_US_CR.RTSEN
RTS
The following figure shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables
the transmitter. If a character is being processed, the transmitter is disabled only after the completion of the current
character and transmission of the next character happens as soon as the pin CTS falls.
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-28. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
If USART FIFOs are enabled (bit FLEX_US_CR.FIFOEN), the RTS pin can be controlled by the USART Receive
FIFO thresholds. The RTS pin control through Receive FIFO thresholds can be activated with the
FLEX_US_FMR.FRTSC bit. Once activated, the RTS pin will be controlled by Receive FIFO thresholds, set to level 1
each time RXFTHRES is reached and set to level ‘0’ each time RXFTHRES2 is reached (and RXFTHRES is not
reached).
Figure 46-29. Receiver Behavior When FIFO Enabled and FRTSC Set to ‘1’
RXD
RXDIS = 1
Read
FLEX_US_RHR
RXEN = 1
Write
FLEX_US_CR
RTS
above/equal to RXFTHRES
RXFTHRES = 3
below/equal to RXFTHRES2
RXFTHRES2 = 1
RXFL
0
1
2
3
2
1
2
Note: In this mode, RXFTHRES must be > RXFTHRES2.
46.7.4
ISO7816 Mode
The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and
Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by
the ISO7816 specification are supported.
Setting the USART in ISO7816 mode is performed by writing the FLEX_US_MR.USART_MODE field to the value
0x4 for protocol T = 0 and to the value 0x6 for protocol T = 1.
46.7.4.1 ISO7816 Mode Overview
The ISO7816 is a half-duplex communication on only one bidirectional line. The baud rate is determined by a division
of the clock provided to the remote device (see figure in section Baud Rate Generator).
The USART connects to a smart card as shown in the following figure. The TXD line becomes bidirectional and the
baud rate generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output
remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the
input of the receiver. The USART is considered as the master of the communication as it generates the clock.
Figure 46-30. Connection of a Smart Card to the USART
USART
SCK
TXD
CLK
I/O
Smart
Card
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is partially predefined. The
configuration is forced to 8 data bits, and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9
and CHMODE fields. MSBF can be used to transmit LSB or MSB first. The bit INVDATA can be used to transmit in
Normal or Inverse mode.
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Flexible Serial Communication Controller (FLEXCOM)
The USART cannot operate concurrently in both Receiver and Transmitter modes as the communication is
unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the
receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816
mode may lead to unpredictable results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on
the I/O line at their negative value.
46.7.4.2 Protocol T = 0
In T = 0 protocol, a character is made up of 1 start bit, 8 data bits, 1 parity bit and 1 guard time, which lasts two bit
times. The transmitter shifts out the bits and does not drive the I/O line during the guard time.
If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the
transmission of the next character, as shown in the following figure.
If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in figure "T = 0
Protocol with Parity Error" below. This error bit is also named NACK, for Non Acknowledge. In this case, the
character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1
bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive
Holding Register (FLEX_US_RHR). It appropriately sets the PARE bit in the Status Register (FLEX_US_CSR) so that
the software can handle the error.
Figure 46-31. T = 0 Protocol without Parity Error
Baud Rate
Clock
RXD
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Guard Guard Next
Bit Time 1 Time 2 Start
Bit
Figure 46-32. T = 0 Protocol with Parity Error
Baud Rate
Clock
Error
I/O
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Guard
Bit Time 1
Guard Start
Time 2 Bit
D0
D1
Repetition
46.7.4.2.1 Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of Error
(FLEX_US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading FLEX_US_NER
automatically clears the NB_ERRORS field.
46.7.4.2.2 Receive NACK Inhibit
The USART can be configured to inhibit an error. This is done by writing a ‘1’ to FLEX_US_MR.INACK. In this case,
no error signal is driven on the I/O line even if a parity bit is detected.
Moreover, if INACK = 1, the erroneous received character is stored in the Receive Holding register as if no error
occurred, and the RXRDY bit rises.
46.7.4.2.3 Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before
moving on to the next one. Repetition is enabled by writing the FLEX_US_MR.MAX_ITERATION field at a value
higher than 0. Each character can be transmitted up to eight times: the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in
MAX_ITERATION.
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
When the USART repetition number reaches MAX_ITERATION, and the last repeated character is not
acknowledged, the FLEX_US_CSR.ITER bit is set. If the repetition of the character is acknowledged by the receiver,
the repetitions are stopped and the iteration counter is cleared.
The FLEX_US_CSR.ITER bit can be cleared by writing the FLEX_US_CR.RSTIT bit to 1.
46.7.4.2.4 Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by
setting the FLEX_US_MR.DSNACK bit. The maximum number of NACKs transmitted is programmed in the
MAX_ITERATION field. As soon as MAX_ITERATION is reached, no error signal is driven on the I/O line and the
FLEX_US_CSR.ITER bit is set.
46.7.4.3 Protocol T = 1
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop
bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the
FLEX_US_CSR.PARE bit.
46.7.5
IrDA Mode
The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the
modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in the following
figure. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data
transfer speeds ranging from 2.4 kbit/s to 115.2 kbit/s.
The USART IrDA mode is enabled by setting the FLEX_US_MR.USART_MODE field to the value 0x8. The IrDA
Filter Register (FLEX_US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate
in a normal Asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are
activated.
Figure 46-33. Connection to IrDA Transceivers
USART
IrDA
Transceivers
Receiver
Demodulator
Transmitter
Modulator
RXD
RX
TXD
TX
The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be
managed.
To receive IrDA signals, the following needs to be done:
•
•
•
Disable TX and Enable RX
Configure the TXD pin as PIO and set it as an output to 0 (to avoid LED transmission). Disable the internal
pullup (better for power consumption).
Receive data
46.7.5.1 IrDA Modulation
For baud rates up to and including 115.2 kbit/s, the RZI modulation scheme is used. “0” is represented by a light
pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in the following table.
Table 46-10. IrDA Pulse Duration
Baud Rate
Pulse Duration (3/16)
2.4 kbit/s
78.13 μs
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
...........continued
Baud Rate
Pulse Duration (3/16)
9.6 kbit/s
19.53 μs
19.2 kbit/s
9.77 μs
38.4 kbit/s
4.88 μs
57.6 kbit/s
3.26 μs
115.2 kbit/s
1.63 μs
The following figure shows an example of character transmission.
Figure 46-34. IrDA Modulation
Start
Bit
Transmitter
Output
0
Stop
Bit
Data Bits
1
0
1
0
0
1
1
0
1
TXD
Bit Period
3/16 Bit Period
46.7.5.2 IrDA Baud Rate
The following table gives some examples of CD values, baud rate error and pulse duration. Note that the requirement
on the maximum acceptable error of ±1.87% must be met.
Table 46-11. IrDA Baud Rate Error
Peripheral Clock
Baud Rate (bit/s)
CD
Baud Rate Error
Pulse Time (μs)
3,686,400
115,200
2
0.00%
1.63
20,000,000
115,200
11
1.38%
1.63
32,768,000
115,200
18
1.25%
1.63
40,000,000
115,200
22
1.38%
1.63
3,686,400
57,600
4
0.00%
3.26
20,000,000
57,600
22
1.38%
3.26
32,768,000
57,600
36
1.25%
3.26
40,000,000
57,600
43
0.93%
3.26
3,686,400
38,400
6
0.00%
4.88
20,000,000
38,400
33
1.38%
4.88
32,768,000
38,400
53
0.63%
4.88
40,000,000
38,400
65
0.16%
4.88
3,686,400
19,200
12
0.00%
9.77
20,000,000
19,200
65
0.16%
9.77
32,768,000
19,200
107
0.31%
9.77
40,000,000
19,200
130
0.16%
9.77
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
...........continued
Peripheral Clock
Baud Rate (bit/s)
CD
Baud Rate Error
Pulse Time (μs)
3,686,400
9,600
24
0.00%
19.53
20,000,000
9,600
130
0.16%
19.53
32,768,000
9,600
213
0.16%
19.53
40,000,000
9,600
260
0.16%
19.53
3,686,400
2,400
96
0.00%
78.13
20,000,000
2,400
521
0.03%
78.13
32,768,000
2,400
853
0.04%
78.13
46.7.5.3 IrDA Demodulator
The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the
value programmed in FLEX_US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts
counting down at the peripheral clock speed. If a rising edge is detected on the RXD pin, the counter stops and is
reloaded with FLEX_US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is
driven low during one bit time.
The following figure illustrates the operations of the IrDA demodulator.
Figure 46-35. IrDA Demodulator Operations
MCK
RXD
Counter
Value
Receiver
Input
6
5
4 3
Pulse
Rejected
2
6
6
5
4
3
2
1
0
Pulse
Accepted
The programmed value in the FLEX_US_IF register must always meet the following criteria:
tperipheral clock × (IRDA_FILTER + 3) < 1.41 μs
As the IrDA mode uses the same logic as the ISO7816, note that the FLEX_US_FIDI.FI_DI_RATIO field must be set
to a value higher than 0 to make sure IrDA communications operate correctly.
46.7.6
RS485 Mode
The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART
behaves as though in Asynchronous or Synchronous mode and configuration of all the parameters is possible. The
difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is
controlled by the TXEMPTY bit. A typical connection of the USART to an RS485 bus is shown in the following figure.
Figure 46-36. Typical Connection to an RS485 Bus
USART
RXD
Differential
Bus
TXD
RTS
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The USART is set in RS485 mode by writing the value 0x1 to the FLEX_US_MR.USART_MODE field.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is
programmed, so that the line can remain driven after the last character completion. The following figure gives an
example of the RTS waveform during a character transmission when the timeguard is enabled.
Figure 46-37. Example of RTS Drive with Timeguard
TG = 4
1
Baud Rate
Clock
TXD
Start D0
Bit
D1
D2
D3
D4
D5
D6
D7 Parity Stop
Bit Bit
RTS
Write
FLEX_US_THR
TXRDY
TXEMPTY
46.7.7
USART Comparison Function on Received Character
The CMP flag in FLEX_US_CSR is set when the received character matches the conditions programmed in
FLEX_US_CMPR. The CMP flag is set as soon as FLEX_US_RHR is loaded with the new received character. The
CMP flag is cleared by writing a one to FLEX_US_CR.RSTSTA.
FLEX_US_CMPR can be programmed to provide different comparison methods:
•
•
•
If VAL1 equals VAL2, then the comparison is performed on a single value and the flag is set to 1 if the received
character equals VAL1.
If VAL1 is strictly lower than VAL2, then any value between VAL1 and VAL2 sets the CMP flag.
If VAL1 is strictly higher than VAL2, then the flag CMP is set to 1 if any received character equals VAL1 or VAL2.
When the FLEX_US_CMPR.CMPMODE bit is set to FLAG_ONLY (value 0), all received data are loaded in
FLEX_US_RHR and the CMP flag provides the status of the comparison result.
By programming the START_CONDITION.CMPMODE bit (value 1), the comparison function result triggers the start
of the loading of FLEX_US_RHR (see the following figure). The trigger condition exists as soon as the received
character value matches the condition defined by the programming of VAL1, VAL2 and CMPPAR in
FLEX_US_CMPR. The comparison trigger event is restarted by writing a 1 to the FLEX_US_CR.REQCLR bit.
By setting the CMPMODE bit to FILTER (value 2), the comparison result triggers the start of the US_RHR loading.
The trigger condition exists as soon as the received address byte value matches the conditions defined by VAL1,
VAL2 in US_CMPR. The comparison trigger event is restarted automatically after the reception of the data byte. This
comparison mode is only available when FLEX_US_MR.USART_MODE is set to DATA16BIT _SLAVE_MODE (value
13).
The value programmed in the VAL1 and VAL2 fields must not exceed the maximum value of the received character
(see CHRL field in register 46.10.5 FLEX_US_MR).
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Figure 46-38. Receive Holding Register Management
CMPMODE = 1, VAL1 = VAL2 = 0x06
Peripheral
Clock
RXD
0x0F
0x06
0xF0
0x08
0x06
RXRDY rising enabled
RXRDY
Write REQCLR
RHR
46.7.8
0x0F
0x06
0xF0
0x08
0x06
LIN Mode
The LIN mode provides master node and slave node connectivity on a LIN bus.
The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of
mechatronic nodes in distributed automotive applications.
The main properties of the LIN bus are:
•
•
•
•
•
•
Single master/multiple slaves concept
Low-cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or
as a pure state machine.
Self synchronization without quartz or ceramic resonator in the slave nodes
Deterministic signal transmission
Low cost single-wire implementation
Speed up to 20 kbit/s
LIN provides cost efficient bus communication where the bandwidth and versatility of CAN are not required.
The LIN mode enables processing LIN frames with a minimum of action from the microprocessor.
46.7.8.1 Modes of Operation
The USART can act either as a LIN master node or as a LIN slave node.
The node configuration is chosen by setting the USART_MODE field in the USART Mode Register (FLEX_US_MR):
•
•
LIN master node (USART_MODE = 0xA)
LIN slave node (USART_MODE = 0xB)
In order to avoid unpredictable behavior, any change of the LIN node configuration must be followed by a software
reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (See section
46.7.2 Receiver and Transmitter Control.)
46.7.8.2 Baud Rate Configuration
See section Baud Rate in Asynchronous Mode.
•
•
LIN master node: The baud rate is configured in FLEX_US_BRGR.
LIN slave node: The initial baud rate is configured in FLEX_US_BRGR. This configuration is automatically
copied in the LIN Baud Rate Register (FLEX_US_LINBRR) when writing FLEX_US_BRGR. After the
synchronization procedure, the baud rate is updated in FLEX_US_LINBRR.
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46.7.8.3 Receiver and Transmitter Control
See section 46.7.2 Receiver and Transmitter Control.
46.7.8.4 Character Transmission
See section Transmitter Operations.
46.7.8.5 Character Reception
See section Receiver Operations.
46.7.8.6 Header Transmission (Master Node Configuration)
All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch
Field and Identifier Field.
So in master node configuration, the frame handling starts with the sending of the header.
The header is transmitted as soon as the identifier is written in the LIN Identifier Register (FLEX_US_LINIR). At this
moment the flag TXRDY falls.
The Break Field, the Synch Field and the Identifier Field are sent automatically one after the other.
The Break Field consists of 13 dominant bits and 1 recessive bit, the Synch Field is the character 0x55 and the
Identifier corresponds to the character written in the LIN Identifier Register (FLEX_US_LINIR). The Identifier parity
bits can be automatically computed and sent (see section Identifier Parity).
The flag TXRDY rises when the identifier character is transferred into the shift register of the transmitter.
As soon as the Synch Break Field is transmitted, the FLEX_US_CSR.LINBK flag bit is set. Likewise, as soon as the
Identifier Field is sent, the FLEX_US_CSR.LINID flag bit is set. These flags are reset by writing a one to the
FLEX_US_CR.RSTSTA bit.
Figure 46-39. Header Transmission
Baud Rate
Clock
TXD
Break Field
13 dominant bits (at 0)
Write
FLEX_US_LINIR
FLEX_US_LINIR
Break
Delimiter
1 recessive bit
(at 1)
Start
1
Bit
0
1
0
1
0
Synch Byte = 0x55
1
0
Stop Start
Stop
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Bit Bit
Bit
ID
TXRDY
LINBK
in FLEX_US_CSR
LINID
in FLEX_US_CSR
Write RSTSTA=1
in FLEX_US_CR
46.7.8.7 Header Reception (Slave Node Configuration)
All the LIN frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch
Field and Identifier Field.
In slave node configuration, the frame handling starts with the reception of the header.
The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11
consecutive recessive bits are detected on the bus, the USART detects a Break Field. As long as a Break Field has
not been detected, the USART stays idle and the received data are not taken in account.
When a Break Field has been detected, the FLEX_US_CSR.LINBK flag is set and the USART expects the Synch
Field character to be 0x55. This field is used to update the actual baud rate in order to remain synchronized (see
section Slave Node Synchronization). If the received Synch character is not 0x55, an Inconsistent Synch Field error
is generated (see section LIN Errors).
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After receiving the Synch Field, the USART expects to receive the Identifier Field.
When the Identifier Field has been received, the FLEX_US_CSR.LINID flag bit is set. At this moment, the IDCHR
field in the LIN Identifier Register (FLEX_US_LINIR) is updated with the received character. The Identifier parity bits
can be automatically computed and checked (see section Identifier Parity).
If the header is not entirely received within the time given by the maximum length of the header tHeader_Maximum, the
FLEX_US_CSR.LINHTE error flag bit is set.
The flag bits LINID, LINBK and LINHTE are reset by writing a one to the FLEX_US_CR.RSTSTA bit.
Figure 46-40. Header Reception
Baud Rate
Clock
RXD
Break Field
13 dominant bits (at 0)
Break
Delimiter
1 recessive bit
(at 1)
Start
1
Bit
0
1
0
1
0
Synch Byte = 0x55
1
0
Stop Start
Stop
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Bit Bit
Bit
LINBK
LINID
FLEX_US_LINIR
Write RSTSTA=1
in FLEX_US_CR
46.7.8.8 Slave Node Synchronization
The synchronization is done only in slave node configuration. The procedure is based on time measurement between
the falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times.
Figure 46-41. Synch Field
Synch Field
8 tbit
2 tbit
2 tbit
2 tbit
2 tbit
Start
bit
Stop
bit
The time measurement is made by a 19-bit counter driven by the sampling clock (see section Baud Rate Generator).
When the start bit of the Synch Field is detected, the counter is reset. Then during the next eight tbit of the Synch
Field, the counter is incremented. At the end of these eight tbit, the counter is stopped. At this moment, the 16 most
significant bits of the counter (value divided by 8) give the new clock divider (LINCD) and the 3 least significant bits of
this value (the remainder) give the new fractional part (LINFP).
Once the Synch Field has been entirely received, the clock divider (LINCD) and the fractional part (LINFP) are
updated in the LIN Baud Rate Register (FLEX_US_LINBRR) with the computed values, if the Synchronization is not
disabled by the SYNCDIS bit in the LIN Mode Register (FLEX_US_LINMR).
After reception of the Synch Field:
•
•
If it appears that the computed baud rate deviation compared to the initial baud rate is superior to the maximum
tolerance FTol_Unsynch (±15%), then the clock divider (LINCD) and the fractional part (LINFP) are not updated,
and the FLEX_US_CSR.LINSTE error flag bit is set.
If it appears that the sampled Synch character is not equal to 0x55, then the clock divider (LINCD) and the
fractional part (LINFP) are not updated, and the FLEX_US_CSR.LINISFE error flag bit is set.
Flags LINSTE and LINISFE are reset by writing a one to the FLEX_US_CR.RSTSTA bit.
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Figure 46-42. Slave Node Synchronization
Baud Rate
Clock
RXD
Break Field
13 dominant bits (at 0)
Break
Delimiter
1 recessive bit
(at 1)
Start
1
Bit
0
1
0
1
0
Synch Byte = 0x55
1
0
Stop Start
Stop
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Bit Bit
Bit
LINIDRX
Reset
000_0011_0001_0110_1101
Synchro Counter
FLEX_US_BRGR
Clock Divider (CD)
Initial CD
FLEX_US_BRGR
Fractional Part (FP)
Initial FP
FLEX_US_LINBRR
Clock Divider (CD)
Initial CD
0000_0110_0010_1101
FLEX_US_LINBRR
Fractional Part (FP)
Initial FP
101
The synchronization accuracy depends on several parameters:
•
•
•
The nominal clock frequency (fNom) (the theoretical slave node clock frequency)
The baud rate
The oversampling (OVER = 0 => 16X or OVER = 1 => 8X)
The following formula is used to compute the deviation of the slave bit rate relative to the master bit rate after
synchronization (fSLAVE is the real slave node clock frequency).
Baud rate deviation = 100 ×
Baud rate deviation = 100 ×
� × 8 × 2 − Over + � × Baud rate
%
8 × f SLAVE
� × 8 × 2 − Over + � × Baud rate
−0.5 ≤ � ≤ +0.5 ‐1 < � < +1
8×
f TOL_UNSYNCH
× f Nom
100
%
fTOL_UNSYNCH is the deviation of the real slave node clock from the nominal clock frequency. The LIN Standard
imposes that it must not exceed ±15%. The LIN Standard imposes also that for communication between two nodes,
their bit rate must not differ by more than ±2%. This means that the baud rate deviation must not exceed ±1%.
Therefore, a minimum value for the nominal clock frequency can be computed as follows:
f Nom min = 100 ×
0.5 × 8 × 2 − Over + 1 × Baud rate
Examples:
•
•
•
•
−15
8 × 100 + 1 × 1%
Hz
Baud rate = 20 kbit/s, OVER = 0 (Oversampling 16X) => fNom(min) = 2.64 MHz
Baud rate = 20 kbit/s, OVER = 1 (Oversampling 8X) => fNom(min) = 1.47 MHz
Baud rate = 1 kbit/s, OVER = 0 (Oversampling 16X) => fNom(min) = 132 kHz
Baud rate = 1 kbit/s, OVER = 1 (Oversampling 8X) => fNom(min) = 74 kHz
46.7.8.9 Identifier Parity
A protected identifier consists of two subfields: the identifier and the identifier parity. Bits 0 to 5 are assigned to the
identifier, and bits 6 and 7 are assigned to the parity.
The USART interface can generate/check these parity bits, but this feature can also be disabled. The user can
choose between two modes via the FLEX_US_LINMR.PARDIS bit:
•
PARDIS = 0:
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•
– During header transmission, the parity bits are computed and sent with the six least significant bits of the
IDCHR field of the LIN Identifier Register (FLEX_US_LINIR). Bits 6 and 7 of this register are discarded.
– During header reception, the parity bits of the identifier are checked. If the parity bits are wrong, an
Identifier Parity error occurs (see section Parity). Only the six least significant bits of the IDCHR field are
updated with the received Identifier. Bits 6 and 7 are stuck to 0.
PARDIS = 1:
– During header transmission, all the bits of the IDCHR field of the LIN Identifier Register (FLEX_US_LINIR)
are sent on the bus.
– During header reception, all the bits of the IDCHR field are updated with the received Identifier.
46.7.8.10 Node Action
Depending on the identifier, the node is affected—or not—by the LIN response. Consequently, after sending or
receiving the identifier, the USART must be configured. There are three possible configurations:
•
•
•
PUBLISH: the node sends the response.
SUBSCRIBE: the node receives the response.
IGNORE: the node is not concerned by the response, it does not send and does not receive the response.
This configuration is made by the LIN Node Action (NACT) field in USART LIN Mode Register (FLEX_US_LINMR).
Example: a LIN cluster that contains a master and two slaves:
•
Data transfer from the master to slave 1 and to slave 2:
NACT(master) = PUBLISH
NACT(slave 1) = SUBSCRIBE
NACT(slave 2) = SUBSCRIBE
•
Data transfer from the master to slave 1 only:
NACT(master) = PUBLISH
NACT(slave 1) = SUBSCRIBE
NACT(slave 2) = IGNORE
•
Data transfer from slave 1 to the master:
NACT(master) = SUBSCRIBE
NACT(slave 1) = PUBLISH
NACT(slave 2) = IGNORE
•
Data transfer from slave 1 to slave 2:
NACT(master) = IGNORE
NACT(slave 1) = PUBLISH
NACT(slave 2) = SUBSCRIBE
•
Data transfer from slave 2 to the master and to slave 1:
NACT(master) = SUBSCRIBE
NACT(slave 1) = SUBSCRIBE
NACT(slave 2) = PUBLISH
46.7.8.11 Response Data Length
The LIN response data length is the number of data fields (bytes) of the response excluding the checksum.
The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the
Identifier (compatibility to LIN Specification 1.1). The user can choose between these two modes by the
FLEX_US_LINMR.DLM bit:
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•
DLM = 0: The response data length is configured by the user via the FLEX_US_LINMR.DLC field. The response
data length is equal to (DLC + 1) bytes. DLC can be programmed from 0 to 255, so the response can contain
from 1 data byte up to 256 data bytes.
• DLM = 1: The response data length is defined by the Identifier (IDCHR in FLEX_US_LINIR) according to the
table below. The FLEX_US_LINMR.DLC field is discarded. The response can contain 2 or 4 or 8 data bytes.
Table 46-12. Response Data Length if DLM = 1
IDCHR[5]
IDCHR[4]
Response Data Length (bytes)
0
0
2
0
1
2
1
0
4
1
1
8
Figure 46-43. Response Data Length
User configuration: 1–256 data fields (DLC+1)
Identifier configuration: 2/4/8 data fields
Sync
Break
Sync
Field
Identifier
Field
Data
Field
Data
Field
Data
Field
Data
Field
Checksum
Field
46.7.8.12 Checksum
The last field of a frame is the checksum. The checksum contains the inverted 8- bit sum with carry, over all data
bytes or all data bytes and the protected identifier. Checksum calculation over the data bytes only is called classic
checksum and it is used for communication with LIN 1.3 slaves. Checksum calculation over the data bytes and the
protected identifier byte is called enhanced checksum and it is used for communication with LIN 2.0 slaves.
The USART can be configured to:
•
•
•
Send/Check an Enhanced checksum automatically (CHKDIS = 0 & CHKTYP = 0)
Send/Check a Classic checksum automatically (CHKDIS = 0 & CHKTYP = 1)
Not send/check a checksum (CHKDIS = 1)
This configuration is made by the Checksum Type (CHKTYP) and Checksum Disable (CHKDIS) bits of
FLEX_US_LINMR.
If the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a
normal data byte and by adding 1 to the response data length (see section Response Data Length).
46.7.8.13 Frame Slot Mode
This mode is useful only for master nodes. It respects the following rule: each frame slot shall be longer than or equal
to tFrame_Maximum.
If the Frame Slot mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set
again only after tFrame_Maximum delay, from the start of frame. So the master node cannot send a new header if the
frame slot duration of the previous frame is inferior to tFrame_Maximum.
If the Frame Slot mode is disabled (FSDIS = 1) and a frame transfer has been completed, the TXRDY flag is set
again immediately.
The tFrame_Maximum is calculated as follows:
If the Checksum is sent (CHKDIS = 0):
•
•
•
•
tHeader_Nominal = 34 × tbit
tResponse_Nominal = 10 × (NData + 1) × tbit
tFrame_Maximum = 1.4 × (tHeader_Nominal + tResponse_Nominal + 1)(1)
tFrame_Maximum = 1.4 × (34 + 10 × (DLC + 1 + 1) + 1) × tbit
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•
tFrame_Maximum = (77 + 14 × DLC) × tbit
If the Checksum is not sent (CHKDIS = 1):
•
•
•
•
•
tHeader_Nominal = 34 × tbit
tResponse_Nominal = 10 × NData × tbit
tFrame_Maximum = 1.4 × (tHeader_Nominal + tResponse_Nominal + 1)(1)
tFrame_Maximum = 1.4 × (34 + 10 × (DLC + 1) + 1) × tbit
tFrame_Maximum = (63 + 14 × DLC) × tbit
Note: 1. The term “+1” leads to an integer result for tFrame_Maximum (LIN Specification 1.3).
Figure 46-44. Frame Slot Mode
Frame slot = tFrame_Maximum
Frame
Header
Break
Synch
Data3
Interframe
space
Response
space
Protected
Identifier
Response
Data N-1
Data 1
Data N
Checksum
TXRDY
Frame Slot Mode Frame Slot Mode
Disabled
Enabled
Write
FLEX_US_LINID
Write
FLEX_US_THR
Data 1
Data 2
Data 3
Data N
LINTC
46.7.8.14 LIN Errors
46.7.8.14.1 Bit Error
This error is generated in master of slave node configuration, when the USART is transmitting and if the transmitted
value on the Tx line is different from the value sampled on the Rx line. If a bit error is detected, the transmission is
aborted at the next byte border.
This error is reported by the FLEX_US_CSR.LINBE flag.
46.7.8.14.2 Inconsistent Synch Field Error
This error is generated in slave node configuration, if the Synch Field character received is other than 0x55.
This error is reported by the FLEX_US_CSR.LINISFE flag.
46.7.8.14.3 Identifier Parity Error
This error is generated in slave node configuration, if the parity of the identifier is wrong. This error can be generated
only if the parity feature is enabled (PARDIS = 0).
This error is reported by the FLEX_US_CSR.LINIPE flag.
46.7.8.14.4 Checksum Error
This error is generated in master of slave node configuration, if the received checksum is wrong. This flag can be set
to 1 only if the checksum feature is enabled (CHKDIS = 0).
This error is reported by the FLEX_US_CSR.LINCE flag.
46.7.8.14.5 Slave Not Responding Error
This error is generated in master of slave node configuration, when the USART expects a response from another
node (NACT = SUBSCRIBE) but no valid message appears on the bus within the time given by the maximum length
of the message frame, tFrame_Maximum (see section Frame Slot Mode). This error is disabled if the USART does not
expect any message (NACT = PUBLISH or NACT = IGNORE).
This error is reported by the FLEX_US_CSR.LINSNRE.
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46.7.8.14.6 Synch Tolerance Error
This error is generated in slave node configuration if, after the clock synchronization procedure, it appears that the
computed baud rate deviation compared to the initial baud rate is superior to the maximum tolerance FTol_Unsynch
(±15%).
This error is reported by the FLEX_US_CSR.LINSTE flag.
46.7.8.14.7 Header Timeout Error
This error is generated in slave node configuration, if the Header is not entirely received within the time given by the
maximum length of the Header, tHeader_Maximum.
This error is reported by the FLEX_US_CSR.LINHTE flag.
46.7.8.15 LIN Frame Handling
46.7.8.15.1 Master Node Configuration
• Write FLEX_US_CR.TXEN and FLEX_US_CR.RXEN to enable both the transmitter and the receiver.
• Write FLEX_US_MR.USART_MODE to select the LIN mode and the master node configuration.
• Write FLEX_US_BRGR.CD and FLEX_US_BRGR.FP to configure the baud rate.
• Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, FSDIS and DLC in FLEX_US_LINMR to configure the frame
transfer.
• Check that FLEX_US_CSR. TXRDY is set to 1.
• Write FLEX_US_LINIR.IDCHR to send the header.
What comes next depends on the NACT configuration:
•
•
•
Case 1: NACT = PUBLISH, the USART sends the response.
– Wait until FLEX_US_CSR. TXRDY rises.
– Write FLEX_US_THR.TCHR to send a byte.
– If all the data have not been written, repeat the two previous steps.
– Wait until FLEX_US_CSR.LINTC rises.
– Check the LIN errors.
Case 2: NACT = SUBSCRIBE, the USART receives the response.
– Wait until FLEX_US_CSR.RXRDY rises.
– Read FLEX_US_RHR.RCHR.
– If all the data have not been read, repeat the two previous steps.
– Wait until FLEX_US_CSR.LINTC rises.
– Check the LIN errors.
Case 3: NACT = IGNORE, the USART is not concerned by the response.
– Wait until FLEX_US_CSR.LINTC rises.
– Check the LIN errors.
Figure 46-45. Master Node Configuration, NACT = PUBLISH
Frame slot = tFrame_Maximum
Frame
Header
Break
Synch
Data3
Interframe
space
Response
space
Protected
Identifier
Response
Data N-1
Data 1
Data N
Checksum
TXRDY
FSDIS=1
FSDIS=0
RXRDY
Write
FLEX_US_LINIR
Write
FLEX_US_THR
Data 1
Data 2
Data 3
Data N
LINTC
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Figure 46-46. Master Node Configuration, NACT = SUBSCRIBE
Frame slot = tFrame_Maximum
Frame
Header
Break
Synch
Data3
Interframe
space
Response
space
Protected
Identifier
Response
Data N-1
Data 1
Data N
Checksum
TXRDY
FSDIS=1 FSDIS=0
RXRDY
Write
FLEX_US_LINIR
Read
FLEX_US_RHR
Data 1
Data N-2
Data N-1
Data N
LINTC
Figure 46-47. Master Node Configuration, NACT = IGNORE
Frame slot = tFrame_Maximum
Frame
Break
Response
space
Header
Data3
Synch
Protected
Identifier
Interframe
space
Response
Data 1
Data N-1
Data N
Checksum
TXRDY
FSDIS=1
FSDIS=0
RXRDY
Write
FLEX_US_LINIR
LINTC
46.7.8.15.2 Slave Node Configuration
• Write FLEX_US_CR.TXEN and FLEX_US_CR.RXEN to enable both the transmitter and the receiver.
• Write FLEX_US_MR.USART_MODE to select the LIN mode and the slave node configuration.
• Write FLEX_US_BRGR.CD and FLEX_US_BRGR.FP to configure the baud rate.
• Wait until FLEX_US_CSR.LINID rises.
• Check LINISFE and LINPE errors.
• Read FLEX_US_RHR.IDCHR.
• Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM and DLC in FLEX_US_LINMR to configure the frame
transfer.
IMPORTANT: If the NACT configuration for this frame is PUBLISH, FLEX_US_LINMR must be written with NACT =
PUBLISH even if this field is already correctly configured, in order to set the TXREADY flag and the corresponding
write transfer request.
What comes next depends on the NACT configuration:
•
•
Case 1: NACT = PUBLISH, the LIN controller sends the response.
– Wait until FLEX_US_CSR.TXRDY rises.
– Write FLEX_US_THR.TCHR to send a byte.
– If all the data have not been written, repeat the two previous steps.
– Wait until FLEX_US_CSR. LINTC rises.
– Check the LIN errors.
Case 2: NACT = SUBSCRIBE, the USART receives the response.
– Wait until FLEX_US_CSR.RXRDY rises.
– Read FLEX_US_RHR.RCHR.
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•
– If all the data have not been read, repeat the two previous steps.
– Wait until FLEX_US_CSR.LINTC rises.
– Check the LIN errors.
Case 3: NACT = IGNORE, the USART is not concerned by the response.
– Wait until FLEX_US_CSR.LINTC rises.
– Check the LIN errors.
Figure 46-48. Slave Node Configuration, NACT = PUBLISH
Break
Synch
Protected
Identifier
Data N-1
Data 1
Data N
Checksum
Data N
Checksum
TXRDY
RXRDY
LINIDRX
Read
FLEX_US_LINID
Write
FLEX_US_THR
Data 1 Data 2
Data 3
Data N
LINTC
Figure 46-49. Slave Node Configuration, NACT = SUBSCRIBE
Break
Synch
Protected
Identifier
Data 1
Data N-1
TXRDY
RXRDY
LINIDRX
Read
FLEX_US_LINID
Read
FLEX_US_RHR
Data 1
Data N-2
Data N-1
Data N
LINTC
Figure 46-50. Slave Node Configuration, NACT = IGNORE
Break
Synch
Protected
Identifier
Data 1
Data N-1
Data N
Checksum
TXRDY
RXRDY
LINIDRX
Read
FLEX_US_LINID
Read
FLEX_US_RHR
LINTC
46.7.8.16 LIN Frame Handling with the DMA
The USART can be used in association with the DMA in order to transfer data directly into/from the on- and off-chip
memories without any processor intervention.
The DMA uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The DMA always writes in the
Transmit Holding Register (FLEX_US_THR) and it always reads in the Receive Holding Register (FLEX_US_RHR).
The size of the data written or read by the DMA in the USART is always a byte.
46.7.8.16.1 Master Node Configuration
The user can choose between two DMA modes by configuring the FLEX_US_LINMR.PDCM bit:
•
PDCM = 1: The LIN configuration is stored in the WRITE buffer and it is written by the DMA in the Transmit
Holding register FLEX_US_THR (instead of the LIN Mode register FLEX_US_LINMR). Because the DMA
transfer size is limited to a byte, the transfer is split into two accesses. During the first access, the NACT,
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•
PARDIS, CHKDIS, CHKTYP, DLM and FSDIS bits are written. During the second access, the 8-bit DLC field is
written.
PDCM = 0: The LIN configuration is not stored in the WRITE buffer and it must be written by the user in
FLEX_US_LINMR.
The WRITE buffer also contains the Identifier and the data, if the USART sends the response (NACT = PUBLISH).
The READ buffer contains the data if the USART receives the response (NACT = SUBSCRIBE).
Figure 46-51. Master Node with DMA (PDCM = 1)
WRITE BUFFER
WRITE BUFFER
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
DLC
NODE ACTION = PUBLISH
IDENTIFIER
(Peripheral) DMA
Controller
NODE ACTION = SUBSCRIBE
IDENTIFIER
APB bus
USART3
LIN Controller
READ BUFFER
APB bus
(Peripheral) DMA
Controller
RXRDY
USART3
LIN Controller
TXRDY
DATA 0
DATA 0
DATA N
TXRDY
DATA N
Figure 46-52. Master Node with DMA (PDCM = 0)
WRITE BUFFER
WRITE BUFFER
IDENTIFIER
IDENTIFIER
NODE ACTION = PUBLISH
DATA 0
|
|
|
|
NODE ACTION = SUBSCRIBE
APB bus
APB bus
READ BUFFER
(Peripheral) DMA
Controller
TXRDY
USART3
LIN Controller
DATA 0
(Peripheral) DMA
Controller
RXRDY
USART3
LIN Controller
TXRDY
DATA N
DATA N
46.7.8.16.2 Slave Node Configuration
In this configuration, the DMA transfers only the data. The identifier must be read by the user in the LIN Identifier
Register (FLEX_US_LINIR). The LIN mode must be written by the user in FLEX_US_LINMR.
The WRITE buffer contains the data if the USART sends the response (NACT = PUBLISH).
The READ buffer contains the data if the USART receives the response (NACT = SUBSCRIBE).
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Figure 46-53. Slave Node with DMA
WRITE BUFFER
READ BUFFER
DATA 0
DATA 0
NACT = SUBSCRIBE
APB bus
(Peripheral) DMA
Controller
APB bus
USART3
LIN Controller
(Peripheral) DMA
Controller
TXRDY
DATA N
USART3
LIN Controller
RXRDY
DATA N
46.7.8.17 Wakeup Request
Any node in a sleeping LIN cluster may request a wakeup.
In the LIN 2.0 specification, the wakeup request is issued by forcing the bus to the dominant state from 250 μs to 5
ms. For this, it is necessary to send the character 0xF0 in order to impose five successive dominant bits. Whatever
the baud rate is, this character respects the specified timings.
•
•
Baud rate min = 1 kbit/s -> tbit = 1 ms -> 5 tbit = 5 ms
Baud rate max = 20 kbit/s -> tbit = 50 μs -> 5 tbit = 250 μs
In the LIN 1.3 specification, the wakeup request should be generated with the character 0x80 in order to impose eight
successive dominant bits.
Using the FLEX_US_LINMR.WKUPTYP bit, the user can choose to send either a LIN 2.0 wakeup request
(WKUPTYP = 0) or a LIN 1.3 wakeup request (WKUPTYP = 1).
A wakeup request is transmitted by writing the FLEX_US_CR.LINWKUP bit to 1. Once the transfer is completed, the
LINTC flag is asserted in the Status Register (FLEX_US_CSR). It is cleared by writing a one to the
FLEX_US_CR.RSTSTA bit.
46.7.8.18 Bus Idle Timeout
If the LIN bus is inactive for a certain duration, the slave nodes shall automatically enter in Sleep mode. In the LIN 2.0
specification, this timeout is defined as 4 seconds. In the LIN 1.3 specification, it is defined as 25,000 tbit.
In slave Node configuration, the receiver timeout detects an idle condition on the RXD line. When a timeout is
detected, the FLEX_US_CSR.TIMEOUT bit rises and can generate an interrupt, thus indicating to the driver to go
into Sleep mode.
The timeout delay period (during which the receiver waits for a new character) is programmed in the
FLEX_US_RTOR.TO field. If a zero is written to the TO field, the Receiver Timeout is disabled and no timeout is
detected. The FLEX_US_CSR.TIMEOUT bit remains at 0. Otherwise, the receiver loads a 17-bit counter with the
value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the FLEX_US_CSR.TIMEOUT bit rises.
If STTTO is performed, the counter clock is stopped until a first character is received.
If RETTO is performed, the counter starts counting down immediately from the value TO.
Table 46-13. Receiver Timeout Programming
LIN Specification
Baud Rate
Timeout period
TO
2.0
1,000 bit/s
4s
4,000
1.3
© 2020 Microchip Technology Inc.
2,400 bit/s
9,600
9,600 bit/s
38,400
19,200 bit/s
76,800
20,000 bit/s
80,000
–
Complete Datasheet
25,000 tbit
25,000
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46.7.9
LON Mode
The LON mode provides connectivity to the local operating network (LON).
The LON standard covers all seven layers of the OSI (Open Systems Interconnect) reference model from the
physical interfaces such as wired, power line, RF, and IP to the application layer and all layers in between.
The LON mode enables the transmission and reception of Physical Protocol Data Unit (PPDU) frames with minimum
intervention from the microprocessor.
Figure 46-54. LON Protocol Layering
Application & Presentation Layers
Layers 6, 7
Application:
network variable exchange
application-specific TPC, etc.
Network Management:
network management RPC,
diagnostics
Session Layer
Layer 5
Request-response
Transport Layer
Acknowledged and unacknowledged unicast and multicast
Authentication
Layer 4
Application
Software
Server
Transaction Control Sublayer
Common ordering and duplicate detection
Layer 3
Network Layer
Connection-less, domain-wide broadcast, no segmentation,
loop-free topology, learning routers
Link Layer
Framing, data encoding, CRC checking
Layer 2
MAC Sublayer
Predictive p-persistent CSMA: collision avoidance
optional priority and collision detection
Layer 1
Physical Layer
Multiple-media, medium-specific protocols
USART
in
LON Mode
Transceiver
The USART configured in LON mode is a full-layer 2 implementation including standard timings handling, framing
(transmit and receive PPDU frames), backlog estimation and other features. At the frame encoding/decoding level,
differential Manchester encoding is used (also known as CDP). When configured in LON mode, there is no
embedded digital line filter, thus the optimal usage is node-to-node communication.
46.7.9.1 Mode of Operation
To configure the USART to act as a LON node, the USART_MODE field of the USART Mode Register
(FLEX_US_MR) must be set to 0x9.
To avoid unpredictable behavior, any change of the LON node configuration must be preceded by a software reset of
the transmitter and the receiver (except the initial node configuration after a hardware reset) and followed by a
transmitter/receiver enable. See section Receiver and Transmitter Control.
46.7.9.2 Receiver and Transmitter Control
See section Receiver and Transmitter Control.
46.7.9.3 Character Transmission
A LON frame is made up of a preamble, a data field (up to 256 bytes) and a 16-bit CRC field. The preamble and CRC
fields are automatically generated and the LON node starts the transmission algorithm on a write to LON_L2HDR.
See section Sending a Frame.
46.7.9.4 Character Reception
When receiving a LON frame, the Receive Holding Register (FLEX_US_RHR) is updated upon completed character
reception and the RXRDY bit in the Status register rises. If a character is completed while the RXRDY bit is set, the
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OVRE (Overrun Error) bit is set. The LON preamble field is only used for synchronization, therefore only the Data and
CRC fields are transmitted to the Receive Holding Register (FLEX_US_RHR). See section Sending a Frame.
46.7.9.5 LON Frame
Figure 46-55. LON Framing
Preamble
Byte
Sync
Bit-Sync
Data
1
1
1
1
1
1
1
1
1
1
0
Line Code
Violation
Data + CRC
0
0
1
0
0
1
1
0
0
46.7.9.5.1 Encoding / Decoding
The USART configured in LON mode encodes transmitted data and decodes received data using differential
Manchester encoding. In differential Manchester encoding, a ‘1’ bit is indicated by making the first half of the signal
equal to the last half of the previous bit's signal (no transition at the start of the bit-time). A ‘0’ bit is indicated by
making the first half of the signal opposite to the last half of the previous bit's signal (a zero bit is indicated by a
transition at the beginning of the bit-time). As is the case with normal Manchester encoding, missing transition at the
middle of bit-time represents a Manchester code violation.
The FLEX_US_MAN.RXIDLEV bit informs the USART of the receiver line idle state value (receiver line inactive) thus
ensuring higher reliability of preamble synchronization. By default, RXIDLEV is set (receiver line is at level 1 when
there is no activity).
Differential Manchester encoding is polarity-insensitive.
Figure 46-56. LON PPDU
Preamble
L2HDR
NPDU
CRC
46.7.9.5.2 Preamble Transmission
Each LON frame begins with a preamble of variable length which consists of a bit-sync field and a byte-sync field.
The LONPL field of the USART LON Preamble Register (FLEX_US_LONPR) defines the preamble length. Note that
a preamble length of ‘0’ is not allowed.
The LON implementation allows two different preamble patterns ALL_ONE and ALL_ZERO which can be configured
through the TX_PL field of the USART Manchester Configuration Register (FLEX_US_MAN). The following figure
illustrates and defines the valid patterns.
Other preamble patterns are not supported.
Figure 46-57. Preamble Patterns
Differential
Manchester
encoded
data
DATA
Txd
8-bit width "ALL_ONE" Preamble (bit-sync)
Differential
Manchester
encoded
data
byte-sync
DATA
Txd
8-bit width "ALL_ZERO" Preamble (bit-sync)
byte-sync
46.7.9.5.3 Preamble Reception
LON received frames begin with a preamble of variable length. The receiving algorithm does not check the preamble
length, although a minimum of length of 4 bits is required for the receiving algorithm to consider the received
preamble as valid.
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As is the case with LON preamble transmission, two preamble patterns (ALL_ONE and ALL_ZERO) are allowed and
can be configured through the RX_PL field of the USART Manchester Configuration Register (FLEX_US_MAN). The
above figure illustrates and defines the valid patterns.
Other preamble patterns are not supported.
46.7.9.5.4 Header Transmission
Each LON frame, after sending the preamble, starts with the frame header also called L2HDR according to CEA-709
specification. This header consist of the priority bit, the alternative path bit and the backlog increment. It is the first
data to be sent.
In LON mode, the transmitting algorithm starts when FLEX_US_LONL2HDR is written (it is the first data to send).
46.7.9.5.5 Header Reception
Each LON frame, after receiving the preamble, receives the frame header also called L2HDR according to CEA-709
specification. This header consists of the priority bit, the alternative path bit, and the backlog increment.
The frame header is the first received data and the RXRDY bit rises as soon as the frame header as been received
and stored in the Receive Holding Register (FLEX_US_RHR).
46.7.9.5.6 Data
Data are sent/received serially after the preamble transmission/reception. Data can be either sent/received MSB first
or LSB first depending on the MSBF bit value in the USART Mode Register (FLEX_US_MR).
46.7.9.5.7 CRC
The two last bytes of LON frames are dedicated to CRC.
When transmitting, the CRC of the frame is automatically generated and sent when expected.
When receiving frames, the CRC is automatically checked and the FLEX_US_CSR.LCRCE flag is set if the
calculated CRC does not match the received one. Note that the two received CRC bytes are seen as two additional
data from the user point of view.
46.7.9.5.8 End Of Frame
The USART configured in LON mode terminates the frame with a three tbit long Manchester code violation. After
sending the last CRC bit, it maintains the data transitionless during three bit periods.
46.7.9.6 LON Operating Modes
46.7.9.6.1 Transmitting/Receiving Modules
According to the LON node configuration and LON network state, the transmitting module is activated if a
transmission request has been made and access to the LON bus granted. It returns to idle state once the
transmission ends.
According to the LON node configuration and LON network state, the receiving module is activated if a valid
preamble is detected and the transmitting module is not activated.
46.7.9.6.2 comm_type
In CEA-709 standard 2, communication configurations are defined and configurable through the comm_type variable.
The comm_type variable value can be set in the USART LON Mode Register (FLEX_US_LONMR) through the
COMMT bit. The selection of the comm_type determines the MAC behavior in the following ways:
•
•
comm_type = 1:
– An indeterminate time is defined during the Beta 1 period in which all transitions on the channel are ignored
(see figure below).
– The MAC sublayer ignores collisions occurring during the first 25% of the transmitted preamble. Optionally
(according to the FLEX_US_LONMR.CDTAIL bit), it ignores collisions reported following the transmission
of the CRC but prior to the end of transmission.
– If a collision is detected during preamble transmission, the MAC sublayer can terminate the packet if so
configured according to the FLEX_US_LONMR.TCOL bit. Collisions detected after the preamble have been
sent do not terminate transmission.
comm_type = 2:
– No indeterminate time is defined at the MAC sublayer.
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– The MAC sublayer always terminates the packet upon notification of a collision.
Figure 46-58. LON Indeterminate Time
IDT
Beta2
Packet
Beta1
Random delay
46.7.9.6.3 Collision Detection
As an option of the CEA-709 standard collision detection is supported through an active low Collision Detect (CD)
input from the transceiver.
The Collision Detection source can be either external (see section I/O Lines Description) or internal. The collision
detection source selection is defined through the LCDS bit in the USART LON Mode Register (FLEX_US_LONMR).
The Collision Detection feature can be activated through the COLDET bit of the USART LON Mode Register. If the
collision detection feature is enabled and CD signal goes low for at least half tbit period then a collision is detected
and reported as defined in section comm_type.
46.7.9.6.4 Collision Detection Mode
As defined in section comm_type, if comm_type = 1 the LON node can be configured to either not terminate
transmission upon collision notification during preamble transmission or terminate transmission.
The FLEX_US_LONMR.TCOL bit allows to decide whether to terminate transmission or not upon collision notification
during preamble transmission.
46.7.9.6.5 Collision Detection after CRC
As defined in section comm_type, if comm_type = 1 the LON node can be configured to ignore collisions reported
after the CRC has been sent but prior to the end of the frame.
The FLEX_US_LONMR.CDTAIL bit can be used to decide whether such collision notifications must be considered or
not.
46.7.9.6.6 Random Number Generation
The Predictive p-persistent CSMA algorithm defined in the CEA-709.1 Standard is based on a random number
generation.
This random number is automatically generated by an internal algorithm.
In addition, a USART IC DIFF Register (FLEX_US_ICDIFF) is available to avoid that two same chips with the same
software generate the same random number after reset. The value of this register is used by the internal algorithm to
generate the random number. Therefore, putting a different value here for each chip ensures that the random number
generated after a reset at the same time will not be the same. It is recommended to put the chip ID code here.
46.7.9.7 LON Node Backlog Estimation
As defined in CEA-709, the LON node maintains its own backlog estimation. The node backlog estimation is initially
set to one, will always be greater than 1 and will never exceed 63. If the node backlog estimation exceeds the
maximum backlog value, the backlog value is set to 63 and a backlog overflow error flag is set (LBLOVFE flag).
The node backlog estimation is incremented each time a frame is sent or received successfully. The increment to the
backlog is encoded into the link layer header, and represents the number of messages that the packet shall cause to
be generated upon reception.
The backlog decrements under one of the following conditions:
•
•
•
•
On waiting to transmit: If Wbase randomizing slots go by without channel activity.
On receive: If a packet is received with a backlog increment of ‘0’.
On transmit: If a packet is transmitted with a backlog increment of ‘0’.
On idle: If a packet cycle time expires without channel activity.
46.7.9.7.1 Optional Collision Detection Feature And Backlog Estimation
Each time a frame is transmitted and a collision occurred, the backlog is incremented by 1. In this case, the backlog
increment encoded in the link layer is ignored.
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46.7.9.8 LON Timings
Figure 46-59. LON Timings
IDT
Beta2
Packet
Packet
1 2 3 ... ... ... n
Beta1
Priority
Slots
Random Delay
46.7.9.8.1 Beta2
A node wishing to transmit generates a random delay T. This delay is an integer number of randomizing slots of
duration Beta2.
The beta2 length (in tbit) is configurable through FLEX_US_FIDI. Note that a length of ‘0’ is not allowed.
46.7.9.8.2 Beta1 Tx/Rx
Beta1 is the period immediately following the end of a packet cycle (see the above figure). A node attempting to
transmit monitors the state of the channel, and if it detects no transmission during the Beta1 period, it determines the
channel to be idle.
The Beta1 value is different depending on the previous packet type (received packet or transmitted packet).
Beta1Rx and Beta1Tx length can be configured respectively through the USART LON Beta1 Rx Register
(FLEX_US_LONB1RX) and the USART LON Beta1 Tx Register (FLEX_US_LONB1TX). Note that a length of ‘0’ is
not allowed.
46.7.9.8.3 Pcycle Timer
The packet cycle timer is reset to its initial value whenever the backlog is changed. It is started (begins counting
down at its current value) whenever the MAC layer becomes idle. An idle MAC layer is defined as:
•
•
•
•
•
Not receiving
Not transmitting,
Not waiting to transmit,
Not timing Beta1,
Not waiting for priority slots, and not waiting for the first Wbase randomizing window to complete.
On transition from idle to either transmit or receive, the packet cycle timer is halted.
The pcycle timer value can be configured in FLEX_US_TTGR. Note that ‘0’ value is not allowed.
46.7.9.8.4 Wbase
The wbase timer represents the base windows size. Its duration, derived from Beta2, equals 16 Beta2 slots.
46.7.9.8.5 Priority Slots
On a channel by channel basis, the protocol supports optional priority. Priority slots, if any, follow immediately after
the Beta1 period that follows the transmission of a packet (see the above figure). The number of priority slots per
channel ranges from 0 to 127.
The number of priority slots in the LON network configuration is defined through the PSNB field of the USART LON
Priority Register (FLEX_US_LONPRIO). And the priority slot affected to the LON node, if any, is defined through the
FLEX_US_LONPRIO.NPS field.
46.7.9.8.6 Indeterminate Time
See section comm_type.
Like Beta1, the IDT value is different depending on whether the previous frame was transmitted or received.
IDTRx and IDTTx can be configured respectively through the USART LON IDT Rx Register (FLEX_US_LONIDTRX)
and the USART LON IDT Tx Register (FLEX_US_LONIDTTX).
46.7.9.8.7 End of Frame Condition
The USART configured in LON mode terminates the frame with a three tbit long Manchester code violation. After
sending the last CRC bit, it maintains the data transitionless during three bit periods.
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While receiving data, the USART configured in LON mode detects an end of frame condition after a teof transitionless
Manchester code violation. The EOFS field in the USART LON Mode Register can configure teof.
46.7.9.9 LON Errors
All these flags can be read in the LON Channel Status Register (FLEX_US_CSR) and generate interrupts if
configured in the LON Interrupt Enable Register (FLEX_US_IER).
These flags can be reset by writing a one to the FLEX_US_CR.RSTSTA bit.
46.7.9.9.1 Underrun Error
If the USART is in LON mode and if a character is sent while the Transmit Holding Register (FLEX_US_THR) is
empty, the UNRE bit flag is set.
46.7.9.9.2 Collision Detection
The LCOL flag is set whenever a valid collision has been detected and the LON node is configured to report it (see
section Collision Detection).
46.7.9.9.3 LON Frame Early Termination
The LFET flag is set whenever a LON frame has been terminated early due to collision detection.
46.7.9.9.4 Reception Error
The LCRCE flag is set if the received frame has an erroneous CRC and the flag LSFE is set if the received frame is
too short (LON frames must be at least 8 bytes long).
These flags can be read in FLEX_US_CSR.
46.7.9.9.5 Backlog Overflow
The LBLOVFE flag is set if the LON node backlog estimation goes over 63, which is the maximum backlog value.
46.7.9.10 Drift Compensation
It may happen that while receiving a frame, the baud rate used by the sender is not exactly the one expected, due to
sender clock drifting for instance. In such case, the hardware drift compensation algorithm is used to recover up to
16% clock drift (expected baud rate ±16% is supported).
Drift compensation is available only in 16X Oversampling mode. To enable the hardware system, the DRIFT bit of the
FLEX_US_MAN register must be set. If the RXD edge is between one and three 16X clock cycles away from the
expected edge, then the period is shortened or lengthened accordingly to center the RXD edge.
Drift compensation hardware feature allows up to 16% clock drift to be handled, provided system clock is fast enough
compared to the selected baud rate.
Figure 46-60. Bit Resynchronization
Oversampling
16x Clock
RXD
Sampling
point
Expected edge
Synchro Error
Synchro Jump
Synchro Error
46.7.9.11 LON Frame Handling
46.7.9.11.1 Sending a Frame
1. Write FLEX_US_CR.TXEN and FLEX_US_CR.RXEN to enable both the transmitter and the receiver.
2. Write FLEX_US_MR.USART_MODE to select the LON mode configuration.
3. Write FLEX_US_BRGR.CD and FLEX_US_BRGR.FP to configure the baud rate.
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4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Write COMMT, COLDET, TCOL, CDTAIL, RDMNBM and DMAM in FLEX_US_LONMR to configure the LON
operating mode.
Write BETA2, BETA1TX, BETA1RX, PCYCLE, PSNB, NPS, IDTTX and ITDRX respectively in FLEX_US_FIDI,
FLEX_US_LONB1TX, FLEX_US_LONB1RX, FLEX_US_TTGR, FLEX_US_LONPRIO, FLEX_US_LONIDTTX
and FLEX_US_LONIDTRX to set the LON network configuration.
Write FLEX_US_MAN.TX_PL to select the preamble pattern to use.
Write LONPL and LONDL in FLEX_US_LONPR and FLEX_US_LONDL to set the frame transfer.
Check that FLEX_US_CSR.TXRDY is set to 1.
Write FLEX_US_LONL2HDR to send the header.
Wait until FLEX_US_CSR.TXRDY rises.
Write FLEX_US_THR.TCHR to send a byte.
If all the data have not been written, repeat the two previous steps.
Wait until FLEX_US_CSR.LTXD rises.
Check the LON errors.
Figure 46-61. Tx Frame
Random Delay
Preamble
l2hdr
Data 1
Data 2
Data N-1
Data N
CRC
CRC
TXRDY
RXRDY
write
FLEX_US_LONL2HDR
write
FLEX_US_THR
Data 1
LTXD
Data 2
Data 3
Data 4
Data N
46.7.9.11.2 Receiving a Frame
1. Write FLEX_US_CR.TXEN and FLEX_US_CR.RXEN to enable both the transmitter and the receiver.
2. Write FLEX_US_MR.USART_MODE to select the LON mode configuration.
3. Write FLEX_US_BRGR.CD and FLEX_US_BRGR.FP to configure the baud rate.
4. Write COMMT, COLDET, TCOL, CDTAIL, RDMNBM and DMAM in FLEX_US_LONMR to configure the LON
operating mode.
5. Write BETA2, BETA1TX, BETA1RX, PCYCLE, PSNB, NPS, IDTTX and ITDRX respectively in FLEX_US_FIDI,
FLEX_US_LONB1TX, FLEX_US_LONB1RX, FLEX_US_TTGR, FLEX_US_LONPRIO, FLEX_US_LONIDTTX
and FLEX_US_LONIDTRX to set the LON network configuration.
6. Write FLEX_US_MAN.RXIDLEV and FLEX_US_MAN.RX_PL to indicate the receiver line value and select the
preamble pattern to use.
7. Wait until FLEX_US_CSR.RXRDY rises.
8. Read FLEX_US_RHR.RCHR.
9. If all the data and the two CRC bytes have not been read, repeat the two previous steps.
10. Wait until FLEX_US_CSR.LRXD rises.
11. Check the LON errors.
Figure 46-62. Rx Frame
Random Delay
Preamble
l2hdr
Data 1
Data 2
Data N-1
Data N
CRC
CRC
TXRDY
RXRDY
write
FLEX_US_LONL2HDR
read
FLEX_US_RHR
LRXD
© 2020 Microchip Technology Inc.
l2hdr
Data 1
Data 2
Complete Datasheet
Data N-1
Data N
DS60001579C-page 1352
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
46.7.9.12 LON Frame Handling with the Peripheral DMA Controller
The USART can be used in association with the DMA Controller in order to transfer data directly into/from the on- and
off-chip memories without any processor intervention.
The DMA uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The DMA always writes in the
Transmit Holding Register (FLEX_US_THR) and it always reads in the Receive Holding Register (FLEX_US_RHR).
The size of the data written or read by the DMA in the USART is always a byte.
46.7.9.12.1 Configuration
The user can choose between two DMA modes by the DMAM bit in the LON Mode register
(FLEX_US_LONMR):
•
•
DMAM = 1: The LON frame data length (DATAL) is stored in the WRITE buffer and it is written by the DMA in the
Transmit Holding register FLEX_US_THR (instead of the LON Data Length register FLEX_US_LONDL).
DMAM = 0: The LON frame data length (DATAL) is not stored in the WRITE buffer and it must be written by the
user in the LON Data Length Register (FLEX_US_LONDL).
In both DMA modes, L2HDR is considered as a data and its value must be stored in the WRITE buffer as the first
data to write.
Figure 46-63. DMAM = 1
WRITE BUFFER
READ BUFFER
DATAL
L2HDR
L2HDR
NODE ACTION = TRANSMIT
APB bus
DATA 0
NODE ACTION = RECEIVE
USART
LON Controller
DMA
APB bus
DATA 0
|
|
|
|
TXRDY
|
|
|
|
USART
LON Controller
DMA
RXRDY
DATA N
DATA N
Figure 46-64. DMAM = 0
WRITE BUFFER
READ BUFFER
L2HDR
L2HDR
NODE ACTION = TRANSMIT
APB bus
DATA 0
DATA N
DATA 0
USART
LON Controller
DMA
|
|
|
|
NODE ACTION = RECEIVE
APB bus
|
|
|
|
TXRDY
USART
LON Controller
DMA
RXRDY
DATA N
46.7.9.12.2 DMA and Collision Detection
As explained in section comm_type, depending on LON configuration the transmission may be terminated early upon
collision notification which means that the DMA transfer may be stopped before its end.
In case of early end of transmission due to collision detection, the USART in LON mode acts as follows:
•
•
•
•
Send the end of frame trigger.
Hold down TXRDY, thus avoiding any additional DMA transfer.
Set the LTXD, LCOL and LFET flags in FLEX_US_CSR.
Wait for the application to reconfigure the DMA.
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SAM9X60
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•
Wait until the LCOL and LFET flags are cleared through the FLEX_US_CR.RSTSTA bit (it will release the
TXRDY signal).
Figure 46-65. DMA, Collision and Early Frame Termination
Random Delay
Preamble
l2hdr
Data 1
Data N-i
Collision
notification
TXRDY
RXRDY
write
FLEX_US_LONL2HDR
write
FLEX_US_THR
Data 1
Data 2
Data 3
Data (N-i)+1
LTXD
LCOL
LFET
RSTSTA
46.7.10 Test Modes
The USART can be programmed to operate in three different test modes. The internal loopback capability allows onboard diagnostics. In Loopback mode, the USART interface pins are disconnected or not and reconfigured for
loopback internally or externally.
46.7.10.1 Normal Mode
Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.
Figure 46-66. Normal Mode Configuration
Receiver
RXD
Transmitter
TXD
46.7.10.2 Automatic Echo Mode
Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD
pin, as shown in the following figure. Programming the transmitter has no effect on the TXD pin. The RXD pin is still
connected to the receiver input, thus the receiver remains active.
Figure 46-67. Automatic Echo Mode Configuration
Receiver
RXD
Transmitter
TXD
46.7.10.3 Local Loopback Mode
Local Loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in the
following figure. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is
continuously driven high, as in idle state.
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-68. Local Loopback Mode Configuration
RXD
Receiver
1
Transmitter
TXD
46.7.10.4 Remote Loopback Mode
Remote Loopback mode directly connects the RXD pin to the TXD pin, as shown in the following figure. The
transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission.
Figure 46-69. Remote Loopback Mode Configuration
1
Receiver
RXD
TXD
Transmitter
46.7.11 USART FIFOs
46.7.11.1 Overview
The USART includes two FIFOs which can be enabled/disabled using FLEX_US_CR.FIFOEN/FIFODIS. Both the
transmitter and the receiver must be disabled before enabling or disabling the FIFOs, using the
FLEX_US_CR.TXDIS/RXDIS bits.
Writing FLEX_US_CR.FIFOEN to ‘1’ enables a 16-data Transmit FIFO and a 16-data Receive FIFO.
It is possible to write or to read single or multiple data in the same access to FLEX_US_THR/RHR. See sections
USART Single Data Mode and USART Multiple Data Mode.
Figure 46-70. FIFOs Block Diagram
USART
Receive FIFO
Transmit FIFO
TXCHR3
FLEX_US_THR
write
TXCHR2
Threshold
RXCHR3
TXCHR1
TXCHR0
RXCHR2
Threshold
RXCHR1
FLEX_US_RHR
read
RXCHR0
Tx shifter
Rx shifter
TXD RXD
46.7.11.2 Sending Data with FIFO Enabled
When the Transmit FIFO is enabled, write access to FLEX_US_THR loads the Transmit FIFO.
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The FIFO level is provided in FLEX_US_FLR.TXFL. If the FIFO can accept the number of data to be transmitted,
there is no need to monitor FLEX_US_CSR.TXRDY and the data can be successively written in FLEX_US_THR.
If the FIFO cannot accept the data due to insufficient space, wait for the TXRDY flag to be set before writing the data
in FLEX_US_THR.
When the space in the FIFO allows only a portion of the data to be written, the TXRDY flag must be monitored before
writing the remaining data.
Figure 46-71. Sending Data with FIFO Enabled
BEGIN
Read FLEX_US_FESR
Yes
No
Enough space in Transmit FIFO
to write all the data to send?
Write FLEX_US_THR
Read FLEX_US_CSR
TXRDY = 1?
No
All data have been written
in FLEX_US_THR?
No
Yes
Yes
Write FLEX_US_THR
No
All data have been written
in FLEX_US_THR?
Yes
Read FLEX_US_CSR
No
TXEMPTY = 1 ?
Yes
END
46.7.11.3 Receiving Data with FIFO Enabled
When the Receive FIFO is enabled, FLEX_US_RHR access reads the FIFO.
When data are present in the Receive FIFO (RXRDY flag set to ‘1’), the exact number of data can be checked with
FLEX_US_FLR.RXFL. All the data can be read successively in FLEX_US_RHR without checking the RXRDY flag
between each access.
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Figure 46-72. Receiving Data with FIFO Enabled
BEGIN
Read FLEX_US_CSR
RXRDY = 1 ?
No
Yes
Read FLEX_US_FLR
and get the number of data in Receive FIFO
Read FLEX_US_RHR
All data have been read
in FLEX_US_RHR?
No
Yes
END
46.7.11.4 Clearing/Flushing FIFOs
Each FIFO can be cleared/flushed using FLEX_US_CR.TXFCLR/RXFCLR.
46.7.11.5 TXEMPTY, TXRDY and RXRDY Behavior
FLEX_US_CSR.TXEMPTY, FLEX_US_CSR.TXRDY and FLEX_US_CSR.RXRDY flags display a specific behavior
when FIFOs are enabled.
The TXEMPTY flag is cleared as long as there are characters in the Transmit FIFO or in the internal shift register.
TXEMPTY is set when there are no characters in the Transmit FIFO and in the internal shift register.
TXRDY indicates if a data can be written in the Transmit FIFO. Thus the TXRDY flag is set as long as the Transmit
FIFO can accept new data. See figure TXRDY in Single Data Mode and TXRDYM = 0.
RXRDY indicates if an unread data is present in the Receive FIFO. Thus the RXRDY flag is set as soon as one
unread data is in the Receive FIFO. See figure RXRDY in Single Data Mode and RXRDYM = 0 below.
TXRDY and RXRDY behavior can be modified using the TXRDYM and RXRDYM fields in the USART FIFO Mode
Register (FLEX_US_FMR) to reduce the number of accesses to FLEX_US_RHR/THR. However, for some
configurations, the following constraints apply:
•
•
If FLEX_US_MR.MODE9 is set, FLEX_US_FMR.TXRDYM/RXRDYM must be cleared.
If FLEX_US_MR.USART_MODE is set to either LON_MODE, LIN_MASTER or LIN_SLAVE,
FLEX_US_FMR.TXRDYM/RXRDYM must be cleared.
See USART FIFO Mode Register for the FIFO configuration.
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SAM9X60
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Figure 46-73. TXRDY in Single Data Mode and TXRDYM = 0
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop Start
D0
Bit Bit Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop Start
D0
Bit Bit Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop Start
Bit Bit Bit
Write
FLEX_US_THR
RSTSTA = 1
Write
FLEX_US_CR
TXRDY
TXFFF
TXFL
0
1
1
2
3
3
4
FIFO size -1
FIFO full
FIFO size -1
TXEMPTY
Figure 46-74. RXRDY in Single Data Mode and RXRDYM = 0
Baud Rate
Clock
RXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop Start
D0
Bit Bit Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
RSTSTA = 1
Write
FLEX_US_CR
Read
FLEX_US_RHR
RXRDY
RXFL
0
1
FIFO full
FIFO size - 1
FIFO size - 2
0
RXFFF
RXFEF
OVRE
46.7.11.6 USART Single Data Mode
In Single Data mode, only one data is written every time FLEX_US_THR is accessed, and only one data is read
every time FLEX_US_RHR is accessed.
When FLEX_US_FMR.TXRDYM = 0, the Transmit FIFO operates in Single Data mode.
When FLEX_US_FMR.RXRDYM = 0, the Receive FIFO operates in Single Data mode.
If FLEX_US_MR.MODE9 is set, or if FLEX_US_MR.USART_MODE is set to either LON_MODE, LIN_MASTER or
LIN_SLAVE, the FIFOs must operate in Single Data mode.
See USART Receive Holding Register (FLEX_US_RHR) and USART Transmit Holding Register (FLEX_US_THR).
46.7.11.6.1 DMA
The DMA transfer type must be configured in bytes or halfwords when FIFOs operate in Single Data mode (the same
applies when FIFOs are disabled).
46.7.11.7 USART Multiple Data Mode
Multiple Data mode minimizes the number of accesses by concatenating the data to send/read in one access.
When FLEX_US_FMR.TXRDYM > 0, the Transmit FIFO operates in Multiple Data mode.
When FLEX_US_FMR.RXRDYM > 0, the Receive FIFO operates in Multiple Data mode.
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However, Multiple Data mode cannot be used for the following configurations:
•
•
If FLEX_US_MR.MODE9 is set
If FLEX_US_MR.USART_MODE is set to either LON_MODE, LIN_MASTER or LIN_SLAVE
In Multiple Data mode, it is possible to write/read up to four data in one FLEX_US_THR/FLEX_US_RHR access.
The number of data to write/read is defined by the size of the register access. If the access is a byte-size register
access, only one data is written/read, if the access is a halfword size register access, then two data are written/read
and, finally, if the access is a word-size register access, four data are written/read.
Written/read data are always right-aligned, as described in sections USART Receive Holding Register (FIFO Multi
Data) and USART Transmit Holding Register (FIFO Multi Data).
As an example, if the Transmit FIFO is empty and there are six data to send, either of the following write accesses
may be performed:
•
•
•
six FLEX_US_THR-byte write accesses
three FLEX_US_THR-halfword write accesses
one FLEX_US_THR word write access and one FLEX_US_THR halfword write access
With a Receive FIFO containing six data, any of the following read accesses may be performed:
•
•
•
six FLEX_US_RHR-byte read accesses
three FLEX_US_RHR-halfword read accesses
one FLEX_US_RHR-word read access and one FLEX_US_RHR-halfword read access
46.7.11.7.1 TXRDY and RXRDY Configuration
In Multiple Data mode, it is possible to write one or more data in the same FLEX_US_THR/FLEX_US_RHR access.
The TXRDY flag indicates if one or more data can be written in the FIFO depending on the configuration of
FLEX_US_FMR.TXRDYM/RXRDYM.
As an example, if four data are written each time in FLEX_US_THR, it is useful to configure the TXRDYM field to the
value ‘2’ so that the TXRDY flag is at ‘1’ only when at least four data can be written in the Transmit FIFO.
In the same way, if four data are read each time in FLEX_US_RHR, it is useful to configure the RXRDYM field to the
value ‘2’ so that the RXRDY flag is at ‘1’ only when at least four unread data are in the Receive FIFO.
46.7.11.7.2 DMA
When FIFOs operate in Multiple Data mode, the DMA transfer type must be configured in byte, halfword or word
depending on the FLEX_US_FMR.TXRDYM/RXRDYM settings.
46.7.11.8 Transmit FIFO Lock
•
LIN Mode:
If a frame is aborted using the Abort LIN Transmission bit (FLEX_US_CR.LINABT), a lock is set on the Transmit
FIFO, preventing any new frame from being sent until it is cleared. This allows clearing the FIFO if needed, resetting
DMA channels, etc., without any risk.
•
LON Mode:
If a frame is terminated early due to collision, a lock is set on the Transmit FIFO preventing any new frame from being
sent until it is cleared. This allows clearing the FIFO if needed, resetting DMA channels, etc., without any risk.
The TXFLOCK bit in the USART FIFO Event Status Register (FLEX_US_FESR) is used to check the state of the
Transmit FIFO lock.
The Transmit FIFO lock can be cleared by setting FLEX_US_CR.TXFLCLR to ‘1’.
46.7.11.9 FIFO Pointer Error
A FIFO overflow is reported in FLEX_US_FESR.
If the Transmit FIFO is full and a write access is performed on FLEX_US_THR, it generates a Transmit FIFO pointer
error and sets FLEX_US_FESR.TXFPTEF.
In Multiple Data mode, if the number of data written in FLEX_US_THR (according to the register access size) is
greater than the free space in the Transmit FIFO, a Transmit FIFO pointer error is generated and
FLEX_US_FESR.TXFPTEF is set.
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A FIFO underflow is reported in FLEX_US_FESR.
In Multiple Data mode, if the number of data read in FLEX_US_RHR (according to the register access size) is greater
than the number of unread data in the Receive FIFO, a Receive FIFO pointer error is generated and
FLEX_US_FESR.RXFPTEF is set.
No pointer error occurs if the FIFO state/level is checked before writing/reading in FLEX_US_THR/FLEX_US_RHR.
The FIFO state/level can be checked either with TXRDY, RXRDY, TXFL or RXFL. When a pointer error occurs, other
FIFO flags may not behave as expected; their states should be ignored.
If a Transmit pointer error occurs, a transmitter reset must be performed using FLEX_US_CR.RSTTX. If a Receive
pointer error occurs, a receiver reset must be performed using FLEX_US_CR.RSTRX.
46.7.11.10 FIFO Thresholds
Each Transmit and Receive FIFO includes a threshold feature used to set a flag and an interrupt when a FIFO
threshold is crossed. Thresholds are defined as a number of data in the FIFO, and the FIFO state (TXFL or RXFL)
represents the number of data currently in the FIFO.
The Transmit FIFO threshold can be set using the field FLEX_US_FMR.TXFTHRES. Each time the Transmit FIFO
level goes from ‘above threshold’ to ‘equal to or below threshold’, the flag FLEX_US_FESR.TXFTHF is set. The
application is warned that the Transmit FIFO has reached the defined threshold and that it can be reloaded.
The Receive FIFO threshold can be set using the field FLEX_US_FMR.RXFTHRES. Each time the Receive FIFO
level goes from ‘below threshold’ to ‘equal to or above threshold’, the flag FLEX_US_FESR.RXFTHF is set. The
application is warned that the Receive FIFO has reached the defined threshold and that it can be read to prevent an
underflow.
The Receive FIFO threshold 2 can be set using the field FLEX_US_FMR.RXFTHRES2. Each time the Receive FIFO
level goes from ‘above threshold 2’ to ‘equal to or below threshold 2’, the flag FLEX_US_FESR.RXFTHF2 is set. The
application is warned that the Receive FIFO has reached the defined threshold and that it can be read to prevent an
underflow.
The TXFTHF, RXFTHF and RXTHF2 flags can be configured to generate an interrupt using FLEX_US_FIER and
FLEX_US_FIDR.
46.7.11.11 FIFO Flags
FIFOs come with a set of flags which can be configured to generate interrupts through FLEX_US_FIER and
FLEX_US_FIDR.
FIFO flags state can be read in FLEX_US_FESR. They are cleared by writing FLEX_US_CR.RSTSTA to ‘1’.
46.7.12 16-bit Data Protocol Support
When configuring 0xC in the USART_MODE field, the transmitter sends a 16-bit data frame and the receiver expects
an 8-bit data frame. The number of stop bits is defined in the NBSTOP field.
When configuring 0xD in the USART_MODE field, the transmitter sends an 8-bit frame whereas the receiver expects
a 16-bit frame.
The FIFO mode must be enabled by setting FLEX_US_CR.FIFOEN to ‘1’.
A 16-bit frame starts as soon as two 8-bit characters are written in the FLEX_US_THR (assuming 0xC is written in
the USART_MODE field).
46.7.13 USART Register Write Protection
The FLEXCOM operating mode (FLEX_MR.OPMODE) must be set to FLEX_MR_OPMODE_USART to enable
access to the write protection registers.
To prevent any single software error from corrupting USART behavior, certain registers in the address space can be
write-protected by setting the WPEN (Write Protection Enable), WPITEN (Write Protection Interrupt Enable), and/or
WPCREN (Write Protection Control Enable) bits in the USART Write Protection Mode Register (FLEX_US_WPMR).
If a write access to a write-protected register is detected, the Write Protection Violation Status (WPVS) flag in the
USART Write Protection Status Register (FLEX_US_WPSR) is set and the Write Protection Violation Source
(WPVSRC) field indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading FLEX_US_WPSR.
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The following registers can be write-protected when WPEN is set:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
USART Mode Register
USART Baud Rate Generator Register
USART Receiver Timeout Register
USART Transmitter Timeguard Register
USART FI DI RATIO Register
USART IrDA FILTER Register
USART Manchester Configuration Register
USART LON Mode Register
USART LON Beta1 Tx Register
USART LON Beta1 Rx Register
USART LON Priority Register
USART LON IDT Tx Register
USART LON IDT Rx Register
USART IC DIFF Register
USART Comparison Register
The following register(s) can be write-protected when WPITEN is set:
•
•
USART Interrupt Enable Register
USART Interrupt Disable Register
The following register(s) can be write-protected when WPCREN is set:
•
46.8
46.8.1
USART Control Register
SPI Functional Description
Modes of Operation
The SPI operates in Master mode or in Slave mode.
•
•
The SPI operates in Master mode by writing a 1 to the MSTR bit in the SPI Mode Register (FLEX_SPI_MR):
– The pins NPCS0 to NPCS3 are all configured as outputs.
– The SPCK pin is driven.
– The MISO line is wired on the receiver input.
– The MOSI line is driven as an output by the transmitter.
The SPI operates in Slave mode if the MSTR bit in FLEX_SPI_MR is written to 0:
– The MISO line is driven by the transmitter output.
– The MOSI line is wired on the receiver input.
– The SPCK pin is driven by the transmitter to synchronize the receiver.
– The NPCS0 pin becomes an input, and is used as a slave select signal (NSS).
– Pins NPCS1 to NPCS3 are not driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operation. The bit rate generator is activated only
in Master mode.
46.8.2
Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the
CPOL bit in the SPI Chip Select Register (FLEX_SPI_CSR). The clock phase is programmed with the NCPHA bit.
These two parameters determine the edges of the clock signal on which data are driven and sampled. Each of the
two parameters has two possible states, resulting in four possible combinations that are incompatible with one
another. Consequently, a master/slave pair must use the same parameter pair values to communicate. If multiple
slaves are connected and require different configurations, the master must reconfigure itself each time it needs to
communicate with a different slave.
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The following table shows the four modes and corresponding parameter settings.
Table 46-14. SPI Bus Protocol Mode
SPI Mode
CPOL
NCPHA
Shift SPCK Edge
Capture SPCK Edge
SPCK Inactive Level
0
0
1
Falling
Rising
Low
1
0
0
Rising
Falling
Low
2
1
1
Rising
Falling
High
3
1
0
Falling
Rising
High
The following figures show examples of data transfers.
Figure 46-75. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
SPCK cycle (for reference)
1
2
3
4
5
6
7
8
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
MSB
MSB
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
*
NSS
(to slave)
* Not defined.
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Figure 46-76. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
1
SPCK cycle (for reference)
2
3
4
5
7
6
8
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
*
MSB
6
5
4
3
2
1
MSB
6
5
4
3
2
1
LSB
LSB
NSS
(to slave)
* Not defined.
46.8.3
Master Mode Operations
When configured in Master mode, the SPI operates on the clock generated by the internal programmable bit rate
generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the
chip select line to the slave and the serial clock signal (SPCK).
The SPI features two holding registers, the Transmit Data Register (FLEX_SPI_TDR) and the Receive Data Register
(FLEX_SPI_RDR), and a single shift register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer starts when the processor writes to FLEX_SPI_TDR. The written data are
immediately transferred in the shift register and the transfer on the SPI bus starts. While the data in the shift register
is shifted on the MOSI line, the MISO line is sampled and shifted in the shift register. Data cannot be loaded in
FLEX_SPI_RDR without transmitting data. If there is no data to transmit, a dummy data can be used
(FLEX_SPI_TDR filled with ones). When the WDRBT bit is set, a new data cannot be transmitted if FLEX_SPI_RDR
has not been read. If Receiving mode is not required, for example when communicating with a slave receiver only
(such as an LCD), the receive status flags in the SPI Status Register (FLEX_SPI_SR) can be discarded.
Before writing the TDR, the FLEX_SPI_MR.PCS field must be set in order to select a slave.
If new data are written in FLEX_SPI_TDR during the transfer, it is kept in FLEX_SPI_TDR until the current transfer is
completed. Then, the received data are transferred from the shift register to FLEX_SPI_RDR, the data in
FLEX_SPI_TDR is loaded in the shift register and a new transfer starts.
As soon as the FLEX_SPI_TDR is written, the Transmit Data Register Empty (TDRE) flag in FLEX_SPI_SR is
cleared. When the data written in FLEX_SPI_TDR is loaded into the shift register, the FLEX_SPI_SR.TDRE flag is
set. The TDRE bit is used to trigger the Transmit DMA channel (see figure below).
The end of transfer is indicated by FLEX_SPI_SR.TXEMPTY. If a transfer delay (DLYBCT) is greater than 0 for the
last transfer, TXEMPTY is set after the completion of this delay. The peripheral clock can be switched off at this time.
Notes:
1. When the SPI is enabled, the TDRE and TXEMPTY flags are set.
2. The TXEMPTY flag alone cannot be used to detect the end of the buffer DMA transfer.
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SAM9X60
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Figure 46-77. TDRE and TXEMPTY Flag Behavior
Write FLEX_SPI_CR.SPIEN = 1
Write FLEX_SPI_THR
TDRE
Write FLEX_SPI_THR
Write FLEX_SPI_THR
automatic set
THR loaded
in shifter
automatic set
THR loaded
in shifter
automatic set
THR loaded
in shifter
TXEMPTY
Transfer
Transfer
DLYBCT
Transfer
DLYBCT
DLYBCT
The transfer of received data from the shift register to FLEX_SPI_RDR is indicated by the Receive Data Register Full
(RDRF) bit in FLEX_SPI_SR. When the received data are read, the RDRF bit is cleared.
If FLEX_SPI_RDR has not been read before new data are received, the Overrun Error bit (OVRES) in FLEX_SPI_SR
is set. As long as this flag is set, data are loaded in FLEX_SPI_RDR. The user has to read the status register to clear
the OVRES bit.
The following figures show, respectively, a block diagram of the SPI when operating in Master mode and a flow chart
describing how transfers are handled.
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46.8.3.1 Master Mode Block Diagram
Figure 46-78. Master Mode Block Diagram
FLEX_SPI_CSRx
SCBR
Baud Rate Generator
Peripheral clock
SPCK
SPI
Clock
FLEX_SPI_SR
FLEX_SPI_CSRx
BITS
NCPHA
CPOL
LSB
MISO
FLEX_SPI_RDR
RDRF
OVRES
RD
MSB
Shift Register
FLEX_SPI_TDR
TD
MOSI
TDRE
FLEX_SPI_CSRx
FLEX_SPI_RDR
CSAAT
PCS
PS
NPCSx
PCSDEC
FLEX_SPI_MR
PCS
0
Current
Peripheral
FLEX_SPI_TDR
NPCS0
PCS
1
MSTR
MODF
NPCS0
MODFDIS
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46.8.3.2 Master Mode Flowchart
Figure 46-79. Master Mode
SPI Enable
- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the current Chip Select
1
TDRE ?
0
1
PS ?
0
1
0
Fixed
peripheral
Variable
peripheral
FLEX_SPI_TDR(PCS)
= NPCS ?
PS ?
1
Fixed
peripheral
0
CSAAT ?
Variable
peripheral
no
NPCS = FLEX_SPI_TDR(PCS) NPCS = FLEX_SPI_MR(PCS)
yes
FLEX_SPI_MR(PCS)
= NPCS ?
no
NPCS deasserted
NPCS deasserted
Delay DLYBCS
Delay DLYBCS
NPCS = FLEX_SPI_TDR(PCS)
NPCS = FLEX_SPI_MR(PCS),
FLEX_SPI_TDR(PCS)
Delay DLYBS
Serializer = FLEX_SPI_TDR(TD)
TDRE = 1
Data Transfer
FLEX_SPI_RDR(RD) = Serializer
RDRF = 1
Delay DLYBCT
TDRE ?
0
1
1
CSAAT ?
0
NPCS deasserted
Delay DLYBCS
The following figure shows the behavior of Transmit Data Register Empty (TDRE), Receive Data Register (RDRF)
and Transmission Register Empty (TXEMPTY) status flags within FLEX_SPI_SR during an 8-bit data transfer in
Fixed mode without the DMAC involved.
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Figure 46-80. Status Register Flags Behavior
1
2
3
4
5
6
7
8
SPCK
NPCS0
MOSI
(from master)
MSB
6
5
4
3
2
1
LSB
TDRE
RDR read
Write in
FLEX_SPI_TDR
RDRF
MISO
(from slave)
MSB
6
5
4
3
2
1
LSB
TXEMPTY
shift register empty
46.8.3.3 Clock Generation
The SPI bit rate clock is generated by dividing a source clock which can be the peripheral clock or a programmable
clock from the GCLK. The divider can be a value between 1 and 255.
If the SCBR field is programmed to 1 and the clock source is GCLK, the operating bit rate is peripheral clock (refer to
the section “Electrical Characteristics” for the SPCK maximum frequency). Triggering a transfer while SCBR is at 0
can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it to a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the
FLEX_SPI_CSR.SCBR field. This allows the SPI to automatically adapt the bit rate for each interfaced peripheral
without reprogramming.
If GCLK is selected as source clock (FLEX_SPI_MR.BRSRCCLK = 1), the bit rate is independent of the
processor/bus clock. Thus, the processor clock can be changed while SPI is enabled. The processor clock frequency
changes must be performed only by programming the PMC_MCKR.PRES field (refer to the section “Power
Management Controller” (PMC)). Any other method to modify the processor/bus clock frequency (PLL multiplier, etc.)
is forbidden when SPI is enabled.
The peripheral clock frequency must be at least three times higher than GCLK.
46.8.3.4 Transfer Delays
The figure below shows a chip select transfer change and consecutive transfers on the same chip select. Three
delays can be programmed to modify the transfer waveforms:
•
•
•
The delay between the chip selects. It is programmable only once for all chip selects by writing the
FLEX_SPI_MR.DLYBCS field. The SPI slave device deactivation delay is managed through DLYBCS. If there is
only one SPI slave device connected to the master, the DLYBCS field does not need to be configured. If several
slave devices are connected to a master, DLYBCS must be configured depending on the highest deactivation
delay. Refer to the SPI slave device electrical characteristics.
The delay before SPCK, independently programmable for each chip select by writing the DLYBS field. The SPI
slave device activation delay is managed through DLYBS. Refer to the SPI slave device electrical characteristics
to define DLYBS.
The delay between consecutive transfers, independently programmable for each chip select by writing the
DLYBCT field. The time required by the SPI slave device to process received data is managed through DLYBCT.
This time depends on the SPI slave system activity.
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These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
Figure 46-81. Programmable Delays
Chip Select 1
Chip Select 2
SPCK
DLYBCS
DLYBS
DLYBCT
DLYBCT
46.8.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all NPCS
signals are high before and after each transfer.
•
•
Fixed Peripheral Select Mode: SPI exchanges data with only one peripheral.
Fixed Peripheral Select mode is enabled by writing the FLEX_SPI_MR.PS bit to zero. In this case, the current
peripheral is defined by the FLEX_SPI_MR.PCS field, and the FLEX_SPI_TDR. PCS field has no effect.
Variable Peripheral Select Mode: Data can be exchanged with more than one peripheral without having to
reprogram FLEX_SPI_MR.PCS.
Variable Peripheral Select Mode is enabled by setting the FLEX_SPI_MR.PS bit to one. The
FLEX_SPI_TDR.PCS field is used to select the current peripheral. This means that the peripheral selection can
be defined for each new data. The value must be written in a single access to FLEX_SPI_TDR in the following
format:
[xxxxxxx(7-bit) + LASTXFER(1-bit)(1)+ xxxx(4-bit) + PCS (4-bit) + TD (8 to 16-bit data)]
with LASTXFER at 0 or 1 depending on the CSAAT bit, and PCS equal to the chip select to assert, as defined in
section SPI Transmit Data Register (FLEX_SPI_TDR).
Note: 1. Optional
The CSAAT, LASTXFER and CSNAAT bits are discussed in section Peripheral Deselection with DMA.
If LASTXFER is used, the command must be issued after writing the last character. Instead of LASTXFER, the
user can use the SPIDIS command. After the end of the DMA transfer, it is necessary to wait for the TXEMPTY
flag and then write SPIDIS into the SPI Control Register (FLEX_SPI_CR). This does not change the
configuration register values). The NPCS is disabled after the last character transfer. Then, another DMA
transfer can be started if the FLEX_SPI_CR.SPIEN bit has previously been written.
46.8.3.6 SPI Direct Access Memory Controller (DMAC)
In both Fixed and Variable modes, the Direct Memory Access Controller (DMAC) can be used to reduce processor
overhead.
The fixed peripheral selection allows buffer transfers with a single peripheral. Using the DMAC is an optimal means,
as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, if the peripheral
selection is modified, FLEX_SPI_MR must be reprogrammed.
The variable peripheral selection allows buffer transfers with multiple peripherals without reprogramming
FLEX_SPI_MR. Data written in FLEX_SPI_TDR is 32 bits wide and defines the real data to be transmitted and the
destination peripheral. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the
PCS and LASTXFER fields in the MSBs. However, the SPI still controls the number of bits (8 to 16) to be transferred
through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in terms of
memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without
any intervention of the processor.
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46.8.3.7 Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 slave peripherals by decoding the four chip select lines,
NPCS0 to NPCS3 with an external decoder/demultiplexer (see the following figure). This can be enabled by setting
the FLEX_SPI_MR.PCSDEC bit.
When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one
NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is
driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on the NPCS lines of
either FLEX_SPI_MR or FLEX_SPI_TDR (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e., all chip select lines at 1) when not processing any
transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select registers. As a result, when external decoding is activated, each NPCS chip select
defines the characteristics of up to four peripherals. As an example, FLEX_SPI_CRS0 defines the characteristics of
the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Consequently, the user has to
make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. The
following figure shows this type of implementation.
If the CSAAT bit is used, with or without the DMAC, the mode fault detection for NPCS0 line must be disabled. This is
not needed for all other chip select lines since mode fault detection is only on NPCS0.
Figure 46-82. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
SPCK
MISO
MOSI
SPI Master
SPCK MISO MOSI
SPCK MISO MOSI
SPCK MISO MOSI
Slave 0
Slave 1
Slave 14
NSS
NSS
NSS
NPCS0
NPCS1
NPCS2
NPCS3
Decoded chip select lines
External 1-of-n Decoder/Demultiplexer
46.8.3.8 Peripheral Deselection without DMA
During a transfer of more than one data on a Chip Select without the DMA, FLEX_SPI_TDR is loaded by the
processor, the TDRE flag rises as soon as the content of FLEX_SPI_TDR is transferred into the internal shift register.
When this flag is detected high, FLEX_SPI_TDR can be reloaded. If this reload by the processor occurs before the
end of the current transfer, and if the next transfer is performed on the same chip select as the current transfer, the
Chip Select is not deasserted between the two transfers. But depending on the application software handling the SPI
status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor may not
reload FLEX_SPI_TDR in time to keep the chip select active (low). A null DLYBCT value (delay between consecutive
transfers) in FLEX_SPI_CSR, gives even less time for the processor to reload FLEX_SPI_TDR. With some SPI slave
peripherals, if the chip select line must remain active (low) during a full set of transfers, communication errors can
occur.
To facilitate interfacing with such devices, the Chip Select registers [CSR0...CSR3] can be programmed with the Chip
Select Active After Transfer (CSAAT) bit to 1. This allows the chip select lines to remain in their current state (low =
active) until a transfer to another chip select is required. Even if FLEX_SPI_TDR is not reloaded, the chip select
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remains active. To de-assert the chip select line at the end of the transfer, the Last Transfer (LASTXFER) bit in
FLEX_SPI_CR must be set after writing the last data to transmit into FLEX_SPI_TDR.
46.8.3.9 Peripheral Deselection with DMA
DMA provides faster reloads of FLEX_SPI_TDR compared to software. However, depending on the system activity, it
is not guaranteed that FLEX_SPI_TDR is written with the next data before the end of the current transfer.
Consequently, a data can be lost by the deassertion of the NPCS line for SPI slave peripherals requiring the chip
select line to remain active between two transfers. The only way to guarantee a safe transfer in this case is the use of
the CSAAT and LASTXFER bits.
When the CSAAT bit is cleared, the NPCS does not rise in all cases between two transfers on the same peripheral.
During a transfer on a Chip Select, the TDRE flag rises as soon as the content of FLEX_SPI_TDR is transferred into
the internal shift register. When this flag is detected, FLEX_SPI_TDR can be reloaded. If this reload occurs before the
end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the
Chip Select is not deasserted between the two transfers. This can lead to difficulties to interface with some serial
peripherals requiring the chip select to be deasserted after each transfer. To facilitate interfacing with such devices,
FLEX_SPI_CSR can be programmed with the Chip Select Not Active After Transfer (CSNAAT) bit to 1. This allows
the chip select lines to be deasserted systematically during a time “DLYBCS” (the value of the CSNAAT bit is
processed only if the CSAAT bit is cleared for the same chip select).
The following figure shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.
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Figure 46-83. Peripheral Deselection
CSAAT = 0 and CSNAAT = 0
TDRE
NPCS[0..n]
CSAAT = 1 and CSNAAT= 0 / 1
DLYBCT
DLYBCT
A
A
A
A
DLYBCS
A
DLYBCS
PCS = A
PCS = A
Write FLEX_SPI_TDR
TDRE
NPCS[0..n]
DLYBCT
DLYBCT
A
A
A
A
DLYBCS
A
DLYBCS
PCS = A
PCS=A
Write FLEX_SPI_TDR
TDRE
NPCS[0..n]
DLYBCT
DLYBCT
A
A
B
B
DLYBCS
DLYBCS
PCS = B
PCS = B
Write FLEX_SPI_TDR
CSAAT = 0 and CSNAAT = 1
CSAAT = 0 and CSNAAT = 0
DLYBCT
DLYBCT
TDRE
NPCS[0..n]
A
A
A
A
DLYBCS
PCS = A
PCS = A
Write FLEX_SPI_TDR
46.8.3.10 Mode Fault Detection
The SPI has the capability to operate in multi-master environment. Consequently, the NPCS0/NSS line must be
monitored. If one of the masters on the SPI bus is currently transmitting, the NPCS0/NSS line is low and the SPI
must not transmit a data. A mode fault is detected when the SPI is programmed in Master mode and a low level is
driven by an external master on the NPCS0/NSS signal. In multi-master environment, NPCS0, MOSI, MISO and
SPCK pins must be configured in open drain (through the PIO controller). When a mode fault is detected, the
FLEX_SPI_SR.MODF bit is set until FLEX_SPI_SR is read and the SPI is automatically disabled until it is re-enabled
by writing the FLEX_SPI_CR.SPIEN bit to 1.
By default, the mode fault detection is enabled. The user can disable it by setting the FLEX_SPI_MR.MODFDIS bit.
46.8.4
SPI Slave Mode
When operating in Slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits until NSS goes active before receiving the serial clock from an external master. When NSS falls, the
clock is validated and the data are loaded in FLEX_SPI_RDR according to the configuration value of the
FLEX_SPI_CSR0.BITS field. These bits are processed following a phase and a polarity defined respectively by the
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FLEX_SPI_CSR0.NCPHA and FLEX_SPI_CSR0.CPOL bits. Note that the BITS field, CPOL bit and NCPHA bit of
the other Chip Select registers have no effect when the SPI is programmed in Slave mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
Note: For more information on the BITS field, see also the note below the FLEX_SPI_CSRx register bitmap in
section SPI Chip Select Register
When all bits are processed, the received data are transferred in FLEX_SPI_RDR and the RDRF bit rises. If
FLEX_SPI_RDR has not been read before new data are received, the Overrun Error bit (OVRES) in FLEX_SPI_SR
is set. As long as this flag is set, data are loaded in FLEX_SPI_RDR. The user must read FLEX_SPI_SR to clear the
OVRES bit.
When a transfer starts, the data shifted out is the data present in the shift register. If no data has been written in
FLEX_SPI_TDR, the last data received is transferred. If no data has been received since the last reset, all bits are
transmitted low, as the shift register resets to 0.
When a first data is written in FLEX_SPI_TDR, it is transferred immediately in the shift register and the TDRE flag
rises. If new data is written, it remains in FLEX_SPI_TDR until a transfer occurs, i.e., NSS falls and there is a valid
clock on the SPCK pin. When the transfer occurs, the last data written in FLEX_SPI_TDR is transferred in the shift
register and the TDRE flag rises. This enables frequent updates of critical variables with single transfers.
Then, a new data is loaded in the shift register from FLEX_SPI_TDR. If no character is ready to be transmitted, i.e.,
no character has been written in FLEX_SPI_TDR since the last load from FLEX_SPI_TDR to the shift register,
FLEX_SPI_TDR is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in FLEX_SPI_SR.
If NSS rises between two characters, it must be kept high for two MCK clock periods or more and the next SPCK
capture edge must not occur less than four MCK periods after NSS rise.
In slave mode, if the NSS line rises and the received character length does not match the configuration defined in
FLEX_SPI_CSR0.BITS, the flag SFERR is set in FLEX_SPI_SR.
The following figure shows a block diagram of the SPI when operating in Slave mode.
Figure 46-84. Slave Mode Functional Block Diagram
SPCK
NSS
SPI
Clock
SPIEN
SPIENS
SPIDIS
FLEX_SPI_SR
FLEX_SPI_CSR0
BITS
NCPHA
CPOL
MOSI
LSB
RD
Shift Register
FLEX_SPI_TDR
TD
46.8.5
RDRF
OVRES
SFERR
FLEX_SPI_RDR
MSB
MISO
TDRE
SPI Comparison Function on Received Character
The comparison is only relevant for SPI Slave mode (MSTR = 0 in FLEX_US_MR).
In Active mode, the CMP flag in FLEX_SPI_SR is raised. It is set when the received character matches the
conditions programmed in the SPI Comparison Register (FLEX_SPI_CMPR). The CMP flag is set as soon as
FLEX_SPI_RDR is loaded with the new received character. The CMP flag is cleared by reading FLEX_SPI_SR.
The SPI Comparison Register can be programmed to provide different comparison methods. These are listed below:
•
If VAL1 equals VAL2, then the comparison is performed on a single value and the flag is set to 1 if the received
character equals VAL1.
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•
•
If VAL1 is strictly lower than VAL2, then any value between VAL1 and VAL2 sets the CMP flag.
If VAL1 is strictly higher than VAL2, then the flag CMP is set to 1 if any received character equals VAL1 or VAL2.
When FLEX_SPI_MR.CMPMODE is cleared, all received data is loaded in FLEX_SPI_RDR and the CMP flag
provides the status of the comparison result.
By setting the CMPMODE bit, the comparison result triggers the start of FLEX_SPI_RDR loading (see the figure
below). The trigger condition exists as soon as the received character value matches the conditions defined by VAL1
and VAL2 in FLEX_SPI_CMPR. The comparison trigger event is restarted by writing a 1 to the
FLEX_SPI_CR.REQCLR bit.
The value programmed in VAL1 and VAL2 fields must not exceed the maximum value of the received character (see
BITS field in SPI Chip Select Register (FLEX_SPI_CSR)).
Figure 46-85. Receive Data Register Management
CMPMODE = 1, VAL1 = VAL2 = 0x06
Peripheral
Clock
NSS
MOSI
0x0F
0x06
0xF0
0x08
0x06
RDRF rising enabled
RDRF
Write REQCLR
RDR
46.8.6
0x0F
0x06
0xF0
0x08
0x06
SPI FIFOs
46.8.6.1 Overview
The SPI includes two FIFOs which can be enabled/disabled using the FLEX_SPI_CR.FIFOEN/FIFODIS. The SPI
module must be disabled before enabling or disabling the SPI FIFOs (FLEX_SPI_CR.SPIDIS).
Writing FLEX_SPI_CR.FIFOEN to ‘1’ enables a FIFO_DEPTH-data Transmit FIFO and a FIFO_DEPTH-data Receive
FIFO.
It is possible to write or to read single or multiple data in the same access to FLEX_SPI_TDR/RDR. See sections SPI
Single Data Mode and SPI Multiple Data Mode.
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Figure 46-86. FIFOs Block Diagram
SPI
Transmit FIFO
Receive FIFO
.......
TD3
FLEX_SPI_TDR
write
TD2
Threshold
TD1
.......
RD3
TD0
RD2
Threshold
.......
RD1
.......
RD0
Tx shifter
(Master) MOSI
(Slave) MISO
FLEX_SPI_RDR
read
Rx shifter
(Master) MISO
(Slave) MOSI
46.8.6.2 Sending Data with FIFO Enabled
When the Transmit FIFO is enabled, write access to FLEX_SPI_TDR loads the Transmit FIFO.
The FIFO level is provided in FLEX_SPI_FLR.TXFL. If the FIFO can accept the number of data to be transmitted,
there is no need to monitor FLEX_SPI_SR.TDRE and the data can be successively written in FLEX_SPI_TDR.
If the FIFO cannot accept the data due to insufficient space, wait for the TDRE flag to be set before writing the data in
FLEX_SPI_TDR.
When the space in the FIFO allows only a portion of the data to be written, the TDRE flag must be monitored before
writing the remaining data.
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Figure 46-87. Sending Data with FIFO Enabled
BEGIN
Read FLEX_SPI_FLR.TXFL
Yes
Enough space in Transmit FIFO
to write the data to send?
Write FLEX_SPI_TDR
No
Read FLEX_SPI_SR
TDRE = 1 ?
No
Data has been written
in FLEX_SPI_TDR ?
No
Yes
Yes
Write FLEX_SPI_TDR
No
All data has been written
in FLEX_SPI_TDR ?
Yes
Read FLEX_SPI_SR
No
TXEMPTY = 1 ?
Yes
END
46.8.6.3 Receiving Data with FIFO Enabled
When the Receive FIFO is enabled, FLEX_SPI_RDR access reads the FIFO.
When data are present in the Receive FIFO (RDRF flag set to ‘1’), the exact number of data can be checked with
FLEX_SPI_FLR.RXFL. All the data can be read successively in FLEX_SPI_RDR without checking the RDRF flag
between each access.
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Figure 46-88. Receiving Data with FIFO Enabled
BEGIN
Read FLEX_SPI_SR
RDRF = 1 ?
No
Yes
Read FLEX_SPI_FLR.RXFL
and get the number of data in Receive FIFO
Read FLEX_SPI_RDR
All data has been read
in FLEX_SPI_RDR ?
No
Yes
END
46.8.6.4 Clearing/Flushing FIFOs
Each FIFO can be cleared/flushed using FLEX_SPI_CR.TXFCLR/RXFCLR.
46.8.6.5 TXEMPTY, TDRE and RDRF Behavior
FLEX_SPI_SR.TXEMPTY, FLEX_SPI_SR.TDRE and FLEX_SPI_SR.RDRF flags display a specific behavior when
FIFOs are enabled.
The TXEMPTY flag is cleared as long as there are characters in the Transmit FIFO or in the internal shift register.
TXEMPTY is set when there are no characters in the Transmit FIFO and in the internal shift register.
TDRE indicates if a data can be written in the Transmit FIFO. Thus the TDRE flag is set as long as the Transmit FIFO
can accept new data. See figure TDRE in Single Data Mode and TXRDYM = 0.
RDRF indicates if an unread data is present in the Receive FIFO. Thus the RDRF flag is set as soon as one unread
data is in the Receive FIFO. See figure RDRF in Single Data Mode and RXRDYM = 0.
TDRE and RDRF behavior can be modified using the TXRDYM and RXRDYM fields in the SPI FIFO Mode Register
(FLEX_SPI_FMR) to reduce the number of accesses to FLEX_SPI_TDR/RDR. However, for some configurations, the
following constraints apply:
•
•
When the Variable Peripheral Select mode is used (FLEX_SPI_MR.PS=1), TXRDYM/RXRDYM must be
cleared.
In Master mode (FLEX_SPI_MR.MSTR=1), RXRDYM must be cleared.
As an example, in Master mode, the Transmit FIFO can be loaded with multiple data in the same access by
configuring TXRDYM>0.
See SPI FIFO Mode Register (FLEX_SPI_FMR) for the FIFO configuration.
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Figure 46-89. TDRE in Single Data Mode and TXRDYM = 0
1
3
2
SPCK
NPCS0
MOSI
MSB 6
(from master)
MISO
MSB
(from slave)
6
5
4
3
2
1 LSB MSB
6
5
4
3
2
1
LSB MSB
6
5
4
3
2
1
LSB
5
4
3
2
1 LSB MSB
6
5
4
3
2
1
LSB MSB
6
5
4
3
2
1
LSB
Write
FLEX_SPI_TDR
Read
FLEX_SPI_SR
TDRE
TXFFF
1
0
1
TXFL
2
3
2
FIFO size -1 FIFO full
FIFO size -1
TXEMPTY
Figure 46-90. RDRF in Single Data Mode and RXRDYM = 0
1
3
2
SPCK
NPCS0
MOSI
(from master)
MISO
(from slave)
MSB 6
MSB
6
5
4
3
2
1 LSB
MSB 6
5
4
3
2
1
LSB MSB
6
5
4
3
2
1
LSB
5
4
3
2 1 LSB
MSB 6
5
4
3
2
1
LSB MSB
6
5
4
3
2
1
LSB
Read
FLEX_SPI_RDR
Read
FLEX_SPI_SR
RDRF
RXFFF
RXFEF
RXFL
0
1
FIFO full
FIFO size -1
0
46.8.6.6 SPI Single Data Mode
In Single Data mode, only one data is written every time FLEX_SPI_TDR is accessed, and only one data is read
every time FLEX_SPI_RDR is accessed.
When FLEX_SPI_FMR.TXRDYM = 0, the Transmit FIFO operates in Single Data mode.
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When FLEX_SPI_FMR.RXRDYM = 0, the Receive FIFO operates in Single Data mode.
If Master mode is used (FLEX_SPI_MR.MSTR=1), the Receive FIFO must operate in Single Data mode.
If Variable Peripheral Select mode is used (FLEX_SPI_MR.PS=1), the Transmit FIFO must operate in Single Data
mode.
See sections SPI Transmit Data Register and SPI Receive Data Register.
46.8.6.6.1 DMA
When FIFOs operate in Single Data mode, the DMA transfer type must be configured either in bytes, halfwords or
words depending on FLEX_SPI_MR.PS bit value and FLEX_SPI_CSRx.BITS field value.
The same applies when FIFOs are disabled.
46.8.6.7 SPI Multiple Data Mode
Multiple Data mode minimizes the number of accesses by concatenating the data to send/read in one access.
When FLEX_SPI_FMR.TXRDYM > 0, the Transmit FIFO operates in Multiple Data mode.
When FLEX_SPI_FMR.RXRDYM > 0, the Receive FIFO operates in Multiple Data mode.
Multiple data can be read from the Receive FIFO only in Slave mode (FLEX_SPI_MR.MSTR=0).
The Transmit FIFO can be loaded with multiple data in the same access by configuring TXRDYM>0 and when
FLEX_SPI_MR.PS=0.
In Multiple Data mode, up to two data can be written in one FLEX_SPI_TDR write access. It is also possible to read
up to four data in one FLEX_SPI_RDR access if FLEX_SPI_CSRx.BITS is configured to ‘0’ (8-bit data size) and up to
two data if FLEX_SPI_CSRx.BITS is configured to a value other than ‘0’ (more than 8-bit data size).
The number of data to write/read is defined by the size of the register access. If the access is a byte-size register
access, only one data is written/read. If the access is a halfword size register access, then up to two data are read
and only one data is written. Lastly, if the access is a word-size register access, then up to four data are read and up
to two data are written.
Written/read data are always right-aligned, as described in sections SPI Receive Data Register (FIFO Multiple Data,
8-bit), SPI Receive Data Register (FIFO Multiple Data, 16-bit) and SPI Transmit Data Register (FIFO Multiple Data, 8to 16-bit).
As an example, if the Transmit FIFO is empty and there are six data to send, either of the following write accesses
may be performed:
•
•
six FLEX_SPI_TDR-byte write accesses
three FLEX_SPI_TDR-halfword write accesses
With a Receive FIFO containing six data, any of the following read accesses may be performed:
•
•
•
six FLEX_SPI_RDR-byte read accesses
three FLEX_SPI_RDR-halfword read accesses
one FLEX_SPI_RDR-word read access and one FLEX_SPI_RDR-halfword read access
46.8.6.7.1 TDRE and RDRF Configuration
In Multiple Data mode, it is possible to write one or more data in the same FLEX_SPI_TDR/RDR access. The TDRE
flag indicates if one or more data can be written in the FIFO depending on the configuration of
FLEX_SPI_FMR.TXRDYM/RXRDYM.
As an example, if two data are written each time in FLEX_SPI_TDR, it is useful to configure the TXRDYM field to the
value ‘1’ so that the TDRE flag is at ‘1’ only when at least two data can be written in the Transmit FIFO.
Similarly, if four data are read each time in FLEX_SPI_RDR, it is useful to configure the RXRDYM field to the value
‘2’ so that the RDRF flag is at ‘1’ only when at least four unread data are in the Receive FIFO.
46.8.6.7.2 DMA
It is mandatory to configure DMA channel size (byte, halfword or word) according to FLEX_SPI_FMR.TXRDYM/
RXRDYM configuration. See section SPI Multiple Data Mode for constraints.
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46.8.6.8 FIFO Pointer Error
A FIFO overflow is reported in FLEX_SPI_SR.
If the Transmit FIFO is full and a write access is performed on FLEX_SPI_TDR, it generates a Transmit FIFO pointer
error and sets FLEX_SPI_SR.TXFPTEF.
In Multiple Data mode, if the number of data written in FLEX_SPI_TDR (according to the register access size) is
greater than the free space in the Transmit FIFO, a Transmit FIFO pointer error is generated and
FLEX_SPI_SR.TXFPTEF is set.
A FIFO underflow is reported in FLEX_SPI_SR.
In Multiple Data mode, if the number of data read in FLEX_SPI_RDR (according to the register access size) is
greater than the number of unread data in the Receive FIFO, a Receive FIFO pointer error is generated and
FLEX_SPI_SR.RXFPTEF is set.
No pointer error occurs if the FIFO state/level is checked before writing/reading in FLEX_SPI_TDR/SPI_RDR. The
FIFO state/level can be checked either with TXRDY, RXRDY, TXFL or RXFL. When a pointer error occurs, other
FIFO flags may not behave as expected; their states should be ignored.
If a pointer error occurs, a software reset must be performed using FLEX_SPI_CR.SWRST (configuration will be
lost).
46.8.6.9 FIFO Thresholds
Each Transmit and Receive FIFO includes a threshold feature used to set a flag and an interrupt when a FIFO
threshold is crossed. Thresholds are defined as a number of data in the FIFO, and the FIFO state (TXFL or RXFL)
represents the number of data currently in the FIFO.
The Transmit FIFO threshold can be set using the field FLEX_SPI_FMR.TXFTHRES. Each time the Transmit FIFO
level goes from ‘above threshold’ to ‘equal to or below threshold’, the flag FLEX_SPI_SR.TXFTHF is set. The
application is warned that the Transmit FIFO has reached the defined threshold and that it can be reloaded.
The Receive FIFO threshold can be set using the field FLEX_SPI_FMR.RXFTHRES. Each time the Receive FIFO
level goes from ‘below threshold’ to ‘equal to or above threshold’, the flag FLEX_SPI_SR.RXFTHF is set. The
application is warned that the Receive FIFO has reached the defined threshold and that it can be read to prevent an
underflow.
The TXFTHF and RXFTHF flags can be configured to generate an interrupt using FLEX_SPI_IER and
FLEX_SPI_IDR.
46.8.6.10 FIFO Flags
FIFOs come with a set of flags which can be configured to generate interrupts through FLEX_SPI_IER and
FLEX_SPI_IDR.
FIFO flags state can be read in FLEX_SPI_SR. They are cleared when FLEX_SPI_SR is read.
46.8.7
SPI Register Write Protection
The FLEXCOM operating mode (FLEX_MR.OPMODE) must be set to FLEX_MR_OPMODE_SPI to enable access to
the write protection registers.
To prevent any single software error from corrupting SPI behavior, certain registers in the address space can be
write-protected by setting the WPEN (Write Protection Enable), WPITEN (Write Protection Interrupt Enable), and/or
WPCREN (Write Protection Control Enable) bits in the SPI Write Protection Mode Register (FLEX_SPI_WPMR).
If a write access to a write-protected register is detected, the Write Protection Violation Status (WPVS) flag in the SPI
Write Protection Status Register (FLEX_SPI_WPSR) is set and the Write Protection Violation Source (WPVSRC)
field indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading FLEX_SPI_WPSR.
The following registers can be write-protected when WPEN is set:
•
•
•
SPI Mode Register
SPI Chip Select Register
SPI Comparison Register
The following registers can be write-protected when WPITEN is set:
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
•
•
SPI Interrupt Enable Register
SPI Interrupt Disable Register
The following register can be write-protected when WPCREN is set:
•
SPI Control Register
46.9
TWI Functional Description
46.9.1
Transfer Format
The data put on the TWD line must be 8 bits long. Data are transferred MSB first; each byte must be followed by an
acknowledgement. The number of bytes per transfer is unlimited (see figure below).
Figure 46-91. Transfer Format
TWD
TWCK
Start
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
Each transfer begins with a START condition and terminates with a STOP condition (see figure below).
•
•
A high-to-low transition on the TWD line while TWCK is high defines the START condition.
A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 46-92. START and STOP Conditions
TWD
TWCK
Start
46.9.2
Stop
Modes of Operation
The TWI has different modes of operation:
•
•
•
•
•
•
Master Transmitter mode (Standard, Fast mode, Fast mode Plus)
Master Receiver mode (Standard, Fast mode, Fast mode Plus)
Multi-master Transmitter mode (Standard, Fast mode, Fast mode Plus)
Multi-master Receiver mode (Standard, Fast mode, Fast mode Plus)
Slave Transmitter mode (Standard, Fast mode, Fast mode Plus and High-speed mode)
Slave Receiver mode (Standard, Fast mode, Fast mode Plus and High-speed mode)
These modes are described in the following sections.
46.9.3
Master Mode
46.9.3.1 Definition
The master is the device that starts a transfer, generates a clock and stops it.
46.9.3.2 Programming Master Mode
The following fields must be programmed before entering Master mode:
1.
DADR (+ IADRSZ + IADR if a 10-bit device is addressed): The device address is used to access slave devices
in Read or Write mode.
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2.
3.
4.
CWGR + CKDIV + CHDIV + CLDIV: Clock waveform.
SVDIS: Disables Slave mode.
MSEN: Enables Master mode.
Note: If the TWI is already in Master mode, the device address (DADR) can be configured without disabling
the Master mode.
46.9.3.3 Transfer Speed/Bit Rate
The TWI speed is defined in FLEX_TWI_CWGR. The TWI bit rate can be based either on the peripheral clock if the
BRSRCCLK bit value is 0 or on a programmable clock source provided by the GCLK if the BRSRCCLK bit value is 1.
If BRSRCCLK = 1, the bit rate is independent of the processor/peripheral clock and thus processor/peripheral clock
frequency can be changed without affecting the TWI transfer rate.
The GCLK frequency must be at least three times lower than the peripheral clock frequency.
46.9.3.4 Master Transmitter Mode
After the master initiates a START condition when writing into the Transmit Holding register FLEX_TWI_THR, it
sends a 7-bit slave address, configured in the Master Mode Register (DADR in FLEX_TWI_MMR), to notify the slave
device. The bit following the slave address indicates the transfer direction, 0 in this case (FLEX_TWI_MMR.MREAD
= 0).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (ninth
pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the
acknowledge. If the slave does not acknowledge the byte, then the Not Acknowledge flag (NACK) is set in the TWI
Status Register (FLEX_TWI_SR) of the master and a STOP condition is sent. Alternatively, if the
FLEX_TWI_MMR.NOAP bit is set, no stop condition will be sent and a START or STOP condition must be triggered
manually through the FLEX_TWI_CR.START or FLEX_TWI_CR.STOP bit once the software is ready for the
transmission of the condition. The NACK flag must be cleared by reading the TWI Status Register (FLEX_TWI_SR)
before the next write into the TWI Transmit Holding Register (FLEX_TWI_THR). As with the other status bits, an
interrupt can be generated if enabled in the interrupt enable Register (FLEX_TWI_IER). If the slave acknowledges
the byte, the data written in FLEX_TWI_THR is then shifted in the internal shifter and transferred. When an
acknowledge is detected, the TXRDY bit is set until a new write in FLEX_TWI_THR.
TXRDY is used as transmit ready for the DMA transmit channel.
Note: To clear the TXRDY flag in Master mode, write the FLEX_TWI_CR.MSDIS bit to 1, then write the
FLEX_TWI_CR.MSEN bit to 1.
While no new data is written in FLEX_TWI_THR, the serial clock line is tied low. When new data is written in
FLEX_TWI_THR, the SCL is released and the data is sent. To generate a STOP event, the STOP command must be
performed by writing in the STOP field of the TWI Control Register (FLEX_TWI_CR).
After a master write transfer, the Serial Clock line is stretched (tied low) while no new data is written in
FLEX_TWI_THR or until a STOP command is performed.
See the following figures.
Figure 46-93. Master Write with One Data Byte
STOP Command sent (write in FLEX_TWI_CR)
TWD
S
DADR
W
A
DATA
A
P
TXCOMP
TXRDY
Write FLEX_TWI_THR (DATA)
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Figure 46-94. Master Write with Multiple Data Bytes
STOP command performed
(by writing in FLEX_TWI_CR)
S
TWD
DADR
W
A
DATA n
A
DATA n+1
A
DATA n+2
A
P
TWCK
TXCOMP
TXRDY
Write FLEX_TWI_THR (Data n)
Write FLEX_TWI_THR (Data n+1)
Write FLEX_TWI_THR (Data n+2)
Last data sent
Figure 46-95. Master Write with One Byte Internal Address and Multiple Data Bytes
STOP command performed
(by writing in FLEX_TWI_CR)
TWD
S
DADR
W
A
IADR
A
DATA n
A
DATA n+1
A
DATA n+2
A
P
TWCK
TXCOMP
TXRDY
Write FLEX_TWI_THR (Data n)
Write FLEX_TWI_THR (Data n+1)
Write FLEX_TWI_THR (Data n+2)
Last data sent
46.9.3.5 Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit
slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this
case (FLEX_TWI_MMR.MREAD = 1). During the acknowledge clock pulse (9th pulse), the master releases the data
line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line
during this clock pulse and sets the FLEX_TWI_SR.NACK bit if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received,
the master sends an acknowledge condition to notify the slave that the data has been received except for the last
data (see figure "Master Read with One Data Byte" below). When the FLEX_TWI_SR.RXRDY bit is set, a character
has been received in the Receive Holding Register (FLEX_TWI_RHR). The RXRDY bit is reset when reading
FLEX_TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must
be set at the same time. See figure "Master Read with One Data Byte" below. When a multiple data byte read is
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-last data received
(same condition applies for START bit to generate a repeated start). See figure "Master Read with Multiple Data
Bytes" below. For internal address usage, see section Internal Address.
If FLEX_TWI_RHR is full (RXRDY high) and the master is receiving data, the serial clock line will be tied low before
receiving the last bit of the data and until FLEX_TWI_RHR is read. Once FLEX_TWI_RHR is read, the master will
stop stretching the serial clock line and end the data reception. See figure "Master Read Clock Stretching with
Multiple Data Bytes" below.
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When receiving multiple bytes in Master Read mode, if the next-to-last access is not read (the RXRDY flag
remains high), the last access will not be completed until FLEX_TWI_RHR is read. The last access stops
on the next-to-last bit (clock stretching). When FLEX_TWI_RHR is read there is only half a bit period to
send the STOP bit (or START bit) command, else another read access might occur (spurious access).
WARNING
A possible workaround is to set the STOP bit (or START bit) before reading FLEX_TWI_RHR on the next-to-last
access (within IT handler).
Figure 46-96. Master Read with One Data Byte
TWD
S
DADR
R
A
DATA
N
P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
Figure 46-97. Master Read with Multiple Data Bytes
TWD
S
DADR
R
A
DATA n
A
DATA (n+1)
A
DATA (n+m)-1
A
DATA (n+m)
N
P
TXCOMP
Write START Bit
RXRDY
Read RHR
DATA n
Read RHR
DATA (n+1)
Read RHR
DATA (n+m)-1
Read RHR
DATA (n+m)
Write STOP Bit
after next-to-last data read
Figure 46-98. Master Read Clock Stretching with Multiple Data Bytes
STOP command performed
(by writing in FLEX_TWI_CR)
Clock Streching
TWD
S
DADR
W
A
DATA n
A
DATA n+1
A
DATA n+2
A
P
TWCK
TXCOMP
RXRDY
Read RHR (Data n)
Read RHR (Data n+1)
Read RHR (Data n+2)
RXRDY is used as receive ready trigger event for the DMA receive channel.
46.9.3.6 Internal Address
The TWI interface can perform transfers with 7-bit slave address devices and with 10-bit slave address devices.
46.9.3.6.1 7-bit Slave Addressing
When addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write)
accesses to reach one or more data bytes, e.g., within a memory page location in a serial memory. When performing
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read operations with an internal address, the TWI performs a write operation to set the internal address into the slave
device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See figure Master Read with One, Two or
Three Bytes Internal Address and One Data Byte.
See figures Master Write with One, Two or Three Bytes Internal Address and One Data Byte and Internal Address
Usage for the master write operation with internal address.
The three internal address bytes are configurable through the Master Mode Register (FLEX_TWI_MMR).
If the slave device supports only a 7-bit address, i.e., no internal address, IADRSZ must be configured to 0.
The abbreviations listed below are used in the following figures:
S
Start
Sr
Repeated Start
P
Stop
W
Write
R
Read
A
Acknowledge
N
Not Acknowledge
DADR
Device Address
IADR
Internal Address
Figure 46-99. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address
TWD
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
W
A
IADR(15:8)
A
IADR(7:0)
A
DATA
A
W
A
IADR(7:0)
A
DATA
A
DATA
A
P
Two bytes internal address
TWD
S
DADR
P
One byte internal address
TWD
S
DADR
P
Figure 46-100. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address
TWD
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
Sr
DADR
R
A
DATA
N
P
Two bytes internal address
TWD
S
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
Sr
A
IADR(7:0)
A
Sr
R
A
DADR
R
A
DATA
N
P
One byte internal address
TWD
S
DADR
W
DADR
DATA
N
P
46.9.3.6.2 10-bit Slave Addressing
For a slave address higher than seven bits, the user must configure the address size (IADRSZ) and set the other
slave address bits in the Internal Address Register (FLEX_TWI_IADR). The two remaining internal address bytes,
IADR[15:8] and IADR[23:16], can be used the same way as in 7-bit slave addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1.
2.
3.
Program IADRSZ = 1
Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
Program FLEX_TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
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The following figure shows a byte write to a TWI EEPROM. This demonstrates the use of internal addresses to
access the device.
Figure 46-101. Internal Address Usage
S
T
A
R
T
Device
Address
W
R
I
T
E
FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
S
T
O
P
DATA
0
M
S
B
LR A
S / C
BW K
M
S
B
A
C
K
LA
SC
BK
A
C
K
46.9.3.7 Repeated Start
In addition to Internal Address mode, repeated start (Sr) can be generated manually by writing the START bit at the
end of a transfer instead of the STOP bit. In such case the parameters of the next transfer (direction, SADR, etc.) will
need to be set before writing the START bit at the end of the previous transfer.
See section Read/Write Flowcharts.
46.9.3.8 Bus Clear Command
The TWI interface can perform a Bus Clear Command:
1.
2.
Configure the Master mode (DADR, CKDIV, etc).
Start the transfer by setting the FLEX_TWI_CR.CLEAR bit.
Note: If an alternative command is used (ACMEN bit = 1), the DATAL field must be cleared.
46.9.3.9 SMBus Mode
SMBus mode is enabled when the FLEX_TWI_CR.SMBEN bit is written to one. SMBus mode operation is similar to
I²C operation with the following exceptions:
1.
2.
3.
4.
Only 7-bit addressing can be used.
The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These
timeout values must be programmed into FLEX_TWI_SMBTR.
Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
A set of addresses has been reserved for protocol handling, such as alert response address (ARA) and host
header (HH) address. Address matching on these addresses can be enabled by configuring FLEX_TWI_CR
appropriately.
46.9.3.9.1 Packet Error Checking
Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing the FLEX_TWI_CR.PECEN
bit to one enables automatic PEC handling in the current transfer. Transfers with and without PEC can freely be
intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every
bit transmitted or received, so that PEC handling on combined transfers will be correct.
In Master Transmitter mode, the master calculates a PEC value and transmits it to the slave after all data bytes have
been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself.
If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values
differ, data was corrupted, and the slave will return a NACK value. Some slaves may not be able to check the
received PEC in time to return a NACK if an error occurred. In this case, the slave should always return an ACK after
the PEC byte, and some other mechanism must be implemented to verify that the transmission was received
correctly.
In Master Receiver mode, the slave calculates a PEC value and transmits it to the master after all data bytes have
been transmitted. Upon reception of this PEC byte, the master will compare it to the PEC value it has computed itself.
If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and the
FLEX_TWI_SR.PECERR bit is set. In Master Receiver mode, the PEC byte is always followed by a NACK
transmitted by the master, since it is the last byte in the transfer.
In combined transfers, the PECRQ bit should only be set in the last of the combined transfers. If Alternative
Command mode is enabled, only the NPEC bit should be set.
Consider the following transfer:
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK, P
See section Read/Write Flowcharts for detailed flowcharts.
46.9.3.9.2 Timeouts
The FLEX_TWI_SMBTR.TLOWS/TLOWM fields configure the SMBus timeout values. If a timeout occurs, the master
transmits a STOP condition and leaves the bus. Furthermore, the FLEX_TWI_SR.TOUT bit is set.
46.9.3.10 SMBus Quick Command (Master Mode Only)
The TWI interface can perform a quick command:
1.
2.
3.
Configure the Master mode (DADR, CKDIV, etc).
Write the FLEX_TWI_MMR.MREAD bit at the value of the one-bit command to be sent.
Start the transfer by setting the FLEX_TWI_CR.QUICK bit.
Note: If an alternative command is used (ACMEN bit = 1), the DATAL field must be cleared.
Figure 46-102. SMBus Quick Command
TWD
S
DADR
R/W
A
P
TXCOMP
TXRDY
Write QUICK command in FLEX_TWI_CR
46.9.3.11 Alternative Command
Another way to configure the transfer is to enable the Alternative Command mode with the ACMEN bit of the TWI
Control Register.
In this mode, the transfer is configured through the TWI Alternative Command Register. It is possible to define a
simple read or write transfer or a combined transfer with a repeated start.
In order to set a simple transfer, the DATAL field and the DIR field of the TWI Alternative Command Register must be
filled accordingly and the NDATAL field must be cleared. To begin the transfer, either set the START bit in the TWI
Control Register in case of a read transfer, or write the TWI Transmit Holding Register in case of a write transfer.
For a combined transfer linked by a repeated start, the NDATAL field must be filled with the length of the second
transfer and NDIR with the corresponding direction.
The PEC and NPEC bits are used to set a PEC field. In the case of a single transfer with PEC, the PEC bit must be
set. In the case of a combined transfer, the NPEC bit must be set.
Note: If the Alternative Command mode is used, the TWIHS_MMR.IADRSZ field must be set to 0.
See Read/Write Flowcharts for detailed flowcharts.
46.9.3.12 Handling Errors in Alternative Command
In case of NACK generated by a slave device or SMBus timeout error, the TWI stops immediately the frame, but the
DMA transfer may still be active. To prevent a new frame to be restarted with the remaining DMA data (transmit), the
TWI prevents any start of frame until the FLEX_TWI_SR.LOCK flag is cleared.
The FLEX_TWI_SR.LOCK bit indicates the state of the TWI (locked or not locked).
When the TWI is locked, no transfer can begin until the LOCK is cleared using the FLEX_TWI_CR.LOCKCLR bit and
until the error flags are cleared reading FLEX_TWI_SR.
In case of error, FLEX_TWI_THR may have been loaded with a new data. The FLEX_TWI_CR.THRCLR bit can be
used to flush FLEX_TWI_THR. If the THRCLR bit is set, the TXRDY and TXCOMP flags are set.
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SAM9X60
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46.9.3.13 Read/Write Flowcharts
The flowcharts shown in this section provide examples for read and write operations. A polling or interrupt method
can be used to check the status bits. The interrupt method requires that the Interrupt Enable Register
(FLEX_TWI_IER) be configured first.
Figure 46-103. TWI Write Operation with Single Data Byte without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Transfer direction bit
Write ==> bit MREAD = 0
Load Transmit register
FLEX_TWI_THR = Data to send
Write STOP Command
FLEX_TWI_CR = STOP
Read Status register
TXRDY = 1?
No
Yes
Read Status register
No
TXCOMP = 1?
Yes
Transfer finished
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Figure 46-104. TWI Write Operation with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Internal address size (IADRSZ)
- Transfer direction bit
Write ==> bit MREAD = 0
Set the internal address
FLEX_TWI_IADR = address
Load transmit register
FLEX_TWI_THR = Data to send
Write STOP command
FLEX_TWI_CR = STOP
Read Status register
No
TXRDY = 1?
Yes
Read Status register
TXCOMP = 1?
No
Yes
Transfer finished
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Figure 46-105. TWI Write Operation with Multiple Data Bytes with or without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
No
Internal address size = 0?
Set the internal address
FLEX_TWI_IADR = address
Yes
Load Transmit register
FLEX_TWI_THR = Data to send
Read Status register
FLEX_TWI_THR = data to send
No
TXRDY = 1?
Yes
Yes
Data to send?
No
Write STOP Command
FLEX_TWI_CR = STOP
Read Status register
No
TXCOMP = 1?
Yes
END
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-106. SMBus Write Operation with Multiple Data Bytes with or without Internal Address and PEC
Sending
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS + SMBEN + PECEN
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
No
Internal address size = 0?
Set the internal address
FLEX_TWI_IADR = address
Yes
Load Transmit register
FLEX_TWI_THR = Data to send
Read Status register
FLEX_TWI_THR = data to send
No
TXRDY = 1?
Yes
Yes
Data to send?
No
Write PECRQ Command
Write STOP Command
FLEX_TWI_CR = STOP & PECRQ
Read Status register
No
TXCOMP = 1?
Yes
END
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Figure 46-107. SMBus Write Operation with Multiple Data Bytes with PEC and Alternative Command Mode
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
FLEX_TWI_CR = MSEN + SVDIS + ACMEN + SMBEN + PECEN
Set the Master Mode register:
- Device slave address
Set the Alternative Command Register:
- DATAL, DIR, PEC
Load Transmit register
FLEX_TWI_THR = Data to send
Read Status register
FLEX_TWI_THR = data to send
No
TXRDY = 1?
Yes
Yes
Data to send?
No
Read Status register
No
TXCOMP = 1?
Yes
END
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-108. TWI Write Operation with Multiple Data Bytes and Read Operation with Multiple Data Bytes
(Sr)
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 0
No
Internal address size = 0?
Set the internal address
FLEX_TWI_IADR = address
Yes
Load Transmit register
FLEX_TWI_THR = Data to send
Read Status register
FLEX_TWI_THR = data to send
No
TXRDY = 1?
Yes
Data to send ?
Yes
No
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- FLEX_TWI_IADR = address (if Internal address size = 0)
- Transfer direction bit
Read ==> bit MREAD = 1
Set the next transfer
parameters and
send the repeated start
command
Start the transfer
FLEX_TWI_CR = START
Read Status register
No
RXRDY = 1?
Yes
Read Receive Holding register (FLEX_TWI_RHR)
No
Last data to read
but one?
Yes
Stop the transfer
FLEX_TWI_CR = STOP
Read Status register
No
RXRDY = 1?
Yes
Read Receive Holding register (FLEX_TWI_RHR)
Read status register
TXCOMP = 1?
No
Yes
END
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SAM9X60
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Figure 46-109. TWI Write Operation with Multiple Data Bytes + Read Operation and Alternative Command
Mode + PEC
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS + ACMEN
Set the Master Mode register:
- Device slave address
Set the Alternative Command Register:
- DATAL, PEC, NDATAL, NPEC
- DIR = WRITE
- NDIR = READ
Load Transmit register
FLEX_TWI_THR = Data to send
Read Status register
FLEX_TWI_THR = data to send
TXRDY = 1?
No
Yes
Data to send ?
Yes
No
Read Status register
RXRDY = 1?
No
Yes
Read Receive Holding register (FLEX_TWI_RHR)
No
Last data to read ?
Yes
Read status register
TXCOMP = 1?
No
Yes
END
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Figure 46-110. TWI Read Operation with Single Data Byte without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Transfer direction bit
Read ==> bit MREAD = 1
Start the transfer
FLEX_TWI_CR = START | STOP
Read status register
RXRDY = 1?
No
Yes
Read Receive Holding Register
Read Status register
TXCOMP = 1?
No
Yes
END
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SAM9X60
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Figure 46-111. TWI Read Operation with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (IADRSZ)
- Transfer direction bit
Read ==> bit MREAD = 1
Set the internal address
FLEX_TWI_IADR = address
Start the transfer
FLEX_TWI_CR = START | STOP
Read Status register
RXRDY = 1?
No
Yes
Read Receive Holding register
Read Status register
TXCOMP = 1?
No
Yes
END
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Figure 46-112. TWI Read Operation with Multiple Data Bytes with or without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
No
Internal address size = 0?
Set the internal address
FLEX_TWI_IADR = address
Yes
Start the transfer
FLEX_TWI_CR = START
Read Status register
RXRDY = 1?
No
Yes
Read Receive Holding register (FLEX_TWI_RHR)
No
Last data to read
but one?
Yes
Stop the transfer
FLEX_TWI_CR = STOP
Read Status register
RXRDY = 1?
No
Yes
Read Receive Holding register (FLEX_TWI_RHR)
Read status register
TXCOMP = 1?
No
Yes
END
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SAM9X60
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Figure 46-113. TWI Read Operation with Multiple Data Bytes with or without Internal Address with PEC
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
FLEX_TWI_CR = MSEN + SVDIS + SMBEN + PECEN
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
Internal address size = 0?
No
Set the internal address
FLEX_TWI_IADR = address
Yes
Start the transfer
FLEX_TWI_CR = START
Read Status register
RXRDY = 1?
No
Yes
Read Receive Holding register (FLEX_TWI_RHR)
No
Last data to read
but one ?
Yes
Check PEC and Stop the transfer
FLEX_TWI_CR = STOP & PECRQ
Read Status register
No
RXRDY = 1?
Yes
Read Receive Holding register (FLEX_TWI_RHR)
Read status register
TXCOMP = 1?
No
Yes
END
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Figure 46-114. TWI Read Operation with Multiple Data Bytes with Alternative Command Mode with PEC
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
FLEX_TWI_CR = MSEN + SVDIS + SMBEN + ACMEN + PECEN
Set the Master Mode register:
- Device slave address
Set the Alternative Command Register:
- DATAL, DIR, PEC
Start the transfer
FLEX_TWI_CR = START
Read Status register
RXRDY = 1?
No
Yes
Read Receive Holding register (FLEX_TWI_RHR)
No
Last data to read ?
Yes
Read Status register
RXRDY = 1?
No
Yes
Read the received PEC:
Read Receive Holding register (FLEX_TWI_RHR)
Read status register
TXCOMP = 1?
No
Yes
END
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SAM9X60
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Figure 46-115. TWI Read Operation with Multiple Data Bytes + Write Operation with Multiple Data Bytes (Sr)
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
No
Internal address size = 0?
Set the internal address
FLEX_TWI_IADR = address
Yes
Start the transfer
FLEX_TWI_CR = START
Read Status register
No
RXRDY = 1?
Yes
Read Receive Holding register (FLEX_TWI_RHR)
No
Last data to read
but one?
Yes
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
-FLEX_TWI_IADR = address (if Internal address size = 0)
- Transfer direction bit
Write ==> bit MREAD = 0
Set the next transfer
parameters and
send the repeated start
command
Start the transfer (Sr)
FLEX_TWI_CR = START
Read Status register
Read the last byte
of the first read transfer
RXRDY = 1?
No
Yes
Read Receive Holding register (FLEX_TWI_RHR)
Read Status register
FLEX_TWI_THR = data to send
No
TXRDY = 1?
Yes
Yes
Data to send ?
No
Stop the transfer
FLEX_TWI_CR = STOP
Read status register
TXCOMP = 1?
No
Yes
END
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SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-116. TWI Read Operation with Multiple Data Bytes + Write with Alternative Command Mode with
PEC
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS + ACMEN
Set the Master Mode register:
- Device slave address
Set the Alternative Command Register:
- DATAL, PEC, NDATAL, NPEC
- DIR = WRITE
- NDIR = READ
Load Transmit register
FLEX_TWI_THR = Data to send
Read Status register
FLEX_TWI_THR = data to send
TXRDY = 1?
No
Yes
Data to send ?
Yes
No
Read Status register
RXRDY = 1?
No
Yes
Read Receive Holding register (FLEX_TWI_RHR)
No
Last data to read ?
Yes
Read status register
TXCOMP = 1?
No
Yes
END
46.9.4
Multi-Master Mode
46.9.4.1 Definition
In Multi-Master mode, more than one master may handle the bus at the same time without data corruption by using
arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops
(arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a STOP.
When the STOP is detected, the master that has lost arbitration may put its data on the bus by respecting arbitration.
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Arbitration is illustrated in figure "Arbitration Cases" below.
46.9.4.2 Different Multi-Master Modes
Two Multi-Master modes may be distinguished:
•
•
TWI as Master Only—TWI is considered as a master only and will never be addressed.
TWI as Master or Slave—TWI may be either a master or a slave and may be addressed.
Note: Arbitration in supported in both Multi-Master modes.
46.9.4.2.1 TWI as Master Only
In this mode, the TWI is considered as a master only (MSEN is always at one) and must be driven like a master with
the ARBLST (ARBitration Lost) flag in addition.
If arbitration is lost (ARBLST = 1), the user must reinitiate the data transfer.
If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically
waits for a STOP condition on the bus to initiate the transfer (see figure "User Sends Data While the Bus is Busy"
below).
Note: The state of the bus (busy or free) is not indicated in the user interface.
46.9.4.2.2 TWI as Master or Slave
The automatic reversal from master to slave is not supported in case of a lost arbitration.
Then, in the case where TWI may be either a master or a slave, the user must manage the pseudo Multi-Master
mode described in the steps below:
1.
2.
3.
4.
5.
6.
7.
Program the TWI in Slave mode (SADR + MSDIS + SVEN) and perform a slave access (if TWI is addressed).
If the TWI has to be set in Master mode, wait until TXCOMP flag is at 1.
Program the Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR).
As soon as the Master mode is enabled, the TWI scans the bus in order to detect if it is busy or free. When the
bus is considered as free, the TWI initiates the transfer.
As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the
user must monitor the ARBLST flag.
If the arbitration is lost (ARBLST is = 1), the user must program the TWI in Slave mode in case the master that
won the arbitration needs to access the TWI.
If the TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode.
Note: In case the arbitration is lost and the TWI is addressed, the TWI will not acknowledge even if it is
programmed in Slave mode as soon as ARBLST = 1. Then the master must repeat SADR.
Figure 46-117. User Sends Data While the Bus is Busy
TWCK
START sent by the TWI
STOP sent by the master
TWD
DATA sent by a master
DATA sent by the TWI
Bus is busy
Bus is free
TWI DATA transfer
A transfer is programmed
(DADR + W + START + Write THR)
© 2020 Microchip Technology Inc.
Transfer is kept
Bus is considered as free
Transfer is initiated
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Figure 46-118. Arbitration Cases
TWCK
TWD
TWCK
Data from a Master
S
1
0
0 1 1
Data from TWI
S
1
0
1
TWD
S
1
0
0
P
Arbitration is lost
TWI stops sending data
1 1
Data from the master
P
Arbitration is lost
S
1
0
1
S
1
0
0 1
1
S
1
0
0 1
1
The master stops sending data
Data from the TWI
ARBLST
Bus is busy
Transfer is kept
TWI DATA transfer
A transfer is programmed
(DADR + W + START + Write THR)
Bus is free
Transfer is stopped
Transfer is programmed again
(DADR + W + START + Write THR)
Bus is considered as free
Transfer is initiated
The flowchart shown in the following figure gives an example of read and write operations in Multi-Master mode.
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Figure 46-119. Multi-Master Mode
START
Program the SLAVE mode:
SADR + MSDIS + SVEN
Read Status Register
SVACC = 1 ?
Yes
GACC = 1 ?
No
No
No
No
SVREAD = 1 ?
EOSACC = 1 ?
TXRDY = 1 ?
Yes
Yes
Yes
No
TXCOMP = 1 ?
Write in FLEX_TWI_THR
No
RXRDY= 1 ?
Yes
Yes
Read FLEX_TWI_RHR
Need to perform
a master access ?
No
No
GENERAL CALL TREATMENT
Yes
Decoding of the
programming sequence
No
Prog seq
OK ?
Change SADR
Program the Master mode
DADR + SVDIS + MSEN + CLK + R / W
Read Status Register
Yes
No
ARBLST = 1 ?
Yes
Yes
No
MREAD = 1 ?
RXRDY= 0 ?
TXRDY= 0 ?
No
No
Read FLEX_TWI_RHR
Yes
Yes
Data to read?
Data to send ?
Yes
Write in FLEX_TWI_THR
No
No
Stop Transfer
FLEX_TWI_CR = STOP
Read Status Register
Yes
46.9.5
TXCOMP = 0 ?
No
Slave Mode
46.9.5.1 Definition
Slave mode is defined as a mode where the device receives the clock and the address from another device called
the master.
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In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and
STOP conditions are always provided by the master).
46.9.5.2 Programming Slave Mode
The following fields must be programmed before entering Slave mode:
1.
2.
3.
4.
FLEX_TWI_SMR.SADR: The slave device address is used in order to be accessed by master devices in Read
or Write mode.
(Optional) FLEX_TWI_SMR.MASK can be set to mask some SADR address bits and thus allow multiple
address matching.
FLEX_TWI_CR.MSDIS: Disables the Master mode.
FLEX_TWI_CR.SVEN: Enables the Slave mode.
As the device receives the clock, values written in FLEX_TWI_CWGR are not processed.
46.9.5.3 Receiving Data
After a START or repeated START condition is detected, and if the address sent by the master matches the slave
address programmed in the SADR (Slave Address) field, the SVACC (Slave Access) flag is set and SVREAD (Slave
Read) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected,
EOSACC (End Of Slave Access) flag is set.
46.9.5.3.1 Read Sequence
In the case of a read sequence (SVREAD is high), the TWI transfers data written in FLEX_TWI_THR (TWI Transmit
Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected.
Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC is reset.
As soon as data is written in FLEX_TWI_THR, the TXRDY (Transmit Holding Register Ready) flag is reset, and it is
set when the internal shifter is empty and the sent data acknowledged or not. If the data is not acknowledged, the
NACK flag is set.
Note that a STOP or a repeated START always follows a NACK.
See figure "Read Access Ordered by a Master" below.
Note: To clear the TXRDY flag in Slave mode, write the FLEX_TWI_CR.SVDIS bit to 1, then write the
FLEX_TWI_CR.SVEN bit to 1.
46.9.5.3.2 Write Sequence
In the case of a write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon
as a character has been received in FLEX_TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading
FLEX_TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is
detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
See figure "Write Access Ordered by a Master" below.
46.9.5.3.3 Clock Stretching Sequence
If FLEX_TWI_THR or FLEX_TWI_RHR is not written/read in time, the TWI performs a clock stretching.
Clock stretching information is given by the SCLWS (Clock Wait State) bit.
See figures "Clock Stretching in Read Mode" and "Clock Stretching in Write Mode" below.
Note: Clock stretching can be disabled by configuring the FLEX_TWI_SMR.SCLWSDIS bit. In that case, UNRE and
OVRE flags will indicate underrun (when FLEX_TWI_THR is not filled on time) or overrun (when FLEX_TWI_RHR is
not read on time).
46.9.5.3.4 General Call
In the case where a GENERAL CALL is performed, the GACC (General Call Access) flag is set.
After GACC is set, it is up to the user to interpret the meaning of the GENERAL CALL and to decode the new
address programming sequence.
See figure "Master Performs a General Call" below.
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46.9.5.4 Data Transfer
46.9.5.4.1 Read Operation
The Read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address
(SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in FLEX_TWI_THR.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
The following figure describes the read operation.
Figure 46-120. Read Access Ordered by a Master
SADR matches,
TWI answers with an ACK
SADR does not match,
TWI answers with a NACK
TWD
S
ADR
R
NA
DATA
NA
P/S/Sr
SADR R
A
DATA
A
ACK/NACK from the Master
A
DATA
NA
S/Sr
TXRDY
Read RHR
Write THR
NACK
SVACC
SVREAD
SVREAD has to be taken into account only while SVACC is active
EOSACC
Notes:
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from FLEX_TWI_THR to the internal shifter and set when this
data has been acknowledged or non acknowledged.
46.9.5.4.2 Write Operation
The Write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC
is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in FLEX_TWI_RHR.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
The following figure describes the write operation.
Figure 46-121. Write Access Ordered by a Master
SADR does not match,
TWI answers with a NACK
TWD
S
ADR
W
NA
DATA
NA
SADR matches,
TWI answers with an ACK
P/S/Sr
SADR W
A
DATA
A
Read RHR
A
DATA NA
S/Sr
RXRDY
SVACC
SVREAD
SVREAD has to be taken into account only while SVACC is active
EOSACC
Notes:
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the internal shifter to FLEX_TWI_RHR, and reset when
this data is read.
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46.9.5.4.3 General Call
The general call is performed in order to change the address of the slave.
If a GENERAL CALL is detected, GACC is set.
After the detection of general call, it is up to the user to decode the commands which follow.
In case of a WRITE command, the user has to decode the programming sequence and program a new SADR if the
programming sequence matches.
The following figure describes the general call access.
Figure 46-122. Master Performs a General Call
0000000 + W
TXD
S
GENERAL CALL
RESET command = 00000110X
WRITE command = 00000100X
A
Reset or write DADD
A
DATA1
A
DATA2
A
New SADR
A
P
New SADR
Programming sequence
SVACC
Cleared on read
GACC
Note: This method enables to create a user-specific programming sequence by choosing the number of
programming bytes. The programming sequence has to be provided to the master.
46.9.5.4.4 Clock Stretching
In both Read and Write modes, it may happen that the FLEX_TWI_THR/FLEX_TWI_RHR buffer is not filled/emptied
before the transmission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock
stretching mechanism is implemented.
Note: Clock stretching can be disabled by setting the FLEX_TWI_SMR.SCLWSDIS bit. In that case, the UNRE and
OVRE flags indicate an underrun (when FLEX_TWI_THR is not filled on time) or an overrun (when FLEX_TWI_RHR
is not read on time).
— Clock Stretching in Read Mode
The clock is tied low if the internal shifter is empty and if a STOP or REPEATED START condition was not detected.
It is tied low until the internal shifter is loaded.
The following figure describes clock stretching in Read mode.
Figure 46-123. Clock Stretching in Read Mode
FLEX_TWI_THR
S
SADR
R
DATA1
1
DATA0
A
DATA0
A
DATA2
A
DATA1
XXXXXXX
DATA2
NA
S
2
TWCK
Write THR
CLOCK is tied low by the TWI
as long as THR is empty
SCLWS
TXRDY
SVACC
SVREAD
As soon as a START is detected
TXCOMP
FLEX_TWI_THR is transmitted to the internal shifter.
ACK or NACK from the master
1
The data is memorized in FLEX_TWI_THR until a new value is written.
2
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching.
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Notes:
1. TXRDY is reset when data has been written in FLEX_TWI_THR to the internal shifter, and set when this data
has been acknowledged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address
different from SADR.
3. SCLWS is automatically set when the clock stretching mechanism is started.
— Clock Stretching in Write Mode
The clock is tied low if the internal shifter and FLEX_TWI_RHR are full. If a STOP or REPEATED_START condition
was not detected, it is tied low until FLEX_TWI_RHR is read.
The following figure describes the clock stretching in Write mode.
Figure 46-124. Clock Stretching in Write Mode
TWCK
CLOCK is tied low by the TWI as long as RHR is full
TWD
S
SADR
W
A
DATA0
A
A
DATA1
FLEX_TWI_RHR
DATA2
NA
DATA1
DATA0 is not read in the RHR
S
ADR
DATA2
SCLWS
SCL is stretched after the acknowledge of DATA1
RXRDY
Rd DATA0
Rd DATA1
Rd DATA2
SVACC
SVREAD
As soon as a START is detected
TXCOMP
Notes:
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address
different from SADR.
2. SCLWS is automatically set when the clock stretching mechanism is started and automatically reset when the
mechanism is finished.
46.9.5.4.5 Reversal after a Repeated Start
— Reversal of Read to Write
The master initiates the communication by a read command and finishes it by a write command.
The following figure describes the repeated start and the reversal from Read mode to Write mode.
Figure 46-125. Repeated Start and Reversal from Read Mode to Write Mode
FLEX_TWI_THR
TWD
DATA0
S
SADR
R
A
DATA0
DATA1
A
DATA1
NA
Sr
SADR
W
A
DATA2
FLEX_TWI_RHR
A
DATA3
DATA2
A
P
DATA3
SVACC
SVREAD
TXRDY
RXRDY
EOSACC
TXCOMP
Cleared after read
As soon as a START is detected
(1)
Note:
1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
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— Reversal of Write to Read
The master initiates the communication by a write command and finishes it by a read command.
The following figure describes the repeated start and the reversal from Write mode to Read mode.
Figure 46-126. Repeated Start and Reversal from Write Mode to Read Mode
DATA2
FLEX_TWI_THR
DATA3
(1)
TWD
S
SADR
W
A
DATA0
FLEX_TWI_RHR
A
DATA1
DATA0
A
Sr
SADR
R
A
DATA2
A
DATA3
NA
P
DATA1
SVACC
SVREAD
TXRDY
RXRDY
Read FLEX_TWI_RHR
EOSACC
TXCOMP
Cleared after read
As soon as a START is detected
(2)
Notes:
1. In this case, if FLEX_TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK.
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
46.9.5.4.6 SMBus Mode
SMBus mode is enabled when the FLEX_TWI_CR.SMEN bit is written to one. SMBus mode operation is similar to
I²C operation with the following exceptions:
1.
2.
3.
4.
Only 7-bit addressing can be used.
The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These
timeout values must be programmed into FLEX_TWI_SMBTR.
Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
A set of addresses have been reserved for protocol handling, such as alert response address (ARA) and host
header (HH) address. Address matching on these addresses can be enabled by configuring FLEX_TWI_CR
appropriately.
— Packet Error Checking
Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing the FLEX_TWI_CR.PECEN
bit to one will send/check the FLEX_TWI_ACR.PEC field in the current transfer. The PEC generator is always
updated on every bit transmitted or received, so that PEC handling on following linked transfers will be correct.
In Slave Receiver mode, the master calculates a PEC value and transmits it to the slave after all data bytes have
been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself.
If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values
differ, data was corrupted, and the slave will return a NACK value. The FLEX_TWI_SR.PECERR bit is set
automatically if a PEC error occurred.
In Slave Transmitter mode, the slave calculates a PEC value and transmits it to the master after all data bytes have
been transmitted. Upon reception of this PEC byte, the master will compare it to the PEC value it has computed itself.
If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and the master
must take appropriate action.
See section Slave Read/Write Flowcharts for detailed flowcharts.
— Timeouts
The TWI SMBus Timing Register (FLEX_TWI_SMBTR) configures the SMBus timeout values. If a timeout occurs, the
slave will leave the bus. Furthermore, the FLEX_TWI_SR.TOUT bit is set.
46.9.5.5 High-Speed Slave Mode
High-speed mode is enabled when the FLEX_TWI_CR.HSEN bit is written to one. Furthermore, the analog pad filter
must be enabled, the FLEX_TWI_FILTR.PADFEN bit must be written to one and the FLEX_TWI_FILTR.FILT bit must
be cleared. TWI High-speed mode operation is similar to TWI operation with the following exceptions:
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1.
2.
A master code is received first at normal speed before entering High-speed mode period.
When TWI High-speed mode is active, clock stretching is only allowed after acknowledge (ACK), notacknowledge (NACK), START (S) or repeated START (Sr) (asa consequence, OVF may happen).
TWI High-speed mode allows transfers of up to 3.4 Mbit/s.
The TWI slave in High-speed mode requires that the peripheral clock runs at a minimum of 14 MHz if slave clock
stretching is enabled (SCLWSDIS bit at ‘0’). If slave clock stretching is disabled (SCLWSDIS bit at ‘1’), the peripheral
clock must run at a minimum of 11 MHz (assuming the system has no latency).
Notes:
1. When slave clock stretching is disabled, FLEX_TWI_RHR must always be read before receiving the next data
(MASTER write frame). It is strongly recommended to use either the polling method on the
FLEX_TWI_SR.RXRDY flag, or the DMA. If the receive is managed by an interrupt, the TWI interrupt priority
must be set to the right level and its latency minimized to avoid receive overrun.
2. When slave clock stretching is disabled, FLEX_TWI_THR must be filled with the first data to send before the
beginning of the frame (MASTER read frame). It is strongly recommended to use either the polling method on
the FLEX_TWI_SR.TXRDY flag, or the DMA. If the transmit is managed by an interrupt, the TWI interrupt
priority must be set to the right level and its latency minimized to avoid transmit underrun.
46.9.5.5.1 Read/Write Operation
A TWI high-speed frame always begins with the following sequence:
1.
2.
3.
START condition (S)
Master Code (0000 1XXX)
Not-acknowledge (NACK)
When the TWI is programmed in Slave mode and TWI High-speed mode is activated, master code matching is
activated and internal timings are set to match the TWI High-speed mode requirements.
Figure 46-127. High-Speed Mode Read/Write
FS Mode
S
MASTER CODE
HS Mode
NA
Sr
SADR
R/W
A
FS Mode
S
MASTER CODE
FS Mode
DATA
A/NA
P
FS Mode
HS Mode
NA
Sr
SADR
R/W
A
DATA
A/NA
Sr
P
SADR
46.9.5.5.2 Usage
TWI High-speed mode usage is the same as the standard TWI (see section Read/Write Flowcharts).
46.9.5.6 Alternative Command
In Slave mode, the Alternative Command mode is used when the SMBus mode is enabled to send or check the PEC
byte.
The Alternative Command mode is enabled by setting the ACMEN bit of the TWIHS Control Register, and the
transfer is configured in TWIHS_ACR.
For a combined transfer with PEC, only the NPEC bit in TWIHS_ACR must be set as the PEC byte is sent once at
the end of the frame.
See section Slave Read/Write Flowcharts for detailed flowcharts.
46.9.5.7 Slave Read/Write Flowcharts
The flowchart shown in the following figure gives an example of read and write operations in Slave mode. A polling or
interrupt method can be used to check the status bits. The interrupt method requires that the Interrupt Enable
Register (FLEX_TWI_IER) be configured first.
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Figure 46-128. Read/Write in Slave Mode
START
Set the SLAVE mode:
SADR + MSDIS + SVEN
Read Status Register
SVACC = 1 ?
No
No
No
EOSACC = 1 ?
GACC = 1 ?
No
SVREAD = 1 ?
TXRDY = 1 ?
No
No
Write in FLEX_TWI_THR
TXCOMP = 1 ?
RXRDY = 1 ?
No
END
Read FLEX_TWI_RHR
GENERAL CALL TREATMENT
Decoding of the
programming sequence
Prog seq
OK ?
No
Change SADR
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Figure 46-129. Read/Write in Slave Mode with SMBus PEC
START
Set the SLAVE mode:
SADR + MSDIS + SVEN + SMBEN + PECEN
Read Status Register
SVACC = 1 ?
GACC = 1 ?
No
SVREAD = 1 ?
No
No
No
EOSACC = 1 ?
TXRDY = 1 ?
No
RXRDY = 1 ?
No
Last data sent ?
TXCOMP = 1 ?
Last data to read ?
END
Write in PECRQ
No
Write in FLEX_TWI_THR
No
Write in PECRQ
Read FLEX_TWI_RHR
GENERAL CALL TREATMENT
Decoding of the
programming sequence
Prog seq
OK ?
No
Change SADR
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Figure 46-130. Read/Write in Slave Mode with SMBus PEC and Alternative Command Mode
START
Set the SLAVE mode:
SADR + MSDIS + SVEN + SMBEN + PECEN + ACMEN
Read Status Register
SVACC = 1 ?
No
No
No
GACC = 1 ?
No
SVREAD = 1 ?
EOSACC = 1 ?
TXRDY = 1 ?
No
No
Write in FLEX_TWI_THR
TXCOMP = 1 ?
RXRDY= 1 ?
No
END
Read FLEX_TWI_RHR
GENERAL CALL TREATMENT
Decoding of the
programming sequence
Prog seq
OK ?
No
Change SADR
46.9.6
TWI FIFOs
46.9.6.1 Overview
The TWI includes two FIFOs which can be enabled/disabled using FLEX_TWI_CR.FIFOEN/FIFODIS. Both Master
and Slave modes must be disabled before enabling or disabling the FIFOs (FLEX_TWI_CR.MSDIS/SVDIS).
Writing FLEX_TWI_CR.FIFOEN to ‘1’ enables a 16-data Transmit FIFO and a 16-data Receive FIFO.
It is possible to write or to read single or multiple data in the same access to FLEX_TWI_THR/RHR, depending on
FLEX_TWI_FMR.TXRDYM/RXRDYM settings.
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Figure 46-131. FIFOs Block Diagram
TWI
Receive FIFO
Transmit FIFO
.......
TXDATA3
FLEX_TWI_THR
write
TXDATA2
Threshold
TXDATA0
.......
RXDATA3
TXDATA1
RXDATA2
Threshold
.......
RXDATA1
.......
RXDATA0
Tx shifter
FLEX_TWI_RHR
read
Rx shifter
TWD
46.9.6.2 Sending Data with FIFO Enabled
When the Transmit FIFO is enabled, write access to FLEX_TWI_THR loads the Transmit FIFO.
The Transmit FIFO level is provided in FLEX_TWI_FLR.TXFL. If the FIFO can accept the number of data to be
transmitted, there is no need to monitor FLEX_TWI_SR.TXRDY and the data can be successively written in
FLEX_TWI_THR.
If the FIFO cannot accept the data due to insufficient space, wait for the TXRDY flag to be set before writing the data
in FLEX_TWI_THR.
When the space in the FIFO allows only a portion of the data to be written, the TXRDY flag must be monitored before
writing the remaining data.
See figures Sending Data with FIFO Enabled in Master Mode and Sending/Receiving Data with FIFO Enabled in
Slave Mode.
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Figure 46-132. Sending Data with FIFO Enabled in Master Mode
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
FLEX_TWI_CR = MSEN + SVDIS + ACMEN
Set the Master Mode register:
- Device slave address
Set the Alternative Command Register:
- DATAL, DIR
Yes
Enough space in the FIFO
to write all the data to send?
No
Read FLEX_TWI_SR
Load Transmit register
FLEX_TWI_THR = Data to send
No
TXRDY = 1?
No
Yes
All the data have been written
in FLEX_TWI_THR?
Load Transmit register
FLEX_TWI_THR = Data to send
No
All the data have been written
in FLEX_TWI_THR ?
Read Status register
No
TXCOMP = 1?
Yes
END
46.9.6.3 Receiving Data with FIFO Enabled
When the Receive FIFO is enabled, FLEX_TWI_RHR access reads the FIFO.
When data are present in the Receive FIFO (RXRDY flag set to ‘1’), the exact number of data can be checked with
FLEX_TWI_FLR.RXFL. All the data can be read successively in FLEX_TWI_RHR without checking the
FLEX_TWI_SR.RXRDY flag between each access.
See figures Receiving Data with FIFO Enabled in Master Mode and Sending/Receiving Data with FIFO Enabled in
Slave Mode.
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Figure 46-133. Receiving Data with FIFO Enabled in Master Mode
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in FLEX_TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
FLEX_TWI_CR = MSEN + SVDIS + ACMEN
Set the Master Mode register:
- Device slave address
Set the Alternative Command Register:
- DATAL
- DIR = READ
Start the transfer
FLEX_TWI_CR = START
Read FLEX_TWI_SR
RXRDY = 1?
No
Yes
Read FLEX_TWI_FSR
and get the number of data in the Receive FIFO
Read FLEX_TWI_RHR
All data have been read
in FLEX_TWI_RHR?
No
Yes
Read status register
TXCOMP = 1?
No
Yes
END
46.9.6.4 Sending/Receiving with FIFO Enabled in Slave Mode
See sections Sending Data with FIFO Enabled and Receiving Data with FIFO Enabled for details.
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Figure 46-134. Sending/Receiving Data with FIFO Enabled in Slave Mode
START
Set the SLAVE mode:
SADR + MSDIS + SVEN
Read Status Register
SVACC = 1 ?
GACC = 1 ?
No
No
No
EOSACC = 1 ?
No
SVREAD = 0 ?
No
Enough space in the FIFO
to write all the data to send ?
Load Transmit register
FLEX_TWI_THR = Data to send
TXCOMP = 1 ?
No
END
RXRDY= 0 ?
All the data has been
written in FLEX_TWI_THR ?
No
TXRDY= 1 ?
No
Write in FLEX_TWI_THR
No
Read FLEX_TWI_FSR
and get the number of data
in the Receive FIFO
Read FLEX_TWI_RHR
All data have been read
in FLEX_TWI_RHR ?
No
GENERAL CALL TREATMENT
Decoding of the
programming sequence
Prog seq
OK ?
No
Change SADR
46.9.6.5 Clearing/Flushing FIFOs
Each FIFO can be cleared/flushed using FLEX_TWI_CR.TXFCLR/RXFCLR.
46.9.6.6 TXRDY and RXRDY Behavior
FLEX_TWI_SR.TXRDY/RXRDY flags display a specific behavior when FIFOs are enabled.
TXRDY indicates if a data can be written in the Transmit FIFO. Thus the TXRDY flag is set as long as the Transmit
FIFO can accept new data. See figure TXRDY Behavior when TXRDYM = 0 in Master mode.
RXRDY indicates if an unread data is present in the Receive FIFO. Thus the RXRDY flag is set as soon as one
unread data is in the Receive FIFO. Refer to figure RXRDY Behavior when RXRDYM = 0 in Master and Slave
modes.
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TXRDY and RXRDY behavior can be modified using the TXRDYM and RXRDYM fields in the TWI FIFO Mode
Register (FLEX_TWI_FMR) to reduce the number of accesses to FLEX_TWI_THR/RHR.
As an example, in Master mode, the Transmit FIFO can be loaded with multiple data in the same access by
configuring TXRDYM>0.
See TWI FIFO Mode Register for the FIFO configuration.
Figure 46-135. TXRDY Behavior when TXRDYM = 0 in Master Mode
TWD
S
DADR
W
A
DATA n
A
DATA n+1
A
DATA n+2
A
Write
FLEX_TWI_THR
Read
FLEX_TWI_SR
TXRDY
TXFFF
1
TXFL
0
1
2
1
FIFO size - 1
FIFO full
FIFO size - 1
TXCOMP
Figure 46-136. RXRDY Behavior when RXRDYM = 0 in Master and Slave Modes
TWD
S
DADR
R
A
DATA n
A
DATA n+1
A
DATA n+2
A
Read
FLEX_TWI_RHR
Read
FLEX_TWI_SR
RXRDY
RXFFF
RXFEF
0
RXFL
1
FIFO full
0
FIFO size - 1
TXCOMP
Figure 46-137. TXRDY Behavior when TXRDYM = 0 in Slave Mode
TWD
S
DADR
W
A
DATA n
A
DATA n+1
A
DATA n+2
A
Write
FLEX_TWI_THR
Read
FLEX_TWI_SR
SVACC
TXRDY
TXFFF
TXFL
1
0
1
2
1
FIFO size - 1
FIFO full
FIFO size - 1
TXCOMP
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1417
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
46.9.6.7 TWI Single Data Mode
In Single Data mode, only one data is written every time FLEX_TWI_THR is accessed, and only one data is read
every time FLEX_TWI_RHR is accessed.
When FLEX_TWI_FMR.TXRDYM = 0, the Transmit FIFO operates in Single Data mode.
When FLEX_TWI_FMR.RXRDYM = 0, the Receive FIFO operates in Single Data mode.
See sections TWI Transmit Holding Register and TWI Receive Holding Register.
46.9.6.8 TWI Multiple Data Mode
Multiple Data mode minimizes the number of accesses by concatenating the data to send/read in one access.
When FLEX_TWI_FMR.TXRDYM > 0, the Transmit FIFO operates in Multiple Data mode.
When FLEX_TWI_FMR.RXRDYM > 0, the Receive FIFO operates in Multiple Data mode.
In Multiple Data mode, it is possible to write/read up to four data in one FLEX_TWI_THR/FLEX_TWI_RHR register
access.
The number of data to write/read is defined by the size of the register access. If the access is a byte-size register
access, only one data is written/read. If the access is a halfword size register access, then up to two data are read
and only one data is written. Lastly, if the access is a wordsize register access, then up to four data are read and up
to two data are written.
Written/Read data are always right-aligned, as described in sections TWI Receive Holding Register (FIFO Enabled)
and TWI Transmit Holding Register (FIFO Enabled).
As an example, if the Transmit FIFO is empty and there are six data to send, either of the following write accesses
may be performed:
•
•
•
six FLEX_TWI_THR-byte write accesses
three FLEX_TWI_THR-halfword write accesses
one FLEX_TWI_THR-word write access and one FLEX_TWI_THR halfword write access
With a Receive FIFO containing six data, any of the following read accesses may be performed:
•
•
•
six FLEX_TWI_RHR-byte read accesses
three FLEX_TWI_RHR-halfword read accesses
one FLEX_TWI_RHR-word read access and one FLEX_TWI_RHR-halfword read access
46.9.6.8.1 TXRDY and RXRDY Configuration
In Multiple Data mode, it is possible to write one or more data in the same FLEX_TWI_THR/FLEX_TWI_RHR access.
The TXRDY flag indicates if one or more data can be written in the FIFO depending on the configuration of
FLEX_TWI_FMR.TXRDYM/RXRDYM.
As an example, if two data are written each time in FLEX_TWI_THR, it is useful to configure the TXRDYM field to the
value ‘1’ so that the TXRDY flag is at ‘1’ only when at least two data can be written in the Transmit FIFO.
In the same way, if four data are read each time in FLEX_TWI_RHR, it is useful to configure the RXRDYM field to the
value ‘2’ so that the RXRDY flag is at ‘1’ only when at least four unread data are in the Receive FIFO.
46.9.6.8.2 DMA
When FIFOs operate in Multiple Data mode, the DMA transfer type must be configured in byte, halfword or word
depending on the FLEX_TWI_FMR.TXRDYM/RXRDYM settings.
46.9.6.9 Transmit FIFO Lock
If a frame is terminated early due to a not-acknowledge error (NACK flag), SMBus timeout error (TOUT flag) or
master code acknowledge error (MACK flag), a lock is set on the Transmit FIFO preventing any new frame from
being sent until it is cleared. This allows clearing the FIFO if needed, resetting DMA channels, etc., without any risk.
FLEX_TWI_SR.LOCK is used to check the state of the Transmit FIFO lock.
The Transmit FIFO lock can be cleared by setting FLEX_TWI_CR.TXFLCLR to ‘1’.
46.9.6.10 FIFO Pointer Error
A FIFO overflow is reported in FLEX_TWI_FSR.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1418
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
If the Transmit FIFO is full and a write access is performed on FLEX_TWI_THR, it generates a Transmit FIFO pointer
error and sets FLEX_TWI_FSR.TXFPTEF.
In Multiple Data mode, if the number of data written in FLEX_TWI_THR (according to the register access size) is
greater than the free space in the Transmit FIFO, a Transmit FIFO pointer error is generated and
FLEX_TWI_FSR.TXFPTEF is set.
A FIFO underflow is reported in FLEX_TWI_FSR.
In Multiple Data mode, if the number of data read in FLEX_TWI_RHR (according to the register access size) is
greater than the number of unread data in the Receive FIFO, a Receive FIFO pointer error is generated and
FLEX_TWI_FSR.RXFPTEF is set.
No pointer error occurs if the FIFO state/level is checked before writing/reading in FLEX_TWI_THR/FLEX_TWI_RHR.
The FIFO state/level can be checked either with TXRDY, RXRDY, TXFL or RXFL. When a pointer error occurs, other
FIFO flags may not behave as expected; their states should be ignored.
If a Transmit or Receive pointer error occurs, a software reset must be performed using FLEX_TWI_CR.SWRST.
Note that issuing a software while transmitting might leave a slave in an unknown state holding the TWD line. In such
case, a Bus Clear Command will allow to make the slave release the TWD line (the first frame sent afterwards might
not be received properly by the slave).
46.9.6.11 FIFO Thresholds
Each Transmit and Receive FIFO includes a threshold feature used to set a flag and an interrupt when a FIFO
threshold is crossed. Thresholds are defined as a number of data in the FIFO, and the FIFO state (TXFL or RXFL)
represents the number of data currently in the FIFO.
The Transmit FIFO threshold can be set using the field FLEX_TWI_FMR.TXFTHRES. Each time the Transmit FIFO
level goes from ‘above threshold’ to ‘equal to or below threshold’, the flag FLEX_TWI_FESR.TXFTHF is set. The
application is warned that the Transmit FIFO has reached the defined threshold and that it can be reloaded.
The Receive FIFO threshold can be set using the field FLEX_TWI_FMR.RXFTHRES. Each time the Receive FIFO
level goes from ‘below threshold’ to ‘equal to or above threshold’, the flag FLEX_TWI_FESR.RXFTHF is set. The
application is warned that the Receive FIFO has reached the defined threshold and that it can be read to prevent an
underflow.
The TXFTHF and RXFTHF flags can be configured to generate an interrupt using FLEX_TWI_FIER and
FLEX_TWI_FIDR.
46.9.6.12 FIFO Flags
FIFOs come with a set of flags which can be configured to generate interrupts through FLEX_TWI_FIER and
FLEX_TWI_FIDR.
FIFO flags state can be read in FLEX_TWI_FSR. They are cleared when FLEX_TWI_FSR is read.
46.9.7
TWI Comparison Function on Received Character
The TWI has the capability to extend the address matching on up to three slave addresses. The
FLEX_TWI_SMR.SADR1EN/SADR2EN/SADR3EN bits enable address matching on additional addresses which can
be configured through the FLEX_TWI_SWMR.SADR1/SADR2/SADR3 fields. The DATAMEN bit has no effect.
The SVACC bit is set when there is a comparison match with the received slave address.
46.9.8
Sniffer Mode
The Slave Sniffer mode of a TWI can be enabled to ease the analysis/debug of a TWI bus activity. The TWI bus to be
analyzed can be mastered by one TWI master embedded in the product or mastered by an I2C master outside the
product.
In this mode, the TWI reports all (or part of) the TWI bus activity without impacting the TWI bus (no bus drive is
performed). Depending on the MASK field value, only some specific transfers can be logged instead of the whole
activity.
The peripheral TWIn+1 can be configured to analyze the peripheral TWIn (n being the instance index of the TWI) in a
full transparent mode via predefined internal connections between TWI instances.
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1419
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
The predefined internal connections provides the capability to use the TWD and TWCK pins for alternate functions
while the TWI peripheral is configured in Sniffer Slave mode and the selected TWI bus to analyze is carried on these
internal links.
The following fields must be programmed before entering Slave mode:
1.
2.
3.
4.
5.
6.
FLEX_TWI_SMR.SADR: Use the slave device address to indicate which frame(s) to log.
FLEX_TWI_SMR.MASK: Indicate which SADR bits should be masked and thus which transfers should be
logged (set to 0x7F to log the whole TWI bus activity; all SADR bits are masked in this case). General Call
accesses will always match.
FLEX_TWI_SMR.BSEL: Select the TWI bus to analyze (see Figure 46-138).
FLEX_TWI_SMR.SNIFF: Set to ‘1’ to enable Slave Sniffer mode.
FLEX_TWI_CR.MSDIS: Disable Master mode.
FLEX_TWI_CR.SVEN: Enable Slave mode.
As the device receives the clock, values written in FLEX_TWI_CWGR are not relevant.
Once configured in Slave Sniffer mode, the FLEX_TWI_SR.RXRDY bit indicates when a transfer has been logged in
FLEX_TWI_RHR. An interrupt can be generated if configured. The FLEX_TWI_SR.OVRE flag indicates if an overrun
error occurred if the application is not fast enough to read FLEX_TWI_RHR.
In Slave Sniffer mode, FLEX_TWI_RHR logs data as follows:
•
•
•
•
The RXDATA field reports the sniffed 8-bit data field.
The SSTATE field indicates if a START condition has been detected before the 8-bit data field.
The PSTATE field indicates if a STOP condition has been detected after the previously sniffed 8-bit data field.
The ASTATE field indicates which acknowledge condition has been detected after the previously sniffed 8-bit
data field.
Figure 46-138. Sniffer Mode Application Overview
CPU
System Bus Matrix
DMA
Peripheral Bridge
System Memory
TWIx
dma trigger events
(e.g. TWI0 full
frame dump via
DMA and TWI1)
dma trigger events
x,y= TWI instance index
Application
TWI Bus
Master
TWIy
Non-intrusive
TWI
Bus Analysis,
Debug
1
TWCKx
TWDx
BSEL
TWCKy
1
TWDy
Application
I2C
Slave
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1420
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
Figure 46-139. Slave Sniffer Mode Log
TWD
S
ADR+R/W
A/NA
DATA
A/NA
P
S
ADR+R/W
A/NA
DATA
RXRDY
46.9.9
Read RHR
Read RHR
Read RHR
ASTATE = 0
PSTATE = 0
SSTATE = 1
RXDATA = ADR +R/W
ASTATE = 1 or 2
PSTATE = 0
SSTATE = 0
RXDATA = DATA
ASTATE = 1 or 2
PSTATE = 1
SSTATE = 1
RXDATA = ADR + R/W
TWI Register Write Protection
The FLEXCOM operating mode (FLEX_MR.OPMODE) must be set to FLEX_MR_OPMODE_TWI to enable access
to the write protection registers.
To prevent any single software error from corrupting TWI behavior, certain registers in the address space can be
write-protected by setting the WPEN (Write Protection Enable), WPITEN (Write Protection Interrupt Enable), and/or
WPCREN (Write Protection Control Enable) bits in the TWI Write Protection Mode Register (FLEX_TWI_WPMR).
If a write access to a write-protected register is detected, the Write Protection Violation Status (WPVS) flag in the TWI
Write Protection Status Register (FLEX_TWI_WPSR) is set and the Write Protection Violation Source (WPVSRC)
field indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading FLEX_TWI_WPSR.
The following register(s) can be write-protected when WPEN is set:
•
•
•
•
TWI Slave Mode Register
TWI Clock Waveform Generator Register
TWI SMBus Timing Register
TWI FIFO Mode Register
The following register(s) can be write-protected when WPITEN is set:
•
•
TWI Interrupt Enable Register
TWI Interrupt Disable Register
The following register(s) can be write-protected when WPCREN is set:
•
TWI Control Register
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1421
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
46.10
Register Summary
Offset
Name
Bit Pos.
0x00
FLEX_MR
31:24
23:16
15:8
7:0
0x04
...
0x0F
6
5
4
3
2
1
0
OPMODE[1:0]
Reserved
0x10
FLEX_RHR
0x14
...
0x1F
Reserved
0x20
FLEX_THR
0x24
...
0x01FF
Reserved
0x0200
FLEX_US_CR
0x0204
FLEX_US_MR
0x0208
FLEX_US_IER
0x0208
FLEX_US_IER
(LIN_MODE)
0x0208
FLEX_US_IER
(LON_MODE)
0x020C
7
FLEX_US_IDR
0x020C
FLEX_US_IDR
(LIN_MODE)
0x020C
FLEX_US_IDR
(LON_MODE)
31:24
23:16
15:8
7:0
RXDATA[15:8]
RXDATA[7:0]
31:24
23:16
15:8
7:0
TXDATA[15:8]
TXDATA[7:0]
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
FIFODIS
FIFOEN
RETTO
RSTNACK
TXDIS
TXEN
ONEBIT
MODSYNC
INVDATA
VAR_SYNC
CHMODE[1:0]
CHRL[1:0]
REQCLR
LINWKUP
LINABT
RSTIT
SENDA
RXDIS
RXEN
MAN
FILTER
DSNACK
INACK
NBSTOP[1:0]
USCLKS[1:0]
RTSDIS
STTTO
RSTTX
CMP
OVER
TXFLCLR
RXFCLR
TXFCLR
RTSEN
STPBRK
STTBRK
RSTSTA
RSTRX
MAX_ITERATION[2:0]
CLKO
MODE9
MSBF
PAR[2:0]
SYNC
USART_MODE[3:0]
MANE
CTSIC
PARE
LINHTE
FRAME
LINSTE
NACK
OVRE
LINSNRE
LINTC
PARE
LINID
FRAME
LINBK
OVRE
LINCE
LBLOVFE
LINIPE
LRXD
ITER
RXBRK
LINISFE
TXEMPTY
TXRDY
LINBE
TIMEOUT
RXRDY
LFET
TXEMPTY
TXRDY
LCOL
TIMEOUT
RXRDY
LTXD
UNRE
LCRCE
LSFE
OVRE
CMP
PARE
LINHTE
FRAME
LINSTE
LINTC
PARE
LINID
FRAME
LINBK
OVRE
LINCE
LBLOVFE
LINIPE
LRXD
ITER
RXBRK
LINISFE
TXEMPTY
TXRDY
LINBE
TIMEOUT
RXRDY
LFET
TXEMPTY
TXRDY
LCOL
TIMEOUT
RXRDY
LTXD
TXEMPTY
TXRDY
RXRDY
UNRE
© 2020 Microchip Technology Inc.
LSFE
RXRDY
MANE
CTSIC
NACK
OVRE
LINSNRE
LCRCE
TXEMPTY
TXRDY
OVRE
Complete Datasheet
DS60001579C-page 1422
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
...........continued
Offset
Name
0x0210
FLEX_US_IMR
0x0210
FLEX_US_IMR
(LIN_MODE)
0x0210
FLEX_US_IMR
(LON_MODE)
0x0214
FLEX_US_CSR
0x0214
FLEX_US_CSR
(LIN_MODE)
0x0214
FLEX_US_CSR
(LON_MODE)
0x0218
FLEX_US_RHR
0x0218
FLEX_US_RHR
(FIFO_MULTI_DATA
)
0x021C
FLEX_US_THR
FLEX_US_THR
0x021C (FIFO_MULTI_DATA
)
0x0220
FLEX_US_BRGR
0x0224
FLEX_US_RTOR
0x0228
FLEX_US_TTGR
0x0228
FLEX_US_TTGR
(LON_MODE)
0x022C
...
0x023F
Reserved
Bit Pos.
7
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
6
5
4
3
2
1
0
MANE
CMP
CTSIC
PARE
LINHTE
FRAME
LINSTE
NACK
OVRE
LINSNRE
LINTC
PARE
LINID
FRAME
LINBK
OVRE
LINCE
LINIPE
LBLOVFE
LRXD
ITER
RXBRK
LINISFE
TXEMPTY
TXRDY
LINBE
TIMEOUT
RXRDY
LFET
TXEMPTY
TXRDY
LCOL
TIMEOUT
RXRDY
LTXD
UNRE
LCRCE
LSFE
CTS
CMP
PARE
LINHTE
LINBLS
LINTC
PARE
OVRE
FRAME
LINSTE
LINID
FRAME
LINBK
OVRE
LINCE
LINIPE
LRXD
ITER
RXBRK
LINISFE
TXEMPTY
TXRDY
LINBE
TIMEOUT
RXRDY
LFET
TXEMPTY
TXRDY
LCOL
TIMEOUT
RXRDY
LTXD
TXEMPTY
TXRDY
RXRDY
UNRE
LSFE
RXRDY
MANE
CTSIC
NACK
OVRE
LINSNRE
LBLOVFE
LCRCE
TXEMPTY
TXRDY
OVRE
RXSYNH
RXCHR[8]
RXCHR[7:0]
RXCHR3[7:0]
RXCHR2[7:0]
RXCHR1[7:0]
RXCHR0[7:0]
TXSYNH
© 2020 Microchip Technology Inc.
TXCHR[8]
TXCHR[7:0]
TXCHR3[7:0]
TXCHR2[7:0]
TXCHR1[7:0]
TXCHR0[7:0]
FP[2:0]
CD[15:8]
CD[7:0]
TO[16]
TO[15:8]
TO[7:0]
TG[7:0]
PCYCLE[23:16]
PCYCLE[15:8]
PCYCLE[7:0]
Complete Datasheet
DS60001579C-page 1423
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
...........continued
Offset
Name
0x0240
FLEX_US_FIDI
0x0240
FLEX_US_FIDI
(LON_MODE)
0x0244
FLEX_US_NER
0x0248
...
0x024B
0x024C
0x0250
0x0254
0x0258
FLEX_US_IF
FLEX_US_MAN
FLEX_US_LINMR
FLEX_US_LINIR
FLEX_US_LINBRR
0x0260
FLEX_US_LONMR
0x0268
0x026C
0x0270
0x0274
7
6
5
4
3
2
1
0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
FI_DI_RATIO[15:8]
FI_DI_RATIO[7:0]
BETA2[23:16]
BETA2[15:8]
BETA2[7:0]
NB_ERRORS[7:0]
Reserved
0x025C
0x0264
Bit Pos.
FLEX_US_LONPR
FLEX_US_LONDL
FLEX_US_LONL2H
DR
FLEX_US_LONBL
FLEX_US_LONB1T
X
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
RXIDLEV
DRIFT
ONE
IRDA_FILTER[7:0]
RX_MPOL
RX_PP[1:0]
RX_PL[3:0]
TX_MPOL
TX_PP[1:0]
TX_PL[3:0]
SYNCDIS
WKUPTYP
FSDIS
DLM
DLC[7:0]
CHKTYP
CHKDIS
PARDIS
PDCM
NACT[1:0]
IDCHR[7:0]
LINFP[2:0]
LINCD[15:8]
LINCD[7:0]
EOFS[7:0]
LCDS
DMAM
CDTAIL
TCOL
COLDET
COMMT
LONPL[13:8]
LONPL[7:0]
LONDL[7:0]
PB
© 2020 Microchip Technology Inc.
ALTP
BLI[5:0]
LONBL[5:0]
BETA1TX[23:16]
BETA1TX[15:8]
BETA1TX[7:0]
Complete Datasheet
DS60001579C-page 1424
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
...........continued
Offset
Name
0x0278
FLEX_US_LONB1R
X
0x027C
FLEX_US_LONPRI
O
0x0280
FLEX_US_IDTTX
0x0284
FLEX_US_IDTRX
0x0288
FLEX_US_ICDIFF
0x028C
...
0x028F
0x0290
0x0294
...
0x029F
0x02A0
0x02A4
0x02A8
0x02AC
0x02B0
0x02B4
0x02B8
...
0x02E3
Bit Pos.
7
6
5
31:24
23:16
4
3
2
1
0
BETA1RX[23:16]
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
BETA1RX[15:8]
BETA1RX[7:0]
NPS[6:0]
PSNB[6:0]
IDTTX[23:16]
IDTTX[15:8]
IDTTX[7:0]
IDTRX[23:16]
IDTRX[15:8]
IDTRX[7:0]
ICDIFF[3:0]
Reserved
FLEX_US_CMPR
31:24
23:16
15:8
7:0
VAL2[8]
VAL2[7:0]
CMPPAR
CMPMODE[1:0]
VAL1[8]
VAL1[7:0]
Reserved
FLEX_US_FMR
FLEX_US_FLR
FLEX_US_FIER
FLEX_US_FIDR
FLEX_US_FIMR
FLEX_US_FESR
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
RXFTHRES2[5:0]
RXFTHRES[5:0]
TXFTHRES[5:0]
FRTSC
RXRDYM[1:0]
TXRDYM[1:0]
RXFL[5:0]
TXFL[5:0]
RXFPTEF
TXFPTEF
RXFTHF
RXFFF
RXFEF
TXFTHF
RXFTHF2
TXFFF
TXFEF
RXFPTEF
TXFPTEF
RXFTHF
RXFFF
RXFEF
TXFTHF
RXFTHF2
TXFFF
TXFEF
RXFPTEF
TXFPTEF
RXFTHF
RXFFF
RXFEF
TXFTHF
RXFTHF2
TXFFF
TXFEF
RXFPTEF
TXFPTEF
RXFTHF
RXFFF
RXFEF
TXFTHF
RXFTHF2
TXFFF
TXFLOCK
TXFEF
Reserved
© 2020 Microchip Technology Inc.
Complete Datasheet
DS60001579C-page 1425
SAM9X60
Flexible Serial Communication Controller (FLEXCOM)
...........continued
Offset
Name
0x02E4
FLEX_US_WPMR
0x02E8
0x02EC
...
0x03FF
0x0400
0x0404
FLEX_US_WPSR
FLEX_SPI_CR
FLEX_SPI_MR
FLEX_SPI_RDR
0x0408
FLEX_SPI_RDR
(FIFO_MULTI_DATA
_8)
0x0408
FLEX_SPI_RDR
(FIFO_MULTI_DATA
_16)
FLEX_SPI_TDR
FLEX_SPI_TDR
0x040C (FIFO_MULTI_DATA
)
0x0410
0x0414
0x0418
7
6
5
4
3
31:24
23:16
WPKEY[23:16]
WPKEY[15:8]
15:8
7:0
31:24
23:16
15:8
7:0
WPKEY[7:0]
2
1
0
WPCREN
WPITEN
WPEN
WPVSRC[15:8]
WPVSRC[7:0]
WPVS
Reserved
0x0408
0x040C
Bit Pos.
FLEX_SPI_SR
FLEX_SPI_IER
FLEX_SPI_IDR
0x041C
FLEX_SPI_IMR
0x0420
...
0x042F
Reserved
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
31:24
23:16
15:8
7:0
FIFODIS
FIFOEN
RXFCLR
LASTXFER
TXFCLR
SPIDIS
SPIEN
REQCLR
SWRST
DLYBCS[7:0]
PCS[3:0]
LLB
WDRBT
CMPMODE
MODFDIS
BRSRCCLK
PCSDEC
PS
MSTR
PCS[3:0]
RD[15:8]
RD[7:0]
RD3[7:0]
RD2[7:0]
RD1[7:0]
RD0[7:0]
RD1[15:8]
RD1[7:0]
RD0[15:8]
RD0[7:0]
LASTXFER
PCS[3:0]
RXFPTEF
TXFPTEF
RXFTHF
TD[15:8]
TD[7:0]
TD1[15:8]
TD1[7:0]
TD0[15:8]
TD0[7:0]
RXFFF
RXFEF
TXFTHF
TXFFF
RXFFF
CMP
OVRES
RXFEF
UNDES
MODF
TXFTHF
TXEMPTY
TDRE
TXFFF
TXFEF
SPIENS
NSSR
RDRF
TXFEF
RXFFF
CMP
OVRES
RXFEF
UNDES
MODF
TXFTHF
TXEMPTY
TDRE
TXFFF
NSSR
RDRF
TXFEF
RXFFF
CMP
OVRES
RXFEF
UNDES
MODF
TXFTHF
TXEMPTY
TDRE
TXFFF
NSSR
RDRF
TXFEF
CMP
OVRES
UNDES
MODF
TXEMPTY
TDRE
NSSR
RDRF
SFERR
RXFPTEF
RXFPTEF
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