AD5116

Single-Channel, 128-/64-/32-Position, I2C, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer Data Sheet FEATURES Single-channel, 128-/64-/32-position resolution 5 kΩ, 10 kΩ, 80 kΩ nominal resistance Maximum ±8% nominal resistor tolerance error Low wiper resistance ±6 mA maximum wiper current density Resistor tolerance stored in EEPROM (0.1% accuracy) Rheostat mode temperature coefficient: 35 ppm/°C Potentiometer mode temperature coefficient: 5 ppm/°C 2.3 V to 5.5 V single-supply operation 1.8 V to 5.5 V logic supply operation Power-on EEPROM refresh time < 50 μs I2C-compatible interface Wiper setting and EEPROM readback 50-year typical data retention at 125°C 1 million write cycles Wide operating temperature: −40°C to +125°C Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package AD5110/AD5112/AD5114 FUNCTIONAL BLOCK DIAGRAM VLOGIC VDD AD5110/AD5112/AD5114 POWER-ON RESET A W DATA SDA SCL EEPROM I2C SERIAL INTERFACE B DATA RDAC REGISTER 09582-001 GND Figure 1. APPLICATIONS Mechanical potentiometer replacement Portable electronics level adjustment Audio volume control Low resolution DAC LCD panel brightness and contrast control Programmable voltage to current conversion Programmable filters, delays, time constants Feedback resistor programmable power supply Sensor calibration GENERAL DESCRIPTION The AD5110/AD5112/AD5114 provide a nonvolatile solution for 128-/64-/32-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance, low nominal temperature coefficient and high bandwidth simplify open-loop applications, as well as tolerance matching applications. The new low wiper resistance feature minimizes the wiper resistance in the extremes of the resistor array to only 45 Ω, typical. The wiper settings are controllable through an I2C-compatible digital interface that is also used to readback the wiper register and EEPROM content. Resistor tolerance is stored within EEPROM, providing an end-to-end tolerance accuracy of 0.1%. The AD5110/AD5112/AD5114 are available in a 2 mm × 2 mm LFCSP package. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. ±8% Resistance Tolerance Family Model AD5110 AD5111 AD5112 AD5113 AD5116 AD5114 AD5115 Resistance (kΩ) 10, 80 10, 80 5, 10, 80 5, 10, 80 5, 10, 80 10, 80 10, 80 Position 128 128 64 64 64 32 32 Interface I2C Up/down I2C Up/down Push-button I2C Up/down Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD5110/AD5112/AD5114 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics—AD5110 .......................................... 3 Electrical Characteristics—AD5112 .......................................... 5 Electrical Characteristics—AD5114 .......................................... 7 Interface Timing Specifications .................................................. 9 Shift Register and Timing Diagram ......................................... 10 Absolute Maximum Ratings .......................................................... 11 Thermal Resistance .................................................................... 11 ESD Caution ................................................................................ 11 Pin Configuration and Function Descriptions ........................... 12 Typical Performance Characteristics ........................................... 13 Test Circuits ..................................................................................... 18 Data Sheet Theory of Operation ...................................................................... 19 RDAC Register and EEPROM .................................................. 19 I2C Serial Data Interface ............................................................ 19 Input Shift Register .................................................................... 20 Write Operation.......................................................................... 21 EEPROM Write Acknowlegde Polling .................................... 23 Read Operation........................................................................... 23 Reset ............................................................................................. 23 Shutdown Mode ......................................................................... 23 RDAC Architecture .................................................................... 24 Programming the Variable Resistor ......................................... 24 Programming the Potentiometer Divider ............................... 25 Terminal Voltage Operating Range ......................................... 26 Power-Up Sequence ................................................................... 26 Layout and Power Supply Biasing ............................................ 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27 REVISION HISTORY 10/11—Revision 0: Initial Version Rev. 0 | Page 2 of 28 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5110 AD5110/AD5112/AD5114 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity2 Symbol N R-INL Test Conditions/Comments Min 7 −2.5 −1 −0.5 −1 −8 Typ1 Max Unit Bits LSB LSB LSB LSB % ppm/°C Ω Ω Ω RAB = 10 kΩ, VDD = 2.3 V to 2.7 V RAB = 10 kΩ, VDD = 2.7 V to 5.5 V RAB = 80 kΩ Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW RBS RTS ±0.5 ±0.25 ±0.1 ±0.25 35 70 45 70 +2.5 +1 +0.5 +1 +8 140 80 140 Code = full scale Code = zero scale Code = bottom scale Code = top scale DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 Terminal Voltage Range5 Capacitance A, Capacitance B3 INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 80 kΩ RAB = 10 kΩ RAB = 80 kΩ Code = half scale RAB = 10 kΩ RAB = 80 kΩ −0.5 −0.5 −2.5 −1.5 ±0.15 ±0.15 +0.5 +0.5 1.5 0.5 ±10 −6 −1.5 GND 20 +6 +1.5 VDD LSB LSB LSB LSB LSB LSB ppm/°C mA mA V pF CA, CB Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUT (SDA) Output Low Voltage3 Three-State Leakage Current Three-State Output Capacitance3 CW f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V f = 1 MHz, measured to GND, code = half scale, VA = VB = 2.5 V VA = VW = VB 35 −500 ±15 +500 pF nA VINH VINL VHYST IN CIN VOL VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC 0.2 × VLOGIC 0.3 × VLOGIC 0.1 × VLOGIC ±1 5 V V V V V μA pF V V μA pF ISINK = 3 mA ISINK = 6 mA −1 2 0.2 0.4 +1 Rev. 0 | Page 3 of 28 AD5110/AD5112/AD5114 Parameter POWER SUPPLIES Single-Supply Power Range Logic Supply Range Positive Supply Current EEMEM Store Current3, 6 EEMEM Read Current3, 7 Logic Supply Current Power Dissipation8 Power Supply Rejection3 Symbol Test Conditions/Comments Min 2.3 1.8 IDD IDD_NVM_STORE IDD_NVM_READ ILOGIC PDISS PSR VDD = 5 V 750 2 320 30 5 −50 −64 Typ1 Data Sheet Max 5.5 VDD Unit V V nA mA μA nA μW dB dB VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = 5 V ± 10% RAB = 10 kΩ RAB = 80 kΩ Code = half scale, −3 dB RAB = 10 kΩ RAB = 80 kΩ VA = VDD/2 +1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 10 kΩ RAB = 80 kΩ VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 10 kΩ RAB = 80 kΩ Code = half scale, TA = 25°C, f = 100 kHz RAB = 10 kΩ RAB = 80 kΩ TA = 25°C 100 DYNAMIC CHARACTERISTICS3, 9 Bandwidth BW 2 200 MHz kHz Total Harmonic Distortion THD −80 −85 dB dB VW Settling Time ts 3 12 μs μs Resistor Noise Density eN_WB 9 20 1 50 nV/√Hz nV/√Hz MCycles kCycles Years FLASH/EE MEMORY RELIABILITY3 Endurance10 Data Retention11 1 2 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Different from operating current; supply current for NVM program lasts approximately 30 ms. 7 Different from operating current; supply current for NVM read lasts approximately 20 μs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. Rev. 0 | Page 4 of 28 Data Sheet ELECTRICAL CHARACTERISTICS—AD5112 AD5110/AD5112/AD5114 5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity2 Symbol N R-INL Test Conditions/Comments Min 6 −2.5 −1 −1 −0.25 +1 −8 Typ1 Max Unit Bits LSB LSB LSB LSB LSB % ppm/°C Ω Ω Ω RAB = 5 kΩ, VDD = 2.3 V to 2.7 V RAB = 5 kΩ, VDD = 2.7 V to 5.5 V RAB = 10 kΩ RAB = 80 kΩ Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW RBS RTS ±0.5 ±0.25 ±0.25 ±0.1 ±0.25 35 70 45 70 +2.5 +1 +1 +0.25 +1 +8 140 80 140 Code = full scale Code = zero scale Code = bottom scale Code = top scale DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 Differential Nonlinearity4 Full-Scale Error INL DNL VWFSE Zero-Scale Error VWZSE Voltage Divider Temperature Coefficient3 RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 Terminal Voltage Range5 Capacitance A, Capacitance B3 (ΔVW/VW)/ΔT × 106 RAB = 5 kΩ RAB =10 kΩ RAB = 80 kΩ RAB = 5 kΩ RAB =10 kΩ RAB = 80 kΩ Code = half scale RAB = 5 kΩ, 10 kΩ RAB = 80 kΩ −0.5 −0.5 −2.5 −1.5 −1 ±0.15 ±0.15 +0.5 +0.5 1.5 1 0.25 ±10 −6 −1.5 GND 20 +6 +1.5 VDD LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C mA mA V pF CA, CB Capacitance W3 CW Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUT (SDA) Output Low Voltage3 Three-State Leakage Current Three-State Output Capacitance3 f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V f = 1 MHz, measured to GND, code = half scale, VA = VB = 2.5 V VA = VW = VB 35 pF −500 ±15 +500 nA VINH VINL VHYST IN CIN VOL VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC 0.2 × VLOGIC 0.3 × VLOGIC 0.1 × VLOGIC ±1 5 V V V V V μA pF V V μA pF ISINK = 3 mA ISINK = 6 mA −1 2 0.2 0.4 +1 Rev. 0 | Page 5 of 28 AD5110/AD5112/AD5114 Parameter POWER SUPPLIES Single-Supply Power Range Logic Supply Range Positive Supply Current EEMEM Store Current3, 6 EEMEM Read Current3, 7 Logic Supply Current Power Dissipation8 Power Supply Rejection3 Symbol Test Conditions/Comments Min 2.3 1.8 IDD IDD_NVM_STORE IDD_NVM_READ ILOGIC PDISS PSR VDD = 5 V 750 2 320 30 5 −43 −50 −64 Typ1 Max 5.5 VDD Data Sheet Unit V V nA mA μA nA μW dB dB dB VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = 5 V ± 10% RAB = 5 kΩ RAB =10 kΩ RAB = 80 kΩ Code = half scale − 3 dB RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ Code = half scale, TA = 25°C, f = 100 kHz RAB = 5 kΩ RAB = 10 kΩ RAB = 80 kΩ TA = 25°C 100 DYNAMIC CHARACTERISTICS3, 9 Bandwidth BW 4 2 200 MHz MHz kHz Total Harmonic Distortion THD −75 −80 −85 VW Settling Time ts dB dB dB μs μs μs μs 2.5 3 10 Resistor Noise Density eN_WB 7 9 20 1 50 nV/√Hz nV/√Hz nV/√Hz MCycles kCycles Years FLASH/EE MEMORY RELIABILITY3 Endurance10 Data Retention11 1 2 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Different from operating current; supply current for NVM program lasts approximately 30 ms. 7 Different from operating current; supply current for NVM read lasts approximately 20 μs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. Rev. 0 | Page 6 of 28 Data Sheet ELECTRICAL CHARACTERISTICS—AD5114 AD5110/AD5112/AD5114 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 4. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance Symbol N R-INL R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW RBS RTS Test Conditions/Comments Min 5 −0.5 −0.25 −8 Code = full scale Code = zero scale Code = bottom scale Code = top scale 35 70 45 70 Typ1 Max Unit Bits LSB LSB % ppm/°C Ω Ω Ω +0.5 +0.25 +8 140 80 140 DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Integral Nonlinearity4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 RESISTOR TERMINALS Maximum Continuous IA, IB, and IW Current3 Terminal Voltage Range5 Capacitance A, Capacitance B3 INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 80 kΩ RAB = 10 kΩ RAB = 80 kΩ Code = half scale RAB = 10 kΩ RAB = 80 kΩ −0.25 −0.25 −1 −0.5 +0.25 +0.25 1 0.25 ±10 −6 −1.5 GND 20 +6 +1.5 VDD LSB LSB LSB LSB LSB LSB ppm/°C mA mA V pF CA, CB Capacitance W3 CW Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUT (SDA) Output Low Voltage3 Three-State Leakage Current Three-State Output Capacitance3 f = 1 MHz, measured to GND, code = half scale, VW = VA = 2.5 V or VW = VB = 2.5 V f = 1 MHz, measured to GND, code = half scale, VA = VB = 2.5 V VA = VW = VB 35 pF −500 ±15 +500 nA VINH VINL VHYST IN CIN VOL VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC 0.2 × VLOGIC 0.3 × VLOGIC 0.1 × VLOGIC ±1 5 V V V V V μA pF V V μA pF ISINK = 3 mA ISINK = 6 mA −1 2 0.2 0.4 +1 Rev. 0 | Page 7 of 28 AD5110/AD5112/AD5114 Parameter POWER SUPPLIES Single-Supply Power Range Logic Supply Range Positive Supply Current EEMEM Store Current3, 6 EEMEM Read Current3,7 Logic Supply Current Power Dissipation8 Power Supply Rejection3 Symbol Test Conditions/Comments Min 2.3 1.8 IDD IDD_NVM_STORE IDD_NVM_READ ILOGIC PDISS PSR VDD = 5 V 750 2 320 30 5 −50 −64 Typ1 Max 5.5 VDD Data Sheet Unit V V nA mA μA nA μW dB dB VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = 5 V ± 10% RAB = 10 kΩ RAB = 80 kΩ Code = half scale, −3 dB RAB = 10 kΩ RAB = 80 kΩ VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 10 kΩ RAB = 80 kΩ VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 10 kΩ RAB = 80 kΩ Code = half scale, TA = 25°C, f = 100 kHz RAB = 10 kΩ RAB = 80 kΩ TA = 25°C 100 DYNAMIC CHARACTERISTICS3, 9 Bandwidth BW 2 200 MHz kHz Total Harmonic Distortion THD −80 −85 dB dB VW Settling Time ts 2.7 9.5 μs μs Resistor Noise Density eN_WB 9 20 1 50 nV/√Hz nV/√Hz MCycles kCycles Years FLASH/EE MEMORY RELIABILITY3 Endurance10 Data Retention11 1 2 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Different from operating current; supply current for NVM program lasts approximately 30 ms. 7 Different from operating current; supply current for NVM read lasts approximately 20 μs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. Rev. 0 | Page 8 of 28 Data Sheet INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter 1 fSCL 2 t1 t2 t3 t4 t5 t6 t7 Test Conditions/ Comments Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Fast mode Min Typ Max 100 400 Unit kHz kHz µs µs µs µs ns ns µs µs µs µs µs µs µs µs µs µs ns ns ns ns ns ns ns ns ns ns ns ms µs µs AD5110/AD5112/AD5114 Description Serial clock frequency tHIGH, SCL high time tLOW, SCL low time tSU;DAT, data setup time tHD;DAT, data hold time tSU;STA, setup time for a repeated start condition tHD;STA, hold time (repeated) start condition tBUF, bus free time between a stop and a start condition tSU;STO, setup time for stop condition tRDA, rise time of SDA signal tFDA, fall time of SDA signal tRCL, rise time of SCL signal tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit. tFCL, fall time of SCL signal Pulse width of suppressed spike Memory program time Power-on EEPROM restore time Reset EEPROM restore time 4.0 0.6 4.7 1.3 250 100 0 0 4.7 0.6 4 0.6 4.7 1.3 4 0.6 20 + 0.1 CL 20 + 0.1 CL 20 + 0.1 CL 20 + 0.1 CL 20 + 0.1 CL 0 15 3.45 0.9 t8 t9 t10 t11 t11A t12 tSP 3 tEEPROM_PROGRAM 4 tPOWER_UP 5 tRESET 1 2 1000 300 300 300 1000 300 1000 300 300 300 50 50 50 25 Maximum bus capacitance is limited to 400 pF. The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode. 4 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles. 5 Maximum time after VDD is equal to 2.3 V. Rev. 0 | Page 9 of 28 AD5110/AD5112/AD5114 SHIFT REGISTER AND TIMING DIAGRAM DB7 (MSB) C1 C0 D7 D6 D5 D4 D3 DB0 (LSB) D0 Data Sheet 0 0 0 0 0 C2 D2 D1 DATA BITS CONTROL BITS Figure 2. Input Register Content t11 t2 SCL t12 t6 t6 t4 SDA P t1 t3 t5 t10 t8 t9 09582-003 t7 S S P Figure 3. 2-Wire Serial Interface Timing Diagram Rev. 0 | Page 10 of 28 09582-002 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to GND VLOGIC to GND VA, VW, VB to GND IA, IW, IB Pulsed 1 Frequency > 10 kHz RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Frequency ≤ 10 kHz RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Continuous RAW = 5 kΩ and 10 kΩ RAW = 80 kΩ Digital Inputs SDA and SCL Operating Temperature Range 3 Maximum Junction Temperature (TJ Max) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation 1 AD5110/AD5112/AD5114 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating –0.3 V to +7.0 V –0.3 V to +7.0 V GND − 0.3 V to VDD + 0.3 V THERMAL RESISTANCE ±6 mA/d 2 ±1.5 mA/d2 ±6 mA/√d2 ±1.5 mA/√d2 ±6 mA ±1.5 mA −0.3 V to +7 V or VLOGIC + 0.3 V (whichever is less) −40°C to +125°C 150°C −65°C to +150°C 260°C 20 sec to 40 sec (TJ max − TA)/θJA θJA is defined by JEDEC specification JESD-51, and the value is dependent on the test board and test environment. Table 7. Thermal Resistance Package Type 8-Lead LFCSP 1 θJA 901 θJC 25 Unit °C/W JEDEC 2S2P test board, still air (0 m/sec air flow). ESD CAUTION Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of EEPROM memory. Rev. 0 | Page 11 of 28 AD5110/AD5112/AD5114 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 A2 W3 B4 Data Sheet AD5110/ AD5112/ AD5114 TOP VIEW (Not to Scale) 8 VLOGIC 7 SDA 6 SCL 5 GND 09582-004 NOTES 1. THE EXPOSED PAD IS INTERNALLY FLOATING. Figure 4. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD A W B GND SCL SDA VLOGIC EPAD Description Positive Power Supply; 2.3 V to 5.5 V. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC. GND ≤ VA ≤ VDD. Wiper Terminal of RDAC. GND ≤ VW ≤ VDD. Terminal B of RDAC. GND ≤ VB ≤ VDD. Ground Pin, Logic Ground Reference. Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers. Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. Logic Power Supply; 1.8 V to VDD. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. Exposed Pad. The exposed pad is internally floating. Rev. 0 | Page 12 of 28 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, –40°C +25°C +125°C –40°C +25°C +125°C 0.02 0.01 0 –0.01 AD5110/AD5112/AD5114 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C R-DNL (LSB) R-INL (LSB) –0.02 –0.03 –0.04 –0.05 –0.06 80kΩ, –40°C –0.07 80kΩ, +25°C 80kΩ, +125°C 09582-008 09582-010 0 7 70 77 84 91 98 112 105 119 14 21 28 35 42 49 56 63 127 0 7 14 21 28 35 42 49 56 63 70 77 84 91 98 112 105 119 09582-005 CODE (Decimal) CODE (Decimal) Figure 5. R-INL vs. Code (AD5110) 0.08 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C Figure 8. R-DNL vs. Code (AD5110) 0.02 0.01 0 –0.01 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 0.06 0.04 0.02 R-DNL (LSB) R-INL (LSB) –0.02 –0.03 –0.04 0 –0.02 –0.05 –0.04 –0.06 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) –0.06 09582-006 –0.07 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) Figure 6. R-INL vs. Code (AD5112) 0.020 0.015 0.010 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, –40°C +25°C +125°C –40°C +25°C +125°C R-DNL (LSB) 0.004 0.002 0 –0.002 –0.004 –0.006 –0.008 –0.010 –0.012 –0.014 Figure 9. R-DNL vs. Code (AD5112) R-INL (LSB) 0.005 0 –0.005 –0.010 –0.016 09582-007 –0.015 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 CODE (Decimal) –0.018 0 2 4 10kΩ, –40°C 80kΩ, –40°C 6 8 10kΩ, +25°C 80kΩ, +25°C 10kΩ, +125°C 80kΩ, +125°C 10 12 14 16 18 20 22 24 26 28 31 CODE (Decimal) Figure 7. R-INL vs. Code (AD5114) Figure 10. R-DNL vs. Code (AD5114) Rev. 0 | Page 13 of 28 09582-009 10kΩ, –40°C 80kΩ, –40°C 10kΩ, +25°C 80kΩ, +25°C 10kΩ, +125°C 80kΩ, +125°C 127 AD5110/AD5112/AD5114 0.08 0.06 0.04 0.02 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, –40°C +25°C +125°C –40°C +25°C +125°C Data Sheet 0.02 0.01 0 –0.01 INL (LSB) DNL (LSB) –0.02 –0.03 –0.04 0 –0.02 –0.04 –0.06 –0.08 –0.05 –0.06 –0.07 10kΩ, –40°C 80kΩ, –40°C 10kΩ, +25°C 80kΩ, +25°C 10kΩ, +125°C 80kΩ, +125°C 09582-011 CODE (Decimal) CODE (Decimal) Figure 11. INL vs. Code (AD5110) 0.08 0.06 0.04 0.02 INL (LSB) Figure 14. DNL vs. Code (AD5110) 0.02 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C 0.01 0 –0.01 DNL (LSB) 5kΩ, –40°C 10kΩ, –40°C 5kΩ, +25°C 10kΩ, +25°C 5kΩ, +125°C 10kΩ, +125°C 0 –0.02 –0.04 –0.06 09582-012 –0.02 –0.03 –0.04 –0.05 09582-015 –0.08 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) –0.06 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 CODE (Decimal) Figure 12. INL vs. Code (AD5112) 0.015 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, –40°C +25°C +125°C –40°C +25°C +125°C Figure 15. DNL vs. Code (AD5112) 0.004 0.002 0 –0.002 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 0.010 0.005 0 DNL (LSB) INL (LSB) –0.004 –0.006 –0.008 –0.010 –0.012 –0.005 –0.010 –0.015 –0.014 09582-013 80kΩ, –40°C 0 2 4 6 8 80kΩ, +25°C 80kΩ, +125°C 24 26 28 31 09582-016 –0.020 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 CODE (Decimal) –0.016 10 12 14 16 18 20 22 CODE (Decimal) Figure 13. INL vs. Code (AD5114) Figure 16. DNL vs. Code (AD5114) Rev. 0 | Page 14 of 28 09582-014 0 7 70 77 84 91 98 112 105 119 14 21 28 35 42 49 56 63 127 0 7 70 77 84 91 98 112 105 119 14 21 28 35 42 49 56 63 127 Data Sheet 800 700 600 SUPPLY CURRENT (nA) AD5110/AD5112/AD5114 0.12 0.10 SUPPLY CURRENT, ILOGIC (mA) 0.08 0.06 0.04 0.02 0 –0.02 0 0.5 1.0 1.5 2.0 2.5 3.0 500 400 300 200 100 0 09582-017 VLOGIC = 5.0V VLOGIC = 3.3V VLOGIC = 2.3V VLOGIC = 1.8V 2.3V AVERAGE OF I DD 2.3V AVERAGE OF I LOGIC 3.3V AVERAGE OF I DD 3.3V AVERAGE OF I LOGIC 5.0V AVERAGE OF I DD 5.0V AVERAGE OF I LOGIC –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 3.5 4.0 4.5 5.0 DIGITAL INPUT VOLTAGE (V) Figure 17. Supply Current vs. Temperature 200 POTENTIOMETER MODE TEMPCO (ppm/°C) 200 Figure 20. Supply Current (ILOGIC) vs. Digital Input Voltage 180 160 140 120 100 80 60 40 20 0 10kΩ 80kΩ 5kΩ POTENTIOMETER MODE TEMPCO (ppm/°C) VDD = 5V VDD = 5V 180 160 140 120 100 80 60 40 20 0 10kΩ 80kΩ 5kΩ Figure 18. Potentiometer Mode Tempco ((ΔVW/VW)/ΔT × 106) vs. Code 0 0x20 09582-018 Figure 21. Rheostat Mode Tempco ((ΔRWB/RWB)/ΔT × 106) vs. Code 0 0x40 (0x20) [0x10] –10 0x10 0x08 –10 0x20 (0x10) [0x08] 0x10 (0x08) [0x04] –20 GAIN (dB) –20 GAIN (dB) 0x08 (0x04) [0x02] 0x04 (0x02) [0x01] 0x04 0x02 –30 –40 –30 0x01 0x02 (0x01) [0x00] 0x01 (0x00) 0x00 –40 0x00 –50 –60 AD5110 (AD5112) [AD5114] –70 10k 100k FREQUENCY (Hz) –50 09582-019 100k 1M FREQUENCY (Hz) 10M 100M 1M 10M Figure 19. 5 kΩ Gain vs. Frequency vs. Code Figure 22. 10 kΩ Gain vs. Frequency vs. Code Rev. 0 | Page 15 of 28 09582-022 –60 10k 09582-021 0 0 0 20 10 5 40 20 10 60 80 30 40 15 20 CODE (Decimal) 100 50 25 120 AD5110 60 AD5112 30 AD5114 0 0 0 20 10 5 40 20 10 60 80 30 40 15 20 CODE (Decimal) 100 50 25 120 AD5110 60 AD5112 30 AD5114 09582-020 –100 –40 AD5110/AD5112/AD5114 0 0x40 (0x20) [0x10] Data Sheet 80 70 60 5k + 250pF 10k + 75pF 10k + 150pF 10k + 250pF 80k + 0pF 80k + 75pF 80k + 150pF 80k + 250pF 5k + 0pF 5k + 75pF 5k + 150pF 10k + 0pF –10 0x20 (0x10) [0x08] 0x10 (0x08) [0x04] –20 0x08 (0x04) [0x02] 0x04 (0x02) [0x01] –30 0x02 (0x01) [0x00] BANDWIDTH (MHz) 09582-023 GAIN (dB) 50 40 30 20 10 –40 0x01 (0x00) –50 –60 –70 AD5110 (AD5112) [AD5114] 0x00 –80 10k 0 100k FREQUENCY (Hz) 1M Figure 23. 80 kΩ Gain vs. Frequency vs. Code 0 –10 –20 Figure 26. Maximum Bandwidth vs. Code vs. Net Capacitance 150 INCREMENTAL WIPER ON RESISTANCE (Ω) TEMPERATURE = 25°C 120 5.5V 5V 3.3V 2.7V 2.3V PHASE (Degrees) –30 –40 –50 –60 AD5110 RAB = 10kΩ –70 FULL SCALE HALF SCALE QUARTER SCALE –80 10k 100k FREQUENCY (Hz) 90 60 30 09582-024 1M 10M 0 1 2 3 VDD (V) 4 5 6 Figure 24. Normalized Phase Flatness vs. Frequency 0 –10 –20 –30 Figure 27. Incremental Wiper On Resistance vs. VDD 0 VDD = 5V, VA = 2.5V + 1VRMS VB = 2.5V CODE = HALF SCALE NOISE FILTER = 22kHz 5kΩ 10kΩ 80kΩ VDD = 5V, VA = 2.5V + VIN –10 VB = 2.5V fIN = 1kHz –20 CODE = HALF SCALE NOISE FILTER = 22kHz –30 5kΩ 10kΩ 80kΩ THD + N (dB) –40 –50 –60 –70 –80 –90 09582-025 THD + N (dB) –40 –50 –60 –70 –80 20 200 2k FREQUENCY (Hz) 20k 200k 0.01 0.1 1 AMPLITUDE (V rms) Figure 25. Total Harmonic Distortion + Noise (THD + N) vs. Frequency Figure 28. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude Rev. 0 | Page 16 of 28 09582-028 –100 –90 0.001 09582-027 0 09582-026 0 0 0 10 5 20 10 5 40 20 10 CODE (Decimal) 30 15 50 25 60 30 15 AD5110 AD5112 AD5114 Data Sheet 0.35 0.30 0.25 RELATIVE VOLTAGE (V) AD5110/AD5112/AD5114 VDD = 5V VA = VDD VB = GND 5kΩ 10kΩ 80kΩ VOLTAGE (mV) 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 09582-029 VDD = 5V VA = VDD VB = GND 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –1 1 3 5 TIME (µs) 7 9 –0.5 0 0.6 1.2 TIME (µs) 1.8 2.5 Figure 29. Maximum Transition Glitch 0.0025 1.2 Figure 32. Digital Feedthrough 0 –10 CUMULATIVE PROBABILITY 0.0020 1.0 5kΩ 10kΩ 80kΩ PROBABILITY DENSITY –20 0.8 GAIN (dB) 0.0015 0.6 –30 –40 –50 –60 –70 1k 10k 1M FREQUENCY (Hz) 10M 0.0010 0.4 0.0005 0.2 –600 –500 –400 –300 –200 –100 0 100 200 300 400 500 600 RESISTOR DRIFT (ppm) Figure 30. Resistor Lifetime Drift 0 –10 –20 09582-051 Figure 33. Shutdown Isolation vs. Frequency 7 6 THEORETICAL IMAX (mA) 5kΩ 10kΩ 80kΩ 10kΩ 80kΩ 5kΩ 5 PSRR (dB) –30 –40 –50 –60 –70 10 VDD = 5V ± 10% AC VA = 4V VB = GND HALF SCALE TA = 25°C 100 1k 10k 100k 1M 09582-031 4 3 2 1 0 FREQUENCY (Hz) Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 34. Theoretical Maximum Current vs. Code Rev. 0 | Page 17 of 28 09582-034 0 0 0 20 10 5 40 20 10 60 80 30 40 15 20 CODE (Decimal) 100 50 25 120 AD5110 60 AD5112 30 AD5114 09582-033 0 0 09582-032 10kΩ 80kΩ 5kΩ AD5110/AD5112/AD5114 TEST CIRCUITS Figure 35 to Figure 40 define the test conditions used in the Specifications section. NC DUT A W B VMS 09582-035 Data Sheet IW VDD V+ ~ VA A B V+ = VDD ± 10% ΔVMS PSRR (dB) = 20 log ΔV DD 09582-038 W VMS PSS (%/%) = ΔVMS% ΔVDD% NC = NO CONNECT Figure 35. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL) Figure 38. Power Supply Sensitivity (PSS, PSRR) A DUT A V+ B W 09582-036 +15V W V+ = VDD 1LSB = V+/2N VIN OFFSET GND DUT B 2.5V AD8652 VOUT 09582-039 VMS –15V Figure 36. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 39. Gain and Phase vs. Frequency VDD GND GND NC DUT A W B IWB RW = + 0.1V IWB VDD DUT A W B ICM 0.1V – 09582-037 GND NC = NO CONNECT VDD GND Figure 37. Wiper Resistance Figure 40. Common-Mode Leakage Current Rev. 0 | Page 18 of 28 09582-040 GND TO VDD VDD Data Sheet THEORY OF OPERATION The AD5110/AD5112/AD5114 digital programmable resistors are designed to operate as true variable resistors for analog signals within the terminal voltage range of GND < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the I2C interface. Once a desirable wiper position is found, this value can be stored in the EEPROM memory. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of EEPROM data takes approximately 18 ms; during this time, the device is locked and does not acknowledge any new command, thus preventing any changes from taking place. AD5110/AD5112/AD5114 I2C SERIAL DATA INTERFACE The AD5110/AD5112/AD5114 have 2-wire I2C-compatible serial interfaces. These devices can be connected to an I2C bus as a slave device under the control of a master device. See Figure 3 for a timing diagram of a typical write sequence. The AD5110/AD5112/AD5114 support standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address and an R/W bit. The slave device corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master brings the SDA line low before the 10th clock pulse, and high during the 10th clock pulse to establish a stop condition. RDAC REGISTER AND EEPROM The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with 0x3F (128-taps), the wiper is connected to full scale of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. It is possible to both write to and read from the RDAC register using the I2C interface (see Table 10). The contents of the RDAC register can be stored to the EEPROM using Command 1 (Table 10). Thereafter, the RDAC register is always set at that position for any future on-off-on power supply sequence. It is possible to read back the data saved into the EEPROM with Command 6 in Table 10. In addition, the resistor tolerance error is saved within the EEPROM; this can be read back and used to calculate the endto-end tolerance, providing an accuracy of 0.1%. 2. 3. 4. Low Wiper Resistance Feature The AD5110/AD5112/AD5114 include extra steps to achieve a minimum resistance between Terminal W and Terminal A or Terminal B. These extra steps are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 70 Ω to 45 Ω. At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB, and the total resistance is reduced to 70 Ω. The extra steps are not equal to 1 LSB and are not included in the INL, DNL, R-INL, and R-DNL specifications. I2C Address The AD5110/AD5112/AD5114 each have two different slave address options available. See Table 9 for a list of slave addresses. Table 9. Device Address Selection Model AD511X1 BCPZ Y2 AD511X1 BCPZ Y2-1 1 2 7-Bit I2C Device Address 0101111 0101100 Model. Resistance. Rev. 0 | Page 19 of 28 AD5110/AD5112/AD5114 INPUT SHIFT REGISTER For the AD5110/AD5112/AD5114, the input shift register is 16 bits wide (see Figure 2). The 16-bit word consists of five unused bits (should be set to zero), followed by three control bits, and eight RDAC data bits. If the RDAC register is read from or written to in the AD5112, Bit DB0 is a don’t care. The RDAC register is read from or written to in the AD5114, Bit DB0 and DB1 are don’t cares. Data is loaded MSB first (Bit DB15). Table 10. Command Operation Truth Table Command Number 0 1 2 Command DB10 DB8 C2 C1 C0 0 0 0 0 0 1 0 1 0 Data1 DB7 D7 X X 7 MSB 1 1 X D6 X X 6 0 1 X D5 X X 5 0 1 X D4 X X 4 0 1 X D3 X X 3 0 1 X D2 X X 2 0 1 X D1 X X 12 0 1 X DB0 D0 X X 02, 3 LSB 0 1 A0 Data Sheet The three control bits determine the function of the software command (Table 10). Figure 3 shows a timing diagram of a typical AD5110/AD5112/AD5114 write sequence. The command bits (Cx) control the operation of the digital potentiometer and the internal EEPROM. The data bits (Dx) are the values that are loaded into the decoded register. Operation No operation Write contents of RDAC register to EEPROM Write contents of serial register data to RDAC Top scale Bottom scale Software shutdown 0: shutdown off 1: shutdown on Software reset: refresh RDAC register with EEPROM Read contents of RDAC register Read contents of EEPROM A1 A0 Data 0 0 Wiper position saved 0 1 Resistor tolerance 3 0 1 1 4 5 6 1 1 1 0 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X A1 X X A0 1 2 3 X is don’t care. In the AD5114, this bit is a don’t care. In the AD5112, this bit is a don’t care. Rev. 0 | Page 20 of 28 Data Sheet WRITE OPERATION When writing to the AD5110/AD5112/AD5114, the user must begin with a start command followed by an address byte (R/W = 0), after which the AD5110/AD5112/AD5114 acknowledge that it is prepared to receive data by pulling SDA low. Two bytes of data are then written to the DAC, the most significant byte, followed by the least significant byte. Both of 1 SCL 9 AD5110/AD5112/AD5114 these data bytes are acknowledged by the AD5110/AD5112/ AD5114. A stop condition follows. The write operations for the AD5110/AD5112/AD5114 are shown in Figure 41, Figure 42, and Figure 43. A repeated write function gives the user flexibility to update the device a number of times after addressing the part only once, as shown in Figure 44. 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY AD5110 0 0 0 0 0 C2 C1 C0 ACK. BY AD5110 FRAME 1 SERIAL BUS ADDRESS BYTE 9 SCL (CONTINUED) 1 FRAME 2 MOST SIGNIFICANT DATA BYTE 9 SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 09582-041 09582-042 ACK. BY STOP BY AD5110 MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE Figure 41. AD5110 Interface Write Command 1 SCL 9 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY AD5112 0 0 0 0 0 C2 C1 C0 ACK. BY AD5112 FRAME 1 SERIAL BUS ADDRESS BYTE 9 SCL (CONTINUED) 1 FRAME 2 MOST SIGNIFICANT DATA BYTE 9 SDA (CONTINUED) D6 D5 D4 D3 D2 D1 D0 0 ACK. BY STOP BY AD5112 MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE Figure 42. AD5112 Interface Write Command Rev. 0 | Page 21 of 28 AD5110/AD5112/AD5114 1 SCL 9 1 9 Data Sheet SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY AD5114 0 0 0 0 0 C2 C1 C0 ACK. BY AD5114 FRAME 1 SERIAL BUS ADDRESS BYTE 9 SCL (CONTINUED) 1 FRAME 2 MOST SIGNIFICANT DATA BYTE 9 SDA (CONTINUED) D5 D4 D3 D2 D1 D0 0 0 09582-043 ACK. BY STOP BY AD5114 MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE Figure 43. AD5114 Interface Write Command 1 SCL 9 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY AD5110 0 0 0 0 0 C2 C1 C0 ACK. BY AD5110 FRAME 1 SERIAL BUS ADDRESS BYTE 9 SCL (CONTINUED) 1 FRAME 2 MOST SIGNIFICANT DATA BYTE 9 SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD5110 FRAME 3 LEAST SIGNIFICANT DATA BYTE 9 SCL (CONTINUED) 1 9 SDA (CONTINUED) 0 0 0 0 0 C2 C1 C0 ACK. BY AD5110 FRAME 4 MOST SIGNIFICANT DATA BYTE 9 SCL (CONTINUED) 1 9 SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 09582-044 ACK. BY STOP BY AD5110 MASTER FRAME 5 LEAST SIGNIFICANT DATA BYTE Figure 44. AD5110 Interface Multiple Write Rev. 0 | Page 22 of 28 Data Sheet EEPROM WRITE ACKNOWLEGDE POLLING After each write operation to the EEPROM, an internal write cycle begins. The I2C interface of the device is disabled. To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition, followed by the slave address and the write bit. If the I2C interface responds with an acknowledge, the write cycle is complete, and the interface is ready to proceed with further operations. Otherwise, I2C interface polling can be repeated until it succeeds. AD5110/AD5112/AD5114 the RDAC register, EEPROM memory. The user can then read back the data. This begins with a start command followed by an address byte (R/W = 1), after which the device acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the device, which are both acknowledged by the master, as shown in Figure 45. A stop condition follows. If the master does not acknowledge the first byte, then the second byte is not transmitted by the AD5110/ AD5112/AD5114. The AD5110/AD5112/AD5114 does not support repeat readback. READ OPERATION The AD5110/AD5112/AD5114 allow read back of the contents of the RDAC register and EEPROM memory through the I2C interface by using Command 6 (see Table 10). When reading data back from the AD5110/AD5112/AD5114, the user must first issue a readback command to the device. This begins with a start command, followed by an address byte (R/W = 0), after which the AD5110/AD5112/AD5114 acknowledges that it is prepared to receive data by pulling SDA low. Two bytes of data are then written to the AD5110/AD5112/ AD5114, the most significant byte followed by the least significant byte. Both of these data bytes are acknowledged by the AD5110/AD5112/AD5114. A stop condition follows. These bytes contain the read instruction, which enables readback of 1 SCL 9 1 RESET The AD5110/AD5112/AD5114 can be reset by executing Command 4 (see Table 10). The reset command loads the RDAC register with the contents of the EEPROM and takes approximately 25 µs. EEPROM is pre-loaded to midscale at the factory, and initial power-up is, accordingly, at midscale. SHUTDOWN MODE The AD5110/AD5112/AD5114 can be shut down by executing the software shutdown command, Command 3 (see Table 10). This feature places the RDAC in a zero-power-consumption state where Terminal A is open-circuited and the wiper, Terminal W is connected to Terminal B but a finite wiper resistance of 45 Ω is present. The part can be taken out of shutdown mode by executing Command 3 (see Table 10) and setting Bit DB0 to 0. 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY AD5110 0 0 0 0 0 C2 C1 C0 ACK. BY AD5110 FRAME 1 SERIAL BUS ADDRESS BYTE 9 SCL (CONTINUED) 1 FRAME 2 MOST SIGNIFICANT DATA BYTE 9 SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD5110 STOP BY MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE 1 SCL 9 1 9 SDA START BY MASTER 0 1 0 1 1 A1 A0 R/W ACK. BY AD5110 0 0 0 0 0 C2 C1 C0 09582-045 NO ACK. STOP BY BY MASTER MASTER FRAME 2 MOST SIGNIFICANT DATA BYTE FRAME 1 SERIAL BUS ADDRESS BYTE Figure 45. AD5110 Interface Read Command Rev. 0 | Page 23 of 28 AD5110/AD5112/AD5114 RDAC ARCHITECTURE To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5110/AD5112/AD5114 employ a two-stage segmentation approach as shown in Figure 46. The AD5110/AD5112/AD5114 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD. A TS B B B Data Sheet PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation—±8% Resistor Tolerance The AD5110/AD5112/AD5114 operate in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating or tied to the Terminal W as shown in Figure 47. A W A W A W 09582-047 RL Figure 47. Rheostat Mode Configuration RL RS W RS 6-BIT/7-BIT/8-BIT ADDRESS DECODER RL The nominal resistance between Terminal A and Terminal B, RAB, is available in 5 kΩ, 10 kΩ, and 80 kΩ and has 32/64/128 tap points accessed by the wiper terminal. The 5-/6-/7-bit data in the RDAC latch is decoded to select one of the 32/64/128 possible wiper settings. The general equations for determining the digitally programmed output resistance between the W terminal and B terminal are AD5110: RWB  R BS RWB (D )  D  R AB  RW 128 Bottom scale (0xFF) (1) From 0x00 to 0x80 (2) RL BS AD5112: RWB  R BS RWB (D )  D  R AB  RW 64 09582-046 B Bottom scale (0xFF) (3) From 0x00 to 0x40 (4) Figure 46. AD5110/AD5112/AD5114 Simplified RDAC Circuit AD5114: Top Scale/Bottom Scale Architecture In addition, the AD5110/AD5112/AD5114 include a new feature to reduce the resistance between terminals. These extra steps are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 70 Ω to 45 Ω. At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB, and the total resistance is reduced to 70 Ω. The extra steps are not equal to 1 LSB and are not included in the INL, DNL, R-INL, and R-DNL specifications. RWB  RBS RWB (D )  D  RAB  RW 32 Bottom scale (0xFF) (5) From 0x00 to 0x20 (6) where: D is the decimal equivalent of the binary code in the 5-/6-/7-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. RBS is the wiper resistance at bottom scale Rev. 0 | Page 24 of 28 Data Sheet Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA also gives a maximum of 8% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equations for this operation are AD5110: DB7 Sign DB6 24 DB5 23 AD5110/AD5112/AD5114 Table 11. Tolerance Format Data Byte DB4 DB3 22 21 DB2 2-1 DB1 2-2 DB0 2-3 . For example, if RAB = 10 kΩ and the data readback shows 01010010, the end-to-end resistance can be calculated as, if, DB[7] is 0 = negative DB[6:3] is 1010 = 10 DB[2:0] is 010 = 2 × 2−3 = 0.25 then, tolerance = −10.25% and, therefore, RAB = 8.975 kΩ RAW = RAB + RW RAW (D ) = 128 − D × RAB + RW 128 Bottom scale (0xFF) (7) From 0x00 to 0x7F (8) Top scale (0x80) (9) Bottom scale (0xFF) (10) From 0x00 to 0x3F (11) Top scale (0x40) (12) Bottom scale (0xFF) (13) From 0x00 to 0x1F (14) RAW = RTS AD5112: PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A that is proportional to the input voltage at A to B, as shown in Figure 48. Unlike the polarity of VDD to GND, which must be positive, voltage across A-to-B, Wto-A, and W-to-B can be at either polarity. VI A W VO 09582-048 RAW = RAB + RW RAW (D ) = 64 − D × RAB + RW 64 RAW = RTS AD5114: RAW = RAB + RW RAW (D ) = 32 − D × RAB + RW 32 B RAW = RTS Top scale (0x20) (15) where: D is the decimal equivalent of the binary code in the 5-/6-/7-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. RTS is the wiper resistance at top scale. In the bottom-scale condition or top-scale condition, a finite total wiper resistance of 45 Ω is present. Regardless of which setting the part is operating in, take care to limit the current between Terminal A to Terminal B, Terminal W to Terminal A, and Terminal W to Terminal B, to the maximum continuous current of ±6 mA or to the pulse current specified in Table 6. Otherwise, degradation or possible destruction of the internal switch contact can occur. Figure 48. Potentiometer Mode Configuration Connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 5 V. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B, is: VW (D ) = R (D ) RWB (D ) × VA + AW × VB RAB RAB (16) where: RWB(D) can be obtained from Equation 1 to Equation 6. RAW(D) can be obtained from Equation 7 to Equation 15. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RAW and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. Calculating the Actual End-to-End Resistance The resistance tolerance is stored in the internal memory during factory testing. The actual end-to-end resistance can, therefore, be calculated, which is valuable for calibration, tolerance matching, and precision applications. The resistance tolerance in percentage is stored in fixed-point format, using an 8-bit sign magnitude binary. The data can be read back by executing Command 6 and setting Bit DB0 (A0). The MSB is the sign bit (0 = − and 1 = +) and the next four bits are the integer part, the fractional part is represented by the three LSBs, as shown in Table 11. Rev. 0 | Page 25 of 28 AD5110/AD5112/AD5114 TERMINAL VOLTAGE OPERATING RANGE The AD5110/AD5112/AD5114 are designed with internal ESD diodes for protection. These diodes also set the voltage boundary of the terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are clamped by the forward-biased diode. There is no polarity constraint between VA, VW, and VB, but they cannot be higher than VDD or lower than GND. VDD Data Sheet of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VDD and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, once VLOGIC is powered, the power-on preset activates, which restores EEPROM values to the RDAC registers. LAYOUT AND POWER SUPPLY BIASING It is always a good practice to use compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also good practice to bypass the power supplies with quality capacitors. Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and to filter low frequency ripple. Figure 50 illustrates the basic supply bypassing configuration for the AD5110/AD5112/AD5114. AD5110/ AD5112/ AD5114 VDD + C2 10µF C1 0.1µF VDD VLOGIC C3 0.1µF C4 10µF + VLOGIC A W B 09582-049 GND Figure 49. Maximum Terminal Voltages Set by VDD and GND POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (Figure 49), it is important to power VDD first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forward-biased such that VDD is powered unintentionally. The ideal power-up sequence is GND, VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order Figure 50. Power Supply Bypassing Rev. 0 | Page 26 of 28 09582-050 GND Data Sheet OUTLINE DIMENSIONS 2.00 BSC SQ 5 AD5110/AD5112/AD5114 1.70 1.60 1.50 0.50 BSC 8 PIN 1 INDEX AREA 0.425 0.350 0.275 4 TOP VIEW EXPOSED PAD 1.10 1.00 0.90 1 BOTTOM VIEW PIN 1 INDICATOR (R 0.15) 0.60 0.55 0.50 SEATING PLANE 0.30 0.25 0.20 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 063009-A 0.20 REF Figure 51. 8-Lead Frame Chip Scale Package[LFCSP_UD] 2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead (CP-8-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5110BCPZ10-RL7 AD5110BCPZ10-500R7 AD5110BCPZ10-1-RL7 AD5110BCPZ80-RL7 AD5110BCPZ80-500R7 AD5110BCPZ80-1-RL7 AD5112BCPZ5-RL7 AD5112BCPZ5-500R7 AD5112BCPZ5-1-RL7 AD5112BCPZ10-RL7 AD5112BCPZ10-500R7 AD5112BCPZ10-1-RL7 AD5112BCPZ80-RL7 AD5112BCPZ80-500R7 AD5112BCPZ80-1-RL7 AD5114BCPZ10-RL7 AD5114BCPZ10-500R7 AD5114BCPZ10-1-RL7 AD5114BCPZ80-RL7 AD5114BCPZ80-500R7 AD5114BCPZ80-1-RL7 EVAL-AD5110SDZ 1 RAB (kΩ) 10 10 10 80 80 80 5 5 5 10 10 10 80 80 80 10 10 10 80 80 80 Resolution 128 128 128 128 128 128 64 64 64 64 64 64 64 64 64 32 32 32 32 32 32 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD Evaluation Board I2C Address 0101111 0101111 0101100 0101111 0101111 0101100 0101111 0101111 0101100 0101111 0101111 0101100 0101111 0101111 0101100 0101111 0101111 0101100 0101111 0101111 0101100 Package Option CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 CP-8-10 Branding 4J 4J 4H 4L 4L 4K 7P 7P 7N 7L 7L 7K 7R 7R 7Q 81 81 80 83 83 82 Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 AD5110/AD5112/AD5114 NOTES Data Sheet I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09582-0-10/11(0) Rev. 0 | Page 28 of 28