AD5757x

Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity Preliminary Technical Data FEATURES 16/12-Bit Resolution and Monotonicity Dynamic Power Control for Thermal Management IOUT Range: 0mA-20mA, 4mA–20mA or 0mA–24mA ±0.05% Total Unadjusted Error (TUE) Max User programmable Offset and Gain On Chip Diagnostics On-Chip Reference (±5 ppm/°C Max) −40°C to +105°C Temperature Range AD5757/AD5737 GENERAL DESCRIPTION The AD5757/AD5737 is a quad, current output DAC, which operates with a power supply of up to +33v. On chip dynamic power control minimizes package power dissipation in current mode. This is achieved by regulating the voltage on the output driver from between 7V-30V. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the AD5757/AD5737’s current output. The part uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and that is compatible with standard SPI®, QSPI™, MICROWIRE™, DSP and microcontroller interface standards. The interface also features optional CRC-8 packet error checking as well as a watchdog timer that monitors activity on the interface. Table 1. Complementary Devices Part No. ADR445 ADP1871 Description 5V, Ultralow Noise, LDO XFET Voltage Reference with Current Sink and Source Synchronous Buck Controller with Constant On-Time, Valley Current Mode, and Power Save Mode APPLICATIONS Process Control Actuator Control PLC’s HART Network Connectivity PRODUCT HIGHLIGHTS Dynamic Power Control for Thermal management 16bit performance Multi-channel HART Compliant Figure 1. Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. AD5757/AD5737 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Product Highlights ........................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Performance Characteristics ................................................ 5 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 13 Theory of Operation ...................................................................... 14 DAC Architecture ....................................................................... 14 Power On State of AD5757/AD5737 ....................................... 14 Serial Interface ............................................................................ 14 Registers ........................................................................................... 15 Programming Sequence to Write/Enable the Output Correctly ...................................................................................... 16 Changing and Reprogramming the Range ............................. 16 Data Registers ............................................................................. 17 Control Registers ........................................................................ 20 Readback Operation .................................................................. 23 Preliminary Technical Data Features ............................................................................................ 25 Output Fault ................................................................................ 25 Digital Offset and Gain Control ............................................... 25 Status Readback During Write ................................................. 25 Asynchronous Clear................................................................... 25 Packet Error Checking ............................................................... 26 Watchdog timer .......................................................................... 26 Output Alert ................................................................................ 26 Internal Reference ...................................................................... 26 External current setting resistor ............................................... 26 HART ........................................................................................... 26 Slew rate control ......................................................................... 26 Power Dissipation control ......................................................... 27 DC-DC Converters .................................................................... 27 Applications Information .............................................................. 29 Precision Voltage Reference Selection ..................................... 29 Driving Inductive Loads............................................................ 29 Transient voltage protection ..................................................... 29 Microprocessor Interfacing ....................................................... 29 Layout Guidelines....................................................................... 29 Galvanically Isolated Interface ................................................. 30 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31 Rev. PrD | Page 2 of 31 Preliminary Technical Data SPECIFICATIONS AD5757/AD5737 AVDD = 15V, AVSS = 0V/-15 V, VBOOSTA,B,C,D = +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND = GNDSWA,B,C,D = 0 V, REFIN= +5, VOUT : RL = 1kΩ, CL = 220pF, IOUT : RL = 300Ω, all specifications TMIN to TMAX unless otherwise noted. Table 2. Parameter 1 CURRENT OUTPUT Output Current Ranges Min 0 0 4 16 12 Typ Max 24 20 20 Unit mA mA mA Bits Bits Test Conditions/Comments Resolution ACCURACY (External RSet) Total Unadjusted Error (TUE) AD5757 AD5737 TUE TC2 Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift2 Gain Error Gain TC Full-Scale Error Full-Scale TC2 ACCURACY (Internal RSet) Total Unadjusted Error (TUE) 2 −0.05 −0.02 −TBD −0.006 −0.025 −1 −0.035 −TBD TBD ±TB D +0.05 +0.02 +TBD +0.006 +0.025 +1 +0.035 +TBD % FSR % FSR ppm % FSR % FSR LSB % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C TA = 25°C AD5757 AD5737 Guaranteed monotonic TA = 25°C TBD ±TB D TBD −0.02 −TBD −TBD −0.05 −TBD −TBD TBD +0.02 +TBD +TBD +0.05 +TBD +TBD TA = 25°C TA = 25°C TUE TC2 Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error Full-Scale TC2 −0.12 −0.02 −TBD −0.006 −0.025 −1 −0.04 −TBD TBD ±TB D +0.12 +0.02 +TBD +0.006 +0.025 +1 +0.04 +TBD % FSR % FSR ppm % FSR % FSR LSB % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C TA = 25°C AD5757 AD5737 Guaranteed monotonic TA = 25°C TBD ±TB D TBD −0.08 −TBD −TBD −0.12 −TBD −TBD TBD +0.08 +TBD +TBD +0.12 +TBD +TBD TA = 25°C TA = 25°C Rev. PrD | Page 3 of 31 AD5757/AD5737 Parameter 1 OUTPUT CHARACTERISTICS2 Current Loop Compliance Voltage Output Current Drift vs. Time Min Typ TBD ±TB D ±TB D Resistive Load See Com men t See Com men t TBD TBD Output Impedance REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Reference Output Output Voltage Reference TC23 Output Noise (0.1 Hz to 10 Hz) 2 Noise Spectral Density2 Output Voltage Drift vs. Time2 50 Max AVDD 2.5 Unit V max ppm FSR ppm FSR Ω max Preliminary Technical Data Test Conditions/Comments Drift after 500 hours, TJ = 150°C (this is included in the TUE specifications) Drift after 1000 hours, TJ = 150°C (this is included in the TUE specifications) Chosen such that compliance is not exceeded. Plus see graph on load vs AVcc and DCDC switching freq. Inductive Load H max Will need appropriate cap at higher inductance values. See Page X of Datasheet. DC PSRR µA/V µA/V MΩ 4.95 5 4.998 -10 5 TBD 5 ±5 TBD TBD ±TB D ±TB D 5 7 10 TBD TBD 5.05 V nom MΩ min V ppm/°C µV p-p typ nV/√Hz typ ppm ppm For specified performance 5.002 10 TA = 25°C At 10 kHz Drift after 500 hours, TJ = 150°C Drift after 1000 hours, TJ = 150°C Capacitive Load2 Load Current Short Circuit Current Line Regulation2 Load Regulation2 Thermal Hysteresis2 DC-DC SWITCH SWITCH On Resistance SWITCH Leakage Current Peak Current Limit OSCILLATOR Oscillator Frequency Maximum Duty Cycle DIGITAL INPUTS2 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance DIGITAL OUTPUTS2 SDO, ALERT TBD nF mA mA ppm/V ppm/mA ppm 0.5 TBD 0.8 TBD TBD TBD TBD ohm uA A KHz % VIN=TBD, IOUT=TBD, RLOAD=TBD JEDEC compliant 2 −1 10 0.8 +1 V V µA pF Per pin Per pin Rev. PrD | Page 4 of 31 Preliminary Technical Data Parameter 1 VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance FAULT VOL, Output Low Voltage VOL, Output Low Voltage VOH, Output High Voltage POWER REQUIREMENTS AVDD AVSS DVDD, AVCC Input Voltage AIDD AISS DICC AIcc Power Dissipation Min DVDD −0.5 −1 5 Typ Max 0.4 Unit V V µA pF AD5757/AD5737 Test Conditions/Comments sinking 200 µA sourcing 200 µA +1 0.4 0.6 3.6 12 −26.4 33 −10.8/ 0 5.5 TBD TBD TBD TBD TBD TBD TBD V V V V V 10kΩ pull-up resistor to DVDD At 2.5 mA 10kΩ pull-up resistor to DVDD AVss can be tied to AGND 2.7 V mA mA mA mA mW mW mW Output unloaded Bipolar Supply Mode only, outputs unloaded VIH = DVDD, VIL = GND DCDC ’s not enabled AVDD = 33V, AVSS = 0V, outputs unloaded AVDD = 33V, AVSS = -26.4 V, outputs unloaded AVDD = 15V, AVSS = -15 V, outputs unloaded 1 2 3 Temperature range: −40°C to +105°C; typical at +25°C. Guaranteed by design and characterization; not production tested. The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +105°C. AC PERFORMANCE CHARACTERISTICS AVDD = 15V, AVSS = 0V/-15 V, VBOOSTA,B,C,D = +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND = GNDSWA,B,C,D = 0 V, REFIN= +5, VOUT : RL = 1kΩ, CL = 220pF, IOUT : RL = 300Ω, all specifications TMIN to TMAX unless otherwise noted. Table 3. Parameter1 DYNAMIC PERFORMANCE Current Output Output Current Settling Time Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise (100 kHz Bandwidth) Output Noise Spectral Density Slew Rate Min Typ Max Unit Test Conditions/Comments TBD 0.1 TBD µs typ ms typ LSB p-p µV rms nV/√Hz uA/µs µs To 0.1% FSR See Figure 7 and Figure 8 (16-Bit LSB) 80 TBD TBD TBD Measured at 10 kHz To 0.1% FSR. See Figure 7 and Figure 8 for plots with a channels DC-DC enabled. 1 Guaranteed by characterization, not production tested. Rev. PrD | Page 5 of 31 AD5757/AD5737 TIMING CHARACTERISTICS Preliminary Technical Data AVDD = 15V, AVSS = 0V/-15 V, VBOOSTA,B,C,D = +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND = GNDSWA,B,C,D = 0 V, REFIN= +5, VOUT : RL = 1kΩ, CL = 220pF, IOUT : RL = 300Ω, all specifications TMIN to TMAX unless otherwise noted. Table 4. Parameter1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 Limit at TMIN, TMAX 33 13 13 13 13 198 5 5 20 5 t10 t11 t12 t13 t14 t15 t16 10 500 See AC Performance Characteristics 10 TBD 25 20 5 t17 t18 t19 500 700 20 5 1 2 Unit ns min ns min ns min ns min ns min ns min ns min ns min µs min µs min ns min ns max µs max ns min µs max ns max µs min µs min ns min ns min µs min µs min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24/32nd SCLK falling edge to SYNC rising edge SYNC high time Data setup time Data hold time SYNC rising edge to LDAC falling edge (all DACs updated or any channel has digital slew rate control enabled) SYNC rising edge to LDAC falling edge (single DAC updated) LDAC pulse width low LDAC falling edge to DAC output response time DAC output settling time CLEAR high time CLEAR activation time SCLK rising edge to SDO valid (CL SDO = 35 pF) SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated) SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated) LDAC falling edge to SYNC rising edge RESET pulsewidth SYNC high to next SYNC low (Ramp enabled) SYNC high to next SYNC low (Ramp disabled) Guaranteed by design and characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 2 , Figure 3 , Figure 4 and Figure 5 Rev. PrD | Page 6 of 31 Preliminary Technical Data t1 SCLK 1 2 24 AD5757/AD5737 t6 t4 SYNC t3 t2 t5 t7 SDIN MSB t8 LSB t19 t10 LDAC t9 t10 t17 t11 VOUT t12 LDAC = 0 t12 t16 VOUT t13 CLEAR t14 VOUT ALERT RESET t18 FAULT Figure 2. Serial Interface Timing Diagram Rev. PrD | Page 7 of 31 AD5757/AD5737 SCLK Preliminary Technical Data 1 24 1 24 t6 SYNC SDIN MSB LSB MSB LSB INPUT WORD SPECIFIES REGISTER TO BE READ SDO MSB LSB MSB NOP CONDITION LSB UNDEFINED SELECTED REGISTER DATA CLOCKED OUT t 15 Figure 3. Readback Timing Diagram SCLK 1 2 MSB SYNC SDIN R/W DUT_ AD1 DUT_ AD0 X X X DB15 DB14 DB1 DB0 SDO SDO DISABLED SDO ENAB Status Status Status Status Status Bits Readout Figure 4. Status Readback during write 200µA IOL TO OUTPUT PIN CL 50pF 200µA IOH VOH (MIN) OR VOL (MAX) 05303-005 Figure 5. Load Circuit for SDO Timing Diagram Rev. PrD | Page 8 of 31 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter AVDD to AGND, DGND AVSS to AGND, DGND AVDD to AVSS AVcc to AGND DVDD to DGND Digital Inputs to DGND Digital Outputs to DGND REFIN/REFOUT to AGND IOUT A,B,C,D to AGND RSETA,B,C,D to AGND SWA,B,C,D / VBOOSTA,B,C,D to AGND COMPDCDC_A,B,C,D/ CHARTA,B,C,D to AGND AGND, GNDSWA,B,C,D to DGND Operating Temperature Range (TA) Industrial1 Storage Temperature Range Junction Temperature (TJ max) 64-Lead LFCSP θJA Thermal Impedance2 Power Dissipation Lead Temperature Soldering 1 AD5757/AD5737 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.3 V to +33 V +0.3 V to −28 V −0.3 V to +60 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) −0.3 V to DVDD + 0.3 V −0.3 V to AVDD + 0.3 V or +7 V (whichever is less) −0.3 V to AVDD −0.3 V to AVDD + 0.3 V or +7 V (whichever is less) −0.3 to +33 V −0.3 V to +5 V −0.3 V to +0.3 V −40°C to +105°C −65°C to +150°C 125°C 20°C/W (TJ max – TA)/θJA JEDEC Industry Standard J-STD-020 ESD CAUTION Power dissipated on chip must be derated to keep the junction temperature below 125°C 2 Based on a JEDEC 4 layer test board Rev. PrD | Page 9 of 31 AD5757/AD5737 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RSETC RSETD REFOUT REFIN N/C CHARTD IGATED COMPDCDC_D VBOOSTD N/C IOUTD AVSS N/C CHARTC N/C IGATEC Preliminary Technical Data 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Mnemonic RSET_B RSET_A REFGND REFGND ADO AD1 SYNC SCLK SDIN SDO DVDD DGND LDAC Description An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the IOUT_B temperature drift performance. See the Features section. An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the IOUT_A temperature drift performance. See the Features section. Ground Reference Point for Internal Reference. Ground Reference Point for Internal Reference. Address decode for the DUT on the board. Address decode for the DUT on the board. Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 3 and Figure 4. Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. Digital Ground Pin. Load DAC. Active Low Input. This is used to update the DAC registers and consequently the analog outputs. When tied permanently low the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle the DAC input register is updated but the output update only takes place at the falling edge of LDAC. See Figure 2. Using this mode all analog outputs can be updated simultaneously. The LDAC pin must not be left unconnected. Active High, Edge Sensitive Input. Asserting this pin sets the Output Current/Voltage to the preprogrammed CLEAR CODE. Only channels enabled to be cleared will be cleared. See features section for Rev. PrD | Page 10 of 31 14 CLEAR DGND RESET AVDD N/C CHARTA IGATEA COMPDCDC_A VBOOSTA N/C IOUTA AVSS N/C CHARTB N/C IGATEB COMPDCDC_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 6. 64 LFCSP Pin Configuration 00000-000 RSETB RSETA REFGND REFGND AD0 AD1 SYNC SCLK SDIN SDO DVDD DGND LDAC CLEAR ALERT FAULT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR 64 LFCSP 48 COMPDCDC_C 47 IOUTC 46 VBOOSTC 45 AVCC 44 SWC 43 GND_SWC 42 GND_SWD 41 SWD 40 AVss 39 SWA 38 GND_SWA 37 GND_SWB 36 SWB 35 AGND 34 VBOOSTB 33 IOUTB Preliminary Technical Data Pin No. 15 16 Mnemonic ALERT FAULT AD5757/AD5737 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 DGND RESET AVDD N/C CHARTA IGATEA COMPDCDC_A VBOOST_A N/C IOUT_A AVSS N/C CHARTB N/C IGATEB COMPDCDC_B IOUT_B VBOOST_B AGND SW_B GNDSW_B GNDSW_A SW_A AVSS SW_D GNDSW_D GNDSW_C SW_C AVCC VBOOST_C IOUT_C COMPDCDC_C IGATEC N/C CHARTC N/C Description more information. When CLEAR is active, the DAC register cannot be written to. Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a predetermined time. See features section for more information. Active Low Output. This pin is asserted low when an open circuit in current mode is detected or a short circuit in voltage mode is detected or a PEC error is detected or an over temperature is detected (see Features section). Open Drain Output. Digital Ground Pin. Hardware Reset. Active Low Input. Positive Analog Supply Pin. Voltage ranges from 10.8 V to 33 V. No Connection. Do not connect to this pin. Hart Input Connection for DAC Channel A Optional connection for external pass transistor. Not required when using DC-DC. Should be left unconnected. DC-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of channel A’s DC-DC converter. Supply for channel A’s current output stage (See Figure 14). To use the DC-DC feature of the device, connect as shown in Figure 20. No Connection. Do not connect to this pin. Current Output Pin for DAC Channel A. Negative Analog Supply Pin. This Can be connected to AGND. No Connection. Do not connect to this pin. Hart Input Connection for DAC Channel B No Connection. Do not connect to this pin. Optional connection for external pass transistor. Not required when using DC-DC. Should be left unconnected. DC-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of channel B’s DC-DC converter. Current Output Pin for DAC Channel B. Supply for channel B’s current output stage (See Figure 14). To use the DC-DC feature of the device, connect as shown in Figure 1. Ground Reference Point for Analog Circuitry. This must be connected to 0 V. Switching output for Channel B’s DC-DC circuitry. To use the DC-DC feature of the device, connect as shown in Figure 1. Ground connection for DC-DC switching circuit. This pin should always be connected to GND. Ground connection for DC-DC switching circuit. This pin should always be connected to GND. Switching output for Channel A’s DC-DC circuitry. To use the DC-DC feature of the device, connect as shown in Figure 1. Negative Analog Supply Pin. Switching output for Channel D’s DC-DC circuitry. To use the DC-DC feature of the device, connect as shown in Figure 1. Ground connections for DC-DC switching circuit. This pin should always be connected to GND. Ground connections for DC-DC switching circuit. This pin should always be connected to GND. Switching output for Channel C’s DC-DC circuitry. To use the DC-DC feature of the device, connect as shown in Figure 1. Supply for DC-DC circuitry. Supply for channel C’s current output stage (See Figure 14). To use the DC-DC feature of the device, connect as shown in Figure 1. Current Output Pin for DAC Channel C. DC-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of channel C’s DC-DC converter. Optional connection for external pass transistor. Not required when using DC-DC. Should be left unconnected. No Connection. Do not connect to this pin. Hart Input Connection for DAC Channel B No Connection. Do not connect to this pin. Rev. PrD | Page 11 of 31 AD5757/AD5737 Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic AVSS IOUT_D N/C VBOOST_D COMPDCDC_D IGATED CHARTD N/C REFIN REFOUT RSET_D RSET_C Exposed PADDLE Preliminary Technical Data Description Negative Analog Supply Pin. Current Output Pin for DAC Channel D. No Connection. Do not connect to this pin. Supply for channel D’s current output stage (See Figure 14). To use the DC-DC feature of the device, connect as shown in Figure 1. DC-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of channel D’s DC-DC converter. Optional connection for external pass transistor. Not required when using DC-DC. Should be left unconnected. Hart Input Connection for DAC Channel D No Connection. Do not connect to this pin. External Reference Voltage Input. Internal Reference Voltage Output. An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the IOUT_D temperature drift performance. See the Features section. An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the IOUT_C temperature drift performance. See the Features section. CONNECTED TO AVss SUPPLY Rev. PrD | Page 12 of 31 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS AD5757/AD5737 TBD Figure 7. Iout settling 0-24mA though 1kΩ load, AVcc=3.0V, LDCDC=10uH, DCDC frequency=250kHz, CDCDC varied. (See Figure 20) Figure 10. TBD Figure 8. Iout settling 0-24mA though 1kΩ load, AVcc=3.0V, LDCDC=10uH, DCDC frequency=406kHz, CDCDC varied. (See Figure 20) Figure 11. TBD Figure 9 TBD Figure 12 Rev. PrD | Page 13 of 31 AD5757/AD5737 THEORY OF OPERATION The AD5757/AD5737 is a quad, precision digital to current loop converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop outputs. The current ranges available are; 0 to 20mA, 0 to 24mA and 4 to 20mA. The desired output configuration is user selectable via the DAC Control Register. On chip dynamic power control minimizes package power dissipation in current mode. Preliminary Technical Data to 5 V, 5 V for specified performance. This input voltage is then buffered before it is applied to the DAC. POWER ON STATE OF AD5757/AD5737 On initial power-up of the AD5757/AD5737 with the Iout pin in tri-state mode. SERIAL INTERFACE The AD5757/AD5737 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI®, QSPI™, MICROWIRE™, and DSP standards. Data coding is always straight binary. DAC ARCHITECTURE The DAC core architecture of the AD5757/AD5737 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 13. The 4 MSBs of the 16/12-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects 1 of 15 matched resistors to either ground or the reference buffer output. The remaining 12/8 bits of the dataword drive switches S0 to S11 /S7 of a 12/8-bit voltage mode R2R ladder network. VOUT 2R 2R S0 2R S1 2R S7/S11 2R E1 2R E2 2R E15 Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. There are two ways in which the DAC outputs can be updated as outlined below. Individual DAC Updating In this mode, LDAC is held low while data is being clocked into the DAC Data Register. The addressed DAC output is updated on the rising edge of SYNC. 8-12 BIT R-2R LADDER FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS 06996-057 Simultaneous Updating of All DACs In this mode, LDAC is held high while data is being clocked into the DAC Data Register. Only the first write to each channels data register will be valid after LDAC is brought high. Any subsequent writes while LDAC is still held high will be ignored. All the DAC outputs are updated by taking LDAC low any time after SYNC has been taken high. OUTPUT I/V AMPLIFIER VREFIN 16-BIT DAC VOUT Figure 13. DAC Ladder Structure The voltage output from the DAC core is converted to a current (see Figure 14) which is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground. VBOOST R2 T2 A2 12-/16-BIT DAC T1 A1 R3 LDAC IOUT DAC REGISTER INPUT REGISTER RSET INTERFACE LOGIC SDO Reference Buffers The AD5757/AD5737 can operate with either an external or internal reference. The reference input has an input range of 4 V Figure 15. Simplified Serial Interface of Input Loading Circuitryfor One DAC Channel Rev. PrD | Page 14 of 31 05303-062 Figure 14. Voltage to Current conversion circuitry SCLK SYNC SDIN Preliminary Technical Data REGISTERS Table 7 below shows an overview of the Registers for the AD5757/AD5737 Table 7. Data and Control Registers for AD5757/AD5737 DATA REGISTERS DAC Data Register (X4) Description Used to write a DAC code to each DAC channel. AD5757 Data bits (D15 to D0), AD5737 Data Bits (D15 to D4). There are four DAC Data Registers, one per DAC Channel. Used to program gain trim on per channel basis. AD5757 Data bits (D15 to D0), AD5737 Data Bits (D15 to D4). There are four Gain Registers, one per DAC channel. Used to program offset tro, on per channel basis. AD5757 Data bits (D15 to D0), AD5737 Data Bits (D15 to D4). There are four Offset Registers, one per DAC channel. AD5757/AD5737 Gain Register (X4) Offset Register (X4) Clear Code Register (X4) Used to program Clear Code on per channel basis. AD5757 Data bits (D15 to D0), AD5737 Data Bits (D15 to D4). There are four Clear Code Registers, one per DAC channel. Used to Configure the part for main operation. Sets functions such as status readback during write, enable output on all channels simultaneously, power on all DC-DC blocks simultaneously, enables and sets conditions of watchdog timer. See Features Section for more details. Has two functions. Used to perform a reset. Is also used as part of the watchdog timer feature to verify correct data communication operation. Use to program the slew rate of the output. There are four Slew Rate Control Registers, one per channel. These registers are used to control the following: 1) Set the output range, e.g. 4-20ma. 2) Set whether Internal/External sense Resistor used. 3) Enable/Disable channel for CLEAR. 4) Enable/Disable output on a per channel basis. 5) Power on DC-DC on a per channel basis. There are four DAC Control Registers, one per DAC channel. Use to set the DC-DC Control parameters. Can control DC-DC max voltage, phase and frequency. CONTROL REGISTERS Main Control Register Software Register Slew Rate Control Register (X4) DAC Control Register (X4) DC-DC Control Register READBACK Status Register Rev. PrD | Page 15 of 31 AD5757/AD5737 PROGRAMMING SEQUENCE TO WRITE/ENABLE THE OUTPUT CORRECTLY To correctly write to and set up the part from a power on condition the sequence below should be followed. It is recommended to perform a hardware or software reset after initial power on. Firstly, the DC-DC supply block needs to be configured. The user should set the DC-DC switching frequency, max output voltage allowed and the phase that the 4 DC-DC channels clock at. Secondly the DAC Control Register should be configured on a per channel basis. The output range is selected, and the DCDC block is enabled (DC-DC). Other control bits may be configured at this point, however, the output enable bit (OUTEN) and the INT_ENABLE bit should not be set. Next, the user writes the required code to the DAC Data Register. This will implement a full DAC calibration internally. Finally the user writes to the DAC Control Register again to enable the output (set the OUTEN bit). A flow chart of this sequence is shown below. Preliminary Technical Data CHANGING AND REPROGRAMMING THE RANGE When changing between ranges the same sequence as above should be used. It is recommended to set the range to its zero point (can be mid-scale or zeroscale) prior to disabling the output. As the DC-DC switching frequency, max voltage and phase have already been selected, there is no need to reprogram this. A flow chart of this sequence is shown below. Channels Output is enabled Step 1: Write to channels DAC Data Register, Set the output to 0V (zero or midscale). Step 2: Write to DAC Control Register. Disable the output (OUTEN=0), and set the new output range. Keep the DC-DC enabled, do not select the INT_Enable bit. Step 3: Write value to the DAC Data Register. Power On Step 1: Perform a Software/Hardware Reset Step 2: Write to DC-DC Control Register to set DC-DC Clock Frequency, phase and maximum voltage. Step 3: Write to DAC Control Register. Select the DAC Channel and output Range. Set the DC_DC bit and other control bits as required. Do not select OUTEN bit or the INT_ENABLE bit.. Step 4: Write to each/all DAC Data Registers. Step 5: Write to DAC Control Register. Reload sequence as in Step 3 above.This time select the OUTEN bit to enable the output. Figure 16. Programming Sequence for Enabling the Output Correctly Step 4: Write to DAC Control Register. Reload sequence as in Step 2 above.This time select the OUTEN bit to enable the output. Figure 17. Steps for Changing the Output Range Rev. PrD | Page 16 of 31 Preliminary Technical Data DATA REGISTERS The input register is 24 bits wide. When writing to a data register the following format must be used: Table 8. AD5757/AD5737 Writing to a Data Register D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0 R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 Table 9. AD5757/AD5737 Input Register Decode Register R/W Function Indicates a read from or a write to the addressed register. AD5757/AD5737 DUT_AD1, DUT_AD0 Used in association with External Pins AD1, AD0 to determine which AD5757/AD5737 device is being addressed by the system controller. DUT_AD1 0 0 1 1 DUT_AD0 0 1 0 1 Function Addresses Part with Pins AD1=0, Addresses Part with Pins AD1=0, Addresses Part with Pins AD1=1, Addresses Part with Pins AD1=1, AD0=0 AD0=1 AD0=0 AD0=1 DREG2, DREG1, DREG0 Selects whether a data register or a control register is written to. If a control register is selected, a further decode of CREG bits is required to select the particular control register, as detailed below. DREG2 0 0 0 1 1 1 1 DREG1 0 1 1 0 0 1 1 DAC_AD0 0 1 0 1 X DREG0 0 0 1 0 1 0 1 Function Write to DAC Data Register (Individual Channel Write) Write to Gain Register Write to Gain Register (ALL DACS) Write to Offset Register Write to Offset Register (ALL DACS) Write to Clear Code Register Write to a Control Register DAC Channel/ Register Address DAC A DAC B DAC C DAC D These are don’t cares if they are not relevant to the operation being performed. DAC_AD1, DAC_AD0 These bits are used to decode the DAC channel DAC_AD1 0 0 1 1 X DAC DATA REGISTER Table 10. Programming the AD5757 DAC Data Registers When writing to the AD5757 DAC Data Registers D15-D0 are used for DAC DATA bits. See Table x for input register decode. MSB D23 D22 R/W DUT_AD1 D21 DUT_AD0 LSB D20 D19 D18 D17 D16 D15 to D0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DATA Table 11. Programming the AD5737 DAC Data Registers When writing to the AD5737 DAC Data Registers D15-D4 are used for DAC DATA bits. See Table x for input register decode. MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D4 D3 D2 D1 D0 R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DATA X X X X Rev. PrD | Page 17 of 31 AD5757/AD5737 GAIN REGISTER Preliminary Technical Data The Gain Register stores the Gain Code (M) which is used in the DAC transfer function to calculated the overall DAC input code (see formula below). The Gain Register is addressed by setting DREG bits to ‘0,1,0’. The DAC address bits select which DAC channel the gain write is addressed to. It is possible to write the same gain code to all 4 DAC channels at the same time by setting the DREG bits to 011. The AD5757/AD5737 Gain Register is a 16/12 bit register (bits G15.. G0/G3) and allows the user to adjust the gain of each channel in steps of 1 LSB as shown in the Table below. For the AD5737, the last 4 bits should be set to 1. The Gain Register coding is straight binary. In theory the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is about 50% of programmed range in order to maintain accuracy. Table 12. Programming the AD5757 Gain Register R/W 0 R/W 0 DUT_ DUT_ AD1 AD0 DEVICE ADDRESS DUT_ DUT_ AD1 AD0 DEVICE ADDRESS DREG2 DREG1 010 DREG0 DAC_ DAC_ AD1 AD0 DAC Channel Address DAC_ DAC_ AD1 AD0 DAC Channel Address G13 1 1 0 0 G12 to G4 1 1 0 0 G4 1 0 1 0 D15-D0 G15 to G0 D15-D4 G15 to G4 G3 1 1 0 0 G3 X X X X X Table 13. Programming the AD5737 Gain Register DREG2 DREG1 010 DREG0 D3 1 G2 1 1 0 0 G2 X X X X X D2 1 D1 1 G1 1 0 0 0 G1 X X X X X D0 1 G0 1 0 1 0 G0 X X X X X Table 14. AD5757 Gain Register Gain Adjustment +65535 LSBs +65534 LSBs 1 LSBs 0 LSBs G15 1 1 0 0 G15 1 1 1 LSBs 0 LSBs 0 0 G14 1 1 0 0 G14 1 1 0 0 Table 15. AD5737 Gain Register Gain Adjustment +8192 LSBs +8191 LSBs G13 to G5 1 1 0 0 OFFSET REGISTER The Offset Register is addressed by setting the DREG BITS to DREG2 =1 DREG1=0, DREG0=0. The DAC address bits select with which DAC channel the offset write is addressed to. It is possible to write the same offset code to all 4 DAC channels at the same time by setting the DREG bits to 101. The AD5757/AD5737 offset code is 16/12 bit (bits OF15.. OF0/OF3) and allows the user to adjust the offset of each channel by −32768/8192 LSBs to +32767/8191 LSBs in steps of 1 LSB as shown in the Table below. For the AD5737, the last 4 bits are ignored and should be set to zero. The Offset Register coding is straight binary. The default code in the Offset Register is 0x8000/0x800. This will result in zero offset programmed to the output. Table 16. Programming the AD5757 Offset Register R/W 0 DUT_ DUT_ AD1 AD0 DEVICE ADDRESS DREG2 100 DREG1 DREG0 DAC_ DAC_ AD1 AD0 DAC Channel Address D15 to D0 OF15 to OF0 Table 17. Programming the AD5737 Offset Register R/W 0 DUT_ DUT_ AD1 AD0 DEVICE ADDRESS DREG2 100 DREG1 DREG0 DAC_ DAC_ AD1 AD0 DAC Channel Address Rev. PrD | Page 18 of 31 D15 to D4 OF15 to OF4 D3 0 D2 0 D1 0 D0 0 Preliminary Technical Data Table 18. AD5757 Offset Register options Offset Adjustment +32768 LSBs +32767 LSBs No Adjustment (default) −32767 LSBs −32768 LSBs Offset Adjustment +8192 LSBs +8191 LSBs No Adjustment (default) −8191 LSBs −8192 LSBs OF15 1 1 1 0 0 OF15 1 1 1 0 0 OF14 1 1 0 0 0 OF14 1 1 0 0 0 OF13 1 1 0 0 0 OF13 1 1 0 0 0 OF12 to OF4 1 1 0 0 0 OF12 to OF4 1 1 0 1 0 OF3 1 1 0 0 0 OF3 X X X X X X X OF2 1 1 0 0 0 OF2 X X X X X X X AD5757/AD5737 OF1 1 0 0 0 0 OF1 X X X X X X X OF0 1 0 0 0 0 OF0 X X X X X X X Table 19. AD5737 Offset Register options CLEAR CODE REGISTER There is a per channel Clear Code Register. The Clear Code Register is 16 bits wide and is addressed by setting the DREG bits to’1,1,0’. It is also possible, via software, to enable/disable on a per channel basis which channels will be cleared when the CLEAR pin is activated. The default clear code is all 0’s. See Features section for more information. Table 20. Programming AD5757 Clear Code Register D23 R/W 0 D22 DUT_AD1 D21 DUT_AD0 D20 DREG2 110 D19 DREG1 D18 DREG0 D17 DAC_AD1 D16 DAC_AD0 D15 to D0 CLEAR CODE DATA DEVICE ADDRESS DAC Channel Address Table 21. Programming the AD5737 Offset Register R/W 0 DUT_ AD1 DUT_ AD0 DREG2 110 DREG1 DREG0 DAC_ AD1 DAC_ AD0 D15 to D4 CLEAR CODE D3 0 D2 0 D1 0 D0 0 DEVICE ADDRESS DAC Channel Address Rev. PrD | Page 19 of 31 AD5757/AD5737 CONTROL REGISTERS When writing to a data register the following format must be used: Table 22. Writing to a control register Preliminary Technical Data MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12to D0 R/W DUT_AD1 DUT_AD0 1 1 1 DAC_AD1 DAC_AD0 CREG2 CREG1 CREG0 See Table 9 for configuration on bits D23 to D16. The control registers are addressed by setting the DREG bits to DREG2 = 1, DREG1 = 1, DREG0=1 and then setting the CREG2, CREG1 and CREG0 bits to the appropriate decode address for that register as per Table 23 below. These CREG bits select between the various control registers. Table 23. Register Access Decode CREG2, (D15) 0 0 0 0 1 CREG1, (D14) 0 0 1 1 0 CREG0, (D13) 0 1 0 1 0 Slew Rate Control Register (one per channel) Main Control Register DAC Control Register (one per channel) DC-DC Control Register Software Register (one per channel) MAIN CONTROL REGISTER CREG2, CREG1, CREG0 are set to ‘0,0,1’ to select the Main Control Register. The Main Control Register options are shown below. Table 24. Programming the Main Control Register MSB D15 0 LSB D14 0 D13 1 D12 0 D11 STATREAD D10 EWD D9 WD1 D8 WD0 D7 X D6 X D5 OUTEN ALL D4 DC-DC ALL D3 to D0 X Table 25. Main Control Register Functions. Option STATREAD Description Enable status readback during a write. See Features section. STATREAD =1, Enable STATREAD =0, Disable Enable Watchdog Timer. See features section for more information. EWD=1, Enable Watchdog EWD=0, Disable Watchdog Timeout Select Bits. Used to select timeout period for watchdog timer. WD1 WD0 0 0 5ms 0 1 10ms 1 0 100ms 1 1 200ms Enables the output on all 4 DAC simultaneously. Do not use the OUTEN ALL bit when using the OUTEN bit in the DAC Control Registers. When set, Powers up the DC-DC on all 4 channels Simultaneously. To Power down the DC-DCs all channels outputs must first be disabled. Do not use the DC_DCALL bit when using the DC_DC bit in the DAC Control Registers. EWD WD1, WD0 OUTEN ALL DC_DCALL DAC CONTROL REGISTER The DAC Control Register is used to configure each DAC Channel. The DAC Control Register is selected by setting bits CREG2, CREG1, CREG0 to 0,1,0. Rev. PrD | Page 20 of 31 Preliminary Technical Data Table 26. Programming DAC Control Register D15 0 D14 1 D13 0 D12 X D11 X D10 X D9 X D8 INT_ENABLE D7 CLR_EN D6 OUTEN D5 RSET D4 DC-DC D3 X D2 R2 AD5757/AD5737 D1 R1 D0 R0 Table 27. DAC Control Register Functions Option INT_ENABLE CLR_EN Description Powers up the DC-DC, DAC and internal amplifiers for the selected channel. Does not enable the output. Can only be done on a per channel basis. Per channel Clear Enable bit. Selects if this channel will clear when the CLEAR pin is activated. CLR_EN=1, channel will clear when part is cleared. CLR_EN=0, channel will not clear when part is cleared. Enables/Disables the selected output channel OUTEN=1, Enables channel OUTEN=0, Disable channel Selects internal or external current sense resistor for selected DAC channel RSET = 0 Selects external Resistor RSET = 1 Selects Internal Resistor Powers the DC-DC on selected channel. DC_DC = 1, Power up DC_DC DC_DC = 0, Power down DC_DC This allows per channel DC_DC power up/down. To power down the DCDC, OUTEN and INT_ENABLE bits must also be set to 0. All DC-DCs can also be powered up simultaneously using DCDC_All bit in the Main Control Register. Selects output range enabled. R2 1 1 1 R1 0 0 1 R0 0 1 0 Output Range Selected 4 to 20 mA Current Range 0 to 20 mA Current Range 0 to 24 mA Current Range OUTEN RSET DC_DC R2,R1,R0 SOFTWARE REGISTER The Software Register has three functions. It allows the user to perform a software reset to the part. It can be used to set bit D11 in the Status Register. Lastly it is also used as part of the watchdog feature to ensure that the SPI interface connections are working properly. To ensure all the datapath lines are working properly (i.e. SDI/SCLK/SYNC), the user must write 0x195 to the Software Register within the timeout period. If this command is not received within the timeout period, the ALERT pin will signal a fault condition. Note. This is only required when the Watchdog Timer function is enabled. Table 28. Programming the Software Register To program a software reset you need to write 1,0,0 to CREG2, CREG1, CREG0. MSB D15 1 D14 0 D13 0 D12 User Program Bit LSB D11 to D0 RESET CODE/SPI CODE Table 29. Software Register Functions User Program Bit This bit is mapped to bit D11 of the Status Register. When this bit is set to 1 bit D11 of the Status Register is set to 1. Likewise when D12 is set to 0 bit D11 of the Status Register is also set to zero. This feature can be used to ensure the SPI pins are working correctly by writing known bit to this register and reading back corresponding bit from the Status Register. Option RESET CODE SPI CODE Description Writing 0x555 to D11-D0 performs a reset. If Watchdog Timer feature enabled, 0x195 must be written to the Software Register (D11-D0) within every timeout period to ensure valid data communication path. RESET CODE/SPI CODE Rev. PrD | Page 21 of 31 AD5757/AD5737 DC-DC CONTROL REGISTER Preliminary Technical Data The DC-DC Control Register allows the user control over the DC-DC Switching Frequency, and of the phase of when the per channel switching starts. The maximum allowable DC-DC output frequency is also programmable. Table 30. Programming the DC-DC Control Register MSB D15 0 D14 1 D13 1 D12 to D7 X D5 to D4 DC-DC Phase D3 to D2 DC-DC Freq LSB D1 to D0 DC-DC MaxV Table 31. DC-DC Control Register Options Option DC-DC Phase Description User Programmable DC-DC Phase (Between Channels) 00 = All DC-DCs clock on same edge 01 = ChanA, ChanB clock on same edge, ChanC & ChanD clock on opposite edge 10 = ChanA, ChanC clock on same edge, ChanB & ChanD on opposite edge 11 = ChanA,ChanB,ChanC, ChanD clock 90' out of phase from each other DC-DC Freq User Programmable DC-DC Switching Frequency: 00 = 250 Khz 01 = 406 Khz 10 = 649 Khz 11 = 812 Khz Maximum allowed output Voltage of the DC-DC 00 = 25V ±1V 01 = 27.3 ±1V 10 = 28.6 ±1V 11 = 30 ±1V DC-DCMaxV SLEW RATE CONTROL REGISTER This register is used to program the slew rate control for the selected DAC Channel. The CREG bits are set to ‘0,0,0’ to select the Slew Rate Control Register. SR_CLOCK and SR_STEP allow the user to control the rate of the output SLEW. With the slew rate control feature disabled the output value will change at a rate limited by the output drive circuitry and the attached load. SE enables output slew rate control. It can be both programmed and enabled/disabled on a per channel basis. For more information see the features section. Table 32. Programming the Slew Rate Control Register D15 0 D14 0 D13 0 D12 SE D11-D7 X D6 to D3 SR_CLOCK D2 to D0 SR_STEP Rev. PrD | Page 22 of 31 Preliminary Technical Data READBACK OPERATION AD5757/AD5737 Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, bits DUT_AD1, DUT_AD0, in association with bits RD4, RD3, RD2, RD1, RD0 (See Table 34), select the register to be read. The remaining data bits in the write sequence are don’t care. During the next SPI transfer, the data appearing on the SDO output contains the data from the previously addressed register. The readback diagram in Figure 3 shows the readback sequence. Table 33. Input Shift Register Contents for a read operation D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0 X R/W DUT_AD1 DUT_AD0 RD4 RD3 RD2 RD1 RD0 Table 34. Read Address Decoding RD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 RD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 RD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 RD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 RD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Function Read DACA Data Register Read DACB Data Register Read DACC Data Register Read DACD Data Register Read Control Register DAC A Read Control Register DAC B Read Control Register DAC C Read Control Register DAC D Read Gain Register A Read Gain Register B Read Gain Register C Read Gain Register D Read Offset Register A Read Offset Register B Read Offset Register C Read Offset Register D Clear Code Register DAC A Clear Code Register DAC B Clear Code Register DAC C Clear Code Register DAC D Slew Rate Control Register DAC A Slew Rate Control Register DAC B Slew Rate Control Register DAC C Slew Rate Control Register DAC D Read Status Register Read Main Control Register Read DC-DC Control Register Read Back Example To read back the Gain Register of Device #1 Channel A on the AD5757, the following sequence should be implemented: 1. Write 0xA80000 to the AD5757 input register. This configures the AD5757 device address #1 for read mode with the Gain Register of channel A selected.. Note that all the data bits, D15 to D0, are don’t care. 2. Follow this with any read/write command. During this command, the data from the selected Gain Register is clocked out on the SDO line. Rev. PrD | Page 23 of 31 AD5757/AD5737 Preliminary Technical Data STATUS REGISTER The Status Register is a read only register. This register contains any fault information as a well as a RAMP ACTIVE bit and a User Toggle Bit. By setting the STATREAD bit in the Main Control Register, the Status Register contents can be readback on the SDO pin during every write sequence. Table 35. Decoding the Status Register MSB D15 to D12 X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 DCDCD DCDCC DCDCB DCDCA User Toggle Bit PEC ERROR RAMP ACTIVE OVER TEMP X X X X OPEN CCT ID OPEN CCT IC OPEN CCT IB OPEN CCT IA Table 36. Status Register Options Option DC-DCD DC-DCC DC-DCB DC-DC A User Toggle Bit PEC ERROR OVER TEMP RAMP ACTIVE OPEN CCT ID OPEN CCT IC OPEN CCT IB OPEN CCT IA Description DC-DC Failure on Channel D. This fault indicates that the DCDC is not operating, for example if the boost inductor is not connected. DC-DC Failure on Channel C. This fault indicates that the DCDC is not operating, for example if the boost inductor is not connected. DC-DC Failure on Channel B. This fault indicates that the DCDC is not operating, for example if the boost inductor is not connected. DC-DC Failure on Channel A. This fault indicates that the DCDC is not operating, for example if the boost inductor is not connected. User Writable bit that the user can set and readback while doing a Status Register read. This can be used to verify data communications if needed. Denotes a PEC Error on the SPI Interface Transmit. This bit will be set if the AD5757/AD5737 core temperature exceeds approx. 150°C. This bit will be set while any one of the output channels are slewing (slew rate control enabled on at least one channel) This bit will be set if a fault is detected on DACD IOUT pin. This bit will be set if a fault is detected on DACC IOUT pin. This bit will be set if a fault is detected on DACB IOUT pin. This bit will be set if a fault is detected on DACA IOUT pin. Rev. PrD | Page 24 of 31 Preliminary Technical Data FEATURES OUTPUT FAULT The AD5757/AD5737 is equipped with a FAULT pin, this is an active low open-drain output allowing several AD5757/AD5737 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault scenarios; 1) The Voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with “window limits” since this would require an actual output error before the FAULT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately one volt of remaining drive capability. Thus the FAULT output activates slightly before the compliance limit is reached. Since the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain and an output error does not occur before the FAULT output becomes active. An interface error is detected due to a PEC failure. See Packet Error Checking section. If the core temperature of the AD5757/AD5737 exceeds approx. 150°C. AD5757/AD5737 and they are shared among all 4 channels. This has implications for the update speed when several channels are updated at once. Each time data is written to the M or C register the output is not automatically updated. Rather, the next write to the DAC channel will use these M&C values to perform a new calibration and automatically update the channel. Data output from the DAC2 register is routed to the final DAC register by a multiplexer. Both the Gain Register and the Offset Register have 16 bits of resolution. The correct method to calibrate the gain/offset is firstly to calibrate out the gain and then calibrate the offset. The value (in decimal) that is written to the DAC register can be calculated by: Code DAC Re gister = D × ( M + 1) + C − 215 216 where: D is the code loaded to the DAC channels input register. M is the code in Gain Register − default code = 216 – 1 C is the code in Offset Register − default code = 215 2) 3) STATUS READBACK DURING WRITE The AD5757/AD5737 has the ability to read back the Status Register contents during every write sequence. This feature is enabled via the STATREAD bit in the Main Control Register. This allows the user to continuously monitor the Status Register and act quickly in the case of a fault. When Status Readback During Write is enabled the contents of the 16bit Status register (See Table 36) is outputted on the SDO pin as indicated in Figure 4. The AD5757/AD5737 will power up with this feature disabled. When this is enabled the normal readback feature is not available, except of the status register. To readback any other register set STATREAD low first before following the readback sequence. STATREAD may be set high again after the register read. The OPEN CCT and OVER TEMP bits of the Status Register are used in conjunction with the FAULT output to inform the user which one of the fault conditions caused the FAULT output to be activated. DIGITAL OFFSET AND GAIN CONTROL Each DAC channel has a gain (M) and offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the DAC Data Register is operated on by a digital multiplier and adder controlled by the contents of the M and C registers. The calibrated DAC data is then stored in the DAC2 register. INPUT REGISTER DAC REGISTER ASYNCHRONOUS CLEAR CLEAR is an active high edge sensitive input that allows the output to be cleared to a pre programmed 16 bit code. This code is user programmable via a per-channel 16 bit Clear Code Register. In order for a channel to clear, that channel must be enabled to be cleared via the CLR_EN bit in the channels DAC Control Register. If the channel is not enabled to be cleared then the output will remain in its current state independent of the CLEAR pin level. DAC M REGISTER C REGISTER Figure 18. Digital Offset and Gain control Although this diagram indicates a multiplier and adder for each channel, there is only one multiplier and one adder in the device, Rev. PrD | Page 25 of 31 AD5757/AD5737 When the CLEAR signal is returned low, the relevant outputs remains cleared until a new value is programmed. Preliminary Technical Data INTERNAL REFERENCE The AD5757/AD5737 contains an integrated +5V voltage reference with initial accuracy of ±2mV max and a temperature drift coefficient of ±5 ppm max. The reference voltage is buffered and externally available for use elsewhere within the system. PACKET ERROR CHECKING To verify that data has been received correctly in noisy environments, the AD5757/AD5737 offers the option of packet error checking based on an 8-bit (CRC-8) cyclic redundancy check. The device controlling the AD5757/AD5737 should generate an 8-frame check sequence using the polynomial EXTERNAL CURRENT SETTING RESISTOR Referring toFigure 14, R1 is an internal sense resistor as part of the voltage to current conversion circuitry. The stability of the output current value over temperature is dependent on the stability of the value of R1. As a method of improving the stability of the output current over temperature an external 15kΩ low drift resistor can be connected to the RSET pin of the AD5757/AD5737 to be used instead of the internal resistor R1. The external resistor is selected via the DAC Control register. See Table 26. C ( x) = x8 + x2 + x1 + 1 This is added to the end of the data word, and 32 bits are sent to the AD5757/AD5737 before taking SYNC high. If the AD5757/AD5737 sees a 32-bit frame, it will perform the error check when SYNC goes high. If the check is valid, then the data will be written to the selected register. If the error check fails, the FAULT pin will go low and the PEC ERROR bit in the Status Register will be set. After reading the Status Register, FAULT will return high (assuming there are no other faults) and the PEC ERROR bit will be cleared automatically. The PEC can be used for both transmit and receive of data packets. If Status Readback During Write is enabled, the ‘PEC’ values returned during the Status Readback During Write should be ignored. All other PEC values will be valid though and the user can still use the normal readback operation to monitor Status Register activity.with PEC. HART The AD5757/AD5737 has 4 CHART pins, one corresponding to each output channels. A HART signal can be coupled into these pins. The HART signal will appear on the corresponding current output, if the output is enabled. Table 37 below shows the recommended input voltages for the HART signal at the CHART pin. If these voltages are used the current output should meet the HART amplitude specifications. Figure 19 is the recommended circuit for attenuating and coupling in the HART signal. Table 37. CHART input voltage to HART output current Internal Rset External Rset CHART input voltage 150mVp-p 170mVp-p C1 WATCHDOG TIMER If enabled, an on chip watchdog timer will generate an alert signal if 0x195 has not been written to the Software Register within the programmed timeout period. This feature is useful to ensure communication has not been lost between the MCU and the AD5757/AD5737 and that these datapath lines are working properly (i.e. SDI/SCLK/SYNC). If 0x195 is not received by the Software Register within the timeout period, the ALERT pin will signal a fault condition. The ALERT signal is active high and can be connected directly to the CLEAR pin to enable a CLEAR in the event that data communications are lost from the MCU. The watchdog timer is enabled and the timeout period (50,100,150 or 200ms) set in the control register (See Table 24). Current output (HART) 1mAp-p 1mAp-p CHART HART modem output C2 Figure 19. Coupling HART signal OUTPUT ALERT The AD5757/AD5737 is equipped with a ALERT pin, this is An active high CMOS output. The AD5757/AD5737 has an internal watchdog timer. If enabled, it will monitor SPI communications. If 0x195 is not received by the Software Register within the timeout period, the ALERT pin will go active. A minimum capacitance of C1+C2 will be required to ensure that the 1.2kHz and 2.2kHz “HART frequencies” are not significantly attenuated at the output. This will be in the order of 10’s of nF’s. Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART. SLEW RATE CONTROL The Slew Rate Control feature of the AD5757/AD5737 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. With the slew rate control feature disabled the output value will change at a rate limited by the output drive circuitry and the attached load. If the user wishes to reduce the slew rate Rev. PrD | Page 26 of 31 Preliminary Technical Data this can be achieved by enabling the slew rate control feature. With the feature enabled via the SREN bit of the Slew Rate Control Register, (See Table 32) the output, instead of slewing directly between two values, will step digitally at a rate defined by two parameters accessible via the Slew Rate Control Register as shown in Table 32. The parameters are SR_CLOCK and SR_STEP. SR_CLOCK defines the rate at which the digital slew will be updated, e.g. if the selected update rate is 8KHz the output will update every 125µs, in conjunction with this the SR_STEP defines by how much the output value will change at each update. Together both parameters define the rate of change of the output value. Table 38 and Table 39 outline the range of values for both the SR_CLOCK and SR_STEP parameters. Table 38. Slew Rate Update Clock Options SR_CLOCK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Update Clock Frequency (Hz)* 64K 32K 16K 8k 4k 2k 1k 500 250 125 64 32 16 8 4 0.5Hz AD5757/AD5737 Slew Time = Where: Slew T ime is expressed in seconds Output Change is expressed in Amps W hen the slew rate control feature is enabled, all output changes will change at the programmed slew rate, for example if the CLEAR pin is asserted the output will slew to the clear value at the programmed slew rate (assuming that Clear channel is enabled to be cleared). T he update clock frequency for any given value will be the same for all output ranges, the step size however will vary across output ranges for a given value of step size as the LSB size will be different for each output range. Output Change Step Size × Update Clock Frequency × LSB Size POWER DISSIPATION CONTROL The AD5757/AD5737 contains integrated dynamic power control using a DC-DC boost circuiot allowing reductions in power consumption from standard designs when using the part in current output mode. In standard current input module designs the load resistor values can range from typically 50 ohm to 750 ohm. Output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. For example, in a 4-20ma loop when driving 20ma a compliance voltage of >15V is required. When driving 20ma into a 50 ohm load only 1V compliance is required. The AD5757/AD5737 circuitry senses the output voltage and regulates this voltage to meet compliance requirements plus a small headroom voltage. DC-DC CONVERTERS The AD5757/AD5737 contains 4 independent DCDC converters. These are used to provide dynamic control of the Vboost supply voltage for each channel (See Figure 14). Figure 20 below shows the discreet components needed for the DCDC circuitry and the following sections describe component selection for this circuitry. AVcc L DCDC D DCDC C DCDC SW_x Figure 20. DC-DC Circuit *Clock Frequencies accurate to ±TDB%. Table 39. Slew_Rate Step Size Options SR_STEP 000 001 010 011 100 101 110 111 AD5737 (12 BIT) Step Size (LSBs) 1/16 1/8 1/4 ½ 2 4 8 16 AD5757 (16 BIT) Step Size (LSBs) 1 2 4 16 32 64 128 256 Vboost_x DC-DC Operation The on-board DC-DC converters use a constant frequency, peak current mode control scheme to step-up an AVcc input in the range 2.7 to 5.5v to drive the AD5757/AD5737 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle < 85%. The following equation describes the slew rate as a function of the step size, the update clock frequency and the LSB size. Rev. PrD | Page 27 of 31 AD5757/AD5737 Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable % of the switching cycle. The DCDC converters are non synchronous i.e. they require an external schottky diode. Preliminary Technical Data η = efficiency (Assume = 0.8) DC-DC External schottky selection The AD5757/AD5737 requires an external schottky for correct operation. Ensure the schottky is rated to handle the the maximum reverse breakdown expected in operation & that the rectifier maximum junction temperature is not exceeded. The diode average current = Iload current. DC-DC Output Voltage When a channel current output is enabled the converter regulates the Vboost supply to 7.5V or (Iout*Rload+2V), whichever is greater. The maximum Vboost voltage is set in the DC-DC Control Register (25, 27.3, 28.6 or 30V. See Table 31). DC-DC Compensation Capacitors As the DCDC operates in DCM the uncompensated transfer function is essentially a single pole transfer function. The pole frequency is determined by Cout, Vin, Vout & Iload. The AD5757/AD5737 uses an external capacitor in conjunction with an internal 150k resistor to compensate the regulator loop. For typical 4-20mA applications connect a 10nF capacitor from each of the COMPDCDC_A/_B/_C/_D pins to GND. DC-DC On-Board Switch The AD5757/AD5737 contains a 0.5ohm internal switch . The switch current is monitored on a pulse by pulse basis & is limited to 0.8A peak current. DC-DC Switching Frequency and Phase The AD5757/AD5737 DCDC switching frequency can be selected from the DCDC Control Register to be 250Khz, 400Khz, 649kHz or 812kHz. The phasing of the channels can also be adjusted so that the DCDCs can clock on different edges (See Table 31). For typical applications a 250Khz frequency is recommended. At light loads (low output current & small load resistor) the DCDC enters a pulse skipping mode to minimize switching power dissipation. DC-DC Input and Output Capacitor Selection The output capacitor effects ripple voltage of the DCDC converter & also indirectly limits the maximum slew rate at which the channel output current can rise. The ripple voltage is caused by a combination of the capacitance & ESR (equivalent series resistance) of the capacitor. For the AD5757/AD5737 a ceramic capacitor of 4.7µF is recommended for typical applications. Larger capacitors or paralled capacitors will improve the ripple at the expense of reduced slew rate. The input capacitor will provide much of the dynamic current required for the DCDC converter & should also be a low ESR component. For the AD5757/AD5737 a ceramic capacitor of 10µF is recommended for typical applications. Ceramic capacitors must be chosen carefully as they can exhibit a large sensitivity to DC bias voltages & temperature. X5R or X7R dielectrics are preferred as these capacitors remain stable over wider operating voltage & temperature ranges. DC-DC Inductor Selection For typical 4-20mA applications a 10uH inductor combined with a switching frequency of 250Khz will allow up to 24mA to be driven into a load resistance of up to 1kΩ with an AVcc supply from 2.7 to 5.5v. The inductor must be able to handle the peak current without saturating at the maximum ambient temperature. If an alternative Inductor/Switching frequency is preferred then one must ensure that the DCDC continues to operates in DCM mode and that the inductor current is less than 0.8A. 2 × I OUT max (VOUT max − VCC min ) I PEAK max × FSW 2 Iout Slew Rate when using the DC-DC When the AD5757/AD5737 is configured in Iout mode & a step increase in output current is programmed then the DCDC converter must increase its output voltage so that Vboost ≈ Iout*Rload+2v. This requires that the output capacitor of the DCDC circuit must also be charge to the new voltage. The amount of power required to do this is 0.5*C*(Vnew-Vold). Figure 7. And Figure 8.show Iout settling for a 0 to 24mA step into a 1kohm load for different caps & inductor/switching frequency.