a
Mixed-Signal Front-End (MxFE™) Processor
for Broadband Communications
AD9860/AD9862*
FEATURES
Mixed-Signal Front-End Processor with Dual Converter
Receive and Dual Converter Transmit Signal Paths
Receive Signal Path Includes:
Two 10-/12-Bit, 64 MSPS Sampling A/D Converters
with Internal or External Independent References,
Input Buffers, Programmable Gain Amplifiers,
Low-Pass Decimation Filters, and a Digital Hilbert Filter
Transmit Signal Path Includes:
Two 12-/14-Bit, 128 MSPS D/A Converters with
Programmable Full-Scale Output Current, Channel
Independent Fine Gain and Offset Control, Digital
Hilbert and Interpolation Filters, and Digitally Tunable
Real or Complex Up-Converters
Delay-Locked Loop Clock Multiplier and Integrated
Timing Generation Circuitry Allow for Single Crystal
or Clock Operation
Programmable Output Clocks, Serial Programmable
Interface, Programmable Sigma-Delta, Three Auxiliary
DAC Outputs and Two Auxiliary ADCs with Dual
Multiplexed Inputs
APPLICATIONS
Broadband Wireless Systems
Fixed Wireless, WLAN, MMDS, LMDS
Broadband Wireline Systems
Cable Modems, VDSL, PowerPlug
Digital Communications
Set-Top Boxes, Data Modems
GENERAL DESCRIPTION
The AD9860 and AD9862 (AD9860/AD9862) are versatile
integrated mixed-signal front-ends (MxFE) that are optimized
for broadband communication markets. The AD9860/AD9862
are cost effective, mixed signal solutions for wireless or wireline
standards based or proprietary broadband modem systems where
dynamic performance, power dissipation, cost, and size are all
critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs;
the AD9862 has 12-bit ADCs and 14-bit DACs.
The AD9860/AD9862 receive path (Rx) consists of two channels
that each include a high performance, 10-/12-bit, 64 MSPS analogto-digital converter (ADC), input buffer, Programmable Gain
Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The
Rx can be used to receive real, diversity, or I/Q data at baseband or
low IF. The input buffers provide a constant input impedance for
both channels to ease impedance matching with external components (e.g., SAW filter). The RxPGA provides a 20 dB gain
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
PGA
1x
ADC
RxA DATA
[0:11]
BYPASSABLE LOW-PASS
DECIMATION FILTER
VIN+B
1x
PGA
ADC
VIN–B
SIGDELT
HILBERT
FILTER
RxB DATA
[0:11]
LOGIC LOW
-
AD9860/AD9862
AUX_DAC_A
AUX DAC
AUX_DAC_B
AUX DAC
AUX_DAC_C
AUX DAC
SPI REGISTERS
Rx PATH
TIMING
Tx PATH
TIMING
AUX_ADC_A1
CLOCK
DISTRIBUTION
BLOCK
DLL
1, 2, 4
SPI
INTERFACE
OSC1
OSC2
AUX ADC
AUX_ADC_A2
AUX_ADC_B1
CLKOUT1
AUX ADC
AUX_ADC_B2
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
IOUT+A
IOUT–A
PGA
DAC
PGA
DAC
HILBERT
FILTER
IOUT+B
IOUT–B
CLKOUT2
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
FS/4
FS/8
BYPASSABLE
LOW-PASS
INTERPOLATION
FILTER
Tx DATA
[0:13]
NCO
range for both channels. The output data bus can be multiplexed to accommodate a variety of interface types.
The AD9860/AD9862 transmit path (Tx) consists of two channels that contain high performance, 12-/14-bit, 128 MSPS
digital-to-analog converters (DAC), programmable gain amplifiers
(TxPGA), interpolation filters, a Hilbert filter, and digital mixers
for complex or real signal frequency modulation. The Tx latch
and demultiplexer circuitry can process real or I/Q data. Interpolation rates of 2 and 4 are available to ease requirements on
an external reconstruction filter. For single channel systems, the
digital Hilbert filter can be used with an external quadrature
modulator to create an image rejection architecture. The two
12-/14-bit, high performance DACs produce an output signal
that can be scaled over a 20 dB range by the TxPGA.
REV. 0
A programmable delay-locked loop (DLL) clock multiplier and
integrated timing circuits enable the use of a single external
reference clock or an external crystal to generate clocking for all
internal blocks and also provides two external clock outputs.
Additional features include a programmable sigma-delta output,
four auxiliary ADC inputs and three auxiliary DAC outputs.
Device programmability is facilitated by a serial port interface
(SPI) combined with a register bank. The AD9860/AD9862 is
available in a space saving 128-lead LQFP.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
*Protected by U.S.Patent No. 5,969,657.
MxFE is a trademark of Analog Devices, Inc.
= 3.3 V 5%, V = 3.3 V 10%, f = 128 MHz, f = 64 MHz
Timing Mode, 2 DLL Setting, R = 4 k, 50 DAC Load,
AD9860/AD9862–SPECIFICATIONS (VNormal
RxPGA = +6 dB Gain, TxPGA = +20 dB Gain.)
A
D
DAC
ADC
SET
Tx PARAMETERS
Temp
Test
Level
Min
AD9860/AD9862
Typ
Max
Unit
12-/14-BIT DAC CHARACTERISTICS
Resolution
Maximum Update Rate
Full-Scale Output Current
Gain Error (Using Internal Reference)
Offset Error
Reference Voltage (REFIO Level)
Negative Differential Nonlinearity (–DNL)
Positive Differential Nonlinearity (+DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 6 MHz Tone
Crystal and OSC IN Multiplier Enabled at 4
Output Voltage Compliance Range
Full
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
I
I
I
I
III
III
III
III
25ºC
Full
III
II
TRANSMIT TxPGA CHARACTERISTICS
Gain Range
Step Size Accuracy
Step Size
25ºC
25ºC
25ºC
III
III
III
Tx DIGITAL FILTER CHARACTERISTICS
Hilbert Filter Pass Band ( 1 MW.
The RxPGA stage can provide up to a 2 V p-p signal to the
ADC input.
Analog-to-Digital (A/D) Converter
The analog-to-digital converter (ADC) stage consists of two
high performance 10-/12-bit, 64 MSPS analog-to-digital (A/D)
converters. The dual A/D converter paths are fully independent,
except for a shared internal bandgap reference source, VREF. Each
of the A/D converter’s paths consists of a front-end sample and
hold amplifier followed by a pipelined, switched capacitor, A/D
converter. The pipelined A/D converter is divided into three sections,
consisting of a 4-bit first stage followed by eight 1.5-bit stages and
a final 3-bit flash. Each stage provides sufficient overlap to correct
for flash errors in the preceding stages. The quantized outputs
from each stage are combined into a final 12-bit result through
a digital correction logic block. The pipelined architecture permits
the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the
rising clock edge.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash A/D connected to a switched capacitor DAC and
interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the
flash input for the next stage in the pipeline. One bit of redundancy
is used in each one of the stages to facilitate digital correction of
flash errors. The last stage simply consists of a flash A/D.
A stable and accurate 1.0 V bandgap voltage reference is built into
the AD9860/AD9862 and is used to set a 2 V p-p differential input
range. The internally generated reference should be decoupled
at the VREF pin using a 10 mF and a 0.1 mF capacitor in parallel
to ground. Separate top and bottom references, VRT and VRB,
for each converter are generated from VREF and should also be
decoupled. Recommended decoupling for the top and bottom
references consists of using 10 mF and 0.1 mF capacitors in parallel
between the differential reference pins, and a 0.1 mF capacitor
–22–
REV. 0
AD9860/AD9862
from each to ground. The internal references can also be disabled
(powered down) and driven externally to provide a different input
voltage range or low drift reference. If an external VREF reference
is used, it should not exceed 1.0 V.
A Shared Reference mode allows the user to connect the differential references from both ADCs together externally for superior
gain matching performance. If the ADCs are to function independently, then the reference can be left separate and will provide
superior isolation between the dual channels. Shared Reference
mode can be enabled through the Shared Ref register.
A power-down option allows the user to power down both ADCs
(sleep mode) or either ADC individually to reduce power
consumption.
Decimation Stage
For signals with maximum frequencies less than or equal to 3/16 the
ADC sampling rate, fADC, the decimate by 2 filter (or half-band
filter) can be used to provide on-chip suppression of out-of- band
images and noise. When data is present in frequencies greater
than 1/4 fADC, the decimate by 2 filter can be disabled by switching
the filter out of the circuit. The decimation filter allows the ADC
to oversample the input while decreasing the output data rate by
half. The two main benefits are a simplification of the input antialiasing filter and a slower data interface rate with the external
digital ASIC. The decimation filter is an 11 tap filter and suppresses
out of band noise by 38 dB.
Hilbert Block
The Hilbert filter is available to provide a Hilbert Transform of the
data from the ADC in Channel B. The Digital Hilbert Transform,
in combination with an external complex downconverter, enables
a receive image rejection architecture (similar to Hartley image
rejection architecture). The Hilbert filter pass-band (< 0.1 dB
ripple) is between 25% to 75% of the Nyquist rate of its input data
rate. The maximum data rate of the Rx Hilbert filter is 32 MSPS.
At ADC rates higher than this, the decimation filters should be
enabled. The Hilbert filter transfer function plots are shown in
Figure 7.
0
MAGNITUDE – dB
–40
The output data from the dual ADCs can be multiplexed onto
a single 10-/12-bit output bus. The multiplexing is synchronized
using the RxSYNC output pin that indicates which channel data
is on the output bus.
RECEIVE APPLICATIONS SECTION
The AD9860/AD9862 receive path (Rx) includes two high speed,
high performance, 10-/12-bit ADCs. Figure 6 shows a detailed
block diagram of the Rx data path and can be referred to throughout the explanation of the various modes of operation. The various
Rx modes of operation are broken into three parts determined by
the type of input signal:
1. Single Channel ADC Signal
2. Dual Channel Real ADC Signal (diversity or dual channel)
3. Dual Channel Complex ADC Signal (I and Q or Single
Sideband).
Each one of these parts is further divided into two cases, sampling
input signals up to Nyquist of the ADC (Nyquist sampling) and
sampling at rates above ADC Nyquist rate (IF sampling or
undersampling).
The AD9860/AD9862 uses oversampling and decimation filters to
ease requirements on external filtering components. The decimation filters (for both receive paths) can be used or bypassed so as
to accommodate different signal bandwidths and provide different
output data rates to allow easy integration with several different
data processing schemes.
Nonbaseband data can be used in an effort to avoid the dc offsets
in the receive signal path that can cause errors. By receiving
nonbaseband data, the requirements of external filtering may be
greatly reduced.
In each of the different receive modes, the input buffer, Programmable Gain Amplifier (RxPGA), and output multiplexer remain
within the receive path.
Single Channel ADC Signal
In this mode, a single input signal to be digitized is connected to
the differential input pins, VIN+A and VIN–A. The 10-/12-bit
output Rx data is latched using either CLKOUT1 or CLKOUT2
edges as defined in the Clock Overview section. The Rx path
available options include bypassing the input buffer, Rx PGA
control and using the Decimation Filter. By default, both Rx paths
are enabled and the unused one should be powered down using
the appropriate bit in the Rx Power-Down register, d1.
The input buffer description above explains the conditions under
which the buffer should be bypassed.
–80
–120
–0.5
If the input signal, or the undersampled alias signal for the
IF sampling case, falls below 40% of the ADC Nyquist rate, the
decimation filter can be enabled to suppress out-of-band noise and
spurious signals by 40 dB or more. With the decimation filter
enabled, the SNR of the Rx path improves by about 2.3 dB.
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
NORMALIZED – fS
Figure 7. Rx Hilbert Filter, Keeping Positive Frequencies
Response
Data Output Multiplexer Stage
The Rx data output format can be configured for either twos
complement or offset binary. This is controlled by the Rx Twos
Complement register.
REV. 0
Dual Channel Real ADC Signal
The Dual Channel Real ADC Signal mode is used to receive
diversity signals or dual independent channel signals that will be
processed independent of each other. In this mode, the two input
signals to be digitized are connected to the differential input pins
of the AD9860/AD9862, VIN+A, VIN–A, VIN+B, and VIN–B.
The two 10-/12-bit Rx outputs can be either interleaved onto a
single 10-/12-bit bus or output in parallel on two 10-/12-bit buses.
–23–
AD9860/AD9862
The output will be latched using some configuration of CLKOUT1
or CLKOUT2 edges as defined in the Clock Overview section of
the data sheet. The Rx path available options include bypassing
the input buffer, RxPGA control and using the decimation filter.
An internal Delay Lock Loop (DLL) based clock multiplier provides a low noise, 2 or 4 multiplication of the input clock over
an output frequency range of 32 MHz to 128 MHz. The DLL
Fast register should be used to optimize the DLL performance.
For DLL output frequencies between 32 MHz and 64 MHz, this
bit should be set low. For output frequencies between 64 MHz
to 128 MHz, the Fast bit should be set high (for a 64 MHz output frequency, the register can be set either high or low). The DLL
can be bypassed by setting a 1 multiplication factor in the DLL
Multiplier register. The DLL can be powered down when it is
bypassed for power savings by setting the DLL PwrDwn register.
The input buffer description above explains the conditions under
which the buffer should be bypassed.
If the input signal, or the undersampled alias signal for the
IF sampling case, falls below 40% of the ADC Nyquist rate, the
decimation filter can be enabled to suppress out-of-band noise
and spurious signals by 40 dB or more. With the decimation
filter enabled the SNR of the Rx path improves by about 2.3 dB.
Dual Channel Complex ADC Signal
The Dual Channel Complex ADC Signal mode is used to receive
baseband I and Q signals or a single sideband signal at some IF.
In this mode, a complex input signal is generated from an external
quadrature demodulator. The in-phase channel (I channel) is
connected to VIN+A and VIN–A, and the Quadrature Data
(Q channel) is connected to the VIN+B and VIN–B differential
pins. The Rx path available options include bypassing the input
buffer, RxPGA control, the decimation filter, and using the digital
Hilbert filter. Shared Reference mode is also discussed below.
The RxPGA provides 0 dB to 20 dB gain control for both channels. The input buffer description above explains the conditions
under which the buffer should be bypassed.
If the input signal, or the undersampled alias signal for the IF sampling case, falls below 40% of the ADC Nyquist rate, the decimation
filter can be enabled to suppress out-of-band noise and spurious
signals by 40 dB or more. With the decimation filter enabled,
the SNR of the Rx path improves by about 2.3 dB.
For applications where an external crystal is desired, the AD9860/
AD9862 internal oscillator circuit and the DLL clock multiplier
enable a low frequency, lower cost quartz crystal to be used to
generate the input reference clock. The quartz crystal would be
connected between the OSC1 and OSC2 pins with parallel
resonant load capacitors as specified by the crystal manufacturer.
An internal Duty Cycle Stabilizer (DCS) can be enabled on the
AD9860 by setting the Clk Duty register. This provides a stable
50% duty cycle to the ADC for high speed clock rates between
40 MSPS to 64 MSPS when proper duty cycle is more critical.
System Clock Distribution Circuitry
There are many variables involved in the timing distribution.
External variables include CLKIN, CLKOUT1, CLKOUT2,
Rx Data Rate, Tx Data Rate. Internal variables include ADC
conversion rate, DAC update rate, interpolation rate, decimation
rate, Rx data multiplexing and Tx data demultiplexing. Many of
these parameters are interrelated and based on CLKIN. Optimal
power versus performance and ease of integration options can
be chosen to suit a particular application.
A digital Hilbert filter can be enabled to provide a receive image
rejection architecture on-chip. The digital Hilbert filter combines
the I data and a phase shifted version of the Q data to produce a
single combined Rx signal. The filter can provide 50 dB image
suppression in the pass band (less than 0.1 dB ripple). The pass
band of the filter is from 25% to 75% of Nyquist rate of the data
entering the Hilbert filter. Note, the Hilbert filter’s maximum
input data rate is 32 MSPS, at ADC rates above 32 MSPS. The
decimation filter is required to reduce the data rate. With the
decimation filter also enabled, the pass band of the Hilbert filter
will be 12.5% to 37.5% of the ADC Nyquist rate (still 25% to 75%
of the Nyquist rate of the data entering the Hilbert filter).
NO DECIMATION,
DECIMATE:
REG D6 B0
DATA
MUX
AND
LATCH
Rx DATA
[0:23]
MUX OUT:
REG D5 B0
Rx RETIME:
REG D5 B3
1, 1/2
NO INVERSION,
INVERT
DIV
INV
CLKSEL
INV1: REG D25 B1
CLKOUT1
1, 1/2
1, 2, 4
1, 1/2, 1/4
DIV
DLL
DIV
ADC DIV2:
REG D24 B5
DLL MULTIPLIER:
REG D24 B3, 4
CLKOUT2
DIV FACTOR:
REG 25 B6, 7
NO INVERSION,
INVERT
CLKIN
An optional Shared Reference mode allows the user to connect the
differential references from the dual ADC together externally for
superior gain matching performance. To enable the Shared Reference mode, the Shared Ref register (d4, b1) should be set high.
INV CLKOUT2
NO INTERP
2, 4
TIMING GENERATION BLOCK
DAC
The AD9860/AD9862 Timing Generation block uses a single
external clock reference to derive all internal clocks to operate
the transmit and receive channels. The input clock reference
can consist of either an external single ended clock applied to
the OSC1 pin, with the OSC2 pin left floating or an external
crystal connected between the clock input pins (OSC1 and OSC2).
By default, the AD9860/AD9862 can accept either an external
reference clock or a crystal to generate the input clock. The
internal oscillator, if not used, should be disabled by setting the
Input Control Clock register. The OSC1 input impedance is a
relatively high resistive impedance (typically, about 500 kW).
2
ADC
INV2:
REG D25 B5
DATA
LATCH
AND
DEMUX
Tx DATA
[0:13]
INTERPOLATION:
REG D19 B0, 1
CLOCK PATH
DATA PATH
2 DATA PATHS: REG D19 B4
Q/I ORDER:
REG D18 B5
Tx RETIME:
REG D18 B6
Figure 8. Normal Operation Timing Block Diagram
One of two possible timing operation modes can be selected. The
typical timing mode is called Normal Operation mode; a block
diagram is shown in Figure 8. The other mode is called Alternative Operation mode, and a block diagram is shown in Figure 12.
–24–
REV. 0
AD9860/AD9862
Table I. Rx Data Timing Table
Table Ia. CLKSEL Set Logic Low
CLKSEL
ADC
Div 2
Decimate
See Figure 8 for
Relative Timing
Multiplex
No Mux
No
Decimation
Table Ib. CLKSEL Set Logic High
CLKSEL
Timing No. 4
Rx Data = 2 CLKOUT1
CLKOUT1 = 1⁄2 CLKIN
Not Allowed
No Mux
Timing No. 3
Rx Data = 2 CLKOUT1
CLKOUT1 = 1⁄2 CLKIN
Mux
Timing No. 4
Rx Data(MUXED) = 2 CLKOUT1
CLKOUT1 = 1⁄2 CLKIN
No Mux
Timing No. 3
Rx Data = CLKOUT1
CLKOUT1 = 1⁄2 CLKIN
Mux
Timing No. 4
Rx Data(MUXED) = 2 CLKOUT1
CLOUT1 = 1⁄2 CLKIN
No Mux
Timing No. 2
Rx Data = 1⁄2 CLKOUT1
CLOUT1 = 1⁄2 CLKIN
Mux
Timing No. 3
Rx Data(MUXED) = CLKOUT1
CLKOUT1 = 1⁄2 CLKIN
Decimation
Low
No
Decimation
Div
Decimation
Decimate Multiplex
See Figure 8 for
Relative Timing
No Mux
Timing No. 3
Rx Data = CLKOUT1
CLKOUT1 = CLKIN
Mux
Timing No. 4
Rx Data(MUXED) = 2 CLKOUT1
CLKOUT1 = CLKIN
No Mux
Timing No. 2
Rx Data = 1⁄2 CLKOUT1
CLKOUT1 = CLKIN
Mux
Timing No. 3
Rx Data(MUXED) = CLKOUT1
CLKOUT1 = CLKIN
No Mux
Timing No. 2
Rx Data = 1⁄2 CLKOUT1
CLKOUT1 = CLKIN
Mux
Timing No. 3
Rx Data(MUXED) = CLKOUT1
CLOUT1 = CLKIN
No Mux
Timing No. 1
Rx Data = 1⁄4 CLKOUT1
CLOUT1 = CLKIN
No
Decimation
Mux
No
Div
ADC
Div 2
No
Div
Decimation
High
No
Decimation
Div
Decimation
Timing No. 2
Rx Data(MUXED) = 1⁄2 CLKOUT1
CLKOUT1 = CLKIN
Mux
fCLKOUT1
Rx DATA TIMING No. 1
fRx = CLKOUT4
Rx DATA TIMING No. 2
fRx = CLKOUT2
Rx DATA TIMING No. 3
fRx = CLKOUT
Rx DATA TIMING No. 4
fRx = 2CLKOUT
tR1
tR3
tR2
tR1
Figure 9. Rx Timing Diagram
ADC DIV2
A
CLKIN
DLL MULT
B
0: B = A
1: B = A/2
ADC SAMPLE RATE
(NOT TO EXCEED 64MHz)
CLKOUT2 DIV
C
00: C = B
01: C = B/2
10: C = B/4
DLL OUTPUT RATE
(NOT TO EXCEED 128MHz)
INTERP
D
00: D = C
01: D = C/2
10: D = C/4
E
00: E = D
01: E = 2 D
10: E = 4 D
CLKOUT2
INPUT Tx DATA RATE
(SINGLE CHANNEL)
Figure 10. Single Tx Timing Block Diagram, Alternative Operation
REV. 0
–25–
TxDAC UPDATE RATE
SINGLE CHANNEL
(CANNOT EXCEED
DLL OUTPUT RATE)
AD9860/AD9862
For the Normal Operation mode, the Tx timing is based on
a clock derived from the DLL output, while the Rx clock is
unaffected by the DLL setting.
The Rx data (unless re-timed using the Rx Retime register) is
timed relative to the CLKOUT1 pin output. The Rx output data
can be decimated (halving the data rate) or both channels can be
multiplexed onto the channel A data bus (doubling the data rate).
The Alternative Operation mode, timing utilizes the output of
the DLL to generate both Rx and Tx clocks. It also sets default
operation of the DLL to 4 mode.
Decimation enables oversampling while maintaining a slower
external data transfer rate and provides superior suppression of
out of band signals and noise. Multiplexing enables fewer digital
output bits to be used to transfer data from the Rx path to the
digital ASIC collecting the data.
Normal Operation is typically recommended because the Rx ADC
is more sensitive to the jitter and noise that the DLL may generate, so its performance may degrade. The Mode/TxBlank pin
logic level at power up or RESET defines in which mode the
device powers up. If Mode/TxBlank is low at power up, the
Normal Operation mode is configured. Otherwise, the Alternative
Operation mode is configured.
When Mux Mode is enabled with an output data rate equal to
CLKOUT1 (Timing No. 3 in Figure 9) then the RxSync pin is
required to identify which channel’s output data is on the output
data bus. RxSync output is aligned with the output data, and by
default a logic low indicates data from Rx Channel B is currently
on the output data bus. If RxSync is logic high, then data from
Rx Channel A is currently on the output data bus. The Inv RxSync
register can be used to switch this notation.
Rx Path (Normal Operation)
The ADC sampling rate, the Rx data output rate, and the rate of
CLKOUT1 (clock used to latch output data) are the parameters
of interest for the receive path data. These parameters in addition
to the data bandwidth are related to CLKIN by decimation filters,
divide by two circuits, data multiplexer logic and retiming latches.
The Rx path timing can be broken into two separate relationships: the ADC sample rate relative to the input clock, CLKIN
and the output data rate relative to CLKOUT1.
The CLKOUT1 pin outputs a clock at the frequency of CLKIN or
CLKIN/2 depending on the voltage level applied to the CLKSEL
pin. If a logic low is applied to CLKSEL, CLKOUT1 will run
at half the CLKIN rate, if CLKSEL is set to logic high CLKOUT1
outputs a clock equal to CLKIN.
This timing flexibility along with the invert option for CLKOUT1,
controlled by the Inv 1 register allow for various methods of latching data from the Rx path to the digital ASIC, which will process
the data. These options are shown in Table Ia and Ib along with
a timing diagram in Figure 9. Not shown is the option to invert
CLKOUT1, controlled by the Inv 1 register. For this mode, relative
timing remains the same except the opposite edges of CLKOUT1
would be used.
The ADCs sample rate relative to CLKIN is controlled by the
ADC Div2 register and the sample rate can be equal to or one half
of the input clock rate.
The output data relative to CLKOUT1 has many configurations
providing a flexible interface. The different options are shown in
Figure 8. Table Ia and Ib describe the setup required to obtain
the desired data timing. RxSync is available when the Rx data is
decimated and multiplexed to identify which channel data is
present at the output bus.
ADC DIV2
A
CLKIN
DLL MULT
B
0: B = A
1: B = A/2
CLKOUT2 DIV
C
00: C = B
01: C = 2 B
10: C = 4 B
ADC SAMPLE RATE
(NOT TO EXCEED 64MHz)
DUAL CHANNEL
FACTOR
2 EDGES
D
00: D = C
01: D = C/2
10: D = C/4
DLL OUTPUT RATE
(NOT TO EXCEED 128MHz)
E
0: E = D
1: E = 2 D
CLKOUT2
INTERP
F
F = E/2
INPUT
Tx DATA RATE
G
00: G = F
01: G = 2 F
10: G = 4 F
TxDAC UPDATE RATE
EACH CHANNEL
(CANNOT EXCEED
DLL OUTPUT RATE)
INPUT Tx DATA RATE
EACH CHANNEL
Figure 11. Dual Tx Timing Block Diagram, Alternative Operation
fCLKOUT2
Tx DATA TIMING No. 1
fTx = CLKOUT2
Tx DATA TIMING No. 2
fTx = 2CLKOUT2
fT1
fT3
fT2
fT4
Figure 12. Tx Timing Diagram
–26–
REV. 0
AD9860/AD9862
Tx Path (Normal Operation)
Table II. CLKOUT2 Timing Relative to CLKIN
for Normal Operation Mode
The DAC update rate, the Tx input data rate, and the rate of
CLKOUT2 (clock used to latch Tx input data) are the parameters
of interest for the transmit path data. These parameters, in addition
to the output signal bandwidth, are related to CLKIN by the settings
of the ADC Div2, the DLL multiplier, the CLKOUT2 Div, the
two edges, and the interpolation registers.
CLK DIV2
The Tx data is timed relative to the CLKOUT2 pin (unless it is
retimed relative to CLKOUT1 by setting Tx Retime register) and
the input Tx data is latched on either each rising edge, each
falling edge or both edges (controlled through the Inverse Sample
and two edges registers). The timing diagrams for these cases
are shown in Figure 12.
No Div
The Dual Tx data is multiplexed onto a single bus so that fewer
digital bits are necessary to transfer data. Throughout this discussion of Tx path timing, Tx digital processing options other than
interpolation are ignored because they do not change data timing;
Tx data timing reflects whether single or dual channel data is
latched into the AD9860/AD9862.
The rates of CLKOUT2 (and the input data rate) are related
to CLKIN by the DLL Multiplier Register, the setting of the
CLKOUT2 Divide Factor Register and the register ADC Div2.
These relationships are shown in Table II.
Div by 2
NO DECIMATION,
1, 1/2
DLL
Mult
CLKOUT2
Div Factor
CLKOUT2
1
1
2
4
CLKIN
CLKIN/2
CLKIN/4
2
1
2
4
2CLKIN
CLKIN
CLKIN/2
4
1
2
4
4CLKIN
2CLKIN
CLKIN
1
1
2
4
CLKIN/2
CLKIN/4
CLKIN/8
2
1
2
4
CLKIN
CLKIN/2
CLKIN/4
4
1
2
4
2CLKIN
CLKIN
CLKIN/2
2
DATA MUX
AND
LATCH
ADC
DIV
DECIMATE:
REG D6 B0
Rx DATA
[0:23]
MUX OUT: REG D5 B0
Rx RETIME: REG D5 B3
ADC DIV2:
REG D24 B5
1, 1/2
NO INVERSION, INVERT
DIV
INV
CLKSEL
INV1: REG D25 B1
CLKOUT1
1, 2, 4
CLKIN
DLL
1, 1/2, 1/4
DLL MULTIPLIER:
REG D24 B3, 4
DIV
INV
CLKOUT2 DIV FACTOR:
REG 25 B6, 7
NO INTERP, 2, 4
DAC
CLOCK PATH
DATA PATH
NO INVERSION, INVERT
INTERPOLATION:
REG D19 B0, 1
INV2: REG D25 B5
DATA LATCH
AND
DEMUX
2 DATA PATHS: REG D19 B4
Q/I ORDER: REG D18 B5
Tx RETIME: REG D18 B6
Figure 13. Alternative Operation Timing Block Diagram
REV. 0
–27–
CLKOUT2
Tx DATA
[0:13]
AD9860/AD9862
The timing block diagrams in Figures 10 and 11 show how the
various clocks of the single and dual Tx path are affected by the
various register settings.
pin. If a logic low is applied to CLKSEL, CLKOUT1 will run at
half the CLKIN rate; if CLKSEL is set to logic high, CLKOUT1
outputs a clock equal to CLKIN.
For dual Tx data, an option to redirect demultiplexed data to
either path is available. For example, the AD9860/AD9862 can
accept complex data in the form of I then Q data or Q then I data,
controlled through QI Order register.
This timing flexibility, along with the invert option for CLKOUT1
controlled by the Inv 1 Register, allows for various methods of
latching data from the Rx path to the digital ASIC, which will process the data. These options are shown in Table Ia and Ib along
with a timing diagram in Figure 9. Not shown is the option to
invert CLKOUT1, controlled by the Inv 1 register. For this
mode, relative timing remains the same except the opposite edges
of CLKOUT1 would be used.
For the dual Tx data cases, the Tx_SYNC Pin input logic level
defines what data is currently on the Tx data bus. By default, when
Tx_SYNC is low, Channel A data (first of the set) should be on
the data bus; if TxSYNC is high, Channel B data (or the second of
the set) should be on the Tx bus. This can be reversed be setting
the Inv TxSYNC register.
Rx Path (Alternative Timing Operation)
The ADC sampling rate, the Rx data output rate and the rate of
CLKOUT1 (clock used to latch output data) are the parameters of
interest for the receive path data. These parameters, in addition
to the data bandwidth, are related to CLKIN by decimation filters,
divide by two circuits, data multiplexer logic retiming latches and
also the DLL multiplication setting (which is not the case for
Normal Operation mode). This mode can be configured by
default by forcing the Tx_Blank_In pin to a logic high level during
power up.
The Rx path timing can be broken into two separate relationships:
the ADC sample rate relative to the input clock, CLKIN and
the output data rate relative to CLKOUT1.
The ADCs sample rate relative to CLKIN is controlled by the ADC
Div2 register and the DLL Multiplier register. The sample rate
can be equal to or one half of the DLL output clock rate.
Overall, relative timing can be found by using the Alternative
Operation Mode Master Timing Guide in Table V and using Rx
timing shown in Figure 9.
Tx Path (Alternative Timing Operation)
The DAC update rate, the Tx input data rate and the rate of
CLKOUT2 (clock used to latch Tx input data) are the parameters
of interest for the transmit path data. These parameters in addition to the output signal bandwidth are related to CLKIN by the
settings of the DLL multiplier, the CLKOUT2 Div, the two edge
and the Interpolation registers (in this mode, the ADC Div2
register does not affect Tx timing).
The Tx data is timed relative to the CLKOUT2 pin (unless it is
retimed relative to CLKOUT1 by setting Tx Retime register) and
remains the same as it does in Normal Operation Mode. The input
Tx data is latched on each rising edge, each falling edge or both
edges (controlled through the Inverse Sample and two edge registers). The timing diagrams for these cases are shown in Figure 12.
The output data rate relative to CLKOUT1 for the Alternative
Operation Mode has the same configuration options as in the
Normal Operation Mode. The different options are shown in
Figure 9. Table Ia. and Ib. describe the setup required to obtain
the desired data timing.
The Dual Tx data is multiplexed onto a single bus so that fewer
digital bits are necessary to transfer data. Throughout this discussion of Tx path timing, Tx digital processing options other than
interpolation are ignored because they do not change data timing;
Tx data timing reflects whether single or dual channel data is
latched into the AD9860/AD9862.
The Rx data (unless retimed using the Rx Retime register) is
timed relative to the CLKOUT1 pin output. The Rx output data
can be decimated (halving the data rate) or both channels can be
multiplexed onto the Channel A data bus (doubling the data rate).
The rates of CLKOUT2 (and the input data rate) are related to
CLKIN by the DLL Multiplier register and the setting of the
CLKOUT2 Divide Factor register. These relationships are shown
in Table III.
Decimation enables oversampling while maintaining a slower
external data transfer rate and provides superior suppression of
out of band signals and noise. Multiplexing enables fewer digital
output bits to be used to transfer data from the Rx path to the
digital ASIC collecting the data.
When Multiplexing mode is enabled with an output data rate equal
to CLKOUT1 (Timing No. 3 in Figure 9), then the RxSync pin
is required to identify which channel’s output data is on the
output data bus. RxSync output is aligned with the output data
and by default, a logic low indicates data from Rx Channel B is
currently on the output data bus. If RxSync is logic high, then data
from Rx Channel A is currently on the output data bus. The Inv
RxSync register can be used to switch this notation.
Table III. CLKOUT2 Timing Relative to CLKIN
In Alternative Operation Mode
DLL
Mult
CLKOUT2
Div Factor
CLKOUT2
1
1
2
4
CLKIN
CLKIN/2
CLKIN/4
2
1
2
4
2CLKIN
CLKIN
CLKIN/2
4
1
2
4
4CLKIN
2CLKIN
CLKIN
The CLKOUT1 pin outputs a clock at a frequency of CLKIN or
CLKIN/2 depending on the voltage level applied to the CLKSEL
–28–
REV. 0
AD9860/AD9862
Table IV. Normal Operation Mode Master Timing Guide
ADC Data Rate1 (MSPS)
Dual DAC Data Rate2
(MSPS)
ADC
DLL
Clock
ADC2
Mult
Rate
Non-MUX Mode
1
0
2
0
4
CLKIN CLKIN
1
Interp
2
CLKIN
CLKIN
2
2
Interp
4
CLKSEL CLKSEL CLKDIV CLKDIV CLKDIV
Interp
= Low
= High
= 1
= 1⁄ 2 = 1⁄ 4
2
CLKIN
CLKIN CLKIN CLKIN
2
CLKIN
CLKIN
2
CLKIN
4
4
2
2
CLKIN CLKIN CLKIN CLKIN
2
CLKIN
CLKIN
CLKIN
2
4
8
2
4
CLKIN CLKIN CLKIN CLKIN
4
CLKIN
2
CLKIN
CLKIN
CLKIN
2
CLKIN
4
CLKIN
8
2
CLKIN CLKIN
CLKIN
CLKIN CLKIN
2
2
CLKIN
CLKIN
2
CLKIN
4
2
2
4
CLKIN CLKIN CLKIN CLKIN
2
CLKIN
CLKIN
CLKIN
2
CLKIN
CLKIN
1
1
1
2
1
4
CLKIN CLKIN CLKIN CLKIN
2
2
4
CLKIN CLKIN
2
2
2 CLKOUT2
eUX Mode
M
No Deci Deci by 2 No Deci Deci by 2
0
CLKOUT1
DAC
Update
Rate
CLKIN CLKIN
4
CLKIN
2
NOTES
1100 MHz rate max.
2 Single DAC data rate = 1⁄2 dual DAC data rate.
Table V. Alternative Operation Mode Master Timing Guide
ADC Data Rate1 (MSPS)
ADC
DLL
ADC2
Clock
Mult
Rate
Non-MUX Mode
(two buses)
MUX Mode
(one bus)
Dual DAC Data Rate2
(MSPS)
CLKOUT1
DAC
Update
Rate
No Deci Deci by 2 No Deci Deci by 2
1
Interp
2
Interp
4
CLKSEL CLKSEL CLKDIV CLKDIV CLKDIV
Interp
= Low
= High
= 1
= 1⁄ 2 = 1⁄ 4
2
CLKIN CLKIN CLKIN
CLKIN
2
CLKIN
2
4
CLKIN
2
4
2
2
2
CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN
CLKIN
4
4
CLKIN CLKIN
8
2
CLKIN CLKIN
4
4
8
4
2
4
CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN
1
CLKIN CLKIN
2
2
CLKIN CLKIN
4
1
2
CLKIN CLKIN
1
4
2
2
CLKIN CLKIN
0
1
CLKIN CLKIN
CLKIN
2
2
CLKIN
0
2
2
2
CLKIN CLKIN
CLKIN
0
4
1
CLKIN CLKIN
CLKIN
2
CLKIN
4
2
CLKIN
CLKIN
CLKIN
2
2
CLKIN
4
CLKIN
2
CLKIN
CLKIN
2
CLKIN CLKIN
CLKIN CLKIN CLKIN
CLKIN
2
2
CLKIN
2
CLKIN
CLKIN
2
CLKIN
4
CLKIN
2
2
CLKIN
2
4
2
2
CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN
CLKIN
2
CLKIN
CLKIN
CLKIN
2
4
CLKIN CLKIN
2
8
4
4
2
4
CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN
2
CLKIN
4
CLKIN
2
CLKIN
CLKIN
NOTES
1100 MHz rate max.
2 Single DAC data rate = 1⁄2 dual DAC data rate.
REV. 0
2 CLKOUT2
–29–
CLKIN
AD9860/AD9862
The timing block diagrams in Figures 14 and 15 show how the
various clocks of the single and dual Tx path are affected by the
various register settings.
The AUX ADC A multiplexer controls whether pin AUX_ADC_A1
or pin AUX_ADC_A2 is connected to the input of Auxiliary
ADC A. The multiplexer is programmed through Register D34
B1, SelectA. By default, the register is low, which connects the
AUX_ADC_A2 Pin to the input. Similarly, AUX ADC B has a
multiplexed input controlled by Register D34 B4, SelectB. The
default setting for SelectB is low, which connects the AUX_ADC_B2
input pin to AUX ADC B. If the SelectA or SelectB register bit
is set high, then the AUX_ADC_A1 Pin or the AUX_ADC_B1
pin is connected to the respective AUX ADC input.
For dual Tx data, an option to redirect demultiplexed data to
either path is available. For example, the AD9860/AD9862 can
accept complex data in the form of I then Q data or Q then I data,
controlled through QI Order register.
For the dual Tx data cases, the Tx_SYNC pin input logic level
defines what data is currently on the Tx data bus. By default, when
Tx_SYNC is low, Channel A data (first of the set) should be on the
data bus. If TxSYNC is high, Channel B data (or the second of
the set) should be on the Tx bus. This can be reversed by setting
the Inv TxSYNC register.
An internal reference buffer provides a full-scale reference for
both of the auxiliary ADCs that is equal to the supply voltage for
the auxiliary ADCs. An external full-scale reference can be applied
to either or both of the AUX ADCs by setting the appropriate
bit(s), RefselB for the AUX ADC B and Refsel A for the AUX
ADC B in the Register Map. Setting either or both of these bits
high will disconnect the internal reference buffer and enable the
externally applied reference from the AUX_REF Pin to the
respective channel(s).
ADDITIONAL FEATURES
In addition to the features mentioned above in the transmit,
receive and clock paths, the AD9860/AD9862 also integrates
components typically required in communication systems. These
components include auxiliary analog-to-digital converters (AUX
ADC), auxiliary digital-to-analog converters (AUX DAC), and
a sigma-delta output.
Timing for the auxiliary ADCs is generated from a divided down
Rx ADC clock. The divide down ratio is controlled by register
D35 B0, CLK/4 and is used to maintain a maximum clock rate of
20 MHz. By default, CLK/4 is set low dividing the Rx ADC clock
by 2; this is acceptable when running the Rx ADC at rate of
40 MHz or less. At Rx ADC rate greater than 40 MHz, the CLK/4
register bit should be set high and will divide the Rx ADC clock
by 4 to derive the auxiliary ADC Clock. The conversion time,
including setup, takes 16 clock cycles (16 Rx ADC clock cycles);
when CLK/4 is set low, divide by 2 mode, or 32 clock cycles
when CLK/4 is set high.
Auxiliary ADC
Two auxiliary 10-bit SAR ADCs are available for various external
signals throughout the system, such as a Receive Signal Strength
Indicator (RSSI) function or Temperature Indicator. The auxiliary ADCs can convert at rates up to 1.25 MSPS and have a
bandwidth of around 200 kHz. The two auxiliary ADCs (AUX
ADC A and AUX ADC B) have multiplexed inputs, so that up
to four system signals can be monitored.
DLL MULT
CLKOUT2 DIV
A
00: B = A
01: B = 2 A
10: B = 4 A
CLKIN
INTERP
B
ADC SAMPLE RATE
(NOT TO EXCEED 64MHz)
C
00: C = B
01: C = B/2
10: C = B/4
DLL OUTPUT RATE
(NOT TO EXCEED 128MHz)
D
00: D = C
01: D = 2 C
10: D = 4 C
CLKOUT2
TxDAC UPDATE RATE
SINGLE CHANNEL
(CANNOT EXCEED
DLL OUTPUT RATE)
INPUT Tx DATA RATE
(SINGLE CHANNEL)
Figure 14. Single Tx Timing Block Diagram, Alternative Operation
DLL MULT
A
CLKIN
CLKOUT2 DIV
B
00: B = A
01: B = 2 A
10: B = 4 A
ADC SAMPLE RATE
(NOT TO EXCEED 64MHz)
DUAL CHANNEL
FACTOR
2 EDGES
D
C
00: C = B
01: C = B/2
10: C = B/4
DLL OUTPUT RATE
(NOT TO EXCEED 128MHz)
0: D = C
1: D = 2 C
CLKOUT2
INPUT
Tx DATA RATE
INTERP
E
E = D/2
F
00: F = G
01: F = 2 G
10: F = 4 G
TxDAC UPDATE RATE
EACH CHANNEL
(CANNOT EXCEED
DLL OUTPUT RATE)
INPUT Tx DATA RATE
EACH CHANNEL
Figure 15. Dual Tx Timing Block Diagram, Alternative Operation
–30–
REV. 0
AD9860/AD9862
Conversion is initiated by writing a logic high to one or both of
the Start register bits, Register D34 B0 (StartA) and D34 B3
(StartB). When the conversion is complete, the straight binary,
10-bit output data of the AUX ADC is written to one of four
reserved locations in the register map depending on which auxiliary ADC and which multiplexed input is selected. Because the
auxiliary ADCs output 10 bits, two register addresses are needed
for each data location.
Initiating a conversion or retrieving data can also be accomplished
either through the standard Serial Port Interface by reading and
writing to the appropriate registers or through a dedicated
Auxiliary Serial Port Interface (AUX SPI). The AUX SPI can
be configured to allow fast access and control of either one of the
auxiliary ADCs and is available so that the SPI is not tied up
retrieving auxiliary ADC data.
The AUX SPI can be enabled and configured by setting register
AUX ADC CTRL. Setting register use pins high enables the
AUX SPI port. Setting register Sel BnotA low connects auxiliary
ADC A to the AUX SPI port, while setting it high connects
auxiliary ADC B to the AUX SPI port. As mentioned above,
setting the appropriate Select bit selects which of the multiplexed
input is connected to the auxiliary ADC.
The AUX SPI consists of a chip select pin (AUX_SPI_csb),
a clock pin (AUX_SPI_clk), and a data output pin (AUX_SPI_do).
A conversion is initiated by pulsing the AUX_SPI_csb pin low.
When the conversion is complete, the data pin, AUX_SPI_do,
previously a logic low, will go high. At this point, the user supplies
an external clock, previously tied low, no data is present on the
first rising edge. The data output bit is updated on the falling
edge of the clock pulse and is settled and can be latched on the
next clock rising edge. The data arrives serially, MSB first. The
AUX SPI runs up to a rate of 16 MHz.
REV. 0
AUX DAC
The AD9860/AD9862 has three 8-bit voltage output auxiliary
DACs, AUX DACs. The AUX DACs are available for supplying
various control voltages throughout the system such as a VCXO
voltage control or external VGA gain control and can typically
sink or source up to 1 mA.
An internal voltage reference buffer provides a full-scale voltage
reference for both of the AUX DACs equal to the supply voltage
for the AUX DACs. The straight binary input codes are written
to the appropriate registers. If the Slave Mode register bit is
high, slave mode enabled, the AUX DAC(s) update will occur
when the appropriate update register is written to. Otherwise,
the update will occur at the conclusion of the data being written
to the register. Typical maximum settling time for the auxiliary
DAC is around 6 ms.
Other optional controls include an invert register control and a
power down option. The invert register control, i.e., instead of
hexFF being high and hex00 being low, hex00 is high, and hexFF
will be minimum setting.
Sigma-Delta
A 12-bit sigma-delta (SD) output is available to provide an
additional control voltage. The SD control word is written to
Registers D42, 43; SD [11:4] are the 8 MSBs and SD [3:0] are
the 4 LSBs. The 12-bit word is processed by a sigma-delta
modulator and produces 1-bit data at an oversampled rate equal
to 1/8 of the receive ADC’s sampling rate (up to 8 MSPS). The
1-bit data then feeds a 1-bit DAC. The 1-bit DAC exhibits
perfect linearity. An external low-pass filter at the output should
be used to low-pass filter the pulse modulated data to produce a
linear output control voltage.
–31–
AD9860/AD9862
OUTLINE DIMENSIONS
128-Lead Plastic Quad Flatpack [LQFP]
(ST-128B)
C02970–0–11/02(0)
Dimensions shown in millimeters
16.00 BSC
0.75
0.60
0.45
1.60
MAX
14.00 BSC
103
102
128
1
SEATING
PLANE
20.00
BSC
TOP VIEW
(PINS DOWN)
10
6
2
0.20
0.09
VIEW A
7
0
SEATING
PLANE
65
64
38
39
0.08 MAX
COPLANARITY
0.50
BSC
VIEW A
ROTATED 90 CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026BHB
PRINTED IN U.S.A.
1.45
1.40
1.35
22.00
BSC
–32–
REV. 0
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