FEATURES
PIN CONFIGURATION
Low offset voltage
B grade: 0.4 mV maximum (ADA4610-1/ADA4610-2 only)
A grade: 1 mV maximum
Low offset voltage drift
B grade: 2 µV/°C maximum (ADA4610-1/ADA4610-2 only)
A grade: 8 µV/°C maximum (SOIC, MSOP, LFCSP packages)
Low input bias current: 5 pA typical
Dual-supply operation: ±5 V to ±15 V
Low voltage noise: 0.45 µV p-p at 0.1 Hz to 10 Hz
Voltage noise density: 7.30 nV/√Hz at f = 1 kHz
Low THD + N: 0.00025%
No phase reversal
Rail-to-rail output
Unity-gain stable
Long-term offset voltage drift (10,000 hours): 5 µV typical
Temperature hysteresis: 8 µV typical
OUT A 1
–IN A 2
+IN A 3
V– 4
8
V+
ADA4610-2
7
TOP VIEW
(Not to Scale)
OUT B
6
–IN B
5
+IN B
09646-002
Data Sheet
Low Noise, Precision, Rail-to-Rail Output,
JFET Single/Dual/Quad Op Amps
ADA4610-1/ADA4610-2/ADA4610-4
Figure 1. ADA4610-2 8-Lead SOIC (R Suffix); for Additional Packages and
Models, See the Pin Configurations and Function Descriptions Section
APPLICATIONS
Instrumentation
Medical instruments
Multipole filters
Precision current measurement
Photodiode amplifiers
Sensors
Audio
GENERAL DESCRIPTION
The ADA4610-1/ADA4610-2/ADA4610-4 are precision junction
field effect transistor (JFET) amplifiers that feature low input noise
voltage, current noise, offset voltage, input bias current, and rail-torail output. The ADA4610-1 is a single amplifier, the ADA4610-2 is
a dual amplifier, and the ADA4610-4 is a quad amplifier.
performance filters. Low input bias currents, low offset, and low
noise result in a wide dynamic range for photodiode amplifier
circuits. Low noise and distortion, high output current, and
excellent speed make the ADA4610-1/ADA4610-2/ ADA4610-4
great choices for audio applications.
The combination of low offset, noise, and very low input bias
current makes these amplifiers especially suitable for high
impedance sensor amplification and precise current measurements
using shunts. With excellent dc precision, low noise, and fast
settling time, the ADA4610-1/ADA4610-2/ADA4610-4 provide
superior accuracy in medical instruments, electronic measurement,
and automated test equipment. Unlike many competitive
amplifiers, the ADA4610-1/ADA4610-2/ADA4610-4 maintain
fast settling performance with substantial capacitive loads. Unlike
many older JFET amplifiers, the ADA4610-1/ADA4610-2/
ADA4610-4 do not suffer from output phase reversal when input
voltages exceed the maximum common-mode voltage range.
The ADA4610-1/ADA4610-2/ADA4610-4 are specified over
the −40°C to +125°C extended industrial temperature range.
The fast slew rate and great stability with capacitive loads make
the ADA4610-1/ADA4610-2/ADA4610-4 ideal for high
Rev. I
The ADA4610-1 is available in an 8-lead SOIC package and in a
5-lead SOT-23 package. The ADA4610-2 is available in 8-lead
SOIC, 8-lead MSOP, and 8-lead LFCSP packages. The ADA4610-4
is available in a 14-lead SOIC package and in a 16-lead LFCSP.
Table 1. Related Precision JFET Operational Amplifiers
Single
AD8510
AD8610
AD820
ADA4627-1/ADA4637-1
Not applicable
Dual
AD8512
AD8620
AD822
Not applicable
ADA4001-2
Quad
AD8513
Not applicable
AD824
Not applicable
Not applicable
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Comparative Voltage and Variable Voltage Graphs ............... 17
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 20
Pin Configuration ............................................................................. 1
Applications Information .............................................................. 21
General Description ......................................................................... 1
Input Overvoltage Protection ................................................... 21
Revision History ............................................................................... 3
Peak Detector .............................................................................. 21
Specifications..................................................................................... 4
Current to Voltage (I to V) Conversion Applications ........... 21
Electrical Characteristics ............................................................. 5
Comparator Operation .............................................................. 22
Absolute Maximum Ratings ............................................................ 7
Long-Term Drift ......................................................................... 23
Thermal Resistance ...................................................................... 7
Temperature Hysteresis ............................................................. 23
ESD Caution .................................................................................. 7
Outline Dimensions ....................................................................... 24
Pin Configurations and Function Descriptions ........................... 8
Ordering Guide .......................................................................... 27
Typical Performance Characteristics ........................................... 11
Rev. I | Page 2 of 27
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
REVISION HISTORY
6/2019—Rev. H to Rev. I
Change to Features Section .............................................................. 1
Change to Offset Voltage Drift, B Grade (ADA4610-1/
ADA4610-2) Parameter, Table 2 ..................................................... 4
Change to Offset Voltage Drift, B Grade (ADA4610-1/
ADA4610-2) Parameter, Table 3 ..................................................... 5
Replaced Figure 10 and Figure 13 .................................................11
Change to Theory of Operation Section ......................................20
5/2017—Rev. G to Rev. H
Changed CP-8-21 to CP-8-11 ...................................... Throughout
Changes to Features Section ............................................................ 1
Changes to Figure 15 Caption, Figure 16 Caption, Figure 18
Caption, and Figure 19 Caption ....................................................12
Changed Functional Description Section to Theory of
Operation Section ...........................................................................20
Added Long-Term Drift Section, Temperature Hysteresis Section,
Figure 61, Figure 62, and Figure 63; Renumbered Sequentially .....23
Updated Outline Dimensions ........................................................24
Changes to Ordering Guide ...........................................................27
5/2016—Rev. F to Rev. G
Changed CP-8-20 to CP-8-21 ...................................... Throughout
Changes to Figure 23 Caption and Figure 26 Caption ...............13
Updated Outline Dimensions ........................................................24
Changes to Ordering Guide ...........................................................25
1/2016—Rev. E to Rev. F
Added 5-Lead SOT-23 ....................................................... Universal
Changed CP-8-9 to CP-8-20 ........................................ Throughout
Change to Features Section .............................................................. 1
Added Figure 3 and Table 7; Renumbered Sequentially .............. 8
Updated Outline Dimensions ........................................................23
Changes to Ordering Guide ...........................................................25
4/2015—Rev. D to Rev. E
Added ADA4610-1 ............................................................ Universal
Added 16-Lead LFCSP_WQ ............................................. Universal
Deleted Figure 1 and Figure 3; Renumbered Sequentially .......... 1
Changes to Features Section ............................................................ 1
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................. 5
Added Figure 2 and Table 6; Renumbered Sequentially .............. 7
Added Figure 4 .................................................................................. 8
Added Figure 7 .................................................................................. 9
Changes to Table 8 ............................................................................ 9
Changes to Figure 10 Caption and Figure 13 Caption ...............10
Changes to Figure 14 Caption, Figure 15, Figure 17 Caption,
and Figure 18 ...................................................................................11
Changes to Figure 22 and Figure 25 .............................................12
Changes to Figure 26 to Figure 31 ................................................13
Changes to Figure 32 and Figure 35 ............................................. 14
Changes to Figure 38 and Figure 40 ............................................. 15
Changes to Figure 42 to Figure 46 ................................................ 16
Changes to Figure 48, Figure 50, and Figure 53 .......................... 17
Changes to Figure 54 and Figure 55 ............................................. 18
Changes to Figure 57 and Figure 58 ............................................. 20
Updated Outline Dimensions........................................................ 22
Added Figure 64 .............................................................................. 23
Changes to Ordering Guide ........................................................... 24
11/2014—Rev. C to Rev. D
Change to Figure 56 ........................................................................ 19
5/2014—Rev. B to Rev. C
Added ADA4610-4 and 14-Lead SOIC ........................... Universal
Added Voltage Noise Density to Features Section, Figure 3, and
Table 1; Renumbered Sequentially.................................................. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 ............................................................................ 6
Added Pin Configurations and Function Descriptions
Section, Figure 4 to Figure 6, Table 6, and Table 7 ....................... 7
Changes to Typical Performance Characteristics Section ........... 8
Added Functional Description Section ........................................ 17
Added Input Overvoltage Protection Section, Peak Detector
Section, I to V Conversion Applications Section, and
Photodiode Circuits Section .......................................................... 18
Change to Figure 56 ........................................................................ 18
Added Figure 62, Outline Dimensions ........................................ 20
Changes to Ordering Guide ........................................................... 20
8/2012—Rev. A to Rev. B
Changes to Figure 9 .......................................................................... 8
5/2012—Rev. 0 to Rev. A
Changes to Data Sheet Title and General Description Section .. 1
Changed Input Impedance Parameter, Differential to Input
Capacitance Parameter, and Differential Parameter, Table 1 ...... 3
Added Input Resistance in Table 1.................................................. 3
Changed Input Impedance, Differential Parameter to Input
Capacitance, Differential Parameter, Table 2 ................................ 4
Added Input Resistance Parameter, Table 2 .................................. 4
Added Figure 9, Figure 10, and Figure 14; Renumbered
Sequentially ........................................................................................ 8
Added Figure 15 ................................................................................ 9
Updated Outline Dimensions........................................................ 16
Changes to Ordering Guide ........................................................... 17
12/2011—Revision 0: Initial Version
Rev. I | Page 3 of 27
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
SPECIFICATIONS
VSY = ±5 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
B Grade (ADA4610-1/ADA4610-2)
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
0.2
0.4
0.8
1
1.8
mV
mV
mV
mV
2
8
12
25
1.5
20
0.25
+2.5
µV/°C
µV/°C
µV/°C
pA
nA
pA
nA
V
dB
dB
VOS
−40°C < TA < +125°C
A Grade
0.4
−40°C < TA < +125°C
Offset Voltage Drift
B Grade (ADA4610-1/ADA4610-2) 1
A Grade1 (SOIC, MSOP, LFCSP)
A Grade1 (SOT-23)
Input Bias Current
ΔVOS/ΔT
IB
Input Offset Current
IOS
0.5
1
1
5
−40°C < TA < +125°C
2
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
ADA4610-2
CMRR
AVO
VCM = −2.5 V to +2.5 V
−40°C < TA < +125°C
RL = 2 kΩ, VOUT = −3.5 V to +3.5 V
−40°C < TA < +125°C
ADA4610-1/ADA4610-4
Input Capacitance
Differential
Common-Mode
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
−40°C < TA < +125°C
VCM = 0 V
98
86
96
84
VCM = 0 V
VOH
VOL
RL = 2 kΩ
−40°C < TA < +125°C
RL = 600 Ω
−40°C < TA < +125°C
RL = 2 kΩ
−40°C < TA < +125°C
RL = 600 Ω
−40°C < TA < +125°C
4.85
4.60
4.60
4.05
PSRR
100
dB
dB
dB
dB
98
3.1
4.8
>1013
pF
pF
Ω
4.90
V
V
V
V
V
V
V
V
mA
4.89
−4.90
−4.90
−4.75
−4.80
−4.40
±63
VSY = ±4.5 V to ±18 V
−40°C < TA < +125°C
ADA4610-1/ADA4610-4
ISY
110
−4.95
ISC
ADA4610-2
Supply Current per Amplifier
−2.5
94
86
−40°C < TA < +125°C
IOUT = 0 mA
−40°C < TA < +125°C
Rev. I | Page 4 of 27
106
103
104
100
125
117
1.50
1.70
1.85
dB
dB
dB
dB
mA
mA
Data Sheet
Parameter
DYNAMIC PERFORMANCE
Slew Rate
Rising
Falling
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
Total Harmonic Distortion + Noise
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
1
ADA4610-1/ADA4610-2/ADA4610-4
Symbol
Test Conditions/Comments
±SR
RL = 2 kΩ, AV = 1
Min
Typ
151
151
V/µs
V/µs
MHz
MHz
Degrees
MHz
%
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
GBP
UGC
φM
−3 dB
THD + N
VIN = 5 mV p-p, RL = 2 kΩ, AV = 100
VIN = 5 mV p-p, RL = 2 kΩ, AV = 1
AV = 1, VIN = 5 mV p-p
1 kHz, AV = 1, RL = 2 kΩ, VIN = 1 V rms
21
46
15.4
9.3
61
10.6
0.00025
en p-p
en
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
0.45
14
8.20
7.30
7.30
Max
Unit
Guaranteed by design and characterization.
ELECTRICAL CHARACTERISTICS
VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
B Grade (ADA4610-1/ADA4610-2)
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
0.2
0.4
0.8
1
1.8
mV
mV
mV
mV
2
8
12
25
1.50
20
0.25
+12.5
µV/°C
µV/°C
µV/°C
pA
nA
pA
nA
V
dB
dB
VOS
−40°C < TA < +125°C
A Grade
0.4
−40°C < TA < +125°C
Offset Voltage Drift
B Grade (ADA4610-1/ADA4610-2) 1
A Grade1 (SOIC, MSOP, LFCSP)
A Grade1 (SOT-23)
Input Bias Current
ΔVOS/ΔT
Input Offset Current
IOS
0.5
1
1
5
IB
−40°C < TA < +125°C
2
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
ADA4610-2
CMRR
AVO
VCM = −12.5 V to +12.5 V
−40°C < TA < +125°C
RL = 2 kΩ, VOUT = ±13.5 V
−40°C < TA < +125°C
ADA4610-1/ADA4610-4
Input Capacitance
Differential
Common-Mode
Input Resistance
−40°C < TA < +125°C
VCM = 0 V
VCM = 0 V
Rev. I | Page 5 of 27
−12.5
100
96
104
91
102
86
115
107
104
3.1
4.8
>1013
dB
dB
dB
dB
pF
pF
Ω
ADA4610-1/ADA4610-2/ADA4610-4
Parameter
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
ADA4610-2
Data Sheet
Symbol
Test Conditions/Comments
Min
Typ
VOH
RL = 2 kΩ
−40°C < TA < +125°C
RL = 600 Ω
−40°C < TA < +125°C
RL = 2 kΩ
−40°C < TA < +125°C
RL = 600 Ω
−40°C < TA < +125°C
14.80
14.65
14.25
13.35
14.90
VOL
PSRR
1
Unit
V
V
V
V
V
V
V
V
mA
VSY = ±4.5 V to ±18 V
ADA4610-1/ADA4610-4
DYNAMIC PERFORMANCE
Slew Rate
Rising
Falling
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
Total Harmonic Distortion + Noise
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise
Voltage Noise Density
−14.68
−14.85
−14.75
−14.60
−14.30
±79
−40°C < TA < +125°C
Supply Current per Amplifier
14.47
−14.90
ISC
Max
ISY
−40°C < TA < +125°C
IOUT = 0 mA
−40°C < TA < +125°C
±SR
RL = 2 kΩ, AV = +1
106
103
104
100
125
117
1.60
171
171
GBP
UGC
φM
−3 dB
THD + N
VIN = 5 mV p-p, RL = 2 kΩ, AV = 100
VIN = 5 mV p-p, RL = 2 kΩ, AV = 1
AV = 1, VIN = 5 mV p-p
1 kHz, AV = 1, RL = 2 kΩ, VIN = 5 V rms
25
61
16.3
9.3
66
9.5
0.00025
en p-p
en
0.1 Hz to 10 Hz bandwidth
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
0.45
14
8.50
7.30
7.30
Guaranteed by design and characterization.
Rev. I | Page 6 of 27
1.85
2.0
dB
dB
dB
dB
mA
mA
V/µs
V/µs
MHz
MHz
Degrees
MHz
%
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage
Input Voltage
Input Current1
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 10 sec)
Electrostatic Discharge (ESD)
Human Body Model (HBM)2
Field Induced Charge Device Model (FICDM)3
Rating
±18 V
±VS
±10 mA
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
2500 V
1250 V
Table 5. Thermal Resistance
Package Type
5-Lead SOT-23
8-Lead SOIC
8-Lead LFCSP
8-Lead MSOP
14-Lead SOIC
16-Lead LFCSP
1
The input pins have clamp diodes connected to the power supply pins. Limit
the input current to 10 mA or less whenever input signals exceed the power
supply rail by 0.3 V.
2
ESDA/JEDEC JS-001-2011 applicable standard.
3
JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
1
θJA1
219.4
120
57
142
115
65
θJC
155.6
43
12
45
36
3.2
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA is specified for worst-case conditions, that is, θJA is specified for a device
soldered in a circuit board for surface-mount packages.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. I | Page 7 of 27
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
NIC
1
–IN
2
+IN 3
V–
8
NIC
ADA4610-1
7
V+
TOP VIEW
(Not to Scale)
6
OUT
5
NIC
4
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
09646-101
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. ADA4610-1 Pin Configuration, 8-Lead SOIC (R Suffix)
Table 6. ADA4610-1 Pin Function Descriptions, 8-Lead SOIC
Pin No.
1, 5, 8
2
3
4
6
7
Mnemonic
NIC
−IN
+IN
V−
OUT
V+
Description
Not Internally Connected.
Inverting Input.
Noninverting Input.
Negative Supply Voltage.
Output.
Positive Supply Voltage.
OUT 1
5
V+
4
–IN
ADA4610-1
TOP VIEW
(Not to Scale)
+IN 3
09646-100
V– 2
Figure 3. ADA4610-1 Pin Configuration, 5-Lead SOT-23 (RJ Suffix)
Table 7. ADA4610-1 Pin Function Descriptions, 5-Lead SOT-23
Pin No.
1
2
3
4
5
Mnemonic
OUT
V−
+IN
−IN
V+
Description
Output.
Negative Supply Voltage.
Noninverting Input.
Inverting Input.
Positive Supply Voltage.
Rev. I | Page 8 of 27
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
–IN A 2
+IN A 3
V+
8
ADA4610-2
7
TOP VIEW
(Not to Scale)
OUT B
6
–IN B
5
+IN B
V– 4
09646-104
OUT A 1
OUT A 1
8
V+
–IN A 2
ADA4610-2
7
OUT B
+IN A 3
TOP VIEW
(Not to Scale)
6
–IN B
5
+IN B
V– 4
09646-102
Figure 4. ADA4610-2 Pin Configuration, 8-Lead SOIC (R Suffix)
Figure 5. ADA4610-2 Pin Configuration, 8-Lead MSOP (RM Suffix)
OUT A 1
+IN A 3
V– 4
8 V+
ADA4610-2
TOP VIEW
(Not to Scale)
7 OUT B
6 –IN B
5 +IN B
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO V–.
09646-105
–IN A 2
Figure 6. ADA4610-2 Pin Configuration, 8-Lead LFCSP (CP Suffix)
Table 8. ADA4610-2 Pin Function Descriptions, 8-Lead SOIC, 8-Lead MSOP, and 8-Lead LFCSP
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
EPAD
Description
Output Channel A.
Inverting Input Channel A.
Noninverting Input Channel A.
Negative Supply Voltage.
Noninverting Input Channel B.
Inverting Input Channel B.
Output Channel B.
Positive Supply Voltage.
Exposed Pad for the 8-Lead LFCSP (CP Suffix). The exposed pad must be connected to V−.
Rev. I | Page 9 of 27
13 NIC
14 OUT D
16 NIC
Data Sheet
15 OUT A
ADA4610-1/ADA4610-2/ADA4610-4
–IN A 1
–IN D
ADA4610-4
12
+IN D
TOP VIEW
(Not to Scale)
11
V–
10
+IN C
–IN B 6
9
–IN C
OUT B 7
8
OUT C
+IN A 3
V+ 4
+IN B 5
11 +IN D
10 V–
9
+IN B 4
+IN C
–IN C 8
13
OUT C 7
–IN A 2
TOP
VIEW
V+ 3
–IN B 5
OUT D
OUT B 6
14
09646-106
OUT A 1
12 –IN D
ADA4610-4
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2.THE EXPOSED PAD MUST BE CONNECTED TO V–.
Figure 7. ADA4610-4 Pin Configuration, 14-Lead SOIC (R Suffix)
Figure 8. ADA4610-4 Pin Configuration, 16-Lead LFCSP (CP Suffix)
Table 9. ADA4610-4 Pin Function Descriptions, 14-Lead SOIC and 16-Lead LFCSP
14-Lead SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Not applicable
Not applicable
Pin No.
16-Lead LFCSP
15
1
2
3
4
5
6
7
8
9
10
11
12
14
13, 16
Mnemonic
OUT A
−IN A
+IN A
V+
+IN B
−IN B
OUT B
OUT C
−IN C
+IN C
V−
+IN D
−IN D
OUT D
NIC
EPAD
09646-107
+IN A 2
Description
Output Channel A.
Inverting Input Channel A.
Noninverting Input Channel A.
Positive Supply Voltage.
Noninverting Input Channel B.
Inverting Input Channel B.
Output Channel B.
Output Channel C.
Inverting Input Channel C.
Noninverting Input Channel C.
Negative Supply Voltage.
Noninverting Input Channel D.
Inverting Input Channel D.
Output Channel D.
Not Internally Connected.
Exposed Pad. The exposed pad must be connected to V−.
Rev. I | Page 10 of 27
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
400
400
SOIC
350
350
300
300
NUMBER OF CHANNELS
250
200
150
100
250
200
150
100
0
–1000 –800 –600 –400 –200 0
200 400 600
OFFSET VOLTAGE (µV)
09646-003
0
–1000 –800 –600 –400 –200 0
200 400 600
OFFSET VOLTAGE (µV)
800 1000 1200
Figure 9. Input Offset Voltage Distribution, VSY = ±5 V
70
SOIC
SOIC
60
50
40
30
20
50
40
30
20
10
0
0
TCVOS (µV/°C)
Figure 10. Input Offset Voltage Drift (TCVOS) Distribution, VSY = ±5 V
Figure 13. TCVOS Distribution, VSY = ±15 V
1500
1000
1000
INPUT OFFSET VOLTAGE (uV)
1500
500
0
–500
MEAN
MEAN + 3σ
MEAN – 3σ
–1500
–5
–4
–3
–2
–1
0
1
VCM (V)
0
–500
MEAN
MEAN + 3σ
MEAN – 3σ
–1000
2
3
4
5
–1500
–15
09646-005
–1000
500
Figure 11. Input Offset Voltage vs. Common-Mode Input Voltage (VCM),
VSY = ±5 V, RL = ∞
–10
–5
0
VCM (V)
5
10
15
09646-008
TCVOS (µV/°C)
09646-004
10
09646-007
NUMBER OF CHANNELS
60
–8.0
–7.5
–7.0
–6.5
–6.0
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
NUMBER OF CHANNELS
800 1000 1200
Figure 12. Input Offset Voltage Distribution, VSY = ±15 V
70
INPUT OFFSET VOLTAGE (µV)
09646-006
50
50
–8.0
–7.5
–7.0
–6.5
–6.0
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
NUMBER OF CHANNELS
SOIC
Figure 14. Input Offset Voltage vs. Input Common-Mode Voltage (VCM),
VSY = ±15 V, RL = ∞
Rev. I | Page 11 of 27
Data Sheet
50
40
40
30
30
20
10
0
–10
MEAN
MEAN + 3σ
MEAN – 3σ
–20
20
10
0
–10
–30
–30
–40
–40
–4
–3
–2
–1
0
1
2
3
4
5
VCM (V)
–50
–15
–10
15
100k
SOIC
SOIC
10k
10k
1k
INPUT BIAS CURRENT (pA)
+125°C
100
10
+25°C
1
–40°C
1k
+125°C
100
10
+25°C
1
0.1
–40°C
–3
–2
–1
0
1
2
3
4
5
VCM (V)
0.1
–15
09646-056
–4
–10
–5
0
5
15
10
VCM (V)
Figure 16. Input Bias Current vs. Common-Mode Input Voltage (VCM),
Three Temperatures, VSY = ±5 V, RL = ∞
Figure 19. Input Bias Current vs. Common-Mode Input Voltage (VCM),
Three Temperatures, VSY = ±15 V, RL = ∞
100
INPUT BIAS CURRENT (pA)
100
10
1
–25
0
25
50
TEMPERATURE (°C)
75
100
125
1
0.1
–50
09646-009
0.1
–50
10
Figure 17. Input Bias Current vs. Temperature, VSY = ±5 V
–25
0
25
50
TEMPERATURE (°C)
75
100
125
Figure 20. Input Bias Current vs. Temperature, VSY = ±15 V
Rev. I | Page 12 of 27
09646-012
INPUT BIAS CURRENT (pA)
10
5
Figure 18. Input Bias Current vs. Common-Mode Input Voltage (VCM),
Mean and Three Standard Deviations, VSY = ±15 V, RL = ∞
100k
INPUT BIAS CURRENT (pA)
0
VCM (V)
Figure 15. Input Bias Current vs. Common-Mode Input Voltage (VCM),
Mean and Three Standard Deviations, VSY = ±5 V, RL = ∞
0.01
–5
–5
09646-058
–50
–5
MEAN
MEAN + 3σ
MEAN – 3σ
–20
09646-057
INPUT BIAS CURRENT (pA)
50
09646-055
INPUT BIAS CURRENT (pA)
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
0.1
0.01
0.1
1
10
IOUT SOURCE (mA)
100
0.1
0.01
0.1
100
10
(VOUT – V–) (V)
10
1
1
10
100
IOUT SINK (mA)
0.01
0.01
0.1
1
IOUT SINK (mA)
10
100
Figure 25. Dropout Voltage (VOUT − V−) vs. IOUT Sink, VSY = ±15 V
Figure 22. Dropout Voltage (VOUT − V−) vs. IOUT Sink, VSY = ±5 V
225
100
80
180
80
180
60
135
60
135
GAIN
40
PHASE
90
20
45
0
0
–20
–40
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–90
100M
270
225
GAIN
40
PHASE
90
20
45
0
0
–45
–20
–45
09646-016
100
GAIN (dB)
120
PHASE (Degrees)
270
120
–40
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–90
100M
Figure 26. Open-Loop Gain and Phase Margin vs. Frequency,
VSY = ±15 V, RL = 2 kΩ, VIN = 5 mV
Figure 23. Open-Loop Gain and Phase Margin vs. Frequency,
VSY = ±5 V, RL = 2 kΩ, VIN = 5 mV
Rev. I | Page 13 of 27
PHASE (Degrees)
1
09646-015
0.01
0.1
09646-018
0.1
0.1
09646-019
(VOUT – V–) (V)
10
IOUT SOURCE (mA)
Figure 24. Dropout Voltage (V+ − VOUT) vs. IOUT Source, VSY = ±15 V
Figure 21. Dropout Voltage (V+ − VOUT) vs. IOUT Source, VSY = ±5 V
GAIN (dB)
1
09646-014
(V+ – VOUT) (V)
1
09646-011
(V+ – VOUT) (V)
1
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
60
60
AV = +100
AV = +100
40
40
AV = +10
GAIN (dB)
AV = +1
0
20
AV = +1
0
10k
100k
1M
FREQUENCY (Hz)
10M
100M
–40
1k
09646-017
1k
1k
100
100
10
AV = +100
1
AV = +100
1
0.1
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 31. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±15 V
120
120
100
100
80
80
PSRR (dB)
PSRR–
60
40
PSRR–
60
40
PSRR+
PSRR+
20
20
0
0
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–20
100
09646-022
PSRR (dB)
AV = +1
0.01
100
09646-021
1k
Figure 28. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V
–20
100
100M
AV = +10
AV = +1
0.01
100
10M
10
AV = +10
0.1
100k
1M
FREQUENCY (Hz)
Figure 30. Closed-Loop Gain vs. Frequency, VSY = ±15 V
ZOUT (Ω)
ZOUT (Ω)
Figure 27. Closed-Loop Gain vs. Frequency, VSY = ±5 V
10k
09646-024
–40
1k
09646-020
–20
–20
Figure 29. PSRR vs. Frequency, VSY = ±5 V
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 32. PSRR vs. Frequency, VSY = ±15 V
Rev. I | Page 14 of 27
10M
09646-025
GAIN (dB)
AV = +10
20
ADA4610-1/ADA4610-2/ADA4610-4
120
120
100
100
CMRR (dB)
140
80
60
80
60
40
40
20
20
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
100
09646-023
3
12
2
8
1
0
–1
1M
10M
4
0
–4
0
1
2
3
4
5
6
TIME (µs)
7
8
9
10
–12
09646-027
–3
0
1
2
3
4
5
6
TIME (µs)
7
8
9
10
09646-030
–8
–2
Figure 37. Large Signal Transient Response, VSY = ±15 V, AV = 1,
RL = 2 kΩ, CL = 100 pF
Figure 34. Large Signal Transient Response, VSY = ±5 V, AV = 1,
RL = 2 kΩ, CL = 100 pF
75
50
50
OUTPUT VOLTAGE (mV)
75
25
0
–25
25
0
–25
–50
–50
–75
0
1
2
3
4
5
6
TIME (µs)
7
8
9
10
–75
09646-028
OUTPUT VOLTAGE (mV)
10k
100k
FREQUENCY (Hz)
Figure 36. CMRR vs. Frequency, VSY = ±15 V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 33. CMRR vs. Frequency, VSY = ±5 V
1k
0
1
2
3
4
5
6
TIME (µs)
7
8
9
10
Figure 38. Small Signal Transient Response, VSY = ±15 V, AV = 1,
RL = 2 kΩ, CL = 100 pF
Figure 35. Small Signal Transient Response, VSY = ±5 V, AV = 1,
RL = 2 kΩ, CL = 100 pF
Rev. I | Page 15 of 27
09646-031
CMRR (dB)
140
09646-026
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
10
1
1
10
100
1k
FREQUENCY (Hz)
10k
100k
10
1
1
Figure 39. Voltage Noise Density vs. Frequency, VSY = ±5 V
10
100
1k
FREQUENCY (Hz)
10k
09646-036
VOLTAGE NOISE DENSITY (nV/ Hz)
100
09646-033
VOLTAGE NOISE DENSITY (nV/ Hz)
100
Figure 41. Voltage Noise Density vs. Frequency, VSY = ±15 V
50
50
40
40
OVERSHOOT (%)
30
OS–
10
0
0.01
OS+
30
20
OS–
10
0.1
LOAD CAPACITANCE (nF)
1
0
0.01
Figure 40. Overshoot vs. Load Capacitance, VSY = ±5 V, AV = 1,
RL = 2 kΩ, VIN = 100 mV p-p
0.1
LOAD CAPACITANCE (nF)
1
Figure 42. Overshoot vs. Load Capacitance, VSY = ±15 V, AV = 1,
RL = 2 kΩ, VIN = 100 mV p-p
Rev. I | Page 16 of 27
09646-037
20
09646-034
OVERSHOOT (%)
OS+
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
COMPARATIVE VOLTAGE AND VARIABLE VOLTAGE GRAPHS
10
10
VSY = ±5V
RL = 2kΩ
fIN = 1kHz
1 80kHz FILTER
1
0.1
THD + N (%)
0.1
0.01
0.001
0.001
0.0001
0.0001
0.00001
0.01
0.1
1
0.00001
0.001
AMPLITUDE (V rms)
Figure 46. THD + N vs. Amplitude, VSY = ±15 V
1
VSY = ±5V
VIN = 1.5V rms
0.1
THD + N (%)
10
1
AMPLITUDE (V rms)
Figure 43. THD + N vs. Amplitude, VSY = ±5 V
1
0.1
0.01
09646-040
0.01
09646-205
THD + N (%)
VSY = ±15V
RL = 2kΩ
fIN = 1kHz
80kHz FILTER
VSY = ±15V
VIN = 5V rms
0.1
0.001
500kHz BAND-PASS FILTER
0.0001
80kHz BAND-PASS FILTER
THD + N (%)
0.01
0.01
0.001
500kHz BAND-PASS FILTER
0.0001
10
100
1k
10k
09646-204
0.00001
100k
FREQUENCY (Hz)
0.00001
10
100
1k
100k
10k
FREQUENCY (Hz)
Figure 44. THD + N vs. Frequency, VSY = ±5 V
09646-141
80kHz BAND-PASS FILTER
Figure 47. THD + N vs. Frequency, VSY = ±15 V
16
–40
12
8
VOLTAGE (V)
–80
–100
4
0
–4
–120
–8
–140
–160
100
1k
10k
FREQUENCY (Hz)
Figure 45. Channel Separation vs. Frequency
100k
–16
0
0.1
0.2
0.3
0.4
0.5
0.6
TIME (ms)
0.7
0.8
0.9
1.0
09646-042
OUTPUT
INPUT
–12
09646-039
CHANNEL SEPARATION (dB)
–60
Figure 48. No Phase Reversal, VSY = ±15 V, AV = +1, RL = 2 kΩ, CL = 100 pF
Rev. I | Page 17 of 27
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
300
ISY PER AMPLIFIER (mA)
100
0
–100
–200
–400
0
1
2
3
4
5
6
TIME (Seconds)
7
8
9
10
09646-043
–300
Figure 49. Voltage Noise, 0.1 Hz to 10 Hz
+25°C
–40°C
0
5
12
12
10
10
15
20
VSY (V)
25
30
35
STEP SIZE (V)
8
0.1%
6
0.01%
4
0.01%
0.1%
6
4
2
0.2
0.4
0.6
0.8
1.0
SETTLING TIME (µs)
1.2
1.4
0
09646-044
0
0
0.2
Figure 50. Positive Step Settling Time
1.4
VOUT = 7.3 × VIN
2
0
12
–2
10
–4
VOUT (V)
14
8
6
4
VIN
–6
–8
–10
2
–12
VIN
0
–14
–2
–16
0
0.5
1.0
1.5
2.0
TIME (µs)
2.5
3.0
–18
–0.5
09646-200
–4
–0.5
1.2
4
VOUT = 7.3 × VIN
VOUT
0.6
0.8
1.0
SETTLING TIME (µs)
Figure 53. Negative Step Settling Time
18
16
0.4
09646-045
2
0
VOUT (V)
10
Figure 52. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY) at
Various Temperatures
8
STEP SIZE (V)
+125°C
+85°C
VOUT
0
0.5
1.0
1.5
2.0
TIME (µs)
Figure 51. Positive Overload Recovery
Figure 54. Negative Overload Recovery
Rev. I | Page 18 of 27
2.5
3.0
09646-201
VOLTAGE (nV)
200
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
09646-047
400
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
3
15
VSY = ±5V
VIN = ±2V
AV = +1
RL = 2kΩ
CL = 100pF
2
10
INPUT
0
OUTPUT
VOUT
0
–1
–5
–2
–10
–3
–0.2
0
0.2
0.4
0.6
0.8
1.0
TIME (µs)
1.2
1.4
1.6
1.8
–15
–2.0
–1.5
–1.0
–0.5
TIME (µs)
Figure 55. Positive and Negative Slew Rate (VSY = ±5 V, AV = 1, RL = 2 kΩ)
0
0.5
1.0
09646-202
VOLTAGE (V)
5
09646-203
VOLTAGE (V)
1
VSY = ±15V
VIN = ±10V
AV = +1
RL = 2kΩ
CL = 100 pF
VIN
Figure 56. Positive and Negative Slew Rate (VSY = ±15 V, AV = 1, RL = 2 kΩ)
Rev. I | Page 19 of 27
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
THEORY OF OPERATION
The ADA4610-1/ADA4610-2/ADA4610-4 are manufactured
using the Analog Devices, Inc., iPolar® process, a 36 V dielectrically
isolated (DI) process with P-channel JFET technology. The
unique architecture of the ADA4610-1/ADA4610-2/ADA4610-4
makes it possible to combine high precision and high speed
characteristics into a high voltage, low power op amp. A simplified
schematic for the ADA4610-1/ADA4610-2/ADA4610-4 is
shown in Figure 57. The JFET input stage architecture offers
advantages of low input bias current, high bandwidth, high
gain, low noise, and no phase reversal when the applied input
signal exceeds the common-mode voltage range. The output
stage is rail-to-rail with high drive characteristics and low
dropout voltage for both sinking and sourcing currents.
The ADA4610-1/ADA4610-2 B grades achieve less than 0.4 mV
of offset and 2 μV/°C of offset drift; these characteristics are
usually associated with very high precision bipolar input
amplifiers. The gate current of a typical JFET doubles every
10°C, resulting in a similar increase in input bias current over
temperature. The low power consumption characteristic of the
ADA4610-1/ADA4610-2/ADA4610-4 minimizes the die
temperature, which warrants low input bias currents even at
elevated ambient temperatures, making the amplifiers ideal for
applications that require low leakage specifications without active
cooling. Ensure proper printed circuit board (PCB) layout to
minimize leakage currents between PCB traces. Improper layout
and board handling can generate leakage currents exceeding
the bias currents of the operational amplifier.
The ADA4610-1/ADA4610-2/ADA4610-4 are unconditionally
stable for all gain configurations, even with capacitive loads
well in excess of 1 nF. The devices have internal protective
circuitry that allows voltages as high as 0.3 V beyond the
supplies to be applied at the input of either terminal without
causing damage (for higher input voltages, refer to the Input
Overvoltage Protection section).
The ADA4610-1/ADA4610-2/ADA4610-4 are fully specified with
supply voltages from ±5 V to ±15 V over the extended industrial
temperature range of −40°C to +125°C. The ADA4610-1 is
available in an 8-lead SOIC. The ADA4610-2 is available in an
8-lead MSOP, an 8-lead SOIC, and an 8-lead LFCSP. The
ADA4610-4 is available in a 14-lead SOIC and a 16-lead LFCSP.
All these packages are surface-mount type.
V+
R6
D31
R7
C3
Q30
Q8
R16
Q29
Q9
Q28
+ –
1+
Q12
A1
Q14
Q15
Q18
C2
RC4
DE5
C4
A2
DE1
R10
Q1
DE3
Q4
R2
VIN+
J1
R11
Q5
Q23
Q13
Q16
Q17
VOUT
R3
J2
R5
DE6
VIN–
Q7
C1
Q6
Q27
DE2
I2
I3
Q24
Q25
I4
R15
D26
V–
Figure 57. Simplified Schematic
Rev. I | Page 20 of 27
09646-054
DE4
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
APPLICATIONS INFORMATION
INPUT OVERVOLTAGE PROTECTION
The ADA4610-1/ADA4610-2/ADA4610-4, shown in Figure 58,
are ideal for building a peak detector because U2A requires dc
precision and high output current during fast peaks, and U2B
requires low input bias current (IB) to minimize capacitance
discharge between peaks. A low leakage and low dielectric
absorption capacitor, such as polystyrene or polypropylene, is
required for C3. Reversing the diode directions causes the
circuit to detect negative peaks.
The ADA4610-1/ADA4610-2/ADA4610-4 have internal protective
circuitry that allows voltages as high as 0.3 V beyond the supplies
to be applied at the input of either terminal without causing
damage. For higher input voltages, a series resistor is necessary
to limit the input current. Determine the resistor value by
≤ 10 mA
RS
CURRENT TO VOLTAGE (I TO V) CONVERSION
APPLICATIONS
where:
VIN is the input voltage.
VS is the voltage of either V+ or V−.
RS is the series resistor.
Photodiode Circuits
Common applications for I to V conversion include photodiode
circuits where the amplifier converts a current emitted by a diode
placed at the negative input terminal into an output voltage.
With a very low bias current of RF, the circuit
behavior is not impacted by the effect of the junction resistance.
The maximum signal bandwidth (fMAX) is
ft
2R F CT
where ft is the unity-gain frequency of the op amp.
Calculate CF by
CF
CT
2RF ft
9
COMPARATOR, VOUT = HIGH
where ft is the unity-gain frequency of the op amp, and achieves a
phase margin, φM, of approximately 45°.
ISY FOR ALL CHANNELS (mA)
8
Increase the CF value to obtain a higher phase margin. Setting
CF to twice the previous value yields approximately φM = 65° and a
maximal flat frequency response, but it reduces the maximum
signal bandwidth by 50%.
Using the previous parameters with a CF ≈ 7 pF, the signal
bandwidth is approximately 250 kHz.
COMPARATOR, VOUT = LOW
7
6
FOLLOWER
5
4
3
2
1
0
0
5
10
15
20
VSY (V)
25
30
35
40
09646-053
f MAX
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp can
be used as a comparator; however, this is not recommended for
rail-to-rail output op amps. For rail-to-rail output op amps, the
output stage is generally a ratioed current mirror with bipolar or
MOSFET transistors. With the device operating in open-loop
mode, the second stage increases the current drive to the ratioed
mirror to close the loop. However, the second stage cannot close
the loop, which results in an increase in supply current. With
the ADA4610-1/ADA4610-2/ADA4610-4 op amps configured
as comparators, the supply current can be significantly higher
(see Figure 60 for the supply current vs. the supply voltage for the
ADA4610-4). Configuring an unused section as a voltage follower
with the noninverting input connected to a voltage within the
input voltage range is recommended. The ADA4610-1/ADA4610-2/
ADA4610-4 have a unique output stage design that reduces the
excess supply current but does not entirely eliminate this effect
when the op amp is operating in open-loop mode.
Figure 60. Supply Current (ISY) vs. Supply Voltage (VSY) for the ADA4610-4 Only
Rev. I | Page 22 of 27
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
LONG-TERM DRIFT
TEMPERATURE HYSTERESIS
The stability of a precision signal path over its lifetime or
between calibration procedures is dependent on the long-term
stability of the analog components in the path, such as op amps,
references, and data converters. To help system designers
predict the long-term drift of circuits that use the ADA4610-1/
ADA4610-2/ADA4610-4, Analog Devices measured the offset
voltage of multiple units for 10,000 hours (more than 13 months)
using a high precision measurement system, including an
ultrastable oil bath. To replicate real-world system performance,
the devices under test (DUTs) were soldered onto an FR4 PCB
using a standard reflow profile (as defined in the JEDEC J-STD020D standard), as opposed to testing them in sockets. This
manner of testing is important because expansion and contraction
of the PCB can apply stress to the integrated circuit (IC) package
and contribute to shifts in the offset voltage.
In addition to stability over time as described in the Long-Term
Drift section, it is useful to know the temperature hysteresis,
that is, the stability vs. cycling of temperature. Hysteresis is an
important parameter because it tells the system designer how
closely the signal returns to its starting amplitude after the
ambient temperature changes and subsequent return to room
temperature. Figure 62 shows the change in input offset voltage
as the temperature cycles three times from room temperature to
+125°C to −40°C and back to room temperature. The dotted
line is an initial preconditioning cycle to eliminate the original
temperature-induced offset shift from exposure to production
solder reflow temperatures. In the three full cycles, the offset
hysteresis is typically only 8 µV, or 1% of its 800 µV maximum
offset voltage over the full operating temperature range. The
histogram in Figure 63 shows that the hysteresis is larger when
the device is cycled through only a half cycle, from room
temperature to 125°C and back to room temperature.
40
20
0
100
50
0
–50
–100
–150
–40
–20
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
SAMPLE 1
SAMPLE 2
SAMPLE 3
–40
Figure 62. Change in Offset Voltage over Three Full Temperature Cycles
VSY = 10V
27 UNITS
TA = 25°C
NUMBER OF DEVICES
10,000
09646-061
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
–60
TIME (Hours)
09646-062
MEAN
MEAN PLUS ONE STANDARD DEVIATION
MEAN MINUS ONE STANDARD DEVIATION
PRECONDITION
CYCLE 1
CYCLE 2
CYCLE 3
VSY = 10V
Figure 61. Measured Long-Term Drift of the ADA4610-1/ADA4610-2/
ADA4610-4 Offset Voltage over 10,000 Hours
50
45 VSY = 10V
27 UNITS × 3 CYCLES
40 HALF CYCLE = +26°C, +125°C, +26°C
35 FULL CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C
30
25
20
15
10
5
0
50
45
40
35
30
25
20
15
10
5
0
–80
–64
–48
–32
–16
0
16
32
HALF CYCLE
FULL CYCLE
48
OFFSET VOLTAGE HYSTERESIS (µV)
64
80
09646-063
CHANGE IN OFFSET VOLTAGE (µV)
60
150
CHANGE IN OFFSET VOLTAGE (µV)
The ADA4610-1/ADA4610-2/ADA4610-4 have extremely low
long-term drift, as shown in Figure 61. The red, blue, and green
traces show sample units. Note that the ADA4610-1/ADA4610-2/
ADA4610-4 (B-grade) have a mean drift over 10,000 hours of
approximately 5 µV, or less than 2% of their maximum specified
offset voltage of 400 µV at room temperature.
Figure 63. Histogram Showing the Temperature Hysteresis of the Offset
Voltage over Three Full Cycles and over Three Half Cycles
Rev. I | Page 23 of 27
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 64. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 65. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. I | Page 24 of 27
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
3.00
2.90
2.80
1.70
1.60
1.50
5
1
4
2
3.00
2.80
2.60
3
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.35 MIN
0.20 MAX
0.08 MIN
10°
5°
0°
SEATING
PLANE
0.55
0.45
0.35
0.60
BSC
11-01-2010-A
1.30
1.15
0.90
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 66. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
2.44
2.34
2.24
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
AREA
TOP VIEW
PKG-005136
SEATING
PLANE
SIDE VIEW
0.30
0.25
0.20
4
1
0.20 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET
COMPLIANT TO JEDEC STANDARDS MO-229-W3030D-4
Figure 67. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-11)
Dimensions shown in millimeters
Rev. I | Page 25 of 27
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
08-17-2018-C
0.50
0.40
0.30
0.80
0.75
0.70
1.70
1.60
1.50
EXPOSED
PAD
ADA4610-1/ADA4610-2/ADA4610-4
Data Sheet
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 68. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
DETAIL A
(JEDEC 95)
0.35
0.30
0.25
13
0.65
BSC
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
16
1
12
2.25
2.10 SQ
1.95
EXPOSED
PAD
9
TOP VIEW
PKG-004025/5112
0.80
0.75
0.70
SEATING
PLANE
SIDE VIEW
0.70
0.60
0.50
4
5
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 69. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-23)
Dimensions shown in millimeters
Rev. I | Page 26 of 27
0.20 MIN
08-24-2018-B
PIN 1
INDICATOR
AREA
4.10
4.00 SQ
3.90
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
ORDERING GUIDE
Model 1
ADA4610-1ARZ
ADA4610-1ARZ-R7
ADA4610-1ARZ-RL
ADA4610-1BRZ
ADA4610-1BRZ-R7
ADA4610-1BRZ-RL
ADA4610-1ARJZ-R2
ADA4610-1ARJZ-R7
ADA4610-1ARJZ-RL
ADA4610-2ACPZ-R7
ADA4610-2ACPZ-RL
ADA4610-2ARMZ
ADA4610-2ARMZ-R7
ADA4610-2ARMZ-RL
ADA4610-2ARZ
ADA4610-2ARZ-R7
ADA4610-2ARZ-RL
ADA4610-2BRZ
ADA4610-2BRZ-R7
ADA4610-2BRZ-RL
ADA4610-4ARZ
ADA4610-4ARZ-R7
ADA4610-4ARZ-RL
ADA4610-4ACPZ-R7
ADA4610-4ACPZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
©2011–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09646-0-6/19(I)
Rev. I | Page 27 of 27
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
RJ-5
RJ-5
RJ-5
CP-8-11
CP-8-11
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
R-14
R-14
R-14
CP-16-23
CP-16-23
Marking Code
A37
A37
A37
A2U
A2U
A2U
A2U
A2U
工商网监
湘ICP备2023018690号
