Data Sheet
ADATE320
1.25 GHz Dual Integrated DCL with PPMU, Level Setting DACs, and On-Chip
Calibration Registers
FEATURES
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GENERAL DESCRIPTION
1.25 GHz, 2.5 Gbps data rate
3-level driver with high-Z and reflection clamps
Window and differential comparators
±25 mA active load
Per pin parametric measurement unit (PMU) with a −1.5 V to
+4.5 V range
Low leakage mode (typically 0.8 V.
Table 3.
Parameter
Min
VCH
Functional Range
Offset Error
−0.5
−300
Offset TC
Gain
VCL
Functional Range
Offset Error
Offset TC
analog.com
Max
Unit
Test Level
+5.0
+300
V
mV
D
P
1.1
mV/°C
V/V
CT
P
ppm/°C
µV
µV
CT
D
CT
±0.25
1.0
Gain TC
Resolution
DNL
INL
Typ
±25
153
±250
−20
+20
mV
P
−2.0
−300
+3.5
+300
V
mV
D
P
mV/°C
CT
±0.25
Test Conditions/Comments
Driver high-Z, sinking 1 mA, measured at DAC Code 0x4000 (0.0 V),
uncalibrated
Driver high-Z, sinking 1 mA, gain derived from measurements at DAC
Code 0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V), based on an ideal
DAC transfer function (see Table 24)
Driver high-Z, sinking 1 mA, after two-point gain/offset calibration;
calibration points at DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V), measured over the functional range
Driver high-Z, sinking 1 mA, after two-point gain/offset calibration;
calibration points at DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V), measured over the functional range
Driver high-Z, sourcing 1 mA, measured at DAC Code 0x4000 (0.0 V),
uncalibrated
Rev. C | 7 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 3.
Parameter
Min
Gain
1.0
Gain TC
Resolution
DNL
INL
DC CLAMP CURRENT LIMIT
VCHx
VCLx
DUTGND VOLTAGE ACCURACY
Typ
Max
Unit
Test Level
Test Conditions/Comments
1.1
V/V
P
Drive high-Z, sourcing 1 mA, gain derived from measurements at DAC
Code 0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V), based on an ideal
DAC transfer function (see Table 24)
ppm/°C
µV
µV
CT
D
CT
±25
153
±250
−20
+20
mV
P
−105
+60
−10
−60
+105
+10
mA
mA
mV
P
P
P
±2
Drive high-Z, sourcing 1 mA, after two-point gain/offset calibration;
calibration points at DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V), measured over the functional range
Drive high-Z, sourcing 1 mA, after two-point gain/offset calibration;
calibration points at DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC
(3.0 V), measured over the functional range
Drive high-Z
VCHx = −1.0 V, VCLx = −2.0 V, VDUTx = 4.5 V
VCHx = 5.0 V, VCLx = 4.0 V, VDUTx = −1.5 V
Over ±0.1 V range, measured at end points of VCHx and VCLx
functional range
NORMAL WINDOW COMPARATOR (NWC) SPECIFICATIONS
Table 4.
Parameter
DC SPECIFICATIONS
Input Voltage Range
Differential Voltage Range
Input Offset Voltage
Input Offset Voltage TC
Gain
Min
Typ
−1.5
±0.1
−250
Max
Unit
Test Level
Test Conditions/Comments
+4.5
±6.0
+250
V
V
mV
µV/°C
V/V
D
D
P
CT
P
Measured at DAC Code 0x4000 (0.0 V); uncalibrated
ppm/°C
µV
mV
CT
D
CT
mV
mV
mV
P
P
P
±150
1.0
Gain TC
Threshold Resolution
Threshold DNL
1.1
±10
153
±0.25
Threshold INL
Focused Range
Full Range
DUTGND Voltage Accuracy
−5
−7
−5
±1
+5
+7
+5
Uncertainty Band
10
mV
CB
Programmable Hysteresis
Hysteresis Resolution
DC PSR
100
4
±5
mV
Bits
mV/V
CB
D
CT
Ω
P
mV
CT
Digital Output Characteristics
Internal Pull-up Resistance to
Comparator, VTTCx
Common-Mode Voltage
ADATE320
analog.com
46
50
−250
54
Gain derived from measurements at DAC Code 0x4000 (0.0 V) and DAC
Code 0x8CCC (3.0 V); based on an ideal DAC transfer function (see
Table 24)
Measured over −1.5 V to +4.5 V functional range after two-point gain/
offset calibration; calibration points at DAC Code 0x4000 (0.0 V) and
DAC Code 0x8CCC (3.0 V)
After two-point gain/offset calibration; calibration points at DAC Code
0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V)
Measured over −0.5 V to +3.5 V range
Measured over −1.5 V to +4.5 V range
Over ±0.1 V range; measured over −0.5 V to +3.5 V focused NWC input
range
VDUTx = 0.0 V, sweep comparator threshold to determine the uncertainty
band
Measured at DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V)
calibration points
Source 1 mA and 10 mA from the output pin in high state, measure ∆V
to calculate resistance; R = ∆V/9 mA; repeat for all output pins
Measured relative to VTTCx, with 100 Ω differential termination
Rev. C | 8 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 4.
Parameter
ADATE320-1
Differential Mode Voltage
100 Ω Differential Termination
ADATE320
ADATE320-1
No External Termination
ADATE320
ADATE320-1
AC SPECIFICATIONS
Min
Typ
Max
−400
Unit
Test Level
mV
CT
Test Conditions/Comments
Measured differentially
250
400
450
700
500
800
550
900
mV
mV
CT
CT
mV
mV
P
P
Unless otherwise specified, all ac tests are performed after dc levels
calibration; input transition time: 50 ps 20% to 80%; outputs terminated
50 Ω to 0.0 V; comparator CLC set to ¼ scale (010)
Measured with 50 Ω to 0.0 V
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V, comparator
threshold = 0.5 V
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V, comparator
threshold = 0.5 V
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V, comparator
threshold = 0.5 V
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V, comparator
threshold = 0.5 V
Drive term mode, VIT = 0.0 V
VDUTx = 0.0 V to 0.5 V swing, comparator threshold = 0.25 V
Rise/Fall Times, 20% to 80%
Propagation Delay
100
580
ps
ps
CB
CB
Propagation Delay TC
1
ps/°C
CT
Propagation Delay Matching High
Transition to Low Transition
Propagation Delay Matching High
to Low Comparator
Propagation Delay Dispersion
Slew Rate: 400 ps vs. 1.0 ns
(20% to 80%)
Overdrive: 250 mV vs. 1.0 V
10
ps
CB
10
ps
CB
20
ps
CB
25
ps
CB
1.0 V Pulse Width: 0.4 ns, 0.5
ns, 1 ns, 5 ns, 10 ns
0.5 V Pulse Width: 0.4 ns, 0.5
ns, 1 ns, 5 ns, 10 ns
Duty Cycle: 5% to 95%
Minimum Detectable Pulse Width
25
ps
CB
For 250 mV: VDUTx: 0.0 V to 0.50 V swing; for 1.0 V: VDUTx: 0.0 V to 1.25
V swing, comparator threshold = 0.25 V
VDUTx = 0.0 V to 1.0 V swing, 32 MHz, comparator threshold = 0.5 V
25
ps
CB
VDUTx = 0.0 V to 0.5 V swing, 32 MHz, comparator threshold = 0.25 V
10
200
ps
ps
CB
CB
Input Equivalent Rise/Fall Time,
1.0 V, Terminated
110
ps
CB
Input Equivalent Rise/Fall Time,
2.0 V, Unterminated
500
ps
CB
VDUTx = 0.0 V to 1.0 V swing, 32 MHz, comparator threshold = 0.5 V
VDUTx = 0.0 V to 1.0 V swing, 32 MHz, greater than 50% output
differential amplitude
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V, CLC = 010,
measured from digitized plot, 20% to 80% transition time of digitized plot
is root-sum square (RSS) of input equivalent rise/fall and 50 ps input
stimulus
VDUTx = 0.0 V to 2.0 V swing, drive high-Z, measured from digitized plot,
20% to 80% transition time of digitized plot is root-sum square (RSS) of
input equivalent rise/fall and 50 ps input stimulus
VDUTx = 0.0 V to 1.0 V swing, drive term mode, VIT = 0.0 V, maximum
CLC setting
20
3
280
4.8
%
Bits
ps
ns
CB
D
S
S
Cable Loss Compensation (CLC)
CLC Amplitude
CLC Resolution
CLC Time Constant 1
CLC Time Constant 2
DIFFERENTIAL MODE COMPARATOR (DMC) SPECIFICATIONS
Table 5.
Parameter
DC SPECIFICATIONS
analog.com
Min
Typ
Max
Unit
Test Level
Test Conditions/Comments
VOHx tests at VOLx = −1.5 V, VOLx tests at VOHx = 1.5 V
Rev. C | 9 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 5.
Parameter
Input Voltage Range
Functional Differential Range
Maximum Differential Input
Input Offset Voltage
Input Offset Voltage TC
Gain
Min
−250
Max
Unit
Test Level
+4.5
±1.1
±6.0
+250
V
V
V
mV
D
D
D
P
1.1
µV/°C
V/V
CT
P
ppm/°C
µV
µV
CT
D
CT
mV
P
±150
1.0
Gain TC
VOHx, VOLx Resolution
VOHx, VOLx DNL
VOHx, VOLx INL
Typ
−1.5
±0.05
±40
153
±250
−8
+8
Uncertainty Band
11
mV
CB
Programmable Hysteresis
Hysteresis Resolution
Common-Mode Rejection Ratio
(CMRR)
DC PSR
200
4
mV
Bits
mV/V
CB
D
P
±5
mV/V
CT
Propagation Delay
580
ps
CB
Propagation Delay TC
2
ps/°C
CT
Propagation Delay Matching High
Transition to Low Transition
15
ps
CB
Propagation Delay Matching High to
Low Comparator
15
ps
CB
Slew Rate: 400 ps vs. 1 ns (20%
to 80%)
Overdrive: 250 mV vs. 750 mV
30
ps
CB
25
ps
CB
1.0 V Pulse Width: 0.7 ns, 1.0 ns,
5.0 ns, 10 ns
0.5 V Pulse Width: 0.6 ns, 1.0 ns,
5.0 ns, 10 ns
Duty Cycle: 5% to 95%
25
ps
CB
25
ps
CB
5
ps
CB
−1.0
+1.0
AC SPECIFICATIONS
Propagation Delay Dispersion
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Test Conditions/Comments
Offset interpolated from measurements at DAC Code 0x2666 (−1.0 V)
and DAC Code 0x5999 (1.0 V), with VCM = 0.0 V
Gain derived from measurements at DAC Code 0x2666 (−1.0 V) and
DAC Code 0x5999 (1.0 V); based on an ideal DAC transfer function (see
Table 24)
After two-point gain/offset calibration; VCM = 0.0 V; calibration points at
DAC Code 0x2666 (−1.0 V) and DAC Code 0x5999 (1.0 V)
After two-point gain/offset calibration; VCM = 0.0 V; calibration points
DAC Code 0x2666 (−1.0 V) and DAC Code 0x5999 (1.0 V), measured
over VOHx/VOLx range of −1.1 V to +1.1 V
VDUTx = 0.0 V, sweep comparator threshold to determine the uncertainty
band
∆Offset measured at VCM = −1.5 V and +4.5 V, VDM = 0.0 V
∆Offset measured at VCM = 0.0 V, VDM = calibration points DAC Code
0x2666 (−1.0 V) and DAC Code 0x5999 (1.0 V)
All ac tests are performed after dc levels calibration; input transition time
= 50 ps 20% to 80%; outputs terminated 50 Ω to VTTCx, comparator
CLC set to ¼ scale (010)
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive termination mode,
VIT = 0.0 V, comparator threshold = 0.0 V, repeat with VDUTx inputs
reversed
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive termination mode,
VIT = 0.0 V, comparator threshold = 0.0 V, repeat with VDUTx inputs
reversed
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive termination mode,
VIT = 0.0 V, comparator threshold = 0.0 V, repeat with VDUTx inputs
reversed
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive termination mode,
VIT = 0.0 V, comparator threshold = 0.0 V, repeat with VDUTx inputs
reversed
VDUT0 = 0.0 V, VIT = 0.0 V, drive termination mode, repeat with VDUTx
inputs reversed
VDUT1 = −0.5 V to +0.5 V swing, comparator threshold = 0.0 V
For 250 mV: VDUT1 = 0.0 V to 0.5 V swing; for 750 mV: VDUT1 = 0.0 V to
1.0 V swing, comparator threshold = −0.25 V, repeat with VDUTx inputs
reversed with comparator threshold = +0.25 V
VDUT1 = −0.5 V to +0.5 V swing, 32 MHz, comparator threshold = 0.0 V
VDUT1 = −0.25 V to +0.25 V swing, 32 MHz, comparator threshold = 0.0
V
VDUT1 = −0.5 V to +0.5 V swing, 32 MHz, comparator threshold = 0.0 V
Rev. C | 10 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 5.
Parameter
Unit
Test Level
Test Conditions/Comments
Minimum Detectable Pulse Width
Min
Typ
200
Max
ps
CB
Input Equivalent Rise/Fall Time
110
ps
CB
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, 32 MHz, drive term
mode, VIT = 0.0 V, comparator threshold = 0.0 V, greater than 50%
output differential amplitude, repeat with VDUTx inputs reversed
VDUT0 = 0.0 V, VDUT1 = −0.5 V to +0.5 V swing, drive term mode, VIT
= 0.0 V, comparator threshold = 0.0 V, CLC = ¼ scale, measured from
digitized plot, t = √(tCMP2 − tIN2)
VDUT0 = 0.0 V, VDUT1 = −0.8 V to +0.8 V swing, drive term mode, VIT =
0.0 V, comparator threshold = 0.0 V, comparator CLC set to maximum
CLC setting, repeat with VDUTx inputs reversed
20
3
280
4.8
%
Bits
ps
ns
CB
D
S
S
Cable Loss Compensation (CLC)
CLC Amplitude
CLC Resolution
CLC Time Constant 1
CLC Time Constant 2
ACTIVE LOAD SPECIFICATIONS
Table 6.
Parameter
DC SPECIFICATIONS
Input Characteristics
Active Load Commutation
Voltage (VCOMx) Range
VCOMx Offset
VCOMx Offset TC
VCOMx Gain
Min
Typ
Max
Unit
Test Level
Load in active on state, RCVx active
−1.5
−200
+4.5
V
D
IOHx = IOLx = 1 mA, VDUTx open circuit
+200
mV
µV/°C
V/V
P
CT
P
Measured at DAC Code 0x4000 (0.0 V), uncalibrated
ppm/°
C
µV
µV
CT
mV
mV
mV
P
P
P
mA
D
+600
µA
P
+25
µA/°C
%
CT
P
ppm/°
C
nA
CT
±100
1.0
1.1
VCOMx Gain TC
±20
VCOMx Resolution
VCOMx DNL
153
±250
D
CT
VCOMx INL
Focused Range
Full Range
DUTGND Voltage Accuracy
−5
−10
−5
±1
+5
+10
+5
Output Characteristics
Maximum Source Current (IOLx) 25
IOLx Offset
−600
IOLx Offset TC
IOLx Gain Error
0
±1
IOLx Gain TC
±100
IOLx Resolution
763
analog.com
Test Conditions/Comments
Gain derived from measurements at DAC Code 0x4000 (0.0 V) and DAC
Code 0x8CCC (3.0 V)
IOHx = IOLx = 12.5 mA, after two-point gain/offset calibration; measured
over VCOMx range −1.5 V to +4.5 V; calibration points DAC Code
0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V)
IOHx = IOLx = 12.5 mA; after two-point gain/offset calibration; calibration
points DAC Code 0x4000 (0.0 V) and DAC Code 0x8CCC (3.0 V)
Measured over VCOMx range of −0.5 V to +3.5 V
Measured over VCOMx range of −1.5 V to +4.5 V
Over ±0.1 V range; measured over −0.5 V to +3.5 V focused VCOMx
range
VDUTx ≤ 3.5 V (a compliance limit is set by a 50 Ω internal resistor as
illustrated in Figure 141)
IOHx = −2.5 mA, VCOMx = 1.5 V, VDUTx = 0.0 V; offset extrapolated from
measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666
(20 mA)
IOHx = −2.5 mA, VCOMx = 1.5 V, VDUTx = 0.0 V; gain derived from
measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20
mA); based on an ideal dc transfer function
D
Rev. C | 11 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 6.
Parameter
Min
Unit
Test Level
Test Conditions/Comments
µA
CT
+100
µA
P
0.4
V
P
V
CT
mA
D
+600
µA
P
IOHx = −2.5 mA, VCOMx = 1.5 V, VDUTx = 0.0 V; after two-point gain/
offset calibration; measured over IOLx range 0 mA to 25 mA; calibrated
at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA)
IOHx = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration
IOHx = IOLx = 25 mA, VCOM = 2.0 V, measure IOLx reference at
VDUTx = −1.0 V, measure IOLx current at VDUTx = 1.6 V, check > 90% of
reference current
IOHx = IOLx = 1 mA, VCOM = 2.0 V, measure IOLx reference at VDUTx
= −1.0 V, measure IOLx current at VDUTx = 1.9 V, check > 90% of
reference current
VDUTx ≥ −0.5 V (a compliance limit is set by a 50 Ω internal resistor as
illustrated in Figure 141)
IOLx = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V, offset extrapolated from
measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20
mA)
+25
µA/°C
%
CT
P
ppm/°
C
nA
µA
CT
+100
µA
P
0.4
V
P
0.1
V
CT
Propagation Delay, Load Active
On to Load Active Off
Propagation Delay, Load Active
Off to Load Active On
1.7
ns
CB
2.9
ns
CB
Propagation Delay Matching
Load Spike
Settling Time to Within 5%
1.2
140
2.5
ns
mV
ns
CB
CB
CB
IOLx DNL
IOLx INL
Typ
Max
±1.25
−100
IOLx 90% Commutation Voltage
0.25
0.1
Maximum Sink Current (IOHx)
25
IOHx Offset
−600
IOHx Offset TC
IOHx Gain Error
0
±1
IOHx Gain TC
±100
IOHx Resolution
IOHx DNL
763
±1.25
IOHx INL
−100
IOHx 90% Commutation Voltage
0.25
D
CT
AC SPECIFICATIONS
Dynamic Performance
IOLx = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V, gain derived from
measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20
mA); based on an ideal DAC transfer function
IOLx = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/offset
calibration; measured over IOHx range of 0 mA to 25 mA; calibrated at
DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA)
IOLx = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/offset
calibration
IOHx = IOLx = 25 mA, VCOM = 2.0 V, measure IOHx reference at
VDUTx = 4.0 V, measure IOHx current at VDUTx = 2.4 V, ensure > 90% of
reference current
IOHx = IOLx = 1 mA, VCOM = 2.0 V, measure IOHx reference at VDUTx
= 4.0 V, measure IOHx current at VDUTx = 2.1 VDUTx, ensure > 90% of
reference current
All ac measurements are performed after dc calibration unless noted,
load active on
Toggle RCVx; DUTx terminated 50 Ω to 0.0 V; IOLx = IOHx = 20 mA,
VIH = VIL = 0.0 V; VCOM = +1.5 V for IOLx and −1.5 V for IOHx
Measured from zero crossing of RCVx − RCVx to 50% of final output
value; repeat for drive low and drive high
Measured from zero crossing of RCVx − RCVx to 50% of final output
value; repeat for drive low and drive high
Active on vs. active off; repeat for drive low and drive high
Repeat for drive low and drive high
Measured from output crossing 50% final value to output within 5% final
value
PPMU SPECIFICATIONS
PPMU enabled in force voltage mode unless noted.
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Rev. C | 12 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 7.
Parameter
FORCE VOLTAGE (FV)
Current Ran=ge A
Current Range B
Current Range C
Current Range D
Current Range E
FV Range at Output, Range A
FV Range at Output, Range B,
Range C, Range D, and Range E
FV Offset, Range C
FV Offset, All Ranges
FV Offset TC, All Ranges
FV Gain, Range C
Min
Typ
−40
−1
−100
−10
−2
−1.0
−1.5
−1.5
−100
Max
Unit
Test Level
Test Conditions/Comments
+40
+1
+100
+10
+2
+4.0
+4.5
+4.5
mA
mA
µA
µA
µA
V
V
V
D
D
D
D
D
D
D
D
Output range for full-scale source/sink
Output range for ±25 mA or less
Output range for full-scale source/sink
+100
mV
mV
P
CT
µV/°C
V/V
CT
P
±30
±100
1.0
1.1
FV Gain, All Ranges
1.05
V/V
CT
FV Gain TC, All Ranges
±10
ppm/°C
CT
FV INL
Range A
±1.5
mV
CT
Range C, Focused Range
−1.7
+1.7
mV
P
Range C, Full Range
−5
+5
mV
P
±1.0
mV
CT
FV Compliance vs. Source/Sink
Current, Range A (±40 mA)
±1
mV
CT
FV Compliance vs. Source/Sink
Current, Range A (±25 mA)
±1
mV
CT
FV Compliance vs. Source/Sink
Current, Range B, Range C,
Range D, and Range E
±1
mV
CT
+5
mV
P
+4.0
+4.5
V
V
D
D
Range B, Range D, and Range E
DUTGND Voltage Accuracy
FORCE CURRENT (FI)
DUTx Pin Voltage Range, Range A
analog.com
−5
−1.0
−1.5
±1
Measured at DAC Code 0x4000 (0.0 V) in Range C
Measured at DAC Code 0x4000 (0.0 V) applies to all
other ranges
Measured at DAC Code 0x4000 (0.0 V)
Gain derived from measurements at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V); based on an
ideal DAC transfer function
Gain derived from measurements at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V); based on an
ideal DAC transfer function
Gain derived from measurements at DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V)
After two-point gain/offset calibration, output range of
−1.5 V to +4.5 V; calibration points DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V), PPMU Current
Range A
After two-point gain/offset calibration, output range of
−0.5 V to +3.5 V; calibration points DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V)
After two-point gain/offset calibration, output range of
−1.5 V to +4.5 V; calibration points DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V)
After two-point gain/offset calibration, output range of
−1.5 V to +4.5 V; calibration points DAC Code 0x4000
(0.0 V) and DAC Code 0x8CCC (3.0 V)
Force −1.0 V; measure voltage while sinking 0.0 mA
and full-scale current; measure ∆V; force 4.0 V; measure
voltage while sourcing 0.0 mA and full-scale current;
measure ∆V
Force −1.5 V; measure voltage while sinking 0.0 mA and
25 mA; measure ∆V; force 4.5 V; measure voltage while
sourcing 0.0 mA and 25 mA; measure ∆V
Force −1.5 V; measure voltage while sinking 0.0 mA
and full-scale current; measure ∆V; force 4.5 V; measure
voltage while sourcing 0.0 mA and full-scale current;
measure ∆V
Over ±0.1 V range; measured over −0.5 V to +3.5 V
focused PPMU output range
PPMU enabled in force current/measure current (FIMI)
Full-scale source and sink current
DUTx pin source and sink 25 mA or less
Rev. C | 13 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 7.
Parameter
DUTx Pin Voltage Range, Range B,
Range C, Range D, and Range E
Zero-Current Offset, All Ranges
Zero-Current Offset TC
Gain Error, All Ranges
Min
Max
Unit
Test Level
Test Conditions/Comments
−1.5
+4.5
V
D
Full-scale source and sink current
−14.5
+14.5
% FSR
P
Interpolated from measurements at PPMU DAC Code
0x4CCC (−80% FS) and DAC Code 0xB333 (80% FS)
for each range
30
% FSR/°C
%
CT
P
±50
ppm/°C
CT
±50
±50
ppm/°C
ppm/°C
CT
CT
±0.02
0
Gain Drift
Range A
Range B
Range C, Range D, and Range E
INL
Range A
Range B, Range C, and Range D
Typ
−0.12
−0.04
+0.12
+0.04
% FSR
% FSR
P
P
−0.045
+0.045
% FSR
P
−0.3
+0.3
% FSR
P
−0.1
+0.1
% FSR
P
−0.3
+0.3
% FSR
P
−0.06
+0.06
% FSR
P
Range D
−0.3
+0.3
% FSR
P
Range E
−0.85
+0.85
% FSR
P
−1.5
−25
+4.5
+25
1.02
V
mV
µV/°C
V/V
D
P
CT
P
+1.7
ppm/°C
mV
CT
P
Range E
FI Compliance vs. Voltage Load
Range A
Range B and Range C
MEASURE VOLTAGE (MV)
Range
Offset
Offset TC
Gain
Gain TC
INL
MEASURE CURRENT (MI)
DUTx Pin Voltage Range
analog.com
±50
0.98
±5
−1.7
Derived from measurements at PPMU DAC Code
0x4CCC (−80% FS) and DAC Code 0xB333 (80% FS)
for each range
PPMU self heating effects in Range A can influence gain
drift measurements
After two-point gain/offset calibration
Measured over FSR output of Range A (±40 mA)
Measured over FSR output of Range B (±1 mA), Range
C (±100 µA), and Range D (±10 µA)
Measured over FSR output of Range E (±2 µA)
Force positive full-scale current driving −1.0 V and +4.0
V, measure ∆I at DUTx pin; force negative full-scale
current driving −1.0 V and +4.0 V, measure ∆I at DUTx
pin
Force positive full-scale current driving 0.0 V and 3.0 V,
measure ∆I at DUTx pin; force negative full-scale current
driving 0.0 V and 3.0 V, measure ∆I at DUTx pin
Force positive full-scale current driving −1.5 V and +4.5
V, measure ∆I at DUTx pin; force negative full-scale
current driving −1.5 V and +4.5 V, measure ∆I at DUTx
pin
Force positive full-scale current driving 0.0 V and 3.0 V,
measure ∆I at DUTx pin; force negative full-scale current
driving 0.0 V and 3.0 V, measure ∆I at DUTx pin
Force positive full-scale current driving −1.5 V and +4.5
V, measure ∆I at DUTx pin; force negative full-scale
current driving −1.5 V and +4.5 V, measure ∆I at DUTx
pin
Force positive full-scale current driving −1.5 V and +4.5
V, measure ∆I at DUTx pin; force negative full-scale
current driving −1.5 V and +4.5 V, measure ∆I at DUTx
pin; allows 10 nA DUTx pin leakage
PPMU enabled, force voltage/measure voltage (FVMV)
Range B, VDUTx = 0.0 V, offset = (PPMU_Mx − VDUTx)
Range B, derived from measurements at VDUTx = 0.0 V
and 3.0 V
Range B, measured over −1.5 V to +4.5 V
PPMU enabled in FIMI
Full-scale source and sink current
Rev. C | 14 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 7.
Parameter
Min
Typ
Max
Unit
Test Level
+4.0
+4.5
V
V
D
D
+4
%FSR
P
±0.5
%FSR
CT
±0.01
±0.01
±0.02
%FSR/°C
%FSR/°C
%FSR/°C
CT
CT
CT
Range A
−1.0
Range B, Range C, Range D, and −1.5
Range E
Zero-Current Offset
Range B
−4
All Ranges
Zero-Current Offset TC
Range A
Range B, Range C, and Range D
Range E
Gain Error
−30
DUTx Pin Voltage Rejection
−1.3
Output Leakage Current When
Tristated
Output Short Circuit Current
PPMU_Mx Pin, Parasitic Output
Capacitance
PPMU_Mx Pin, External Load
Capacitance
PPMU VOLTAGE CLAMPS (FI)
−10
+5
%
%
P
CT
±50
±50
±50
ppm/°C>
ppm/°C
ppm/°C
CT
CT
CT
±0.02
+0.02
%FSR
%FSR
%FSR
CT
P
CT
+1.3
µA
P
+5
mV
P
+5.0
200
V
Ω
D
P
−1
+1
µA
P
−10
+10
mA
P
2
pF
S
pF
S
V
V
mV
D
D
P
−0.02
±0.01
−5
−1.5
±1
100
Low Voltage Clamp Range (PCLx)
−1.5
High Voltage Clamp Range (PCHx)
−0.5
Offset, Voltage Clamps (PCHx/PCLx) −300
analog.com
Interpolated from measurements sourcing and sinking
80% FS current each range; for example, 2% FSR is 40
µA in Range B
Derived from measurements sourcing and sinking 80%
FS current
Range B
All Ranges
Gain TC
Range A
Range B, Range C, and Range D
Range E
INL
Range A
Range B
Range C, Range D, and Range E
DUTGND Voltage Accuracy
MEASURE PIN DC
CHARACTERISTICS
Output Range
Output Impedance
Test Conditions/Comments
+3.5
+4.5
+300
After two-point gain/offset calibration at ±80% FS current
Measured over FSR output of −40 mA to +40 mA
Measured over FSR output of −1 mA to +1 mA
Measured over FSR output of Range C, Range D, and
Range E
Range B, FVMI, force −1.0 V and +4.0 V into 0.5 mA
load, measure ∆I reported at PPMU_Mx pin
Over ±0.1 V range
PPMU enabled in FVMV, source resistance: PPMU force
4.5 V into 0.0 mA, −1.0 mA, sink resistance: PPMU
force −1.5 V into 0.0 mA, 1.0 mA, resistance = ∆V/∆I at
PPMU_Mx pin
Tested at −1.7 V and +5.2 V
PPMU enabled in FVMV, source: PPMU force +4.5
V, PPMU_Mx = −1.5 V, sink: PPMU force −1.5 V,
PPMU_Mx = 5.0 V
Parasitic capacitance contributed by pin
External capacitance tolerated by pin (exceeding this
value may cause instability)
PPMU enabled in FIMI, PPMU clamps enabled; clamp
accuracy applies only when |PCHx − PCLx| ≥ 1.0 V
Range B, PPMU force ±0.5 mA into open; PCHx
measured at DAC Code 0x4000 (0.0 V) with PCLx at
DAC Code 0x0000 (−2.5 V); PCLx measured at DAC
Rev. C | 15 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 7.
Parameter
Min
Typ
Max
Unit
Test Level
Test Conditions/Comments
Code 0x4000 (0.0 V) with PCHx at DAC Code 0xFFFF
(+7.5 V)
Offset TC, Voltage Clamps (PCHx/
PCLx)
Gain, Voltage Clamps (PCHx/PCLx)
Gain TC, Voltage Clamps (PCHx/
PCLx)
INL, Voltage Clamps (PCHx/PCLx)
±0.5
1.0
1.1
±25
mV/°C
CT
V/V
P
ppm/°C
CT
Range B, PPMU force ±0.5 mA into open; PCHx gain
derived from measurements at DAC Code 0x4000 (0.0
V) and DAC Code 0x8CCC (3.0 V) with PCLx at
DAC Code 0x0000 (−2.5 V); PCLx gain derived from
measurements at DAC Code 0x4000 (0.0 V) and DAC
Code 0x8CCC (3.0 V) with PCHx at DAC Code 0xFFFF
(7.5 V)
−20
+20
mV
P
Positive Voltage Clamp, Voltage
Droop (Source)
−50
+50
mV
P
Negative Voltage Clamp, Voltage
Droop (Sink)
−50
+50
mV
P
DUTGND Voltage Accuracy
−5
+5
mV
P
−120
−20
%FS
S
20
120
%FS
S
−100
−30
%FS
D
30
100
%FS
D
±160
%FS
P
+10
%FSR
%FSR/°C
P
CT
For example, −100% FS in Range A is −40 mA and
−30% FS in Range A is −12 mA
For example, 30% FS in Range A is 12 mA and 100%
FS in Range A is 40 mA
PCLx at DAC Code 0x0000 (−2.5 V), PCHx at DAC
Code 0xFFFF (7.5 V), sink: force −1.5 V, short DUTx to
4.5 V, source: force 4.5 V, short DUTX to −1.5 V
All ranges; PPMU force ±1.0 V into 0.0 V1
All ranges
30
%
P
All ranges; PPMU force ±1.0 V into 0.0 V2
ppm/°C
CT
All ranges
%FSR
P
All ranges; PPMU force ±1.0 V into 0.0 V, after two-point
gain/offset calibration; PCHx calibration at DAC Code
0xA000 (3.75 V or 50% FS) and DAC Code 0xB333
(4.50 V or 80% FS); PCLx calibration at DAC Code
0x6000 (1.25 V or −50% FS) and DAC Code 0x4CCC
(0.50 V or −80% FS); measured over dc accuracy range
±1
PPMU CURRENT CLAMPS (FV)
Functional Range
Low Current Clamp (PCLx)
High Current Clamp (PCHx)
DC Accuracy Range
Low Current Clamp (PCLx)
High Current Clamp (PCHx)
Static Current Limit, Source and Sink, ±120
All Ranges
Offset, Current Clamps (PCHx/PCLx) −10
Offset TC, Current Clamps (PCHx/
PCLx)
Gain Error, Current Clamps (PCHx/
0
PCLx)
Gain TC, Current Clamps (PCHx/
PCLx)
INL, Current Clamps (PCHx/PCLx)
−0.15
analog.com
±140
±0.02
±50
+0.15
Range B, PPMU force ±0.5 mA into open after two-point
gain/offset calibration; measured over PPMU clamp
functional range
∆V at DUTx pin, Range A, PCHx = +4.0 V, PCLx = −1.0
V, PPMU force 5.0 mA and 40 mA into open circuit,
calibrated
∆V at DUTx pin, Range A, PCHx = +4.0 V, PCLx = −1.0
V, PPMU force −5.0 mA and −40 mA into open circuit,
calibrated
Over ±0.1 V range; measured at end points of clamp
functional range
PPMU enabled in FVMV, dc accuracy of the current
clamps only applies over the following conditions: 30%
FS ≤ PCHx ≤ 100% FS or −100% FS ≤ PCLx ≤ −30%
FS
For example, −120% FS in Range A is −48 mA and
−20% FS in Range A is −8 mA
For example, 20% FS in Range A is 8 mA and 120% FS
in Range A is 48 mA
Rev. C | 16 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 7.
Parameter
Current Droop
Low Current Clamp (PCLx), Sink
High Current Clamp (PCHx),
Source
SETTLING/SWITCHING TIMES
FV Settling Time to 0.1% of Final
Value
Range A, 200 pF and 2000 pF
Load
Range B, 200 pF and 2000 pF
Load
Range C, 200 pF Load
Range C, 2000 pF Load
FV Settling Time to 1.0% of Final
Value
Range A, 200 pF and 2000 pF
Load
Range B, 200 pF and 2000 pF
Load
Range C, 200 pF and 2000 pF
Load
FI Settling Time to 0.1% of Final
Value
Range A, 200 pF in Parallel with
120 Ω
Range B, 200 pF in Parallel with
1.5 kΩ
Range C, 200 pF in Parallel with
15.0 kΩ
FI Settling Time to 1.0% of Final
Value
Range A, 200 pF in Parallel with
120 Ω
Range B, 200 pF in Parallel with
1.5 kΩ
Range C, 200 pF in Parallel with
15.0 kΩ
INTERACTION AND CROSSTALK
Measure Voltage Channel to Channel
Crosstalk
Measure Current Channel to Channel
Crosstalk
analog.com
Min
Typ
Max
Unit
Test Level
Test Conditions/Comments
−2
+2
%FSR
P
−2
+2
%FSR
P
PCLx = 0.5 V (−80% FS), PCHx = 4.5 V (80% FS),
PPMU force −0.5 V and +3.5 V into VDUTx = 4.5 V,
measure ∆I at the DUTx pin in Range A
PCLx = 0.5 V (−80% FS), PCHx = 4.5 V (80% FS),
PPMU force −0.5 V and +3.5 V into VDUTx = −1.5 V,
measure ∆I at the DUTx pin in Range A
20
µs
S
PPMU enabled in FV, Range A, step from 0.0 V to 4.0 V
25
µs
S
25
µs
S
65
µs
S
PPMU enabled in FV, Range B, DCL disabled, step from
0.0 V to 4.0 V
PPMU enabled in FV, Range C, DCL disabled, step from
0.0 V to 4.0 V
PPMU enabled in FV, Range C, DCL disabled, step from
0.0 V to 4.0 V
16
µs
CB
14
µs
CB
18
µs
CB
16
µs
S
10
µs
S
40
µs
S
8
µs
CB
8
µs
CB
8
µs
CB
10
µV
CT
0.0001
%FSR
CT
PPMU enabled in FV, Range A, DCL disabled, step from
0.0 V to 4.0 V
PPMU enabled in FV, Range B, DCL disabled, step from
0.0 V to 4.0 V
PPMU enabled in FV, Range C, DCL disabled enabled,
step from 0.0 V to 4.0 V
PPMU enabled in FI, Range A, DCL disabled, step from
0.0 mA to 40 mA
PPMU enabled in FI, Range B, DCL disabled, step from
0.0 mA to 1 mA
PPMU enabled in FI, Range C, DCL disabled, step from
0.0 mA to 100 µA
PPMU enabled in FI, Range A, DCL disabled, step from
0.0 mA to 40 mA
PPMU enabled in FI, Range B, DCL disabled, step from
0.0 mA to 1 mA
PMU enabled in FI, Range C, DCL disabled, step from
0.0 mA to 100 µA
PPMU enabled in FIMV, Range B, channel under test:
force 0.0 mA into 0.0 V; other channel: force 0.0 mA into
VDUTx; sweep VDUTx from −1.5 V to +4.5 V; measure ∆V
at PPMU_Mx under test
PPMU enabled in FVMI, Range B; channel under test:
force 0.0 V into open circuit; other channel: force 0.0
V into IDUTx; sweep IDUTx from −1.0 mA to +1.0 mA;
measure ∆V at PPMU_Mx under test
Rev. C | 17 of 78
Data Sheet
ADATE320
SPECIFICATIONS
1
PCHx offset is derived from measurements at DAC Code 0xA000 (3.75 V or 50% FS) and DAC Code 0xB333 (4.50 V or 80% FS), with PCLx at DAC Code 0x0000 (−2.5
V). PCLx offset is derived from measurements at DAC Code 0x6000 (1.25 V or −50% FS) and DAC Code 0x4CCC (0.50 V or −80% FS), with PCHx at DAC Code 0xFFFF
(7.5 V).
2
PCHx gain is derived from the measurements at DAC Code 0xA000 (3.75 V or 50% FS) and DAC Code 0xB333 (4.50 V or 80% FS), with PCLx at DAC Code 0x0000
(−2.5 V). PCLx gain is derived from measurements at DAC Code 0x6000 (1.25 V or −50% FS) and DAC Code 0x4CCC (0.50 V or −80% FS), with PCHx at DAC Code
0xFFFF (7.5 V). For example, the ideal gain is ±FS per 2.5 V in all ranges; in Range B, the ideal gain is ±400 µA/V; therefore, 30% error is ±520 µA/V.
PPMU GO/NO-GO COMPARATORS SPECIFICATIONS
Table 8.
Parameter
DC SPECIFICATIONS
Compare Voltage Range
Input Offset Voltage
Input Offset Voltage TC
Gain
Min
Typ
−1.5
−250
Max
Unit
Test Level
+5.0
+250
V
mV
μV/°C
V/V
D
P
CT
P
±100
1.0
1.1
Gain TC
±10
ppm/°C
CT
Comparator Threshold Resolution
Comparator Threshold DNL
153
±250
µV
µV
D
CT
+7
mV
P
+5
mV
P
Comparator Threshold INL
−7
DUTGND Voltage Accuracy
−5
±1
Test Conditions/Comments
Measured at DAC Code 0x4000 (0 V)
Gain derived from measurements at DAC Code 0x4000 (0.0 V) and
DAC Code 0x8CCC (3.0 V)
Gain derived from measurements at DAC Code 0x4000 (0.0 V) and
DAC Code 0x8CCC (3.0 V)
After two-point calibration; measured over POHx/POLx range −1.5 V
to +5.0 V; calibration points DAC Code 0x4000 (0.0 V) and DAC Code
0x8CCC (3.0 V)
After two-point calibration; measured over POHx/POLx range −1.5 V
to +5.0 V; calibration points DAC Code 0x4000 (0.0 V) and DAC Code
0x8CCC (3.0 V)
Over ±0.1 V range
PPMU EXTERNAL SENSE PINS SPECIFICATIONS
Table 9.
Parameter
Min
Typ
Max
Unit
Test Level
Test Conditions/Comments
DC SPECIFICATIONS
Voltage Range
Leakage
Maximum Load Capacitance
−1.5
−2
2000
0.0
+4.5
+2
V
nA
pF
D
P
S
PPMU input select, in all states
Tested at −1.5 V and +4.5 V
Capacitive load tolerated at DUTx sense pins
VREF, VREFGND, AND DUTGND REFERENCE INPUT PINS SPECIFICATIONS
Table 10.
Parameter
DC SPECIFICATIONS
VREF Input Voltage Range
VREF Input Bias Current
DUTGND Input Voltage Range,
Referenced to AGND
DUTGND Input Bias Current
analog.com
Min
Typ
Max
Unit
Test Level
Test Conditions/Comments
2.475
2.500
V
µA
V
D
P
D
Provided externally, VREF = 2.500 V, VREFGND = 0.000 V
Tested with 2.500 V applied
−0.1
2.525
10
+0.1
−10
+10
µA
P
Tested at −100 mV and +100 mV
Rev. C | 18 of 78
Data Sheet
ADATE320
SPECIFICATIONS
TEMPERATURE MONITOR SPECIFICATIONS
Table 11.
Parameter
Min
DC SPECIFICATIONS
Temperature Sensor Gain
Temperature Sensor Accuracy
Typ
Max
10
±10
Unit
Test Level
Test Conditions/Comments
mV/K
°C
D
CT
3.00 V at room temperature, 300 K (23°C)
20°C < TC < 80°C, VCCTHERM only (TJ = TC)
ALARM FUNCTIONS SPECIFICATIONS
Table 12.
Parameter
Min
DC SPECIFICATIONS
Overvoltage Alarm High, OVDH
Functional Voltage Range
Uncalibrated Error at −1.0 V
Uncalibrated Error at 5.0 V
Offset Voltage TC
Gain
−1.0
−300
0
Max
Unit
Test Level
Test Conditions/Comments
+5.0
+200
500
D
P
P
CT
CT
OVDL DAC set to DAC Code 0x0000 (−2.5 V)
Includes 5% uncalibrated gain ±250 mV offset
Includes 5% uncalibrated gain ±250 mV offset
±0.5
1.05
V
mV
mV
mV/°C
V/V
140
mV
CT
±0.5
1.05
V
mV
mV
mV/°C
V/V
D
P
P
CT
CT
Hysteresis
Thermal Alarm
Setpoint Error
Thermal Hysteresis
ALARM Output Characteristics
Off State Leakage
140
mV
CT
±10
15
°C
°C
CT
CT
Relative to default alarm value, TJ = 100°C
10
500
nA
P
Maximum On Voltage at 200 µA
AC SPECIFICATIONS
Propagation Delay
0.1
0.7
V
P
Disable alarm, apply VDD to ALARM pin, and measure leakage
current
ALARM pin asserted, force 200 µA into pin and measure voltage
µs
CB
Hysteresis
Overvoltage Alarm Low, OVDL
Functional Voltage Range
Uncalibrated Error at −2.0 V
Uncalibrated Error at 4.0 V
Offset Voltage TC
Gain
Typ
−2.0
−350
−50
+4.0
+150
+450
0.5
Gain derived from measurements at DAC Code 0x4000 (0.0 V)
and DAC Code 0x8CCC (3.0 V); based on an ideal DAC transfer
function (see Table 24)
Hysteresis is only applied coming out of alarm
OVDH DAC set to DAC Code 0xFFFF (7.5 V)
Includes 5% uncalibrated gain ±250 mV offset
Includes 5% uncalibrated gain ±250 mV offset
Gain derived from measurements at DAC Code 0x4000 (0.0 V)
and DAC Code 0x8CCC (3.0 V); based on an ideal DAC transfer
function (see Table 24)
Hysteresis is only applied coming out of alarm
For OVDH: VDUTx = 0.0 V to 4.5 V step, OVDH = 4.0 V, OVDL =
−1.0 V; for OVDL: VDUTx = 0.0 V to −1.5 V step, OVDH = 4.0 V,
OVDL = −1.0 V
SERIAL PROGRAMMABLE INTERFACE (SPI) SPECIFICATIONS
Table 13.
Parameter
DC SPECIFICATIONS
Input Voltage
Logic High
Logic Low
analog.com
Min
Typ
Max
Unit
Test Level
Test Conditions/Comments
RST, CS, SCLK, SDI
VDD − 0.7
0.0
VDD
0.7
V
V
PF
PF
Rev. C | 19 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 13.
Parameter
Input Bias Current
SCLK Crosstalk on DUTx Pin
Serial Output
Logic High
Logic Low
BUSY Output Characteristics
Off State Leakage
Maximum On Voltage at 2 mA
Min
Typ
Max
Unit
Test Level
Test Conditions/Comments
−10
1
+10
µA
P
mV
CB
Tested at 0.0 V and VDD; RST tested at VDD; RST has an internal 50 kΩ
pull-up to VDD
DCL disabled, PPMU forcing 0.0 V
VDD
0.5
V
V
PF
PF
500
0.7
nA
V
P
P
1
VDD − 0.5
0.0
10
0.01
SDO, sourcing 2 mA
Sinking 2 mA
Open-drain output
BUSY pin not asserted, apply VDD to pin and measure leakage current
BUSY pin asserted, force 2 mA into pin and measure voltage
SPI TIMING SPECIFICATIONS
Table 14.
Parameter
Symbol
SCLK Operating Frequency
fCLK
Unit
Test Level
MHz
MHz
ns
ns
ns
ns
ns
ns
PF
S
S
S
S
S
S
S
tCH
tCL
tCSAS
tCSAH
tCSRS
tCSRH
0.5
4.5
4.5
1.5
1.5
1.5
1.5
100
SCLK High Time
SCLK Low Time
CS to SCLK Setup at Assert
CS to SCLK Hold at Assert
CS to SCLK Setup at Release
CS to SCLK Hold at Release
CS Assert to SDO Active
CS Release to SDO High-Z
tCSO
tCSZ
0
0
4
11
ns
ns
S
S
CS Release to Next Assert
tCSAM
3
Cycles
D
SDI to SCLK Setup
tDS
3
ns
S
SDI to SCLK Hold
tDH
4
ns
S
SCLK to Valid SDO
tDO
0
6
ns
S
BUSY Assert from CS/RST
tBUSA
0
6
ns
S
BUSY Width
Following CS
tBUSW
3
21
Cycles
D
Cycles
D
Following RST
analog.com
Min
Typ
Max
50
744
Description
Setup time of CS assert to next rising edge of SCLK.
Hold time of CS assert to next rising edge of SCLK.
Setup time of CS release to next rising edge of SCLK.
Hold time of CS release to next rising edge of SCLK.
This parameter is only critical if the number of SCLK
cycles from previous release of CS is the minimum
specified by the tCSAM parameter.
Delay time from CS assert to SDO active state.
Delay from CS release to SDO high-Z state, strongly
influenced by external SDO pin loading.
Minimum release time of CS between consecutive
assertions of CS. This parameter is specified in units of
SCLK cycles, more specifically in terms of rising edges
of the SCLK input.
Setup time of SDI data prior to next rising edge of
SCLK.
Hold time of SDI data following previous rising edge of
SCLK.
Propagation delay from rising edge of SCLK to valid
SDO data.
Propagation delay from first rising SCLK following valid
CS release (or RST release in the case of hardware
reset) to BUSY assert.
Delay time from first rising SCLK after valid CS release
to BUSY release. Satisfies the requirements detailed in
the SPI Clock Cycles and the BUSY Pin section, except
following RST or software reset.
Delay time from first rising SCLK after RST release (or
valid CS release in the case of software reset) to BUSY
release. Satisfies the requirement of synchronous reset
sequence detailed in the SPI Clock Cycles and the
BUSY Pin section.
Rev. C | 20 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Table 14.
Parameter
Symbol
Min
BUSY Release from SCLK
tBUSR
0
Width of Assert
tRMIN
RST to SCLK Setup at Assert
SCLK Cycles per SPI Word
Max
Unit
Test Level
Description
10
ns
S
5
ns
S
tRS
1.5
ns
S
tSPI
29
Cycles
D
µs
CB
Propagation delay from qualifying SCLK edge to BUSY
release.
Minimum width of asynchronous RST assert, 5 pF
external loading.
Minimum setup time of RST release to next rising edge
of SCLK.
Minimum number of SCLK rising edge cycles required
per valid SPI operation, including the minimum tCSAM
requirement between consecutive CS assertions.
Settling time of internal analog DAC levels to within ±2
mV. Settling time is relative to the release of BUSY.1
Internal DAC Settling to Within ±2 mV from tDAC
BUSY Release
1
Typ
10
The overall settling time may be dominated by the characteristics of an analog block (such as the PPMU or driver) and its respective mode setting (such as Range A or
Range B).
SPI TIMING DIAGRAMS
Figure 2. SPI Detailed Read/Write Timing Diagram
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Rev. C | 21 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Figure 3. SPI Write Instruction Timing Diagram
Figure 4. SPI Read Request Instruction Timing Diagram (Prior to Readout Instruction)
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Rev. C | 22 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Figure 5. SPI Readout Instruction Timing Diagram (Subsequent to Read Request Instruction)
Figure 6. SPI Detailed Hardware Reset Timing Diagram
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Rev. C | 23 of 78
Data Sheet
ADATE320
SPECIFICATIONS
Figure 7. SPI Detailed Software Reset Timing Diagram
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Rev. C | 24 of 78
Data Sheet
ADATE320
ABSOLUTE MAXIMUM RATINGS
Table 15.
Parameter
Rating
Supply Voltages
Positive Supply Voltage (VCC to PGND)
Positive Supply Voltage (VDD to DGND)
Negative Supply Voltage (VEE to PGND)
Supply Voltage Difference (VCC to VEE)
Reference Ground (DUTGND to AGND)
Supply Sequence or Dropout Condition
Input/Output Voltages
Digital Input Voltage Range
VREF Input Voltage Range
VREFGND, DUTGND Input Voltage Range
DUTx Output Short-Circuit Voltage1
High Speed Termination (VTTCx, VTTDx) Input
Voltage Range
High Speed DATx/RCVx Common-Mode Input
Voltage Range2
High Speed DATx/RCVx Differential Mode Input
Voltage Range2
High Speed CMPHx/CHPLx, PPMU_ CMPHx/
PPMU_CMPLx Absolute Output Voltage Range
DUTx Input/Output Pin Current Limit
DCL Maximum Short-Circuit Current3
Operating Temperature, Junction
Storage Temperature Range
−0.5 V to +9.0 V
−0.5 V to +2.2 V
−6.0 V to +0.5 V
−1.0 V to +15.0 V
−0.5 V to +0.5 V
No limitations
−0.5 V to VDD + 0.5 V
−0.5 V to +3.5 V
−0.5 V to +0.5 V
−3.0 V to +6.0 V
−0.5 V to +2.2 V
−0.5 V to +2.2 V
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 16. Thermal Resistance
Package Type
Airflow Velocity (m/sec)
θJA
θJC
Unit
84-Lead LFCSP
N/A1
N/A1
0
1
2
45
40
37
3.2
N/A1
N/A1
N/A1
°C/W
°C/W
°C/W
°C/W
1
N/A means not applicable.
−1.0 V to +1.0 V
EXPLANATION OF TEST LEVELS
−0.5 V to +2.2 V
D Definition.
S Design verification simulation.
±120 mA
125°C
−65°C to +150°C
1
RL = 0 Ω, VDUTx continuous short-circuit condition (VIH, VIL, VIT), high-Z,
VCOM, and all clamp modes.
2
DATx, DATx, RCVx, RCVx, RSOURCE = 0 Ω, no pin to exceed either maximum
common-mode input range or differential mode input range.
3
RL = 0 Ω, VDUTx = −3 V to +6 V; DCL current limit. Continuous short-circuit
condition. The ADATE320 is designed to withstand continuous short-circuit
fault.
P 100% production tested.
PF Functionally checked during production test.
CT Characterized on tester.
CB Characterized on bench.
USER INFORMATION AND TRUTH TABLES
Table 17. Driver Truth Table
DRV Control Register1
High Speed Inputs2
DRIVE_ENABLE_x,
Address 0x19, Bit 0
DRIVE_FORCE_x,
Address 0x19, Bit 1
DRIVE_FORCE_STATE_x,
Address 0x19, Bits[3:2]
DRIVE_VT_HIZ_x,
Address 0x19, Bit 4
DATx
RCVx
Driver State
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
0
0
XX
00
01
10
11
XX
XX
XX
XX
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
1
1
0
0
Low leakage
Active VIL
Active VIH
Active high-Z
Active VIT
Active high-Z
Active VIT
Active VIL
Active VIH
1
X means don’t care.
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Rev. C | 25 of 78
Data Sheet
ADATE320
ABSOLUTE MAXIMUM RATINGS
2
See Figure 138 for more detailed information about high speed DATx/RCVx input multiplexing.
Table 18. Comparator Truth Table
Comparator State
DMC_ENABLE, Address
0x1A, Bit 0
0
11
1
CMPH0
State
CMPL0
State
CMPH1
State
CMPL1
State
VDUT0 < VOH0
VOH0 < VDUT0
VDUT0 − VDUT1 < VOH0
VOH0 < VDUT0 − VDUT1
0
1
0
1
VDUT0 < VOL0
VOL0 < VDUT0
VDUT0 − VDUT1 < VOL0
VOL0 < VDUT0 − VDUT1
0
1
0
1
VDUT1 < VOH1
VOH1 < VDUT1
VDUT1 < VOH1
VOH1 < VDUT1
0
1
0
1
VDUT1 < VOL1
VOL1 < VDUT1
VDUT1 < VOL1
VOL1 < VDUT1
0
1
0
1
Note that the Channel 1 normal window comparator continues to function while the device is in differential compare mode, but at a greatly reduced bandwidth.
Table 19. Active Load Truth Table
LOAD/DRV Control Registers1
High Speed Inputs2
LOAD_ENABLE_x,
Address 0x1B, Bit 0
LOAD_FORCE_x,
Address 0x1B, Bit 1
DRIVE_VT_HIZ_x, Address 0x19, Bit 4
DATx
RCVx
Load State
0
1
1
1
1
X
1
0
0
0
X
X
X
0
1
X
X
X
X
X
X
X
0
1
1
Low leakage
Active on
Active off
Active on
Active off
1
X means don’t care.
2
See Figure 138 for more detailed information about high speed DATx/RCVx input multiplexing.
Table 20. PPMU Go/No-Go Comparator Truth Table
PPMU Control Register1
PPMU Go/No-Go Comparator State2
PPMU_ENABLE_x, Address
0x1C, Bit 0
PPMU_STANDBY_x, Address
0x1C, Bit 1
PPMU_CMPHx
State
PPMU_CMPLx
State
0
1
1
X
X
X
X
PPMUx MV/MI < POHx
POHx < PPMUx MV/MI
0
0
1
X
PPMUx MV/MI < POLx
POLx < PPMUx MV/MI
0
0
1
1
X means don’t care.
2
The PPMUx MV/MI inputs to the PPMU go/no-go comparators always come directly from the respective internal PPMU instrumentation amplifiers, not from the PPMU_Mx
output pins (see Figure 143). The internal instrumentation amplifiers are independently configured for either measure voltage (MV) or measure current (MI), depending on
the settings of the PPMU_MEAS_VI_x control bit, as described in Figure 150. When PPMU power is not enabled, the respective go/no-go comparator outputs are locked to
a static low state (see Table 21).
Table 21. PPMU Measure Pin Truth Table
PPMU Control Register1
PPMU_ENABLE_x,
Address 0x1C, Bit 0
PPMU_STANDBY_x,
Address 0x1C, Bit 1
PPMU_MEAS_ENABLE_x,
Address 0x1C, Bit 13
PPMU_MEAS_SEL_x,
Address 0x1C, Bit 14
PPMU_MEAS_VI_x,
Address 0x1C, Bit 6
PPMU_Mx, Pin
State
X
0
0
1
1
1
X
X
X
X
X
X
0
1
1
1
1
1
X
0
1
0
0
1
X
X
X
0
1
X
High-Z
Active MV
Active VTHERM2
Active MV
Active MI
Active VTHERM2
1
X means don’t care.
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Rev. C | 26 of 78
Data Sheet
ADATE320
ABSOLUTE MAXIMUM RATINGS
2
When applicable, PPMU_M0 is connected to the internal temperature sensor node (VTHERM), and PPMU_M1 is connected to the internal temperature sensor reference
ground node (AGND) (see Figure 143).
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
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Rev. C | 27 of 78
Data Sheet
ADATE320
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 8. Pin Configuration
Table 22. Pin Function Descriptions
Pin No.
Mnemonic
Description
59
58
57
55
56
5
6
7
9
8
53
52
51
49
50
11
12
13
15
14
61
62
65
41
38
39
3
2
83
DAT0
DAT0
VTTD0
RCV0
RCV0
DAT1
DAT1
VTTD1
RCV1
RCV1
CMPL0
CMPL0
VTTC0
CMPH0
CMPH0
CMPL1
CMPL1
VTTC1
CMPH1
CMPH1
CFFA0
CFFB0
PPMU_S0
PPMU_M0
PPMU_CMPL0
PPMU_CMPH0
CFFA1
CFFB1
PPMU_S1
Driver High Speed Data Input, Channel 0.
Driver High Speed Data Input Complement, Channel 0.
Driver High Speed Input Termination, Channel 0.
Driver High Speed Receive Input, Channel 0.
Driver High Speed Receive Input Complement, Channel 0.
Driver High Speed Data Input, Channel 1.
Driver High Speed Data Input Complement, Channel 1.
Driver High Speed Input Termination, Channel 1.
Driver High Speed Receive Input, Channel 1.
Driver High Speed Receive Input Complement, Channel 1.
Comparator High Speed Output Low, Channel 0.
Comparator High Speed Output Low Complement, Channel 0.
Comparator High Speed Output Termination, Channel 0.
Comparator High Speed Output High, Channel 0.
Comparator High Speed Output High Complement, Channel 0.
Comparator High Speed Output Low, Channel 1.
Comparator High Speed Output Low Complement, Channel 1.
Comparator High Speed Output Termination, Channel 1.
Comparator High Speed Output High, Channel 1.
Comparator High Speed Output High Complement, Channel 1.
PPMU External Compensation Capacitor Pin A, Channel 0.
PPMU External Compensation Capacitor Pin B, Channel 0.
PPMU External Sense Connect, Channel 0.
PPMU Analog Measure Output, Channel 0.
PPMU Go/No-Go Comparator Output Low, Channel 0.
PPMU Go/No-Go Comparator Output High, Channel 0.
PPMU External Compensation Capacitor Pin A, Channel 1.
PPMU External Compensation Capacitor Pin B, Channel 1.
PPMU External Sense Connect, Channel 1.
analog.com
Rev. C | 28 of 78
Data Sheet
ADATE320
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 22. Pin Function Descriptions
Pin No.
Mnemonic
Description
23
26
25
34
32
30
33
31
29
35
19
20
24
68
80
45
44
16, 48, 66, 67, 72, 76, 81, 82
27, 37
22, 40, 42, 74
28, 36
4, 10, 18, 21, 43, 46, 54, 60, 71, 77
17, 47, 64, 69, 70, 73, 75, 78, 79, 84
1, 63
PPMU_M1
PPMU_CMPL1
PPMU_CMPH1
RST
SCLK
CS
SDI
SDO
ALARM
BUSY
VREF
VREFGND
DUTGND
DUT0
DUT1
VCCTHERM
VTHERM
VCC, VCCD0, VCCD1
VDD
AGND
DGND
PGND
VEE, VEED0, VEED1
NC
EP
PPMU Analog Measure Output, Channel 1.
PPMU Go/No-Go Comparator Output Low, Channel 1.
PPMU Go/No-Go Comparator Output High, Channel 1.
Reset Input (Active Low).
Serial Programmable Interface (SPI) Clock Input.
Serial Programmable Interface (SPI) Chip Select Input (Active Low).
Serial Programmable Interface (SPI) Serial Data Input.
Serial Programmable Interface (SPI) Serial Data Output.
Fault Alarm Open-Drain Output (Open-Collector, Active Low).
Serial Programmable Interface (SPI) Busy Output (Open-Collector, Active Low).
DAC Precision 2.500 V Reference Input.
DAC Precision 0.000 V Reference Input.
DUT Ground Sense Input.
DUT Pin, Channel 0.
DUT Pin, Channel 1.
Temperature Sensor VCC Supply (8.0 V).
Temperature Sensor Analog Output.
Analog Supply (8.0 V).
Digital Supply (1.8 V).
Analog Ground (Quiet).
Digital Ground.
Power Ground.
Analog Supply (−5.0 V).
No Connect. These pins can be grounded or left floating.
Exposed Pad. The exposed pad is internally connected via a high impedance die attached to VEE
(substrate).
analog.com
Rev. C | 29 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. DUTx Pin Leakage in High-Z Mode
Figure 12. DUTx Pin Time-Domain Reflectometry (TDR) Response
Figure 10. DUTx Pin Leakage in Low Leakage Mode
Figure 13. Driver Offset vs. Driver CLC Setting, 3-Bit Value
Figure 11. Driver Output Resistance vs. Driver Output Current
Figure 14. Driver VIH INL
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Rev. C | 30 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15. Driver VIL INL
Figure 18. Driver VIL Interaction Error vs. VIH Programmed DAC Voltage
Figure 16. Driver VIT INL
Figure 19. Driver VIT Interaction Error vs. VIH Programmed DAC Voltage
Figure 17. Driver VIH Interaction Error vs. VIL Programmed DAC Voltage
Figure 20. Driver VIT Interaction Error vs. VIL Programmed DAC Voltage
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Rev. C | 31 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 21. Driver Output Current Limit, Sink
Figure 24. Driver Large Swing Response
Figure 22. Driver Output Current Limit, Source
Figure 25. Driver 100 MHz Response, Small Swing
Figure 23. Driver Small Swing Response
Figure 26. Driver 100 MHz Response, Large Swing
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Rev. C | 32 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 27. Driver 800 MHz Response, Small Swing
Figure 30. Driver 1.25 GHz Response, Large Swing
Figure 28. Driver 800 MHz Response, Large Swing
Figure 31. Driver VIL/VIH to/from VIT, VIH = 2.0 V, VIL = 0.0 V, VIT = 1.0 V; 50 Ω
Terminated
Figure 29. Driver 1.25 GHz Response, Small Swing
Figure 32. Driver VIL/VIH to/from High-Z, VIH = 1.0 V, VIL = −1.0 V; 50 Ω
Terminated
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Rev. C | 33 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 33. Driver to/from High-Z Transient Spike, VIH = VIL = 0.0 V; 50 Ω
Terminated
Figure 36. Driver Pulse Width (Positive/Negative) Trailing Edge Timing Error,
VIH = 1.0 V, 2.0 V; VIL = 0.0 V; CLC = Midscale; 50 Ω Terminated
Figure 34. Driver Transition vs. CLC, VIH = 1.0 V, VIL = 0.0 V; 50 Ω Terminated
Figure 37. Driver Eye Diagram, 800 Mbps, PRBS31, VIH = 50 mV, VIL = 0.0 V;
50 Ω Terminated
Figure 35. Driver Pulse Width (Positive/Negative) Trailing Edge Timing Error,
VIH = 0.2 V, 0.5 V; VIL = 0.0 V; CLC = Midscale; 50 Ω Terminated
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Figure 38. Driver Eye Diagram, 800 Mbps, PRBS31, VIH = 1.0 V, VIL = 0.0 V;
50 Ω Terminated
Rev. C | 34 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 39. Driver Eye Diagram, 2.5 Gbps, PRBS31, VIH = 50 mV, VIL = 0.0 V;
50 Ω Terminated
Figure 42. Driver Eye Diagram, 4.0 Gbps, PRBS31, VIH = 1.0 V, VIL = 0.0 V;
50 Ω Terminated
Figure 40. Driver Eye Diagram, 2.5 Gbps, PRBS31, VIH = 1.0 V, VIL = 0.0 V;
50 Ω Terminated
Figure 43. Reflection Clamp VCLx INL
Figure 44. Reflection Clamp VCHx INL
Figure 41. Driver Eye Diagram, 4.0 Gbps, PRBS31, VIH = 50 mV, VIL = 0.0 V;
50 Ω Terminated
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Rev. C | 35 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 45. Reflection Clamp Current Limit, VCHx = 5.0 V, VCLx = 4.0 V; VDUTx
Swept from −2.0 V to +5.0 V
Figure 48. Differential Mode Comparator Threshold INL
Figure 49. Differential Mode Comparator Common-Mode Rejection Error
Figure 46. Reflection Clamp Current Limit, VCHx = −1.0 V, VCLx = −2.0 V;
VDUTx Swept from −2.0 V to +5.0 V
Figure 50. Normal Window Comparator Offset Error vs. CLC Setting
Figure 47. Normal Window Comparator Threshold INL
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Rev. C | 36 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 51. Differential Mode Comparator Offset Error vs. CLC Setting
Figure 54. Comparator CML Output Waveform (ADATE320)
Figure 52. Normal Window Comparator Hysteresis vs. Programmed
Hysteresis Value
Figure 55. Comparator CML Output Waveform (ADATE320-1)
Figure 53. Differential Mode Comparator Hysteresis vs. Programmed
Hysteresis Value
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Figure 56. Normal Window Comparator Propagation Delay vs. Input Rise
Time, 1.0 V Input Swing
Rev. C | 37 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 57. Normal Window Comparator Pulse Width (Positive/Negative)
Trailing Edge Timing Error, 1.0 V Input Swing
Figure 60. Normal Window Comparator Eye Diagram, 800 Mbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
Figure 58. Normal Window Comparator Equivalent Rise Time (ERT), 1.0 V
Input Swing, 50 ps 20% to 80%; 50 Ω Terminated
Figure 61. Normal Window Comparator Eye Diagram, 2.5 Gbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
Figure 59. Normal Window Comparator Equivalent Fall Time (EFT), 1.0 V
Input Swing, 50 ps 20% to 80%; 50 Ω Terminated
Figure 62. Normal Window Comparator Eye Diagram, 4.0 Gbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
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Rev. C | 38 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 63. Differential Mode Comparator Eye Diagram, 800 Mbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
Figure 66. Active Load VCOM INL
Figure 67. Active Load IOHx/IOLx Transfer Function
Figure 64. Differential Mode Comparator Eye Diagram, 2.5 Gbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
Figure 68. Active Load IOHx INL
Figure 65. Differential Mode Comparator Eye Diagram, 4.0 Gbps, PRBS31,
1.0 V Input Swing; 50 Ω Terminated
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Rev. C | 39 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 69. Active Load IOLx INL
Figure 72. Active Load IOHx to/from Driver Transient Response, VIH = VIL =
0.0 V, IOHx = IOLx = 20 mA; 50 Ω Terminated
Figure 70. Active Load Commutation Response, VCOM = 2.0 V
Figure 73. PPMU Force Voltage INL, All Ranges
Figure 71. Active Load to/from Driver Input/Output Spike, VIH = VIL = 0.0 V,
IOHx = IOLx = 0.0 mA; 50 Ω Terminated
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Figure 74. PPMU Force Voltage Output Current Limit, Range A, FV = −1.5 V,
VDUTx Swept −2.0 V to +5.0 V
Rev. C | 40 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 75. PPMU Force Voltage Output Current Limit, Range A, FV = 4.5 V,
VDUTx Swept −2.0 V to +5.0 V
Figure 78. PPMU Force Voltage Compliance Error, Range A, FV = −1.0 V vs.
Output Current, Internal Sense
Figure 76. PPMU Force Voltage Output Current Limit, Range E, FV = −1.5 V,
VDUTx Swept −2.0 V to +5.0 V
Figure 79. PPMU Force Voltage Compliance Error, Range A, FV = 4.0 V vs.
Output Current (IDUTx) , Internal Sense
Figure 77. PPMU Force Voltage Output Current Limit, Range E, FV = 4.5 V,
VDUTx Swept −2.0 V to +5.0 V
Figure 80. PPMU Force Voltage Compliance Error, Range B, FV = −1.5 V vs.
Output Current(IDUTx), Internal Sense
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Rev. C | 41 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 81. PPMU Force Voltage Compliance Error, Range B, FV = 4.5 V vs.
Output Current (IDUTx), Internal Sense
Figure 84. PPMU Force Current INL, Range C
Figure 85. PPMU Force Current INL, Range D
Figure 82. PPMU Force Current INL, Range A
Figure 86. PPMU Force Current INL, Range E
Figure 83. PPMU Force Current INL, Range B
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Rev. C | 42 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 87. PPMU Force Current Compliance Error, Range A, FI = −40 mA vs.
Output Voltage (VDUTx)
Figure 90. PPMU Force Current Compliance Error, Range B, FI = 1 mA vs.
Output Voltage (VDUTx)
Figure 88. PPMU Force Current Compliance Error, Range A, FI = 40 mA vs.
Output Voltage (VDUTx)
Figure 91. PPMU Force Current Compliance Error, Range C, FI = −100 µA vs.
Output Voltage (VDUTx)
Figure 89. PPMU Force Current Compliance Error, Range B, FI = −1 mA vs.
Output Voltage (VDUTx)
Figure 92. PPMU Force Current Compliance Error, Range C, FI = 100 µA vs.
Output Voltage (VDUTx)
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Rev. C | 43 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 93. PPMU Force Current Compliance Error, Range E, FI = −2 µA vs.
Output Voltage (VDUTx)
Figure 96. PPMU Voltage Clamp PCHx INL
Figure 97. PPMU Current Clamp PCLx INL, Range A
Figure 94. PPMU Force Current Compliance Error, Range E, FI = 2 µA vs.
Output Voltage (VDUTx)
Figure 98. PPMU Current Clamp PCHx INL, Range A
Figure 95. PPMU Voltage Clamp PCLx INL
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Rev. C | 44 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 99. PPMU Current Clamp PCLx INL, Range B
Figure 102. PPMU Current Clamp PCHx INL, Range C
Figure 100. PPMU Current Clamp PCHx INL, Range B
Figure 103. PPMU Current Clamp PCLx INL, Range D
Figure 101. PPMU Current Clamp PCLx INL, Range C
Figure 104. PPMU Current Clamp PCHx INL, Range D
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Rev. C | 45 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 105. PPMU Current Clamp PCLx INL, Range E
Figure 106. PPMU Current Clamp PCHx INL, Range E
Figure 108. PPMU Measure Current INL, Range B
Figure 109. PPMU Measure Current Common-Mode Rejection Error, Force
Voltage Measure Current (FVMI), Source 0.5 mA
Figure 107. PPMU Measure Voltage INL, Range B
Figure 110. PPMU Force Voltage Transient Response, Range A, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 200 pF
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Rev. C | 46 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 111. PPMU Force Voltage Transient Response, Range B, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 200 pF
Figure 114. PPMU Force Voltage Transient Response, Range B, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 2000 pF
Figure 112. PPMU Force Voltage Transient Response, Range C, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 200 pF
Figure 115. PPMU Force Voltage Transient Response, Range C, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 2000 pF
Figure 113. PPMU Force Voltage Transient Response, Range A, 0.0 V to 0.5 V,
Uncalibrated, CLOAD = 2000 pF
Figure 116. PPMU Force Voltage Transient Response, Range A, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 200 pF
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Rev. C | 47 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 117. PPMU Force Voltage Transient Response, Range B, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 200 pF
Figure 120. PPMU Force Voltage Transient Response, Range B, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 2000 pF
Figure 118. PPMU Force Voltage Transient Response, Range C, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 200 pF
Figure 121. PPMU Force Voltage Transient Response, Range C, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 2000 pF
Figure 119. PPMU Force Voltage Transient Response, Range A, 0.0 V to 4.0 V,
Uncalibrated, CLOAD = 2000 pF
Figure 122. PPMU Force Current Transient Response, Range A, Full-Scale
Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 127 Ω
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Rev. C | 48 of 78
Data Sheet
ADATE320
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 123. PPMU Force Current Transient Response, Range B, Full-Scale
Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 1.8 kΩ
Figure 126. Typical DUTGND Transfer Function Voltage Error, Drive Low, VIL
= 0.0 V
Figure 124. PPMU Force Current Transient Response, Range C, Full-Scale
Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 18.5 kΩ
Figure 125. PPMU Go/No-Go Comparator Threshold INL
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Rev. C | 49 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
SERIAL PROGRAMMABLE INTERFACE (SPI)
SPI Hardware Interconnect Details
Figure 127. Multiple SPI with a Shared SDO Line
SPI Reset Sequence and the RST Pin
The internal state of the ADATE320 is indeterminate following power-up. For this reason, it is necessary to perform a valid hardware
reset sequence as soon as the power supplies are stabilized.
The ADATE320 provides an active low reset pin (RST) for this
purpose. Asserting RST asynchronously initiates a reset sequence.
Furthermore, the RST pin must be asserted before and during
the power-up cycling sequence, and released only after all power
supplies are guaranteed to be stable.
A soft reset sequence can also be initiated under SPI software
control by writing to the SPI_RESET bit (see Figure 146). In the
case of a soft reset, the sequence begins on the first rising edge of
SCLK following the release of CS, subject to the normal setup and
hold times. Certain actions occur immediately upon the initiation of
the reset request, whereas other actions require several cycles of
SCLK.
The following asynchronous actions occur immediately following the
detection of the reset request, whether it was hardware (RST) or
software (SPI) initiated:
►
►
►
►
►
Assert open-drain BUSY pin
Force all control registers to their default reset states as defined
in Table 29
Clear all calibration registers to their default reset states as
defined in Table 29
Override all DAC analog outputs and force dc levels to VDUTGND,
disable the driver and PPMU functions
Enable active loads with IOHx = IOLx = 100 µA (uncalibrated
and expected to vary with offset from device to device); soft
connect DUTx pins to VCOM = VDUTGND
The device remains in this static reset state indefinitely until the
clocked portion of the sequence begins with either the first rising
edge of SCLK following the release of RST in the case of an
asynchronous hardware reset, or the second rising edge of SCLK
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following the release of CS in the case of a software SPI reset.
Regardless of how the reset sequence was initiated, the clocked
portion of the sequence requires 744 SCLK cycles to run through
to completion, and the open-drain BUSY pin (if available) remains
asserted until all clock cycles are received. The following actions
occur during the clocked portion of the reset sequence:
Complete initialization of internal SPI controller
Write default values to appropriate DAC X2 registers
► Enable the thermal alarm with a 100°C threshold
► Disable the PPMU clamp and overvoltage detect (OVD) alarms
►
►
The 744 rising edges of SCLK release BUSY and start a self timed
DAC deglitch period of approximately 3 µs. DAC voltages begin to
change as soon as the deglitch circuits time out. An additional 10
µs is required to settle to the final values. A full reset sequence thus
requires approximately 30 µs, comprising 16 µs (744 cycles × 20
ns) for post reset initialization, 3 µs for DAC deglitch, and another
10 µs for DAC analog level settling.
SPI Clock Cycles and the BUSY Pin
The ADATE320 offers a digital BUSY output pin to indicate that the
SPI controller requires more SCLK cycles to be input on the SCLK
pin. The device may be operated without this pin, but care must be
exercised to ensure that the required number of SCLK cycles are
provided in each case to complete each SPI instruction.
After any valid SPI instruction is written to the ADATE320, the
BUSY pin is asserted to indicate a busy status of the DAC update
and calibration routines. The BUSY pin is an open-drain output
capable of sinking a minimum of 2 mA from the VDD supply. It is
recommended to tie the BUSY pin to VDD with an external 1 kΩ
pull-up resistor.
It is not a requirement to wait for release of BUSY prior to a subsequent assertion of the CS pin. As long as the minimum number of
Rev. C | 50 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
SCLK cycles following the previous release of CS is met according
to the tCSAM parameter, the CS pin can again be asserted for
another SPI operation. With the one exception of recovery from a
reset request (either by hardware assertion of RST pin or software
setting of the internal SPI_RESET control bit), there is no scenario
in normal operation of the ADATE320 in which the user must wait
for release of BUSY before asserting the CS pin for a subsequent
SPI operation. The only requirement on the assertion of CS is that
the tCSAM parameter has been met as defined in Figure 2 and Table
14.
It is very important, however, that the SCLK pin continue to operate
for as long as the BUSY pin state remains active. This period of
time is defined by the parameter tBUSW and is defined in Figure 2,
Table 14, and Table 23. If the SCLK pin does not remain active
for at least the number of cycles specified, operations pending to
the internal processor may not fully complete. In such a case, a
temporary malfunction of the ADATE320 may occur, or unexpected
results may be obtained. After the device releases the BUSY pin
(or the required minimum number of clock cycles is satisfied), SCLK
may again be stopped to prevent any unwanted digital noise from
coupling into the analog functions. In every case (with no exception
for reset recovery), it is the purpose of the BUSY pin to notify the
supervisory ASIC or FGPA that it is again safe to stop the SCLK
signal. Running SCLK for extra periods when BUSY is not active
is never a problem except for the possibility of adding unwanted
digital switching noise into analog functions.
The required length of the BUSY period (tBUSW) is variable depending on the particular preceding SPI instruction, but it is always deterministic. It depends only on factors such as whether the previous
instruction involved a write to one or more DAC addresses, and, if
so, how many channels were involved and whether calibration was
enabled. Table 23 details the length of the tBUSW requirement in
units of rising edge SCLK cycles for each possible SPI instruction
scenario, including recovery from a hardware RST reset.
Because tBUSW is deterministic, it is therefore possible to predict
in advance the minimum number of rising edge SCLK cycles that
are required to complete any given SPI instruction, which makes it
possible to operate the device without a need to monitor the BUSY
pin. For applications in which it is neither possible nor desirable to
monitor the pin, it is acceptable to use the deterministic information
provided in Table 23 to guarantee the minimum number of cycles is
provided. Either way, it is necessary to honor the minimum number
of required rising edge SCLK cycles, as defined by tBUSW, following
the release of CS for each of the SPI instruction scenarios listed.
Table 23. BUSY Minimum SCLK Cycle Requirements
SPI Instruction Type (Single- or Dual-Channel Operation)
Minimum tBUSW (SCLK Cycles)
Following Release of Asynchronous RST Reset Pin (Hardware Reset)
744
Following Assertion of the SPI_RESET Control Bit (Software Reset)
744
Write to No Operation (NOP) (Address 0x00, Address 0x20, Address 0x50, Address 0x60)
3
Write to a Valid Address That Is Not a DAC (Address > 0x10)
3
Write to Any DAC Except VILx or VIHx (Address 0x01 to Address 0x0F, Except Address 0x01 and Address 0x03)
18
Write to VILx or VIHx DAC (Address 0x01 or Address 0x03)
21
SPI Read/Write Register Definition
Figure 128. SPI Word Definition
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Rev. C | 51 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
The ADATE320 is configured through a collection of 16-bit registers
as defined in Table 29. Mode configuration, DAC level settings,
calibration constants, and alarm flags status can all be controlled
and monitored by accessing the respective registers.
Specific access to any 16-bit register is made through a serial programmable interface (SPI). A single SPI control register is exposed
to the user by this hardware SPI interface. The format of the SPI
Control Register is illustrated in Figure 128. The SPI control register
includes address and channel information, read/write direction, and
a 16-bit data field. Any valid SPI write instruction cycle populates
all these fields, and the ADATE320 subsequently operates on the
addressed channel and register using the data provided. Any valid
SPI read instruction cycle populates only the address and channel
fields, and the ADATE320 makes the addressed register contents
in the 16-bit data field available for subsequent readout at the SDO
pin.
Detailed SPI timing diagrams for each read/write operation type are
provided in Figure 2 through Figure 7. Respective dc and ac timing
parameters are provided in Table 13 and Table 14, respectively.
A typical hardware wiring diagram for the SPI is illustrated in Figure
127.
LEVEL SETTING DACS
DAC Update Modes
The ADATE320 provides 32 16-bit integrated level setting DACs
organized as two channel banks of 16 DACs each. The detailed
mapping of each DAC register to each pin electronics function is
shown in Table 29. Each DAC can be individually programmed by
writing data to the respective SPI register address and channel.
The ADATE320 provides two methods for updating analog DAC
levels: DAC immediate update mode and DAC deferred update
mode. At the release of the CS pin associated with any valid SPI
write to a DAC address, the update of the analog levels can start
immediately or can be deferred, depending on the state of the
DAC_LOAD_MODE control bit in the DAC control register (see
Figure 145). Initiation of the analog level update sequence (and
triggering of the on-chip deglitch circuit) begins four SCLK cycles
following the associated release of CS pin. For the purpose of this
data sheet, the analog level update sequence is assumed to start
coincident with the release of CS. The DAC update mode can be
selected independently for each channel bank.
If the DAC_LOAD_MODE control bit for a given channel bank is
cleared, the DACs assigned to that channel bank are placed in
the DAC immediate update mode. Writing to any DAC within that
channel causes the corresponding analog levels to be updated
immediately following the associated release of CS. Because all
analog levels are updated on a per channel basis, any previously
pending DAC writes queued to that channel (while in an earlier
deferred update mode) are also updated at this time. This situation
can arise if DAC writes are queued to the channel while in deferred
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update mode, and then the DAC_LOAD_MODE bit is subsequently
changed to immediate update mode before writing to the respective
DAC_LOAD control bit (see Figure 145). The queued data is not
lost. Note that writing to the DAC_LOAD control bit has no effect
while in immediate update mode.
If the DAC_LOAD_MODE control bit for a given channel is set, then
the DACs assigned to that channel bank is in the deferred update
mode. Writing to any DAC of that channel only queues the DAC
data into that channel. The analog update of queued DAC levels
is deferred until the respective DAC_LOAD control bit is set (see
Figure 145). The DAC deferred update mode, in conjunction with
the respective DAC_LOAD control bit, provides the means to queue
all DAC level writes to a given channel bank before synchronously
updating the analog levels with a single SPI command.
The OVDH and OVDL DAC levels do not fit neatly within a particular channel bank. However, they must be updated as a part of the
channel bank to which they are assigned, as shown in Table 29.
The ADATE320 provides a feature in which a single SPI write
operation can address two channels at one time. With this feature,
a single SPI write operation can address corresponding DACs on
both channels at the same time, even though the channels may
be configured with different DAC update modes. In such a case,
the device behaves as expected. For example, if both channels
are in immediate update mode, the update of analog levels of both
channel banks begins following the associated release of the CS
pin. If both channels are in deferred update mode, the update of
analog levels is deferred for both channels until the corresponding
DAC_ LOAD control bit is set. If one channel is in deferred update
mode and the other is in immediate update mode, the deferred
channel defers analog updates until the corresponding DAC_LOAD
bit is written, and the immediate channel begins analog updates
immediately following release of the CS pin.
An on-chip deglitch circuit with a period of approximately 3 µs is
provided to prevent DAC-to-DAC crosstalk within a channel whenever an analog update is processed. Each DAC channel bank has
its own dedicated deglitch circuitry, and each channel may therefore
operate independently.
A deglitch circuit can be retriggered if an analog level update
is initiated before a previous update operation on that channel
completes. Analog transitions at the DAC outputs do not begin until
after the deglitch circuit times out. Final settling to full precision
requires an additional 7 µs beyond the end of the 3 µs deglitch
interval. The total DAC settling time following the release of the
associated CS pin is approximately 10 µs maximum. Note that
an extended retriggering sequence of the deglitch circuit on one
channel may cause the apparent settling time of analog levels on
that channel to appear delayed longer than the specified 10 µs.
A typical DAC update sequence is illustrated in Figure 129. In this
example, consecutive immediate mode DAC updates are written in
direct succession. This example was chosen to illustrate what hapRev. C | 52 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
pens when a DAC update command is written before the previous
update command finishes its deglitch and settling sequence.
Figure 129. SPI DAC Write Timing Diagram and Settling of DC Levels
DAC Levels and VTHERM Pin Transfer Function
Table 24. Detailed DAC Code to/from Voltage Level Transfer Functions
Programmable Range
(0x0000 to 0xFFFF)
Level
DAC-to-Level and Level-to-DAC Transfer Functions
VILx, VIHx, VITx/VCOMx, VOLx, VOHx, POLx,
−2.5 V to +7.5 V
POHx, VCHx, VCLx, PCHx, PCLx, OVDHx, OVDLx,
PPMUx (FV), PCHx (FI), PCLx (FI)
VDUTx = (4 × (DAC/216) − 1) × (VREF − VREFGND) + VDUTGND
DAC = ((VDUTx − VDUTGND) + (VREF − VREFGND))/(4 × (VREF −VREFGND)) × 216
IOHx, IOLx
−12.5 mA to +37.5 mA
IDUTx = (4 × (DAC/216) − 1) × (VREF − VREFGND) × (25 mA/5)
PPMUx (FI, Range A), PCHx and PCLx (FV, Range
A)
−80 mA to +80 mA
DAC = ((IDUTx × (5/25 mA)) + (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (80 mA/5)
DAC = ((IDUTx/80 mA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
PPMUx (FI, Range B), PCHx and PCLx (FV, Range
B)
−2 mA to +2 mA
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (2 mA/5)
DAC = ((IDUTx/2 mA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
PPMUx (FI, Range C), PCHx and PCLx (FV, Range
C)
−200 µA to +200 µA
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (200 µA/5)
DAC = ((IDUTx/200 µA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
PPMUx (FI, Range D) PCHx and PCLx (FV, Range
D)
−20 µA to +20 µA
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (20 µA/5)
DAC = ((IDUTx/20 µA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
PPMUx (FI, Range E) PCHx and PCLx (FV, Range
E)
−4 µA to +4 µA
IDUTx = (4 × (DAC/216) − 2) × (VREF − VREFGND) × (4 µA/5)
DAC = ((IDUTx/4 µA × 5) + 2 × (VREF − VREFGND))/(4 × (VREF − VREFGND)) × 216
Table 25. Load Transfer Functions
Load Level
Transfer Functions
Notes
IOLx
VIOLx/(2 × (VREF − VREFGND)) × 25 mA
VIOLx DAC levels are not referenced to VDUTGND
IOHx
VIOHx/(2 × (VREF − VREFGND)) × 25 mA
VIOHx DAC levels are not referenced to VDUTGND
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Rev. C | 53 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
Table 26. PPMU Transfer Functions
PPMU Mode
Transfer Functions1
FV
VDUTx = PPMUx
−1.5 V < PPMUx < +4.5 V
FI
IDUTx = (PPMUx − (VREF − VREFGND))/(5 × RPPMU)
0.0 V < PPMUx < 5.0 V
Uncalibrated PPMU DAC Settings to Achieve Specified PPMU Range
MV
VPPMU_Mx = VDUTx (internal sense path)
Not applicable
MV
VPPMU_Mx = VPPMU_Sx (external sense path)
Not applicable
MI
VPPMU_Mx = (VREF − VREFGND) + (5 × IDUTx × RPPMU) + VDUTGND
Not applicable
1
RPPMU = 12.5 Ω for Range A, 500 Ω for Range B, 5.0 kΩ for Range C, 50 kΩ for Range D, and 250 kΩ for Range E.
Table 27. Temperature Sensor Transfer Function
Temperature
Output
0K
0.00 V
300 K
3.00 V
TKELVIN
0.00 V + (TKELVIN ) × 10 mV/K
DAC Gain and Offset Correction
Each analog function within the ADATE320 has independent gain
(m) and offset (c) calibration registers that allow digital trim of
first-order errors in the analog signal chain. These registers correct
errors in the pin electronics transfer functions as well as errors
intrinsic to the DAC itself.
The m and c registers are volatile and must be reloaded after each
power-on cycle as part of a calibration routine if values other than
the defaults are required. The registers are not cleared by any reset
operation (although the DAC_CAL_ENABLE bit is cleared following
reset).
The gain and offset calibration function can be bypassed by clearing the DAC_CAL_ENABLE bit in the DAC control register (see
Figure 145). This bypass mode is available only on a per chip
basis. In other words, it is not possible to bypass the calibration
function for a specific subset of the DACs.
The calibration function, when enabled, adjusts the numerical data
sent to each DAC according to the following equation:
X2 =
m+1
216
× X1 + c − 215
(1)
where:
X2 is the 16-bit data-word gated into the physical DAC, and returned by subsequent SPI read from that same DAC.
m is the code in the respective DAC gain calibration register (the
default code is 0xFFFF = 216 − 1).
X1 is the 16-bit data-word written by the user to the DAC via the
SPI.
c is the code in the respective DAC offset calibration register (the
default code is 0x8000 = 215).
From Equation 1, it can be seen that the gain applied to any written
X1 data is always ≤1.0, with the effect that the effective output of
a DAC can only be made smaller in magnitude by the calibration
mechanism. To compensate for this imposed limitation, each of the
analog signal paths in the pin electronics functions are guaranteed
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by designed to have a gain ≥1.0 when the default m register values
are applied. A signal path gain ≥1.0 guarantees that proper gain
calibration can always be achieved by multiplying down.
DAC X2 Registers and SPI Readback
When data is written via the SPI to a particular DAC, that data is
operated on in accordance with Equation 1. The results are stored
in an X2 register associated with that DAC (see Figure 130).
There is only a single physical X2 register per DAC, and it is the
value of this X2 register that is eventually gated into the physical
DAC at the time of analog update, which can be either in immediate
or deferred mode. It is also this register value that is returned
to the user during an SPI read operation addressed to that DAC
channel. In the special case of a dual channel write to a DAC, both
of the associated X2 registers are sequentially updated using the
appropriate m register and c register for each channel.
When enabled, the calibration function applies this operation to the
X2 registers only after a SPI write to the respective X1 registers.
The X2 registers are not updated after write operations to either m
register or c register or following any changes to functional modes
or range settings of the device. For this reason, to ensure that calibration data is recalculated for any particular DAC, it is necessary
to write fresh data to that DAC after changes are first made to the
associated m register and c register, and any associated functional
modes and ranges for that DAC function.
For each DAC, there is only a single X2 register, and generally
there is one dedicated and unique set of m calibration register
and c calibration register assigned. In several special cases (for
example, the PPMU DAC) there is still only one X2 register per
DAC, but there are several different choices for m register and
c register depending on the particular configuration of mode and
range control settings for the function. For those DACs, a choice of
calibration register is made automatically based on the respective
mode and range control settings in place for that function when the
DAC is written.
Rev. C | 54 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
Table 28 describes detailed m register and c register selection as a
function of mode and range control settings. For all DAC functions,
it is necessary to ensure that the respective m register and c
register values are put in place first, and that the desired mode and
range settings are updated prior to sending data to the DAC. It is
only during the DAC write sequence that the calibration constants
are selected and applied.
Table 28. m and c Calibration Register Selection
SPI Address
[Channel]
DAC
Name
Functional (DAC Usage)
Description
DMC_ENAB
LE
(Address
m Register c Register 0x1A[0])1
0x01[0]
VIH0
Driver high level, Channel 0
0x21[0]
0x31[0]
X
X
X
X
XXX
0x01[1]
VIH1
Driver high level, Channel 1
0x21[1]
0x31[1]
X
X
X
X
XXX
0x02[0]
VIT0/
VCOM0
Driver term level, Channel 0
0x22[0]
0x32[0]
X
0
X
X
XXX
Load commutation voltage, Channel 0
0x42[0]
0x52[0]
X
1
X
X
XXX
VIT1/
VCOM0
Driver termination level, Channel 1
0x22[1]
0x32[1]
X
0
X
X
XXX
Load commutation voltage, Channel 1
0x42[1]
0x52[1]
X
1
X
X
XXX
0x03[0]
VIL0
Driver low level, Channel 0
0x23[0]
0x33[0]
X
X
X
X
XXX
0x03[1]
VIL1
Driver low level, Channel 1
0x23[1]
0x33[1]
X
X
X
X
XXX
0x04[0]
VCH0
Reflection clamp high level, Channel 0
0x24[0]
0x34[0]
X
X
X
X
XXX
0x04[1]
VCH1
Reflection clamp high level, Channel 1
0x24[1]
0x34[1]
X
X
X
X
XXX
0x05[0]
VCL0
Reflection clamp low level, Channel 0
0x25[0]
0x35[0]
X
X
X
X
XXX
0x05[1]
VCL1
Reflection clamp low level, Channel 1
0x25[1]
0x35[1]
X
X
X
X
XXX
0x06[0]
VOH0
Normal window comparator high
level, Channel 0
0x26[0]
0x36[0]
0
X
X
X
XXX
Differential mode comparator high
level, Channel 0
0x46[0]
0x56[0]
1
X
X
X
XXX
0x02[1]
LOAD_ENA
BLE_x
(Address
0x1B[0])
PPMU_MEAS
_VI_x
PPMU_FORCE_ PPMU_RANG
(Address
VI_x (Address E_x (Address
0x1C[6])
0x1C[5])
0x1C[4:2])
0x06[1]
VOH1
Normal window comparator high
level, Channel 1
0x26[1]
0x36[1]
X
X
X
X
XXX
0x07[0]
VOL0
Normal window comparator low
level, Channel 0
0x27[0]
0x37[0]
0
X
X
X
XXX
Differential mode comparator low
level, Channel 0
0x47[0]
0x57[0]
1
X
X
X
XXX
0x07[1]
VOL1
Normal window comparator low
level, Channel 1
0x27[1]
0x37[1]
X
X
X
X
XXX
0x08[0]
VIOH0
Load IOHx level, Channel 0
0x28[0]
0x38[0]
X
X
X
X
XXX
0x08[1]
VIOH1
Load IOHx level, Channel 1
0x28[1]
0x38[1]
X
X
X
X
XXX
0x09[0]
VIOL0
Load IOL level, Channel 0
0x29[0]
0x39[0]
X
X
X
X
XXX
0x09[1]
VIOL1
Load IOL level, Channel 1
0x29[1]
0x39[1]
X
X
X
X
XXX
0x0A[0]
PPMU0
PPMU VIN FV level, Channel 0
0x2A[0]
0x3A[0]
X
X
X
0
XXX
PPMU VIN FI level Range A,
Channel 0
0x4A[0]
0x5A[0]
X
X
X
1
111
PPMU VIN FI level Range B,
Channel 0
0x4B[0]
0x5A[0]
X
X
X
1
110
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Rev. C | 55 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
Table 28. m and c Calibration Register Selection
SPI Address
[Channel]
0x0A[1]
0x0B[0]
0x0B[1]
0x0C[0]
0x0C[1]
0x0D[0]
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DAC
Name
PPMU1
PCH0
PCH1
PCL0
PCL1
POH0
DMC_ENAB
LE
(Address
m Register c Register 0x1A[0])1
LOAD_ENA
BLE_x
(Address
0x1B[0])
PPMU_MEAS
_VI_x
PPMU_FORCE_ PPMU_RANG
(Address
VI_x (Address E_x (Address
0x1C[6])
0x1C[5])
0x1C[4:2])
PPMU VIN FI level Range C,
Channel 0
0x4C[0]
0x5A[0]
X
X
X
1
101
PPMU VIN FI level Range D,
Channel 0
0x4D[0]
0x5A[0]
X
X
X
1
100
PPMU VIN FI level Range E,
Channel 0
0x4E[0]
0x5A[0]
X
X
X
1
0XX
PPMU VIN FV level, Channel 1
0x2A[1]
0x3A[1]
X
X
X
0
XXX
PPMU VIN FI level Range A,
Channel 1
0x4A[1]
0x5A[1]
X
X
X
1
111
PPMU VIN FI level Range B,
Channel 1
0x4B[1]
0x5A[1]
X
X
X
1
110
PPMU VIN FI level Range C,
Channel 1
0x4C[1]
0x5A[1]
X
X
X
1
101
PPMU VIN FI level Range D,
Channel 1
0x4D[1]
0x5A[1]
X
X
X
1
100
PPMU VIN FI level Range E,
Channel 1
0x4E[1]
0x5A[1]
X
X
X
1
0XX
PPMU current clamp (FV) high lev- 0x44[0]
el, Channel 0
0x54[0]
X
X
X
0
XXX
PPMU voltage clamp (FI) high level, Channel 0
0x2B[0]
0x3B[0]
PPMU current clamp (FV) high lev- 0x44[1]
el, Channel 1
0x54[1]
PPMU voltage clamp (FI) high level, Channel 1
0x2B[1]
0x3B[1]
PPMU current clamp (FV) low level, Channel 0
0x45[0]
0x55[0]
PPMU voltage clamp (FI) low level, 0x2C[0]
Channel 0
0x3C[0]
PPMU current clamp (FV) low level, Channel 1
0x45[1]
0x55[1]
X
X
X
0
PPMU voltage clamp (FI) low level, 0x2C[1]
Channel 1
0x3C[1]
X
X
X
1
PPMU go/no-go MV high level,
Channel 0
0x2D[0]
0x3D[0]
X
X
0
X
XXX
PPMU go/no-go MI Range A high
level, Channel 0
0x61[0]
0x5D[0]
X
X
1
X
111
PPMU go/no-go MI Range B high
level, Channel 0
0x62[0]
0x5D[0]
X
X
1
X
110
PPMU go/no-go MI Range C high
level, Channel 0
0x63[0]
0x5D[0]
X
X
1
X
101
PPMU go/no-go MI Range D high
level, Channel 0
0x64[0]
0x5D[0]
X
X
1
X
100
PPMU go/no-go MI Range E high
level, Channel 0
0x65[0]
0x5D[0]
X
X
1
X
0XX
Functional (DAC Usage)
Description
1
X
X
X
0
XXX
1
X
X
X
0
XXX
1
XXX
Rev. C | 56 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
Table 28. m and c Calibration Register Selection
DMC_ENAB
LE
(Address
m Register c Register 0x1A[0])1
LOAD_ENA
BLE_x
(Address
0x1B[0])
PPMU_MEAS
_VI_x
PPMU_FORCE_ PPMU_RANG
(Address
VI_x (Address E_x (Address
0x1C[6])
0x1C[5])
0x1C[4:2])
SPI Address
[Channel]
DAC
Name
Functional (DAC Usage)
Description
0x0D[1]
POH1
PPMU go/no-go MV high level,
Channel 1
0x2D[1]
0x3D[1]
X
X
0
X
XXX
PPMU go/no-go MI Range A high
level, Channel 1
0x61[1]
0x5D[1]
X
X
1
X
111
PPMU go/no-go MI Range B high
level, Channel 1
0x62[1]
0x5D[1]
X
X
1
X
110
PPMU go/no-go MI Range C high
level, Channel 1
0x63[1]
0x5D[1]
X
X
1
X
101
PPMU go/no-go MI Range D high
level, Channel 1
0x641[]
0x5D[1]
X
X
1
X
100
PPMU go/no-go MI Range E high
level, Channel 1
0x65[1]
0x5D[1
X
X
1
X
0XX
PPMU go/no-go MV low level,
Channel 0
0x2E[0]
0x3E[0]
X
X
0
X
XXX
PPMU go/no-go MI Range A low
level, Channel 0
0x66[0]
0x5E[0]
X
X
1
X
111
PPMU go/no-go MI Range B low
level, Channel 0
0x67[0]
0x5E[0]
X
X
1
X
110
PPMU go/no-go MI Range C low
level, Channel 0
0x68[0]
0x5E[0]
X
X
1
X
101
PPMU go/no-go MI Range D low
level, Channel 0
0x69[0]
0x5E[0]
X
X
1
X
100
PPMU go/no-go MI Range E low
level, Channel 0
0x6A[0]
0x5E[0]
X
X
1
X
0XX
PPMU go/no-go MV low level,
Channel 1
0x2E[1]
0x3E[1]
X
X
0
X
XXX
PPMU go/no-go MI Range A low
level, Channel 1
0x66[1]
0x5E[1]
X
X
1
X
111
PPMU go/no-go MI Range B low
level, Channel 1
0x67[1]
0x5E[1]
X
X
1
X
110
PPMU go/no-go MI Range C low
level, Channel 1
0x68[1]
0x5E[1]
X
X
1
X
101
PPMU go/no-go MI Range D low
level, Channel 1
0x69[1]
0x5E[1]
X
X
1
X
100
PPMU go/no-go MI Range E low
level, Channel 1
0x6A[1]
0x5E[1]
X
X
1
X
0XX
0x0E[0]
0x0E[1]
POL0
POL1
0x0F[0]
OVDL
Overvoltage detect low level
0x2F[0]
0x3F[0]
X
X
X
X
XXX
0x0F[1]
OVDH
Overvoltage detect high level
0x2F[1]
0x3F[1]
X
X
X
X
XXX
1
X means don’t care.
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Rev. C | 57 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
Figure 130. DAC X2 Registers and Calibration Diagram
ALARM FUNCTIONS
The ADATE320 contains per channel overvoltage detectors (OVDL/
OVDH), per channel PPMU voltage/current clamps (PCLx/PCHx),
and a thermal alarm to detect and signal these respective fault
conditions. Any of these functions may flag an alarm independently
in the alarm state register (see Figure 152). The status of the
alarms may be determined at any time by reading the SPI alarm
state register. This register is read only, and its contents are cleared
by the read operation. The alarm flag bits can then become set by
any of the respective alarm functions. The individual fault condition
flags are logically OR'ed together to drive the open-drain ALARM
output pin to indicate that a fault condition has occurred (see Figure
134).
The various alarm flags can be either enabled or disabled (masked)
using the alarm mask register (see Figure 151). The thermal alarm
is enabled by default (mask bit clear), and the overvoltage and
PPMU clamp alarms are all disabled by default (mask bits set).
The PPMU clamp alarm behavior depends on the mode of the
PPMU. When in FI mode, the PPMU clamps behave as programmable voltage clamps. The high and low voltage clamp levels are
set by the respective PCHx and PCLx level setting DACs. If the
voltage on the DUTx pin reaches either the PCHx or PCLx setting,
a PPMU clamp alarm is generated, but only if the clamps are enabled with the PPMU_CLAMP_ENABLE_x control bit in the PPMU
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control register (see Figure 150). Note that if the PPMU clamps are
enabled and a PPMU clamp alarm is generated, the alarm can still
be masked with the alarm mask register. However, if the voltage
clamps are disabled, no PPMU clamp alarm is generated.
When the PPMU is in FV mode, the PPMU clamps behave as
programmable current clamps. The source and sink current clamp
levels are set with the respective PCHx and PCLx level setting
DACs. The current clamps cannot be disabled by setting or clearing
the PPMU_CLAMP_ENABLE_x control bit—the clamps are always
active when in PPMU FV mode. If the PCHx and PCLx levels are
set outside their functional range, a ±140% static current limit is
left in effect. If the current on a DUTx pin reaches either the PCHx
or PCLx clamp setting, or, alternatively, one of the static current
limits, a PPMU clamp alarm results. The PPMU clamp alarm can be
masked separately in the alarm mask register.
Refer to Figure 131 through Figure 134 for more information about
PPMU clamp functions.
The only purpose of the various alarm circuits is to detect and
indicate the presence of a fault condition of interest to the user.
The only action the ADATE320 takes upon detection of a fault is to
set the appropriate alarm state register flag bits in the alarm state
register and then activate the open-drain ALARM pin. No other
action is taken.
Rev. C | 58 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
Figure 131. PPMU Voltage Clamp High, Functional Diagram (Voltage Clamp Low Fixed at −1.5 V)
Figure 132. PPMU Voltage Clamp Low, Functional Diagram (Voltage Clamp High Fixed at 4.5 V)
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Rev. C | 59 of 78
Data Sheet
ADATE320
THEORY OF OPERATION
Figure 133. PPMU Current Clamp High and Low, Functional Diagram
Figure 134. Fault Alarm Functional Block Diagram
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Rev. C | 60 of 78
Data Sheet
ADATE320
APPLICATIONS INFORMATION
POWER SUPPLY, GROUNDING, AND TYPICAL
DECOUPLING STRATEGY
The ADATE320 is internally divided into a digital core and an
analog core.
The VDD and DGND pins provide power and ground for the digital
core that includes the SPI, certain logic functions, and the digital
calibration functions. DGND is the logic ground reference for the
VDD supply. Therefore, bypass VDD adequately to DGND with
good quality, low effective series resistance (ESR) bypass capacitors. To reduce transient digital switching noise coupling to the
analog core, connect DGND to a dedicated external ground plane
that is separated from the analog ground domains. If the application
permits, the DGND pins can share a digital ground domain with the
supervisory FPGA or ASIC that interfaces with the ADATE320 SPI.
All CMOS inputs and outputs are referenced between VDD and
DGND, and their valid levels must be guaranteed relative to these
power supply pins.
The analog core of the device includes all analog ATE functional
blocks such as the DACs, the driver, the comparator, the load,
and the PPMU. The VCC and VEE supplies provide power to
the analog core. AGND and PGND are analog ground and power
ground references, respectively. PGND is generally noisier with
analog switching transients, and it may also have large static dc
currents. AGND is generally quieter and has relatively smaller static
dc currents. These two grounds can be connected together outside
the chip to a single shared analog ground plane. Regardless, keep
PGND and AGND (whether separated or shared) separated from
the DGND ground plane if system design constraints permit.
The transient frequencies generated by the analog core can be a
full order of magnitude greater than those generated by the SPI
and on-chip digital circuitry. Therefore, pay close attention to the
decoupling of the VCC and VEE supplies. Each supply must be adequately bypassed to the PGND ground domain using the highest
quality bypass capacitors available. Locate the decoupling capacitors as close to the device as practically possible. The decoupling
capacitors must have very low ESR and effective series inductance
(ESL). Commonly available ceramic capacitors may provide only
a marginally low impedance path to ground at the frequencies
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encountered in the ADATE320. Therefore, consider only the highest
performance decoupling capacitors if possible. In accordance with
generally accepted practices, a typical 10 µF tantalum capacitor
must also be shared across each power supply domain.
Pay particularly close attention to decoupling the VCC and VEE
supplies in proximity to the transmission line at the DUTx pins of the
device. To avoid undesired waveform aberrations and degradation
of performance, it is important that all return currents to and from
the transmission line have a direct and low impedance path back to
the VCCDx and VEEDx pins adjacent to the respective DUTx pins.
See Figure 135 for a typical transmission line decoupling strategy.
The ADATE320 has a DUTGND reference input pin that senses the
remote low frequency ground potential at the target device under
test (DUT). With the exception of the VIOH and VIOL active load
currents and VPMU when in PPMU FI mode, all DAC levels are
adjusted on-chip relative to this DUTGND input. Furthermore, the
PPMU measure output pins (PPMU_Mx) are also referenced to
DUTGND. The off-chip system analog-to-digital converter (ADC)
that measures the PPMU_Mx pins must therefore be referenced to
DUTGND as well. Referencing the system ADC to AGND results
in errors unless DUTGND is tied directly to AGND as close as
possible to the ADATE320. For applications that do not distinguish
between DUT ground reference and system analog ground reference, the DUTGND pin may be connected to the same ground
plane as AGND.
Avoid routing digital lines under the device, because these lines
can couple noise into the device. Generous use of an analog
ground plane under the device shields noise coupling that can
otherwise enter the device. The power supply distribution lines
must provide very wide and low inductance paths to the respective
supply planes. This is especially true for VCC and VEE. Attention
to via inductance is extremely important in these supplies—it cannot be neglected. Fast switching signals routed in proximity to
the ADATE320 must be adequately shielded, preferably with their
proper ground returns to avoid radiating noise to other parts of the
board. Route such lines as far away as possible from the analog
inputs to the device, such as the AGND, DUTGND, VREF, and
VREFGND reference inputs.
Rev. C | 61 of 78
Data Sheet
ADATE320
APPLICATIONS INFORMATION
Figure 135. Power Supply and Transmission Path Decoupling Detail
POWER SUPPLY SEQUENCING
The ADATE320 is designed to tolerate sequencing of power supplies in any order. It is therefore not critical that the power supplies
be sequenced in any particular order; however, there are recommended best practices.
The ADATE320 has two analog power supplies (VCC, VEE) and
one digital power supply (VDD). The analog supplies service all of
the analog functions on the chip such as level setting DACs, driver,
comparator, load, and PPMU. The digital supply services the SPI
and all digital CMOS control circuitry.
There is careful separation between the analog and digital partitions
of the chip, and significant effort has been made to decouple these
two partitions both functionally and electrically. The analog partition
remains in the default configuration in the absence of VDD, and
similarly, the digital partition remains in the default configuration in
the absence of either (or both) VCC and VEE.
It is not possible to guarantee predictable behavior of the analog
partition if either the VEE or VCC supply is poorly conditioned or
absent. It is therefore recommended that any externally connected
device be disconnected from the DUTx pin to prevent potential
damage to that device while either of the VEE or VCC supplies is out
of specification.
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Assuming the VEE and VCC analog supplies are both applied and
within specification, the analog partition ensures that all functions
remain in the default configuration. This is true even when the
VDD supply is absent and digital CMOS control circuitry is not yet
functioning. In such a case (or whenever the RST pin is asserted),
all of the level setting DACs takes the voltage present at the
DUTGND input pin, and all SPI control bits assume their reset
default values. The analog functions remain in this safe condition
as long as VDD remains absent or as long as the RST pin remains
asserted.
It is recommended that the RST pin always be asserted during the
time that the VDD supply is being brought up. If this condition is met,
the level setting DACs continue to hold the DUTGND potential after
VDD stabilizes and after the RST pin is released. A fully clocked
reset sequence then initializes the level setting DACs to the reset
default conditions as specified in Table 29.
The reset sequence is described in more detail in the SPI Reset
Sequence and the RST Pin section.
In light of these considerations, it is recommended that the two
analog supplies be applied first. It is preferable that the smaller
valued supply (VEE) be applied before the larger valued supply
(VCC). Bring up the digital VDD supply next while the RST pin
Rev. C | 62 of 78
Data Sheet
ADATE320
APPLICATIONS INFORMATION
is asserted. After VDD is stable and the RST pin is subsequently
released, a fully clocked reset sequence must follow. This power
supply sequence ensures that analog functions and all level setting
DACs receive the proper configuration information during the digital
partition reset sequence.
The power supplies must be removed in the reverse order.
Note that VREF and the high speed transmission line termination
pins (VTTDx, VTTCx) are all part of the analog partition, but they
are not treated as supplies. VREF can be managed independent
of VCC and VEE, provided its potential never goes outside those of
the VEE and VCC supply buses to prevent ESD protection diodes
from becoming forward biased. The VTTDx and VTTCx pins do not
have this restriction relative to VCC and VEE, but they must never go
outside the absolute maximum ratings as measured with respect to
PGND.
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Rev. C | 63 of 78
Data Sheet
ADATE320
DETAILED FUNCTIONAL BLOCK DIAGRAMS
Figure 141 through Figure 144 illustrate the top-level functionality of the capabilities of the ADATE320 for the driver, comparator, active load,
and PPMU.
Figure 136. Driver Block Diagram
Figure 137. Driver Equivalent Input Stage Diagram
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Rev. C | 64 of 78
Data Sheet
ADATE320
DETAILED FUNCTIONAL BLOCK DIAGRAMS
Figure 138. Driver Input Multiplex Diagram
Figure 139. Comparator Functional Block Diagram
Figure 140. Comparator Equivalent Output Stage Diagram
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Rev. C | 65 of 78
Data Sheet
ADATE320
DETAILED FUNCTIONAL BLOCK DIAGRAMS
Figure 141. Active Load Functional Block Diagram
Figure 142. Active Load Functional Logic Diagram
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Rev. C | 66 of 78
Data Sheet
ADATE320
DETAILED FUNCTIONAL BLOCK DIAGRAMS
Figure 143. PPMU Functional Block Diagram
Figure 144. PPMU Go/No-Go Comparator Functional Block Diagram
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Rev. C | 67 of 78
Data Sheet
ADATE320
SPI REGISTER MEMORY MAP AND DETAILS
MEMORY MAP
Table 29. SPI Register Memory Map
CH[1:0]1, 2
Address (ADDR[6:0])
R/W
DATA[15:0]3
Register Description
XX
0x00
X
XXXX
NOP
CC
0x01
R/W
DDDD
VIH DAC level (reset value = 0.0 V)
0x4000
CC
0x02
R/W
DDDD
VIT/VCOM DAC level (reset value = 0.0 V)
0x4000
CC
0x03
R/W
DDDD
VIL DAC level (reset value = 0.0 V)
0x4000
CC
0x04
R/W
DDDD
VCHx DAC level (reset value = VMAX)
0xFFFF
CC
0x05
R/W
DDDD
VCLx DAC level (reset value = VMIN)
0x0000
CC
0x06
R/W
DDDD
VOHx DAC level (reset value = 4.0 V)
0xA666
CC
0x07
R/W
DDDD
VOLx DAC level (reset value = −1.0 V)
0x2666
CC
0x08
R/W
DDDD
VIOH DAC level (reset value ≥ 0 µA)4
0x4000
0x4000
0x4000
Reset Value
CC
0x09
R/W
DDDD
VIOL DAC level (reset value ≥ 0 µA)4
CC
0x0A
R/W
DDDD
PPMU DAC level (reset value = 0.0 V)
CC
0x0B
R/W
DDDD
PCHx DAC level (reset value = VMAX)
0xFFFF
CC
0x0C
R/W
DDDD
PCLx DAC level (reset value = VMIN)
0x0000
CC
0x0D
R/W
DDDD
POHx DAC level (reset value = 4.0 V)
0xA666
CC
0x0E
R/W
DDDD
POLx DAC level (reset value = −1.0 V)
0x2666
01
0x0F
R/W
DDDD
OVDL DAC level (reset value = VMIN)
0x0000
10
0x0F
R/W
DDDD
OVDH DAC level (reset value = VMAX)
0xFFFF
XX
0x10
X
XXXX
Reserved
CC
0x11
R/W
DDDD
DAC control register
0x0000
01
0x12
R/W
DDDD
SPI control register
0x0000
XX
0x13 to 0x18
X
XXXX
Reserved
CC
0x19
R/W
DDDD
DRV control register
0x0000
CC
0x1A
R/W
DDDD
CMP control register
0xFF00
CC
0x1B
R/W
DDDD
Load control register
0x0003
CC
0x1C
R/W
DDDD
PPMU control register
0x0000
01
0x1D
R/W
DDDD
Alarm mask register
0x0085
10
0x1D
R/W
DDDD
Alarm mask register
0x0005
CC
0x1E
R
DDDD
Alarm state register
0x0000
CC
0x1F
R/W
DDDD
Product serialization code register
Unique
XX
0x20
X
XXXX
NOP
CC
0x21
R/W
DDDD
VIH (driver high level) m coefficient
0xFFFF
CC
0x22
R/W
DDDD
VIT (driver term level) m coefficient
0xFFFF
CC
0x23
R/W
DDDD
VIL (driver low level) m coefficient
0xFFFF
CC
0x24
R/W
DDDD
VCHx (driver reflection clamp) m coefficient
0xFFFF
CC
0x25
R/W
DDDD
VCLx (driver reflection clamp) m coefficient
0xFFFF
CC
0x26
R/W
DDDD
VOHx (normal window comparator) m coefficient
0xFFFF
CC
0x27
R/W
DDDD
VOLx (normal window comparator) m coefficient
0xFFFF
CC
0x28
R/W
DDDD
VIOH (active load IOHx) m coefficient
0xFFFF
CC
0x29
R/W
DDDD
VIOL (active load IOL) m coefficient
0xFFFF
CC
0x2A
R/W
DDDD
PPMU (PPMU FV) m coefficient
0xFFFF
CC
0x2B
R/W
DDDD
PCHx (PPMU voltage clamp, FI) m coefficient
0xFFFF
CC
0x2C
R/W
DDDD
PCLx (PPMU voltage clamp, FI) m coefficient
0xFFFF
CC
0x2D
R/W
DDDD
POHx (PPMU comparator MV) m coefficient
0xFFFF
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Rev. C | 68 of 78
Data Sheet
ADATE320
SPI REGISTER MEMORY MAP AND DETAILS
Table 29. SPI Register Memory Map
CH[1:0]1, 2
Address (ADDR[6:0])
R/W
DATA[15:0]3
Register Description
Reset Value
CC
0x2E
R/W
DDDD
POLx (PPMU comparator MV) m coefficient
0xFFFF
01
0x2F
R/W
DDDD
OVDL m coefficient
0xFFFF
10
0x2F
R/W
DDDD
OVDH m coefficient
0xFFFF
XX
0x30
X
XXXX
Reserved
CC
0x31
R/W
DDDD
VIH (driver high level) c coefficient
0x8000
CC
0x32
R/W
DDDD
VIT (driver term level) c coefficient
0x8000
CC
0x33
R/W
DDDD
VIL (driver low level) c coefficient
0x8000
CC
0x34
R/W
DDDD
VCHx (driver reflection clamp) c coefficient
0x8000
CC
0x35
R/W
DDDD
VCLx (driver reflection clamp) c coefficient
0x8000
CC
0x36
R/W
DDDD
VOHx (normal window comparator) c coefficient
0x8000
CC
0x37
R/W
DDDD
VOLx (normal window comparator) c coefficient
0x8000
CC
0x38
R/W
DDDD
VIOH (active load IOHx) c coefficient
0x8000
CC
0x39
R/W
DDDD
VIOL (active load IOL) c coefficient
0x8000
CC
0x3A
R/W
DDDD
PPMU (PPMU FV) c coefficient
0x8000
CC
0x3B
R/W
DDDD
PCHx (PPMU voltage clamp, FI) c coefficient
0x8000
CC
0x3C
R/W
DDDD
PCLx (PPMU voltage clamp, FI) c coefficient
0x8000
CC
0x3D
R/W
DDDD
POHx (PPMU comparator MV) c coefficient
0x8000
CC
0x3E
R/W
DDDD
POLx (PPMU comparator MV) c coefficient
0x8000
01
0x3F
R/W
DDDD
OVDL c coefficient
0x8000
10
0x3F
R/W
DDDD
OVDH c coefficient
0x8000
XX
0x40 to 0x41
X
XXXX
Reserved
CC
0x42
R/W
DDDD
VCOM (active load) m coefficient
XX
0x43
X
XXXX
Reserved
CC
0x44
R/W
DDDD
PCHx (PPMU current clamp, FV) m coefficient
0xFFFF
CC
0x45
R/W
DDDD
PCLx (PPMU current clamp, FV) m coefficient
0xFFFF
01
0x46
R/W
DDDD
VOHx (differential comparator) m coefficient
0xFFFF
01
0x47
R/W
DDDD
VOLx (differential comparator) m coefficient
0xFFFF
XX
0x48 to 0x49
X
XXXX
Reserved
CC
0x4A
R/W
DDDD
PPMU FI Range A m coefficient
0xFFFF
CC
0x4B
R/W
DDDD
PPMU FI Range B m coefficient
0xFFFF
CC
0x4C
R/W
DDDD
PPMU FI Range C m coefficient
0xFFFF
CC
0x4D
R/W
DDDD
PPMU FI Range D m coefficient
0xFFFF
CC
0x4E
R/W
DDDD
PPMU FI Range E m coefficient
0xFFFF
XX
0x4F
X
XXXX
Reserved
XX
0x50 to 0x51
X
XXXX
Reserved
CC
0x52
R/W
DDDD
VCOM (active load) c coefficient
XX
0x53
X
XXXX
Reserved
CC
0x54
R/W
DDDD
PCHx (PPMU current clamp, FV) c coefficient
0x8000
CC
0x55
R/W
DDDD
PCLx (PPMU current clamp, FV) c coefficient
0x8000
01
0x56
R/W
DDDD
VOHx (differential comparator) c coefficient
0x8000
01
0x57
R/W
DDDD
VOLx (differential comparator) c coefficient
0x8000
XX
0x58 to 0x59
X
XXXX
Reserved
CC
0x5A
R/W
DDDD
PPMU FI c coefficient
XX
0x5B to 0x5C
X
XXXX
Reserved
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0xFFFF
0x8000
0x8000
Rev. C | 69 of 78
Data Sheet
ADATE320
SPI REGISTER MEMORY MAP AND DETAILS
Table 29. SPI Register Memory Map
CH[1:0]1, 2
Address (ADDR[6:0])
R/W
DATA[15:0]3
Register Description
Reset Value
CC
0x5D
R/W
DDDD
POHx (PPMU comparator MI) c coefficient
0x8000
CC
0x5E
R/W
DDDD
POLx (PPMU comparator MI) c coefficient
0x8000
XX
0x5F
X
XXXX
Reserved
XX
0x60
X
XXXX
Reserved
CC
0x61
R/W
DDDD
POHx (PPMU comparator MI Range A) m coefficient
0xFFFF
CC
0x62
R/W
DDDD
POHx (PPMU comparator MI Range B) m coefficient
0xFFFF
CC
0x63
R/W
DDDD
POHx (PPMU comparator MI Range C) m coefficient
0xFFFF
CC
0x64
R/W
DDDD
POHx (PPMU comparator MI Range D) m coefficient
0xFFFF
CC
0x65
R/W
DDDD
POHx (PPMU comparator MI Range E) m coefficient
0xFFFF
CC
0x66
R/W
DDDD
POLx (PPMU comparator MI Range A) m coefficient
0xFFFF
CC
0x67
R/W
DDDD
POLx (PPMU comparator MI Range B) m coefficient
0xFFFF
CC
0x68
R/W
DDDD
POLx (PPMU comparator MI Range C) m coefficient
0xFFFF
CC
0x69
R/W
DDDD
POLx (PPMU comparator MI Range D) m coefficient
0xFFFF
CC
0x6A
R/W
DDDD
POLx (PPMU comparator MI Range E) m coefficient
0xFFFF
XX
0x6B to 0x7F
X
XXXX
Reserved
1
X means don’t care for the respective field.
2
CC represents two contiguous binary channel bits.
3
DDDD represents four-digit hexadecimal data.
4
The active load VIOHx and VIOLx voltage offsets are guaranteed to be nonzero and positive. These offsets result in a nonzero current for each IOHx and IOLx level
following valid reset sequence and prior to calibration. Furthermore, the active load is forced into the active on state following a reset, which facilitates a soft connect of the
DUTx pin to VCOMx = 0.0 V following a valid reset sequence (with small but nonzero IOHx and IOLx currents).
REGISTER DETAILS
Reserved bits in any register are undefined. In some cases, a
physical but unused memory bit may be present.
Any SPI read operation from a reserved bit or register results in an
unknown but deterministic readback value. Any SPI write operation
to a reserved bit or register results in no action.
A write to a control bit or control register defined only on Channel 0
must be addressed to Channel 0. Any such write that is addressed
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to only Channel 1 is ignored if no register or control bit is defined on
Channel 1.
Furthermore, any such write that is addressed to both Channel 0
and Channel 1 (as a multichannel write) proceeds as if the write
is addressed to both Channel 0 and Channel 1. If no register or
control bit is defined at Channel 1, data addressed to the undefined
Channel 1 is ignored. If a register or control bit is defined at
Channel 1, it is filled as part of the multichannel write.
Rev. C | 70 of 78
Data Sheet
ADATE320
SPI REGISTER MEMORY MAP AND DETAILS
Figure 145. DAC Control Register (Address 0x11)
Figure 146. SPI Control Register (Address 0x12)
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Rev. C | 71 of 78
Data Sheet
ADATE320
SPI REGISTER MEMORY MAP AND DETAILS
Figure 147. DRV Control Register (Address 0x19)
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Rev. C | 72 of 78
Data Sheet
ADATE320
SPI REGISTER MEMORY MAP AND DETAILS
Figure 148. CMP Control Register (Address 0x1A)
Figure 149. Load Control Register (Address 0x1B)
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Rev. C | 73 of 78
Data Sheet
ADATE320
SPI REGISTER MEMORY MAP AND DETAILS
Figure 150. PPMU Control Register (Address 0x1C)
Figure 151. Alarm Mask Register (Address 0x1D)
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Rev. C | 74 of 78
Data Sheet
ADATE320
SPI REGISTER MEMORY MAP AND DETAILS
Figure 152. Alarm State Register (Address 0x1E) (Read Only)
Figure 153. Product Serialization Code Register (Address 0x1F)
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Rev. C | 75 of 78
Data Sheet
ADATE320
DEFAULT TEST CONDITIONS
Table 30. Default Test Conditions
Name
SPI Address
Default Test Condition
VIHx DAC Levels
Address 0x01[x]
2.0 V
VITx/VCOMx DAC Levels
Address 0x02[x]
1.0 V
VILx DAC Levels
Address 0x03[x]
0.0 V
VOHx DAC Levels
Address 0x06[x]
5.0 V
VOLx DAC Levels
Address 0x07[x]
−2.0 V
POHx DAC Levels
Address 0x0D[x
5.5 V
POLx DAC Levels
Address 0x0E[x]
−2.0 V
VCHx DAC Levels
Address 0x04[x]
5.0 V
VCLx DAC Levels
Address 0x05[x]
−2.0 V
PCHx DAC Levels
Address 0x0B[x]
7.0 V
PCLx DAC Levels
Address 0x0C[x]
−2.0 V
VIOHx DAC Levels
Address 0x08[x]
0.0 mA
VIOLx DAC Levels
Address 0x09[x]
0.0 mA
PPMUx DAC Levels
Address 0x0A[x]
0.0 V
OVDH DAC Level
Address 0x0F[1]
5.0 V
OVDL DAC Level
Address 0x0F[0]
−2.0 V
DAC Control Register
Address 0x11[0]
0x0000
DAC calibration disabled, DAC load mode is immediate
SPI Control Register
Address 0x12[1]
0x0000
SDO pin is always active, independent of CS state
DRV Control Registers
Address 0x19[x]
0x0000
Driver disabled in low leakage mode, DATx/RCVx inputs are multiplexed to primary
channels, CLC is off, driver responds high-Z to RCVx inputs when enabled
CMP Control Registers
Address 0x1A[x]
0x0000
Normal window comparator mode, CLC is off, hysteresis is off
LOAD Control Registers
Address 0x1B[x]
0x0000
Active load is disabled and in power-down mode
PPMU Control Registers
Address 0x1C[x]
0x0000
PPMU disabled and in power-down mode, mode set FVMV Range E, input select
VDUTGND internal sense path to VDUTx, PPMU_Mx pins high-Z, clamps disabled
ALARM Mask Registers
Address 0x1D[x]
0x0085
Disable PPMU and overvoltage detector alarm functions
Calibration m Coefficients
Not applicable
1.0 (0xFFFF)
Calibration c Coefficients
Not applicable
0.0 (0x8000)
DATx, RCVx Inputs
Not applicable
Static low
SCLK Input
Not applicable
Static low
DUTx Pins
Not applicable
Unterminated
CMPHx, CMPLx Outputs
Not applicable
Unterminated
VDUTGND
Not applicable
0.0 V
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Description
Rev. C | 76 of 78
Data Sheet
ADATE320
EXTERNAL COMPONENTS
In addition to the external components identified in Table 31 and Table 32, see the Power Supply, Grounding, and Typical Decoupling
Strategy section for further information about recommended power
supply decoupling capacitors.
Table 31. PPMU External Compensation Capacitors
External Components Value (pF)
Location
1000 pF
Between the CFFB0 and CFFA0 pins
1000 pF
Between the CFFB1 and CFFA1 pins
Table 32. Other External Components
External Components Value (kΩ)
Location
10 kΩ
ALARM pull-up resistor to VDD
1 kΩ
BUSY pull-up resistor to VDD
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Rev. C | 77 of 78
Data Sheet
ADATE320
OUTLINE DIMENSIONS
Figure 154. 84-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm Body, Very Thin Quad
(CP-84-2)
Dimensions shown in millimeters
Updated: August 24, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADATE320-1KCPZ
ADATE320KCPZ
+25°C to +75°C
+25°C to +75°C
84-Lead LFCSP (10mm x 10mm w/ EP)
84-Lead LFCSP (10mm x 10mm w/ EP)
CP-84-2
CP-84-2
1
Z = RoHS Compliant Part.
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Rev. C | 78 of 78
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