EV1HMC832ALP6G

25 MHz to 3000 MHz Fractional-N PLL with Integrated VCO HMC832A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM LD/SDO RF bandwidth: 25 MHz to 3000 MHz 3.3 V supply Maximum phase detector rate: 100 MHz Ultralow phase noise −110 dBc/Hz in band (typical), fO at 1600 MHz Fractional figure of merit (FOM): −226 dBc/Hz 24-bit step size, 3 Hz typical resolution Exact frequency mode with 0 Hz frequency error Fast frequency hopping 40-lead, 6 mm × 6 mm LFCSP package: 36 mm2 HMC832A SCK SDI LOCK DETECT CONTROL SPI PROGRAMMING INTERFACE SEN EN MODULATOR CAL RF_P EN RF_N ÷1, 2, 4, 6, ...62 ÷N APPLICATIONS VCO CP CP PFD VTUNE ÷R 13110-001 Cellular infrastructure Microwave radios WiMax, WiFi Communications test equipment CATV equipment DDS replacement Military Tunable reference sources for spurious-free performance XREFP Figure 1. GENERAL DESCRIPTION The HMC832A is a 3.3 V, high performance, wideband, fractional-N, phase-locked loop (PLL) that features an integrated voltage controlled oscillator (VCO) with a fundamental frequency of 1500 MHz to 3000 MHz and an integrated VCO output divider (divide by 1, 2, 4, 6, … 62) that enables the HMC832A to generate continuous frequencies from 25 MHz to 3000 MHz. The integrated phase detector (PD) and Σ-Δ modulator, capable of operating at up to 100 MHz, permit wider loop bandwidths and faster frequency tuning with excellent spectral performance. Industry leading phase noise and spurious performance, across all frequencies, enable the HMC832A to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. A low noise floor (−160 dBc/Hz eliminates any contribution to modulator/mixer noise floor in transmitter applications. Rev. B The HMC832A is footprint compatible to the HMC830 PLL with an integrated VCO. It features 3.3 V supply and innovative programmable performance technology that enables the HMC832A to tailor current consumption and corresponding noise floor performance to individual applications by selecting either a low current consumption mode or a high performance mode for improved noise floor performance. Additional features of the HMC832A include 12 dB of RF output gain control in 1 dB steps; an output mute function to automatically mute the output during frequency changes when the device is not locked; selectable output return loss; programmable differential or single-ended outputs, with the ability to select either output in single-ended mode; a Σ-Δ modulator exact frequency mode that enables users to generate output frequencies with 0 Hz frequency error; and a register configurable 3.3 V or 1.8 V serial port interface (SPI). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC832A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ID, Read Address, and Reset (RST) Registers ........................ 35 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Reference Divider (REFDIV), Integer, and Fractional Frequency Registers ................................................................... 35 General Description ......................................................................... 1 VCO SPI Register ....................................................................... 36 Revision History ............................................................................... 2 Σ-Δ Configuration Register ...................................................... 36 Specifications..................................................................................... 3 Lock Detect Register .................................................................. 37 Timing Specifications .................................................................. 6 Analog Enable (EN) Register .................................................... 37 Absolute Maximum Ratings ............................................................ 7 Charge Pump Register ............................................................... 38 Recommended Operating Conditions ...................................... 7 Autocalibration Register............................................................ 38 ESD Caution .................................................................................. 7 Phase Detector (PD) Register ................................................... 39 Pin Configuration and Function Descriptions ............................. 8 Exact Frequency Mode Register ............................................... 39 Typical Performance Characteristics ............................................. 9 General-Purpose, SPI, and Reference Divider (GPO_SPI_RDIV) Register ...................................................... 40 Theory of Operation ...................................................................... 15 PLL Subsystem Overview .......................................................... 15 VCO Subsystem Overview ........................................................ 15 SPI Configuration of PLL and VCO Subsystems ................... 15 VCO Subsystem .......................................................................... 17 PLL Subsystem ............................................................................ 21 Soft Reset and Power-On Reset ................................................ 28 Power-Down Mode .................................................................... 28 General-Purpose Output (GPO) .............................................. 28 Chip Identification ..................................................................... 29 Serial Port Interface (SPI) .......................................................... 29 Applications Information .............................................................. 32 Power Supply ............................................................................... 33 VCO Tune Register .................................................................... 41 Sucessive Approximation Register ........................................... 41 General-Purpose 2 Register ...................................................... 41 Built-In Self Test (BIST) Register ............................................. 41 VCO Subsystem Register Map ...................................................... 42 VCO Enable Register ................................................................. 42 VCO Output Divider Register .................................................. 43 VCO Configuration Register .................................................... 43 VCO Calibration/Bias, Center Frequency Calibration (CF_CAL), and MSB Calibration Registers ............................ 44 VCO Output Power Control ..................................................... 44 Evaluation Printed Circuit Board (PCB) ..................................... 45 Programmable Performance Technology................................ 33 Changing Evaluation Board Reference Frequency and CP Current Configuration .............................................................. 46 Loop Filter and Frequency Changes ........................................ 33 Evaluation Kit Contents ............................................................ 46 RF Programmable Output Return Loss................................... 34 Outline Dimensions ....................................................................... 47 Mute Mode .................................................................................. 34 Ordering Guide .......................................................................... 48 PLL Register Map ........................................................................... 35 REVISION HISTORY 11/15—Revision B: Initial Version Rev. B | Page 2 of 48 Data Sheet HMC832A SPECIFICATIONS VPPCP, VDDLS, VCC1, VCC2, RVDD, AVDD, DVDD, VCCPD, VCCHF, VCCPS = 3.3 V minimum and maximum specified across the temperature range of −40°C to +85°C. Table 1. Parameter RF OUTPUT CHARACTERISTICS Output Frequency VCO Frequency at PLL Input RF Output Frequency at fVCO OUTPUT POWER RF Output Power Output Power Control Range HARMONICS FOR FUNDAMENTAL MODE fO Mode at 2 GHz fO/2 Mode at 2 GHz/2 = 1 GHz fO/30 Mode at 3 GHz/30 = 100 MHz fO/62 Mode at 1550 MHz/62 = 25 MHz VCO OUTPUT DIVIDER VCO RF Divider Range PLL RF DIVIDER CHARACTERISTICS 19-Bit N-Divider Range (Integer) 19-Bit N-Divider Range (Fractional) REFERENCE (XREFP PIN) INPUT CHARACTERISTICS Maximum XREFP Input Frequency XREFP Input Level XREFP Input Capacitance 14-Bit R-Divider Range PHASE DETECTOR (PD)2 PD Frequency Fractional Mode3 PD Frequency Integer Mode CHARGE PUMP Output Current Charge Pump Gain Step Size PD/Charge Pump Single Sideband (SSB) Phase Noise 1 kHz 10 kHz 100 kHz LOGIC INPUTS Input Voltage Low (VIL) High (VIH) SCK Clock Frequency Rate Test Conditions/Comments Min Typ 25 1500 1500 Across all frequencies (see Figure 25), high performance mode (VCO_REG 0x03[1:0] = 3d) Maximum gain setting (VCO_REG 0x07[3:0] = 0xB), single-ended Gain Setting 6 (VCO_REG 0x07[3:0] = 6d), differential 1 dB steps Second/third/fourth harmonics Second/third/fourth harmonics Second/third/fourth harmonics Second/third/fourth harmonics Max Unit 3000 3000 3000 MHz MHz MHz 7 dBm 2 dBm 12 dB −20/−29/−45 −26/−10/−34 −33/−10/−40 −40/−6/−43 dBc dBc dBc dBc 1, 2, 4, 6, 8, … 62 1 62 Maximum = 219 − 1 Fractional nominal divide ratio varies (±4) dynamically maximum 16 20 524,287 524,283 AC-coupled1 −6 MHz dBm pF 1 350 +12 5 16,383 DC DC 100 100 MHz MHz 2.54 20 mA µA −143 −150 −152 dBc/Hz dBc/Hz dBc/Hz 0.02 50 MHz reference, input referred Add 2 dB for fractional mode Add 3 dB for fractional mode 1.8 V and 3.3 V modes 0.75 1.15 6 Rev. B | Page 3 of 48 50 V V MHz HMC832A Parameter LD/SDO LOGIC OUTPUT Output High Voltage High (VOH) Low (VOL) SCK Clock Frequency Rate Capacitive Load Load Current Output Resistance When Driver Is Low (RON) Pull-Up Resistor (RUP) Rise Time Fall Time SCK to SDO Turnaround Time Output Impedance (ROUT) POWER SUPPLY VOLTAGES 3.3 V Supplies POWER SUPPLY CURRENTS High Performance Mode 2500 MHz, 11 dB Gain 800 MHz, 11 dB Gain 2500 MHz, 6 dB Gain 800 MHz, 6 dB Gain 2500 MHz, 1 dB Gain 800 MHz, 1 dB Gain Low Current Mode 2500 MHz, 6 dB Gain 800 MHz, 6 dB Gain 2500 MHz, 1 dB Gain 800 MHz, 1 dB Gain Power-Down Crystal Off Crystal On, 100 MHz POWER-ON RESET Typical Reset Voltage on DVDD Minimum DVDD Voltage for No Reset Power-On Reset Delay VCO CLOSED-LOOP PHASE NOISE fO at 1600 MHz, 10 kHz Offset Data Sheet Test Conditions/Comments Min CMOS 1.8 V mode (Register 0x0F[9:8] = 00b, Register 0x0B[22] = 0) CMOS 3.3 V mode (Register 0x0F[9:8] = 00b, Register 0x0B[22] = 1) Open-drain mode (Register 0x0F[9:8] = 01b)4 CMOS mode (Register 0x0F[9:8] = 00b) Open-drain mode (Register 0x0F[9:8] = 01b)5 CMOS mode (Register0x0F[9:8] = 00b)6 Open-drain mode (Register0x0F[9:8] = 01b)7 CMOS mode (Register0x0F[9:8] = 00b) Open-drain mode (Register0x0F[9:8] = 01b)8 CMOS mode (Register0x0F[9:8] = 00b)9 Open-drain mode (Register0x0F[9:8] = 01b)10 Open-drain mode (Register0x0F[9:8] = 01b) Open-drain mode (Register0x0F[9:8] = 01b) CMOS mode (Register0x0F[9:8] = 00b)11 CMOS mode (Register0x0F[9:8] = 00b)11 CMOS mode (Register0x0F[9:8] = 00b)11 1.8 V mode (Register 0x0B[22] = 0) AVDD, VCCHF, VCCPS, VCCPD, RVDD, DVDD, VPPCP, VDDLS, VCC1, VCC2 Typ Max Unit 1.3 2.3 V VDD − 0.2 1.8 VDD V 0.1 V V 0.4 6 5 10 500 100 1000 0.5 + 0.3(CLOAD) 1.5 + 0.2(CLOAD) 0.9 + 0.1(CLOAD) 100 3.1 VCO_REG 0x03[1:0] = 3d12 11 dB gain (VCO_REG 0x07[3:0] = 11d), single-ended output (VCO_REG 0x03[3:2] = 2d) Single-ended output 6 dB gain (VCO_REG 0x07[3:0] = 6d), differential output (VCO_REG 0x03[3:2] = 3d) Differential output 1 dB gain (VCO_REG 0x07[3:0] = 1d), differential output (VCO_REG 0x03[3:2] = 3d) Differential output VCO_REG 0x03[1:0] = 1d12 6 dB gain (VCO_REG 0x07[3:0] = 6d), differential output (VCO_REG 0x03[3:2] = 3d) Differential output 1 dB gain (VCO_REG 0x07[3:0] = 1d), differential output (VCO_REG 0x03[3:2] = 3d) Differential output Register 0x01 = 0, crystal not clocked Register 0x01 = 0, crystal clocked at 100 MHz 3.3 Rev. B | Page 4 of 48 7 10 12 200 MHz MHz pF pF mA mA Ω Ω ns ns ns Ω 3.5 V 219 mA 230 226 mA mA 237 210 mA mA 221 mA 195 mA 205 180 mA mA 192 mA 10 5 µA mA 700 250 mV V µs −110 dBc/Hz 1.5 See Figure 3 50 10 20 10 3.6 7.2 200 Data Sheet Parameter VCO OPEN-LOOP PHASE NOISE fO at 2 GHz13 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset fO at 2 GHz/2 = 1 GHz13 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset fO at 3 GHz/30 = 100 MHz13 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset 250 kHz Offset fO13 HMC832A Test Conditions/Comments Frequency Resolution Fundamental Mode Divider Mode Reference Spurs FIGURE OF MERIT (FOM) Floor Integer Mode Floor Fractional Mode Flicker (Both Modes) Typ Max Unit −88 −116 −139 −157 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −93 −122 −145 −159 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −110 −139 −160 −163 −163 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −124.5 −122.5 −122.0 −121.0 dBc/Hz dBc/Hz dBc/Hz dBc/Hz −113.5 −113.5 −112.5 −109.5 500 dBc/Hz dBc/Hz dBc/Hz dBc/Hz µs fPD/224 Hz fPD/(224 × output divider) −85 Hz −229 −226 −268 dBc/Hz dBc/Hz dBc/Hz Over manufacturing process variations with 3.3 V power supply at 25°C fO = 1584 MHz fO = 1998 MHz fO = 2416 MHz fO = 2812 MHz PLL Phase Noise at 20 kHz Offset, 50 MHZ PFD Rate fO = 1582.896 MHz fO = 1998.25 MHz fO = 2415.735 MHz fO = 2811.21 MHz Lock Time Min Over process with 3.3 V power supply at 25°C, measured with >200 kHz loop bandwidth Depends on loop filter bandwidth, PFD rate, and definition of lock (to within ±Hz or ±degrees of settling) Depends on PFD rate and VCO output divider setting 1.5 GHz to 3 GHz output; at typical phase detector frequency (fPD) of 50 MHz, typical resolution = 3 Hz