EVAL-ADF7024DB2Z

Easy to Use, Low Power, Sub GHz, ISM/SRD, FSK/GFSK, Transceiver IC ADF7024 Data Sheet FEATURES Receiver performance Highly linear: −11.5 dBm input IP3 Blocking: 76 dB at 10 MHz offset Receiver sensitivity, bit error rate (BER) −111 dBm at 9.6 kbps −105 dBm at 100 kbps Low power: 12.8 mA in Rx Transmitter performance High efficiency power amplifier (PA): 23.3 mA in Tx at 10 dBm Output power range: −20 dBm to +13.5 dBm Output power resolution: 0.5 dB Low power mode performance 0.33 μA in PHY_SLEEP mode (Deep Sleep Mode 1) 0.75 μA in PHY_SLEEP mode (32 kHz RC oscillator active) 11.75 μA autonomous Rx sniff using SWM, 300 kbps Supported regulations ETSI EN 300 220 FCC Part 15.231, Part 15.247, Part 15.249 Radio frequency (RF) bands: 431 MHz to 435 MHz and 862 MHz to 928 MHz Data rates supported: 9.6 kbps, 38.4 kbps, 50 kbps, 100 kbps, 200 kbps, and 300 kbps Modulation: two-level frequency (FSK) and Gaussian frequency (GFSK) shift keying 2.2 V to 3.6 V power supply Ultralow power sleep modes for long battery life Simple serial port interface (SPI) control interface Fast radio state transitions Automatic frequency control (AFC) and automatic gain control (AGC) Digital received signal strength indication (RSSI) Fully integrated low noise RF synthesizer and transmit (Tx)/receive (Rx) switch Image rejection calibration (U.S. Patent 8,238,865 and U.S. Patent 8,358,993) Integrated packet management support Insertion/detection of preamble/sync word/cyclic redundancy check (CRC) Manchester and 8-bit/10-bit data encoding and decoding Data whitening 240-byte packet buffer for Tx/Rx data Smart wake mode (SWM) Autonomous carrier sense, packet sniffing, and reception Integrated battery alarm and temperature sensor Integrated RC oscillator On-chip, 8-bit analog-to-digital converter (ADC) 5 mm × 5 mm, 32-lead LFCSP APPLICATIONS Wireless sensor networks (WSNs) Home and building automation
sset tracking Process and building control Industrial control Internet of Things (IoT) FUNCTIONAL BLOCK DIAGRAM IRQ CTRL LNA RFI_P LOW IF RECEIVER RFI_N ADF7024 RFO LDO (1 TO 4) PA DIGITAL BASEBAND, PACKET HANDLER, AND MEMORY SYNTHESIZER IRQ_GP3 CS MISO SPI SCLK MOSI TRANSMITTER GPx GPx BIAS TEMPERATURE SENSOR BATTERY MONITOR 32kHz RC OSC SMART WAKE CONTROLLER 26MHz OSC CREGx RBIAS XOSC26P, XOSC26N 12027-001 2 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF7024 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions........................... 13 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 15 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 21 Revision History ............................................................................... 2 SPI Interface ................................................................................ 21 General Description ......................................................................... 3 Radio Control ............................................................................. 21 Specifications..................................................................................... 4 Memory Map .............................................................................. 21 RF and Synthesizer Specifications .............................................. 4 Radio Blocks ............................................................................... 21 Transmitter Specifications ........................................................... 5 Radio Profiles .............................................................................. 22 Receiver Specifications ................................................................ 6 Packet Management ................................................................... 22 Timing and Digital Specifications .............................................. 8 Smart Wake Modes .................................................................... 22 Auxilary Block Specifications ..................................................... 9 Typical Application Circuit ........................................................... 23 General Specifications ............................................................... 10 Outline Dimensions ....................................................................... 24 Timing Specifications ................................................................ 11 Ordering Guide .......................................................................... 24 Absolute Maximum Ratings .......................................................... 12 ESD Caution ................................................................................ 12 REVISION HISTORY 7/15—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to General Description Section ...................................... 3 Changes to Theory of Operation Section .................................... 21 Changes to Radio Profiles Section ............................................... 22 Changes to Typical Application Circuit Section......................... 23 7/14—Rev. 0 to Rev. A Changes to Adjacent Channel Rejection Parameter .................... 6 Changes to Table 11 ........................................................................ 21 Updated Outline Dimensions ....................................................... 24 6/14—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet ADF7024 GENERAL DESCRIPTION The ADF7024 is an ultralow power, integrated transceiver for use in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. Its ease of use and high performance make it suitable for a wide variety of wireless applications. The ADF7024 is suitable for operation under the European ETSI EN 300-220 regulation, the North American FCC Part 15 regulation, and other similar regulatory standards. The ADF7024 can operate under a number of predefined radio profiles. For each radio profile, optimized register settings are provided for the ADF7024 radio. This ensures that the RF communication layer works seamlessly, allowing the user to concentrate on the protocol and system level design and prototyping. The radio profiles cover common data rate and modulation options. There are six radio profiles in total, as shown in Table 1. The ADF7024 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance. The low IF receiver minimizes power consumption and provides excellent sensitivity. The receiver is exceptionally linear and, therefore, is very resilient to the presence of interferers in spectrally noisy environments. The highly efficient transmitter has programmable output power up to 13.5 dBm and automatic power amplifier (PA) ramping to meet transient spurious specifications. The RF synthesizer comprises a voltage controlled oscillator (VCO), a low noise fractional-N phase-locked loop (PLL) and a loop filter, all of which are fully integrated and automatically calibrated. This agile frequency synthesizer facilitates the implementation of frequency-hopping spread spectrum (FHSS) systems. The smart wake mode (SWM) allows the ADF7024 to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption. The ADF7024 eases the processing burden of the host processor by integrating the lower layers of a typical communication protocol stack. The host processor can configure the ADF7024 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function. A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). For more information, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package. Table 1. Radio Profiles Radio Profile A B C D E F Data Rate (kbps) 9.6 38.4 50 100 200 300 Modulation FSK/GFSK FSK/GFSK FSK/GFSK FSK/GFSK FSK/GFSK FSK/GFSK Frequency Deviation (kHz) 9.6 20 25 25 50 75 IF Bandwidth (kHz) 100 100 100 100 200 300 Rev. B | Page 3 of 24 Typical Channel Spacing (kHz) 200 200 200 200 400 600 RF Range (MHz) 862 to 928 431 to 435, 862 to 928 862 to 928 862 to 928 862 to 928 862 to 928 ADF7024 Data Sheet SPECIFICATIONS VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. RF AND SYNTHESIZER SPECIFICATIONS Table 2. Parameter RF CHARACTERISTICS Frequency Ranges Min SPURIOUS EMISSIONS Integer Boundary Spurious 910.1 MHz 911.0 MHz Reference Spurious 868 MHz/915 MHz Clock Related Spur Level Max Unit Test Conditions/Comments 928 435 MHz MHz All radio profiles Radio Profile B only 396.7 −88 Hz dBc/Hz 10 kHz offset, PA output power = 10 dBm, RF = 868 MHz −126 −131 −142 142 56 dBc/Hz dBc/Hz dBc/Hz μs μs PA output power = 10 dBm, RF = 868 MHz PA output power = 10 dBm, RF = 868 MHz PA output power = 10 dBm, RF = 868 MHz Parallel load resonant crystal 1800 2.1 310 388 MHz pF Ω pF μs μs −39 dBc −79 dBc Radio Profile A, integer boundary spur at 910 MHz (26 MHz × 35), inside synthesizer loop bandwidth Radio Profile A, integer boundary spur at 910 MHz (26 MHz × 35), outside synthesizer loop bandwidth −80 −60 dBc dBc 862 431 PHASE-LOCKED LOOP (PLL) Channel Frequency Resolution Phase Noise (In-Band) Phase Noise at Offset 1 MHz 2 MHz 10 MHz VCO Calibration Time Synthesizer Settling Time CRYSTAL OSCILLATOR Crystal Frequency Recommended Load Capacitance Maximum Crystal ESR Pin Capacitance Start-Up Time Typ 26 7 18 Rev. B | Page 4 of 24 Frequency synthesizer settles to within ±5 ppm of the target frequency within this time following the VCO calibration in transmit and receive 26 MHz crystal with 18 pF load capacitance Capacitance for XOSC26P and XOSC26N 26 MHz crystal with 7 pF load capacitance 26 MHz crystal with 18 pF load capacitance Radio Profile A Measured in a span of ±350 MHz, RF = 868.95 MHz, PA output power = 10 dBm, VDD = 3.6 V Data Sheet ADF7024 TRANSMITTER SPECIFICATIONS Table 3. Parameter DATA RATE Radio Profile A Radio Profile B Radio Profile C Radio Profile D Radio Profile E Radio Profile F FSK/GFSK FREQUENCY DEVIATION Radio Profile A Radio Profile B Radio Profile C Radio Profile D Radio Profile E Radio Profile F GAUSSIAN FILTER BANDWITH TIME (BT) POWER AMPLIFIER Maximum Power1 Minimum Power Transmit Power Variation vs. Temperature Variation vs. VDD Flatness Programmable Step Size HARMONICS Second Harmonic Third Harmonic All Other Harmonics OPTIMUM PA LOAD IMPEDANCE PA Output in Transmit Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz PA Output in Receive Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz 1 2 Min Typ Max Unit Test Conditions/Comments 9.6 38.4 50 100 200 300 kbps kbps kbps kbps kbps kbps 9.6 20 25 25 50 75 0.5 kHz kHz kHz kHz kHz kHz 13.5 −20 dBm dBm Programmable, separate PA and LNA match2 ±0.5 ±1 ±1 0.5 dB dB dB dB −40°C to +85°C, RF = 868 MHz 2.2 V to 3.6 V, RF = 868 MHz 902 MHz to 928 MHz and 863 MHz to 870 MHz −20 dBm to +13.5 dBm, programmable in 60 steps 868 MHz, unfiltered conductive, PA output power = 10 dBm −15.1 −29.3 −47.6 dBc dBc dBc 50.8 + j10.2 45.5 + j12.1 46.8 + j19.9 Ω Ω Ω 9.4 − j124 9.5 − j130.6 11.9 − j260.1 Ω Ω Ω Not programmable Measured as the maximum unmodulated power. A combined single-ended PA and LNA match can reduce the maximum achievable output power by as much as 1 dB. Rev. B | Page 5 of 24 ADF7024 Data Sheet RECEIVER SPECIFICATIONS Table 4. Parameter INPUT SENSITIVITY, BIT ERROR RATE (BER)1 Radio Profile A Radio Profile B Radio Profile C Radio Profile D Radio Profile E Radio Profile F INPUT SENSITIVITY, PACKET ERROR RATE (PER)3 Radio Profile A Radio Profile B Radio Profile C Radio Profile D Radio Profile E Radio Profile F LNA AND MIXER, INPUT IP3 LNA Gain Minimum Maximum LNA AND MIXER, INPUT IP2 Gain Maximum LNA, Maximum Mixer Minimum LNA, Minimum Mixer LNA AND MIXER, 1 dB COMPRESSION POINT Gain Maximum LNA, Maximum Mixer Minimum LNA, Minimum Mixer ADJACENT CHANNEL REJECTION CW Interferer Min Typ Max Unit −111 −107.5 −107.4 −105 −103 −100.5 dBm dBm dBm dBm dBm dBm −110.6 −106 −104.1 −102.6 −99.1 −97.9 dBm dBm dBm dBm dBm dBm −11.5 −12.2 dBm dBm Test Conditions/Comments BER = 10−3, LNA and PA matched separately2 9.6 kbps 38.4 kbps 50 kbps 100 kbps 200 kbps 300 kbps At PER = 1%, LNA and PA matched separately,2 packet length = 128 bits 9.6 kbps 38.4 kbps 50 kbps 100 kbps 200 kbps 300 kbps Receiver local oscillator (LO) frequency (fLO) = 914.8 MHz, fSOURCE1 = fLO + 0.4 MHz, fSOURCE2 = fLO + 0.7 MHz fLO = 920.8 MHz, fSOURCE1 = fLO + 1.1 MHz, fSOURCE2 = fLO + 1.3 MHz 18.5 27 dBm dBm RF = 915 MHz −21.9 −21 dBm dBm 200 kHz Channel Spacing 400 kHz Channel Spacing 600 kHz Channel Spacing Modulated Interferer 41 40 41 dB dB dB 200 kHz Channel Spacing 400 kHz Channel Spacing 600 kHz Channel Spacing CO-CHANNEL REJECTION 37 34 35 −4 dB dB dB dB Rev. B | Page 6 of 24 Wanted signal 3 dB above the input sensitivity level (BER = 10−3), CW interferer power level increased until BER = 10−3, image calibrated Radio Profile B, RF = 433 MHz Radio Profile E Radio Profile F Wanted signal 3 dB above the input sensitivity level (BER = 10−3), modulated interferer with the same modulation as the wanted signal; interferer power level increased until BER = 10−3, image calibrated Radio Profile B, RF = 433 MHz Radio Profile E Radio Profile F Desired signal 10 dB above the input sensitivity level (BER = 10−3), Radio Profile B, RF = 868 MHz Data Sheet Parameter BLOCKING RF = 433 MHz ±2 MHz ±10 MHz RF = 868 MHz ±2 MHz ±10 MHz RF = 915 MHz ±2 MHz ±10 MHz BLOCKING, ETSI EN 300 220 ±2 MHz ±10 MHz WIDEBAND INTERFERENCE REJECTION ADF7024 Min Typ Max Unit 68 76 dB dB 66 74 dB dB 66 74 dB dB Measurement procedure as per ETSI EN 300-220-1 V2.3.1; desired signal 3 dB above the ETSI EN 300-220 reference sensitivity level of −99 dBm, Radio Profile B, unmodulated interferer −28 −20.5 75 dBm dBm dB 36/45 40/54 dB dB 1 kHz −97 to −26 ±2 ±3 12 dBm dB dB dBm 75.9 − j32.3 78.0 − j32.4 95.5 − j23.9 Ω Ω Ω 7.6 + j9.2 7.7 + j8.6 7.9 + j4.6 Ω Ω Ω −66 −62 dBm dBm IMAGE CHANNEL ATTENUATION 868 MHz, 915 MHz 433 MHz AFC Accuracy RSSI Range at Input Linearity Absolute Accuracy MAXIMUM RF INPUT LEVEL LNA INPUT IMPEDANCE, DIFFERENTIAL Receive Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz Transmit Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz RX SPURIOUS EMISSIONS4 Maximum < 1 GHz Maximum > 1 GHz Test Conditions/Comments Desired signal 3 dB above the input sensitivity level (BER = 10−3), carrier wave interferer, power level increased until BER = 10−3, Radio Profile B 1 RF = 868 MHz, swept from 10 MHz to 100 MHz either side of the RF Measured as image attenuation at the IF filter output, carrier wave interferer at 400 kHz below the channel frequency, 100 kHz IF filter bandwidth Uncalibrated/calibrated Uncalibrated/calibrated At antenna input, unfiltered conductive At antenna input, unfiltered conductive Sensitivity measured with FSK modulation. Sensitivity for combined Tx/Rx matching network case is typically 1 dB less than separate Tx/Rx matching networks. Sensitivity measured with FSK modulation and AFC disabled. 4 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications. 2 3 Rev. B | Page 7 of 24 ADF7024 Data Sheet TIMING AND DIGITAL SPECIFICATIONS Table 5. Parameter Rx AND Tx TIMING PARAMETERS PHY_ON to PHY_RX (on CMD_PHY_RX) PHY_ON to PHY_TX (on CMD_PHY_TX) LOGIC INPUTS Input Voltage High Low Input Current Input Capacitance LOGIC OUTPUTS Output Voltage High Low GPx Rise/Fall GPx Load Maximum Output Current ATB OUTPUTS ADCIN_ATB3 and ATB4 Output High Voltage, VOH Output Low Voltage, VOL Maximum Output Current GP5_ATB1 and ATB2 Output High Voltage, VOH Output Low Voltage, VOL Maximum Output Current Symbol Min VINH VINL IINH/IINL CIN 0.7 × VDD VOH VOL VDD − 0.4 Typ Max Unit Test Conditions/Comments 300 μs Includes VCO calibration and synthesizer settling 296 μs Includes VCO calibration and synthesizer settling, does not include PA ramp-up 0.2 × VDD ±1 10 0.4 5 10 5 V V µA pF V V ns pF mA IOH = 500 µA IOL = 500 µA Used for external PA and LNA control 1.8 0.1 0.5 V V mA VDD 0.1 5 V V mA Rev. B | Page 8 of 24 Data Sheet ADF7024 AUXILARY BLOCK SPECIFICATIONS Table 6. Parameter 32 kHz RC OSCILLATOR Frequency Frequency Accuracy Frequency Drift Temperature Coefficient Voltage Coefficient Calibration Time WAKE-UP CONTROLLER (WUC) Hardware Timer Wake-Up Period Firmware Timer Wake-Up Period ADC Resolution DNL INL Conversion Time Input Capacitance BATTERY MONITOR Absolute Accuracy Alarm Voltage Set Point Alarm Voltage Step Size Start-Up Time Current Consumption TEMPERATURE SENSOR Range Resolution Accuracy of Temperature Readback Min Typ Max Unit Test Conditions/Comments 32.768 1.5 kHz % After calibration After calibration at 25°C 0.14 4 1.25 %/°C %/V ms 61 × 10−6 1.31 × 105 sec 1 216 Hardware periods 8 ±1 ±1 1 12.4 Bits LSB LSB µs pF ±45 1.7 2.7 62 100 30 −40 +85 mV V mV µs µA 0.3 −4 to +7 °C °C °C ±4 °C ±3 °C Rev. B | Page 9 of 24 Firmware counter counts of the number of hardware wake-up cycles, resolution of 16 bits VDD from 2.2 V to 3.6 V, TA = 25°C VDD from 2.2 V to 3.6 V, TA = 25°C 5-bit resolution When enabled With averaging Temperature range = −40°C to +85°C (calibrated at 25°C) Temperature range = −36°C to +84°C (calibrated at 25°C) Temperature range = −12°C to +79°C (calibrated at 25°C) ADF7024 Data Sheet GENERAL SPECIFICATIONS Table 7. Parameter TEMPERATURE RANGE, TA VOLTAGE SUPPLY VDD TRANSMIT CURRENT CONSUMPTION 433 MHz −10 dBm 0 dBm 10 dBm 13.5 dBm 868 MHz/915 MHz −10 dBm 0 dBm 10 dBm 13.5 dBm POWER MODES PHY_SLEEP (Deep Sleep Mode 2) PHY_SLEEP (Deep Sleep Mode 1) PHY_SLEEP (RC Oscillator Active) PHY_OFF PHY_ON PHY_RX SMART WAKE MODE Min −40 Typ 2.2 Max +85 Unit °C Test Conditions/Comments 3.6 V Applied to VDDBAT1 and VDDBAT2 In the PHY_TX state, PA matched to 50 Ω, separate PA and LNA match 8.7 12.2 23.3 32.1 mA mA mA mA 10.3 13.3 24.1 32.1 mA mA mA mA 0.18 0.33 0.75 1 µA µA µA mA 1 mA 12.8 mA 21.78 µA 11.75 µA Rev. B | Page 10 of 24 Sleep mode, memory not retained Sleep mode, memory retained WUC active, RC oscillator running, memory retained Device in PHY_OFF state, 26 MHz oscillator running, digital and synthesizer regulators active, all register values retained Device in PHY_ON state, 26 MHz oscillator running, digital, synthesizer, VCO, and RF regulators active, baseband filter calibration performed, all register values retained Device in PHY_RX state Average current consumption Autonomous reception every 1 sec, with receive dwell time of 1.25 ms, using RC oscillator, Radio Profile B Autonomous reception every 1 sec, with receive dwell time of 0.5 ms, using RC oscillator, Radio Profile F Data Sheet ADF7024 TIMING SPECIFICATIONS VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, VGND = GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Table 8. SPI Interface Timing Parameter t2 t3 t4 t5 t6 t7 t8 t9 t11 t12 t13 t14 t15 Limit 85 85 85 170 10 5 5 85 270 310 20 20 25 Unit ns min ns min ns min ns min ns max ns min ns min ns min ns min µs typ ns max ns max µs max Test Conditions/Comments CS low to SCLK setup time SCLK high time SCLK low time SCLK period SCLK falling edge to MISO delay MOSI to SCLK rising edge setup time MOSI to SCLK rising edge hold time SCLK falling edge to CS hold time CS high time CS low to MISO high wake-up time, 26 MHz crystal with 7 pF load capacitance, TA = 25°C SCLK rise time SCLK fall time Initialization time; do not issue a command during this time; alternatively, poll the status word and wait for the CMD_READY bit to go high Timing Diagrams CS t11 t3 t2 t4 t5 t14 t13 t9 SCLK t6 BIT 7 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 2 1 0 7 BIT 0 X BIT 7 t8 t7 MOSI BIT 6 7 6 5 4 3 7 Figure 2. SPI Interface Timing CS t9 t15 7 SCLK t12 6 5 4 3 2 1 0 t6 MISO SLEEP WAKE UP SPI READY Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready t12 After the Falling Edge of CS) Rev. B | Page 11 of 24 12027-003 X SPI STATE 12027-002 MISO ADF7024 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Connect the exposed pad of the LFCSP to ground. Table 9. This device is a high performance, RF integrated circuit with an ESD rating of