LTC3417A-2
Dual Synchronous
1.5A/1A 4MHz
Step-Down DC/DC Regulator
DESCRIPTION
FEATURES
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High Efficiency: Up to 95%
1.5A/1A Guaranteed Minimum Output Current
Synchronizable to External Clock
No Schottky Diodes Required
Programmable Frequency Operation: 1.5MHz or
Adjustable From 0.6MHz to 4MHz
Low Ripple ( VOUT2:
IRMS = 2 •I1 •I2 • D2(1– D1) +I2 2 (D2 – D22 ) +I12 (D1– D12 )
VOUT2 > VOUT1:
IRMS = 2 •I1 •I2 • D1(1– D2) +I2 2 (D2 – D22 ) +I12 (D1– D12 )
where.
D1=
VOUT1
V
and D2 = OUT2
VIN
VIN
Table 1
MANUFACTURER
PART NUMBER
VALUE (μH)
MAX DC CURRENT (A)
DCR
DIMENSIONS L × W × H (mm)
L1 on OUT1
Toko
A920CY-1R5M-D62CB
A918CY-1R5M-D62LCB
1.5
1.5
2.8
2.9
0.014
0.018
6 × 6 × 2.5
6×6×2
Coilcraft
D01608C-152ML
1.5
2.6
0.06
6.6 × 4.5 × 2.9
Sumida
CDRH4D22/HP 1R5
1.5
3.9
0.031
5 × 5 × 2.4
Midcom
DUP-1813-1R4R
1.4
5.5
0.033
4.3 × 4.8 × 3.5
Toko
A915AY-2ROM-D53LC
2.0
3.9
0.027
5×5×3
Coilcraft
D01608C-222ML
2.2
2.3
0.07
6.6 × 4.5 × 2.9
Sumida
CDRH3D16/HP 2R2
2.2
2.2
1.75
1.6
0.047
0.035
4 × 4 × 1.8
3.2 × 3.2 × 2
Midcom
DUP-1813-2R2R
2.2
3.9
0.047
4.3 × 4.8 × 3.5
L2 on OUT2
3417a2fa
10
LTC3417A-2
APPLICATIONS INFORMATION
When D1 = D2 then the equation simplifies to:
IRMS = (I1 +I2 ) D (1– D)
or
IRMS = (I1 +I2 )
VOUT ( VIN – VOUT )
VIN
where the maximum average output currents I1 and I2
equal the respective peak currents minus half the peakto-peak ripple currents:
ΔI
I1 =ILIM1 – L1
2
ΔIL2
I2 =ILIM2 –
2
These formula have a maximum at VIN = 2VOUT, where
IRMS = (I1 + I2)/2. This simple worst case is commonly
used to determine the highest IRMS.
For “out of phase” operation, the ripple current can be
lower than the “in phase” current.
In the “out of phase” case, the maximum IRMS does not
occur when VOUT1 = VOUT2. The maximum typically occurs when VOUT1 – VIN/2 = VOUT2 or when VOUT2 – VIN/2
= VOUT1. As a good rule of thumb, the amount of worst
case ripple is about 75% of the worst case ripple in the
“in phase” mode. Also note that when VOUT1 = VOUT2 =
VIN/2 and I1 = I2, the ripple is zero.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours lifetime. This makes
it advisable to further derate the capacitor, or choose a
capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet the
size or height requirements of the design. An additional
0.1μF to 1μF ceramic capacitor is also recommended on
VIN for high frequency decoupling, when not using an all
ceramic capacitor solution.
Output Capacitor (COUT1 and COUT2) Selection
The selection of COUT1 and COUT2 is driven by the required
ESR to minimize voltage ripple and load step transients.
Typically, once the ESR requirement is satisfied, the
capacitance is adequate for filtering. The output ripple
(ΔVOUT) is determined by:
1
VOUT IL ESRCOUT +
8 • fO • COUT
where fO = operating frequency, COUT = output capacitance
and ΔIL = ripple current in the inductor. The output ripple
is highest at maximum input voltage, since ΔIL increases
with input voltage. With ΔIL = 0.35ILOAD(MAX), the output
ripple will be less than 100mV at maximum VIN and fO =
1MHz with:
ESRCOUT < 150mΩ
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface tantalums, available in case heights ranging from
2mm to 4mm. Aluminum electrolytic capacitors have a
significantly larger ESR, and are often used in extremely
cost-sensitive applications provided that consideration
3417a2fa
11
LTC3417A-2
APPLICATIONS INFORMATION
is given to ripple current ratings and long term reliability.
Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, high voltage and
temperature coefficient and exhibit audible piezoelectric
effects. In addition, the high Q of ceramic capacitors along
with trace inductance can lead to significant ringing. Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3417A-2 in parallel with the
main capacitors for high frequency decoupling.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Because the
LTC3417 control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size. When choosing the input and output
ceramic capacitors, choose the X5R or X7R dielectric
formulations. These dielectrics have the best temperature
and voltage characteristics of all the ceramics for a given
value and size.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must fulfill a charge storage requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4
cycles are required to respond to a load step, but only in
the first cycle does the output drop linearly. The output
droop, VDROOP , is usually about 2 to 3 times the linear
droop of the first cycle. Thus, a good place to start is with
the output capacitor size of approximately:
COUT ≈ 2.5
ΔIOUT
fO • VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage
The LTC3417A-2 develops a 0.8V reference voltage between
the feedback pins, VFB1 and VFB2, and the signal ground
as shown in Figure 4. The output voltages are set by two
resistive dividers according to the following formulas:
R1
VOUT1 0.8V 1+
R2
R3
VOUT2 0.8V 1+
R4
Keeping the current small (1μF) input capacitors. The discharged input capacitors are effectively
put in parallel with COUT, causing a rapid drop in VOUT. No
regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap™ controller
is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and
soft- starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (P1+ P2 + P3 +…)
where P1, P2, etc. are the individual losses as a percentage of input power.
Hot Swap is a trademark of Linear Technology Corporation.
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14
LTC3417A-2
APPLICATIONS INFORMATION
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3417A-2 circuits: 1) LTC3417A-2 IS current, 2)
switching losses, 3) I2R losses, 4) other losses.
1) The IS current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and
control currents. IS current results in a small (< 0.1%)
loss that increases with VIN, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge moves from
VIN to ground. The resulting charge over the switching
period is a current out of VIN that is typically much larger
than the DC bias current. The gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
3) I2R losses are calculated from the DC resistances of the
internal switches, RSW, and the external inductor, RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET RDS(ON) and the duty cycle (DC) as
follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
where RL is the resistance of the inductor.
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design
of a system. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESRCOUT at
the switching frequency. Other losses including diode
conduction losses during dead-time and inductor core
losses generally account for less than 2% total additional
loss.
Thermal Considerations
The LTC3417A-2 requires the package Exposed Pad
(PGND2/GNDD pin) to be well soldered to the PC board.
This gives the DFN and TSSOP packages exceptional
thermal properties, compared to similar packages of this
size, making it difficult in normal operation to exceed the
maximum junction temperature of the part. In a majority
of applications, the LTC3417A-2 does not dissipate much
heat due to its high efficiency. However, in applications
where the LTC3417A-2 is running at high ambient temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both switches
in both regulators will be turned off and the SW nodes will
become high impedance.
To prevent the LTC3417A-2 from exceeding its maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
TRISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
As an example, consider the case when the LTC3417A-2
is in dropout in both regulators at an input voltage of 3.3V
with load currents of 1.5A and 1A. From the Typical Performance Characteristics graph of Switch Resistance, the
RDS(ON) resistance of the 1.5A P-channel switch is 0.09Ω
and the RDS(ON) of the 1A P-channel switch is 0.163Ω.
3417a2fa
15
LTC3417A-2
APPLICATIONS INFORMATION
The power dissipated by the part is:
Using the 1.5MHz frequency setting (FREQ = VIN), we get
the following equations for L1 and L2:
PD = I12 • RDS(ON)1 + I22 • RDS(ON)2
PD = 1.52 • 0.09 + 12 • 0.163
1.8V
1.8V
1–
= 1.3μH
1.5MHz • 525mA 4.2V
Use 1.5μH.
L1=
PD = 366mW
The DFN package junction-to-ambient thermal resistance,
θJA, is about 43°C/W. Therefore, the junction temperature
of the regulator operating in a 70°C ambient temperature
is approximately:
TJ = 0.366 • 43 + 70
TJ = 85.7°C
Remembering that the above junction temperature is
obtained from an RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. However, we can safely assume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
2.5V
2.5V
1–
= 1.9μH
1.5MHz • 350mA 4.2V
Use 2.2μH.
L2 =
COUT selection is based on load step droop instead of ESR
requirements. For a 2.5% output droop:
COUT1 = 2.5 •
1.5A
= 28μF
1.5MHz ( 5% • 1.8V )
COUT2 = 2.5 •
1A
= 13μF
1.5MHz ( 5% • 2.5V )
Design Example
The closest standard values are 47μF and 22μF.
As a design example, consider using the LTC3417A-2 in
a portable application with a Li-Ion battery. The battery
provides a VIN from 2.8V to 4.2V. One load requires 1.8V
at 1.5A in active mode, and 1mA in standby mode. The
other load requires 2.5V at 1A in active mode, and 500μA
in standby mode. Since both loads still need power in
standby, Burst Mode operation is selected for good low
load efficiency (SYNC/MODE = VIN).
The output voltages can now be programmed by choosing the values of R1, R2, R3, and R4. To maintain high
efficiency, the current in these resistors should be kept
small. Choosing 2μA with the 0.8V feedback voltages makes
R2 and R4 equal to 400k. A close standard 1% resistor is
412k. This then makes R1 = 515k. A close standard 1%
is 511k. Similarily, with R4 at 412k, R3 is equal to 875k.
A close 1% resistor is 866k.
First, determine what frequency should be used. Higher
frequency results in a lower inductor value for a given ΔIL
(ΔIL is estimated as 0.35ILOAD(MAX)). Reasonable values
for wire wound surface mount inductors are usually in the
range of 1μH to 10μH.
The compensation should be optimized for these components by examining the load step response, but a good
place to start for the LTC3417A-2 is with a 5.9kΩ and
2200pF filter on ITH1 and 2.87k and 6800pF on ITH2. The
output capacitor may need to be increased depending on
the actual undershoot during a load step.
CONVERTER OUTPUT
ILOAD(MAX)
ΔIL
SW1
1.5A
525mA
SW2
1A
350mA
The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate speed.
Figure 4 shows a complete schematic for this design.
3417a2fa
16
LTC3417A-2
APPLICATIONS INFORMATION
VIN
2.25V TO 5.5V
CIN
10μF
CIN2
0.1μF
CIN1
0.1μF
R7
100k
VIN1 VIN2
VOUT1
1.8V
1.5A
L1
1.5μH
SW1
C1 22pF
VIN
SW2
RUN1
RUN2
C2 22pF
VIN
LTC3417A-2
R1 511k
VFB1
R2
412k
PHASE
VOUT2
2.5V
1A
R3 866k
VFB2
FREQ
ITH2
EXPOSED
GNDA PAD GNDD
R4
412k
VIN
COUT2
22μF
ITH1
R5
5.9k
R6
2.87k
C3
2200pF
C4
6800pF
3417A-2 F04
L2: MIDCOM DUS-5121-2R2R
COUT2, CIN: KEMET C1206C106K4PAC
L1: MIDCOM DUS-5121-1R5R
COUT1: KEMET C1210C226K8PAC
OUT1 Efficiency vs Load Current
10
100
VIN = 3.6V
VOUT = 1.8V
95 FREQ = 1MHz
REFER TO FIGURE 4
90
1
EFFICIENCY
0.1
85
80
POWER LOSS
POWER LOSS (W)
EFFICIENCY (%)
COUT1
47μF
L2
2.2μH
SYNC/MODE PGOOD
0.01
75
70
0.001
0.01
0.1
1
LOAD CURRENT (A)
0.001
10
3417A-2 F04a
Figure 4. 1.8V at 1.5A/2.5V at 1A Step-Down Regulators
3417a2fa
17
LTC3417A-2
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3417A-2. These items are also illustrated graphically
in the layout diagram of Figure 5. Check the following in
your layout.
1. Does the capacitor CIN connect to the power VIN1
(Pin 2), VIN2 (Pin 8), and PGND2/GNDD (Pin 17) as
close as possible (DFN package)? It may be necessary
to split CIN into two capacitors. This capacitor provides
the AC current to the internal power MOSFETs and
their drivers.
2. Are the COUT1, L1 and COUT2, L2 closely connected? The
(–) plate of COUT1 returns current to PGND1, and the
(–) plate of COUT2 returns current to the PGND2/GNDD
and the (–) plate of CIN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT1 and a ground line terminated near GNDA. The resistor divider, R3 and R4,
must be connected between the (+) plate of COUT2 and
a ground line terminated near GNDA. The feedback
signals VFB1 and VFB2 should be routed away from noise
components and traces, such as the SW lines, and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor CIN, the compensation capacitors
CC1, CC2, CITH1 and CITH2 and all resistors R1, R2, R3,
R4, RITH1 and RITH2 should be routed away from the
SW traces and the inductors L1 and L2.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GNDA pin at one
point which is then connected to the PGND2/GNDD
pin.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to one of the input supplies.
VIN
CIN2
0.1μF
CIN
10μF
VIN2
VIN1
PGND2/
EXPOSED PAD
PGND1
GNDA
COUT2
COUT1
L2
VOUT2
L1
SW1
SW2
CC2
R3
VFB2
LTC3417A-2
RITH2
CITH2
R8
VOUT1
CC1
R1
VFB1
R4
STAR TO
GNDA
VIN
CIN1
0.1μF
R2
ITH2
ITH1
POR
FREQ
RUN2
PHASE
RITH1
R7
STAR TO
GNDA
CITH1
VIN
RUN1
SYNC/MODE
GNDD
3417A-2 F05
Figure 5. Layout Guideline
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18
LTC3417A-2
PACKAGE DESCRIPTION
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
R = 0.115
TYP
5.00 ± 0.10
(2 SIDES)
R = 0.20
TYP
0.65 ± 0.05
3.50 ± 0.05
1.65 ± 0.05
2.20 ± 0.05 (2 SIDES)
9
3.00 ± 0.10
(2 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
NOTCH
PIN 1
TOP MARK
(SEE NOTE 6)
(DHC16) DFN 1103
8
1
0.25 ± 0.05
0.50 BSC
0.75 ± 0.05
0.200 REF
0.25 ± 0.05
0.50 BSC
0.40 ± 0.10
16
4.40 ± 0.05
(2 SIDES)
4.40 ± 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 13 12 11
6.60 ± 0.10
2.74
(.108)
4.50 ± 0.10
6.40
2.74
(.252)
(.108)
BSC
SEE NOTE 4
0.45 ± 0.05
1.05 ± 0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3417a2fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3417A-2
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95% Efficiency, VIN(MIN): 2.3V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V,
IQ = 125μA, ISD < 1μA, TSSOP-16E, 3mm × 3mm DFN-16 Package
LTC3418
8A, 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN(MIN): 2.25V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V,
IQ = 380μA, ISD < 1μA, 5mm × 7mm QFN-38 Package
LTC3419/-1
Dual 600mA/600mA 2.25MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V,
IQ = 35μA, ISD < 1μA, MS10, 3mm × 3mm DFN-10 Package
LTC3438
800mA, 1MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN(MIN): 2.4V, VIN(MAX): 5.5V, VOUT(MIN) = 1.5V to 5.25V,
IQ = 35μA, ISD < 1μA, 2mm × 3mm DFN-8 Package
LTC3440
600mA, 2MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 2.5V to 5.5V,
IQ = 25μA, ISD < 1μA, MS10, 3mm × 3mm DFN-10 Package
LTC3441/2/3
1.2A, 2MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN(MIN): 2.4V, VIN(MAX): 5.5V, VOUT(MIN) = 2.4V to 5.25V,
IQ = 50μA, ISD < 1μA, 3mm × 4mm DFN-12 Package
LTC3530
600mA, 2MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN(MIN): 1.8V, VIN(MAX): 5.5V, VOUT(MIN) = 1.8V to 5.5V,
IQ = 40μA, ISD < 1μA, MS10, 3mm × 3mm DFN-10 Package
LTC3531/-3/3.3 200mA, 1.5MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN(MIN): 1.8V, VIN(MAX): 5.5V, VOUT(MIN) = 2V to 5V,
IQ = 16μA, ISD < 1μA, ThinSOT, 3mm × 3mm DFN-6 Package
LTC3532
500mA, 2MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN(MIN): 2.4V, VIN(MAX): 5.5V, VOUT(MIN) = 2.4V to 5.25V,
IQ = 35μA, ISD < 1μA, MS10E, 3mm × 3mm DFN-10 Package
LTC3542
500mA, 2.25MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V,
IQ = 26μA, ISD < 1μA, 2mm × 2mm DFN-6, ThinSOT Package
LTC3544/B
Quad 100/200/200/300mA, 2.25MHz Synchronous
Step-Down DC/DC Converter
95% Efficiency, VIN(MIN): 2.3V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V,
IQ = 70μA, ISD < 1μA, 3mm × 3mm QFN-16 Package
LTC3545/-1
Triple, 800mA x 3, 2.25MHz Synchronous Step-Down DC/DC 95% Efficiency, VIN(MIN): 2.3V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V,
IQ = 58μA, ISD < 1μA, 3mm × 3mm QFN-16 Package
Converter
LTC3547/B
Dual 300mA, 2.25MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V,
IQ = 40μA, ISD < 1μA, DFN-8 Package
LTC3548/-1/-2
Dual 400mA & 800mA IOUT, 2.25MHz, Synchronous
Step-Down DC/DC Converter
95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V,
IQ = 40μA, ISD < 1μA, MS10E, 3mm × 3mm DFN-10 Package
LTC3560
800mA 2.25MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V,
IQ = 16μA, ISD < 1μA, ThinSOT Package
LTC3561
1.25A, 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V,
IQ = 240μA, ISD < 1μA, 3mm × 3mm DFN-8 Package
LTC3562
Quad, I2C Interface, 600/600/400/400mA , 2.25MHz
Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN(MIN): 2.9V, VIN(MAX): 5.5V, VOUT(MIN) = 0.425V,
IQ = 100μA, ISD < 1μA, 3mm × 3mm QFN-20 Package
ThinSOT is a trademark of Linear Technology Corporation.
20 Linear Technology Corporation
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LT 0808 REV A • PRINTED IN USA
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