LTC6560
Single Channel Transimpedance
Amplifier with Output Multiplexing
FEATURES
DESCRIPTION
220MHz –3dB Bandwidth with 2pF Input
Capacitance
nn Single-Ended Output
nn 74kΩ Transimpedance Gain
nn 4.8pA/√Hz Input Current Noise Density at 200MHz
(2pF)
nn 64nA
RMS Integrated Input Current Noise Over
200MHz (2pF)
nn Linear Input Range 0µA to 30µA
nn Overload Current > ±400mA Peak
nn Fast Overload Recovery: 1mA in 10ns
nn Fast Output MUXing: ENABLED
1E4
1000
100
10
1
MIN. MEASURED SWITCHING TIME
RC MODELED
1
10
100
1000
1E4
INPUT CAPACITOR VALUE (pF)
1E5
6560 G35
Rev. B
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9
LTC6560
TYPICAL PERFORMANCE CHARACTERISTICS USING DC2807
O_MUX Switching Glitch
AC Coupled Input, 10pF
1.25
O_MUX Switching Glitch
AC Coupled Input, 100pF
1.25
INPUT COUPLING CAP = 10pF
1.00
0.75
O_MUX SELECT GLITCH
0.50
0.25
AMPLITUDE (V)
AMPLITUDE (V)
1.00
0
INPUT COUPLING CAP = 100pF
100
200
300
TIME (nSec)
400
O_MUX SELECT GLITCH
0.50
0.25
ChSel
OUT
0
0.75
0
500
ChSel
OUT
0
400
800
1200
TIME (nSec)
1600
6560 G37
Pulse Stretching
CIN = 0.5pF, Using FWHM
USING FULL WIDTH = HALF MAX.
TO DETERMINE OUTPUT PULSE WIDTH
y = 5.1x + 2.0
CIN = 0.5pF
125°C
85°C
25°C
–40°C
CURVE FIT
0
0.2
0.4 0.6 0.8 1 1.2
INPUT CURRENT (mA)
1.4
PULSE STRETCHING (nS)
PULSE STRETCHING (nS)
6560 G36
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1.6
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Pulse Stretching
CIN = 2.0pF, Using FWHM
USING FULL WIDTH = HALF MAX.
TO DETERMINE OUTPUT PULSE WIDTH
y = 8.0x + 2.0
CIN = 2.0pF
125°C
85°C
25°C
–40°C
CURVE FIT
0
0.2
0.4 0.6 0.8 1 1.2
INPUT CURRENT (mA)
1.4
Pulse Stretching
CIN = 4.0pF, Using FWHM
Pulse Width vs ADP Current
Optical Measurement
USING FULL WIDTH = HALF MAX.
TO DETERMINE OUTPUT
PULSE WIDTH
y = 10.5x + 2.0
CIN = 4.0pF
125°C
85°C
25°C
–40°C
CURVE FIT
0
0.2
0.4 0.6 0.8 1 1.2
INPUT CURRENT (mA)
1.6
6560 G39
1.4
1.6
PULSE WIDTH (nS)
PULSE STRETCHING (nS)
6560 G38
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2000
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
APD CAP APPROXIMATELY 4pF
0
6560 G40
2
4
6
APD CURRENT (mA)
8
10
6560 G41
Rev. B
10
For more information www.analog.com
LTC6560
PIN FUNCTIONS
VCCO (Pin 1): Positive Power Supply for the Output Stage.
Typically, 5V. VCCO can be tied to VCCI for single supply
operation. Bypass capacitors of 1000pF and 0.1µF should
be placed as close as possible between VCCO and ground.
DNC (Pins 2 to 4, 7 to 10, 13, 16): Do not connect these
pins. Allow them to float.
IN (Pin 5): Input Pin for Transimpedance Amplifier.
This pin is internally biased to 1.55V when the channel is active. See the Applications section for specific
recommendations.
VREF (Pin 6): Reference Voltage Pin for TIA. This pin sets
the input DC voltage for the TIA. The VREF pin should be
bypassed with a high quality ceramic bypass capacitor
of at least 0.1µF. The bypass cap should be located close
to the VREF pin. The VREF pin has a Thevenin equivalent
resistance of approximately 1.4k and can be overdriven
by an external voltage. If no voltage is applied to VREF, it
will float to a default voltage of approximately 1.55V on a
5V supply when active.
O_MUX (Pin 12): Output MUX is a digital input controlling the output multiplexing function. The pin is functional
when multiple LTC6560s are combined at the output.
When O_MUX is low, the output is enabled. When O_MUX
is high, the input is decoupled from the output. Its default
value is 0V. This MUX pin is ineffective unless a second
LTC6560 is DC-coupled at the output. See Applications
section on how to use O_MUX to expand the channel
count with multiple LTC6560’s. The O_MUX pin has a
29kΩ internal pull-down resistor.
OUTTERM (Pin 14): TIA Output with an Internal Series
50Ω Resistor.
OUT (Pin 15): TIA Output without an Internal Series 50Ω
Resistor.
GND (Exposed Pad Pin 17): Negative Power Supply.
Normally tied to ground. The exposed pad (pin 17) should
have multiple via holes to an underlying ground plane for
low inductance and good heat transfer.
VCCI (Pin 11): Positive Power Supply for the Input Stage.
Typically 5V. Bypass capacitors of 1000pF and 0.1µF
should be placed as close as possible between VCCI
and ground.
BLOCK DIAGRAM
VCCI
IN
VCCO
OUT
OUTPUT
STAGE
TIA
50Ω
GAIN
VREF
GND
OUTTERM
O_MUX
6560 BD
Rev. B
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11
LTC6560
OPERATION
The LTC6560 is a transimpedance amplifier with output
MUXing. A transimpedance amplifier converts an input
current to an output voltage. The output multiplexer capability (O_MUX) allows multiple single channel LTC6560
devices to be combined. For example 2, 4, 6 or 8 current
input channels are easily multiplexed into a single voltage
output.
data loss. As the level of input current exceeds the linear
range, the output pulse width will widen. However, the
recovery time remains in the 10’s of ns. See Figure 10 and
Figure 11 plots of pulse stretching versus input current.
Internally the LTC6560 consists of multiple stages. The
first stage is a transimpedance amplifier. A second voltage
gain stage leads to a final output buffer that can drive a
2VP-P swing into a 100Ω load.
In typical LIDAR applications, the LTC6560 amplifies the
output current of an APD. APDs are biased near breakdown
to achieve high current gain. Under intense optical illumination they can conduct large currents, often in excess
of 1A. The LTC6560 survives and quickly recovers from
large overload currents of this magnitude. Rapid overload recovery is critical for LIDAR applications. During
recovery, any TIA is blinded from subsequent pulses. The
LTC6560 recovers from 1mA saturation events in less
than 12ns without phase reversal, minimizing this form of
VCCI
VCCO
LTC6560
OUT
OUTPUT
STAGE
+
–150V
To increase a LIDAR system’s spatial resolution, many
APDs are deployed, often in an array. To achieve maximum
bandwidth, each APD pixel must have a dedicated TIA, as
increasing CIN will reduce bandwidth. The LTC6560 output multiplexing capability allows compact multichannel
designs without external multiplexers. The use of multiple
LTC6560s works well with multiple single APDs to minimize trace capacitance, cost and solution size.
IN
TIA
TIME-OF-FLIGHT
DETECTOR
50Ω
GAIN
VREF
–
47.5Ω
OUTTERM
GND
O_MUX
6560 F01
Figure 1. Single LTC6560 with DC-Coupled Inputs Driving a TDC with Back-Terminated Cable
VCCI
+
–150V
–
VCCO
LTC6560
OUT 47.5Ω
OUTPUT
STAGE
IN1
AMP
TIA
50Ω
GAIN
VREF
+
LPF
ADC
–
OUTTERM
GND
O_MUX
6560 F02
Figure 2. Typical Application with Output to an ADC
Rev. B
12
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LTC6560
APPLICATIONS INFORMATION
External Bypassing
range by injecting current at the TIA input to offset the
APD’s DC current components. Care must be taken at
the TIA’s input as current injection can also inject noise.
The LTC6560 has separate supply pins for input (VCCI)
and output (VCCO), both of which should be bypassed
with 1000pF and 0.1µF capacitors to ground. For simplest
operation, the input and output supplies should be set to
the same voltage.
AC Coupling the Input
Recommended values for AC coupling are shown in
Table 1. An AC coupled input will block all DC inputs,
preserving the TIA’s full dynamic range. See Figure 3.
However, switching times will degrade depending on
the choice of AC coupling capacitor. When a channel is
switched from inactive to active using the O_MUX control, a glitch will appear at the output. See Figure 5 and
Figure 6. The TIA will not be ready for a desired input
pulse until the glitch has settled. The glitch settling time
is dependent upon the AC coupling capacitor value. The
value of the AC coupling cap must be carefully considered.
A plot of switching times vs. coupling capacitor is shown
in Figure 4.
The LTC6560 has a small internal bypass capacitor connected between the VREF pin and ground to ensure low
input noise. For the lowest possible input noise, the VREF
pin should also be bypassed externally with a high quality 0.1µF ceramic capacitor to ground. This bypass cap
should be located physically close the VREF pin.
AC or DC Input-Coupling: Design Tradeoffs
Coupling the APD to the TIA is a critical design aspect with
many tradeoffs to consider. A DC coupled input is the simplest, requiring minimal components to directly couple
the APD to the TIA. In the DC case, switching times are
fast 100kHz the left side of the output
Rev. B
14
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LTC6560
APPLICATIONS INFORMATION
coupling cap (typically 1000pF) will not have time to fully
discharge before the next pulse arrives. See Figure 3.
If an AC coupled output is desired, a 1kΩ resistor should
be added to the LTC6560 output. The shunt 1kΩ resistor
will insure fast overload recovery and switching times.
For AC coupling, a 1000pF capacitor is recommended
as higher cap values will slow O_MUX switching speed
and smaller values could distort the pulse. A shunt 1kΩ
resistor on the LTC6560 output will increase the quiescent current by 1mA while minimally impacting gain and
output matching. On the other hand, directly DC coupling
the output to a 50Ω load will add 10mA of current draw.
If the LTC6560 output is directly terminated into a high
impedance load like an oscilloscope, the output falling
edge will again be distorted as the LTC6560 has limited
ability to sink current. When monitoring the output with
an oscilloscope, be sure to set the scope’s input termination to 50Ω.
Output MUXing
The output MUX (O_MUX) feature can be used when
multiple LTC6560 share a common DC output connection. The active LTC6560 can be selected by asserting
its O_MUX pin low. The inactive channels must have their
O_MUX pin(s) high. The active LTC6560 effectively overpowers the others, operating in a master/slave relationship. It is recommended to DC couple the outputs after
the series 40-50Ω resistor as this will limit reflection from
unselected outputs. At least one LTC6560 output must
be selected at all times. In its default mode O_MUX is
pulled low and the LTC6560 output is enabled. If there is
MULTIPLE LTC6560s
VCCI
OUT(2)
In high speed TIAs, bandwidth and rise time of the output pulse are a strong function of input capacitance. To
receive narrow pulses, a low capacitance APD sensor is
recommended. Trace capacitance and parasitic pad capacitance should also be minimized at the input. All LTC6560
plots reference CIN,TOT which is the total input capacitance
including APD sensor, trace routing and parasitics.
Using individual LTC6560’s allows the TIA to be placed
close to the APD. This provides tidy routing for individual
APDs and a compact solution size for APD arrays. Traces
should be as short as possible between the APD and the
TIA to avoid coupling and to minimize parasitics.
Internal protection circuitry at each TIA input can protect
the LTC6560 even under strong overdrive conditions.
Most application circuits will not need external protection
diodes which add to the total input capacitance and slows
the rise time. Output rise time can be estimated from the
amplifier bandwidth using the following relationship:
Rise Time =
OUT
47.5Ω
WIRE OR
MUX
47.5Ω
TIME-OF-FLIGHT
DETECTOR
RLOAD
50Ω
GAIN
OUTTERM
GND
0.35
BW
For an APD with 0.5pF of total input capacitance, the rise
time is calculated to be 1.5ns, appropriate for pulses
greater than 4ns wide.
LTC6560
TIA
VREF
APD Input Capacitance
COUT
VCCO
OUTPUT
STAGE
IN
only one LTC6560, then setting the O_MUX pin high will
not MUX anything; however, the output will be isolated
from the input. Using O_MUX to disable a channel will
not reduce power consumption.
O_MUX(2)
O_MUX
RSHUNT
6560 F08
Figure 8. AC Coupled Output
For more information www.analog.com
Rev. B
15
LTC6560
APPLICATIONS INFORMATION
For an APD with 4pF of total input capacitance, the rise
time is calculated to be 2.3ns, appropriate for pulses
greater than 6ns wide.
R1
2k
IN
J1
R2
100Ω
C1
0.1µF
25V
R3
100Ω
0603
TIA
C2
OPT
6560 F09
APD Biasing
An example of a typical APD bias network is shown in
Figure 13. Starting at the negative bias input, two physically large 10kΩ resistors limit the maximum ADP current and filter the HV supply. They are decoupled with
a 1nF capacitor. Moving towards the APD, a second
smaller quenching resistor 50Ω is decoupled by two
0.047µF capacitors. This smaller quenching resistor acts
to dampen ringing especially under high slew rates due to
large optical inputs pulses. It can also limit the maximum
pulse current. All capacitors must be rated for high voltage as APD bias voltages can run above 200V.
Figure 9.
79µA
2.8µA
WITH SERIES 50Ω, INTO 50Ω LOAD
10ns/DIV
120
USING FULL WIDTH = HALF MAX.
TO DETERMINE OUTPUT PULSE WIDTH
110
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
INPUT CURRENT (mA)
10
6560 F11
Figure 11. Pulse Stretching T = 25°C, Using FWHM
12
USING FULL WIDTH = HALF MAX.
TO DETERMINE OUTPUT PULSE WIDTH
11
10
PULSE STRETCHING (nS)
Monotonic pulse widening can be demonstrated using
the DC2807 evaluation board with a DC coupled output.
This evaluation board uses a series 2k resistor to convert a voltage pulse into a current pulse, as it is difficult to obtain a fast current pulse generator. The input
is terminated to 50Ω so that current pulses with precise
amplitude are generated at the TIA input using a voltage
6560 F10
Figure 10. Output Pulse Over Input Current
Dramatically Improving the LTC6560’s Dynamic
Range
The LTC6560’s offers 30µA of linear input range while
monitoring the output amplitude. It is possible to dramatically improve the range over which input current can be
accurately measured by monitoring pulse width. The measurement range can be increased from 30µA to at least
3mA, a 100x improvement in current measurement range!
As the input current exceeds the linear range, the pulse
amplitude saturates. In saturation, the output pulse width
widens in a predictable monotonic manner (Figure 10).
3mA
1mA
155µA
29µA
14µA
PULSE
AMPLITUDE
(200mV/DIV)
PULSE STRETCHING (nS)
Proper APD biasing is key to producing a high-fidelity
output and protecting both the APD and TIA. A negatively
biased APD generally provides the lowest input capacitance and allows the APD to be DC coupled to the TIA. To
keep the optical gain stable the APD bias should be temperature compensated. Quenching resistors in series are
required to limit the maximum current, thereby protecting
the APD and TIA from damage.
9
8
7
6
5
4
3
2
1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
INPUT CURRENT (mA)
6560 F12
Figure 12. Pulse Stretching Detailed T = 25°C, Using FWHM
Rev. B
16
For more information www.analog.com
LTC6560
APPLICATIONS INFORMATION
U3
8
5
7
4
6
3
1
2
R48
50Ω
1206
R47
10k
1206
C45
0.047µF
1206
300V
R75
10k
1206
C70
0.047µF
1206
300V
C46
1nF
1206
HOLE FOR –300V
E8
HOLE FOR GND
E11
6560 F13
APD
Figure 13. Typical APD Bias Current
At high optical input powers, the balun degrades the
APD input current pulse. A DC2803 optical evaluation
circuit without a balun was characterized under high optical input. Using a calibrated laser source, we find that
pulse stretching continues even at extremely high laser
power levels of 50 Watts. At high illumination levels, the
PULSE WIDTH (nS)
In the previous example, we used electrical excitation as
it is difficult to measure the input pulse current of an APD
without disturbing the desired pulse. The LTC6560’s pulse
stretching has also been demonstrated using the DC2803
optical evaluation board at low to moderate optical input
levels. Independently measuring the current generated
during an optical pulse impinging on an APD is quite difficult. The parasitics of any measuring device will impair
the actual pulse input. Referring to Figure 13, using a
balun across series resistor R48 feeding the APD, we can
get an independent determination of APD current to the
TIA for moderate laser input powers. Again, when this
APD current is plotted versus pulse stretching, we find
a nearly linear relationship under moderate illumination.
relationship of input current to pulse stretching no longer
appears perfectly linear, (Figure 15) but the potential to
measure these high optical power levels appears possible.
A calibration of optical input power to pulse stretching
should be done as the optical gain is a strong function of
the APD reverse bias, temperature and the choice of APD.
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0
2000
4000
6000
8000
APD CURRENT (µA)
10000
6560 F14
Figure 14. Pulse Width vs APD Current Optical Measurement
1.2
5W
1.0
PULSE AMPLITUDE (V)
source (Figure 9). Sweeping the TIA pulse input current
from 2.8µA to 3mA, we see that as the current surpasses
the 30µA linear input range, the pulse width increases
(Figure 11 and Figure 12). Figure 12 shows the pulse
width stretching in detail (output response width – input
pulse width). We observe that the stretching is linearly
proportional to the input current. In the linear range up
to 30µA, the pulse does not stretch. FWHM (full width
half max) criteria was used to measure the pulse width.
Pulse output width is taken at half of the maximum swing,
usually around 0.45V. A more sophisticated algorithm
could be used to gain greater accuracy assuming the
pulse edges are accurately captured by an ADC or TDC.
50W
0.8
0.6
507µW
0.4
5mW
0.2 5µW
0.0
0
1
2
TIME (µsec)
3
4
6561 F15
Figure 15. Pulse Width vs Input Hi Power Optical
Rev. B
For more information www.analog.com
17
LTC6560
APPLICATIONS INFORMATION
Evaluation board DC2807A allows for electrical evaluation
using a voltage source to create a current input to the TIA.
A 2k series resistor converts the voltage from a voltage
pulse generator into a current pulse at the input of the TIA.
This board is also compatible with 50Ω test equipment.
Figure 16. DC2807A Single Channel Electrical Evaluation Board
5
4
VCC0
VCC0 EXT
E1
C11
1uF
25V
0805
C10
1000pF
25V
0402
2
1
VCC
JP2
VCC0_SEL
D
GND
3
C12
1000pF
25V
0402
EXT VCC
C13
1uF
25V
0805
E2
E3
VCC
D
E4
VCC0
GND
C4
0.1uF
25V 0603
C5
U1
1000pF
25V 0402
VCC0
2
3
1
NC
OUT
NC
OUTTERM
NC
0_MUX
8
9
0.1uF
25V
0603
R6
NC
17
16
C6
15
R4
47.5
14
R5
OPT
0.1uF
1
25V 0603
OUT
J2
C
C7
13
OPT
OPT
1
OUTTERM
J3
0603
NO STUFF
12
C3
7
GND
NC
VREF
VCC1
R3
100
IN
11
6
C2
OPT
NC
5
25V 0603
R2
100
C
0.1uF
NC
J1
C1
NC
2k
10
R1
1
IN
NC
4
LTC6560-UD
R7
OPT
VCC
C8
1000pF
25V 0402
C9
0.1uF
25V 0603
VCC
R10
1k
JP1
0_MUX
DIS EN
B
B
PCA ADDITIONAL PARTS
MP1
STANDOFF,NYLON, SNAP-ON, 0.250"
MP2
STANDOFF,NYLON, SNAP-ON, 0.250"
MP3
STANDOFF,NYLON, SNAP-ON, 0.250"
MP4
STANDOFF,NYLON, SNAP-ON, 0.250"
LB1
LABEL
PCB1 PCB, DC2807A
STNCL1
REV0x
TOOL, STENCIL, 700-DC2807A
REV0x
CUSTOMER NOTICE
NOTE: UNLESS OTHERWISE SPECIFIED
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
3
ANALOG
DEVICES
AHEAD OF WHAT'S POSSIBLE
2
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
A
www.analog.com
TM
TITLE: DEMO CIRCUIT SCHEMATIC,
LIDAR RECEIVER
PCA BOM: 700-DC2807A_REV03
PCA ASS'Y: 705-DC2807A_REV03
DC2807A
DATE: 04/09/2018
SIZE: N/A
SCALE = NONE
SKU NO.
1. ALL RESISTORS ARE IN OHMS, 0402
ALL CAPACITORS ARE IN MICROFARADS, 0402
5
APPROVALS
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A PCB DES. AK
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
APP ENG. NOE Q.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
IC NO.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
LTC6560
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
A
SCHEMATIC NO. AND REVISION:
710-DC2807A_REV03
SHEET
1
OF
1
1
Rev. B
18
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LTC6560
APPLICATIONS INFORMATION
Evaluation board DC2803A allows for optical evaluation using a laser source. An onboard APD converts an
optical pulse into a current pulse that is converted to an
output voltage by the LTC6560. Use of the DC2803 will
more closely resemble LIDAR and any other optically
driven applications.
DC2803A Front Side
DC2803A Back Side
Figure 17. DC2803A Single Channel Demonstration Circuit for Optical Evaluation
5
4
3
VCC0
JP1
VCC0 EXT
E2
C2
1000pF
25V
0402
C1
1uF
25V
0805
D
GND
2
1
VCC
XJP1
EXT VCC
VCC0_SEL
E3
C3
1000pF
25V
0402
TMP
VCC
C4
1uF
25V
0805
E1
VCC
GND
E5
E6
E4
1
2
3
GND
U5
VOUT
GND
+VS
NC
SHUTDOWN
VCC
5
R1
4
0
D
0402
TMP36GRTZ
R15 OPT
1206
J1 GND
C8
3
4
6
C9
4
4
U1 LTC6560-UD
6
8
IN
GND
NC
VREF
OUT
NC
OUTTERM
NC
9
NC
C13
0.1uF
0603
7
NC
5
C
1000pF
25V 0402
C17
OPT
0805
AD230-9-6PIN-SMD
0.1uF
25V 0603
5
1
5
2
6
2
VCC0
1
0_MUX
3
VCC0
NC
17
R6
16
15
OPT
C11 0.1uF
1
R10 47.5
OUT
J2
14
13
1
R11 OPT
C14 OPT
OUTTERM
J3
NO STUFF
R13 OPT
12
2
R16
OPT
3
1
C
49.9
1206
NC
C7
0.047uF
500V
1206
U4
VCC1
C6
0.047uF
500V
1206
11
1206
R4
NC
10k
NC
1206
C5
1000pF
630V
1206
C18
1000pF
630V
1206
R3
10
-HV
10k
7
R2
2
7
1
B
B
1
VCC
C15 1000pF
25V 0402
C16 0.1uF
25V 0603
R17
OPT
VCC
JP2
DIS
O_MUX
J4
R18
1k
NO STUFF
O_MUX
EN
PCA ADDITIONAL PARTS
A
MP1
STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)
MP2
STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)
MP3
STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)
MP4
STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)
LB1
PCB1
STNCL1
LABEL
PCB, DC2803A
CUSTOMER NOTICE
REV0x
TOOL, STENCIL, 700-DC2803A
REV0x
NOTE: UNLESS OTHERWISE SPECIFIED
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
3
ANALOG
DEVICES
AHEAD OF WHAT'S POSSIBLE
2
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
A
www.analog.com
TM
TITLE: DEMO CIRCUIT SCHEMATIC,
LTC6560 OPTICAL SINGLE CHANNEL RECEIVER
PCA BOM: 700-DC2803A_REV05
PCA ASS'Y: 705-DC2803A_REV03
DC2803A
DATE: 09/26/2018
SIZE: N/A
SCALE = NONE
SKU NO.
1. ALL RESISTORS ARE IN OHMS, 0402
ALL CAPACITORS ARE IN MICROFARADS, 0402
5
APPROVALS
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A PCB DES. AK
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
APP ENG. NOE Q.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
IC NO.
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
LTC6560
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
SCHEMATIC NO. AND REVISION:
710-DC2803A_REV05
SHEET
1
OF
1
1
Rev. B
For more information www.analog.com
19
LTC6560
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1700 Rev A)
Exposed Pad Variation AA
0.70 ±0.05
3.50 ±0.05
1.65 ±0.05
2.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ±0.05
15
PIN 1
TOP MARK
(NOTE 6)
16
0.40 ±0.10
1
1.65 ±0.10
(4-SIDES)
2
(UD16 VAR A) QFN 1207 REV A
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-4)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
Rev. B
20
For more information www.analog.com
LTC6560
REVISION HISTORY
REV
DATE
DESCRIPTION
A
02/19
Added H-Grade version, updated graphics, app notes
PAGE NUMBER
All Pages
B
11/19
Added W-Grade (Automotive) version
All Pages
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
21
LTC6560
TYPICAL APPLICATION
Typical Application with Multiplexed Output
MULTIPLE LTC6560’s
VCCI
OUT(2)
VCCO
LTC6560
OUT
OUTPUT
STAGE
+
IN
–
VREF
47.5Ω WIRE-OR
MUX
TIA
50Ω
GAIN
–150V
TIME-OF-FLIGHT
DETECTOR
47.5Ω
OUTTERM
O_MUX(2)
GND
O_MUX
6561 TA02
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COMMENTS
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Slew Rate: 6800 V/μs
AD9694
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22
11/19
www.analog.com
For more information www.analog.com
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