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A1324

A1324

  • 厂商:

    ALLEGRO(埃戈罗)

  • 封装:

  • 描述:

    A1324 - Low Noise, Linear Hall Effect Sensor ICs with Analog Output - Allegro MicroSystems

  • 数据手册
  • 价格&库存
A1324 数据手册
A1324, A1325, and A1326 Low Noise, Linear Hall Effect Sensor ICs with Analog Output Features and Benefits • Temperature-stable quiescent output voltage and sensitivity • Output voltage proportional to magnetic flux density • Low-noise output increases accuracy • Precise recoverability after temperature cycling • Ratiometric rail-to-rail output • Wide ambient temperature range: –40°C to 150°C • Immune to mechanical stress • Solid-state reliability • Enhanced EMC performance for stringent automotive applications Description New applications for linear output Hall-effect devices, such as displacement, angular position, and current measurement, require high accuracy in conjunction with small package size. The Allegro® A1324, A1325, and A1326 linear Hall-effect sensor ICs are designed specifically to achieve both goals. This temperature-stable device is available in a miniature surface mount package (SOT23W) and an ultra-mini through-hole single in-line package. These ratiometric Hall effect sensor ICs provide a voltage output that is proportional to the applied magnetic field. They feature a quiescent voltage output of 50% of the supply voltage. The A1324/25/26 feature factory programmed sensitivities of 5.0 mV/G, 3.125 mV/G, and 2.5 mV/G, respectively. The features of these linear devices make them ideal for use in automotive and industrial applications requiring high accuracy, and are guaranteed through an extended temperature range, –40°C to 150°C. Each BiCMOS monolithic circuit integrates a Hall element, temperature-compensating circuitry to reduce the intrinsic sensitivity drift of the Hall element, a small-signal high-gain amplifier, a clamped low-impedance output stage, and a proprietary dynamic offset cancellation technique. Packages 3-pin ultramini SIP 1.5 mm × 4 mm × 3 mm (suffix UA) 3-pin SOT23-W 2 mm × 3 mm × 1 mm (suffix LH) Approximate footprint These devices are available in a 3-pin ultra-mini SIP package (UA), and a 3-pin surface mount SOT-23 style package (LH). Both are lead (Pb) free, with 100% matte tin leadframe plating. Functional Block Diagram V+ To All Subcircuits VCC Dynamic Offset Cancellation Tuned Filter VOUT Sensitivity and Sensitivity TC Offset Trim Control GND A1324-DS, Rev. 1 A1324, A1325, and A1326 Linear Hall Effect Sensor ICs with Analog Output Selection Guide Part Number A1324LLHLX-T A1324LUA-T2 A1325LLHLX-T A1325LUA-T2 A1326LLHLX-T A1326LUA-T2 1Contact Allegro® 2Contact Packing1 10 000 pieces per reel 500 pieces per bag 10 000 pieces per reel 500 pieces per bag 10 000 pieces per reel 500 pieces per bag Package 3-pin SOT-23W surface mount 3-pin ultramini SIP through hole mount 3-pin SOT-23W surface mount 3-pin ultramini SIP through hole mount 3-pin SOT-23W surface mount 3-pin ultramini SIP through hole mount Sensitivity (Typ.) (mV/G) 5.000 3.125 2.500 for additional packing options. factory for availability. Absolute Maximum Ratings Characteristic Forward Supply Voltage Reverse Supply Voltage Forward Output Voltage Reverse Output Voltage Output Source Current Output Sink Current Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VCC VRCC VOUT VROUT IOUT(SOURCE) IOUT(SINK) TA TJ(max) Tstg VOUT to GND VCC to VOUT L temperature range Notes Rating 8 –0.1 15 –0.1 2 10 –40 to 150 165 –65 to 170 Unit V V V V mA mA ºC ºC ºC Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Package LH, on 4-layer PCB with copper limited to solder pads Package Thermal Resistance RθJA Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side, connected by thermal vias Package UA, on 1-layer PCB with copper limited to solder pads *Additional thermal information available on the Allegro website Value 228 110 165 Unit ºC/W ºC/W ºC/W Pin-out Diagrams 3 Terminal List Table Name VCC VOUT Number LH 1 2 3 UA 1 3 2 Function Input power supply; tie to GND with bypass capacitor Output signal; also used for programming Ground 1 LH Package 2 1 2 3 GND UA Package Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A1324, A1325, and A1326 Linear Hall Effect Sensor ICs with Analog Output OPERATING CHARACTERISTICS Valid throughout TA range, CBYPASS = 0.1 μF, VCC = 5 V; unless otherwise noted Characteristics Electrical Characteristics Supply Voltage Supply Current Power-On Time2 Supply Zener Clamp Voltage Internal Bandwidth Chopping Frequency3 Output Characteristics Quiescent Voltage Output Output Referred Noise VOUT(Q) VN B = 0 G, TA = 25°C A1324, TA = 25°C, CBYPASS = 0.1 μF A1325, TA = 25°C, CBYPASS = 0.1 μF A1326, TA = 25°C, CBYPASS = 0.1 μF Input Referred RMS Noise Density DC Output Resistance Output Load Resistance Output Load Capacitance Output Saturation Voltage Magnetic Characteristics A1324, TA = 25°C Sensitivity Sens A1325, TA = 25°C A1326, TA = 25°C Sensitivity Temperature Coefficient TCSens LH package; programmed at TA = 150°C, calculated relative to Sens at 25°C UA package; programmed at TA = 150°C, calculated relative to Sens at 25°C LH package; from hot to room temperature UA package; from hot to room temperature LH package; from cold to room temperature UA package; from cold to room temperature 4.750 2.969 2.375 – – 5.000 3.125 2.500 0 0.03 5.250 3.281 2.625 – – mV/G mV/G mV/G %/°C %/°C VNRMS ROUT RL CL VOUT to VCC VOUT to GND VOUT to GND TA = 25°C, CBYPASS = open, no load on VOUT, f |B(– )| . Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A1324, A1325, and A1326 Linear Hall Effect Sensor ICs with Analog Output Typical Characteristics (30 pieces, 3 fabrication lots) Average Supply Current versus Ambient Temperature VCC = 5 V 12 11 10 ICCav (mA) 9 8 7 6 5 4 – 40 25 TA (°C) 150 Average Postive Linearity versus Ambient Temperature VCC = 5 V 105 104 103 Lin+av (%) 101 100 99 98 97 96 95 – 40 25 TA (°C) 150 Lin–av (%) 102 105 104 103 102 101 100 99 98 97 96 95 Average Negative Linearity versus Ambient Temperature VCC = 5 V – 40 25 TA (°C) 150 Average Quiescent Voltage Output Ratiometry versus Ambient Temperature 101.0 100.8 100.6 RatVOUTQ(av) (%) 100.4 100.2 100.0 99.8 99.6 99.4 99.2 99.0 – 40 25 TA (°C) 150 VCC 5.5 to 5.0 V 4.5 to 5.0 V RatSens(av) (%) 102.0 101.5 101.0 100.5 100.0 99.5 99.0 98.5 98.0 Average Sensitivity Ratiometry versus Ambient Temperature VCC 5.5 to 5.0 V 4.5 to 5.0 V – 40 25 TA (°C) 150 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A1324, A1325, and A1326 Linear Hall Effect Sensor ICs with Analog Output Typical Characteristics, continued (30 pieces, 3 fabrication lots) Average Absolute Quiescent Voltage Output versus Ambient Temperature VCC = 5 V 2.565 2.545 VOUT(Q)av (V) 2.525 2.505 2.485 2.465 2.445 2.425 – 40 25 TA (°C) 150 A1324 A1325 VOUT(Q) (V) A1326 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 Quiescent Voltage Output versus Supply Voltage TA = 25°C A1324 A1325 A1326 4.5 5 VCC (V) 5.5 Average Absolute Sensitivity versus Ambient Temperature VCC = 5 V 6.0 5.5 Sensav (mV/G) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 – 40 A1326 A1325 A1324 Sensav (mV/G) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 25 TA (°C) 150 1.0 Average Sensitivity versus Supply Voltage TA = 25°C A1324 A1325 A1326 4.5 5 VCC (V) 5.5 Average Quiescent Voltage Output Drift versus Ambient Temperature ∆VOUT(Q)av values relative to 25°C, VCC = 5 V 10 8 6 ∆VOUT(Q)av (G) ∆Sensav (%) 4 2 0 -2 -4 -6 -8 -10 – 40 25 TA (°C) 150 10 8 6 4 2 0 -2 -4 -6 -8 -10 Average Sensitivity Drift versus Ambient Temperature ∆Sensav values relative to 25°C, VCC = 5 V – 40 25 TA (°C) 150 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A1324, A1325, and A1326 Linear Hall Effect Sensor ICs with Analog Output V+ 1[1] VCC VOUT 2[3] VOUT A132x CBYPASS 0.1 μF GND 3[2] Pin numbers in brackets refer to the UA package Typical Application Circuit Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. Allegro employs a patented technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at baseband, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. In addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the Hall IC while completely removing the modulated residue resulting from the chopper operation. The chopper stabilization technique uses a high frequency sampling clock. For demodulation process, a sample-and-hold technique is used. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with highdensity logic integration and sample-and-hold circuits. Regulator Clock/Logic Hall Element Amp Anti-Aliasing LP Filter Tuned Filter Concept of Chopper Stabilization Technique Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A1324, A1325, and A1326 Linear Hall Effect Sensor ICs with Analog Output Package LH, 3-Pin SOT23W +0.12 2.98 –0.08 1.49 D 3 A +4° 4° –0° +0.020 0.180–0.053 0.96 D +0.10 2.90 –0.20 D +0.19 1.91 –0.06 0.25 MIN 1.00 1 2 0.55 REF 0.25 BSC Seating Plane Gauge Plane 8X 10° REF Branded Face 2.40 0.70 0.95 B PCB Layout Reference View 1.00 ±0.13 NNN +0.10 0.05 –0.05 0.95 BSC 0.40 ±0.10 1 C Standard Branding Reference View N = Last three digits of device part number For Reference Only; not for tooling use (reference DWG-2840) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A B Active Area Depth, 0.28 mm REF Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Branding scale and appearance at supplier discretion Hall element, not to scale C D Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A1324, A1325, and A1326 Linear Hall Effect Sensor ICs with Analog Output Package UA, 3-Pin SIP +0.08 4.09 –0.05 45° B C E 2.05 NOM 10° E 1.52 ±0.05 Mold Ejector Pin Indent Branded Face 0.79 REF 45° NNN 1.44 NOM +0.08 3.02 –0.05 E 1.02 MAX A 1 D Standard Branding Reference View 1 2 3 = Supplier emblem N = Last three digits of device part number 14.99 ±0.25 +0.03 0.41 –0.06 For Reference Only; not for tooling use (reference DWG-9065) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusio Exact case and lead configuration at supplier discretion within limits s +0.05 0.43 –0.07 A B C Dambar removal protrusion (6X) Gate and tie bar burr area Active Area Depth, 0.50 mm REF Branding scale and appearance at supplier discretion Hall element (not to scale) D E Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A1324, A1325, and A1326 Linear Hall Effect Sensor ICs with Analog Output Revision History Revision Rev. 1 Revision Date October 11, 2011 Description of Revision Update Sensitivity specifications Copyright ©2010-2011, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12
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