AS4C64M16D1A-6TINTR

AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Revision History 1Gb SDRAM-AS4C64M16D1A - 66pin TSOP II PACKAGE Revision Rev 1.0 Details Datasheet Date Oct 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Features Overview • Fast clock rate: 166MHz The 1Gb DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 1024 Mbits. It is internally configured as a quad 16M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK . Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The device provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, 1Gb DDR features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth; result in a device particularly well suited to high performance main memory and graphics applications. • Differential Clock CK & CK • Bi-directional DQS • DLL enable/disable by EMRS • Fully synchronous operation • Internal pipeline architecture • Four internal banks, 16M x 16-bit for each bank • Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved • Individual byte write mask control • DM Write Latency = 0 • Auto Refresh and Self Refresh • 8192 refresh cycles / 64ms • Precharge & active power down • Power supplies: VDD & VDDQ = 2.5V ± 0.2V • Industrial Operating Temperature: TA = -40~85°C • Interface: SSTL_2 I/O Interface • Package: 66 Pin TSOP II, 0.65mm pin pitch - Pb and Halogen free Table 1. Ordering Information Max Clock (MHz) Org Temperature AS4C64M16D1A-6TCN 64 x 16 Commercial 0°C to 85°C 166MHz 66 Pin TSOPII AS4C64M16D1A-6TIN 64 x 16 Industrial 166MHz 66 Pin TSOPII Product part No Confidential -40°C to 85°C - 2/62 - Package Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 1. Pin Assignment (Top View) VDD 1 66 VSS DQ0 2 65 DQ15 VDDQ 3 64 VSSQ DQ1 4 63 DQ14 DQ2 5 62 DQ13 VSSQ 6 61 VDDQ DQ3 7 60 DQ12 DQ4 8 59 DQ11 9 58 VSSQ DQ5 10 57 DQ10 VDDQ DQ6 11 56 DQ9 VSSQ 12 55 VDDQ DQ7 13 54 DQ8 NC 14 53 NC VDDQ 15 52 VSSQ LDQS 16 51 UDQS A13 17 50 NC VDD 18 49 VREF NC 19 48 VSS LDM 20 47 UDM WE 21 46 CK CAS 22 45 CK RAS 23 44 CKE CS 24 43 NC NC 25 42 A12 BA0 26 41 A11 BA1 27 40 A9 A10/AP 28 39 A8 A0 29 38 A7 A1 30 37 A6 A2 31 36 A5 A3 32 35 A4 VDD 33 34 VSS Confidential - 3/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 2. Block Diagram CK CK DLL CLOCK BUFFER COMMAND DECODER COLUMN COUNTER A10/AP A0-A9 A11-A13 BA0 BA1 CONTROL SIGNAL GENERATOR MODE REGISTER 16M x 16 CELL ARRAY (BANK #0) Column Decoder Row Decoder CS RAS CAS WE Row Decoder CKE 16M x 16 CELL ARRAY (BANK #1) Column Decoder Row Decoder ADDRESS BUFFER REFRESH COUNTER DATA STROBE BUFFER LDQS UDQS DQ0 16M x 16 CELL ARRAY (BANK #2) Column Decoder DQ Buffer Row Decoder ~ DQ15 LDM UDM Confidential - 4/62 - 16M x 16 CELL ARRAY (BANK #3) Column Decoder Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN  Pin Descriptions Table 2. Pin Details Symbol Type Description CK, CK Input Differential Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK . Input and output data is referenced to the crossing of CK and CK (both directions of the crossing) CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. BA0, BA1 Input Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. A0-A13 Input Address Inputs: A0-A13 are sampled during the BankActivate command (row address A0A13) and Read/Write command (column address A0-A9 with A10 defining Auto Precharge). CS Input Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. RAS Input Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and WE signals and is latched at the positive edges of CK. When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE signal. When the WE is asserted "HIGH," the BankActivate command is selected and the bank designated by BA is turned on to the active state. When the WE is asserted "LOW," the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation. CAS Input Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS and WE signals and is latched at the positive edges of CK. When RAS is held "HIGH" and CS is asserted "LOW," the column access is started by asserting CAS "LOW." Then, the Read or Write command is selected by asserting WE "HIGH" or “LOW”. WE Input Write Enable: The WE signal defines the operation commands in conjunction with the RAS and CAS signals and is latched at the positive edges of CK. The WE input is used to select the BankActivate or Precharge command and Read or Write command. LDQS, Input / UDQS Output Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. LDM, Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. DQ0 - DQ15 Input / Output Data I/O: The DQ0-DQ15 input and output data are synchronized with positive and negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes. VDD Supply Power Supply: 2.5V ± 0.2V . VSS Supply Ground VDDQ Supply DQ Power: 2.5V ± 0.2V . Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VREF Supply Reference Voltage for Inputs: +0.5*VDDQ NC - UDM Confidential No Connect: These pins should be left unconnected. - 5/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Operation Mode Table 3 shows the truth table for the operation commands. Table 3. Truth Table (Note (1), (2)) Command State CKEn-1 CKEn DM BA0,1 A10 A0-9, 11-13 CS RAS CAS WE Idle(3) H X X V Row address L L H H BankPrecharge Any H X X V L X L L H L PrechargeAll Any H X X X H X L L H L Write Active(3) H X X V L H L L Write and AutoPrecharge H X X V H Column address (A0 ~ A9) L Active(3) L H L L Read Active(3) H X X V L L H L H Read and Autoprecharge Active(3) H X X V H Column address (A0 ~ A9) L H L H (Extended) Mode Register Set Idle H X X L L L L No-Operation Any H X X X X X L H H H Active(4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H SelfRefresh Exit Idle L H X X X X H X X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V H X X X L H H H X X X X Data Input Mask Enable(5) Active H X H X X X X Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BA signal. 4. Device state is 2, 4, and 8 burst operation. 5. LDM and UDM can be enabled respectively. X X X BankActivate Burst Stop OP code (SelfRefresh) Precharge Power Down Mode Entry Precharge Power Down Mode Exit Active Power Down Mode Entry Active Power Down Mode Exit Data Input Mask Disable Confidential Idle Any H L L H X X X X X X X X (PowerDown) Active Any H L L H X X X X X X X X (PowerDown) Active H X - 6/62 - L X X X Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Mode Register Set (MRS) The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The default value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by asserting Low on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A13 and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Mode Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0 should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific codes for various burst lengths, burst types and CAS latencies. Table 4. Mode Register Bitmap BA1 BA0 A13 A12 A11 A10 0 0 A8 0 1 X A9 RFU must be set to “0” A7 Test Mode 0 Normal mode 0 DLL Reset 1 Test mode BA0 Mode 0 MRS 1 EMRS A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A8 A7 A6 T.M. A4 A3 CAS Latency BT A4 CAS Latency Reserved 0 Reserved 1 2 0 1 3 0 Reserved 1 Reserved 0 2.5 1 Reserved A5 A3 Burst Type 0 Sequential 1 Interleave A2 0 0 0 0 1 1 1 1 A2 A1 A0 Burst Length A1 0 0 1 1 0 0 1 1 Address Field Mode Register A0 Burst Length 0 Reserved 1 2 0 4 1 8 0 Reserved 1 Reserved 0 Reserved 1 Reserved • Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8. Table 5. Burst Length A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Confidential - 7/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN • Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2, 4 and 8. Table 6. Addressing Mode A3 Addressing Mode 0 Sequential 1 Interleave • Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 7. Burst Address ordering Burst Length 2 4 8 A2 X X X X X X 0 0 0 0 1 1 1 1 Start Address A1 X X 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sequential Interleave 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 • CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) ≤ CAS Latency X tCK Table 8. CAS Latency A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 clocks 1 1 1 Reserved • Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. Table 9. Test Mode • A8 A7 Test Mode 0 0 Normal mode 1 0 DLL Reset ( BA0, BA1) Confidential - 8/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Table 10. MRS/EMRS BA1 BA0 A13 ~ A0 RFU 0 MRS Cycle RFU 1 Extended Functions (EMRS) Extended Mode Register Set (EMRS) The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The Extened Mode Register is written by asserting Low on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE should be High). The state of A0 ~ A13, BA0 and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. A1 is used for setting driver strength to normal, or weak. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes. Table 11. Extended Mode Register Bitmap BA1 BA0 A13 A12 A11 A10 0 A9 A8 A7 1 RFU must be set to “0” BA0 0 Mode MRS A6 0 A1 0 Drive Strength Full 1 EMRS 0 1 Weak 1 0 1 1 Confidential A6 A5 A4 A3 A2 A1 A0 Address Field DS1 RFU must be set to “0” DS0 DLL Extended Mode Register Comment A0 0 DLL Enable 1 Disable RFU Reserved For Future Matched impedance Output driver matches impedance - 9/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Table 12. Absolute Maximum Rating Symbol VI/O Item Voltage on I/O Pins Relative to Vss Values Unit - 0.5 ~ VDDQ + 0.5 V Voltage on VDD, VDDQ Supply Relative to Vss - 1 ~ 3.6 V VIN Voltage on Inputs Relative to Vss - 1 ~ 3.6 V TA Ambient Temperature -40 ~ +85 °C TSTG Storage Temperature - 55 ~ +150 °C 260 °C VDD, VDDQ TSOLDER PD Soldering Temperature Power Dissipation 1.3 W Short Circuit Output Current IOS 50 mA Note: Absolute maximum DC requirements contain stress ratings only. Functional operation at the absolute maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability. Table 13. Recommended D.C. Operating Conditions (VDD = 2.5V ± 0.2V, TA = -40 ~ 85 °C) Symbol Parameter Min. Max. Unit VDD Power Supply Voltage 2.3 2.7 V VDDQ Power Supply Voltage (for I/O Buffer) 2.3 2.7 V VREF Input Reference Voltage 0.49*VDDQ 0.51* VDDQ V VIH (DC) Input High Voltage (DC) VREF + 0.15 VDDQ + 0.3 V VIL (DC) Input Low Voltage (DC) -0.3 VREF – 0.15 V VREF - 0.04 VREF + 0.04 V VDDQ + 0.3 V VTT Termination Voltage VIN (DC) Input Voltage Level, CK and CK inputs -0.3 VID (DC) Input Different Voltage, CK and CK inputs 0.36 VDDQ + 0.6 V Input leakage current -2 2 µA IOZ Output leakage current -5 5 µA IOH Output High Current (VOH = 1.95V) -16.2 - mA 16.2 - mA II IOL Output Low Current (VOL = 0.35V) Note: All voltages are referenced to VSS. Table 14. Capacitance (VDD = 2.5V, f = 1MHz, TA = 25 °C) Symbol Parameter Min. Max. Delta Unit CIN1 Input Capacitance (CK, CK ) 3.5 4.5 0.5 pF CIN2 Input Capacitance (All other input-only pins) 3.5 4.5 0.5 pF CI/O DQ, DQS, DM Input/Output Capacitance 4 5 0.5 Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested pF Confidential - 10/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Table 15. D.C. Characteristics (VDD = 2.5V ± 0.2V, TA = -40 ~ 85 °C) Parameter & Test Condition OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT: One bank; BL=4; reads - Refer to the following page for detailed test conditions PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; tCK=tCK(min); CKE = LOW PRECHARGE FLOATING STANDBY CURRENT: CS = HIGH; all banks idle; CKE = HIGH; tCK =tCK(min); address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM PRECHARGE QUIET STANDBY CURRENT: CS =HIGH; all banks idle; CKE =HIGH; tCK=tCK(min) address and other control inputs stable at ≥ VIH(min) or ≤ VIL (max); VIN = VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power-down mode; CKE=LOW; tCK=tCK(min) ACTIVE STANDBY CURRENT : CS =HIGH;CKE=HIGH; one bank active ; tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle OPERATING CURRENT BURST READ : BL=2; READS; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); lout=0mA;50% of data changing on every transfer OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous Burst ;one bank active; address and control inputs changing once per clock cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50% of data changing on every transfer AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min) SELF REFRESH CURRENT: Self Refresh Mode ; CKE≦0.2V; tCK=tCK(min) BURST OPERATING CURRENT 4 bank operation: Four bank interleaving READs; BL=4;with Auto Precharge; tRC=tRC(min); tCK=tCK(min); Address and control inputs change only during Active, READ , or WRITE command Confidential -6 Max. Unit Note IDD0 160 mA IDD1 180 mA IDD2P 10 mA IDD2F 70 mA IDD2Q 70 mA IDD3P 40 mA IDD3N 130 mA IDD4R 260 mA IDD4W 260 mA IDD5 280 mA IDD6 12 mA IDD7 420 mA Symbol - 11/62 - Rev. 1.0 1 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Table 16. Electrical Characteristics and Recommended A.C.Operating Condition (VDD = 2.5V ± 0.2V, TA = -40 ~ 85 °C) Symbol -6 Parameter CL = 2 tCK Clock cycle time tCH tCL Clock high level width Min. Max. 7.5 12 6 12 0.45 0.55 ns ns ns tCK tCK tCLMIN or tCHMIN - ns 2 - 0.7 ns 3 -0.7 0.7 ns 3 CL = 2.5 CL = 3 Clock low level width Unit Note 5 12 0.45 0.55 tHP Clock half period tHZ Data-out-high impedance time from CK, tLZ Data-out-low impedance time from CK, tDQSCK DQS-out access time from CK, CK -0.6 0.6 ns tAC Output access time from CK, CK -0.7 0.7 ns tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tWPST tDQSH tDQSL tIS tIH tDS tDH tQH tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tMRD tREFI tXSRD tXSNR tDAL tDIPW tIPW tQHS tDSS tDSH DQS-DQ Skew - 0.4 Read preamble 0.9 1.1 tRAP Active to Autoprecharge Delay Confidential CK CK tWR+tRP - DQ and DM input pulse width 1.75 - Control and Address input pulse width 2.2 - - 0.5 DQS falling edge to CK setup time 0.2 - DQS falling edge hold time from CK 0.2 - ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns tCK ns µs tCK ns ns ns ns ns tCK tCK tRCD or tRASmin - ns Read postamble 0.4 0.6 CK to valid DQS-in 0.72 1.25 DQS-in setup time 0 - 0.25 - DQS write postamble 0.4 0.6 DQS in high level pulse width 0.35 - DQS in low level pulse width 0.35 - Address and Control input setup time 0.7 - Address and Control input hold time 0.7 - DQ & DM setup time to DQS 0.4 - DQS Write preamble DQ & DM hold time to DQS 0.4 - tHP - tQHS - Row cycle time 55 - Refresh row cycle time 70 - Row active time 40 70K Active to Read or Write delay 15 - Row precharge time 15 - Row active to Row active delay 10 - Write recovery time 15 - Internal Write to Read Command Delay 2 - Mode register set cycle time 10 - - 7.8 DQ/DQS output hold time from DQS Average Periodic Refresh interval Self refresh exit to read command delay 200 - Self refresh exit to non-read command delay 75 - Auto Precharge write recovery + precharge time Data Hold Skew Factor - 12/62 - 4 5 6 6 7 Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Table 17. Recommended A.C. Operating Conditions (VDD = 2.5V ± 0.2V, TA = -40 ~ 85 °C) Symbol Min. Max. Unit VIH (AC) Input High Voltage (AC) Parameter VREF + 0.31 - V VIL (AC) Input Low Voltage (AC) - VREF – 0.31 V 0.7 VDDQ + 0.6 V 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V VID (AC) Input Different Voltage, CK and CK inputs VIX (AC) Input Crossing Point Voltage, CK and CK inputs Note: 1) Enables on-chip refresh and address counters. 2) Min(tCL, tCH) refers to the smaller of the actual clock low time and actual clock high time as provided to the device. 3) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ). 4) The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or before this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 5) The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 6) For command/address and CK & CK slew rate ≧ 1.0V/ns. 7) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 8) Power-up sequence is described in Note 10 9) A.C. Test Conditions Table 17. SSTL _2 Interface Reference Level of Output Signals (VREF) 0.5 * VDDQ Output Load Reference to the Test Load Input Signal Levels VREF+0.31 V / VREF-0.31 V Input Signals Slew Rate 1 V/ns Reference Level of Input Signals 0.5 * VDDQ Figure 3. SSTL_2 A.C. Test Load 0.5 * VDDQ 50Ω DQ, DQS Z0=50Ω 30pF 10) Power up Sequence Power up must be performed in the following sequence. Confidential - 13/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN 1) 2) 3) 4) 5) 6) 7) 8) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held "NOP" state and maintain CKE “LOW”. Start clock and maintain stable condition for minimum 200µs. Issue a “NOP” command and keep CKE “HIGH” Issue a “Precharge All” command. Issue EMRS – enable DLL. Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL). Precharge all banks of the device. Issue two or more Auto Refresh commands. 9) Issue MRS – with A8 to low to initialize the mode register. Confidential - 14/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Timing Waveforms Figure 4. Activating a Specific Row in a Specific Bank CK CK CKE HIGH CS RAS CAS WE Address RA BA0,1 BA RA=Row Address BA=Bank Address Don’t Care Confidential - 15/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 5. tRCD and tRRD Definition CK CK COMMAND ACT Address Row Row Col BA0,BA1 Bank A Bank B Bank B NOP NOP ACT tRRD NOP NOP NOP RD/WR tRCD Don’t Care Figure 6. READ Command CK CK CKE HIGH CS RAS CAS WE A0 - A9 CA EN AP A10 DIS AP BA0,1 BA CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge Don’t Care Confidential - 16/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 7. Read Burst Required CAS Latencies (CL=2) CK CK COMMAND READ ADDRESS Bank A, Col n NOP NOP NOP NOP NOP CL=2 DQS DO n DQ DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care Read Burst Required CAS Latencies (CL=2.5) CK CK COMMAND READ ADDRESS Bank A, Col n NOP NOP NOP NOP NOP CL=2.5 DQS DO n DQ DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care Confidential - 17/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Read Burst Required CAS Latencies (CL=3) CK CK COMMAND READ ADDRESS Bank A, Col n NOP NOP NOP NOP NOP CL=3 DQS DO n DQ DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care Confidential - 18/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 8. Consecutive Read Bursts Required CAS Latencies (CL=2) CK CK COMMAND ADDRESS READ NOP READ NOP NOP NOP Bank, Col o Bank, Col n CL=2 DQS DQ DO n DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device Don’t Care Confidential - 19/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Consecutive Read Bursts Required CAS Latencies (CL=2.5) CK CK COMMAND ADDRESS READ NOP READ NOP NOP NOP Bank, Col o Bank, Col n CL=2.5 DQS DO n DQ DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device Don’t Care Confidential - 20/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Consecutive Read Bursts Required CAS Latencies (CL=3) CK CK COMMAND ADDRESS READ NOP Bank, Col n READ NOP NOP NOP Bank, Col o CL=3 DQS DO n DQ DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands shown must be to the same device Don’t Care Confidential - 21/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 9. Non-Consecutive Read Bursts Required CAS Latencies (CL=2) CK CK COMMAND ADDRESS READ NOP NOP READ NOP NOP Bank, Col o Bank, Col n CL=2 DQS DO n DQ DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) Don’t Care Non-Consecutive Read Bursts Required CAS Latencies (CL=2.5) CK CK COMMAND ADDRESS READ NOP NOP READ NOP NOP NOP Bank, Col o Bank, Col n CL=2.5 DQS DQ DO n DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) Don’t Care Confidential - 22/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Non-Consecutive Read Bursts Required CAS Latencies (CL=3) CK CK COMMAND ADDRESS READ NOP NOP READ NOP NOP NOP Bank, Col o Bank, Col n CL=3 DQS DO n DQ DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) Don’t Care Confidential - 23/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 10. Random Read Accesses Required CAS Latencies (CL=2) CK CK COMMAND ADDRESS READ READ READ READ Bank, Col n Bank, Col o Bank, Col p Bank, Col q NOP NOP CL=2 DQS DO n' DO n DQ DO o' DO o DO p' DO p DO q DO n, etc. =Data Out from column n, etc. n', etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks Don’t Care Random Read Accesses Required CAS Latencies (CL=2.5) CK CK COMMAND ADDRESS READ READ READ READ Bank, Col n Bank, Col o Bank, Col p Bank, Col q NOP NOP CL=2.5 DQS DO n DQ DO n' DO o DO o' DO p DO p' DO n, etc. =Data Out from column n, etc. n', etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks Don’t Care Confidential - 24/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Random Read Accesses Required CAS Latencies (CL=3) CK CK COMMAND ADDRESS READ READ READ READ Bank, Col n Bank, Col o Bank, Col p Bank, Col q NOP NOP CL=3 DQS DO n DQ DO n' DO o DO o' DO p DO n, etc. =Data Out from column n, etc. n', etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks Don’t Care Confidential - 25/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 11. Terminating a Read Burst Required CAS Latencies (CL=2) CK CK COMMAND READ ADDRESS Bank A, Col n NOP BST NOP NOP NOP CL=2 DQS DO n DQ DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care Terminating a Read Burst Required CAS Latencies (CL=2.5) CK CK COMMAND READ ADDRESS Bank A, Col n NOP BST NOP NOP NOP CL=2.5 DQS DO n DQ DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care Confidential - 26/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Terminating a Read Burst Required CAS Latencies (CL=3) CK CK COMMAND READ ADDRESS Bank A, Col n NOP BST NOP NOP NOP CL=3 DQS DO n DQ DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care Confidential - 27/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 12. Read to Write Required CAS Latencies (CL=2) CK CK COMMAND ADDRESS READ BST NOP NOP WRITE NOP Bank, Col o Bank, Col n tDQSS min CL=2 DQS DQ DO n DI o DM DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order Don’t Care Confidential - 28/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Read to Write Required CAS Latencies (CL=2.5) CK CK COMMAND ADDRESS READ BST NOP NOP NOP WRITE Bank, Col o Bank, Col n CL=2.5 tDQSS min DQS DO n DQ DI o DM DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order Don’t Care Confidential - 29/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Read to Write Required CAS Latencies (CL=3) CK CK COMMAND ADDRESS READ BST NOP NOP NOP WRITE Bank, Col o Bank, Col n tDQSS min CL=3 DQS DO n DQ DI o DM DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order Don’t Care Confidential - 30/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 13. Read to Precharge Required CAS Latencies (CL=2) CK CK COMMAND READ NOP PRE NOP NOP ACT tRP ADDRESS Bank A, Col n Bank (a or all) Bank A, Row CL=2 DQS DQ DO n DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met Don’t Care Confidential - 31/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Read to Precharge Required CAS Latencies (CL=2.5) CK CK COMMAND READ NOP PRE NOP NOP ACT tRP ADDRESS Bank A, Col n Bank (a or all) Bank A, Row CL=2.5 DQS DO n DQ DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met Don’t Care Confidential - 32/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Read to Precharge Required CAS Latencies (CL=3) CK CK COMMAND READ NOP PRE NOP NOP ACT tRP ADDRESS Bank A, Col n Bank (a or all) Bank A, Row CL=3 DQS DO n DQ DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met Confidential - 33/62 - Don’t Care Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 14. Write Command CK CK CKE HIGH CS RAS CAS WE A0 - A9 CA EN AP A10 DIS AP BA0,1 BA CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge Don’t Care Confidential - 34/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 15. Write Max DQSS T0 T1 T2 T3 T4 T5 T6 T7 CK CK COMMAND WRITE ADDRESS Bank A, Col n NOP NOP NOP tDQSS max DQS DQ DI n DM DI n = Data In for column n 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled) Don’t Care Confidential - 35/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 16. Write Min DQSS T0 T1 T2 T3 T4 T5 T6 CK CK COMMAND ADDRESS NOP WRITE NOP NOP Bank A, Col n tDQSS min DQS DQ DI n DM DI n = Data In for column n 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled) Don’t Care Confidential - 36/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 17. Write Burst Nom, Min, and Max tDQSS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK COMMAND ADDRESS NOP WRITE NOP NOP NOP NOP Bank , Col n tDQSS (nom) DQS DI n DQ DM tDQSS (min) DQS DQ DI n DM tDQSS (max) DQS DQ DI n DM DI n = Data In for column n 3 subsequent elements of Data are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled) DM=UDM & LDM Don’t Care Confidential - 37/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 18. Write to Write Max tDQSS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK COMMAND ADDRESS WRITE NOP WRITE NOP NOP NOP Bank , Col o Bank , Col n tDQSS (max) DQS DQ DI n DI o DM DI n , etc. = Data In for column n,etc. 3 subsequent elements of Data In are applied in the programmed order following DI n 3 subsequent elements of Data In are applied in the programmed order following DI o Non-interrupted bursts of 4 are shown DM= UDM & LDM Don’t Care Confidential - 38/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 19. Write to Write Max tDQSS, Non Consecutive T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK COMMAND ADDRESS WRITE NOP NOP Bank Col n WRITE NOP NOP Bank Col o tDQSS (max) DQS DQ DI n DI o DM DI n, etc. = Data In for column n, etc. 3 subsequent elements of Data In are applied in the programmed order following DI n 3 subsequent elements of Data In are applied in the programmed order following DI o Non-interrupted bursts of 4 are shown DM= UDM & LDM Don’t Care Confidential - 39/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 20. Random Write Cycles Max tDQSS T0 T1 T2 T4 T3 T5 T6 T8 T7 T9 CK CK COMMAND ADDRESS WRITE WRITE WRITE WRITE WRITE Bank Col n Bank Col o Bank Col p Bank Col q Bank Col r tDQSS (max) DQS DQ DI n DI n' DI o DI o' DI p DI p' DI q DI q' DM DI n, etc. = Data In for column n, etc. n', etc. = the next Data In following DI n, etc. according to the programmed burst order Programmed Burst Length 2, 4, or 8 in cases shown If burst of 4 or 8, the burst would be truncated Each WRITE command may be to any bank and may be to the same or different devices DM= UDM & LDM Don’t Care Confidential - 40/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 21. Write to Read Max tDQSS Non Interrupting T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK CK COMMAND WRITE NOP NOP NOP READ NOP NOP tWTR ADDRESS Bank Col o Bank Col n CL=3 tDQSS (max) DQS DI n DQ DM DI n, etc. = Data In for column n, etc. 1 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 2 is shown tWTR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are to the same devices but not necessarily to the same bank DM= UDM & LDM Don’t Care Confidential - 41/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 22. Write to Read Max tDQSS Interrupting T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK CK COMMAND WRITE NOP NOP NOP READ NOP tWTR ADDRESS Bank Col o Bank Col n CL=3 tDQSS (max) DQS DI n DQ DM DI n, etc. = Data In for column n, etc. 1 subsequent elements of Data In are applied in the programmed order following DI n An interrupted burst of 8 is shown, 2 data elements are written tWTR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are to the same devices but not necessarily to the same bank DM= UDM & LDM Don’t Care Confidential - 42/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 23. Write to Read Max tDQSS, ODD Number of Data, Interrupting T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK CK COMMAND WRITE NOP NOP NOP READ NOP tWTR ADDRESS Bank Col o Bank Col n CL=3 tDQSS (max) DQS DI n DQ DM DI n = Data In for column n An interrupted burst of 8 is shown, 1 data elements are written tWTR is referenced from the first positive CK edge after the last Data In Pair (not the last desired Data In element) A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) The READ and WRITE commands are to the same devices but not necessarily to the same bank DM= LDM & UDM Don’t Care Confidential - 43/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 24. Write to Precharge Max tDQSS, NON- Interrupting T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK COMMAND WRITE NOP NOP NOP NOP PRE tWR ADDRESS Bank a, Col n Bank (a or al) tRP tDQSS (max) DQS DQ DI n DM DI n = Data In for column n 1 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 2 is shown tWR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) DM= UDM & LDM Don’t Care Confidential - 44/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 25. Write to Precharge Max tDQSS, Interrupting T0 T1 T2 T3 T4 T5 T6 T8 T7 T9 T10 T11 CK CK COMMAND WRITE ADDRESS Bank a, Col n NOP NOP NOP PRE NOP tWR Bank (a or all) tDQSS (max) tRP *2 DQS DI n DQ DM *1 *1 *1 *1 DI n = Data In for column n An interrupted burst of 4 or 8 is shown, 2 data elements are written tWR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes don't care at this point DM= UDM & LDM Don’t Care Confidential - 45/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 26. Write to Precharge Max tDQSS ODD Number of Data Interrupting T0 T1 T2 T3 T4 T5 T6 T8 T7 T9 T10 T11 CK CK COMMAND WRITE NOP NOP NOP NOP PRE tWR ADDRESS Bank a, Col n Bank (a or all) tDQSS (max) tRP *2 DQS DQ DI n DM *1 *1 *1 *1 DI n = Data In for column n An interrupted burst of 4 or 8 is shown, 1 data element is written tWR is referenced from the first positive CK edge after the last Data In Pair A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes don't care at this point DM= UDM & LDM Don’t Care Confidential - 46/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 27. Precharge Command CK CK CKE HIGH CS RAS CAS WE ADDRESS ALL BANKS A10 ONE BANK BA0,1 BA BA= Bank Address (if A10 is LOW, otherwise don't care) Don’t Care Confidential - 47/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 28. Power-Down T0 T1 T2 T3 T4 Tn Tn+3 Tn+4 Tn+5 Tn+6 Tn+1 Tn+2 CK CK tIS tIS CKE COMMAND NOP NOP VALID Exit power-down mode Enter power-down mode No column access in progress VALID Don’t Care Figure 29. Clock Frequency Change in Precharge T0 T1 T2 T4 Tx Tx+1 Ty Ty+1 Ty+2 Ty+3 Ty+4 Tz CK CK CMD CKE NOP NOP NOP Frequency Change Occurs here NOP NOP Valid tIS tRP Stable new clock Before power down exit Minmum 2 clocks Required before Changing frequency Confidential DLL RESET - 48/62 - 200 Clocks Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 30. Data input (Write) Timing tDQSH tDQSL DQS tDS DI n DQ tDH tDS DM tDH DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n Don’t Care Figure 31. Data Output (Read) Timing tCH tCL CK CK DQS DQ tDQSQ tDQSQ max tQH max tQH Burst Length = 4 in the case shown Confidential - 49/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 32. Initialize and Mode Register Sets VDD VDDQ tVDT>=0 VTT (system*) tCK tCH tCL VREF CK CK tIS tIH CKE LVCMOS LOW LEVEL tIS tIH NOP COMMAND PRE MRS EMRS PRE AR AR MRS ACT CODE RA CODE RA BA0=L BA1=L BA DM tIS tIH CODE ADDRESS ALL BANKS A10 tIS tIH CODE tIS tIH ALL BANKS CODE CODE tIS tIH tIS tIH BA0=H BA1=L BA0,BA1 BA0=L BA1=L High-Z DQS High-Z DQ T=200µs **tMRD **tMRD Extended mode Register set Power-up: VDD and CLK stable tRP tRFC tRFC **tMRD 200 cycles of CK** Load Mode Register, Reset DLL (with A8=H) Load Mode Register, (with A8=L) *=VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up. ** = tMRD is required before any command can be applied, and 200 cycles of CK are required before any executable command can be applied the two auto Refresh commands may be moved to follow the first MRS but precede the second PRECHARGE ALL command. Don’t Care Confidential - 50/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 33. Power Down Mode tCK tCH tCL CK CK tIS tIH tIS tIS CKE tIS tIH COMMAND VALID* NOP NOP VALID tIS tIH ADDRESS VALID VALID DQS DQ DM Enter power-down mode Exit power-down mode No column accesses are allowed to be in progress at the time Power-Down is entered *=If this command is a PRECHARGE ALL (or if the device is already in the idle state) then the Power-Down mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active) then the Power-Down mode shown is active Power Down. Don’t Care Confidential - 51/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 34. Auto Refresh Mode tCK tCH tCL CK CK tIS tIH CKE VALID VALID tIS tIH COMMAND NOP PRE NOP NOP AR NOP AR NOP NOP ACT A0-A9 RA A11-A13 RA ALL BANKS RA A10 ONE BANKS tIS tIH BA0,BA1 BA *Bank(s) DQS DQ DM tRP tRFC tRFC * = Don't Care , if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks) PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other valid commands may be possible after tRFC DM, DQ and DQS signals are all Don't Care /High-Z for operations shown Don’t Care Confidential - 52/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 35. Self Refresh Mode tCK tCH Clock must be stable before Exiting Self Refresh mode tCL CK CK tIS tIH tIS tIS CKE tIS tIH COMMAND NOP NOP AR VALID tIS tIH VALID ADDRESS DQS DQ DM tRP* tXSNR/ tXSRD** Enter Self Refresh mode Exit Self Refresh mode * = Device must be in the All banks idle state prior to entering Self Refresh mode ** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is required before a READ command can be applied. Don’t Care Confidential - 53/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 36. Read without Auto Precharge tCK tCH tCL CK CK tIH tIS tIH CKE VALID VALID VALID NOP NOP NOP tIS tIH NOP COMMAND READ PRE NOP NOP NOP ACT tIS tIH Col n A0-A9 RA RA A11-A13 tIS tIH ALL BANKS RA A10 DIS AP ONE BANKS tIS tIH Bank X BA0,BA1 Bank X *Bank X CL=3 tRP DM Case 1: tAC/tDQSCK=min tDQSCK min tRPRE tRPST DQS tLZ min DO n DQ tLZ tAC min min Case 2: tAC/tDQSCK=max tDQSCK max tRPRE tRPST DQS tLZ max tHZ max DO n DQ tLZ max tAC max DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other commands may be valid at these times Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks Confidential - 54/62 - Don’t Care Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 37. Read with Auto Precharge tCK tCH tCL CK CK tIH tIS tIH CKE VALID VALID VALID NOP NOP NOP tIS tIH NOP COMMAND READ NOP NOP NOP NOP ACT tIS tIH Col n A0-A9 RA RA A11-A13 EN AP RA A10 tIS tIH tIS tIH Bank X BA0,BA1 Bank X CL=3 tRP DM Case 1: tAC/tDQSCK=min tDQSCK min tRPST tRPRE DQS tLZ min DO n DQ tLZ tAC min min Case 2: tAC/tDQSCK=max tDQSCK max tRPST tRPRE DQS tLZ max tHZ max DO n DQ tLZ max tAC max DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n EN AP = Enable Autoprecharge ACT = ACTIVE, RA = Row Address NOP commands are shown for ease of illustration; other commands may be valid at these times The READ command may not be issued until tRAP has been satisfied. If Fast Autoprecharge is supported, tRAP = tRCD, else the READ may not be issued prior to tRASmin - (BL*tCK/2) Don’t Care Confidential - 55/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 38. Bank Read Access tCK tCH tCL CK CK tIS tIH CKE tIS tIH NOP COMMAND ACT NOP NOP NOP READ NOP PRE NOP NOP ACT tIS tIH A0-A9 RA A11-A13 RA Col n RA tIS A10 RA tIH ALL BANKS RA RA DIS AP ONE BANKS Bank X *Bank X tIS tIH Bank X BA0,BA1 Bank X tRC tRAS tRCD tRP CL=3 DM Case 1: tAC/tDQSCK=min tDQSCK min tRPRE tRPST DQS tLZ DO n min DQ tLZ tAC tDQSCK min Case 2: tAC/tDQSCK=max min max tRPRE tRPST DQS tHZ tLZ max max DO n DQ tLZ DO n = Data Out from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DO n max tAC max DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting) Confidential - 56/62 - Don’t Care Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 39. Write without Auto Precharge tCK tCH tCL CK CK tIH tIS tIH CKE VALID tIS tIH NOP COMMAND WRITE NOP NOP NOP NOP PRE NOP NOP ACT tIS tIH RA Col n A0-A9 RA A11-A13 tIS tIH ALL BANKS RA A10 ONE BANKS DIS AP tIS tIH Bank X BA0,BA1 Case 1: tDQSS=min tDQSS BA *Bank X tDSH tDQSH tRP tDSH tWR tWPST DQS tDQSL tWPRES tWPRE DI n DQ DM tDSS Case 2: tDQSS=max tDQSS tDQSH tDSS tWPST DQS tWPRES tDQSL tWPRE DI n DQ DM DI n = Data In from column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks Confidential - 57/62 - Don’t Care Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 40. Write with Auto Precharge tCK tCH tCL CK CK tIS tIH CKE VALID VALID VALID NOP NOP NOP tIS tIH COMMAND NOP WRITE NOP NOP NOP NOP ACT tIS tIH A0-A9 RA Col n RA A11-A13 DIS AP RA A10 tIS tIH BA0,BA1 Bank X BA tDAL Case 1: tDQSS=min tDQSS tDSH tDQSH tDSH tWPST DQS tWPRES tDQSL tWPRE DI n DQ DM Case 2: tDQSS=max tDQSS tDSS tDQSH tDSS tWPST DQS tWPRES tDQSL tWPRE DI n DQ DM DI n = Data In from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DI n EN AP = Enable Autoprecharge ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Don’t Care Confidential - 58/62 - Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 41. Bank Write Access tCK tCH tCL CK CK tIS tIH CKE tIS tIH NOP COMMAND ACT NOP NOP WRITE NOP NOP NOP NOP PRE tIS tIH A0-A9 RA A11-A13 RA A10 RA Col n tIS tIH ALL BANKS DIS AP ONE BANK tIS tIH Bank X BA0,BA1 Bank X *Bank X tRAS tRCD Case 1: tDQSS=min tWR tDQSS tDSH tDQSH tDSH tWPST DQS tWPRES tWPRE tDQSL DI n DQ DM tDSS Case 2: tDQSS=max tDQSS tDSS tDQSH tWPST DQS tWPRES tDQSL tWPRE DI n DQ DM DI n = Data In from column n Burst Length = 4 in the case shown 3 subsequent elements of Data Out are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks Confidential - 59/62 - Don’t Care Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 42. Write DM Operation tCK tCH tCL CK CK tIS tIH CKE VALID tIS tIH NOP COMMAND WRITE NOP NOP NOP NOP PRE NOP NOP ACT tIS tIH RA Col n A0-A9 RA A11-A13 tIS tIH ALL BANKS RA A10 ONE BANKS DIS AP tIS tIH Bank X BA0,BA1 Case 1: tDQSS=min tDQSS BA *Bank X tDSH tDQSH tRP tDSH tWR tWPST DQS tDQSL tWPRES tWPRE DI n DQ DM tDSS Case 2: tDQSS=max tDQSS tDSS tDQSH tWPST DQS tWPRES tDQSL tWPRE DI n DQ DM DI n = Data In from column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are provided in the programmed order following DI n DIS AP = Disable Autoprecharge *= Don't Care , if A10 is HIGH at this point PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address NOP commands are shown for ease of illustration; other commands may be valid at these times Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25% window of the corresponding positive clock edge Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks Confidential - 60/62 - Don’t Care Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN Figure 43. 66 Pin TSOP II Package Outline Drawing Information Units: mm D D C L A2 L E E HE L1 L1 C A θ A1 b e S A1 F Symbol D A A1 A2 b e C D E HE L L1 F θ S Confidential y Dimension in mm Min Nom Max (TYP) Dimension in inch Min Nom Max --0.05 0.9 0.22 --- ----1.0 --0.65 1.2 0.2 1.1 0.45 --- --0.002 0.035 0.009 --- ----0.039 --0.026 0.047 0.008 0.043 0.018 --- 0.095 22.09 10.03 11.56 0.40 0.125 22.22 10.16 11.76 0.5 0.21 22.35 10.29 11.96 0.6 0.004 0.87 0.395 0.455 0.016 0.005 0.875 0.4 0.463 0.02 0.008 0.88 0.405 0.471 0.024 ----0°˚ 0.8 0.25 ----8°˚ ----0°˚ 0.032 0.01 --- --- --0.028 ----8°˚ 0.10 --- --- --- --0.71 --- --- - 61/62 - --0.004 Rev. 1.0 Oct.2015 AS4C64M16D1A-6TIN AS4C64M16D1A-6TCN PART NUMBERING SYSTEM AS4C DRAM 64M16D1A 64M16=64Mx16 D1=DDR1 (A=A Die Rev.) 6 6= 166MHz T C/I N T = TSOP II C=Commercial (0° C- +85° C) I=Industrial (-40° C- +85° C) Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Confidential - 62/62 - Rev. 1.0 Oct.2015