AX58100

AX58100 EtherCAT Slave Controller Features Document No: AX58100/V1.05/19/05/20 2/3-port EtherCAT Slave Controller (ESC) with Step & Direction Controller Adjustable step pulse width, polarity and the delay time for direction change 2 Integrated Fast Ethernet PHYs Standard EtherCAT Slave Controller (ESC) 8 Fieldbus Memory Management Units (FMMUs) 8 Sync Managers 64-bit distributed clock 9K bytes RAM Incremental and Hall Encoder Interface Support single ended ABZ with configurable counting constant, polarity and Multiple Zsignal functions support Supports clockwise/counter clockwise (CW/CCW) and direction-count (DIR/CLK) Inputs Supports Hall sensor Integrated Fast Ethernet PHYs Compliant with IEEE 802.3/802.3u 100BASETX/100BASE-FX PHY loopback mode Supports twisted pair crossover detection and auto-correction (HP Auto-MDIX) Automatic polarity detection and correction Emergency Stop Input Configurable Watchdog for Outputs and Inputs Monitoring IRQ Event Output Interrupts for EtherCAT related events Interrupts for Application related events Interrupts for Watchdog Timeout 3rd Ethernet MII Port for Flexible EtherCAT Network Configurations Up to 32 Digital/General Purpose IOs Each IO is configurable individually and mapped to FMMU directly SPI Master Interface Programmable SPI clock frequency up to 50MHz Supports 4 timing modes Supports MSB/LSB first transfer fashion Supports up to 8 SPI devices selection Supports up to 8 channels, each channel with 8 bytes read/write buffer Supports ADC Data Ready and DAC Data Loaded indication Supports periodic data acquisition Supports late sample for high latency device Supports external interrupt input SPI Slave Interface Supports Mode 3 timing modes Supports MSB first transfer fashion Local Bus Interface Supports 8-bit or 16-bit data bus width Supports Asynchronous Local Bus Supports BHE with 16-bit data bus width Bridge Supports function and ESC registers mirror with selectable synchronous conditions Supports I2C Master Interface 3-channel PWM Controller Adjustable frequency, phase align and BBM (Break Before Make) for all channels Adjustable duty cycle, phase shift, and signal polarity per channel Integrates On-chip Power-on Reset Circuit 80-pin LQFP RoHS Compliant Package Operating Temperature Range: -40 to +105°C Target Applications DAC/ADC Converters Control Sensors Data Acquisition Robotics Operator HMI Interfaces Industrial Automation Motion/Motor Control Digital I/O Control Communication Module ASIX Electronics Corporation 4F, No.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan 30078 1 Released Date: 19/05/2020 TEL: +886-3-579-9500 FAX: +886-3-579-9558 http://www.asix.com.tw/ AX58100 EtherCAT Slave Controller Typical Applications Diagram Figure 0-1: AX58100 Typical Applications Diagram 2 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. DISCLAIMER No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make changes to the product specifications and descriptions in this document at any time, without notice. ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without limitation warranties of merchantability, fitness for a particular purpose, and non-infringement. Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined” or “NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a design of ASIX products. TRADEMARKS ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the property of their respective owners. EtherCAT® is a registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany. 3 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Table of Contents 1 INTRODUCTION ............................................................................................................................................. 8 GENERAL DESCRIPTION ................................................................................................................................ 8 BLOCK DIAGRAM.......................................................................................................................................... 8 PINOUT DIAGRAM ......................................................................................................................................... 9 SIGNAL DESCRIPTION ................................................................................................................................. 10 1.4.1 General .............................................................................................................................................. 10 1.4.2 PDI Digital IO / GPIO ....................................................................................................................... 12 1.4.3 ESC PDI / Function SPI Slave Interface ............................................................................................ 12 1.4.4 ESC PDI / Function Local Bus Interface ........................................................................................... 13 1.4.5 PWM Motor Controller ...................................................................................................................... 13 1.4.6 Incremental / Hall Encoder Interface ................................................................................................ 13 1.4.7 SPI Master ......................................................................................................................................... 14 1.4.8 Port 2 MII .......................................................................................................................................... 14 2 FUNCTION DESCRIPTION.......................................................................................................................... 15 CLOCKS/RESETS ......................................................................................................................................... 15 ETHERCAT SLAVE CONTROLLER (ESC) .................................................................................................... 15 ETHERNET PHY .......................................................................................................................................... 15 BRIDGE FUNCTION ...................................................................................................................................... 15 I/O WATCHDOG .......................................................................................................................................... 16 PWM CONTROLLER.................................................................................................................................... 16 INCREMENTAL AND HALL ENCODER INTERFACE ........................................................................................ 16 SPI MASTER CONTROLLER ......................................................................................................................... 16 3 CHIP CONFIGURATION AND MEMORY MAP DESCRIPTION .......................................................... 17 BOOTSTRAP PINS FOR CHIP CONFIGURATION ............................................................................................. 17 HARDWARE CONFIGURATION EEPROM (HWCFGEE) ............................................................................. 18 3.2.1 EEPROM Contents Detailed Descriptions ........................................................................................ 21 MEMORY MAP ............................................................................................................................................ 26 3.3.1 ESC Memory Map .............................................................................................................................. 26 3.3.2 Function Register Map ....................................................................................................................... 32 3.3.3 Memory Map between ESC Memory and Function Registers ............................................................ 34 4 ELECTRICAL SPECIFICATIONS .............................................................................................................. 36 DC CHARACTERISTICS................................................................................................................................ 36 4.1.1 Absolute Maximum Ratings................................................................................................................ 36 4.1.2 Recommended Operating Condition .................................................................................................. 36 4.1.3 Leakage Current and Capacitance .................................................................................................... 36 4.1.4 DC Characteristics of 3.3V with 5V Tolerant I/O Pins ...................................................................... 37 POWER CONSUMPTION................................................................................................................................ 38 POWER-ON-RESET (POR) SPECIFICATION .................................................................................................. 39 POWER–UP SEQUENCE ................................................................................................................................ 40 AC TIMING CHARACTERISTICS ................................................................................................................... 41 4.5.1 I2C Timing .......................................................................................................................................... 41 4.5.2 Port 2 MII Timing .............................................................................................................................. 43 4.5.3 Distributed Clocks SYNC/LATCH ...................................................................................................... 46 4.5.4 Digital I/O Timing .............................................................................................................................. 47 4.5.5 ESC PDI SPI Slave Timing ................................................................................................................ 49 4.5.6 Function SPI Slave Timing................................................................................................................. 54 4.5.7 ESC PDI Local Bus Timing................................................................................................................ 55 4.5.8 Function Local Bus Timing ................................................................................................................ 59 4.5.9 PWM Motor Controller Timing ......................................................................................................... 61 4.5.10 Incremental and Hall Encoder Interface Timing ............................................................................... 64 4.5.11 SPI Master Timing ............................................................................................................................. 66 4 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4.5.12 RSTO, EEPROM and EEP_DONE Timing ........................................................................................ 69 5 PACKAGE INFORMATION ......................................................................................................................... 71 6 ORDERING INFORMATION ....................................................................................................................... 72 7 REVISION HISTORY .................................................................................................................................... 72 5 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller List of Figures FIGURE 0-1: AX58100 TYPICAL APPLICATIONS DIAGRAM .......................................................................................... 2 FIGURE 1-1: AX58100 BLOCK DIAGRAM ..................................................................................................................... 8 FIGURE 1-2: AX58100 PINOUT DIAGRAM .................................................................................................................... 9 FIGURE 3-1: AX58100 I2C EEPROM LAYOUT .......................................................................................................... 20 FIGURE 14-1: POWER ON RESET (POR) TIMING DIAGRAM ........................................................................................ 39 FIGURE 14-2: POWER-UP SEQUENCE TIMING DIAGRAM ............................................................................................. 40 FIGURE 14-3: WRITE ACCESS (1 ADDRESS BYTE, UP TO 16 KBIT EEPROMS) ............................................................. 41 FIGURE 14-4: WRITE ACCESS (2 ADDRESS BYTES, 32 KBIT - 4 MBIT EEPROMS) ....................................................... 41 FIGURE 14-5: READ ACCESS (1 ADDRESS BYTE, UP TO 16 KBIT EEPROMS)............................................................... 42 FIGURE 14-6: PORT 2 MII TX TIMING DIAGRAM ........................................................................................................ 43 FIGURE 14-7: PORT 2 MII RX TIMING DIAGRAM ....................................................................................................... 44 FIGURE 14-8: MDC/MDIO WRITE ACCESS ................................................................................................................ 45 FIGURE 14-9: MDC/MDIO READ ACCESS .................................................................................................................. 45 FIGURE 14-10: LATCH TIMING .................................................................................................................................. 46 FIGURE 14-11: SYNC TIMING .................................................................................................................................... 46 FIGURE 14-12: DIGITAL INPUT: INPUT DATA SAMPLED AT SOF, IO CAN BE READ IN THE SAME FRAME ..................... 47 FIGURE 14-13: DIGITAL INPUT: INPUT DATA SAMPLED WITH LATCH_IN ................................................................. 47 FIGURE 14-14: DIGITAL INPUT: INPUT DATA SAMPLED WITH SYNC0/1 ..................................................................... 47 FIGURE 14-15: DIGITAL OUTPUT TIMING .................................................................................................................... 48 FIGURE 14-16: BASIC MOSI/MISO TIMING ............................................................................................................... 49 FIGURE 14-17: PDI SPI SLAVE READ ACCESS (2 BYTE ADDRESSING, 1 BYTE READ DATA) WITH WAIT STATE BYTE .. 50 FIGURE 14-18: PDI SPI SLAVE READ ACCESS (2 BYTE ADDRESSING, 2 BYTE READ DATA) WITH WAIT STATE BYTE .. 51 FIGURE 14-19: PDI SPI SLAVE WRITE ACCESS (2 BYTE ADDRESSING, 1 BYTE WRITE DATA)....................................... 52 FIGURE 14-20: PDI SPI SLAVE WRITE ACCESS (3 BYTE ADDRESSING, 1 BYTE WRITE DATA)....................................... 53 FIGURE 14-21: FUNCTION SPI SLAVE WITH SHARE PIN TIMING DIAGRAM ................................................................. 54 FIGURE 14-22: FUNCTION SPI SLAVE WITH INDIVIDUAL PIN TIMING DIAGRAM ......................................................... 54 FIGURE 14-23: PDI LOCAL BUS READ ACCESS (WITHOUT PRECEDING WRITE ACCESS) .............................................. 55 FIGURE 14-24: PDI LOCAL BUS WRITE ACCESS (WRITE AFTER RISING EDGE LWRN, WITHOUT PRECEDING WRITE ACCESS) .............................................................................................................................................................. 55 FIGURE 14-25: PDI LOCAL BUS SEQUENCE OF TWO WRITE ACCESSES AND A READ ACCESS....................................... 56 FIGURE 14-26: PDI LOCAL BUS WRITE ACCESS (WRITE AFTER FALLING EDGE LWRN ............................................... 56 FIGURE 14-27: FUNCTION LOCAL BUS SIGNAL READ ACCESS ................................................................................... 59 FIGURE 14-28: FUNCTION LOCAL BUS WRITE ACCESS (LATE SAMPLE = 0) ............................................................... 59 FIGURE 14-29: FUNCTION LOCAL BUS WRITE ACCESS (LATE SAMPLE = 1) ............................................................... 60 FIGURE 14-30: PWMX TIMING ................................................................................................................................... 61 FIGURE 14-31: ONLY PWM CHANNEL 2 SHIFT DIAGRAM .......................................................................................... 62 FIGURE 14-32: BBM (BREAK BEFORE MAKE) TIMING DIAGRAM .............................................................................. 63 FIGURE 14-33: ONE SHOT WITH MULTI STEP TIMING DIAGRAM ................................................................................. 63 FIGURE 14-34: ABZ TIMING DIAGRAM ...................................................................................................................... 64 FIGURE 14-35: CW/CCW TIMING DIAGRAM.............................................................................................................. 64 FIGURE 14-36: CLK/DIR TIMING DIAGRAM .............................................................................................................. 64 FIGURE 14-37: HALL TIMING DIAGRAM ..................................................................................................................... 64 FIGURE 14-38: SPI MASTER TIMING .......................................................................................................................... 66 FIGURE 14-39: MMISO /MMOSIO TIMING ............................................................................................................... 66 FIGURE 14-40: SPI MDRLD READY TIMEOUT TIMING .............................................................................................. 67 FIGURE 14-41: SPI MTRG TRIGGER PULSE TIMEOUT ................................................................................................ 67 FIGURE 14-42: SPI MDRLD TRIGGER LDAC GAP AND WIDTH TIMING.................................................................... 67 FIGURE 14-43: POWER UP TO RSTO, EEPROM AND EEP_DONE TIMING ................................................................ 69 FIGURE 14-44: RSTN TO RSTO, EEPROM AND EEP_DONE TIMING ....................................................................... 69 FIGURE 14-45: REGISTER RESET TO RSTO, EEPROM AND EEP_DONE TIMING...................................................... 70 6 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller List of Tables TABLE 1-1: COMMON PIN DESCRIPTION ..................................................................................................................... 10 TABLE 1-2: ETHERNET PHY PIN DESCRIPTION........................................................................................................... 11 TABLE 1-3: POWER/GROUND PIN DESCRIPTION ......................................................................................................... 11 TABLE 1-4: PDI DIGITAL I/O, GPIO PIN DESCRIPTION .............................................................................................. 12 TABLE 1-5: PDI SPI SLAVE INTERFACE PIN DESCRIPTION ......................................................................................... 12 TABLE 1-6: PDI LOCAL BUS INTERFACE PIN DESCRIPTION ........................................................................................ 13 TABLE 1-7: PWM MOTOR CONTROLLER PIN DESCRIPTION ....................................................................................... 13 TABLE 1-8: INCREMENTAL/HALL ENCODER INTERFACE PIN DESCRIPTION ................................................................ 13 TABLE 1-9: SPI MASTER PIN DESCRIPTION ................................................................................................................ 14 TABLE 1-10: PORT 2 MII PIN DESCRIPTION ................................................................................................................ 14 TABLE 3-1: BOOTSTRAP PINS CONFIGURATION .......................................................................................................... 17 TABLE 3-2: ESC MEMORY MAP ................................................................................................................................. 31 TABLE 3-3: FUNCTION REGISTER MAP ....................................................................................................................... 33 TABLE 3-4: ESC MEMORY AND FUNCTION REGISTERS MIRROR MAPPING TABLE ..................................................... 35 TABLE 14-1: AX58100 POWER CONSUMPTION .......................................................................................................... 38 TABLE 14-2: THERMAL CHARACTERISTICS ................................................................................................................ 38 TABLE 14-3: POWER ON RESET (POR) TIMING TABLE............................................................................................... 39 TABLE 14-4: POWER-UP SEQUENCE TIMING TABLE.................................................................................................... 40 TABLE 14-5: I2C EEPROM TIMING TABLE ................................................................................................................ 42 TABLE 14-6: PORT 2 MII TX TIMING TABLE .............................................................................................................. 43 TABLE 14-7: PORT 2 MII RX TIMING TABLE.............................................................................................................. 44 TABLE 14-8: MDC/MDIO TIMING TABLE.................................................................................................................. 45 TABLE 14-9: DC SYNC/LATCH TIMING CHARACTERISTICS ..................................................................................... 46 TABLE 14-10: DIGITAL I/O TIMING TABLE ................................................................................................................. 48 TABLE 14-11: PDI SPI SLAVE TIMING TABLE ............................................................................................................ 49 TABLE 14-12: FUNCTION SPI WITH SHARE PIN TIMING TABLE ................................................................................... 54 TABLE 14-13: FUNCTION SPI WITH INDIVIDUAL PIN TIMING TABLE........................................................................... 54 TABLE 14-14: PDI LOCAL BUS TIMING TABLE........................................................................................................... 58 TABLE 14-15: FUNCTION LOCAL BUS ACCESS TIMING............................................................................................... 60 TABLE 14-16: PWMX TIMING TABLE......................................................................................................................... 61 TABLE 14-17: PWMX SHIFT TIMING TABLE .............................................................................................................. 62 TABLE 14-18: PWMX BBM TIMING TABLE ............................................................................................................... 63 TABLE 14-19: STEP FUNCTION TIMING TABLE............................................................................................................. 63 TABLE 14-20: INCREMENTAL AND HALL ENCODER TIMING TABLE ........................................................................... 65 TABLE 14-21: SPI MASTER TIMING TABLE ................................................................................................................ 68 TABLE 14-22: RSTO, EEPROM AND EEP_DONE TIMING TABLE ............................................................................. 70 7 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 1 Introduction General Description The AX58100 is a 2/3-port EtherCAT Slave Controller (ESC), licensed from Beckhoff Automation, with two integrated Fast Ethernet PHYs which support 100Mbps full-duplex operation and HP Auto-MDIX. The AX58100 supports the CANopen over EtherCAT (CoE), File Access over EtherCAT (FoE), Vendor Specific-protocol over EtherCAT (VoE), etc. Standard EtherCAT protocols provide a cost-effective solution for industrial automation applications, such as motion/motor/digital I/O control, Digital to Analog (DAC)/Analog to Digital (ADC) converters control, sensors data acquisition, and robotics, to be applied in industrial fieldbus. The AX58100 provides either a three-channel PWM controller or a Step/Direction controller, and also provides an Increment/Hall encoder interface for closed-loop motor control, a SPI master controller for DAC/ADC converter control and sensors data acquisition, 32 DIOs for industrial I/O control and an I/O watchdog for functional safety. The AX58100 provides two Process Data Interfaces (PDI), SPI slave and Local Bus, which support the connection with most popular MCU and DSP on those non-EtherCAT fieldbus applications. The AX58100 also provides two memory spaces, ESC and Function, users can decide which to access by using chip select. The bridge will synchronize two memory spaces’ contents for EtherCAT Master to remotely control AX58100 functions (PWM, SPI master etc.). The AX58100 reports the ESC and Functions interrupt events to interrupt status registers and supports level or edge interrupt trigger mode to inform external MCU/DSP to manage these ESC and Functions interrupt events. AX58100 supports a configurable individual function SPI slave interface to enhance SPI slave bandwidth. The AX58100, in 80-pin LQFP with EPAD, supports the RoHS compliant package and industrial grade operating temperature, which range from -40 to 105°C. Block Diagram Figure 1-1: AX58100 Block Diagram 8 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Pinout Diagram IO[4] / LDA[4] / MSS[0] TEST RSTO RSTn NC VCCK VCC12A_PLL IO[5] / LDA[5] / MSS[1] IO[19] / LA[11] / PULZ / TXD[0] IO[3] / LDA[3] / MINT IO[18] / LA[10] / PULC / MDC IO[10] / LA[2] / SFINT IO[17] / LA[9] / PULAB / MDIO IO[1] / LDA[1] / MMOSI VCCK VCC3IO IO[16] / LA[8] / LINK IO[0] / LDA[0] / MSCLK IO[20] / LA[12] / PULB / TXD[1] P1_ACT 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AX58100 is housed in an 80-pin E-PAD LQFP package. PDI_EMU 61 40 P0_ACT SCL 62 39 VCC33A SDA 63 38 P0_TXOP OE_EXT / LRDn / SCLK 64 37 P0_TXON VCC3IO 65 36 P0_RXIP IO[21] / LA[13] / PULA / TXD[2] 66 35 P0_RXIN IO[6] / LDA[6] / MSS[2] 67 34 P0_SD IO[22] / LBHE / PWM3H / TXD[3] 68 33 RSET_BG IO[7] / LDA[7] / MSS[3] 69 32 VCC33A IO[23] / PWM3L / TX_EN 70 31 XSCI IO[8] / LA[0] / MDRLD 71 30 XSCO VCCK 72 29 VCCK IO[24] / LDA[8] / PWM2H / RXD[0] 73 28 VCC33A AX58100 11 12 13 14 15 16 17 18 19 20 IO[28] / LDA[12] / EMn / RX_ER IO[13] / LA[5] / SMOSI IO[29] / LDA[13] / ENCA / RX_DV IO[14] / LA[6] IO[30] / LDA[14] / ENCB / RX_CLK VCCK IO[15] / LA[7] IO[31] / LDA[15] / ENCZ / MCLK LED_RUN LED_ERR EEP_DONE 10 VCC33A 21 VCC3IO 22 80 9 SOF / LECSn / SCS_ESC EOF / LFCSn / SCS_FUNC 8 P1_TXOP IO[12] / LA[4] / FSCLK 23 79 IO[27] / LDA[11] / PWM1L / RXD[3] 78 7 OUTVLD / LWRn / MOSI IO[11] / LA[3] / FMISO P1_TXON 6 24 LAT_IN / LRDY / MISO 77 5 VCC3IO VCCK P1_RXIP 4 25 3 76 SYNC_LATCH[1] IO[26] / LDA[10] / PWM1H / RXD[2] IO[2] / LDA[2] / MMISO P1_RXIN 2 26 SYNC_LATCH[0] P1_SD 75 1 27 IO[25] / LDA[9] / PWM2L / RXD[1] WD_TRIG / LINT / SINT IO[9] / LA[1] / MTRG 74 Figure 1-2: AX58100 Pinout Diagram 9 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Signal Description Following abbreviations are used in “Type” column of below pin description tables. Note that some I/O pins with multiple signal definitions on the same pin may have different attributes in “Type” column for different signal definition. AB AI AO B5 I5 O5 I3 O3 Analog Bi-directional I/O Analog Input Analog Output Bi-directional I/O, 3.3V with 5V tolerant Input, 3.3V with 5V tolerant Output, 3.3V with 5V tolerant Input, 3.3V Output, 3.3V PU PD P S T 4m 8m Internal Pull-Up (75K) Internal Pull-Down (75K) Power/Ground pin Schmitt Trigger Tri-state 4mA driving strength 8mA driving strength For example, pin 6 in AX58100 package can be LAT_IN, MISO or LRDY. If LAT_IN is selected, its Type is I5; if MISO or LRDY is selected, its Type is O5 or O5/T. In other words, the T (tri-state) only takes effect in LRDY signal mode while LAT_IN and MISO signal mode don’t. Users should refer to the table specific to the desired function for exact pin type definition. The multi-function pin settings are configured by the I2C Hardware Configuration EEPROM (HWCFGEE). Please refer to Section 3.2 for details. 1.4.1 General Pin Name Type Pin No TEST I5/PD/S 59 RSTn I5/PU/S 57 RSTO\ RSTO_POL O5/8m 58 31 30 PDI_EMU AI AB O5/T/4m/ S B5/T/4m/ S I5 EEP_DONE O5/8m 21 LED_RUN\ EEP_SIZE B5/4m 19 LED_ERR\ 3PORT_MODE B5/4m 20 SYNC_LATCH[0] B5/8m SYNC_LATCH[1] B5/8m NC I3 2 3 56 XSCI XSCO SCL SDA 62 63 61 Pin Description Test mode enable For normal operation, please always tie to logic low or NC. Reset Input, active low RST_N is the hardware reset input used to reset this chip. This input is AND with internal Power-On-Reset (POR) circuit, which generates the main system reset for this chip. Reset Output This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the RSTO polarity, please refer to Section 3.1. Crystal 25MHz Input Crystal 25MHz Output I2C Serial Clock line for I2C master controller SCL is a tri-stateable output, which requires an external pull-up resistor. I2C Serial Data line for I2C master controller. SDA is a tri-stateable output, which requires an external pull-up resistor. PDI Emulation enable This pin asserted high indicates that the EEPROM is successfully loaded (Checksum matched) and the PDI can be used. LED_RUN is input direction during chip reset stage used to bootstrap the mode setting to decide the EEPROM size configuration, please refer to Section 3.1. LED_ERR is input direction during chip reset stage used to bootstrap the mode setting to decide the Port 2 MII enable configuration, please refer to Section 3.1. Distributed Clocks SyncSignal output or LatchSignal input 0 Distributed Clocks SyncSignal output or LatchSignal input 1 Reserved. Please connect to GND. Table 1-1: Common Pin Description 10 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Pin Name Type Pin No P0_TXOP AB 38 P0_TXON AB 37 P0_RXIP AB 36 P0_RXIN AB 35 P0_SD AB 34 P0_ACT\ P0_FIBER B5/4m 40 P1_TXOP AB 23 P1_TXON AB 24 P1_RXIP AB 25 P1_RXIN AB 26 P1_SD AB 27 P1_ACT\ P1_FIBER B5/4m 41 RSET_BG AO 33 Pin Name Type VCC3IO P VCCK P VCC33A P VCC12A_PLL P GND P Pin No 10, 45, 65, 77 5, 16, 29, 46, 55, 72 22, 28, 32, 39 Pin Description PHY 0 differential Transmitted Positive signal In the copper mode, the differential data is transmitted to the media on the TXOP/TXON signal pair in the MDI mode. In the fiber mode, the signal pair should be connected to the TX+/TX- pin of the fiber transceiver. PHY 0 differential Transmitted Negative signal PHY 0 differential Received Positive signal In the copper mode, the differential data from the media is received on the RXIP/RXIN signal pair in the MDI mode. In the fiber mode, the signal pair should be connected to the RX+/RX- pin of the fiber transceiver. PHY 0 differential Received Negative signal PHY 0 fiber mode Signal Detect SD < 0.2V, Copper mode1.0V < SD < 1.8V, Fiber mode without detected signal. Generate far-end fault SD > 2.4V, Fiber mode with detected signal PHY 0 Link/Activity LED This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the PHY 0 media mode, please refer to Section 3.1. PHY 1 differential Transmitted Positive signal Same as PHY0 TXOP/ON description PHY 1 differential Transmitted Negative signal PHY 1 differential Received Positive signal Same as PHY0 RXIP/IN description PHY 1 differential Received Negative signal PHY 1 fiber mode Signal Detect Same P0_SD description PHY 1 Link/Activity LED This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the PHY 1 media mode, please refer to Section 3.1. PHY off-chip Bias Resistor Connects an external resistor of 12 KΩ ± 1% to the PCB analog ground. Table 1-2: Ethernet PHY Pin Description Pin Description Digital Power for I/O pins, 3.3V Please add a 0.1uF bypass capacitor between each VCC3IO and GND. Digital Power for core, 1.2V Please add a 0.1uF bypass capacitor between each VCCK and GND. Analog Power for Ethernet PHY, 3.3V Please add a 0.1uF bypass capacitor between VCC33A and GND. Analog Power for PLL, 1.2V. 54 Please add a 0.1uF bypass capacitor between VCC12A_PLL and GND. EPAD Ground for all Analog and Digital Power. Table 1-3: Power/Ground Pin Description 11 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 1.4.2 PDI Digital IO / GPIO Pin Name Type Pin No Pin Description 18, 15, 13, IO[31:24] B5/8m 11, 8, 76, Digital/General Purpose I/O[31:24] 75, 73 70, 68, 66, IO[23:16] B5/8m 42, 52, 50, Digital /General Purpose I/O[23:16] 48, 44 17, 14, 12, IO[15:8] B5/8m 9, 7, 49, Digital /General Purpose I/O[15:8] 74, 71 69, 67, 53, IO[7:0] B5/8m 60, 51, 4, Digital /General Purpose I/O[7:0] 47, 43 SOF O5/8m 79 Start-of-Frame EOF O5/8m 80 End-of-Frame OE_EXT I5 64 Output Enable OUTVLD O5/8m 78 Output data Valid/Output event LAT_IN I5 6 external data Latch WD_TRIG O5/8m 1 Watchdog Trigger Note: The IO[31:0] in PDI Digital mode is for DIO[31:0], in PDI SPI slave mode is for GPIO[31:0] Table 1-4: PDI Digital I/O, GPIO Pin Description 1.4.3 ESC PDI / Function SPI Slave Interface Pin Name Type Pin No Pin Description SCS_ESC I5 79 SPI Chip Select for ESC SCS_FUNC I5 80 SPI Chip Select for Function SCLK I5 64 SPI Clock MOSI I5 78 SPI data MOSI MISO O5 6 SPI data MISO SINT O5/T 1 SPI Interrupt FSCLK I5 9 Function SPI Clock FMOSI I5 12 Function SPI data MOSI FMISO O5 7 Function SPI data MISO SFINT O5/T 49 SPI Function Interrupt Note 1: The Function SPI slave could share pin with ESC or use independent pin, please refer to Section 3.2. Note 2: “Function” means the design for PWM, Incremental/Hall Encoder, SPI Master, I/O Watchdog and Bridge function, excluding ESC. Table 1-5: PDI SPI Slave Interface Pin Description 12 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 1.4.4 ESC PDI / Function Local Bus Interface Pin Name LECSn LFCSn LRDn LWRn LBHE LRDY LINT Type I5 I5 I5 I5 I5 O5/T O5/T Pin No Pin Description 79 Local bus ESC Chip Select 80 Local bus Function Chip Select 64 Local bus Read 78 Local bus Write 68 Local bus Byte High Enable (16-bit width only) 6 Local bus Ready 1 Local bus Interrupt 66, 42, 52, 50, 48, 44, LA[13:0] I5 Local bus Address bus 17, 14, 12, 9, 7, 49, 74, 71 18, 15, 13, LDA[15:8] B5 11, 8, 76, 75, Local bus Data bus [15:8] 73 69, 67, 53, LDA[7:0] B5 60, 51, 4, 47, Local bus Data bus [7:0] 43 Note: “Function” means the design for PWM, Incremental/Hall Encoder, SPI Master, I/O Watchdog and Bridge function, excluding ESC. Table 1-6: PDI Local Bus Interface Pin Description 1.4.5 PWM Motor Controller Pin Name PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PULA PULB PULZ PULC PULAB EMn Type O5/T O5/T O5/T O5/T O5/T O5/T O5 O5 O5 O5 O5 I5 Pin No Pin Description 8 PWM 1 Low pin or STEP pin 76 PWM 1 High pin or DIR pin 75 PWM 2 Low pin 73 PWM 2 High pin 70 PWM 3 Low pin 68 PWM 3 High pin 66 Pulse A, programmable point A 42 Pulse B, programmable point B 52 Pulse Z, PWM period start point 50 Pulse C, PWM period central point 48 Pulse AB, toggle when programmable point A and B 11 Emergency input, active low Table 1-7: PWM Motor Controller Pin Description 1.4.6 Incremental / Hall Encoder Interface Pin Name Type ENCA I5 ENCB I5 ENCZ I5 Pin No Pin Description 13 ENC input A, Sin., CW, CLK, or HALL A 15 ENC input B, Cos., CCW, DIR, or HALL B 18 ENC input Z, Zero point or HALL C Table 1-8: Incremental/Hall Encoder Interface Pin Description 13 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 1.4.7 SPI Master Pin Name Type MSS[3:0] O5 MSCLK MMOSI MMISO MINT MTRG MDRLD O5 O5 I5 I5 I5 B5 Pin No 69, 67, 53, 60 43 47 4 51 74 71 Pin Description SPI Master Slave Select SPI Master SCLK SPI Master MOSI SPI Master MISO SPI Master Interrupt in SPI Master Trigger in SPI Master ADC Data Ready / DAC Data Loaded Table 1-9: SPI Master Pin Description 1.4.8 Port 2 MII Pin Name Type Pin No MCLK O5 18 LINK I5 44 MDC MDIO TXD[3] O5 B5 O5 50 48 68 TXD[2:1] \ O5 TX_SH[1:0] 66, 42 TXD[0] \ O5 LINK_POL 52 TX_EN RX_CLK O5 I5 RXD[3:0] I5 RX_ER RX_DV I5 I5 Pin Description MII Clock 25 MHz clock source for Ethernet PHYs LINK Provided by the PHY if a 100 Mbps (Full Duplex) link is established. PHY Management Interface clock PHY Management Interface data Transmit data [3] Transmit data [2:1] This pin is input direction during chip reset stage used to bootstrap the mode setting to decide the external PHY’s TXD phase shift, please refer to Section 3.1. Transmit data [0] These pins are input direction during chip reset use to bootstrap the mode setting to decide external PHY’s LINK polarity, please refer to Section 3.1. Transmit enable Receive Clock 70 15 8, 76, 75, Receive data 73 11 Receive error 13 Receive data valid Table 1-10: Port 2 MII Pin Description 14 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 2 Function Description Clocks/Resets The AX58100 requires a crystal (25MHz, ±25 PPM at room temperature) as the clock source. Internal PLL generates the 100MHz clock for EtherCAT Slave Controller (ESC) and also for other functions. The AX58100 has three reset sources. First, during the VCCK power-on, the internal Power-On-Reset (POR) can generate a reset pulse to reset all the function blocks when the VCCK power pin rises to a certain threshold voltage level. The second reset is RSTn pin, which is to do the fundamental reset. And third, EtherCAT command reset, the EtherCAT master can send reset sequence to force AX58100 reset. AX58100 also supports a reset output RSTO polarity bootstrap configuration (RSTO_POL). EtherCAT Slave Controller (ESC) The AX58100 implements a 3-port EtherCAT slave controller (ESC), licensed from Beckhoff Automation, with 9 Kbytes Process Data RAM, 8 Fieldbus Memory Management Units (FMMUs), 8 Sync-Managers and a 64-bit Distributed Clock. Port 0 and 1 integrate embedded Ethernet PHYs, and port 2 is an optional MII interface which are multi-function pins shared with other interfaces (i.e. PWM, Hall, Local Bus, Digital I/O). Packets are forwarded in the following order: Port 0->EtherCAT Processing Unit->Port 1->Port 2. The Process Data Interface (PDI, also named host interface) provides SPI slave, asynchronous 8/16-bit microcontroller interface (also named Asynchronous Local Bus) and Digital I/O. The SPI slave and asynchronous 8/16-bit Local Bus interface will be used when external MCU in employed the slave system, and the Digital I/O is used for when direct I/O control. The AX58100 supports function register mirror from/to ESC memory space. The mirror registers located at process data memory address from 0x3000 to 0x33FF. For detailed information about the EtherCAT technology, the EtherCAT core mechanisms, and major features, we refer to the official standard documentations and guidelines available from ETG (www.ethercat.org, ETG.1000), IEC (http://www.iec.ch, IEC61158, IEC61784-2, IEC 61800-7), and Beckhoff (http://www.beckhoff.de, technical specification) web sites. Ethernet PHY The AX58100 is embedded two DSP-based Ethernet PHYs, which are fully compliant with the 100BASE-TX and 100BASE-FX Ethernet standards such as IEEE 802.3u, and ANSI X3.263-1995 (FDDI-TP-PMD). In copper mode, it supports the MDI/MDIX auto-crossover function (HP Auto-MDIX). Bridge Function The AX58100 has two memory spaces, one for ESC and another for AX58100 specific functions. The bridge handles data synchronization between ESC’s memory and function registers, and uses EthterCAT packet’s SOF, EOF, ESC control signal: SYNCx and LATx, PDI chip select (ESC and function) asserts and de-assert, the PWM cycle starts, register writes and register data change, total 13 sources to synchronize two space’s register content. Each function mirror could be enabled independent, the interrupt related registers mirror (INTCR and INTSR) are also enabled when any function mirror is enabled. 15 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller I/O Watchdog The I/O Watchdog is for AX58100 safety engine and used to monitor I/O signals toggle status and an emergency stop input (EMn) pin. When I/O signals don't match a pattern or keep over excepted time, the watchdog will be triggered, or EMn input pin asserted which would force I/O pads to enter default level. The default level is configurable which could be driven low, high or Tristate. PWM Controller The PWM control module provides Pulse Width Modulation (PWM) and STEP / DIR to control motor driving. The PWM mode has eight pins. There are three pairs of control signal. Each control signal pair has a high pulse pin (PWMxH) and low pulse pin (PWMxL) control power drive circuit. Others are two alignment pins, PULZ and PULC point cycle start and central time, and three programmable trigger pins, PULA PULB and PULAB. The step pulse mode has 2 pins, step (STEP) and direction (DIR), which connect to step motor controller and share PWM1H/L pins. The PWM supports up to 12.5MHz output frequency, and programmable polarity, timing adjustment. Incremental and Hall Encoder Interface The AX58100 provides an interface with a linear or rotary incremental encoder to get position information, and supports four input modes, including the Sin/Cos mode (A / B / Z pins), Clock-Wise mode (CW / CCW / Z pins), Direction-Clock mode (DIR / CLK / Z pins) and the Hall mode (A / B / C pins). It can accumulate positions in three modes, Sin/Cos, Clock-Wise and Direction-Clock modes, and calculate the GAP time in Hall mode. The Sin/Cos mode supports input frequency up to 8.33MHz, CW/CCW and DIR/CLK up to 16.66MHz, and the Hall mode up to 2.77MHz respectively. SPI Master Controller The Serial Peripheral Interface (SPI) master controller provides a full-duplex, synchronous serial communication interface (4 wires) to flexibly work with numerous SPI peripheral devices or microcontroller with the SPI slave. The SPI master controller supports 4 types of interface timing modes, namely, mode 0, 1, 2, and 3 to allow working with most SPI devices available. It also supports MSB/LSB first data transfer. The SPI master controller supports 8 channels, which could sequentially access per device, and supports variable transfer length up to 8 bytes each channel. It also supports multi-channel access to the same device, and the data length could be up to 64bytes. For high performance applications, the SPI master controller supports continuous transfer data between the SPI device and data registers. The SPI master controller provides 4 chip select, supports one-cold encode output (up to 4 devices), or uses binary encode output (use an external binary decoder) up to 8 devices. The SPI master controller supports standard SPI device access without glue logic circuit. Besides, it supports “trigger data ready input” for ADC application, and also supports “data loaded indication out” and “data path daisy chain” for DAC application. The MSCLK (SPI clock) is programmable by software and can run up to 50MHz. 16 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 3 Chip Configuration and Memory Map Description Bootstrap Pins for Chip Configuration The AX58100 supports five multi-function bootstrap pins (pin 19, 20, 58, 40, and 41) for five hardware configurations, i.e. external I2C EEPROM size, ESC supported port number, RSTO polarity and integrated port 0/1 PHY media mode; and it also supports other three multi-function bootstrap pins (pin 42, 52, 66) for the configuration of port 2 MII signals. User needs to utilize an external resistor to pull up / down these bootstrap pins. Pins Signal Name 19 EEP_SIZE 20 3PORT_MODE 58 RSTO_POL 61 PDI_EMU 40 P0_FIBER 41 P1_FIBER 66 TX_SH [1] 42 TX_SH [0] 52 LINK_POL Description I2C EEPROM Size 0: 1 Kbit to 16Kbit 1: 32Kbit to 4Mbit ESC port number 0: 2 ports mode 1: 3 ports mode RSTO Reset Output Polarity 0: Active Low 1: Active High Device emulation (0x0141.0) 0: Device status register is controlled by PDI 1: Device status register is identical to device control register Port 0 PHY media mode 0: Copper mode 1: Fiber mode Port 1 PHY Media mode 0: Copper mode 1: Fiber mode Port 2 MII TXD Align position 2‘b00: Align with MCLK, 2’b01: Delay 1/4 phase with MCLK 2’b10: Delay 1/2 phase with MCLK 2’b11: Delay 3/4 phase with MCLK Port 2 MII LINK Polarity 0: Active Low 1: Active High Table 3-1: Bootstrap Pins Configuration 17 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Hardware Configuration EEPROM (HWCFGEE) The AX58100 I2C master controller supports the communication to external I2C devices and an I2C Hardware Configuration EEPROM Loader to support loading the EtherCAT Slave Information (ESI) from external I2C EEPROM during chip reset. The AX58100 supports I2C EEPROM with EEPROM size from 1 Kbit (128 bytes) to 4 Mbit (500Kbytes). The AX58100 I2C Hardware Configuration EEPROM layout is shown in following figure. EEPROM Byte Offset EEPROM Word Offset 0x00 0x01 0x02 0x03 0x05 - 0x04 0x07 - 0x06 0x09 - 0x08 0x0A 0x0B 0x0C 0x0D 0x0F - 0x0E 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x13 - 0x10 0x17 - 0x14 0x1B - 0x18 0x1F - 0x1C 0x27 - 0x20 0x09 – 0x08 0x0B – 0x0A 0x0D – 0x0C 0x0F – 0x0E 0x13 – 0x10 0x29 - 0x28 0x2B - 0x2A 0x2D - 0x2C 0x2F - 0x2E 0x14 0x15 0x16 0x17 0x31 - 0x30 0x33 - 0x32 0x35 - 0x34 0x37 - 0x36 0x39 - 0x38 0x3F - 0x3A 0x18 0x19 0x1A 0x1B 0x1C 0x1F – 0x1D ESC Register Offset Parameter ESC Configuration Area PDI Control ESC Configuration (bit 2 is also mapped to ESC register 0x0110.2) PDI Configuration Sync/Latch [1:0] Configuration Pulse Length of SyncSignals Extended PDI Configuration Configured Station Alias Host Interface Extend Setting and Drive Strength Reserved, shall be zero Reserved, shall be zero Multi-Function Select and Drive Strength Checksum 0x0140 0x0141 0x0150 0x0151 0x0983 - 0x0982 0x0153 - 0x0152 0x0013 - 0x0012 Vendor ID Product Code Revision Number Serial Number Reserved Bootstrap Mailbox Config Bootstrap Receive Mailbox Offset Bootstrap Receive Mailbox Size Bootstrap Send Mailbox Offset Bootstrap Send Mailbox Size Mailbox Sync Man Config Standard Receive Mailbox Offset Standard Receive Mailbox Size Standard Send Mailbox Offset Standard Send Mailbox Size Mailbox Protocol Reserved 0x3D – 0x20 Reserved 0x3E Size 0x3F Version ESC Category 1 (for AX58100 Bridge Access Configuration if used) *Note1 0x81 ~ 0x80 0x40 Category 1 Type (Default: 0x0001) 0x83 ~ 0x82 0x41 Category 1 Data Size (words) (Default: 0x0021) 0x84 0x42 MCTLR Access Control 0x7B - 0x40 0x7D - 0x7C 0x7F - 0x7E 18 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. 0x0580 AX58100 EtherCAT Slave Controller EEPROM Byte Offset 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 EEPROM Word Offset 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A Parameter PXCFGR Access Control PTAPPR Access Control PTBPPR Access Control PPCR Access Control PBBMR Access Control P1CTRLR Access Control P1SHR Access Control P1HPWR Access Control P2CTRLR Access Control P2SHR Access Control P2HPWR Access Control P3CTRLR Access Control P3SHR Access Control P3HPWR Access Control SGTR Access Control SHPWR Access Control TDLYR Access Control STNR Access Control SCFGR Access Control SCTRLR Access Control SCNTR Access Control ECNTVR Access Control ECNSTR Access Control ELATR Access Control EMODR Access Control ECLRR Access Control HALSTR Access Control WTR Access Control WCFGR Access Control WTPVCR Access Control WMSPR Access Control WMMR Access Control WOMR Access Control WOER Access Control WOPR Access Control WTPVR Access Control SPICFGR Access Control SPIBRR Access Control SPIDBSR Access Control SPIDTR Access Control SPIRPTR Access Control SPILTR Access Control SPIPRLR Access Control SPI01BCR Access Control SPI23BCR Access Control SPI45BCR Access Control SPI67BCR Access Control SPI03SSR Access Control 19 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. ESC Register Offset 0x0581 0x0582 0x0583 0x0584 0x0585 0x0586 0x0587 0x0588 0x0589 0x058A 0x058B 0x058C 0x058D 0x058E 0x058F 0x0590 0x0591 0x0592 0x0593 0x0594 0x0595 0x0596 0x0597 0x0598 0x0599 0x059A 0x059B 0x059C 0x059D 0x059E 0x059F 0x05A0 0x05A1 0x05A2 0x05A3 0x05A4 0x05A5 0x05A6 0x05A7 0x05A8 0x05A9 0x05AA 0x05AB 0x05AC 0x05AD 0x05AE 0x05AF 0x05B0 AX58100 EtherCAT Slave Controller EEPROM Byte Offset 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 EEPROM Word Offset Parameter SPI47SSR Access Control SPIINTSR Access Control 0x5B SPITSR Access Control SPIPOSR Access Control 0x5C SPI Data Status (SPIDSR and SPIDSMR) Access Control SPIC0DR Access Control 0x5D SPIC1DR Access Control SPIC2DR Access Control 0x5E SPIC3DR Access Control SPIC4DR Access Control 0x5F SPIC5DR Access Control SPIC6DR Access Control 0x60 SPIC7DR Access Control SPIMCR Access Control 0x61 INTCR Access Control INTSR Access Control 0x62 Function Mirror Enable Other ESC Categories Information (Subdivided in Categories) … Category Strings Category Generals Category FMMU Category SyncManager Category Tx - / RxPDO for each PDO ESC Register Offset 0x05B1 0x05B2 0x05B3 0x05B4 0x05B5 0x05B6 0x05B7 0x05B8 0x05B9 0x05BA 0x05BB 0x05BC 0x05BD 0x05BE 0x05BF 0x05C0 0x05C1 Figure 3-1: AX58100 I2C EEPROM Layout Note 1: Reserved words or reserved bits of the ESC Configuration Area should be filled with 0. Note 2: When (re-) configuring the EEPROM from an EtherCAT master system special care must be taken. Not every master allows writing a category 1 entry to the EEPROM. There are different ways to write this into the EEPROM for automatically loading access control configuration when AX58100 booting. 1. Use preprogrammed I2C EEPROM. 2. Use a different category, e.g., 2049, first. Then overwrite the upper byte with 0 with a single EEPROM byte writes. The AX58100 HWCFGEE contents from offset 0x00 to 0x7F are mandatory, as well as the general category (at least the minimum I2C EEPROM size is 2Kbit, and for the complex devices with many categories should be equipped with 32 Kbit EEPROMs or larger one). The ESC Configuration Area is used for AX58100 hardware configuration. All other areas are used by the EtherCAT master or the local application. The ESC Configuration Area (EEPROM offset 0x00 to 0x0F) is automatically read by AX58100 after poweron or reset. It contains the PDI configuration, Distributed Clocks settings, and Configured Station Alias. The consistency of the ESC Configuration Area data is secured with a checksum. The EtherCAT Master can invoke reloading the EEPROM contents. In this case, the Configured Station Alias register 0x0012:0x0013 and ESC Configuration register bits 0x0141 [1,4,5,6,7] (enhanced link detection) are not transferred into the registers. They are only transferred at the initial EEPROM loading after power-on or reset. To use AX58100 bridge functionalities, users should define the Bridger Access Configuration parameters in the first category located at EEPROM offset 0x80. The Category Type must be 0x0001and the Category Data Size 20 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller must be 0x0020 so the AX58100 will automatically load the EEPROM Bridger Access Configuration parameters into the Bridge Access Configuration registers memory area starting at 0x0580 after power-on or reset. 3.2.1 EEPROM Contents Detailed Descriptions PDI Control (0x00) Bit 7:0 Description PDI Control [7:0] 0x00: Interface deactivated (no PDI) 0x04: Digital I/O 0x05: SPI Slave 0x08: 16-bit Asynchronous Local Bus 0x09: 8-bit Asynchronous Local Bus Others: reserved ESC Configuration (0x01) Bit 0 1 3:2 4 5 6 7 Description Device emulation enables (control of AL status) Enhanced Link detection all ports Reserved Enhanced Link port 0 Enhanced Link port 1 Enhanced Link port 2 Reserved PDI Configuration (0x02) Digital I/O Bit 0 1 2 3 5:4 7:6 OUTVALID polarity OUTVALID mode Unidirectional/Bidirectional mode Watchdog behavior Input DATA is sampled Output DATA is updated SPI Slave Bit 1:0 3:2 4 5 7:6 SPI mode SPI_IRQ output driver/polarity SPI_SEL polarity Data Out sample mode Reserved Description Description Asynchronous Local Bus Bit 1:0 BUSY/RDY driver/polarity 3:2 IRQ driver/polarity 4 BHE/Byte Enable polarity 7:5 Reserved Description 21 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Sync/Latch[1:0] Configuration (0x03) Bit 1:0 2 3 5:4 6 7 Description SYNC0 output driver/polarity SYNC0/LATCH0 configuration SYNC0 mapped to AL Event Request SYNC1 output driver/polarity SYNC1/LATCH1 configuration SYNC1 mapped to AL Event Request Pulse Length SyncSignals (0x05 - 0x04) Bit 15:0 Description Pulse length of SyncSignal Extended PDI Configuration (0x07 - 0x06) Digital I/O / SPI Slave (for GPIO) Bit Description Digital I/O or GPIO Digital I/O or GPIO are configured in pairs (1:0) as inputs or outputs: 0 0: Input 1: Output 1 3:2 pair (0: Input, 1: Output) 2 5:4 pair (0: Input, 1: Output) 3 7:6 pair (0: Input, 1: Output) 4 9:8 pair (0: Input, 1: Output) 5 11:10 pair (0: Input, 1: Output) 6 13:12 pair (0: Input, 1: Output) 7 15:14 pair (0: Input, 1: Output) 8 17:16 pair (0: Input, 1: Output) 9 19:18 pair (0: Input, 1: Output) 10 21:20 pair (0: Input, 1: Output) 11 23:22 pair (0: Input, 1: Output) 12 25:24 pair (0: Input, 1: Output) 13 27:26 pair (0: Input, 1: Output) 14 29:28 pair (0: Input, 1: Output) 15 31:30 pair (0: Input, 1: Output) Asynchronous Local Bus Bit Description 0 Read BUSY delay 1 Perform internal write 10:2 Reserved 11 23:22 pair (data bus 8-bit width only) (0: Input, 1: Output) 12 25:24 pair (data bus 8-bit width only) (0: Input, 1: Output) 13 27:26 pair (data bus 8-bit width only) (0: Input, 1: Output) 14 29:28 pair (data bus 8-bit width only) (0: Input, 1: Output) 15 31:30 pair (data bus 8-bit width only) (0: Input, 1: Output) Configured Station Alias (0x09 - 0x08) Bit 15:0 Description Alias Address used for node addressing 22 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Host Interface Extend Setting and Drive Strength (0x0A) Digital I/O Bit 4:0 Reserved Control Driving Select: 5 0: 4mA 1: 8mA IO [9:0] Driving Select: 6 0: 4mA 1: 8mA IO [15:10] Driving Select: 7 0: 4mA 1: 8mA Description SPI Slave / Asynchronous Local Bus Bit Description Interrupt Edge Pulse Length (INTP_LEN) 3:0 Interrupt Edge Pulse = (INTP_LEN+1) * 100ns The trigger type of interrupt signal, SINT / LINT 4 0: Level trigger. 1: Edge trigger. Control Driving Select: 5 0: 4mA 1: 8mA IO [9:0] Driving Select: 6 0: 4mA 1: 8mA IO [15:10] Driving Select: 7 0: 4mA 1: 8mA Multi-Function Select and Drive Strength (0x0D) Bit 0 1 2 3 4 5 Description IO [9:0] select: 0: IO [9:0] 1: MTRG, MDRLD, MSS [3:0], MINT, MMISO, MMOSI, MSCLK, Note: in Local Bus mode this bit no function IO [15:10] (SPI slave separates) select: 0: IO [15:10] 1: IO [15:14], FMOSI, FSCLK, FMISO, SFINT Note: in Local Bus mode this bit no function IO [21:16] select: 0: IO [21:16] 1: PULA, PULB, PULZ, PULZ, PULAB, IO [16] Note: in Local Bus mode this bit no function IO [25:22] select: 0: IO [25:22] 1: PWM2L, PWM2H, PWM3L, PWM3H Note: in Local Bus 16 bits mode this bit no function IO [28:26] select: 0: IO [28:26] 1: EM, PWM1L, PWM1H Note: in Local Bus 16 bits mode this bit no function IO [31:29] select: 0: IO [31:29] 1: ENCZ, ENCB, ENCA Note: in Local Bus 16 bits mode this bit no function 23 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller IO [21:16] Driving Select: 0: 4mA 1: 8mA IO [31:22] Driving Select: 7 0: 4mA 1: 8mA Note: When MII port 2 enable, the IO [31:16] pins are forced to MII port 2 6 Checksum (0x0F - 0x0E) Bit 15:0 Description Checksum Low byte contains remainder of division of EEPROM offset 0x00 to 0x0D as unsigned number divided by the polynomial X^8+X^2+X+1 (initial value 0xFF) For debugging purposes, it is possible to disable the checksum validation with a checksum value of 0x88A4. Note that NEVER use this for production! Category 1 Type (0x81 - 0x80) Bit 15:0 Description Category 1 Type MUST be 0x0001 Category 1 Data Size (0x83 - 0x82) Bit 15:0 Description Category 1 Data Size (words) MUST be 0x0021 MCTLR Access Control (0x84) Bit 3:0 4 7:5 Description Sync. Source Select 0x0: Always triggered 0x1: Start Of Frame (SOF) 0x2: End Of Frame (EOF) 0x3: SYNC0 signal 0x4: LATCH0 signal 0x5: SYNC1 signal 0x6: LATCH1 signal 0x7: After write access 0x8: Trigger when data value changes 0x9: PDI Chip Select Assert 0xA: PDI Chip Select De-assert 0xB: FUNC Chip Select Assert 0xC: FUNC Chip Select De-assert 0xD: Trigger at start of MFC PWM cycle Others: Always triggered ESC Access Enable 0: Writeable with Function Host Interface 1: Writeable with ESC Reserved The Bit Definitions of the other parameters from EEPROM offset 0x85 to 0xC4 are the same as the Bit Definitions of EEPROM offset 0x84. 24 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Function mirror enable (0xC5) Bit 0 1 2 3 7:4 Description PWM function register mirror: 0: Disable PWM function register mirror 1: Enable PWM function register mirror ENC function register mirror: 0: Disable ENC function register mirror 1: Enable ENC function register mirror SPI Master function register mirror: 0: Disable SPI Master function register mirror 1: Enable SPI Master function register mirror IO Watchdog function register mirror: 0: Disable IO Watchdog function register mirror 1: Enable IO Watchdog function register mirror Reserved 25 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Memory Map This section introduces the memory mapping in AX58100. AX58100 provides SPI and Local Bus slave interfaces for both ESC PDI and Function to access the internal registers. Section 3.3.1 introduces the ESC memory map which can be accessed by PDI SPI or Local bus interface ,and section 3.3.2 introduces the Function register map which can be accessed by Function SPI or Local Bus interface. Due to the Function registers can be accessed by PDI interface and EtherCAT Master directly. So, section 3.3.3 introduces the relationship between Function and ESC PDI through the Bridge function. 3.3.1 ESC Memory Map ESC Address Length (Bytes) 0x0000 0x0001 0x0002 0x0004 0x0005 0x0006 0x0007 0x0008 1 1 2 1 1 1 1 2 0x0010 0x0012 2 2 0x0020 0x0021 0x0030 0x0031 1 1 1 1 0x0040 0x0041 0x0100 0x0108 0x0110 1 1 4 2 2 0x0120 0x0130 0x0134 0x0138 0x0139 2 2 2 1 1 0x0140 0x0141 0x0150 0x0151 0x0152 1 1 1 1 2 0x0200 0x0204 0x0210 2 4 2 Description ESC Information Type Revision Build FMMUs supported SyncManagers supported RAM Size Port Descriptor ESC Features supported Station Address Configured Station Address Configured Station Alias Write Protection Write Register Enable Write Register Protection ESC Write Enable ESC Write Protection Data Link Layer ESC Reset ECAT ESC Reset PDI ESC DL Control Physical Read/Write Offset ESC DL Status Application Layer AL Control AL Status AL Status Code RUN LED Override ERR LED Override PDI PDI Control ESC Configuration PDI Configuration Sync/Latch PDI Configuration Extended PDI Configuration Interrupts ECAT Event Mask AL Event Mask ECAT Event Request 26 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 0x0220 0x0300 0x0308 0x030C 0x030D 0x030E 0x0310 0x0400 0x0410 0x0420 0x0440 0x0442 0x0443 0x0500 0x0501 0x0502 0x0504 0x0508 0x0510 0x0512 0x0513 0x0514 0x0516 0x0517 0x0518 0x0580 0x0581 0x0582 0x0583 0x0584 0x0585 0x0586 0x0587 0x0588 0x0589 0x058A 0x058B 0x058C 0x058D 0x058E 0x058F 0x0590 0x0591 0x0592 0x0593 0x0594 0x0595 0x0596 4 AL Event Request Error Counters 4x2 RX Error Counter [3:0] 4x1 Forwarded RX Error counter [3:0] 1 ECAT Processing Unit Error Counter 1 PDI Error Counter 1 PDI Error Code 4x1 Lost Link Counter [3:0] Watchdogs 2 Watchdog Divider 2 Watchdog Time PDI 2 Watchdog Time Process Data 2 Watchdog Status Process Data 1 Watchdog Counter Process Data 1 Watchdog Counter PDI I2C EEPROM Interface 1 EEPROM Configuration 1 EEPROM PDI Access State 2 EEPROM Control/Status 4 EEPROM Address 4 EEPROM Data MII Management Interface 2 MII Management Control/Status 1 PHY Address 1 PHY Register Address 2 PHY Data 1 MII Management ECAT Access State 1 MII Management PDI Access State 4 PHY Port Status Bridge Access Configuration (Refer to Section 9.3) MCTLR Access Control Register 1 PXCFGR Access Control Register 1 PTAPPR Access Control Register 1 PTBPPR Access Control Register 1 PPCR Access Control Register 1 PBBMR Access Control Register 1 P1CTRLR Access Control Register 1 P1SHR Access Control Register 1 P1HPWR Access Control Register 1 P2CTRLR Access Control Register 1 P2SHR Access Control Register 1 P2HPWR Access Control Register 1 P3CTRLR Access Control Register 1 P3SHR Access Control Register 1 P3HPWR Access Control Register 1 Step Gap Time Access Control Register 1 SHPWR Access Control Register 1 TDLYR Access Control Register 1 Step Target Number Access Control Register 1 SCFGR Access Control Register 1 SCTRLR Access Control Register 1 Step Counter Content Access Control Register 1 Encoder Counter Value Access Control Register 1 27 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 0x0597 0x0598 0x0599 0x059A 0x059B 0x059C 0x059D 0x059E 0x059F 0x05A0 0x05A1 0x05A2 0x05A3 0x05A4 0x05A5 0x05A6 0x05A7 0x05A8 0x05A9 0x05AA 0x05AB 0x05AC 0x05AD 0x05AE 0x05AF 0x05B0 0x05B1 0x05B2 0x05B3 0x05B4 0x05B5 0x05B6 0x05B7 0x05B8 0x05B9 0x05BA 0x05BB 0x05BC 0x05BD 0x05BE 0x05BF 0x05C0 0x05C1 0x0600:0x067F +0x0 +0x4 +0x6 +0x7 +0x8 +0xA +0xB +0xC +0xD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 2 1 1 2 1 1 1 3 Encoder Constant Access Control Register Encoder Latched Access Control Register EMODR Access Control Register ECLRR Access Control Register HALSTR Access Control Register Watchdog Timer Access Control Register WCFGR Access Control Register WTPVCR Access Control Register Watchdog monitored Polarity Access Control Register Watchdog monitored Mask Access Control Register Watchdog Output Mask Access Control Register Watchdog Output Enable Access Control Register Watchdog Output Polarity Access Control Register Watchdog Timer Peak value Access Control Register SPICFGR Access Control Register SPIBRR Access Control Register SPIDBSR Access Control Register SPIDTR Access Control Register SPIRPTR Access Control Register SPILTR Access Control Register SPIPRLR Access Control Register SPI01BCR Access Control Register SPI23BCR Access Control Register SPI45BCR Access Control Register SPI67BCR Access Control Register SPI03SSR Access Control Register SPI47SSR Access Control Register SPINTSR Access Control Register SPITSR Access Control Register SPIPOSR Access Control Register SPI Data Status (SPIDSR and SPIDSMR) Access Control Register SPIC0DR Access Control Register SPIC1DR Access Control Register SPIC2DR Access Control Register SPIC3DR Access Control Register SPIC4DR Access Control Register SPIC5DR Access Control Register SPIC6DR Access Control Register SPIC7DR Access Control Register SPIMCR Access Control Register INTCR Access Control Register INTSR Access Control Register Function Mirror Enable Register FMMU[7:0] Logical Start Address Length Logical Start bit Logical Stop bit Physical Start Address Physical Start bit Type Activate Reserved 28 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 0x0800:0x083F +0x0 +0x2 +0x4 +0x5 +0x6 +0x7 0x0900:0x09FF 0x0900 0x0904 0x0908 0x090C 0x0910 0x0918 0x0920 0x0928 0x092C 0x0930 0x0932 0x0934 0x0935 0x0980 0x0981 0x0982 0x0984 0x098E 0x098F 0x0990 0x0998 0x09A0 0x09A4 0x09A8 0x09A9 0x09AE 0x09AF 0x09B0 0x09B8 0x09C0 0x09C8 0x09F0 0x09F8 0x09FC 0x0E00 0x0E08 0x0F00 SyncManager[7:0] Physical Start Address Length Control Register Status Register Activate PDI Control Distributed Clocks (DC) DC – Receive Times 4 Receive Time Port 0 4 Receive Time Port 1 4 Receive Time Port 2 4 Receive Time Port 3 DC – Time Loop Control Unit 4(W)/8(R) System Time 8 Receive Time ECAT Processing Unit 8 System Time Offset 4 System Time Delay 4 System Time Difference 2 Speed Counter Start 2 Speed Counter Diff 1 System Time Difference Filter Depth 1 Speed Counter Filter Depth DC – Cyclic Unit Control 1 Cyclic Unit Control DC – SYNC Out Unit 1 Activation 2 Pulse Length of SyncSignals 1 Activation Status 1 SYNC0 Status 1 SYNC1 Status 8 Start Time Cyclic Operation/Next SYNC0 Pulse 8 Next SYNC1 Pulse 4 SYNC0 Cycle Time 4 SYNC1 Cycle Time DC – Latch In Unit 1 Latch0 Control 1 Latch1 Control 1 Latch0 Status 1 Latch1 Status 8 Latch0 Time Positive Edge 8 Latch0 Time Negative Edge 8 Latch1 Time Positive Edge 8 Latch1 Time Negative Edge DC – SyncManager Event Times 4 EtherCAT Buffer Change Event Time 4 PDI Buffer Start Event Time 4 PDI Buffer Change Event Time ESC specific 8 Product ID 8 Vendor ID Digital Input/Output 4 Digital I/O Output Data 2 2 1 1 1 1 29 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 0x0F10 0x0F18 0x0F80 0x1000 0x1000 0x3000 0x3002 0x3004 0x3006 0x3008 0x300A 0x300C 0x300E 0x3010 0x3012 0x3014 0x3016 0x3018 0x301A 0x301C 0x3020 0x3024 0x3026 0x3028 0x302C 0x302E 0x3040 0x3044 0x304C 0x304E 0x3060 0x3064 0x3066 0x3068 0x306C 0x3070 0x3074 0x3078 0x3080 0x3082 0x3084 0x3086 0x3088 0x308A 0x308C 0x3090 0x3092 0x3094 0x3096 0x3098 4 4 General Purpose Outputs General Purpose Inputs User RAM/Extended ESC features 128 User RAM/Extended ESC Features Process Data RAM 4 Digital I/O Input Data 8KB Process Data RAM Function Register Mirror (Refer to Section 3.3.2) Write / Read 2 Motor Control Register 2 PWM Pulse X Configure Register 2 PWM Trigger A Pulse Position Register 2 PWM Trigger B Pulse Position Register PWM Period Cycle Register 2 2 PWM Pulse Break Before Make Register 2 PWM1Control Register 2 PWM1 Counter Shift Register 2 PWM1 High Pulse Width Register 2 PWM2 Control Register PWM2 Shift Register 2 2 PWM2 High Pulse Width Register 2 PWM3 Control Register 2 PWM3 Counter Shift Register 2 PWM3 High Pulse Width Register 4 Step Gap Time Register Step High Pulse Width Register 2 2 Direction Transform Delay Step Register 4 Step Target Number Register 2 Step Configure Register 2 Step Control Register 4 Encoder Counter Value Register Encoder Constant Register 4 2 Encoder Mode configuration Register 2 Encoder Clear Register 4 Watchdog Timer Register 2 Watchdog Control Register 2 Watchdog Timer Peak Value Clear Register Watchdog Monitored Signals Polarity Register 4 4 Watchdog Monitored Signals Mask Register 4 Watchdog Output Mask Register 4 Watchdog Output Enable Register 4 Watchdog Output Polarity Register 2 SPI Configure Register SPI Baud Rate Register 2 2 SPI Delay Byte and SS Register 2 SPI Delay Transfer Register 2 SPI RDY / Pulse Time Register 2 SPI LDAC Time Register 2 SPI Pulse/ RDY/ LDAC Register SPI 0/1 Byte Count Register 2 2 SPI 2/3 Byte Count Register 2 SPI 4/5 Byte Count Register 2 SPI 6/7 Byte Count Register 2 SPI 0/1/2/3 slave Select Register 30 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 0x309A 0x30B0 0x30B8 0x30C0 0x30C8 0x30D0 0x30D8 0x30E0 0x30E8 0x30F2 0x3100 0x3102 2 8 8 8 8 8 8 8 8 2 2 2 0x3230 0x3248 0x3250 0x327C 0x32A8 0x32AA 0x32AC 0x32AE 0x32B0 0x32B8 0x32C0 0x32C8 0x32D0 0x32D8 0x32E0 0x32E8 0x32F0 4 4 2 4 2 2 2 2 8 8 8 8 8 8 8 8 2 SPI 4/5/6/7 slave Select Register SPI Channel 0 Data Register SPI Channel 1 Data Register SPI Channel 2 Data Register SPI Channel 3 Data Register SPI Channel 4 Data Register SPI Channel 5 Data Register SPI Channel 6 Data Register SPI Channel 7 Data Register SPI Master Control Register Interrupt Configure Register Interrupt Status Register Read Only Step Counter Content Register Encoder Latched Register Hall State Register Watchdog Timer Peak Value Register SPI Interrupt Status Register SPI Timeout Status Register SPI Pulse Overrun Status Register SPI Data Status Register SPI Channel 0 Data Register SPI Channel 1 Data Register SPI Channel 2 Data Register SPI Channel 3 Data Register SPI Channel 4 Data Register SPI Channel 5 Data Register SPI Channel 6 Data Register SPI Channel 7 Data Register SPI Data Status Mirror Register Table 3-2: ESC Memory Map 31 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 3.3.2 Function Register Map Address Offset 0x000 0x002 0x004 0x006 0x008 0x00A 0x00C 0x00E 0x010 0x012 0x014 0x016 0x018 0x01A 0x01C 0x020 0x022 0x024 0x026 0x028 0x02A 0x02C 0x02E 0x030 0x032 0x040 0x042 0x044 0x046 0x048 0x04A 0x04C 0x04E 0x050 0x060 0x062 0x064 0x066 0x068 0x06A 0x06C 0x06E 0x070 0x072 0x074 0x076 0x078 0x07A 0x07C 0x07E 0x080 0x082 Name MCTLR PXCFGR PTAPPR PTBPPR PPCR PBBMR P1CTRLR P1SHR P1HPWR P2CTRLR P2SHR P2HPWR P3CTRLR P3SHR P3HPWR SGTLR SGTHR SHPWR TDLYR STNLR STNHR SCFGR SCTRLR SCNTLR SCNTHR ECNTVLR ECNTVHR ECNSTLR ECNSTHR ELATLR ELATHR EMODR ECLRR HALSTR WTLR WTHR WCFGR WTPVCR WMPLR WMPHR WMMLR WMMHR WOMLR WOMHR WOELR WOEHR WOPLR WOPHR WTPVLR WTPVHR SPICFGR SPIBRR Description Motor Control Register PWM Pulse X Configure Register PWM Trigger A Pulse Position Register PWM Trigger B Pulse Position Register PWM Period Cycle Register PWM Pulse Break Before Make Register PWM1Control Register PWM1 Counter Shift Register PWM1 High Pulse Width Register PWM2 Control Register PWM2 Shift Register PWM2 High Pulse Width Register PWM3 Control Register PWM3 Counter Shift Register PWM3 High Pulse Width Register Step Gap Time Low Register Step Gap Time High Register Step High Pulse Width Register direction Transform Delay step Register Step Target Number Low Word Register Step Target Number High Word Register Step Configure Register Step Control Register Step Counter Content Low Register Step Counter Content High Register Encoder Counter value Low Register Encoder Counter value High Register Encoder Constant Low Register Encoder Constant High Register Encoder Latched Low Register Encoder Latched High Register Encoder Mode Configuration Register Encoder Clear Register Hall State Register Watchdog Timer Low Register Watchdog Timer High Register Watchdog Configure Register Watchdog Timer Peak Value Clear Register Watchdog Monitored Polarity Low Register Watchdog Monitored Polarity High Register Watchdog Monitored Mask Low Register Watchdog Monitored Mask High Register Watchdog Output Mask Low Register Watchdog Output Mask High Register Watchdog Output Enable Low Register Watchdog Output Enable High Register Watchdog Output Polarity Low Register Watchdog Output Polarity High Register Watchdog Timer Peak Value Low Register Watchdog Timer Peak Value High Register SPI Configure Register SPI Baud Rate Register 32 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 0x084 0x086 0x088 0x08A 0x08C 0x090 0x092 0x094 0x096 0x098 0x09A 0x0A8 0x0AA 0x0AC 0x0AE 0x0B0 0x0B8 0x0C0 0x0C8 0x0D0 0x0D8 0x0E0 0x0E8 0x0F0 0x0F2 0x100 0x102 0x104 0x106 Others SPIDBSR SPIDTR SPIRPTR SPILTR SPIPRLR SPI01BCR SPI23BCR SPI45BCR SPI67BCR SPI03SSR SPI47SSR SPINTSR SPITSR SPIPOSR SPIDSR SPIC0DR SPIC1DR SPIC2DR SPIC3DR SPIC4DR SPIC5DR SPIC6DR SPIC7DR SPIDSMR SPIMCR INTCR INTSR ESTOR HSTSR Reserved SPI Delay Byte and SS Register SPI Delay Transfer Register SPI RDY / Pulse Time Register SPI LDAC Time Register SPI Pulse/ RDY/ LDAC Register SPI 0/1 Byte Count Register SPI 2/3 Byte Count Register SPI 4/5 Byte Count Register SPI 6/7 Byte Count Register SPI 0/1/2/3 slave Select Register SPI 4/5/6/7 slave Select Register SPI Interrupt Status Register SPI Timeout Status Register SPI Pulse Overrun Status Register SPI Data Status Register SPI Channel 0 Data Register SPI Channel 1 Data Register SPI Channel 2 Data Register SPI Channel 3 Data Register SPI Channel 4 Data Register SPI Channel 5 Data Register SPI Channel 6 Data Register SPI Channel 7 Data Register SPI Data Status Mirror Register SPI Master Control Register Interrupt Configure Register Interrupt Status Register ESC State Override register Host interface Status Register Reserved Table 3-3: Function Register Map 33 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 3.3.3 Memory Map between ESC Memory and Function Registers Function Address 0x000 0x002 0x004 0x006 0x008 0x00A 0x00C 0x00E 0x010 0x012 0x014 0x016 0x018 0x01A 0x01C 0x020 0x022 0x024 0x026 0x028 0x02A 0x02C 0x02E 0x030 0x032 0x040 0x042 0x044 0x046 0x048 0x04A 0x04C 0x04E 0x050 0x060 0x062 0x064 0x066 0x068 0x06A 0x06C 0x06E 0x070 0x072 0x074 0x076 0x078 0x07A 0x07C 0x07E 0x080 0x082 ESC Address R/W RO 0x3000 0x3002 0x3004 0x3006 0x3008 0x300A 0x300C 0x300E 0x3010 0x3012 0x3014 0x3016 0x3018 0x301A 0x301C 0x3020 - 0x3024 0x3026 - 0x3028 - 0x302C 0x302E - - 0x3230 0x3040 - 0x3044 - - 0x3248 0x304C 0x304E - 0x3250 0x3060 - 0x3064 0x3066 - 0x3068 - 0x306C - 0x3070 - 0x3074 - 0x3078 - - 0x327C 0x3080 0x3082 - Name Description MCTLR PXCFGR PTAPPR PTBPPR PPCR PBBMR P1CTRLR P1SHR P1HPWR P2CTRLR P2SHR P2HPWR P3CTRLR P3SHR P3HPWR SGTLR SGTHR SHPWR TDLYR STNLR STNHR SCFGR SCTRLR SCNTLR SCNTHR ECNTVLR ECNTVHR ECNSTLR ECNSTHR ELATLR ELATHR EMODR ECLRR HALSTR WTLR WTHR WCFGR WTPVCR WMPLR WMPHR WMMLR WMMHR WOMLR WOMHR WOELR WOEHR WOPLR WOPHR WTPVLR WTPVHR SPICFGR SPIBRR Motor Control Register PWM Pulse X Configure Register PWM Trigger A Pulse Position Register PWM Trigger B Pulse Position Register PWM Period Cycle Register PWM Pulse Break Before Make Register PWM1Control Register PWM1 Counter Shift Register PWM1 High Pulse Width Register PWM2 Control Register PWM2 Shift Register PWM2 High Pulse Width Register PWM3 Control Register PWM3 Counter Shift Register PWM3 High Pulse Width Register Step Gap Time Low Register Step Gap Time High Register Step High Pulse Width Register direction Transform Delay step Register Step Target Number Low Word Register Step Target Number High Word Register Step Configure Register Step Control Register Step Counter Content Low Register Step Counter Content High Register Encoder Counter value Low Register Encoder Counter value High Register Encoder Constant Low Register Encoder Constant High Register Encoder Latched Low Register Encoder Latched High Register Encoder Mode Configuration Register Encoder Clear Register Hall State Register Watchdog Timer Low Register Watchdog Timer High Register Watchdog Configure Register Watchdog Timer Peak Value Clear Register Watchdog Monitored Polarity Low Register Watchdog Monitored Polarity High Register Watchdog Monitored Mask Low Register Watchdog Monitored Mask High Register Watchdog Output Mask Low Register Watchdog Output Mask High Register Watchdog Output Enable Low Register Watchdog Output Enable High Register Watchdog Output Polarity Low Register Watchdog Output Polarity High Register Watchdog Timer Peak Value Low Register Watchdog Timer Peak Value High Register SPI Configure Register SPI Baud Rate Register 34 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 0x084 0x086 0x088 0x08A 0x08C 0x090 0x092 0x094 0x096 0x098 0x09A 0x0A8 0x0AA 0x0AC 0x0AE 0x0B0 0x0B8 0x0C0 0x0C8 0x0D0 0x0D8 0x0E0 0x0E8 0x0F0 0x0F2 0x100 0x102 0x3084 0x3086 0x3088 0x308A 0x308C 0x3090 0x3092 0x3094 0x3096 0x3098 0x309A 0x30B0 0x30B8 0x30C0 0x30C8 0x30D0 0x30D8 0x30E0 0x30E8 0x30F2 0x3100 0x3102 0x32A8 0x32AA 0x32AC 0x32AE 0x32B0 0x32B8 0x32C0 0x32C8 0x32D0 0x32D8 0x32E0 0x32E8 0x32F0 - SPIDBSR SPIDTR SPIRPTR SPILTR SPIPRLR SPI01BCR SPI23BCR SPI45BCR SPI67BCR SPI03SSR SPI47SSR SPINTSR SPITSR SPIPOSR SPIDSR SPIC0DR SPIC1DR SPIC2DR SPIC3DR SPIC4DR SPIC5DR SPIC6DR SPIC7DR SPIDSMR SPIMCR INTCR INTSR SPI Delay Byte and SS Register SPI Delay Transfer Register SPI RDY / Pulse Time Register SPI LDAC Time Register SPI Pulse/ RDY/ LDAC Register SPI 0/1 Byte Count Register SPI 2/3 Byte Count Register SPI 4/5 Byte Count Register SPI 6/7 Byte Count Register SPI 0/1/2/3 slave Select Register SPI 4/5/6/7 slave Select Register SPI Interrupt Status Register SPI Timeout Status Register SPI Pulse Overrun Status Register SPI Data Status Register SPI Channel 0 Data Register SPI Channel 1 Data Register SPI Channel 2 Data Register SPI Channel 3 Data Register SPI Channel 4 Data Register SPI Channel 5 Data Register SPI Channel 6 Data Register SPI Channel 7 Data Register SPI Data Status Mirror Register SPI Master Control Register Interrupt Configure Register Interrupt Status Register Table 3-4: ESC Memory and Function Registers Mirror Mapping Table 35 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4 Electrical Specifications DC Characteristics 4.1.1 Absolute Maximum Ratings Symbol VCCK VCC3IO, VCC33A VCC12A_PLL VIN TSTG I IN I OUT Parameter Digital core power supply Power supply of 3.3V I/O and Ethernet PHY Analog power supply for PLL Input voltage of 3.3V I/O with 5V tolerant. Storage temperature. DC input current. Output short circuit current. Rating - 0.5 to 1.6 - 0.5 to 4.6 - 0.5 to 1.6 - 0.5 to 5.8 - 65 to 150 50 50 Units V V V V ℃ mA mA Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted in the recommended operating condition section of this datasheet. Exposure to absolute maximum rating condition for extended periods may affect device reliability. 4.1.2 Recommended Operating Condition Symbol VCC3IO VCC33A VCCK VCC12A_PLL Tj Ta Parameter Power supply of 3.3V I/O Analog power supply for Ethernet PHY Digital core power supply Analog power supply for PLL operating junction temperature Min 2.97 2.97 1.08 1.08 -40 Typ 3.3 3.3 1.2 1.2 25 Max 3.63 3.63 1.32 1.32 125 Units V V V V ℃ operating ambient temperature -40 - 105 ℃ 4.1.3 Leakage Current and Capacitance Symbol IIN CIN Parameter Input leakage current. No pull-up or pull-down. Input capacitance. Conditions Min 3.3V with 5V tolerant I/O pins. Vin = 5 or 0V. 3.3V with 5V tolerant I/O pins. - Typ Max Units < ±1 - μA 2.3 - pF 36 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4.1.4 DC Characteristics of 3.3V with 5V Tolerant I/O Pins Symbol Parameter VCC3IO Power supply of 3.3V I/O. Vil Input low voltage. Vih Input high voltage. Schmitt trigger negative going threshold Vtvoltage. Schmitt trigger positive going threshold Vt+ voltage Vol Output low voltage. Voh Output high voltage. Conditions 3.3V I/O LVTTL Min 2.97 2.0 Typ 3.3 - Max 3.63 0.8 - Units V V V 0.8 1.1 - V - 1.6 2.0 V LVTTL Iol = 4 ~ 8mA 0.4 V Ioh = 4 ~ 8mA 2.4 V With internal pullVCC3IO Vopu (1) Output pull-up voltage for 5V tolerant IO V up resistor – 0.9 Rpu Input pull-up resistance. 40 75 190 KΩ Rpd Input pull-down resistance. 40 75 190 KΩ Input leakage current. Vin = 5 or 0V ±1 μA Input leakage current with pull-up resistance. Vin = 0 V -45 μA Iin Input leakage current with pull-down Vin = VCC3IO 45 μA resistance. Note: This parameter indicates that the pull-up resistor for the 5V tolerant I/O pins cannot reach VCC3IO DC level even without DC loading current. 37 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Power Consumption Item Conditions VCCIO + VCC33A VCCK + VCC12A_PLL Units Power on, Unlinked (Typ.) 120 33 mA Digital IO INIT state, Linked (Typ.) 135 48 mA (32 I/O Output) OP state, Linked (Typ.) 160 50 mA Note: Above current value are typical values measured on AX58100 Test board. Table 4-1: AX58100 Power Consumption Symbol ΘJC ΘJA JT Description Thermal resistance of junction to case Thermal resistance of junction to ambient Junction to Top of the Package Characterization Parameter Condition Still air Min - Typ 16 28.3 Max - Unit °C/W °C/W - 1.49 - °C/W Table 4-2: Thermal Characteristics 38 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Power-On-Reset (POR) Specification Below figures and table show the two POR circuit spec during power ramp-up/down. Vrr Vfr VCCK POR Output Tdrop Trst Figure 4-1: Power On Reset (POR) Timing Diagram Symbol VCCK V V Description Power supply voltage to be detected Conditions - Min. 1.0 Typ. 1.2 Max. 1.32 Units V rr VCCK rise relax voltage - - 0.72 0.9 V fr VCCK fall release voltage - - 0.63 0.85 V 1.8 2.5 4.8 μs 0.2 0.4 0.9 μs Trst Tdrop VCCK slew rate = 1.0V / 1μs VCCK slew rate = 2.5V / 1μs Reset time after POR trigger up Drop time of VCCK to reset Table 4-3: Power On Reset (POR) Timing Table 39 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Power–up Sequence Trise3 3.3V VCC3IO/VCC33A 0V Trise2 T23 1.2V VCCK /VCC12A_PLL 0V Trst RSTn Tclk … XSCI Figure 4-2: Power-up Sequence Timing Diagram Symbol Parameter Conditions Min Trise3 3.3V power supply rise time. From 0V to 3.3V. Trise2 1.2V power supply rise time. From 0V to 1.2V. VCCK rising to 1.2V to VCC3IO T23 rising to 3.3V interval. From VCC3IO rising to 3.3V to Trst RSTn asserted low level interval. RSTn going high. From VCC3IO rising to 3.3V to Tclk 25MHz crystal oscillator start-up time. clock stable of 25MHz crystal oscillator. PDI operational after power good, without I2C EEPROM loading TStartup Startup time error Note: The above typical timing data is measured from AX58100 test board. Typ 400 200 Max Units us us 200 - us 40 - us - 60 ms - 70 ms Table 4-4: Power-up Sequence Timing Table 40 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller AC Timing Characteristics 4.5.1 I2C Timing Figure 4-3: Write access (1 address byte, up to 16 Kbit EEPROMs) Figure 4-4: Write access (2 address bytes, 32 Kbit - 4 Mbit EEPROMs) 41 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-5: Read access (1 address byte, up to 16 Kbit EEPROMs) Symbol Typical Up to 16 Kbit 32 Kbit-4 Mbit 6.72 (≈ 150 KHz) 250 310 Parameter TClk TWrite EEPROM clock period Write access time (without errors) TRead Read access time 2 words (without errors): configuration (8 Words) TDelay Time until configuration loading begins after Reset is gone Units us us 440 500 us 1.16 1.22 ms 65.5 Table 4-5: I2C EEPROM Timing Table 42 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. us AX58100 EtherCAT Slave Controller 4.5.2 Port 2 MII Timing Figure 4-6: Port 2 MII TX Timing Diagram Symbol TCLK25 TTX_delay TPHY_TX_CLK Description Min Typ Max Units - 40 - ns - - 2 ns - PHY dependent - ns - - ns - - ns MCLK output TX_EN/TXD[3:0] delay after rising edge of MCLK Delay between MCLK and TX_CLK output of the PHY TPHY_TX_setup PHY setup time TPHY_TX_hold PHY hold time PHY dependent PHY dependent Table 4-6: Port 2 MII TX Timing Table 43 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-7: Port 2 MII RX Timing Diagram Symbol TRX_CLK TRX_setup TRX_hold Description RX_CLK period (100 PPM with maximum FIFO Size only) RX_DV/RX_ER/RXD[3:0] valid before rising edge of RX_CLK RX_DV/RX_ER/RXD[3:0] valid after rising edge of RX_CLK Min Typ Max Units - 40 - ns 2.1 - - ns 0.5 - - ns Table 4-7: Port 2 MII RX Timing Table 44 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-8: MDC/MDIO Write access Figure 4-9: MDC/MDIO Read access Symbol TMDC TWrite TRead TMI_startup Description Min MDC period MI Write access time MI Read access time Time between reset end and the first access of MI Link detection and configuration Typ 400 (≈ 2.5 MHz) 25.6 25.4 1.34 Table 4-8: MDC/MDIO Timing Table 45 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. Max Units ns us us ms AX58100 EtherCAT Slave Controller 4.5.3 Distributed Clocks SYNC/LATCH Symbol TDC_LATCH TDC_SYNC_Jitter Description Min Time between LATCH 0/1 events SYNC 0/1 output jitter Typ Max 12 Table 4-9: DC SYNC/LATCH timing characteristics Figure 4-10: LATCH timing Figure 4-11: SYNC timing 46 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. 12 Units ns ns AX58100 EtherCAT Slave Controller 4.5.4 Digital I/O Timing Figure 4-12: Digital Input: Input data sampled at SOF, IO can be read in the same frame Figure 4-13: Digital Input: Input data sampled with LATCH_IN Figure 4-14: Digital Input: Input data sampled with SYNC0/1 47 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-15: Digital Output timing Symbol TDATA_setup TDATA_hold TLAT_IN TSOF TSOF_to_DATA_setup TSOF_to_DATA_hold Tinput_event_delay TOUTVLD TDATA_to_OUTVLD TWD_TRIG TDATA_to_WD_TRIG TDATA_to_EOF TDATA_to_SYNC TOE_EXT_to_DATA_invalid Toutput_event_delay TOUT_EXT_valid TOUT_EXT_invalid Description Min Typ Max Units Input data valid before LAT_IN Input data valid after LAT_IN LAT_IN high time SOF high time Input data valid after SOF, so that Inputs can be read in the same frame Input data invalid after SOF Time between consecutive input events OUTVLD high time Output data valid before OUTVLD WD_TRIG high time Output data valid after WD_TRIG Output data valid after EOF Output data valid after SYNC0/1 Outputs zero or Outputs hi-Z after OE_EXT set to low Time between consecutive output events OUT_EXT valid before OUTVLD OUT_EXT invalid after OUTVLD 5 2 4 - 40 - ns ns ns ns 0 - 1.2 us 1.6 440 79 - 80 40 - 20 20 20 us ns ns ns ns ns ns ns 0 - 9.5 ns 320 - 80 80 - ns ns ns Table 4-10: Digital I/O timing Table 48 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4.5.5 ESC PDI SPI Slave Timing Figure 4-16: Basic MOSI/MISO timing Symbol Description Min TSCLK SCLK frequency TSEL_to_CLK First SCLK cycle after SCS_ESC asserted SPI mode 0/2, SPI mode 1/3 5 Deassertion of SCS_ESC with normal data out sample after last SCLK cycle SPI mode 1/3 with late data out TCLK/2+ 5 sample Only for read access between address/command and first data byte. Can be ignored if BUSY or Wait State Bytes are 240 used. Delay between SPI accesses 40 MOSI valid before SCLK edge 3 MOSI valid after SCLK edge 0 MISO valid after SCLK edge MISO invalid after SCLK edge 0 Internal delay between AL event and SINT output to enable correct reading of the interrupt registers. TCLK_to_SEL Tread Taccess_delay TMOSI_setup TMOSI_hold TSCLK_to_MISO_valid TSCLK_to_MISO_invalid TIRQ_delay Typ Max Units - - ns - - ns - - ns - - ns - 10.5 - ns ns ns ns ns 180 - ns 21 (≤47MHz) 5 Table 4-11: PDI SPI Slave Timing Table 49 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-17: PDI SPI Slave read access (2 byte addressing, 1 byte read data) with Wait State byte 50 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-18: PDI SPI Slave read access (2 byte addressing, 2 byte read data) with Wait State byte 51 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-19: PDI SPI Slave write access (2 byte addressing, 1 byte write data) 52 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-20: PDI SPI Slave write access (3 byte addressing, 1 byte write data) 53 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4.5.6 Function SPI Slave Timing Figure 4-21: Function SPI Slave with share pin Timing Diagram Symbol TSCLK TDO TSU THD TCSSP TDHD TCSHD TGN Description SCLK clock frequency MISO data valid time after SCLK edge MOSI data setup time before SCLK edge MOSI data hold time after SCLK edge SCS setup time before MISO active SCS hold time after SCLK edge MISO data hold time after SCS de-assert SCS negation to next SCS assertion time Min Typ Max Units 9.2 2 2 7.6 21 2.6 40 - 50 - MHz ns ns ns ns ns ns ns Min Typ Max Units 10.5 2 2 7.7 21 2.5 40 - 47.5 - MHz ns ns ns ns ns ns ns Table 4-12: Function SPI with share pin Timing Table Figure 4-22: Function SPI Slave with individual pin Timing Diagram Symbol TSCLK TDO TSU THD TCSSP TDHD TCSHD TGN Description SCLK clock frequency MISO data valid time after SCLK edge MOSI data setup time before SCLK edge MOSI data hold time after SCLK edge SCS setup time before MISO active SCS hold time after SCLK edge MISO data hold time after SCS de-assert SCS negation to next SCS assertion time Table 4-13: Function SPI with individual pin Timing Table 54 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4.5.7 ESC PDI Local Bus Timing Figure 4-23: PDI Local Bus Read access (without preceding write access) Figure 4-24: PDI Local Bus Write access (write after rising edge LWRn, without preceding write access) 55 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-25: PDI Local Bus Sequence of two write accesses and a read access Note: The first write access to ADR1 is performed after the first rising edge of WR. After that, the ESC is internally busy writing to ADR1. After CS is deasserted, BUSY is not driven any more, nevertheless, the ESC is still writing to ADR1. Hence, the second write access to ADR2 is delayed because the write access to ADR1 has to be completed first. So, the second rising edge of WR must not occur before BUSY is gone. After the second rising edge of WR, the ESC is busy writing to ADR2. This is reflected with the BUSY signal as long as CS is asserted. The third access in this example is a read access. The ESC is still busy writing to ADR2 while the falling edge of RD occurs. In this case, the write access to ADR2 is finished first, and afterwards, the read access to ADR3 is performed. The ESC signals BUSY during both write and read access Figure 4-26: PDI Local Bus Write access (write after falling edge LWRn 56 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Symbol Description TCS_to_BUSY TADR_BHE_setup TRD_to_DATA_driven TRD_to_BUSY Tread Tread_int Tprec_write TBUSY_to_DATA_valid TADR_BHE_to_DATA_invali Min Typ Max BUSY driven and valid after CS 45 assertion ADR and BHE valid before RD 0 assertion DATA bus driven after RD assertion 0 BUSY asserted after RD assertion 0 10 External read time (RD assertion to BUSY deassertion) with normal read busy output (0x0152[0]). Additional 20 ns if delayed read busy output is configured. without preceding write access or TWR_to_RD ≥ Tprec_write + TColl or Tread_int configuration: write after falling edge of WR Tread_int + Tprec_write + with preceding write access and TColl TWR_to_RD < Tprec_write + TColl TWR_to_RD 8-bit access, absolute worst case with preceding write access 420 (TWR_to_RD=min, Tprec_write =max, TColl=max) 16-bit access, absolute worst case with preceding write access 560 (TWR_to_RD=min, Tprec_write =max, TColl=max) Internal read 8-bit access 220 time 16-bit access 300 Time for 8-bit access 180 preceding write 16-bit access 260 access DATA bus valid normal read busy 5 after device output BUSY is delayed read busy -15 deasserted output DATA invalid after ADR or BHE change 0 Units ns ns ns ns ns ns ns ns - - ns - 7.5 ns - 8.5 ns - - ns - - ns - - ns - - ns - - ns - - ns - 12 ns - Twrite_int d TCS_RD_to_DATA_release TCS_to_BUSY_release TCS_delay TRD_delay TADR_BHE_DATA_setup TADR_BHE_DATA_hold TWR_active TBUSY_to_WR_CS TWR_to_BUSY Twrite DATA bus released after CS deassertion 2.5 or RD deassertion BUSY released after CS deassertion 2.5 Delay between CS deassertion an 5 assertion Delay between RD deassertion 5 and assertion ADR, BHE and Write DATA valid 6.5 before WR deassertion ADR, BHE and Write DATA valid after 2 WR deassertion WR assertion time 8.5 WR or CS deassertion after BUSY 0 deassertion BUSY assertion after WR deassertion External write time (WR assertion to BUSY deassertion) Configuration: write after falling edge of 0 WR (act. low) 57 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. ns AX58100 EtherCAT Slave Controller Twrite_int TWR_delay TColl TWR_to_RD TCS_WR_overlap TCS_RD_overlap TIRQ_delay with preceding write access and TWR_delay < Twrite_int (Write after rising edge -of WR) without preceding write access or TWR_delay ≥ Twrite_int (Write after rising edge of WR) 8-bit access, absolute worst case with preceding write access (TWR_delay= min, TWR_int=max, Write after rising edge of WR) 16-bit access, absolute worst case with preceding write access (TWR_delay=min, TWR_int=max, Write after rising edge of WR) Internal write 8-bit access time 16-bit access Delay between WR deassertion and assertion RD access directly follows WR access with the same address Extra read delay (8-bit accesses or 8-bit WR and 16-bit RD) different addresses or 16-bit accesses Delay between WR deassertion and RD assertion Time both CS and WR have to be deasserted simultaneously (only if CS is deasserted at all) Time both CS and RD have to be deasserted simultaneously (only if CS is deasserted at all) Internal delay between AL event and LINT output to enable correct reading of the interrupt registers. - Twrite_int TWR_delay - 0 ns - 180 - 260 - - 180 260 ns 5 - - ns - - 20 ns 0 0 - - ns 5 - - ns 5 - - ns - 180 - ns Table 4-14: PDI Local Bus Timing Table 58 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4.5.8 Function Local Bus Timing Figure 4-27: Function Local Bus Signal Read Access Figure 4-28: Function Local Bus Write Access (Late Sample = 0) 59 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-29: Function Local Bus Write Access (Late Sample = 1) Symbol TCS TCS2RD TCS2WR TRD2CS TWR2CS TAS TAH TA2D TRD TRD2D TWR TWR2RDY TWR2WR TDS_NOR TDH_NOR TDS_LAT TDH_LAT Description LFCSn back to back LFCSn to LRDn LFCSn to LWR, LRDn to LFCSn LWRn to LFCSn LA setup time LA hold time LA change to LDA valid LRDn pulse LRDn to LRDY LWRn pulse LWRn assert to LRDY assert LWRn back to back (late sample) LDA setup time LDA hold time LDA setup time with Late Sample LDA hold time with Late Sample Min Typ Max Units 30 0 0 0 0 0 0 - - 40 80 60 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TRD2D 30 100 0 40 10 10 Table 4-15: Function Local Bus Access Timing 60 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4.5.9 PWM Motor Controller Timing Figure 4-30: PWMx Timing Symbol Description TPPC PWM Period Cycle TPxHP PWM x High pulse Width set by PxHPWR TPxLP PWM x Low pulse Width set by PxHPWR Pulse width for PULZ, PULC, PULA, PULB, and PULAB PWM Trigger Pulse A Position in PWM Period TPAPP Cycle PWM Trigger Pulse B Position in PWM Period TPBPP Cycle Note *1: “x” = 1 ~ 3 TPXHPW EN8X Min Typ Max Units x1 x8 x1 x8 x1 x8 x1 x8 x1 x8 x1 x8 - PPC * 10 PPC * 80 PxHPV * 10*1 PxHPV * 80*1 PxHPV * 10*1 PxHPV * 80*1 PXHPW * 10 PXHPW * 80 PTAPP * 10 PTAPP * 80 PTBPP * 10 PTBPP * 80 - ns ns ns ns ns ns ns ns ns ns ns ns Table 4-16: PWMx Timing Table 61 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-31: Only PWM Channel 2 Shift Diagram Symbol Description TP1SHT PWM pulse was postponed raising time (addition with P1SHR) and the pulse width stays the same TP2SHT Please reference TP1SHT content TP3SHT Please reference TP1SHT content EN8X Min x1 - Typ Max Units P1SHIFT * 10 - ns x8 - P1SHIFT * 80 - ns x1 x8 x1 x8 - P2SHIFT * 10 P2SHIFT * 80 P3SHIFT * 10 P3SHIFT * 80 - ns ns ns ns Table 4-17: PWMx Shift Timing Table 62 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Figure 4-32: BBM (Break Before Make) Timing Diagram Symbol TBBMH TBBML EN8X x1 x8 x1 x8 Description High pulse was postponed raising and reduce pulse width Low pulse was postponed falling and addition pulse width Min Typ Max Units - PBBMH * 10 PBBMH * 80 PBBML * 10 PBBML * 80 - ns ns ns ns Table 4-18: PWMx BBM Timing Table Figure 4-33: One Shot with multi Step Timing Diagram Symbol TSGT Description Step Pulse to Pulse Gap time set by SGTLR and SGTHR Step Pulse Width set by SHPWR TSPW TSPDY Note: Step frequency = 1/ (TSPW +TSGT) Direction Transform Delay Time set by TDLYR Min Typ Max Units - SGT * 10 - ns - SPW * 10 - ns - SPDT * 10 - ns Table 4-19: Step function timing table 63 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4.5.10 Incremental and Hall Encoder Interface Timing Figure 4-34: ABZ Timing Diagram Figure 4-35: CW/CCW Timing Diagram Figure 4-36: CLK/DIR Timing Diagram Figure 4-37: Hall Timing Diagram 64 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Symbol TSK TZ TCWH TCWL TCCWH TCCWL TCLKH TCLKL TC2D TD2C THK Description AB state keep time Z Pulse Width CW high time CW low time CCW high time CCW low time CLK high time CLK low time CLK to DIR time DIR to CLK time Hall state keeps time Min Typ Max Units 30 30 30 30 30 30 30 30 30 30 60 - - ns ns ns ns ns ns ns ns ns ns ns Table 4-20: Incremental and Hall Encoder Timing Table 65 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4.5.11 SPI Master Timing MSS[x] TDBS1 TDBS2 TDBS3 TDT1 TSCLKH MSCLK TSCLKL 8bits 8bits Figure 4-38: SPI Master Timing MSCLK MMISO normal mode TMISET TMIHD MMISO TMISET TMIHD MMOSI TMODLY Figure 4-39: MMISO /MMOSIO Timing 66 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller MSS[x] TRT MDRLD (RDY_pol = 0) Figure 4-40: SPI MDRLD Ready Timeout Timing MSS[x] TPT MINT MTRG (Pulse_pol = 0) Figure 4-41: SPI MTRG Trigger Pulse Timeout MSS[x] TLDACG MDRLD (LDAC_pol = 0) TLDACW Figure 4-42: SPI MDRLD Trigger LDAC Gap and Width Timing 67 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Symbol Description Min Typ - TSCLKH + TSCLKL 5 * Divide 5 * Divide Max Units Clock TSCLK MSCLK Period TSCLKH TSCLKL MSCLK high MSCLK low ns ns TDBS1 Bus Timing MSS[x] to MSCLK (Mode0/1 without DBS1K) MSS[x] to MSCLK (Mode2/3 without DBS1K) MSS[x] to MSCLK (Mode0/1 with DBS1K) MSS[x] to MSCLK (Mode2/3 with DBS1K) ns - Byte to byte (Mode0/1 without DBS1K) Byte to byte (Mode2/3 without DBS1K) TDBS2 Byte to byte (Mode0/1 with DBS1K) Byte to byte (Mode2/3 with DBS1K) MSCLK to MSS[x] (Mode0/1 without DBS1K) MSCLK to MSS[x] (Mode2/3 without DBS1K) TDBS3 MSCLK to MSS[x] (Mode0/1 with DBS1K) MSCLK to MSS[x] (Mode2/3 with DBS1K) TMISET TMIHD TMODLY TRT TPT MSS[x] gap (without DT1K) MSS[x] gap (with DT1K) MMISO setup time MMISO hold time MMOSI output delay MDRLD ready timeout (RDY mode) MTRG timeout TLDACG MDRLD Gap (LDAC mode) TLDACW MDRLD Width (LDAC mode) TDT1 - ns - ns ns (DBS + 1) * Tsclk (DBS + 0.5) * Tsclk ((1024 * (DBS + 1)) + 1) * Tsclk ((1024 * (DBS + 1)) + 0.5) * Tsclk (DBS + 0.5) * Tsclk (DBS + 0.5) * Tsclk ((1024 * (DBS + 1)) + 0.5) * Tsclk ((1024 * (DBS + 1)) + 0.5) * Tsclk (DBS + 0.5) * Tsclk (DBS + 1.0) * Tsclk ((1024 * (DBS + 1)) + 0.5) * Tsclk ((1024 * (DBS + 1)) + 1.0) * Tsclk (DT + 2) * Tsclk (1024 * (DT + 1) + 2) * Tsclk 10.5 0 0.5 (1 + SPIRPT) * 1024 * Tsclk (1 + SPIRPT) * 1024 * Tsclk ((LDACG1K * 1023) + 1) * (LDGAP + 1) * Tsclk (LDACG1K * 1023 + 1) * (LDWID + 1) * Tsclk Table 4-21: SPI Master Timing Table 68 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AX58100 EtherCAT Slave Controller 4.5.12 RSTO, EEPROM and EEP_DONE Timing VCCK Vrr TRSTO RSTO Note: RSTO active low for example TRST2EEP I2C TEEP_LOAD TEEP_DONE EEP_DONE Figure 4-43: Power up to RSTO, EEPROM and EEP_DONE Timing RSTn TRSTi TRSTO RSTO Note: RSTO active low for example I2C TRST2EEP TEEP_DONE EEP_DONE Figure 4-44: RSTn to RSTO, EEPROM and EEP_DONE Timing 69 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. TEEP_LOAD AX58100 EtherCAT Slave Controller RSTn TRSTO RSTO Note: RSTO active low for example TRST2EEP I2C TEEP_LOAD TEEP_DONE EEP_DONE Figure 4-45: Register Reset to RSTO, EEPROM and EEP_DONE Timing Symbol TRSTO TRSTi TRST2EEP TEEP_LOAD TEEP_DONE Description The period of chip internal reset counter RSTn asserted to RSTO active RSTn de-asserted to start EEPROM Loading EEPROM loading period (Checksum Matched) RSTn de-asserted to EEP_DONE active Min Typ Max Units - 63 0 61.5 1.5 63 - ms ns ms ms ms Table 4-22: RSTO, EEPROM and EEP_DONE timing table 70 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 5 Package Information 71 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 6 Ordering Information Part Number AX58100 LT Description 80-pin LQFP lead Free package, Industrial temperature range: -40 to 105°C. 7 Revision History Revision V0.20 V0.30 V1.00 V1.01 V1.02 V1.03 V1.04 V1.05 Date Comments 2018/06/11 Preliminary release. 2018/07/27 1. Changed the pin name, type and descriptions of pin #56 in Section 1.3, 1.4. 2. Removed the “VCC33D” descriptions in Section 14. 3. Modified some descriptions in Section 2.1, 3.2.1, 9.2, 9.4.1. 4. Updated Figure 0-1. 2018/09/26 1. Changed some pin definitions in Section 1.4. 2. Added a new bootstrap pin definition in Section 3.1. 3. Modified some EEPROM layout and bit definitions in Section 3.2. 4. Changed the default value of EEPROM word offset 0x41 to 0x0021. 5. Modified some ESC Memory Map and Function Registers Map definitions in Section 3.3. 6. Updated some timing spec. and waveforms in Section 4. 7. Modified some descriptions in Features and Section 1.1, 2. 8. Updated Figure 1-1, 1-2. 2018/10/05 1. Modified some descriptions in Section 1.1, 2.4, 3, 5. 2. Corrected a typo in Figure 1-2. 2018/11/07 1. Modified a typo in Section 6. 2019/02/20 1. Modified some information in Section 4.2. 2. Updated some description in Section 5. 2019/09/11 Corrected some typos and modified some descriptions 2020/05/19 1. Updated power consumption value in section 4.2 2. Added section 4.5.12 for RSTO, EEPROM and EEP_DONE timing 3. Added some description for EEP_DONE in section 1.4.1 4. Updated Digital IO Timing in section 4.5.4 72 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller 4F, No. 8, Hsin Ann Rd., HsinChu Science Park, HsinChu, Taiwan, R.O.C. TEL: 886-3-5799500 FAX: 886-3-5799558 Email: support@asix.com.tw Web: http://www.asix.com.tw 73 Copyright © 2018-2020 ASIX Electronics Corporation. All rights reserved.