AT24C1024B

Features • Low-voltage Operation – 1.8V (VCC = 1.8V to 3.6V) – 2.5V (VCC = 2.5V to 5.5V) Internally Organized 131,072 x 8 Two-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 400 kHz (1.8V) and 1 MHz (5V, 2.5V) Clock Rate Write Protect Pin for Hardware and Software Data Protection 256-byte Page Write Mode (Partial Page Writes Allowed) Random and Sequential Read Modes Self-timed Write Cycle (5 ms Typical) High Reliability – Endurance: 1,000,000 Write Cycles/Page – Data Retention: 40 Years 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead Ultra Thin Small Array (SAP), and 8-ball dBGA2 Packages Die Sales: Wafer Form, Tape and Reel and Bumped Die • • • • • • • • • • Two-wire Serial EEPROM 1M (131,072 x 8) • • Description The AT24C1024B provides 1,048,576 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to four devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions. 8-lead PDIP 8-lead SOIC NC A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA AT24C1024B with Two Device Address Inputs NC A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead TSSOP NC A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead dBGA2 VCC WP SCL SDA 8 7 6 5 1 2 3 4 NC A1 A2 GND 8-lead Ultra-Thin SAP VCC WP SCL SDA 8 7 6 5 1 2 3 4 Bottom View NC A1 A2 GND Rev. 5194F–SEEPR–1/08 Bottom View Table 0-1. Pin Name A1 A2 SDA SCL WP NC Pin Configurations Function Address Input Address Input Serial Data Serial Clock Input Write Protect No Connect 1. Absolute Maximum Ratings* Operating Temperature..................................–55°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Figure 1-1. Block Diagram VCC GND WP SCL SDA START STOP LOGIC LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W COMP SERIAL CONTROL LOGIC EN H.V. PUMP/TIMING DATA RECOVERY INC X DEC LOAD DATA WORD ADDR/COUNTER EEPROM Y DEC SERIAL MUX DIN DOUT DOUT/ACK LOGIC 2. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/ADDRESSES (A1/A2): The A1, A2 pin is a device address input that can be hardwired or left not connected for hardware compatibility with other AT24Cxx devices. When the A1, A2 pins are hardwired, as many as four 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the A1/A2 pins are left floating, the A1/A2 pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is 3 pF, Atmel recommends connecting the A1/A2 pin to GND. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected high to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is 3 pF, Atmel recommends connecting the pin to GND. Switching WP to VCC prior to a write operation creates a software write-protect function. 3 5194F–SEEPR–1/08 3. Memory Organization AT24C1024B, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of 256 bytes each. Random word addressing requires a 17-bit data word address. Table 3-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A1, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V Table 3-2. DC Characteristics Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol VCC1 VCC2 ICC ICC ISB1 ISB2 ILI ILO VIL VIH VOL1 VOL2 Note: Parameter Supply Voltage Supply Voltage Supply Current Supply Current Standby Current VCC = 5.0V VCC = 5.0V VCC = 1.8V VCC = 3.6V VCC = 2.5V VCC = 5.5V VIN = VCC or VSS VOUT = VCC or VSS –0.6 VCC x 0.7 VCC = 1.8V VCC = 3.0V IOL = 0.15 mA IOL = 2.1 mA READ at 400 kHz WRITE at 400 kHz VIN = VCC or VSS VIN = VCC or VSS 0.10 0.05 Test Condition Min 1.8 2.5 Typ Max 3.6 5.5 2.0 3.0 1.0 3.0 2.0 6.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.2 0.4 Units V V mA mA µA µA µA µA µA µA V V V V Standby Current Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level (1) Output Low Level Output Low Level 1. VIL min and VIH max are reference only and are not tested. Table 3-3. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 1.8-volt Symbol fSCL tLOW tHIGH Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High 1.3 0.6 Min Max 400 0.4 0.4 2.5, 5.0-volt Min Max 1000 Units kHz µs µs 4 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Table 3-3. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 1.8-volt Symbol ti tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Notes: Parameter Noise Suppression Time(1) Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time (1) 2.5, 5.0-volt Min Max 50 0.05 0.5 0.25 0.25 0 100 0.55 Units ns µs µs µs µs µs ns 0.3 100 0.25 50 5 1,000,000 5 µs ns µs ns ms Write Cycles Min Max 100 0.05 1.3 0.6 0.6 0 100 0.9 0.3 300 0.6 50 Inputs Fall Time(1) Stop Set-up Time Data Out Hold Time Write Cycle Time 25°C, Page Mode, 3.3V 1. This parameter is ensured by characterization only. 2. AC measurement conditions: RL (connects to VCC): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 50 ns Input and output timing reference voltages: 0.5 VCC 4. Device Operation CLOCK and DATA TRANSITIONS: T he SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4-4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below. 5 5194F–SEEPR–1/08 START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 4-5 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the Stop command will place the EEPROM in a standby power mode (see Figure 4-5 on page 8). ACKNOWLEDGE: A ll addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C1024B features a low-power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Figure 4-1. Software Reset Start bit Dummy Clock Cycles Start bit Stop bit SCL 1 2 3 8 9 SDA Figure 4-2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O®) tF tHIGH tLOW tR SCL tSU.STA tHD.STA tLOW tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT 6 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Figure 4-3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O) SCL SDA 8th BIT ACK WORDn twr STOP CONDITION Note: (1) START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4-4. Data Validity SDA SCL DATA STABLE DATA CHANGE DATA STABLE 7 5194F–SEEPR–1/08 Figure 4-5. Start and Stop Definition SDA SCL START STOP Figure 4-6. Output Acknowledge SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE 5. Device Addressing The 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7-1 on page 11). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices. The 1024K uses the two device address bit, A1, A2, to allow up to four devices on the same bus. These A1, A2 bits must compare to the corresponding hardwired input pins. The A1, A2 pin uses an internal proprietary circuit that biases it to a logic low condition if the pin is allowed to float. The seventh bit (P0) of the device address is a memory page address bit. This memory page address bit is the most significant bit of the data word address that follows. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. 8 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B DATA SECURITY: The AT24C1024B has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at VCC. 6. Write Operations BYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address. The word address field consists of the P0 bit of the device address, then the most significant word address followed by the least significant word address (see Figure 7-2 on page 11) A write operation requires the P0 bit and two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, TWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 7-2 on page 11). PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 7-3 on page 11). The data word address lower 8 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “rollover” during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: O nce the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue. 7. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: T he internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover” during read is from the last byte of the last memory page, to the first byte of the first page. 9 5194F–SEEPR–1/08 Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 7-4 on page 11). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 7-5 on page 12). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop condition (see Figure 7-6 on page 12). 10 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Figure 7-1. Device Address A2 0 Figure 7-2. Byte Write MOST SIGNIFICANT LEAST SIGNIFICANT P 0 Figure 7-3. Page Write MOST SIGNIFICANT LEAST SIGNIFICANT P 0 Figure 7-4. Current Address Read 11 5194F–SEEPR–1/08 Figure 7-5. Random Read High Byte ADDRESS Low Byte ADDRESS P 0 Figure 7-6. Sequential Read High Byte ADDRESS Low Byte ADDRESS Data n + 1 Data n + 2 Data n + X P 0 12 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B Ordering Information Ordering Code AT24C1024B-PU (Bulk form only) AT24C1024B-PU25 (Bulk form only) AT24C1024BN-SH-B(1) (NiPdAu Lead Finish) AT24C1024BN-SH-T(2) (NiPdAu Lead Finish) AT24C1024BN-SH25-B AT24C1024BN-SH25-T (1) Voltage 1.8 2.5 1.8 1.8 2.5 2.5 1.8 1.8 2.5 2.5 1.8 1.8 2.5 2.5 1.8 2.5 1.8 1.8 Package 8P3 8P3 8S1 8S1 8S1 8S1 8S2 8S2 8S2 8S2 8A2 8A2 8A2 8A2 8Y7 8Y7 8U4-1 Die Sale Operation Range (NiPdAu Lead Finish) (NiPdAu Lead Finish) (2) AT24C1024BW-SH-B(1) (NiPdAu Lead Finish) AT24C1024BW-SH-T(2) (NiPdAu Lead Finish) AT24C1024BW-SH25-B(1) (NiPdAu Lead Finish) AT24C1024BW-SH25-T AT24C1024B-TH-T (2) (2) (NiPdAu Lead Finish) Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) AT24C1024B-TH-B(1) (NiPdAu Lead Finish) (NiPdAu Lead Finish) (1) AT24C1024B-TH25-B AT24C1024B-TH25-T (NiPdAu Lead Finish) (NiPdAu Lead Finish) (2) AT24C1024BY7-YH-T(2) (NiPdAu Lead Finish) AT24C1024BY7-YH25-T(2) (NiPdAu Lead Finish) AT24C1024BU4-UU-T AT24C1024B-W-11 (3) (2) Industrial Temperature (–40°C to 85°C) Notes: 1. “-B” denotes bulk 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel. 3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type 8P3 8S1 8S2 8A2 8Y7 8U4-1 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.200” Wide Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) 8-ball, die Ball Grid Array Package (dBGA2) Options –1.8 –2.5 Low-voltage (1.8V to 3.6V) Low-voltage (2.5V to 5.5V) 13 5194F–SEEPR–1/08 8. Part marking scheme 8.1 8-SOIC(1.8V) Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark TOP MARK | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 2 G B 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 8.2 8-SOIC(2.5V) Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark TOP MARK | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 2 G B 2 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 14 AT24C1024B 5194F–SEEPR–1/08 AT24C1024B 8.3 8-TSSOP(1.8V) Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 2 G B 1 |---|---|---|---|---| BOTTOM MARK |---|---|---|---|---|---|---| P H |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| 2GBU PYMTC |