AT90SCR100H-Z1R

General Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 132 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 16MIPS Throughput at 16Mhz – On-chip 2-cycle Multiplier Non-volatile Program and Data Memories – 64K Bytes of In-System Self-Programmable Flash • Endurance: 10,000 Write/Erase Cycles – 4K Bytes EEPROM • Contains 128 Bytes of One Time Programmable Memory • Endurance: 100,000 Write/Erase Cycles – 4K Bytes Internal SRAM – Optional Boot Code Section • In-System Programming by On-chip Bootloader program JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Locks Bits through JTAG Interface – Locking JTAG for Software Security (using OTP programmation) ISO7816 UART Interface Fully compliant with EMV, GIE-CB and WHQL Standards – Programmable ISO clock from 1 Mhz to 4.8, 6, 8 or 12Mhz – Card insertion/removal detection with automatic deactivation sequence – Programmable Baud Rate Generator from 372 to 3 clock cycles – Synchronous/Asynchronous Protocols T=0 and T=1 with Direct or Inverse Convention – Automatic character repetition on parity errors – 32 Bit Waiting Time Counter – 16 Bit Guard Time Counter/Block Guard Time Counter – Internal Step Up/Down Converter with Programmable Voltage Output if DC/DC embedded: • Class A: 5V +/-8% at 60mA, Vcc>2.85 (50mA if Vcc >2.7) • Class B: 3V +/-8% at 60mA, Vcc>2.85 (50mA if Vcc >2.7) • Class C: 1.8V +/-8% at 35mA – ISO7816-12 USB Host controller for card interface • Supports up to 60mA USB Smart Cards • Supports limited cable length to Smart Card Connector (~50cm) – 4 kV ESD (MIL/STD 833 Class 3) protection on whole Smart Card Interface USB 2.0 Full-speed Device Module – Complies fully with: • Universal Serial Bus Specification Rev 2.0 – Supports data transfer rates up to 12 Mbit/s – Endpoint 0 for Control Transfers : up to 64-bytes – 8 Programmable Endpoints with IN or OUT Directions and with Bulk, Interrupt or Isochronous Transfers • 3 Programmable Endpoints with double buffering of 64x2 bytes – Suspend/Resume Interrupts, and Remote Wake-up Support – Power-on Reset and USB Bus Reset • 8-bit Microcontroller for Smart Card Readers • AT90SCR100 Datasheet Preliminary • • TPR0327AY–SMS–30Jan09 • • • • • • • • • • • – 48 Mhz clock for Full-speed Bus Operation – USB Bus Disconnection on Microcontroller Request Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler, Compare Mode and PWM Channel – One 8-bit Timer/Counter with Separate Prescaler, Compare Mode and Real Time Counter on Separate Oscillator – One 16-bit Timer/Counter with Separate Prescaler and Compare Mode – Hardware Watchdog – Hardware AES 128/256 Engine – Random Number Generator (RNG) Communication Peripherals – High Speed Master/Slave SPI Serial Interface (Up to 20Mhz) – 2-Wire Serial Interface – USART interface (up to 2Mbps) – Standard SPI Interface (to ease the communication with most RF front end chips) Special Microcontroller Feature – Power-on Reset and Brown-out Detection – Internal Callibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, Power-save, Power-down, Standby and Extended Standby – Supply Monitoring with Interrupt Generation below a fixed level. Keyboard Interface with up to 5x4 Matrix Management Capability with Interrupts and Wake-Up on Key Pressed Event Up to 4 x I/O Ports: Programmable I/O Port Up to 4 x LED Outputs with Programmable Current Sources: 2 or 4 mA (not usable in emulation mode) Specific and Unique Serial Number per IC in production. Operating Temperature – Industrial (-40°C to +85°C) Core Operating Voltages – 2.4 - 5.5V DC/DC Operating Voltages (See “Smart Card Interface Characteristics” for details) – 2.7 - 5.5V Maximum Frequency – 8MHz Clock Input 2 AT90SCR100 TPR0327AY–SMS–30Jan09 AT90SCR100 1. Block Diagram Figure 1-1. Block Diagram CP CCRES L CR K ST CI O CC 4 CC , D 8, P DM Vc c PA7, KbIN7, PCINT7 PA6, KbIN6, PCINT6 PA5, KbIN5, PCINT5 PA4, KbIN4, PCINT4 PA3, KbIN3, PCINT3 PA2, KbIN2, PCINT2 PA1, KbIN1, PCINT1 PA0, KbIN0, PCINT0 PE7, KbO7, PCINT31 PE6, KbO6, PCINT30 PE5, KbO5, PCINT29 PE4, KbO4, PCINT28 PE3, KbO3, PCINT27 PE2, KbO2, PCINT26 PE1, KbO1, PCINT25 PE0, KbO0, PCINT24 PC5, JTGTDI, LED3 PC4, JTGTDO, LED2 PC3, JTGTMS, LED1 PC2, JTGTCK, LED0 PC1, SDA, INT3b PC0, SCL, INT2b Smart Card Interface PORT A Standard ISO7816 USB Host Controller Supply Monitor Keyboard Interface USB DMA PORT E On-chip Debug Watchdog JTAG cpu Interrupt Controller Power Management PORT C LED port TWI SPI DMA PD7, HSMISO, PCINT23 PD6, HSMOSI, PCINT22 PD5, HSSCK, PCINT21 PD4, HSSS, PCINT20 PD3, INT1, PCINT19 PD2, INT0, OC1B, PCINT18 PD1, TXD, PCINT17 PD0, RXD, PCINT16 PB7, SCK, OC2A, PCINT15 PB6, MISO, OC2B, PCINT14 PB5, MOSI, OC1A, PCINT13 PB4, SS, OC0B, PCINT12 PB3, PWM, OC0A, PCINT11 PB2, ICP1, PCINT10 PB1, T1, CKO, PCINT9 PB0, T0, XCK, PCINT8 PORT D High-Speed SPI SRAM 4 KB USART FLASH 64 KB Code EEPROM 4 KB Data SPI PORT B AES 256 RNG USB 8bit T/C 0 16bit T/C 1 Timers/Counters 8bit T/C 2 48MHz PWM RTC Clock Management USB device TO TO Note Except for the PORTC, all the other ports are connected to a Pin Change Interrupt Controller. D UC ap SC D+ 1 SC 2 AL XT 1 AL XT 2 3 TPR0327AY–SMS–30Jan09 4 AT90SCR100 TPR0327AY–SMS–30Jan09 AT90SCR100 2. Pin List Configuration • 2 package configurations to answer different needs – 32pins: LowPinCount package: for small package size, useful for small embedded systems (AT90SCR100L and AT90SCR100LS) – 64pins: FullPinCount: For full performance advanced reader (AT90SCR100H) ! Caution On Full Pin Count (FPC) package, the only supported package type is QFN, and all the Vss signals are connected to the e-pad. It is important to have it fully soldered on groundplane of final PCB. • USBReg refers to 3.3V USB specific regulator Note • PCINTx refer to Pin Change Interrupts. See “External Interrupt Registers” on page 69. Beware of the multiple functionality supported on each port. All functionnality may be active at the same time. The only way to disable a feature is to deactive it inside the corresponding peripheral block. ! Caution Table 2-1. Portmap Pin List Configuration SCR100LHS SCR100LSD SCR100H Supply ID Vcc Vss1 AVss RST Unmapped, generic pins Xtal1 Xtal2 DVcc Vcc2 Vcc3 Vcc4 Vcc5 Vdcdc Vss2 Vss3 D+ DUCap Configuration, Role x e(1) e(1) x x Vcc x x x x x x x e(1) e(1) x x x USB Reg Vcc Vss1 AVss RST XTAL1 XTAL2 DVcc Vcc2 Vcc3 Vcc4 Vcc5 Vdcdc Vss2 Vss3 D+ DUCap USB Decoupling: Used for specific USB regulator decoupling Digital Vcc:Used for internal regulator decoupling Voltage Supply: To be tied to same supply voltage as Vcc Voltage Supply: To be tied to same supply voltage as Vcc Voltage Supply: To be tied to same supply voltage as Vcc Voltage Supply: To be tied to same supply voltage as Vcc Voltage Supply for DC/DC Converter. Second Vss: To be tied to Vss Third Vss: To be tied to Vss Voltage Supply Ground PLL Ground Reset signal: Drive low to reinitialize the chip Clock Input: Support up to 8 Mhz crystals x x x x x x x x x x x x x x x x x x x x x x x x x x x x USB Interface 5 TPR0327AY–SMS–30Jan09 Table 2-1. Portmap Pin List Configuration SCR100LHS SCR100LSD SCR100H Supply ID RTC1 RTC2 PA7 PA6 PA5 PORT A PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PORT B PB4 PB3 PB2 PB1 PB0 PC5 PC4 PORT C(3) PC3 PC2 PC1 PC0 PD7 PD6 PD5 PORT D PD4 PD3 PD2 PD1 PD0 Configuration, Role x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Vcc Vcc INT3 INT2 JTGTDI JTGTDO JTGTMS JTGTCK SDA SCL HSMISO HSMOSI HSSCK HSSS INT1 INT0 TXD RXD OC1B Vcc Vcc KbIN7 KbIN6 KbIN5 KbIN4 KbIN3 KbIN2 KbIN1 KbIN0 SCK MISO MOSI SS PWM OC2A OC2B OC1A OC0B OC0A ICP1 T1 T0 LED3 LED2 LED1 LED0 INT3b INT2b PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 HSxxxx: “High-Speed SPI Controller” (MISO, MOSI, SCK, SS) INTx: “External Interrupts” , default configuration TXD, RXD: “USART” signals OCxB: Output Comparators: See “Timers” on page 87. JTGxxx: “JTAG Interface and On-chip Debug System” SDA, SCL: “2-wire Serial Interface _ TWI” signals LEDx: “LED” Outputs (IO driving current) INTxb: “External Interrupts” , bis configuration CLKO XCK Vcc TOSC1 TOSC2 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 KbINx: Input for “Keyboard Interface” TOSCx: 32.768 Khz crystals input for Real Time Clock. (Please note that these pins are not GPIO accessible). x x x x x x x x x x x x x x SS, MISO, MOSI, SCK: Standard “SPI - Serial Peripheral Interface” OCxx: Output Comparator outputs. See “Timers” on page 87. ICP1: Input Capture. See “16-bit Timer/Counter1 with PWM” PWM: Output from “8-bit Timer/Counter0 with PWM” Tx: Clock input for “Timers” 0 and 1 XCK: Clock input for synchronous “USART” INTx: “External Interrupts” , default configuration CLKO: System clock output. (only active if CKOUT fuse is enabled). “Fuse Low Byte” . 6 AT90SCR100 TPR0327AY–SMS–30Jan09 AT90SCR100 Table 2-1. Portmap Pin List Configuration SCR100LHS SCR100LSD SCR100H Supply ID PE7 PE6 PE5 PORT E PE4 PE3 PE2 PE1 PE0 Configuration, Role x x x x x x x x x x x x x x x x e (1) (2) x x x Smart Card PORT x x x x x x x x x x x x x x x x x x x KbO7 KbO6 KbO5 Vcc KbO4 KbO3 KbO2 KbO1 KbO0 Vcc CPRES CCLK CVcc CRST CIO CC4, DP CC8, DM CVcc CVSense CVcc CVss LI LO PCINT31 PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 KbOx: Output for “Keyboard Interface” Cx: “Smart Card Interface Block (SCIB)” : Standard ISO7816 port and “USB Host Controller” . Smart Card Interface: “DC/DC Converter” Supply Signals x x Notes: 1. Should be connected to e-pad underneath QFN package 2. According to the current configuration, these pins are supplied either by USB regulator or CVcc 3. PORT C is not complete, due to RTC pins, dedicated to oscillator pads 7 TPR0327AY–SMS–30Jan09 8 AT90SCR100 TPR0327AY–SMS–30Jan09 AT90SCR100 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 9 TPR0327AY–SMS–30Jan09 10 AT90SCR100 TPR0327AY–SMS–30Jan09 AT90SCR100 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. The code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 11 TPR0327AY–SMS–30Jan09 12 AT90SCR100 TPR0327AY–SMS–30Jan09 AT90SCR100 5. AVR CPU Core 5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural Overview Figure 5-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control Instruction Register 32 x 8 General Purpose Registrers Interrupt Unit SPI Unit Watchdog Timer Instruction Decoder Indirect Addressing Direct Addressing ALU Control Lines I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. 13 TPR0327AY–SMS–30Jan09 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Flash memory must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or via the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90SCR100 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate operand are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. This implementation of the architecture also provides a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 14 AT90SCR100 TPR0327AY–SMS–30Jan09 AT90SCR100 5.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 5.4.1 SREG – Status Register The AVR Status Register – SREG – is defined as: Bit 0x3F (0x5F) Read/write Initial value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 0x00 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive OR between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag 15 TPR0327AY–SMS–30Jan09 The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 5.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 5-2. AVR CPU General Purpose Working Registers 7 R0 R1 R2 … R13 General Purpose Working Registers R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02 Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 5-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 5.5.1 The X-register, Y-register, and Z-register The registers R26..R31 can also be used as 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5-3. 16 AT90SCR100 TPR0327AY–SMS–30Jan09 AT90SCR100 Figure 5-3. The X-, Y-, and Z-registers 15 X-register 7 R27 (0x1B) 15 Y-register 7 R29 (0x1D) 15 Z-register 7 R31 (0x1F) ZH 0 7 R30 (0x1E) YH 0 7 R28 (0x1C) ZL 0 0 XH 0 7 R26 (0x1A) YL 0 0 XL 0 0 In the different addressing modes these address registers have fixed displacement, automatic increment, and automatic decrement functionality (see the instruction set reference for details). 5.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the highest address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Bit 0x3E (0x5E) 0x3D (0x5D) Read/write Initial value 15 SP7 7 R R/W 0 1 14 SP6 6 R R/W 0 1 13 SP5 5 R R/W 0 1 12 SP12 SP4 4 R/W R/W 1 1 11 SP11 SP3 3 R/W R/W 0 1 10 SP10 SP2 2 R/W R/W 0 1 9 SP9 SP1 1 R/W R/W 0 1 8 SP8 SP0 0 R/W R/W 0 1 0x10 0xFF SPH SPH 5.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. 17 TPR0327AY–SMS–30Jan09 Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 5-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clk CPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 5-5. Single Cycle ALU Operation T1 T2 T3 T4 clk CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 5.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 377 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 63. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 63 for more information. 18 AT90SCR100 TPR0327AY–SMS–30Jan09 AT90SCR100 The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 377. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; start EEPROM write ; disable interrupts during timed sequence C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1