TS87C51RD2

Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 Qualification Package TS87C51RD2 / TS83C51RD2 CMOS 0.5µm TS87C51RD2 / TS83C51RD2 CMOS 0.5 µm JUNE 2001 June 2001 1 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 1 Contents 1 2 3 CONTENTS ........................................................................................................................................................................ 2 GENERAL INFORMATION ............................................................................................................................................ 3 TECHNOLOGY INFORMATION .................................................................................................................................. 4 3.1 3.2 4 WAFER PROCESS TECHNOLOGY .................................................................................................................................... 4 PRODUCT DESIGN ......................................................................................................................................................... 5 QUALIFICATION ............................................................................................................................................................. 6 4.1 QUALIFICATION FLOW .................................................................................................................................................. 6 4.2 WAFER PROCESS QUALIFICATION................................................................................................................................. 7 4.2.1 Process Module Reliability ...................................................................................................................................... 7 4.2.1.1 Hot carrier qualification ................................................................................................................................................ 7 4.2.1.2 Electro-migration ........................................................................................................................................................... 9 4.2.1.3 Time Dependent Dielectric Breakdown ................................................................................................................... 10 4.2.1.3.1 4.2.1.3.2 Field oxide.................................................................................................................................................................. 10 High Voltage MOS Gate oxide transistors ................................................................................................................. 12 4.3 T87C51RD2 QUALIFICATION TESTS .......................................................................................................................... 14 4.3.1 Design tests ............................................................................................................................................................ 14 4.3.2 Package tests ......................................................................................................................................................... 14 4.3.3 Qualification status................................................................................................................................................ 14 5 6 ENVIRONMENTAL INFORMATION.......................................................................................................................... 15 OTHER DATA.................................................................................................................................................................. 16 6.1 6.2 ISO9001 AND QS900 CERTIFICATES .......................................................................................................................... 16 DATA BOOK REFERENCE ............................................................................................................................................ 17 June 2001 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 2 General Information Product Name: Function: TS87C51RD2 8 Bits Microcontroller, 64K bytes memory TS87C51RD2: 64k EPROM TS83C51RD2: 64k ROM Wafer Process: Available Package Types CMOS 0.5um PLCC 44, VQFP 44 1.4, PDIL 40, PLCC 68, VQFP 64 1.4 Other Forms: Locations: Process Development, Product Development Wafer Plant QC Responsibility Probe Test Assembly Final Test Lot Release Shipment Control Quality Assurance Reliability Testing Failure Analysis Die, Wafer ATMEL Nantes , France ATMEL Nantes , France ATMEL Nantes , France ATMEL Nantes, France ATMEL Nantes , France Dependant upon Package Dependant upon Package ATMEL Nantes, France GLOBAL LOGISTICS CENTER, Philippines ATMEL Nantes, France ATMEL Nantes, France ATMEL Nantes, France ATMEL Nantes, France Quality Assurance Management ATMEL Nantes, France Signed: Pascal LECUYER June 2001 3 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 3 Technology Information 3.1 Wafer Process Technology Process Type (Name): Z94 (SCMOS3 Non Volatile - EPROM) Z92 (SCMOS3 - ROM) Bulk 475µm 150 mm Z94: 22 Z92: 14 Base Material: Wafer Thickness (final) Wafer Diameter Number Of Masks Gate Oxide (Logic transistors) Material Thickness Gate Oxide (EPROM cell) Material Thickness Silicon Dioxide 110 A Silicon Dioxide 220 A Polysilicon Number of Layers Thickness Poly 1 Thickness Poly 2 Metal Number of Layers Material: Layer 1 Thickness Layer 2 Thickness Layer 3 Thickness 2 (Z94), 1 (Z92) 2000A 3000A 2 AlCu 5150A 5150A 7650A Passivation Material Thickness Z94: SiO2 / Nitride Oxide – Z92: SiO2 / Nitride Z94: 3000A / 15000A – Z92: 2600A / 6400A June 2001 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 3.2 Product Design 4260µm * 4300µm (17.47mm2) 80µm * 80µm 0.5µm 0.50µm 0.60µm 0.60µm 0.70µm 0.80µm 0.70µm 0.80µm 0.70µm 0.60µm 0.60µm 0.60µm Die Size Pad Size Opening Logic Effective Channel Length Gate Poly Width (min.) Gate Poly Spacing (min.) Metal 1 Width Metal 1 Spacing Metal 2 Width Metal 2 Spacing Metal 3 Width Metal 3 Spacing Contact size Via 1 size Via 2 size June 2001 5 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 4 Qualification 4.1 Qualification Flow General Requirements for Plastic packaged CMOS IC Standard Test Description Qualification acceptance 1/2000 - 12h MIL-STD 883D Method 1005 MIL-STD 883D Method 1005 MIL-STD 883D Method 3015.7 JEDEC 78 Electrical Life Test (Early Failure Rate) 12 hours 140°C / 5.75V Electrical Life Test (Latent Failure Rate) 1000 hours 140°C / 5.75V Dynamic or Static Electrostatic Discharge HBM +/-2000v 1.5kOhm/100pF/3 pulses Latch-up 50mW power injection, 1.5 Vcc over voltage 125°C MEMORY Data Retention High Temperature Storage 165°C Temperature Cycling 1000 cycles –65°C/150°C air/air Autoclave after Preconditioning 144 hours 130°C/85%RH 85/85 Humidity Test 1000 hours 85°C/85%RH/5.5V HAST 168 hours 130°C/85%RH/5.5V Resistance to Soldering Heat Infra Red Stress 235°C/25s/3 times Solderability 0/100 - 500h 0/3 per level 0/5 per condition Atmel Nantes PAQA0046 MIL-STD 883D Method 1010 Atmel Nantes PAQA0184 EIA JESD22-A101 EIA JESD22-A110 EIA JESD20-STD MIL-STD 883D Method 2003 MIL-STD 883D Method 2015 0/50 - 500h 0/50 - 500c 0/50 - 72h 0/50 - 500h 0/50 - 168h 0/10 per level 0/3 Marking Permanency 0/3 June 2001 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 4.2 Wafer Process Qualification 4.2.1 Process Module Reliability This chapter contains all the information relative to the reliability of the SCMOS3 NV technology. Results presented in the following sections concern the reliability of the basic process steps which build up the technology. 4.2.1.1 Hot carrier qualification STATIC NMOS DEGRADATION Channel length in µm Process corner Substrate current in µA/µm VD=5.5V, VG=2.25V Substrate current in µA/µm VD=3.6V, VG=1.6V Lifetime in seconds for 10% shift of Gm at VD=5.5V Lifetime in seconds for 10% shift of Gm at VD=3.6V 0.5 Fast 17 0.35 3.2e3 8e7 0.55 Fast 15 0.3 3.7e3 10e7 0.6 Fast 13.4 0.25 4.2e3 12e7 0.65 Fast 12.1 0.22 4.7e3 14e7 0.7 Fast 11.1 0.2 5.2e3 16e7 0.5 Typical 14.7 0.3 3.8e3 10e7 STATIC PMOS DEGRADATION Channel length in µm Process corner Substrate current in µA/µm VD=5.5V, VG=2.25V Substrate current in µA/µm VD=3.6V VG=1.25V Lifetime in seconds for 10% shift of Gm at VD=5.5V Lifetime in seconds for 10% shift of Gm at VD=3.6V 0.5 Fast 0.31 2.3e-3 2.7e4 2e7 0.55 Fast 0.28 1.9e-3 3.1e4 2.5e7 0.6 Fast 0.25 1.6e-3 3.5e4 3e7 0.65 Fast 0.22 1.4e-3 3.9e4 3.8e7 0.7 Fast 0.21 1.1e-3 4.3e4 4.6e7 0.5 Typical 0.24 1.6e-3 3.5e4 3.2e7 EXPERIMENTAL RESULTS IN DYNAMIC MODE : hot carrier degradation effects on inverter propagation time have been measured on oscillators running at 75 MHz at 7V and 6.5V. Accelerator factor in voltage is then carried out and expected degradation laws at 5V and 3.3V derived. The following graphs show the frequency degradation of oscillators running at 5V and 3.3V. June 2001 7 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 SCMOS3 NV Frequency degradation VCC = 3.3 Volts. 1 0,8 DFreq/freq in % 200 MHz 0,6 0,4 0,2 0 0 5 10 15 20 25 30 100 MHz 50 MHz 25 MHz Years SCMOS3 NV Frequency degradation VCC = 3.3 Volts. 1 0,8 DFreq/freq in % 200 MHz 0,6 0,4 0,2 0 0 5 10 15 20 25 30 100 MHz 50 MHz 25 MHz Years June 2001 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 4.2.1.2 Electro-migration Characterization Stresses of electro-migration are achieved for 1000 hours on 32 packaged metal line running on flat with a current density of 2x106 A/cm² at a temperature of 200°C. Lines are declared to be failed for a shift of the initial resistance by 20%. Results are summarized in the table below. Level Metal1 Metal2 Metal3 W /L/T(1) 2/2000/0.50 2/2000/0.50 2/2000/0.70 Structure Ti/TiN/AlCu/TiN Ti/TiN/AlCu/TiN Ti/TiN/AlCu/TiN Failures no no no (1) W/L/T=Width/Length/Thickness of the metal line in microns Lifetime projection The objective of reliability is to reach less than 10 FIT on metal line within 10 years at a temperature of 150°C. As no failures have been found at 1000 hours in the above stress conditions a lifetime projection in FIT is meaningless. However, assuming for AlCu metalization an activation energy in temperature Ea of 0.60eV and an activation in current with a power-law coefficient n of 2, the current density which guarantees no failures within 10 years at 150°C can be extrapolated. With these assumptions the projected current density for no failures at 150°C within 10 years is calculated as 5x105A/cm² which is much higher than the current density of 2x105A/cm² specified in the design rules. June 2001 9 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 4.2.1.3 Time Dependent Dielectric Breakdown 4.2.1.3.1 Field oxide QBD MEASUREMENT: The critical charge, supported by the thin oxide and related to the extrinsic and intrinsic defects, is measured on -4 -2 TOX/P- and TOX/N- capacitors. The tested capacitor areas are varying from 4.10 to 5.10 cm². Two types of capacitors with poly overlaping the field oxide (DEC) and poly non overlaping the field oxide (INC) are measured. The distributions have been obtained from 750 measurements for each area and type of capacitors on 10 different lots. Extrinsic defects: The two graphs here after represent the % of failures vs area for Qbd below or equal to 0.1 Cb/cm². The law of Poisson is used to determine the D0 defect density of the extrinsic defects: Y=1-exp(-Area * DO) Poly overlaping the Field oxide on Tox/P- and Tox/N-: The DO is found to be 1.1 def/cm². This result is in agreement with the goal for DO of 1 def/cm². Qbd < 0.1Cb/cm² CAPA WITH POLY OVERLAPING THE FIELD OXIDE 0 -0,02 DEC PDEC NPoisson Ln(1-Y) -0,04 -0,06 0 0,02 0,04 0,06 Area in cm² DO=1.1 def/cm² June 2001 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 Poly non overlaping the Field oxide on Tox/P- and Tox/N-: The DO is found to be 0.9def/cm². This result is in agreement with the goal for DO of 1 def/cm². Qbd < 0.1Cb/cm² CAPA WITH POLY NON OVERLAPING THE FIELD OXIDE 0 -0,01 Ln(1-Y) -0,02 INC PINC N- -0,03 Poisson -0,04 -0,05 0 0,02 0,04 0,06 Area in cm² DO=0.9 def/cm² Intrinsic defects: The graph here after represents the percentage of failure for a Qbd > 10 Cb/cm² vs the area. The worst case given by the bigest capacitors shows that 67% of the total distribution has a Qbd > 10 Cb/cm². This result guarantees a good reliability behaviour. The critical charge, supported by thin oxide and related to the extrinsic defects, is measured on TOX/P- capacitors of 42570µm² and TOX/N- capacitors of 85140µm². Following are the average results obtained on recent lots from a distribution of about 60 sites per wafer. The minimum specification limit is 10C/cm². Qbd > 10 Cb/cm² SCMOS3 PROCESS 1 0,9 0,8 DEC PDEC N- Yield 0,7 INC PINC N- 0,6 0,5 0 0,02 0,04 0,06 Area in cm² June 2001 11 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 4.2.1.3.2 High Voltage MOS Gate oxide transistors High voltage gate oxide transistors are used within the EPROM circuits to increase the external programming voltage up to 14.5 Volts. This operation is needed to reach the appropriate programming conditions. As a result, the maximum voltage between gate and source/drain of high voltage MOS transistors can be about 10 Volts . The experiment consists of the application of an accelerated constant voltage stress until the breakdown of the oxide is reached. The time of the breakdown is then extrapolated for nominal voltage condition. The capacitor is made with a 20nm oxide growth on P- substrate and the electrode is phosphorus doped poly : the capacitor area is 0.23 mm². The Time Dependant Dielectric Breakdown is accelerated in voltage and temperature.The temperature is set to 150°C so no acceleration factor depending on temperature is needed for the extrapolation of product lifetime. An unique accelerated electrical field of 9 MV/cm (19.4V for this oxide thickness) has been applied. The experiment has been performed on capacitors issued from 3 wafers coming from 3 different lots : a set of 28 capacitors has been stressed. A cumulative plot of failures obtained first at 19.4V and the second one projected to 10V with the relevant model are presented on the following figure : SCMOS3 NV HVOX 4 2 19.4 V 10V 0 -2 Data Model -4 -6 -8 -10 0 2 4 6 8 10 12 14 16 18 Log(t(s)) June 2001 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 The model predicts a failure level of about 1 ppm for 640 seconds at 150°C far above the specification of 0.01% then the High Voltage MOS gate oxide is qualified. Conclusion: The QBD results demonstrate high reliability level of SCMOS3 NV thin oxide. June 2001 13 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 4.3 T87C51RD2 Qualification Tests This section summarizes the cumulated package level qualification data of the TS87C51RD2. 4.3.1 Design tests Lots Z28303C Z34922E Z33543 Device Type Test Description TS87C51RD2 EFR Dynamic Life Test PLCC44 LFR Dynamic Life Test Data Retention 165°c Z28882 TS83C51RD2 ESD DIL 40.6 Latch-up Step 12h Result 0/900 Comment EFR: 0 ppm 500h 1000h 500h 1000h 3000v 4000v 50mW 7.5v 0/300 0/300 0/150 0/150 0/3 0/3 0/5 0/5 LFR: 19 fit Class 3 Latch-up free 4.3.2 Package tests Lots Z28303C Z34922E Z33543 Device Type TS87C51RD2 PLCC44 Test Description 85/85 Humidity Step 500h 1000h 500c 1000c CSAM Test 15ts 72h 144h Result Comment 0/150 0/150 0/150 0/150 0/30 0/180 0/150 0/150 0/150 0/3 0/3 Thermal Cycles Moisture preconditioning Level 1 Thermal Sh. -65°c/150°c HAST 130°c/85%rh Z25873C PLCC44 Marking permanency (resistance to solvents) Solderability Pass level 1 of JEDEC 20 4.3.3 Qualification status The TS87C51RD2 and TS83C51RD2 have been qualified in July 1999. June 2001 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 5 Environmental Information The Atmel Nantes Environmental Policy aims are : - Reducing the use of harmful chemicals in its processes - Reducing the content of harmful materials in its products - Using re-cyclable materials wherever possible - Reducing the energy content of its products As part of that plan, Ozone Depleting Chemicals are being replaced either by Atmel Nantes or its sub-contractors' process. Atmel Nantes site is ISO14001 certified since May 2000. June 2001 15 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 6 Other Data 6.1 ISO9001 and QS900 Certificates June 2001 Atmel Wireless & Microcontrollers Qualpack TS87C51RD2/TS83C51RD2 6.2 Data Book Reference The data sheet is available upon request to sales representative or upon direct access on ATMEL Wireless and Microcontrollers web site: http://www.atmel-wm.com/ TS87C51RD2 8-bit Microcontroller Address References All inquiries relating to this document should be addressed to the following: ATMEL Nantes BP70602 44306 Nantes Cedex 3 France Telephone (33) 2 40 18 18 18 Telefax (33) 2 40 18 19 00 Or direct contact Pascal LECUYER Product Assurance Manager Telephone (33) 2 40 18 17 73 Telefax (33) 2 40 18 19 00 Remarks: The information given in this document is believed to be accurate and reliable. However, no responsibility is assumed by Atmel for its use. No specific guarantee or warranty is implied or given by this data unless agreed in writing elsewhere. Atmel reserves the right to update or modify this information without notification, at any time, in the interest of providing the latest information. Parts of this publication may be reproduced without special permission on the condition that our author and source are quoted and that two copies of such extracts are placed at our disposal after publication. Before use of such reproduced material the user should check that the information is current. Written permission must be obtained from the publisher for complete reprints or translations. June 2001 17