PI6C4911510FAIE

PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features Description ÎÎFMAX < 1.5GHz The PI6C4911510 is a high-performance low-skew 1-to-10 LVPECL fanout buffer. The PI6C4911510 features two selectable differential clock inputs and translates to ten LVPECL outputs. The CLK inputs accept LVPECL, LVDS, CML and SSTL signals. ÎÎ10 pairs of differential LVPECL outputs ÎÎLow additive jitter, < 0.03ps (typ) ÎÎSelectable differential input pairs with single ended option input PI6C4911510 is ideal for clock distribution applications such as providing fanout for low noise SaRonix-eCera oscillators. ÎÎInput CLK accepts: LVPECL, LVDS, CML, SSTL input level ÎÎOutput skew: 40ps (typ) ÎÎOperating Temperature: -40oC to 85oC ÎÎCore Power supply: 2.5V ±5% & 3.3V ±10%, Output Power supply: 2.5V ±5% & 3.3V ±10% ÎÎPackaging (Pb-free & Green): ÎÎ32-pin QFN and TQFP available Pin Configuration Q3 /Q3 Q4 /Q4 Q5 /Q5 Q6 /Q6 Block Diagram 15-0077 1 PI6C4911510 vDDO Q7 /Q7 Q8 /Q8 Q9 /Q9 vDDO VEE /CLK1 CLK1 VBB (NC) /CLK0 CLK0 CLK_SEL 24 23 22 21 20 19 18 17 16 25 15 26 14 27 13 28 12 29 11 30 10 31 9 32 1 2 3 4 5 6 7 8 VDD VDDO /Q2 Q2 /Q1 Q1 /Q0 Q0 vDDO Rev H 6/25/2015 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux Pin Description(1) Pin # Name Type Description 1 VDD Power Core Power Supply 2 CLK_SEL Input Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. LVCMOS/LVTTL level with 50kΩ pull down. 3 CLK0 Input Differential clock input with pull-down 4 /CLK0 Input Inverting differential clock input. Defaults to VDD/2 if left floating. 5 VBB (NC) Power Internal Common Mode Voltage, can be left as not connected if unused. 6 CLK1 Input Differential clock input with pull-down 7 /CLK1 Input Inverting differential clock input. Defaults to VDD/2 if left floating. 8 VEE Power Connect to negative power supply 9, 16, 25, 32 VDDO Power Output Power pin 11, 10 Q9, /Q9 Output Differential output pair, LVPECL interface level. 13,12 Q8, /Q8 Output Differential output pair, LVPECL interface level. 15,14 Q7, /Q7 Output Differential output pair, LVPECL interface level. 18,17 Q6, /Q6 Output Differential output pair, LVPECL interface level. 20,19 Q5, /Q5 Output Differential output pair, LVPECL interface level. 22,21 Q4, /Q4 Output Differential output pair, LVPECL interface level. 24, 23 Q3, /Q3 Output Differential output pair, LVPECL interface level. 27,26 Q2, /Q2 Output Differential output pair, LVPECL interface level. 29,28 Q1, /Q1 Output Differential output pair, LVPECL interface level. 31,30 Q0, /Q0 Output Differential output pair, LVPECL interface level. Note: 1. I = Input, O = Output, P = Power supply connection. Control Input Function Table CLK_SEL Outputs 0 CLK0 1 CLK1 15-0077 2 PI6C4911510 Rev H 6/25/2015 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux Absolute Maximum Ratings(1) Symbol Parameter Conditions Min VDD Supply voltage Referenced to GND VIN Input voltage Referenced to GND IOUT Surge Current TSTG Storage temperature VBB Sink/source Current, IBB Tj Junction Temperature Typ -0.5 Max Units 4.6 V VDD+0.5V V 100 mA -55 150 oC -0.5 +0.5 mA 125 oC Note: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Conditions Symbol Parameter VDD Core Power Supply Voltage VDDO Conditions Min Max Units 2.375 3.6 V Output Power Supply Voltage 2.375 3.6 V TA Ambient Temperature -40 85 oC IDD Core Power Supply Current IDDO Output Power Supply Current All LVPECL outputs unloaded Typ 70 95 110 200 mA LVCMOS/LVTTL DC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±10%, VDDO = 2.5V ±5% to 3.3V ±10%) Symbol Parameter VIH Input High Voltage CLK_SEL 1.7 VIL Input Low Voltage CLK_SEL -0.3 IIH Input High Current CLK_SEL VIN = VDD = 3.6V IIL Input Low Current CLK_SEL VIN = 0V, VDD = 3.6V R Input Pullup/Pulldown Resistance 15-0077 Conditions Min Typ Max Units VDD+0.3 150 μA -150 μA 50 3 V kΩ PI6C4911510 Rev H 6/25/2015 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux LVPECL DC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±10%, VDDO = 2.5V ±5% to 3.3V ±10%) Symbol Parameter Conditions Min IIH Input High Current CLK0, CLK1 IIL Input Low Current VCMR Common Mode Input Voltage(1) VOH Output High Voltage(2) VDDO = 2.5V or 3.3V VDDO1.5 VOL Output Low Voltage(2) VDDO = 2.5V or 3.3V VDDO2.2 R Input Pullup/Pulldown Resistance Typ Max Units VIN = VDD = 3.6V 150 µA /CLK0, /CLK1 VIN = VDD = 3.6V 150 µA CLK0, CLK1 VDD = 3.6V, VIN = 0V -150 µA /CLK0, /CLK1 VDD = 3.6V, VIN = 0V -150 µA VEE+0.5 VDD V VDDO-1.4 VDDO-0.9 V VDDO-2.0 VDDO-1.7 V 50 kΩ Notes: 1. For single-ended applications, the maximum input voltage for CLK and /CLK is V DD+0.3V 2. Outputs terminated with 50Ω to V DD-2.0V AC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±10%, VDDO = 2.5V ±5% to 3.3V ±10%) Symbol Parameter Conditions Min Typ Max Units fmax Output Frequency tpd Propagation Delay(1) 1500 MHz 1200 ps Tsk Output-to-output Skew(2) 40 ps tr/tf Output Rise/Fall time 20% - 80% 150 ps todc Output duty cycle f ≤ 650 MHz 48 VPP Output Swing LVPECL outputs 0.6 52 1.0 % V 156.25MHz (12KHz20MHz integration range) tj Buffer additive jitter RMS Input condition per Phase Noise and Additive Jitter Plot below 0.03 0.05 ps Notes: 1. Measured from the differential input to the differential output crossing point 2. Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing point 15-0077 4 PI6C4911510 Rev H 6/25/2015 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux Phase Noise and Additive Jitter Output phase noise (Dark Blue) vs Input Phase noise (light blue) Additive jitter is calculated at ~27fs RMS (12kHz to 20MHz). Additive jitter = √(Output jitter2 - Input jitter2) Configuration Test Load Board Termination for LVPECL Outputs LVPECL Buffer VDDQx Z o = 50 L = 0 ~ 10 in. 100 Z o = 50 150 15-0077 150 5 PI6C4911510 Rev H 6/25/2015 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux Application Information Wiring the differential input to accept single ended levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609. VDD R1 1K Single Ended Clock Input CLK /CLK C1 0.1µ R2 1K Figure 1. Single-ended input to Differential input device Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. All power pins should be individually connected to the power supply plane through vias, and 0.1μF an 1μF bypass capacitors should be used for each pin. VDD VDD 0.1µF 1µF VDDO VDDO 0.1µF 15-0077 1µF 6 PI6C4911510 Rev H 6/25/2015 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux Packaging Mechanical: 32-pin QFN (ZH) Notes: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. 3. Refer JEDEC MO-220 4. Recommended land pattern is for reference only. 5. Thermal pad soldering area (mesh stencile design is recommended) DATE: 06/30/11 DESCRIPTION: 32-contact, Thin Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH32 DOCUMENT CONTROL #: PD-2070 REVISION: B 11-0147 Thermal Information Symbol Description ΘJA Junction-to-ambient thermal resistance ΘJC Junction-to-case thermal resistance 15-0077 Condition 44.70 °C/W Still air 21.70 °C/W 7 PI6C4911510 Rev H 6/25/2015 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux Packaging Mechanical: 32-pin TQFP (FA) DOCUMENT CONTROL NO. PD - 1814 9.00 BSC .354 Square REVISION: C DATE: 03/09/05 Square 7.00 BSC 0.09 0.20 .004 .008 GAUGE PLANE 0.25 mm .276 1 1.20 Max. .047 0° 7° 0.45 .018 0.75 .030 1.00 REF .039 .004 0.10 Seating Plane 0.30 .012 0.45 .018 0.80 BSC .032 0.05 0.15 .002 .006 0.95 1.05 .037 .041 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Notes: 1. Controlling dimensions in millimeters 2. Ref.: JEDEC MS-026D/ABA 3. Package Outline Exclusive of Mold Flash and Metal Burr DESCRIPTION: 32-Pin, Thin Quad Flat Package, TQFP PACKAGE CODE: FA Thermal Information Symbol Description ΘJA Junction-to-ambient thermal resistance ΘJC Junction-to-case thermal resistance 15-0077 Condition 86 °C/W Still air 12.7 °C/W 8 PI6C4911510 Rev H 6/25/2015 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux Packaging Mechanical: 32-pin TQFP with E-Pad (FAE) D D2 D1 9 25 1 24 8 17 8 17 1 24 E E1 PIN1 Index Area 16 E2 32 16 32 25 BOTTOM VIEW TOP VIEW PKG. DIMENSIONS(MM) A θ e b A1 c A2 SYMBOLS SIDE VIEW MAX. - 1.20 A1 0.05 0.15 A2 0.95 1.05 b 0.30 0.45 c 0.09 0.20 D 8.75 9.25 D1 6.90 7.10 E 8.75 9.25 E1 6.90 7.10 e L MIN. A 0.80 BSC L 0.45 0.75 D2 E2 3.19 3.90 3.19 3.90 θ 0° 7° DATE: 03/24/15 NOTES: 1.Ref: JEDEC MS-026 ABA-HD DESCRIPTION: 32 -Pin, TQFP, 7X7, Exposed Pad PACKAGE CODE: FAE (FAE32) DOCUMENT CONTROL #: PD-2196 REVISION: -- 15-0023 Thermal Information Symbol Description ΘJA Junction-to-ambient thermal resistance ΘJC Junction-to-case thermal resistance 15-0077 Condition 45 °C/W Still air 15 °C/W 9 PI6C4911510 Rev H 6/25/2015 PI6C4911510 2.5V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer w/ 2 to 1 Differential Clock Input Mux Ordering Information(1,2,3) Ordering Code Package Code Package Description PI6C4911510ZHIE ZH Pb-free & Green, 32-pin QFN PI6C4911510ZHIEX ZH Pb-free & Green, 32-pin QFN, Tape & Reel PI6C4911510FAIE FA Pb-free & Green, 32-pin TQFP PI6C4911510FAIEX FA Pb-free & Green, 32-pin TQFP, Tape & Reel PI6C4911510FAEIE FAE Pb-free & Green, 32-pin TQFP E-Pad PI6C4911510FAEIEX FAE Pb-free & Green, 32-pin TQFP E-Pad, Tape & Reel Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free & Green 3. X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336  •  www.pericom.com 15-0077 10 PI6C4911510 Rev H 6/25/2015