74ALVCH32973ZKER

SN74ALVCH32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS www.ti.com SCES436C – APRIL 2003 – REVISED SEPTEMBER 2004 • FEATURES • • Member of the Texas Instruments Widebus+™ Family Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This device contains eight independent noninverting buffers and a 16-bit noninverting bus transceiver and D-type latch designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH32973 is particularly suitable for demultiplexing an address/data bus into a dedicated address bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication between the A and B data bus, and the address signals are latched and buffered on the Q bus. The control-function implementation minimizes external timing requirements. This device can be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit transceiver, and one 16-bit latch. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable (TOE) input can be used to disable the transceivers so that the A and B buses effectively are isolated. When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE) input can be used to place the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, LOE and TOE should be tied to VCC through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of the drivers. The eight independent noninverting buffers perform the Boolean function Y = D and are independent of the state of DIR, TOE, LE, and LOE. The A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION PACKAGE (1) TA -40°C to 85°C (1) LFBGA - GKE LFBGA - ZKE (Pb-free) Tape and reel ORDERABLE PART NUMBER SN74ALVCH32973KR 74ALVCH32973ZKER TOP-SIDE MARKING ACH973 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2004, Texas Instruments Incorporated SN74ALVCH32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS www.ti.com SCES436C – APRIL 2003 – REVISED SEPTEMBER 2004 GKE OR ZKE PACKAGE (TOP VIEW) 1 2 3 4 5 rt rt rt 6 TERMINAL ASSIGNMENTS 1 2 3 4 5 6 A 1A1 D1 1TOE 1DIR 1B1 1Q1 B 1A2 Y1 GND GND 1B2 1Q2 C 1A3 D2 VCC VCC 1B3 1Q3 D 1A4 Y2 GND GND 1B4 1Q4 E E 1A5 D3 GND GND 1B5 1Q5 F F 1A6 Y3 VCC VCC 1B6 1Q6 G G 1A7 D4 GND GND 1B7 1Q7 H H 1A8 Y4 1LE 1LOE 1B8 1Q8 J J 2A1 D5 2TOE 2DIR 2B1 2Q1 K K 2A2 Y5 GND GND 2B2 2Q2 L L 2A3 D6 VCC VCC 2B3 2Q3 M 2A4 Y6 GND GND 2B4 2Q4 N 2A5 D7 GND GND 2B5 2Q5 P 2A6 Y7 VCC VCC 2B6 2Q6 R 2A7 D8 GND GND 2B7 2Q7 T 2A8 Y8 2LE 2LOE 2B8 2Q8 A B C D M N P R T FUNCTION TABLES INPUTS TOE OPERATION DIR L L B data to A bus L H A data to B bus H X A bus and B bus isolation INPUTS 2 LOE LE A OUTPUT Q L H H H L H L L L L X Q0 H X X Z INPUT D OUTPUT Y L L H H SN74ALVCH32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS www.ti.com SCES436C – APRIL 2003 – REVISED SEPTEMBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR A4 A3 1LOE 1LE 1TOE H4 H3 One of Eight Channels C1 A6 1Q1 1D 1A1 A1 A5 1B1 To Seven Other Channels 3 SN74ALVCH32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS www.ti.com SCES436C – APRIL 2003 – REVISED SEPTEMBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) 2DIR J4 J3 2LOE 2LE 2TOE T4 T3 One of Eight Channels C1 J6 2Q1 1D 2A1 J1 J5 To Seven Other Channels One of Eight Channels D1 4 A2 B2 Y1 2B1 www.ti.com SN74ALVCH32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS SCES436C – APRIL 2003 – REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX -0.5 4.6 Except I/O and D input ports (2) -0.5 4.6 I/O and D input ports (2) (3) -0.5 VCC + 0.5 -0.5 VCC + 0.5 UNIT V VI Input voltage range VO Output voltage range (2) (3) IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current ±50 mA ±100 Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) GKE/ZKE package -65 V V mA 40 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V MIN MAX 1.65 3.6 Low-level input voltage V 0.65 × VCC 1.7 V 2 0.35 × VCC VCC = 1.65 V to 1.95 V VIL UNIT VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) VCC = 1.65 V -4 VCC = 2.3 V -12 VCC = 2.7 V -12 VCC = 3 V -24 VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24 -40 mA mA 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5 SN74ALVCH32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS www.ti.com SCES436C – APRIL 2003 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA 1.65 V to 3.6 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA IBHH (3) 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 IBHHO (5) 1.65 V 25 2.3 V 45 VI = 0.8 V 3V 75 VI = 1.07 V 1.65 V -25 VI = 1.7 V 2.3 V -45 3V -75 1.95 V 200 2.7 V 300 3.6 V 500 1.95 V -200 2.7 V -300 3.6 V -500 VI = 0 to VCC VI = 0 to VCC VI = VCC or GND, IO = 0 ∆ICC One input at VCC - 0.6 V, Other inputs at VCC or GND Cio Co (1) (2) (3) (4) (5) (6) 6 A ports B ports Q ±5 VI = 0.7 V ICC D 0.55 VI = 0.57 V VO = VCC or GND Ci 0.4 3V 3.6 V IOZ (6) Control inputs 2.7 V VI = VCC or GND VI = 2 V IBHLO (4) V 1.65 V to 3.6 V IOL = 24 mA UNIT 1.2 IOL = 4 mA IOL = 12 mA IBHL (2) MAX VCC - 0.2 1.65 V IOH = -12 mA II MIN TYP (1) IOH = -4 mA VOH VOL VCC V µA µA µA µA µA ±10 µA 3.6 V 60 µA 3 V to 3.6 V 750 µA 3.6 V VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V VO = VCC or GND 3.3 V 3 4 4.5 4.5 3 pF pF pF All typical values are at VCC = 3.3 V, TA = 25°C. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. For I/O ports, the parameter IOZ includes the input leakage current. SN74ALVCH32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS www.ti.com SCES436C – APRIL 2003 – REVISED SEPTEMBER 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V MIN MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX tw Pulse duration, LE high 2 2 2 ns tsu Setup time, data before LE↓ 0.9 0.9 0.9 ns th Hold time, data after LE↓ 0.9 0.9 0.9 ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd ten VCC = 3.3 V ± 0.3 V TO (OUTPUT) VCC = 1.8 V TYP MIN MAX MIN MAX D Y 2.2 0.5 3.2 0.5 3 2.2 0.5 3.2 0.5 3 2.8 0.5 3.3 0.5 3 A LE Q UNIT A or B B or A 2.2 0.5 3.2 0.5 3 LOE Q 2.9 0.7 4.9 0.7 4.7 3 0.7 4.6 0.7 4.4 3.4 0.7 4.9 0.7 4.7 2.8 0.5 4.3 0.5 4.1 3.2 0.5 4.3 0.5 4.1 3.4 0.5 4.9 0.5 4.7 TOE DIR LOE tdis VCC = 2.5 V ± 0.2 V FROM (INPUT) TOE DIR A or B Q A or B ns ns ns 7 SN74ALVCH32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS www.ti.com SCES436C – APRIL 2003 – REVISED SEPTEMBER 2004 OPERATING CHARACTERISTICS (1) TA = 25°C PARAMETER Cpd (2) (each output) Cpd (Z) Cpd (3) (each LE) (1) (2) (3) 8 Power dissipation capacitance VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP UNIT A outputs enabled, Q outputs disabled, one A output switching One fA = 10 MHz, One fB = 10 MHz, TOE = GND, LOE = VCC, DIR = GND, CL = 0 pF 12 14 19 B outputs enabled, Q outputs disabled, one B output switching One fA = 10 MHz, One fB = 10 MHz, TOE = GND, LOE = VCC, DIR = GND, CL = 0 pF 12 14 21 Q outputs enabled, A and B I/Os isolated, one Q output switching One fA = 10 MHz, One fLE = 20 MHz, One fQ = 10 MHz, TOE = VCC, LOE = GND, CL = 0 pF 11 13 19 One Y output switching, A and B I/Os isolated, Q outputs disabled One fD = 10 MHz, One fY = 10 MHz, TOE = VCC, LOE = VCC, CL = 0 pF 7 8 12 A and B I/Os isolated, Q outputs disabled, one LE and one A data input switching One fA = 10 MHz, One fLE = 20 MHz, fQ not switching, TOE = VCC, LOE = VCC, CL = 0 pF 4 5 11 pF A and B I/Os isolated, Q outputs disabled, one LE input switching fA not switching, One fLE = 20 MHz, fQ not switching, TOE = VCC, LOE = VCC, CL = 0 pF 6 7 9 pF Power dissipation capacitance Power dissipation capacitance TEST CONDITIONS pF Total device Cpd for multiple (m) outputs switching and (n) LE inputs switching = [m * Cpd (each output)] + [n * Cpd (each LE)] Cpd (each output) is the Cpd for each data bit (input and output circuitry) when it operates at 10 MHz (Note: The LE is operating at 20 MHz in this test, but its ICC component has been subtracted). Cpd (each LE) is the Cpd for the clock circuitry only when it operates at 20 MHz. SN74ALVCH32973 16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS www.ti.com SCES436C – APRIL 2003 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL (see Note A) RL S1 Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V ≤2 ns ≤2 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 2 × VCC 2 × VCC 6V 30 pF 30 pF 50 pF 1 kΩ 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V tw VI Timing Input VM VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VM VM 0V tPLH Output Control (low-level enabling) tPLZ VLOAD/2 VM tPZH VOH VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPHL VM VI VM tPZL VI Input VOLTAGE WAVEFORMS PULSE DURATION th VI Data Input VM 0V 0V tsu Output VI VM Input Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VOH VM VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 9 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 74ALVCH32973ZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 85 ACH973 SN74ALVCH32973KR ACTIVE LFBGA GKE 96 1000 TBD SNPB Level-2-235C-1 YEAR -40 to 85 ACH973 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 18-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 74ALVCH32973ZKER LFBGA ZKE 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 Q1 SN74ALVCH32973KR LFBGA GKE 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ALVCH32973ZKER SN74ALVCH32973KR LFBGA ZKE 96 1000 336.6 336.6 41.3 LFBGA GKE 96 1000 336.6 336.6 41.3 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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