BUF16820
BU F1 68 20
SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
14-Channel GAMMA VOLTAGE GENERATOR with Programmable VCOM Outputs and OTP Memory
FEATURES
D D D D D D D D D D D
14-CHANNEL GAMMA CORRECTION 2 VCOM OUTPUTS ON-CHIP OTP MEMORY 10-BIT RESOLUTION RAIL-TO-RAIL OUTPUT LOW SUPPLY CURRENT: 1mA/ch SUPPLY VOLTAGE: 8.5V to 18V DIGITAL SUPPLY: 2.0V to 5.5V INDUSTRY-STANDARD, TWO-WIRE INTERFACE: 3.4MHz HIGH-SPEED MODE HIGH ESD RATING: 4kV HBM, 1kV CDM, 200V MM DEMO BOARD AND SOFTWARE AVAILABLE
APPLICATIONS
D D
D REPLACES RESISTOR-BASED GAMMA
SOLUTIONS TFT-LCD REFERENCE DRIVERS DYNAMIC GAMMA CONTROL
DESCRIPTION
The BUF16820 is a programmable voltage reference generator designed for gamma correction in TFT-LCD panels. It provides 14 programmable outputs and two VCOM channels, each with 10-bit resolution. It offers on-chip, one-time programmable (OTP) memory that allows the user to store the gamma voltages on-chip. This eliminates the need for an external EEPROM. This programmability replaces the traditional, timeconsuming process of changing resistor values to optimize the various gamma voltages, and allows designers to determine the correct gamma voltages for a panel very quickly. Required voltage changes can also be easily implemented without changing the hardware. The BUF16820 uses TI’s latest, small-geometry analog CMOS process, which makes it a very competitive choice for full production, not just evaluation. Programming of each output occurs through an industrystandard, two-wire serial interface. Unlike existing programmable buffers, the BUF16820 offers a high-speed mode that allows clock speeds up to 3.4MHz. For devices with a lower or higher channel count, please contact your local sales or marketing representative.
2V to 5.5V Digital BUF16820
8.5V to 18V Analog REFH
REFH OUT
OUT1
OUT2
… …
DAC Registers 1 OTP Memory
DAC Registers 2
…
14 Output Channels plus Two VCOM Channels
Program Command
OUT13
OUT14
The BUF16820 is available in an HTSSOP-32 PowerPAD package. It is specified from −40°C to +85°C.
VCOM1
BUF16820 RELATED PRODUCTS
FEATURES 18-Channel Programmable, Two VCOM Channels, Memory 12-Channel Programmable Buffer, 10-Bit Programmable VCOM 10 + 1 Channel Gamma Buffer, 22V Supply Voltage PRODUCT BUF20820 BUF12800 BUF01900 BUF11705 TPS651xx
VCOM2 REFL OUT SDA Control IF SCL
LD
A0
REFL
Complete LCD DC/DC Solution
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2006, Texas Instruments Incorporated
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BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PIN CONFIGURATION
TOP VIEW HTSSOP
VCOM2 REFH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PowerPAD Lead−Frame Die Pad Exposed on Underside
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCOM1 REFL REFL OUT NC (1) NC (1) OUT14 GNDA(2) VS OUT13 OUT12 OUT11 OUT10 GNDD(2) LD A0 SDA
ORDERING INFORMATION(1)
PRODUCT BUF16820 PACKAGE-LEAD HTSSOP-32 PACKAGE DESIGNATOR DAP PACKAGE MARKING BUF16820
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 GNDA (2)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +19V Supply Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Signal Input Terminals, SCL, SDA, A0, LD: Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +6V Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Short Circuit(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +95°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C ESD Rating: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Short-circuit to ground.
VS OUT7 OUT8 OUT9 REFH OUT VSD SCL
(1) NC denotes no connection. (2) GNDD and GNDA are internally connected and must be at the same voltage potential.
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BUF16820
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ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = −40°C to +85°C.
At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted. BUF16820 PARAMETER ANALOG Gamma Output Swing—High Gamma Output Swing—Low VCOM Buffer Output Swing—High VCOM Buffer Output Swing—Low Output Current REFH Input Range(1) REFL Input Range(1) Integral Nonlinearity Differential Nonlinearity Gain Error Program-to-Out Delay Output Accuracy over Temperature Input Resistance at REFH and REFL Load Regulation, All References 40mA, All Channels ANALOG POWER SUPPLY Operating Range Total Analog Supply Current over Temperature DIGITAL Logic 1 Input Voltage Logic 0 Input Voltage Logic 0 Output Voltage Input Leakage Clock Frequency DIGITAL POWER SUPPLY Operating Voltage Range Digital Supply Current(2) over Temperature TEMPERATURE Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Resistance, HTSSOP-32 Junction-to-Ambient Junction-to-Case CONDITIONS OUT1−9, REFH OUT, Sourcing 10mA, VREFH = 17.8V, Code 1023 OUT10−14, REFL OUT, Sourcing 10mA, VREFH = 17.8V, Code 1023 OUT1−9, REFH OUT, Sinking 10mA, VREFL = 0.2V, Code 00 OUT10−14, REFL OUT, Sinking 10mA, VREFL = 0.2V, Code 00 VCOM, Sourcing 100mA, VREFH = 17.8V VCOM, Sinking 100mA, VREFL = 0.2V All Channels, Code 512, Sinking/Sourcing MIN 17.7 17.0 TYP MAX UNIT
INL DNL tD
No Load, VREFH = 17V, VREFL = 1V No Load, VREFH = 17V, VREFL = 1V
No Load, VREFH = 17V, VREFL = 1V RINH REG
VOUT = VS/2, IOUT = +5mA to −5mA Step VOUT = VS/2, ISINKING = 40mA, ISOURCING = 40mA
17.8 V 17.2 V 0.6 1.0 V 0.2 0.3 V 13 15.5 V 1 2 V See Typical Characteristic Curve 4 VS V GND VS − 4 V 0.3 1.5 Bits 0.3 1 Bits 0.12 % 5 µs ±20 ±50 mV ±25 mV 100 MΩ 0.5 1.5 mV/mA 0.5 1.5 mV/mA 8.5 18 28 28 V mA mA V V V µA kHz MHz V µA µA °C °C °C °C/W °C/W
VS IS
No Load
18
VIH VIL VOL fCLK
0.7 • VSD ISINK = 3mA Standard/Fast Mode High-Speed Mode 2.0 No-Load, Two-Wire Bus Inactive 25 100 −40 −40 −65 25 10 0.15 ±0.01 0.3 • VSD 0.4 ±10 400 3.4 5.5 50
VSD ISD
Junction Temperature < +125°C
+85 +95 +150
qJA qJC
(1) See the REFH and REFL Input Range section in the Application Information. (2) See typical characteristic curve, Digital Supply Current vs Two-Wire Bus Activity.
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BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = 18V, VSD = 5V, VREFH = 17V, VREFL = 1V, RL = 1.5kΩ connected to ground, and CL = 200pF, unless otherwise noted.
ANALOG SUPPLY CURRENT vs TEMPERATURE 20 18 16 Analog IQ (mA) Digital IQ (µA) 14 12 10 8 6 4 2 0 − 40 − 20 0 20 40 60 80 100 Temperature (_ C) 0 − 40 VS = 10V VS = 18V 30
DIGITAL SUPPLY CURRENT vs TEMPERATURE VS = 5V 25 20 15 10 5
VS = 3.3V
− 20
0
20
40
60
80
100
Temperature (_ C)
Figure 1
FULL−SCALE OUTPUT SWING 18 REFH = 17V REFL = 1V Output Voltage (5V/div) Code 3FF →000 Output Voltage (V) 17 16 15
Figure 2
OUTPUT VOLTAGE vs OUTPUT CURRENT
OUT10−14 (sourcing), Code = 3FFh VREFL = 0.2V, VREFH = 17V RLOAD Connected to GND OUT1−9, VCOM1−2 (sourcing) Code = 3FFh VREFL = 1V, V REFH = 17.8V RLOAD Connected to GND OUT10−14 (sinking), Code = 000h VREFL = 0.2V, VREFH = 17V RLOAD Connected to 18V
3 2 1 0
OUT1−9, VCOM 1−2 (sinking) Code = 000h VREFL = 1V, VREFH = 17.8V RLOAD Connected to 18V
Code 000 →3FF
Time (1µs/div)
0
10
20
30
40
50
60
70
80
90
100
Output Current (mA)
Figure 3
INTEGRAL NONLINEARITY ERROR vs INPUT CODE 0.6 0.4 0.2 0 − 0.2 − 0.4 − 0.6 0 200 400 600 800 1000 Input Code DNL Error (LSB) INL Error (LSB) 0.6 0.4 0.2 0 − 0.2 − 0.4 − 0.6 0 200
Figure 4
DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE
400
600
800
1000
Input Code
Figure 5
Figure 6
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BUF16820
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APPLICATIONS INFORMATION
The BUF16820 programmable voltage reference allows fast and easy adjustment of 14 programmable reference outputs and two channels for VCOM adjustment, each with 10-bit resolution. It allows very simple, time-efficient adjustment of the gamma reference and VCOM voltages. The BUF16820 is programmed through a high-speed, standard, two-wire interface. The BUF16820 features a double-register structure for each DAC channel to simplify the implementation of dynamic gamma control. This structure allows pre-loading of register data and rapid updating of all channels simultaneously. Buffers 1−9 are able to swing to within 200mV of the positive supply rail, and to within 0.6V of the negative supply rail. Buffers 10−14 are able to swing to within 0.8V of the positive supply rail and to within 200mV of the negative supply rail. The BUF16820 can be powered using an analog supply voltage from 8.5V to 18V, and a digital supply from 2V to 5.5V. The digital supply must be applied prior to, or simultaneously with, the analog supply to avoid excessive current and power consumption; damage to the device may occur if it is left connected only to the analog supply for extended periods of time. Figure 7 shows the power supply timing requirements.
communication is called a master, and the devices controlled by the master are slaves.The master generates the serial clock on the clock signal line (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a HIGH to a LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the 9th clock pulse, the slave being addressed responds to the master by generating an acknowledge and pulling SDA LOW. Data transfer is then initiated and eight bits of data are sent followed by an acknowledge bit. During data transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH will be interpreted as a START or STOP condition. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The BUF16820 can act only as a slave device; therefore, it never drives SCL. The SCL pin is only an input for the BUF16820. Table 1 and Table 2 summarize the address and command codes, respectively, for the BUF16820.
Table 1. Quick-Reference Table of Addresses
VSD Digital Supply: GND D VS Analog Supply: GND t1 t1: 0s minimum delay between Digital Supply and Analog Supply.
DEVICE/COMPONENT BUF16820 Address: A0 pin is LOW (device will acknowledge on address 74h) A0 pin is HIGH (device will acknowledge on address 75h)
ADDRESS
1110100 1110101
Table 2. Command Codes Quick-Reference
COMMAND General Call Reset CODE Address byte of 00h followed by a data byte of 06h. 00001xxx , with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code.
Figure 7. Power Supply Timing Requirements
Figure 8 shows the BUF16820 in a typical configuration. In this configuration, the BUF16820 device address is 74h. The output of each digital-to-analog converter (DAC) is immediately updated as soon as data are received in the corresponding register (LD = 0). For maximum dynamic range, set VREFH = VS − 0.2V, and VREFL = GND + 0.2V.
High-Speed Mode
ADDRESSING THE BUF16820
The address of the BUF16820 is 111010x, where x is the state of the A0 pin. When the A0 pin is LOW, the device will acknowledge on address 74h (1110100). If the A0 pin is HIGH, the device will acknowledge on address 75h (1110101). Other valid addresses are possible through a simple mask change. Contact your TI representative for information.
TWO-WIRE BUS OVERVIEW
The BUF16820 communicates through an industrystandard, two-wire interface to receive data in slave mode. This standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus lines are driven to a logic low level only. The device that initiates the
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BUF16820
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BUF16820
(1)
VCOM2
1
VCOM2
(1)
VCOM1
32
VCOM1
VS
2
REFH
REFL
31
VS
(1)
3
OUT1
REFL OUT
30
(1)
4
OUT2
NC
29
(1)
5 Source Driver
OUT3
NC
28
(1)
6
OUT4
(1)
OUT14
27
Source Driver
(1)
7
OUT5
GNDA(2)
26
(1)
8
OUT6
VS
25
100nF
(1)
10µF
VS
9
GNDA(2)
OUT13
24
VS
(1)
100nF
(1)
10µF
10
VS
OUT12
23 Source Driver
11
OUT7
(1)
OUT11
22
Source Driver
(1)
(1)
12
OUT8
OUT10
21
(1)
13
OUT9
GNDD(2)
20
14
REFH OUT
LD
19
3.3V
1µ F
15 100nF
VSD
A0
18
16 Timing Controller
SCL
SDA
17
(1) RC combination optional. (2) GNDD and GNDA are internally connected and must be at the same voltage potential.
Figure 8. Typical Application Configuration
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BUF16820
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DATA RATES
The two-wire bus operates in one of three speed modes:
D D D
Standard—allows a clock frequency of up to 100kHz; Fast—allows a clock frequency of up to 400kHz; High-speed—allows a clock frequency of up to 3.4MHz.
The BUF16820 resets all outputs to the OTP memory values (or to 0000 if the OTP values have not been programmed) when the device address is sent, followed by a valid DAC address with bits D7 to D5 set to ‘100’. If these bits are set to ‘010’, only the DAC being addressed in this most significant byte and the following least significant byte will be reset.
The BUF16820 is fully compatible with all three modes. No special action is required to use the device in Standard or Fast modes, but High-speed (Hs) mode must be activated. To activate Hs mode, send a special address byte of 00001xxx, with SCL = 400kHz, following the START condition; where xxx are bits unique to the Hs-capable master, which can be any value. This byte is called the Hs master code. (Note that this is different from normal address bytes—the low bit does not indicate read/write status.) The BUF16820 will respond to the Hs command regardless of the value of these last three bits. The BUF16820 will not acknowledge this byte; the communication protocol prohibits acknowledgement of the Hs master code. Upon receiving a master code, the BUF16820 will switch on its Hs mode filters, and communicate at up to 3.4MHz. Additional high-speed transfers may be initiated without resending the Hs mode byte by generating a repeat START without a STOP. The BUF16820 will switch out of Hs mode with the next STOP condition.
OUTPUT VOLTAGE
Buffer output values are determined by the reference voltages (VREFH and VREFL) and the decimal value of the binary input code used to program that buffer. The value is calculated using Equation (1):
VOUT + VREFH * VREFL 1024 Decimal Value of Code ) VREFL
(1)
The valid voltage ranges for the reference voltages are:
4V v V REFH v VS * 0.2V and 0.2V v VREFL v VS * 4V
(2)
The BUF16820 outputs are capable of a full-scale voltage output change in typically 5µs—no intermediate steps are required.
OUTPUT LATCH
Updating the DAC register is not the same as updating the DAC output voltage, because the BUF16820 features a double-buffered register structure. There are three methods for latching transferred data from the storage registers into the DACs to update the DAC output voltages. Method 1 requires externally setting the latch pin (LD) LOW, LD = LOW, which updates each DAC output voltage whenever its corresponding register is updated. Method 2 externally sets LD = HIGH to allow all DAC output voltages to retain their values during data transfer until LD = LOW, which then simultaneously updates the output voltages of all DACs to the new register values. Use this method to transfer a future data set in advance to prepare for a very fast output voltage update. Method 3 uses software control. LD is maintained HIGH, and all DACs are updated when the master writes a ‘1’ in bit 15 and a ‘0’ in bit 14 of any DAC register. The update occurs after receiving the 16-bit data for the currently-written register. The General Call Reset or a reset upon power-up updates the DAC regardless of the state of the latch pin.
GENERAL CALL RESET AND POWER-UP
The BUF16820 responds to a General Call Reset, which is an address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110). The BUF16820 acknowledges both bytes. Upon receiving a General Call Reset, the BUF16820 performs a full internal reset, as though it had been powered off and then on. It always acknowledges the General Call address byte of 00h (0000 0000), but does not acknowledge any General Call data bytes other than 06h (0000 0110). The BUF16820 automatically performs a reset upon power-up. As part of the reset, the BUF16820 is configured for all outputs to change either to the programmed OTP memory values, or to 0000 if the OTP values have not been programmed.
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ACQUIRE OF OTP MEMORY
A general acquire command updates all registers and DAC outputs to the values stored in OTP memory. A single channel acquire command updates only the register and DAC output of the DAC corresponding to the DAC address used in the command.
READ/WRITE OPERATIONS
Single or mutiple read and write operations can be done in a single communication transaction. Writing to a DAC register differs from writing to the OTP memory. Bits D15−D14 of the most significant byte of data determine if data will be written to the DAC register or the OTP memory. See Figure 9 through Figure 11 for the timing diagrams and requirements for read/write commands.
General Acquire Command 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF16820 will acknowledge this byte. 3. Send a DAC address byte. Bits D7−D5 must be set to 100. Bits D4−D0 are any valid DAC address. Only addresses 00000 to 01101, 10010, 10011, and 10100 are valid and will be acknowledged. Table 3 shows the DAC addresses. 4. Send a STOP condition on the bus.
Following this command, all DAC registers and DAC outputs change to the OTP memory values.
Read/Write: DAC register
The BUF16820 is able to read from a single DAC or multiple DACs, or write to the register of a single DAC or multiple DACs in a single communication transaction. DAC addresses begin with 00000 (corresponding to DAC_1) and continue through 01101 (corresponding to DAC_14). Addresses 10010 and 10011 correspond to VCOM1 and VCOM2, respectively. Address 10100 corresponds to the write disable bit. Write commands are performed by setting the read/write bit LOW. Setting the read/write bit HIGH performs a read transaction.
Single Channel Acquire Command 1. Send a START condition on the bus. 2. Send the device address and read/write bit = LOW. The BUF16820 will acknowledge this byte. 3. Send a DAC address byte using the DAC address corresponding to the DAC output and register to update with the OTP memory value. Bits D7−D5 must be set to 010. Bits D4−D0 denote the address. Only addresses 00000 to 01101, 10010, 10011, and 10100 are valid and will be acknowledged. Table 3 shows the DAC addresses. 4. Send a STOP condition on the bus.
See Figure 12 for the timing diagrams for the acquire commands.
Writing: To write to a single DAC register:
1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF16820 will acknowledge this byte. Send the DAC or write disable bit address byte. Bits D7−D5 must be set to 0. Bits D4−D0 denote the address. Only addresses 00000 to 01101, 10010,
10011, and 10100 are valid and will be acknowledged. Table 3 shows the DAC addresses.
4. Send two bytes of data for the specified register. Begin by sending the most significant byte first (bits D15−D8, of which only bits D9 and D8 are used, and bits D15−D14 must not be 01), followed by the least significant byte (bits D7−D0). For address 10100, only D0 has meaning. This bit is the write disable bit. The register is updated after receiving the second byte. Send a STOP condition on the bus.
Table 3. DAC Register Addresses
DAC DAC_1 DAC_2 DAC_3 DAC_4 DAC_5 DAC_6 DAC_7 DAC_8 DAC_9 DAC_10 DAC_11 DAC_12 DAC_13 DAC_14 VCOM1 VCOM2 Write Disable Bit
ADDRESS
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 10010 10011 10100
5.
The BUF16820 acknowledges each data byte. If the master terminates communication early by sending a STOP or START condition on the bus, the specified register will not be updated. Updating the DAC register is not the same as updating the DAC output voltage; see the Output Latch section. The process of updating multiple DAC registers begins the same as when updating a single register. However, instead of sending a STOP condition after writing the addressed register, the master continues to send data for the next register. The BUF16820 automatically and sequentially steps through subsequent registers as
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additional data are sent. The process continues until all desired registers have been updated or a STOP condition is sent.
4. 5.
Send a START or STOP/START condition. Send correct device address and read/write bit = HIGH. The BUF16820 will acknowledge this byte. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte (bits D15−D8; only bits D9 and D8 have meaning), and the next byte is the least significant byte (bits D7−D0). Acknowledge after receiving the first byte. Send a STOP condition on the bus or do not acknowledge the second byte to end the read transaction.
To write to multiple DAC registers:
1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF16820 will acknowledge this byte. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC will be the first in the sequence of DACs to be updated. The BUF16820 will begin with this DAC and step through subsequent DACs in sequential order. Send the bytes of data. Begin by sending the most significant byte (bits D15−D8, of which only bits D9 and D8 have meaning, and bits D15−D14 must not be 01), followed by the least significant byte (bits D7−D0). The first two bytes are for the DAC addressed in step 3. Its register is automatically updated after receiving the second byte. The next two bytes are for the following DAC; that DAC register is updated after receiving the fourth byte. This process continues until the registers of all following DACs have been updated. The BUF16820 will continue to accept data for a total of 20 DACs; however, the four data sets following the 14th data set will be meaningless. The 19th and 20th data sets will apply to VCOM1 and VCOM2. The write disable bit cannot be accessed using this method. It must be written to using the write to a single DAC register procedure. Send a STOP condition on the bus. 4. 5. 6.
7. 8.
4.
Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge.
To Read Multiple DACs:
1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF16820 will acknowledge this byte. Send either the DAC_1 address byte to start at the first DAC, or send the address byte for whichever DAC will be the first in the sequence of DACs to be read. The BUF16820 will begin with this DAC and step through subsequent DACs in sequential order. The BUF16820 will continue to accept data for a total of 20 DACs; however, the four data sets following the 14th data set will be meaningless. The 19th and 20th data sets will apply to VCOM1 and VCOM2. Send a START or STOP/START condition on the bus. Send correct device address and read/write bit = HIGH. The BUF16820 will acknowledge this byte. Receive two bytes of data. They are for the specified DAC. The first received byte is the most significant byte (bits D15−D8; only bits D9 and D8 have meaning), and the next byte is the least significant byte (bits D7−D0). Acknowledge after receiving each byte. When all desired DACs have been read, send a STOP or START condition on the bus.
5.
The BUF16820 acknowledges each byte. To terminate communication, send a STOP or START condition on the bus. Only DAC registers that have received both bytes of data will be updated.
Reading:
Reading a DAC register returns the data stored in the DAC. This data can differ from the data stored in the DAC register; see the Output Latch section.
6.
To read the DAC value:
1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF16820 will acknowledge this byte. Send the DAC address byte. Bits D7−D5 must be set to 0; Bits D4−D0 are the DAC address. Only
7. 8.
addresses 00000 to 01101, 10010, 10011, and 10100 are valid and will be acknowledged. For
address 10100, only D0 has meaning. This bit is the write disable bit.
Communication may be terminated by sending a premature STOP or START condition on the bus, or by not sending the acknowledge.
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Write: OTP Memory for the DAC Register
The BUF16820 is able to write to the OTP memory of a single DAC, or multiple DACs in a single communication transaction. DAC addresses begin with 00000 (corresponding to DAC_1) through 01101 (corresponding to DAC_14). Addresses 10010 and 10011 correspond to VCOM1 and VCOM2, respectively. Address 10100 corresponds to the write disable bit. When programming the OTP memory, the analog supply voltage must be between 8.5V and 18V. Write commands are performed by setting the read/write bit LOW.
To write to multiple OTP registers:
1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF16820 will acknowledge this byte. Send either the DAC_1 address byte to start at the OTP register of the first DAC, or send the address byte for whichever DAC will be the first in the sequence to be updated. The BUF16820 will begin with the OTP register of this DAC and step through subsequent registers in sequential order. Send the bytes of data. Begin by sending the most significant byte (bits D15−D8, of which only bits D9 and D8 have meaning, and bits D15−D14 must be 01), followed by the least significant byte (bits D7−D0). The first two bytes are for the OTP register of the DAC addressed in step 3. This OTP register is automatically updated after receiving the second byte. The next two bytes are for the OTP register of the following DAC (bits D15−D14 must again be 01). That DAC OTP register is updated after receiving the fourth byte. This process continues until the registers of all following DAC OTP registers have been updated. The BUF16820 will continue to accept data for a total of 20 DACs; however, the four data sets following the 14th data set will be meaningless. The 19th and 20th data sets will apply to VCOM1 and VCOM2. The write disable bit cannot be accessed using this method. It must be written to using the write to a single OTP register procedure. Send a STOP condition on the bus.
4.
To write to a single OTP register:
1. 2. 3. Send a START condition on the bus. Send the device address and read/write bit = LOW. The BUF16820 will acknowledge this byte. Send the DAC address byte. Bits D7−D5 must be set to 0. Bits D4−D0 are the DAC address. Only
addresses 00000 to 01101, 10010, 10011, and 10100 are valid and will be acknowledged. Table 3 shows the DAC addresses.
4. Send two bytes of data for the OTP register of the specified DAC. Begin by sending the most significant byte first (bits D15−D8, of which only bits D9 and D8 are data bits, and bits D15−D14 must be 01), followed by the least significant byte (bits D7−D0). For address 10100, only D0 has meaning. This bit is the write disable bit. The register is updated after receiving the second byte. Send a STOP condition on the bus.
5.
5.
The BUF16820 will acknowledge each data byte. If the master terminates communication early by sending a STOP or START condition on the bus, the specified OTP register will not be updated. Writing to an OTP register also updates the DAC register and output voltage.
The BUF16820 will acknowledge each byte. To terminate communication, send a STOP or START condition on the bus. Only DAC registers that have received both bytes of data are programmed.
OTP WRITE DISABLE
Writing a ‘1’ in bit D0 of register 10100 disables all future writes. The state of this bit can be accessed the same as any other data bit. It is important to set this bit to ‘1’ after the OTP registers have been programmed in order to prevent accidental changes to the OTP registers. Until bit D0 of register 10100 is set to ‘1’, any OTP register bit can be changed from ‘0’ to ‘1’; however, once a bit is set to a ‘1’, it cannot be set back to ‘0’.
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Write single DAC register. P4−P0 specify DAC address. Write Ackn DAC address pointer. D7−D5 must be 000. Ackn DAC MSbyte. D14 must be 0. Ackn DAC LSbyte
Write Operation Ackn Stop
Start
Device Address
SCL
SDA_in
A c kn A c kn A c kn
A6
A5
A4
A3
A2
A1
A0
W
D7
D6
D5
P4
P3
P2
P1
P0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A ck n
Device_out
A c kn A c kn A c kn
A6 If D15 = 0, the DACs are updated on the Latch pin. If D15 = 1, all DACs are updated when the current DAC register is updated.
A5
A4
A3
A2
A1
A0
W
D7
D6
D5
P4
P3
P2
P1
P0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A ck n
Device_out
a. Write Single DAC
Write Operation Write Ackn Start DAC address pointer. D7−D5 must be 000. Ackn DAC (pointer) MSbyte. D14 must be 0. Ackn DAC (pointer) LSbyte A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 If D15 = 0, the DACs are updated on the Latch pin. If D15 = 1, all DACs are updated when the current DAC register is updated. MSbyte of last DAC.D14 must be 0. . Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 If D15 = 0, the DACs are uploaded on the Latch pin. If D15 = 1, all the DACs are updated when the current DAC register is updated.
The whole DAC register D9−D0 is updated in this moment.
Write multiple DAC registers. P4−P0 specify start DAC address.
Start
Device Address
Ackn DAC (pointer + 1) MSbyte. D14 must be 0.
SCL
SDA_in
A6
A5
A4
A3
D0
Ackn
D15
D14
D13
A6
A5
A4
A3
D0
Ackn
D15
D14
D13
Figure 9. Timing Diagram for Write DAC Register
The whole DAC register D9−D0 is updated in this moment.
LSbyte of last DAC.
Ackn
Stop
D4
D3
D2
D1
D0
Ackn
b. Write Multiple DACs
D4
D3
D2
D1
D0
Ackn
The whole DAC register D9−D0 is updated in this moment.
SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
BUF16820
11
12
Read Operation Write
No Ackn
BUF16820
Read single DAC register. P4−P0 specifyDAC address. Ackn DAC address pointer. D7−D5 must be 000. Ackn Start Device Address Read Ackn DAC MSbyte. D15−D10 have no meaning. Ackn DACLSbyte.
Start
Device Address
Stop
SCL A1
Ackn Ackn Ackn
SDA_in A1
Ackn
A6 A0 D7
Ackn Ackn
A5 W D6 D5 P4 P3 P2 P1 P0 A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
A4
A3
A2
A0
W
D7
D6
D5
P4
P3
P2
P1
P0
A6
A5
A4
A3
A2
A1
A0
R
Ackn
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 D0
Device_out
A6
A5
A4
A3
A2
SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
a. Read Single DAC
Read Operation Write Ackn Start DAC address pointer. D7−D5 must be 000. Ackn Start Device Address Read Ackn DAC (pointer) MSbyte. D15−D10 have no meaning. Ackn A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 R Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn MSbyte of last DAC.D15−D10 have no meaning. Ackn LSbyte of last DAC.
No Ack n
Read multiple DAC registers. P4−P0 specify start DAC address.
Start
Device Address
SCL
SDA_in
A6
A5
A4
A3
Device_out
A6
A5
A4
A3
Figure 10. Timing Diagram for Read DAC Register
D15 D14 D13 D12 D11 D10 D9 D8
A c kn
Stop
D7
D6
D5
D4
D3
D2
D1
D0
b. Read Multiple DACs
D15
D14
D13
D12
D11
D10
D9
D8
A c kn
D7
D6
D5
D4
D3
D2
D1
D0
A ck n
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t1 t2
Ackn Stop Write Operation Write Ackn DAC address pointer. D7−D5 must be 000. Ackn DAC(pointer) MSByte. D15−D14 must be 01. Ackn DAC (pointer) LSbyte Write SupplyActive Write Signal Active
Write single OTP register. P4−P0 specify DAC address.
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Start
Device Address
SCL
SDA_in
A6
A5
A4
A3
A2
A1
A0
W
Ackn
D7
D0
D5
P4
P3
P2
P1
P0
Ackn
D15
D14
D13
D12
D11
D10
D9
D8
Ackn
D7
D6
D5
D4
D3
D2
D1
D0
Ackn
Device_out
A6
A5
A4
A3
A2
A1
A0
W
Ackn
D7
D0
D5
P4
P3
P2
P1
P0
Ackn
D15
D14
D13
D12
D11
D10
D9
D8
Ackn
D7
D6
D5
D4
D3
D2
D1
D0
Ackn
SCL
SDA_in
Device_out A2 A1 A0 W Ackn D7 D0 D5 P4 P3 P2 P1 P0 Ackn D15
a) Write Single OTP Register
t1
Write Operation Write Ackn Start DAC address pointer. D7−D5 must be 000. Ackn DAC(pointer) MSByte. D15−D14 must be 01. Ackn Write SupplyActive Write Signal Active DAC (pointer) LSbyte A2 A1 A0 W Ackn D7 D0 D5 P4 P3 P2 P1 P0 Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D4 D3 D2 D1 D0
The OTPregister D9−D0 is updated at this moment. t1: > 20µs before falling edge of clock. t2: minimum100µs, maximum2ms.
t2
Ackn DAC (pointer +1) MSbyte. D15−D14 must be 01.
Write multiple OTP registers. P4−P0 specify start DAC address.
Start
Device Address
A6
A5
A4
A3
Ackn
D15
D14
D13
A6
A5
A4
A3
Ackn
D15
D14
D13
Figure 11. Timing Diagram for Write OTP Register
MSbyte of last DAC.D14−D10 have no meaning. Ackn D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5 D15 D14 D13 D12 D11 D10 D9 D8 Ackn D7 D6 D5
The OTPregister D9−D0 is updated at this moment. t1
Write SupplyActive Write Signal Active LSbyte of last DAC. Ackn Stop
t2
D4
D3
D2
D1
D0
Ackn
b) Write Multiple OTP Registers
D4
D3
D2
D1
D0
Ackn
Thewhole DACregister D9−D0 is updated at this moment. t1: > 20µs beforefalling edge of clock. t2: minimum100µs, maximum2ms.
SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
BUF16820
13
14
General acquire command. P4−P0 must specify any valid DAC addess. Start SCL Device Address Write Ackn DAC address pointer. D7−D5 must be 100. Ackn Stop Write Operation SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn Device_out A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn Device_out
BUF16820
SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
a) General Acquire
Single channel acquire command. P4−P0 must specify any valid DAC addess. Start SCL Device Address Write Ackn Write Operation DAC address pointer. D7−D5 must be 010. Ackn Stop SDA_in A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn A6 A5 A4 A3 A2 A1 A0 W Ackn D7 D6 D5 P4 P3 P2 P1 P0 Ackn
Figure 12. Timing Diagram for Acquire Operation
b) Single-Channel Acquire
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BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
REPLACEMENT OF TRADITIONAL GAMMA BUFFER
Traditional gamma buffers rely on a resistor string (often using expensive 0.1% resistors) to set the gamma voltages. During development, the optimization of these gamma voltages can be time consuming. Programming these gamma voltages with the BUF16820 can significantly reduce the time required for gamma voltage optimization. The final gamma values can be written into the internal OTP memory to replace a traditional gamma buffer solution. Figure 13a shows the traditional resistor string; Figure 13b shows the more efficient alternative method using the BUF16820. The BUF16820 uses the most advanced high-voltage CMOS process available today, which allows it to be competitive with traditional gamma buffers.
Programmability offers the following advantages:
D D D D
Shortens development time significantly. Increases reliability by eliminating more than 18 external components. Eliminates manufacturing variance between panels. Allows a single panel to be built for multiple customers, with loading of customer-dependent gamma curves during final production. This method significantly lowers inventory cost and risk, and simplifies inventory management. Allows demonstration of various gamma curves to LCD monitor makers by simply uploading a different set of gamma values. Allows simple adjustment of gamma curves during production to accommodate changes in the panel manufacturing process or end-customer requirements. Decreases cost and space.
D D
D
a) Traditional BUFxx704 b) BUF16820 Solution
BUF16820 VCOM1 VCOM VCOM2 Timing Controller PC Register SDA SCL
OUT1
OUT2
Gamma References OUT13
OUT14
SDA Control Interface SCL LCD Panel Electronics
Figure 13. Replacement of the Traditional Gamma Buffer
15
BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
PROGRAMMABLE VCOM
The VCOM channels of the BUF16820 can swing to 2.5V from the positive supply rail while sourcing 100mA, and to 1V above the negative rail while sinking 100mA (see Figure 4, typical characteristic Output Voltage vs Output Current). The gamma and the VCOM values can be permanently stored in the internal OTP memory. The VCOM channels can be programmed independantly from the gamma channels. Figure 14 shows the BUF16820 being used for VCOM voltages.
REFH AND REFL INPUT RANGE
Best performance and output swing range of the BUF16820 are achieved by applying REFH and REFL voltages that are slightly below the power-supply voltages. Most specifications have been tested at REFH = VS − 200mV and REFL = GND + 200mV. The REFH internal buffer is designed to swing very closely to VS, and the REFL internal buffer to GND. However, there is a finite limit on how close they can swing before saturating. To avoid saturation of the internal REFH and REFL buffers, the REFH voltage should not be greater than VS −100mV and REFL voltage should not be lower than GND + 100mV. Figure 15 shows the swing capability of the REFH and REFL buffers.
18 17 Output Voltage (V) 16
REFH OUT (sourcing)
15
BUF16820 VCOM1 VCOM VCOM2
3 2
REFH OUT (sinking)
1 OUT1 Register 0 0 OUT2 10 20 30 40 50 60 70 80 90 100 Output Current (mA)
Gamma References OUT13
Figure 15. Reference Buffer Output Voltage vs Output Current
The other consideration when trying to maximize the output swing capability of the gamma buffers is the limitation in the swing range of output buffers (OUT1−14, VCOM1, and VCOM2), which depends on the load current. A typical load in the LCD application is 5mA to 10mA. For example, if OUT1 is sourcing 10mA, the swing is typically limited to about VS − 200mV. The same applies to OUT14, which typically limits at GND + 200mV when sinking 10mA. An increase in output swing can only be achieved for much lighter loads. For example, a 3mA load typically allows the swing to be increased to approximately VS − 100mV and GND + 100mV. Connecting REFH directly to VS and REFL directly to GND does not damage the BUF16820. As discussed above however, the output stages of the REFH and REFL buffers will saturate. This condition is not desirable and can result in a small error in the measured output voltages of OUT1−14, VCOM1, and VCOM2. As described above, this method of connecting REFH and REFL does not help to maximize the output swing capability.
OUT14
SDA Control Interface SCL
Figure 14. BUF16820 Used for Programmable VCOM
16
BUF16820
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CONFIGURATION FOR 16 GAMMA CHANNELS
The VCOM outputs can be used as additional gamma references in order to achieve two additional gamma channels (16 total). The VCOM outputs will behave the same as the OUT1−9 outputs when sourcing or sinking smaller currents (see the Typical Characteristics, Figure 4). The VCOM outputs are better able to swing to the positive rail than to the negative rail. Therefore, it is better to use the VCOM outputs for higher reference voltages, as shown in Figure 16.
CONFIGURATION FOR 18 GAMMA CHANNELS
In addition to the VCOM outputs, the REFH and REFL OUT outputs can also be used as fixed gamma references. The output voltage is set by the REFH and REFL input
18V 2V to 5.5V Digital BUF16820 Analog
voltages, respectively. Therefore, REFH OUT should be used for the highest voltage gamma reference, and REFL OUT for the lowest voltage gamma reference. An 18-channel solution can be created by using all 14 outputs, the two VCOM outputs, and both REFH/L OUT outputs for gamma references; see Figure 17. However, the REFH and REFL OUT buffers were designed to only drive light loads on the order of 5mA to 10mA. Driving capacitive loads is not recommended with these buffers. In addition, the REFH and REFL buffers must not be allowed to saturate from sourcing/sinking too much current from REFH OUT or REFL OUT. Saturation of the REFH and REFL buffers results in errors in the voltages of OUT1−14, VCOM1, and VCOM2. The BUF01900 (anticipated release in Q2 ‘06), can be used to provide a programmable VCOM output.
17.8V
REFH
REFH OUT 17V
Source Driver
VCOM 1
GMA 1
VCOM 2
GMA 2
OUT1 DAC Registers 1 DAC Registers 2
GMA 3
OTP Memory
OUT2
GMA 4
Program Command
2 VCOM Channels plus 14 Gamma Channels
OUT13
GMA 15
OUT14 GMA 16 REFL OUT 0.2V Control IF
SDA SCL
LD
A0
REFL
18V 0.2V
Figure 16. 16 Gamma Channel Solution—2 VCOM Channels Used as Additional Gamma Channels
17
BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
18V 2V to 5.5V 17.8V Reference buffer and VC OM outputs can be used for extra gamma channels. Digital BUF16820 Analog REFH (REFH OUT will be a fixed voltage.) Source Driver GMA 1
REFH OUT 17V
VC OM1
GMA 2
VC OM2
GMA 3
OUT1
GMA 4
DAC Registers 1
DAC Registers 2
Program Command
OTP Memory
OUT2
GMA 5
2 VC OM Channels plus 14 Output Channels
OUT13 GMA 16
OUT14 GMA 17 REFL OUT 0.2V GMA 18 Control IF Panel LD A0 REFL Output of reference buffer can be used for an extra fixed gamma channel. 0.2V 2V to 5.5V Digital BUF01900 Program Command Voltage Regulator 18V Analog BIAS VC OM
SDA SCL
18V
250kΩ 4 x OTP ROM Switch Control 10−Bit DAC
VCOM Buffer
VCOM OUT
SDA SCL Control IF
A0
Figure 17. 18-Gamma Channel Solution
18
BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
DYNAMIC GAMMA CONTROL
Dynamic gamma control is a technique used to improve the picture quality in LCD TV applications. The brightness in each picture frame is analyzed and the gamma curves are adjusted on a frame-by-frame basis. The gamma curves are typically updated during the short vertical blanking period in the video signal. Figure 18 shows a block diagram using the BUF16820 for dynamic gamma control and VCOM output. The BUF16820 is ideally suited for rapidly changing the gamma curves because of its unique topology:
The double register input structure saves programming time by allowing updated DAC values to be pre-loaded into the first register bank. Storage of this data can occur while a picture is still being displayed. Since the data are only stored into the first register bank, the DAC output values remain unchanged—the display is unaffected. During the vertical sync period, the DAC outputs (and therefore, the gamma voltages) can be quickly updated either by using an additional control line connected to the LD pin, or through software—writing a ‘1’ in bit 15 of any DAC register. For the details on the operation of the double register input structure, see the Output Latch section. Example: Update all 14 gamma registers simultaneously via software. Step 1: Check if LD pin is placed in HIGH state. Step 2: Write DAC Registers 1−14 with bit 15 always ‘0’. Step 3: Write any DAC register a second time with identical data. Make sure that bit 15 is ‘1’. All DAC channels will be updated simultaneously after receiving the last bit of data. (Note: this step may be eliminated by setting bit 15 of DAC 14 to ‘1’ in the previous step.)
D Double register input structure to the DAC. D Fast serial interface. D Simultaneous updating of all DACs by software.
See the Read/Write Operations and the Output Latch sections.
Histogram Digital Picture Data
Black White
Gamma Adjustment Algorithm
SDA
BUF16820 Gamma References 1 through 14
SCL
Timing Controller/µ Controller Source Driver Source Driver VCOM
Figure 18. Dynamic Gamma Control
19
BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
TOTAL TI PANEL SOLUTION
In addition to the BUF16820 programmable voltage reference, TI offers a complete set of ICs for the LCD panel market, including gamma correction buffers, various power-supply solutions, and audio power solutions. See Figure 19 for the total IC solution from TI.
outputs, and other functions. The BUF16820, with its 16 total programmable DAC channels, provides great flexibility to the entire system by allowing the designer to change all these parameters via software. Figure 20 provides various examples of how the BUF16820 can be used in applications. A microcontroller with a two-wire serial interface controls the various DACs of the BUF16820. The BUF16820 can be used for:
THE BUF16820 IN INDUSTRIAL APPLICATIONS
The wide supply range, high output current, and very low cost make the BUF16820 attractive for a range of medium accuracy industrial applications such as programmable power supplies, multi-channel data-acquisition systems, data-loggers, sensor excitation and linearization, power-supply generation, and more. Each DAC channel features 1LSB DNL and INL. Many systems require different levels of biasing and power supply for various components, as well as sensor excitation, control-loop set-points, voltage outputs, current
D D D D D D
Sensor excitation Programmable bias/reference voltages Variable power-supplies High-current voltage output 4-20mA output Set-point generators for control loops
NOTE: At power-up, the output voltages of the BUF16820 DACs are set to either the programmed OTP memory values, or to 0000 if the OTP values have not been programmed.
Gamma Correction BUF16820 2.7V to 5V TPS651xx LCD Supply 15V 26V − 14V
VCOM
3.3V TPA30xx Audio Speaker Driver
n Source Driver
n
Gate Driver
Logic and Timing Controller
High−Resolution TFT−LCS Panel
Figure 19. TI LCD Solution
20
BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
+18V
+5V
BUF16820 Voltage Output High Current Voltage Output Control-Loop Set-Point 4−20mA +5V 4−20mA Generator Bias Voltage Generator +2.5V Bias 0.3V to 17V +5V
2V to 16V, 100mA Sensor Excitation/Linearization
LED Driver Offset Adjustment INA
Ref +4V +4.3V Comparator Threshold Supply Voltage Generator
Ref Reference for MDAC +7.5V SDA SCL MDAC µC
Figure 20. Industrial Applications for the BUF16820
21
BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
EVALUATION BOARD AND SOFTWARE
An evaluation board is available for the BUF16820, as shown in Figure 21. The evaluation board features easy-to-use software that allows individual channel
voltages to be set. Configurations can be quickly evaluated to determine optimal codes for a given application. Contact your local TI representative for more information regarding the evaluation board.
Figure 21. Evaluation Board
22
BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
GENERAL POWERPAD DESIGN CONSIDERATIONS
The BUF16820 is available in a thermally-enhanced PowerPAD package. This package is constructed using a downset leadframe upon which the die is mounted; see Figure 22(a) and Figure 22(b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 22(c). This thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device. Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications that have low power dissipation. This provides the necessary thermal and mechanical connection between the lead frame die pad and the PCB. The PowerPAD must be connected to the most negative supply voltage on the device, GNDA and GNDD. 1. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as for the thermal pad. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns (3x6) for the HTSSOP-32 DAP package can be seen in the technical brief, PowerPAD Thermally-Enhanced Package (SLMA002), available for download at www.ti.com. These holes should be 13 mils in diameter. Keep them small, so that solder wicking through the holes is not a problem during reflow.
3.
Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the BUF16820 IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered; thus, wicking is not a problem. Connect all holes to the internal plane that is at the same voltage potential as the GND pins. When connecting these holes to the internal plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the BUF16820 PowerPAD package should make their connection to the internal plane with a complete connection around the entire circumference of the plated-through hole. The top-side solder mask should leave the terminals of the package and the thermal pad area with its ten holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking prevents solder from being pulled away from the thermal pad area during the reflow process. Apply solder paste to the exposed thermal pad area and all of the IC terminals. With these preparatory steps in place, the BUF16820 IC is simply placed in position and run through the solder reflow operation as any standard surfacemount component. This preparation results in a properly installed part.
4. 5.
6.
7. 8.
2.
23
BUF16820
www.ti.com SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
DIE
Side View (a)
DIE
End View (b)
Exposed Thermal Pad
Bottom View (c)
NOTE: The thermal pad is electrically isolated from all terminals in the package.
Figure 22. Views of Thermally-Enhanced DCP Package
For a given qJA, the maximum power dissipation is shown in Figure 23, and is calculated by Equation 3:
7 Maximum Power Dissipation (W) 6 5 4 3 2 1 0 −40 − 20 0 20 40 60 80 100 TA, Free−Air Temperature (_ C)
T MAX * T A PD + q JA
Where: PD = maximum power dissipation (W)
(3)
TMAX = absolute maximum junction temperature (+125°C) TA = free-ambient air temperature (°C) qJA = qJC + qCA qJC = thermal coefficient from junction-to-case (°C/W) qCA = thermal coefficient from case-to-ambient air (°C/W)
Figure 23. Maximum Power Dissipation vs Free-Air Temperature (with PowerPAD soldered down)
24
PACKAGE OPTION ADDENDUM
www.ti.com
21-Sep-2006
PACKAGING INFORMATION
Orderable Device BUF16820AIDAPR BUF16820AIDAPRG4
(1)
Status (1) ACTIVE ACTIVE
Package Type HTSSOP HTSSOP
Package Drawing DAP DAP
Pins Package Eco Plan (2) Qty 32 32 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
Reel Diameter (mm) 330
Reel Width (mm) 24
A0 (mm)
B0 (mm)
K0 (mm)
P1 (mm) 12
W Pin1 (mm) Quadrant 24 PKGORN T1TR-MS P
BUF16820AIDAPR
DAP
32
TAI
8.6
11.5
1.6
TAPE AND REEL BOX INFORMATION
Device BUF16820AIDAPR Package DAP Pins 32 Site TAI Length (mm) 336.6 Width (mm) 342.9 Height (mm) 41.3
Pack Materials-Page 2
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