CCB3T16210QDGGRQ1

SN74CB3T16210-Q1 SCDS315 – APRIL 2011 www.ti.com 20-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER Check for Samples: SN74CB3T16210-Q1 FEATURES 1 • • 2 • • • • • • • • • • • • Qualified for Automotive Applications Member of the Texas Instruments Widebus™ Family Output Voltage Translation Tracks VCC Supports Mixed-Mode Signal Operation on All Data I/O Ports – 5-V Input Down to 3.3-V Output Level Shift With 3.3-V VCC – 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V VCC 5-V-Tolerant I/Os With Device Powered Up or Powered Down Bidirectional Data Flow With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typ) Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typ) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 40 μA Max) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation • • Supports Digital Applications: Level Translation, PCI Interface, USB Interface, Memory Interleaving, and Bus Isolation Ideal for Low-Power Portable Equipment DGG PACKAGE (TOP VIEW) NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 NC - No internal connection DESCRIPTION/ORDERING INFORMATION The SN74CB3T16210-Q1 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16210-Q1 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated SN74CB3T16210-Q1 SCDS315 – APRIL 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74CB3T16210-Q1 is organized as two 10-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. It can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE is low, the associated 10-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA –40°C to 125°C (1) TSSOP – DGG ORDERABLE PART NUMBER Reel of 2000 CCB3T16210QDGGRQ1 TOP-SIDE MARKING CB3T16210Q Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (EACH 10-BIT BUS SWITCH) INPUT OE INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect VCC 5.5 V VCC IN 9VCC - 1 V OUT 9VCC 9VCC - 1 V CB3T 0V 0V Input Voltages Output Voltages If the input high voltage (VIH) level is greater than or equal to VCC - 1 V, and less than or equal to 5.5 V, the output high voltage (VOH) level will be equal to approximately the VCC voltage level. Figure 1. Typical DC Voltage Translation Characteristics 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN74CB3T16210-Q1 SN74CB3T16210-Q1 SCDS315 – APRIL 2011 www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) 46 2 1A1 1B1 SW 36 12 1A10 1B10 SW 48 1OE 13 2A1 35 25 24 2A10 2OE 2B1 SW SW 2B10 47 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN74CB3T16210-Q1 3 SN74CB3T16210-Q1 SCDS315 – APRIL 2011 www.ti.com SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) A B VG(1) Control Circuit EN(2) (1) Gate voltage (VG) is equal to approximately VCC + VT when the switch is ON and VI > VCC + VT. (2) EN is the internal enable signal applied to the switch. Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT –0.5 7 V (3) –0.5 7 V (3) (4) –0.5 7 VCC Supply voltage range VIN Control input voltage range (2) VI/O Switch I/O voltage range (2) IIK Control input clamp current VIN < 0 II/OK I/O port clamp current VI/O < 0 IIO ON-state switch current (5) Continuous current through VCC or GND ±100 mA θJA Package thermal impedance Tstg Storage temperature range (1) (2) (3) (4) (5) (6) 4 (6) DGG package –65 V –50 mA –50 mA ±128 mA 70 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN74CB3T16210-Q1 SN74CB3T16210-Q1 SCDS315 – APRIL 2011 www.ti.com Recommended Operating Conditions (1) VCC VIH High-level control input voltage VIL Low-level control input voltage VI/O Data input/output voltage TA Operating free-air temperature (1) MIN MAX 2.3 3.6 VCC = 2.3 V to 2.7 V 1.7 5.5 VCC = 2.7 V to 3.6 V 2 5.5 VCC = 2.3 V to 2.7 V 0 0.7 VCC = 2.7 V to 3.6 V 0 0.8 0 5.5 V –40 125 °C Supply voltage UNIT V V V All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics (1) PARAMETER VIK VCC = 3 V, II = –18 mA VOH See Figure 3 and Figure 4 Control inputs IIN IOZ (3) ΔICC (4) Cin Cio(OFF) Cio(ON) μA 10 μA 40 VI = 5.5 V 40 VCC = 3.3 V, VIN = VCC or GND VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC or GND VCC = 3 V, VI = 0 μA ±10 VI = VCC or GND Control inputs (5) μA ±5 VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0 ±10 ±20 Control inputs VCC = 3.3 V, Switch ON, VIN = VCC or GND V –40 VI/O = 5.5 V or 3.3 V UNIT –1.2 VI = 0.7 V to VCC – 0.7 V VI = 0 to 0.7 V VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND MAX VI = VCC – 0.7 V to 5.5 V VCC = 0, VO = 0 to 5.5 V, VI = 0, ICC (1) (2) (3) (4) (5) TYP (2) VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff ron MIN VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND VCC = 3.6 V, Switch ON, VIN = VCC or GND II TA = –40°C TO 125°C TEST CONDITIONS 300 μA μA 4 pF 5 pF 5 pF VI/O = GND 13 IO = 24 mA 5 11.5 IO = 16 mA 5 11.5 IO = 24 mA 5 10.5 IO = 16 mA 5 10.5 Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN74CB3T16210-Q1 5 SN74CB3T16210-Q1 SCDS315 – APRIL 2011 www.ti.com Switching Characteristics for VCC = 2.5 V ± 0.2 V (see Figure 2) FROM (INPUT) TO (OUTPUT) ten OE A or B tdis OE A or B PARAMETER 6 Submit Documentation Feedback VCC = 2.5 V ± 0.2 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 1 14 1 12 ns 1 9.5 1 10.5 ns Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN74CB3T16210-Q1 SN74CB3T16210-Q1 SCDS315 – APRIL 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator VI S1 RL VO 50 Ω 50 Ω VG2 RL CL (see Note A) TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω 3.6 V or GND 5.5 V or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω 3.6 V 5.5 V 30 pF 50 pF 0.15 V 0.3 V V∆ VCC Output Control (VIN) VCC/2 VCC VCC/2 VCC/2 0V tPLH VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) VCC VCC/2 VOL + V∆ VOL tPZH tPHL VCC/2 0V tPZL Output Control (VIN) Open GND tPHZ Output Waveform 2 S1 at Open (see Note B) VOH VCC/2 VOH - V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 2. Test Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN74CB3T16210-Q1 7 SN74CB3T16210-Q1 SCDS315 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs INPUT VOLTAGE OUTPUT VOLTAGE vs INPUT VOLTAGE 4 VCC = 2.3 V IO = 1 µA TA = 25°C 3 VO - Output Voltage - V VO - Output Voltage - V 4 2 1 0 0 1 2 3 4 5 6 VCC = 3 V IO = 1 µA TA = 25°C 3 2 1 0 0 1 VI - Input Voltage - V 2 3 4 5 6 VI - Input Voltage - V Figure 3. Data Output Voltage vs Data Input Voltage 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN74CB3T16210-Q1 SN74CB3T16210-Q1 SCDS315 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4 3.5 VCC = 2.3 V ~ 3.6 V VI = 5.5 V TA = 85°C 100 µA VOH - Output Voltage High - V VOH - Output Voltage High - V 4 8 mA 3 2.5 16 mA 24 mA 2 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 VCC = 2.3 V ~ 3.6 V VI = 5.5 V TA = 25°C 3.5 8 mA 3 2.5 16 mA 24 mA 2 1.5 2.3 3.7 100 µA 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC - Supply Voltage - V VCC - Supply Voltage - V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE VOH - Output Voltage High - V 4 3.5 VCC = 2.3 V ~ 3.6 V VI = 5.5 V TA = -40°C 100 µA 8 mA 3 16 mA 2.5 24 mA 2 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC - Supply Voltage - V Figure 4. VOH Values Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN74CB3T16210-Q1 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) CCB3T16210QDGGRQ1 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 CB3T16210Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of