CD74HC166E

CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 CDx4HC(T)166 High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register 1 Features 2 Description • • The ’HC166 and ’HCT166 8-bit shift register is fabricated with silicon gate CMOS technology. It possesses the low power consumption of standard CMOS integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky device. • • • • • Buffered inputs Fanout (over temperature range) – Standard outputs: 10 LSTTL Loads – Bus driver outputs: 15 LSTTL Loads Wide operating temperature range: -55℃ to 125℃ Balanced propagation delay and transition time Significant power reduction compared to LSTTL Logic ICs HC Types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V HCT Types – 4.5 V to 5.5 V Operation – Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2 V (Min) B A 1 11 C Device Information PACKAGE BODY SIZE (NOM) CD54HC166F3A CDIP (16) 24.38 mm × 6.92 mm CD54HCT166F3A CDIP (16) 24.38 mm × 6.92 mm CD74HC166M SOIC (16) 9.90 mm × 3.90 mm CD74HCT166M SOIC (16) 9.90 mm × 3.90 mm CD74HC166E PDIP (16) 19.31 mm × 6.35 mm CD74HCT166E PDIP (16) 19.31 mm × 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. D 12 13 1D 1D (1) PART NUMBER E 14 F 15 H G 16 18 17 SH/LD 10 SER 1D C1 C1 R CLK INH CLK R 1D R 1D 1D C1 C1 R R R 1D 1D C1 C1 C1 C1 R R 15 2 1 CLR 13 QH Functional Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings(1) .................................... 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Prerequisite for Switching Characteristics.................. 6 5.6 Switching Characteristics............................................7 6 Parameter Measurement Information............................ 8 7 Detailed Description......................................................10 7.1 Overview................................................................... 10 7.2 Functional Block Diagram......................................... 10 7.3 Device Functional Modes..........................................11 8 Power Supply Recommendations................................12 9 Layout.............................................................................12 9.1 Layout Guidelines..................................................... 12 10 Device and Documentation Support..........................13 10.1 Receiving Notification of Documentation Updates..13 10.2 Support Resources................................................. 13 10.3 Trademarks............................................................. 13 10.4 Electrostatic Discharge Caution..............................13 10.5 Glossary..................................................................13 11 Mechanical, Packaging, and Orderable Information.................................................................... 13 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October 2003) to Revision D (February 2022) Page • Updated the numbering, formatting, tables, figures and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 4 Pin Configuration and Functions SER 1 16 VCC A 2 SH/LD H B 3 15 14 C 4 13 QH D CLK INH 5 12 G 6 11 CLK GND 7 8 10 F E CLR 9 J, N, or D package 16-Pin CDIP, PDIP, or SOIC Top View Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 3 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 5 Specifications 5.1 Absolute Maximum Ratings(1) MIN MAX –0.5 7 UNIT VCC Supply voltage IIK Input diode current For VI < -0.5 V or VI > VCC + 0.5 V ±20 mA IOK Output diode current For VO < -0.5 V or VO > VCC + 0.5 V ±20 mA IO Drain current, per output For -0.5 V < VO < VCC + 0.5 V ±25 mA IO Output source or sink current per output pin For VO > -0.5 V or VO < VCC + 0.5 V ±25 mA ±50 mA 150 °C 150 °C 300 °C Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature range -65 Lead temperature (Soldering 10s)(SOIC - lead tips only) (1) V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Recommended Operating Conditions VCC Supply voltage range VI, VO Input or output voltage tt Input rise and fall time TA Temperature range MIN MAX 2 6 V 4.5 5.5 V 0 VCC V HC Types HCT Types 2V UNIT 1000 4.5V ns 500 6V 400 –55 ℃ 125 5.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal resistance (1) D (SOIC) N (PDIP) 16 PINS 16 PINS UNIT 73 67 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 5.4 Electrical Characteristics PARAMETER TEST CONDITIONS(2) VCC (V) 25℃ MIN TYP -40℃ to 85℃ MAX MIN -55℃ to 125℃ MAX MIN MAX UNIT HC TYPES High level input voltage VIH Low level input voltage VIL High level output voltage VOH High level output voltage Low level output voltage VOL Low level output voltage 2 1.5 1.5 1.5 V 4.5 3.15 3.15 3.15 V 6 4.2 4.2 4.2 V 2 0.5 0.5 0.5 V 4.5 1.35 1.35 1.35 V 6 1.8 1.8 1.8 V IOH = – 20 μA 2 1.9 1.9 1.9 V IOH = – 20 μA 4.5 4.4 4.4 4.4 V IOH = – 20 μA 6 5.9 5.9 5.9 V IOH = – 4 mA 4.5 3.98 3.84 3.7 V IOH = – 5.2 mA 6 5.48 IOL = 20 μA 2 0.1 0.1 0.1 V IOL = 20 μA 4.5 0.1 0.1 0.1 V IOL = 20 μA 6 0.1 0.1 0.1 V 5.34 5.2 V IOL = 4 mA 4.5 0.26 0.33 0.4 V IOL = 5.2 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 6 8 80 160 μA HCT TYPES VIH High level input voltage 4.5 to 5.5 VIL Low level input voltage 4.5 to 5.5 VOH VOL 0.8 2 0.8 V 0.8 V IOH = – 20 μA 4.5 4.4 4.4 4.4 V High level output voltage IOH = – 4 mA 4.5 3.98 3.84 3.7 V Low level output voltage IOL = 20 μA 4.5 0.1 0.1 0.1 V Low level output voltage IOL = 4 mA 4.5 0.26 0.33 0.4 V VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA 8 80 160 μA Input leakage current ICC Supply current (1) 2 High level output voltage II ΔICC (1) 2 Additional supply current per input pin VI = VCC or GND 5.5 DS, D0-D7 inputs held at VCC – 2.1 V 4.5 to 5.5 100 72 90 98 PE input held at VCC – 2.1 V 4.5 to 5.5 100 126 157.5 171.5 CP, CE inputs held 4.5 to at VCC – 2.1 V 5.5 100 180 225 245 MR inputs held at VCC – 2.1 V 100 72 90 98 4.5 to 5.5 μA For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 5 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 (2) VI = VIH or VIL, unless otherwise noted. 5.5 Prerequisite for Switching Characteristics See (Parameter Measurement Information) PARAMETER VCC (V) 25℃ MIN -40℃ to 85℃ MAX MIN -55℃ to 125℃ MAX MIN MAX UNIT HC TYPES fMAX tw tW tSU tH tREM tSU tH Clock frequency 2 6 5 4 MHz 4.5 30 25 20 MHz 6 35 29 23 MHz 2 100 125 150 ns 4.5 20 25 30 ns 6 17 21 26 ns 2 80 100 120 ns 4.5 16 20 24 ns 6 14 17 20 ns Set-up time Data and CE to clock 2 80 100 120 ns 4.5 16 20 24 ns 6 14 17 20 ns 2 1 1 1 ns Hold time data to clock 4.5 1 1 1 ns 6 1 1 1 ns 2 0 0 0 ns 4.5 0 0 0 ns 6 0 0 0 ns MR pulse width Clock pulse width Removal time MR to clock Set-up time PE to CP Hold time PE to CP or CE 2 145 180 220 ns 4.5 29 36 44 ns 6 25 31 38 ns 2 0 0 0 ns 4.5 0 0 0 ns 6 0 0 0 ns HCT TYPES 6 fMAX Clock frequency 4.5 25 20 16 MHz tw MR pulse width 4.5 35 44 53 ns tw Clock pulse width 4.5 20 25 30 ns tSU Set-up time data and CE to clock 4.5 16 20 24 ns tH Hold time data to clock 4.5 0 0 0 ns tREM Removal time MR to clock 4.5 0 0 0 ns tSU Set-up time PE to CP 4.5 30 38 45 ns tH Hold time PE to CP or CE 4.5 0 0 0 ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 5.6 Switching Characteristics Input tr, tf = 6 ns. Unless otherwise specified, CL = 50pF. See (Parameter Measurement Information) PARAMETER VCC (V) -40℃ to 85℃ 25℃ TYP -55℃ to 125℃ UNIT MAX MAX MAX 160 200 240 ns 32 40 48 ns 6 27 34 41 ns 2 75 95 110 ns 4.5 15 19 22 ns 6 13 16 19 ns HC TYPES 2 tpd 4.5 Clock to output tt Output transition time tPHL Propagation delay MR to output CI Input capacitance Power dissipation capacitance(1) CPD (2) 13(3) 2 160 200 240 ns 4.5 32 40 48 ns 6 27 34 41 ns 10 10 10 pF 5 41 pF HCT TYPES tpd Clock to output 4.5 40 50 60 ns tt Output transition time 4.5 15 19 22 ns tPHL Propagation delay MR to output 4.5 40 50 60 ns CI Input capacitance 10 10 10 pF (1) (2) (3) CPD is used to determine the dynamic power consumption, per gate. PD = CPD VCC 2fi + Σ (CL VCC 2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. CL = 15 and VCC = 5 V. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 7 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. Test Point From Output Under Test CL(1) (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for Push-Pull Outputs tw VCC Clock Input VCC Input 50% 50% 50% 0V 0V Figure 6-2. Voltage Waveforms, Standard CMOS Inputs Pulse Duration th tsu VCC Data Input 50% 50% 0V Figure 6-3. Voltage Waveforms, Standard CMOS Inputs Setup and Hold Times VCC Input 50% 90% Input 50% tPLH tPHL tr(1) (1) VOH Output 50% VOL tPHL tPLH (1) VOH Output 50% 0V tf(1) 90% VOH 90% Output 50% (1) 10% 10% 0V (1) VCC 90% 50% 10% 10% tr(1) tf(1) VOL (1) The greater between tr and tf is the same as tt. Figure 6-5. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Input Devices VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-4. Voltage Waveforms, Standard CMOS Inputs Setup Propagation Delays 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 tw 3V Clock Input 3V Input 1.3V 1.3V 1.3V 0V 0V tsu Figure 6-6. Voltage Waveforms, TTL-Compatible CMOS Inputs Pulse Duration th 3V Data Input 1.3V 1.3V 0V Figure 6-7. Voltage Waveforms, TTL-Compatible CMOS Inputs Setup and Hold Times 3V Input 1.3V 1.3V 0V tPLH(1) tPHL(1) VOH Output Waveform 1 50% 50% VOL tPHL(1) tPLH(1) VOH Output Waveform 2 50% 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-8. Voltage Waveforms, TTL-Compatible CMOS Inputs Propagation Delays Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 9 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 7 Detailed Description 7.1 Overview The ’HC166 and ’HCT166 8-bit shift register is fabricated with silicon gate CMOS technology. It possesses the low power consumption of standard CMOS integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky device. The ’HCT166 is functionally and pin compatible with the standard ’LS166. The 166 is an 8-bit shift register that has fully synchronous serial or parallel data entry selected by an active LOW Parallel Enable (PE) input. When the PE is LOW one setup time before the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE is HIGH, data is entered into the internal bit position Q0 from Serial Data Input (DS), and the remaining bits are shifted one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. For expansion of the register in parallel to serial converters, the Q7 output is connected to the DS input of the succeeding stage. The clock input is a gated OR structure which allows one input to be used as an active LOW Clock Enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of CE input should only take place while the CP is HIGH for predictable operation. A LOW on the Controller Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a LOW state. 7.2 Functional Block Diagram B A 1 11 C D 12 13 1D 1D E 14 F 15 H G 16 18 17 SH/LD 10 SER 1D C1 C1 R R CLK INH CLK 1D R R 1D 1D C1 C1 R 1D 1D C1 C1 R C1 C1 R R 15 2 1 CLR 13 QH 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 7.3 Device Functional Modes Table 7-1. Truth Table(1) INPUTS (1) INTERNAL Q STATES PARALLEL OUTPUT Q7 MASTER RESET PARALLEL ENABLE CLOCK ENABLE CLOCK SERIAL L X X X X X L L L H X L L X X Q00 Q10 Q0 H L L ↑ X a...h a b h H H L ↑ H X H Q0n Q6n H H L ↑ L X L Q0n Q6n H X H ↑ X X Q00 Q10 Q70 D0 D7 Q0 Q1 H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, a...h = The level of steady-state input at inputs D0 thru D7, respectively, Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ↑ transition of the clock. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 11 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 CD54HC166, CD54HCT166, CD74HC166, CD74HCT166 www.ti.com SCHS157D – FEBRUARY 1998 – REVISED FEBRUARY 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: CD54HC166 CD54HCT166 CD74HC166 CD74HCT166 13 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) CD54HC166F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HC166F3A Samples CD54HCT166F3A ACTIVE CDIP J 16 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54HCT166F3A Samples CD74HC166E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC166E Samples CD74HC166M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC166M Samples CD74HC166M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC166M Samples CD74HCT166E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT166E Samples CD74HCT166EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT166E Samples CD74HCT166M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT166M Samples CD74HCT166M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT166M Samples CD74HCT166MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT166M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of