CD74HC4002M

CD54HC4002, CD74HC4002 SCHS197F – AUGUST 1997 – REVISED FEBRUARY 2022 CDx4HC4002 High-Speed CMOS Logic Dual 4-Input NOR Gate 1 Features 2 Description • The ’HC4002 logic gate utilizes silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The ’HC4002 logic family is functional as well as pin compatible with the standard LS logic family. • • • • • Typical propagation delay = 8 ns at VCC = 5 V, CL = 15 pF, TA = 25℃ Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads Wide operating temperature range: -55℃ to 125℃ Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs HC Types – 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC4002M SOIC (14) 8.65 mm × 3.9 mm CD54HC4002F3A CDIP (14) 19.55 mm × 6.71 mm CD74HC4002E PDIP (14) 19.31 mm × 6.35 mm CD74HC4002PW TSSOP (14) 5.0 mm × 4.4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD54HC4002, CD74HC4002 www.ti.com SCHS197F – AUGUST 1997 – REVISED FEBRUARY 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Recommended Operating Conditions.........................4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics............................................5 6 Parameter Measurement Information............................ 6 7 Detailed Description........................................................7 7.1 Overview..................................................................... 7 7.2 Functional Block Diagram........................................... 7 7.3 Device Functional Modes............................................7 8 Power Supply Recommendations..................................8 9 Layout...............................................................................8 9.1 Layout Guidelines....................................................... 8 10 Device and Documentation Support............................9 10.1 Receiving Notification of Documentation Updates....9 10.2 Support Resources................................................... 9 10.3 Trademarks............................................................... 9 10.4 Electrostatic Discharge Caution................................9 10.5 Glossary....................................................................9 11 Mechanical, Packaging, and Orderable Information...................................................................... 9 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (October 2003) to Revision F (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC4002 CD74HC4002 CD54HC4002, CD74HC4002 www.ti.com SCHS197F – AUGUST 1997 – REVISED FEBRUARY 2022 4 Pin Configuration and Functions J, N, D, or PW package 14-Pin CDIP, PDIP, SOIC, or TSSOP Top View Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC4002 CD74HC4002 3 CD54HC4002, CD74HC4002 www.ti.com SCHS197F – AUGUST 1997 – REVISED FEBRUARY 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX –0.5 7 UNIT VCC Supply voltage IIK Input diode current For VI < -0.5 V or VI > VCC + 0.5 V ± 20 mA IOK Output diode current For VO < -0.5 V or VO > VCC + 0.5 V ± 20 mA IO Output source or sink current per output pin For VO > -0.5 V or VO < VCC + 0.5 V ± 25 mA ± 50 mA Continuous current VCC or ground current TJ Junction temperature Tstg Storage temperature range 150 – 65 150 Lead temperature (Soldering 10s) (SOIC - lead tips only) (1) V 300 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 5.2 Recommended Operating Conditions MIN HC Types VCC Supply voltage range VI, VO Input or output voltage HCT Types MAX 2 6 V 4.5 5.5 V 0 VCC V 1000 ns 4.5 V 500 ns 6V 400 ns 125 ℃ 2V tt Input rise and fall time TA UNIT Temperature range –55 5.3 Thermal Information THERMAL METRIC RθJA (1) 4 Junction-to-ambient thermal (1) resistance D (SOIC) N (PDIP) NS (SO) PW (TSSOP) 14 PINS 14 PINS 14 PINS 14 PINS UNIT 86 80 76 113 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC4002 CD74HC4002 CD54HC4002, CD74HC4002 www.ti.com SCHS197F – AUGUST 1997 – REVISED FEBRUARY 2022 5.4 Electrical Characteristics TEST (1) CONDITIONS PARAMETER VIH VIL High level input voltage Low level input voltage 25 o C VOH High level output voltage VOL Low level output voltage Low level output voltage -55℃ to 125℃ MIN 2 1.5 1.5 1.5 V 4.5 3.15 3.15 3.15 V 6 4.2 4.2 4.2 V TYP MAX MIN MAX MIN MAX UNIT 2 0.5 0.5 0.5 V 4.5 1.35 1.35 1.35 V 1.8 V 6 High level output voltage -40℃ to 85℃ VCC (V) 1.8 1.8 IOH = – 20 μA 2 1.9 1.9 1.9 V IOH = – 20 μA 4.5 4.4 4.4 4.4 V IOH = – 20 μA 6 5.9 5.9 5.9 V IOH = – 4 mA 4.5 3.98 3.84 3.7 V IOH = – 5.2 mA 6 5.48 5.34 5.2 V IOL = 20 μA 2 0.1 0.1 0.1 V IOL = 20 μA 4.5 0.1 0.1 0.1 V IOL = 20 μA 6 0.1 0.1 0.1 V IOL = 4 mA 4.5 0.26 0.33 0.4 V IOL = 5.2 mA 6 0.26 0.33 0.4 V II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 μA ICC Supply current VI = VCC or GND 6 2 20 40 μA (1) VI = VIH or VIL, unless otherwise noted. 5.5 Switching Characteristics Input tr, tf = 6 ns PARAMETER TEST CONDITIONS VCC (V) CL = 50 pF -40℃ to 85℃ 25℃ TYP -55℃ to 125℃ UNIT MAX MAX MAX 2 100 125 150 ns 4.5 20 25 30 ns 17 21 26 ns HC TYPES tPLH, tPHL Propagation delay, nA, nB, nC, nD to nY tTLH, tTHL Output transition times (see Figure 1) CIN Input capacitance CPD Power dissipation capacitance(1) (2) (1) (2) 6 CL = 15 pF 5 2 75 95 110 ns CL = 50 pF 4.5 15 19 22 ns 6 13 16 19 ns 10 10 10 pF CL = 15 pF 5 8 ns 22 pF CPD is used to determine the dynamic power consumption, per gate. PD = VCC 2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC4002 CD74HC4002 5 CD54HC4002, CD74HC4002 SCHS197F – AUGUST 1997 – REVISED FEBRUARY 2022 www.ti.com 6 Parameter Measurement Information Figure 6-1. HC and HCU Transition Times and Propagation Delay Times, Combination Logic 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC4002 CD74HC4002 CD54HC4002, CD74HC4002 www.ti.com SCHS197F – AUGUST 1997 – REVISED FEBRUARY 2022 7 Detailed Description 7.1 Overview The ’HC4002 logic gate utilizes silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The ’HC4002 logic family is functional as well as pin compatible with the standard LS logic family. 7.2 Functional Block Diagram Figure 7-2. Logic Symbol Figure 7-1. Functional Diagram 7.3 Device Functional Modes Table 7-1. Truth Table(1) INPUTS (1) OUTPUT nA nB nC nD nY L L L L H H X X X L X H X X L X X H X L X X X H L H = High Voltage Level, L = Low Voltage Level, X = Irrelevant Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC4002 CD74HC4002 7 CD54HC4002, CD74HC4002 SCHS197F – AUGUST 1997 – REVISED FEBRUARY 2022 www.ti.com 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC4002 CD74HC4002 CD54HC4002, CD74HC4002 www.ti.com SCHS197F – AUGUST 1997 – REVISED FEBRUARY 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CD54HC4002 CD74HC4002 9 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CD54HC4002F3A ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8404401CA CD54HC4002F3A CD74HC4002E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4002E CD74HC4002M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4002M CD74HC4002M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC4002M CD74HC4002MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4002M CD74HC4002PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4002 CD74HC4002PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HJ4002 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of