CD54HC73, CD74HC73, CD74HCT73
SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022
CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger
1 Features
2 Description
•
The ’HC73 and CD74HCT73 utilize silicon gate
CMOS technology to achieve operating speeds
equivalent to LSTTL parts. They exhibit the low power
consumption of standard CMOS integrated circuits,
together with the ability to drive 10 LSTTL loads.
•
•
•
•
•
•
•
•
•
•
Hysteresis on clock inputs for improved noise
immunity and increased input rise and fall times
Asynchronous reset
Complementary outputs
Buffered inputs
Typical fMAX = 60 MHz at VCC = 5 V,
CL = 15 pF, TA = 25℃
Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: –55℃ to 125℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
Logic ICs
HC types
– 2 V to 6V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility,
VIL = 0.8 V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 μA at VOL, VOH
Package Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD74HC73M
SOIC (14)
8.65 mm × 3.90 mm
CD74HCT73M
SOIC (14)
8.65 mm × 3.90 mm
CD74HC73E
PDIP (14)
19.31 mm × 6.35 mm
CD74HCT73E
PDIP (14)
19.31 mm × 6.35 mm
CD54HC73F
CDIP (14)
19.55 mm × 6.71 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC73, CD74HC73, CD74HCT73
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SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings(1) .................................... 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information ...................................................4
5.4 Electrical Specifications.............................................. 5
5.5 Prerequisite for Switching Specifications.................... 6
5.6 Switching Specifications ............................................ 7
6 Parameter Measurement Information............................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Device Functional Modes............................................9
8 Power Supply Recommendations................................10
9 Layout.............................................................................10
9.1 Layout Guidelines..................................................... 10
10 Device and Documentation Support..........................11
10.1 Receiving Notification of Documentation Updates.. 11
10.2 Support Resources................................................. 11
10.3 Trademarks............................................................. 11
10.4 Electrostatic Discharge Caution.............................. 11
10.5 Glossary.................................................................. 11
11 Mechanical, Packaging, and Orderable
Information.................................................................... 11
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (January 2022) to Revision G (October 2022)
Page
• Increased RθJA for packages: D (86 to 138.7); N (80 to 91)..............................................................................4
Changes from Revision E (August 2003 ) to Revision F (January 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022
4 Pin Configuration and Functions
J, N, or D package
14-Pin CDIP, PDIP, or SOIC
Top View
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SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022
5 Specifications
5.1 Absolute Maximum Ratings(1)
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage
IIK
Input diode current
For VI < –0.5 V or VI > VCC + 0.5 V
± 20
mA
IO
Drain current, per output
For –0.5 V < VO < VCC + 0.5 V
± 25
mA
IOK
Output diode current
For VO < –0.5 V or VO > VCC + 0.5 V
± 20
mA
IO
Output source or sink current per output pin
For VO > –0.5 V or VO < VCC + 0.5 V
± 25
mA
ICC
Continuous current through VCC or GND
± 50
mA
TJ
Junction temperature
±150
°C
Tstg
Storage temperature
150
°C
(1)
–65
V
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied.
5.2 Recommended Operating Conditions
MIN
VCC
Supply voltage range
VI, VO
Input or output voltage
HC types
HCT types
2
6
4.5
5.5
0
2V
tt
Input rise and fall time
TA
MAX
UNIT
V
VCC
V
1000
4.5 V
500
6V
400
Temperature range
–55
ns
℃
125
5.3 Thermal Information
THERMAL METRIC
N (PDIP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
138.7
91
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
93.8
78.9
°C/W
RθJB
Junction-to-board thermal resistance
94.7
70.7
°C/W
ψJT
Junction-to-top characterization parameter
49.1
58.6
°C/W
ψJB
Junction-to-board characterization parameter
resistance
94.3
70.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
(1)
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022
5.4 Electrical Specifications
PARAMETER
TEST
CONDITIONS(2)
VCC
(V)
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
VIH
High level input voltage
VIL
Low level input voltage
High level output voltage
VOH
High level output voltage
Low level output voltage
VOL
Low level output voltage
2
1.5
1.5
1.5
4.5
3.15
3.15
3.15
6
4.2
4.2
V
4.2
2
0.5
0.5
0.5
4.5
1.35
1.35
1.35
6
1.8
1.8
1.8
IOH = – 20 μA
2
1.9
1.9
1.9
IOH = – 20 μA
4.5
4.4
4.4
4.4
IOH = – 20 μA
6
5.9
5.9
5.9
IOH = – 4 mA
4.5
3.98
3.84
3.7
IOH = – 5.2 mA
6
5.48
IOL = 20 μA
2
0.1
0.1
0.1
IOL = 20 μA
4.5
0.1
0.1
0.1
IOL = 20 μA
6
0.1
0.1
0.1
5.34
V
V
5.2
IOL = 4 mA
4.5
0.26
0.33
0.4
IOL = 5.2 mA
6
0.26
0.33
0.4
V
II
Input leakage current
VI = VCC or GND
6
±0.1
±1
±1
mA
ICC
Supply current
VI = VCC or GND
6
4
40
80
mA
HCT TYPES
VIH
High level input voltage
4.5 to
5.5
VIL
Low level input voltage
4.5 to
5.5
VOH
VOL
2
2
0.8
2
0.8
V
0.8
High level output voltage
IOH = – 20 μA
4.5
4.4
4.4
4.4
High level output voltage
IOH = – 4 mA
4.5
3.98
3.84
3.7
Low level output voltage
IOL = 20 μA
4.5
0.1
0.1
0.1
Low level output voltage
IOL = 4 mA
4.5
0.26
0.33
0.4
V
V
V
II
Input leakage current
VI = VCC and
GND
5.5
±0.1
±1
±1
μA
ICC
Supply current
VI = VCC and
GND
5.5
4
40
80
μA
ΔICC (1)
Additional supply current All inputs held at
per input pin
VCC – 2.1
108
135
147
μA
(1)
(2)
4.5 to
5.5
100
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
VI = VIH or VIL.
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SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022
5.5 Prerequisite for Switching Specifications
PARAMETER
TEST
VCC(V)
CONDITIONS
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
tw
tw
tSU
tH
tREM
CP pulse width
R pulse width
Setup time, J, K to CP
Hold time, J, K to CP
Removal time
–CL = 50 pF
–CL = 50 pF
CL = 50 pF
CL = 50 pF
–CL = 50 pF
CL = 50 pF
fMAX
CP frequency
2
80
100
120
4.5
16
20
24
6
14
17
20
2
80
100
120
4.5
16
20
24
6
14
17
20
2
80
100
120
4.5
16
20
24
6
14
17
20
2
3
3
3
4.5
3
3
3
6
3
3
3
2
80
100
120
4.5
16
20
24
6
14
17
20
2
6
5
4
4.5
30
25
20
CL = 15 pF
5
60
CL = 50 pF
6
35
29
23
ns
ns
ns
ns
ns
MHz
HCT TYPES
tw
CP pulse width
CL = 50 pF
4.5
16
20
24
ns
tw
R pulse width
CL = 50 pF
4.5
18
23
27
ns
tSU
Setup time, J, K to CP
CL = 50 pF
4.5
16
20
24
ns
tH
Hold time, J, K to CP
CL = 50 pF
4.5
3
3
3
ns
tREM
Removal time
CL = 50 pF
4.5
12
15
18
ns
CL = 50 pF
4.5
30
25
20
CL = 15 pF
5
fMAX
6
CP frequency
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60
MHz
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SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022
5.6 Switching Specifications
Input, tr, tf = 6 ns
TEST
VCC (V)
CONDITIONS
PARAMETER
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to
125℃
MIN
UNIT
MAX
HC TYPES
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
Propagation delay,
CP to Q
Output transition time
CI
Input capacitance
Power dissipation
160
200
240
32
40
48
5
CL = 50 pF
6
28
34
41
2
160
200
240
4.5
32
40
48
13
CL = 15 pF
5
CL = 50 pF
6
28
34
41
2
145
180
220
4.5
29
36
44
38
CL = 50 pF
Propagation delay,
R to Q, Q
2
4.5
CL = 15 pF
CL = 50 pF
Propagation delay,
CP to Q
tTLH,
tTHL
CPD
CL = 50 pF
13
CL = 15 pF
5
CL = 50 pF
6
25
31
2
75
95
CL = 50 pF
4.5
15
19
22
6
13
16
19
10
10
10
capacitance(1) (2)
5
12
18
ns
ns
ns
110
28
ns
pF
pF
HCT TYPES
tPLH,
tPHL
Propagation delay,
CP to Q
CL = 50 pF
4.5
38
48
57
ns
tPLH,
tPHL
Propagation delay,
CP to Q
CL = 50 pF
4.5
36
45
54
ns
tPLH,
tPHL
Propagation delay,
R to Q, Q
CL = 50 pF
4.5
34
43
51
ns
tTLH,
tTHL
Output transition time
CL = 50 pF
4.5
15
19
22
ns
CI
Input capacitance
10
10
10
pF
CPD
Power dissipation capacitance(1) (2)
(1)
(2)
5
28
pF
CPD is used to determine the dynamic power consumption, per flip-flop.
PD = CPD VCC 2fi + ∑ CL VCC 2fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
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6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
VCC
Input
50%
90%
tPLH
tPHL
tr(1)
(1)
VOH
Output
50%
10%
10%
tr(1)
tPLH(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
VOH
50%
VOH
90%
Output
VOL
Output
0V
tf(1)
90%
50%
tPHL(1)
10%
10%
0V
(1)
VCC
90%
Input
50%
Figure 6-3. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
3V
Input
1.3V
1.3V
0V
tPLH
(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
8
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7 Detailed Description
7.1 Overview
The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to
LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the
ability to drive 10 LSTTL loads
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on
the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric
limits.
The HCT logic family is functionally as well as pin compatible with the standard LS logic family
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Truth Table(1)
INPUTS
(1)
OUTPUTS
R
CP
J
K
Q
L
Q
L
X
X
X
H
↓
L
L
H
H
↓
H
L
H
H
↓
L
H
L
H
↓
H
H
Toggle
H
H
X
X
No change
No change
L
H
H = high level (steady state), L = low level (steady state), X = irrelevant, ↓ = high-to-low transition
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SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
10
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8515301CA
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8515301CA
CD54HC73F3A
Samples
CD54HC73F
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC73F
Samples
CD54HC73F3A
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8515301CA
CD54HC73F3A
Samples
CD74HC73E
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC73E
Samples
CD74HC73M
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC73M
Samples
CD74HC73M96
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HC73M
Samples
CD74HC73MT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC73M
Samples
CD74HCT73E
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT73E
Samples
CD74HCT73M
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT73M
Samples
CD74HCT73M96
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCT73M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of