CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with
Set and Reset with Negative-Edge Trigger
1 Features
2 Description
•
The ’HC112 and ’HCT112 utilize silicon-gate CMOS
technology to achieve operating speeds equivalent to
LSTTL parts. They exhibit the low power consumption
of standard CMOS integrated circuits, together with
the ability to drive 10 LSTTL loads.
•
•
•
•
•
•
•
•
•
•
Hysteresis on clock inputs for improved noise
immunity and increased input rise and fall times
Asynchronous set and reset
Complementary outputs
Buffered inputs
Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA
= 25℃
Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
Wide operating temperature range: -55℃ to 125℃
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL
Logic ICs
HC types
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility, VIL = 0.8
V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 μA at VOL, VOH
These flip-flops have independent J, K, PRE, CLR,
and Clock inputs and Q and Q outputs. They
change state on the negative-going transition of
the clock pulse. PRE and CLR are accomplished
asynchronously by low-level inputs.
The HCT logic family is functionally as well as pin
compatible with the standard LS logic family.
Package Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD54HC112F3A
CDIP (16)
24.38 mm × 6.92 mm
CD74HC112M96
SOIC (16)
9.90 mm × 3.90 mm
CD74HC112E
PDIP (16)
19.31 mm × 6.35 mm
CD74HCT112E
PDIP (16)
19.31 mm × 6.35 mm
CD74HC112NSR
SO (16)
6.20 mm × 5.30 mm
CD74HC112PW
TSSOP (16)
5.00 mm × 4.40 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
xPRE
xJ
C
C
xQ
C
xK
xCLK
C
C
C
C
C
C
C
xQ
xCLR
Functional Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Prerequisite for Switching Characteristics.................. 6
5.6 Switching Characteristics............................................7
6 Parameter Measurement Information............................ 8
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Device Functional Modes..........................................10
8 Power Supply Recommendations................................11
9 Layout............................................................................. 11
9.1 Layout Guidelines..................................................... 11
10 Device and Documentation Support..........................12
10.1 Receiving Notification of Documentation Updates..12
10.2 Support Resources................................................. 12
10.3 Trademarks............................................................. 12
10.4 Electrostatic Discharge Caution..............................12
10.5 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (January 2022) to Revision J (October 2022)
Page
• Increased RθJA for packages: D (73 to 117.2); N (67 to 69.3); NS (64 to 88.4); PW (108 to 137.5)................. 4
Changes from Revision H (October 2003) to Revision I (January 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
• Updated pin names to match current standards. CP is now CLK; S is now PRE; 1R is now 1CLR; 2R is now
2CLR; 2CP is now 2CLK; 2S is now 2PRE ....................................................................................................... 3
2
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
4 Pin Configuration and Functions
J, N, D, NS, or PW package
16-Pin CDIP, PDIP, SOIC, SO, TSSOP
Top View
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
5 Specifications
5.1 Absolute Maximum Ratings
(1)
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage
IIK
Input diode current
For VI < -0.5 V or VI > VCC + 0.5 V
± 20
mA
IO
Drain current, per output
For -0.5 V < VO < VCC + 0.5 V
± 25
mA
IOK
Output diode current
For VO < -0.5 V or VO > VCC + 0.5 V
± 20
mA
IO
Output source or sink current per output pin
For VO > -0.5 V or VO < VCC + 0.5 V
± 25
mA
ICC
Continuous current through VCC or GND
± 50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature range
150
°C
300
°C
– 65
Lead temperature (Soldering 10s)
(1)
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 Recommended Operating Conditions
VCC
Supply voltage range
VI, VO
Input or output voltage
tr, tf
Input rise and fall time
TA
Temperature range
HC types
HCT types
MIN
MAX
2
6
4.5
5.5
0
VCC
2V
1
4.5 V
1
6V
UNIT
V
V
ms
1
–55
125
℃
5.3 Thermal Information
THERMAL METRIC
N (PDIP)
NS (SO)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal
(1)
resistance
117.2
69.3
88.4
137.5
°C/W
RθJC (top)
Junction-to-case (top) thermal
resistance
77.2
61.8
46
75.3
°C/W
RθJB
Junction-to-board thermal
resistance
75.6
49.3
50.6
82.2
°C/W
ΨJT
Junction-to-top characterization
parameter
38.1
34.6
13
25.1
°C/W
ΨJB
Junction-to-board characterization
parameter
75.3
49
50.2
81.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
N/A
N/A
N/A
N/A
°C/W
(1)
4
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
5.4 Electrical Characteristics
PARAMETER
TEST
CONDITIONS(2)
VCC(V)
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
–55℃ to 125℃
MAX
MIN
MAX
UNIT
HC TYPES
High level
input voltage
VIH
Low level
input voltage
VIL
High level
output voltage
VOH
High level
output voltage
Low level
output voltage
VOL
2
1.5
1.5
1.5
4.5
3.15
3.15
3.15
6
4.2
4.2
4.2
2
0.5
0.5
0.5
4.5
1.35
1.35
1.35
6
1.8
1.8
1.8
2
1.9
1.9
1.9
IOH = – 20 μA
4.5
4.4
4.4
4.4
6
5.9
5.9
5.9
IOH = – 4 mA
4.5
3.98
3.84
3.7
IOH = – 5.2 mA
6
5.48
IOL = 20 μA
V
5.34
V
V
5.2
2
0.1
0.1
0.1
4.5
0.1
0.1
0.1
6
0.1
0.1
0.1
V
Low level
output voltage
IOL = 4 mA
4.5
0.26
0.33
0.4
IOL = 5.2 mA
6
0.26
0.33
0.4
II
Input leakage
current
VCC or GND
6
±0.1
±1
±1
μA
ICC
Supply current
VCC or GND
6
4
40
80
μA
HCT TYPES
VIH
High level
input voltage
4.5 to
5.5
VIL
Low level
input voltage
4.5 to
5.5
2
2
0.8
2
0.8
V
0.8
V
High level
output voltage
IOH = – 20 μA
4.5
4.4
4.4
4.4
High level
output voltage
IOH = – 4 mA
4.5
3.98
3.84
3.7
Low level
output voltage
IOL = 20 μA
4.5
Low level
output voltage
IOL = 4 mA
4.5
0.26
0.33
0.4
II
Input leakage
current
VCC and GND
5.5
±0.1
±1
±1
μA
ICC
Supply current
4
40
80
μA
VOH
VOL
ΔICC (1)
V
0.1
0.1
V
VCC and GND
5.5
1PRE, 2PRE inputs
held at VCC -2.1
4.5 to
5.5
100
180
225
245
μA
1K, 2K inputs held
at VCC -2.1
Additional
supply current 1CLR, 2CLR inputs
per input pin
held at VCC -2.1
4.5 to
5.5
100
216
270
294
μA
4.5 to
5.5
100
234
292.5
318.5
μA
4.5 to
5.5
100
360
450
490
μA
1J, 2J, 1CLK, 2CLK
inputs held at VCC
-2.1
(1)
0.1
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
(2)
VI = VIH or VIL, unless otherwise noted.
5.5 Prerequisite for Switching Characteristics
PARAMETER
VCC (V)
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
MAX
–55℃ to 125℃
MIN
MAX
UNIT
HC TYPES
tW
tW
tSU
tH
tREM
fMAX
Pulse width CLK
Pulse width CLR, PRE
Setup time J, K, to CLK
Hold time J, K, to CLK
Removal time CLR to CLK, PRE to
CLK
CLK frequency
2
80
100
120
4.5
16
20
24
6
14
17
20
2
80
100
120
4.5
16
20
24
6
14
17
20
2
80
100
120
4.5
16
20
24
6
14
17
20
2
0
0
0
4.5
0
0
0
6
0
0
0
2
80
100
120
4.5
16
20
24
6
14
17
20
2
6
5
4
4.5
30
25
20
6
35
29
23
ns
ns
ns
ns
ns
MHz
HCT TYPES
6
tSU
Pulse width CLK
4.5
16
20
24
ns
tW
Pulse width CLR, PRE
4.5
18
23
27
ns
tH
Setup time J, K, to CLK
4.5
16
20
24
ns
tREM
Hold time J, K, to CLK
4.5
3
3
3
ns
tW
Removal time CLR to CLK, PRE to
CLK
4.5
20
25
30
ns
fMAX
CLK frequency
4.5
30
25
20
MHz
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
5.6 Switching Characteristics
tr, tf = 6 ns
PARAMETER
VCC (V)
25℃
MIN
TYP
–40℃ to 85℃
MAX
MIN
–55℃ to 125℃
MAX
MIN
MAX
UNIT
HC TYPES
2
tPLH, tPHL
tPLH, tPHL
Propagation delay,
CLK to Q, Q
4.5
Propagation delay,
PRE to Q, Q
14
(3)
30
37
45
195
235
31
39
47
26
33
40
180
225
270
36
45
54
6
31
38
46
13
(3)
2
Output transition time
CI
Input capacitance
fMAX
CLK frequency
CPD
Power dissipation
capacitance(1) (2)
53
155
4.5
tTLH, tTHL
265
44
2
4.5
Propagation delay,
CLR to Q, Q
220
35
6
6
tPLH, tPHL
175
15
(3)
2
75
95
110
4.5
15
19
22
6
13
16
19
10
10
10
ns
ns
ns
ns
pF
60
(3)
MHz
5
12
(4)
pF
5
HCT TYPES
tPLH, tPHL
Propagation delay,
CLK to Q, Q
4.5
14
(3)
35
44
53
ns
tPLH, tPHL
Propagation delay,
PRE to Q, Q
4.5
13
(3)
32
40
48
ns
tPLH, tPHL
Propagation delay,
CLR to Q, Q
4.5
14
(3)
37
46
56
ns
tTLH, tTHL
Output transition time
4.5
15
19
22
ns
CI
Input capacitance
10
10
10
fMAX
CLK frequency
5
60
(3)
MHz
CPD
Power dissipation
capacitance(1) (2)
5
20
(4)
pF
(1)
(2)
(3)
(4)
pF
CPD is used to determine the dynamic power consumption, per flip-flop.
PD = CPD VCC 2 fi + ∑ CL fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
CL = 15 pF and VCC = 5 V.
VCC = 5 V.
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
tw
VCC
Clock
Input
VCC
Input
50%
50%
50%
0V
0V
Figure 6-2. Voltage Waveforms, Standard CMOS
Inputs Pulse Duration
th
tsu
VCC
Data
Input
50%
50%
0V
Figure 6-3. Voltage Waveforms, Standard CMOS
Inputs Setup and Hold Times
VCC
Input
50%
90%
Input
50%
tPLH
tPHL
tr(1)
(1)
VOH
Output
50%
VOL
tPHL
tPLH
(1)
VOH
Output
50%
0V
tf(1)
90%
VOH
90%
Output
50%
(1)
10%
10%
0V
(1)
VCC
90%
50%
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 6-5. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
8
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
tw
3V
Clock
Input
3V
Input
1.3V
1.3V
1.3V
0V
0V
tsu
Figure 6-6. Voltage Waveforms, TTL-Compatible
CMOS Inputs Pulse Duration
th
3V
Data
Input
1.3V
1.3V
0V
Figure 6-7. Voltage Waveforms, TTL-Compatible
CMOS Inputs Setup and Hold Times
3V
Input
1.3V
1.3V
0V
tPLH(1)
tPHL(1)
VOH
Output
Waveform 1
50%
50%
VOL
tPHL(1)
tPLH(1)
VOH
Output
Waveform 2
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-8. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
7 Detailed Description
7.1 Overview
The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to
LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the
ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, PRE, CLR, and Clock inputs and Q and Q outputs. They change state
on the negative-going transition of the clock pulse. PRE and CLR are accomplished asynchronously by low-level
inputs.
The HCT logic family is functionally and pin-compatible with the standard LS logic family.
7.2 Functional Block Diagram
xPRE
xJ
C
C
xQ
C
xK
C
xCLK
C
C
C
C
C
C
xQ
xCLR
7.3 Device Functional Modes
Table 7-1. Truth Table(1)
INPUTS
(1)
(2)
10
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H(2)
H(2)
H
H
¯
L
L
H
H
¯
H
L
H
H
H
¯
L
H
L
H
H
¯
H
H
Toggle
H
H
H
X
X
No Change
No Change
L
H
H = high level (steady state), L = low level (steady state), X = don’t care, ↓ = high-to-low transition
Output states unpredictable if both S and R go high simultaneously after both being low at the same time.
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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SCHS141J – MARCH 1998 – REVISED OCTOBER 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
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13-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-8970201EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8970201EA
CD54HCT112F3A
Samples
CD54HC112F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8408801EA
CD54HC112F3A
Samples
CD54HCT112F3A
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-8970201EA
CD54HCT112F3A
Samples
CD74HC112E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC112E
Samples
CD74HC112M96
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC112M
Samples
CD74HC112MT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC112M
Samples
CD74HC112NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC112M
Samples
CD74HC112PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ112
Samples
CD74HC112PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ112
Samples
CD74HC112PWRE4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ112
Samples
CD74HC112PWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ112
Samples
CD74HCT112E
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT112E
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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