CDCP1803
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1:3 LVPECL CLOCK BUFFER
WITH PROGRAMMABLE DIVIDER
Check for Samples: CDCP1803
FEATURES
1
S1
VDD0
Y0
Y0
VDD0
24 23 22 21 20 19
18
VDDPECL
2
17
VDD1
IN
3
16
Y1
IN
4
15
Y1
VDDPECL
5
14
VDD1
VBB
6
(1)
VSS(1)
9
13
10 11 12
S0
VSS
NC
8
VDD2
7
Y2
•
•
•
1
Y2
•
EN
VDD2
•
•
•
•
RGE PACKAGE
(TOP VIEW)
S2
•
Distributes One Differential Clock Input to
Three LVPECL Differential Clock Outputs
Programmable Output Divider for Two LVPECL
Outputs
Low-Output Skew 15 ps (Typical)
VCC Range 3 V–3.6 V
Signaling Rate Up to 800-MHz LVPECL
Differential Input Stage for Wide CommonMode Range
Provides VBB Bias Voltage Output for SingleEnded Input Signals
Receiver Input Threshold ±75 mV
24-Terminal QFN Package (4 mm × 4 mm)
Accepts Any Differential Signaling:
LVDS, HSTL, CML, VML, SSTL-2, and
Single-Ended: LVTTL/LVCMOS
VSS
•
Thermal pad must be connected to VSS.
P0024-02
DESCRIPTION
S2
VDD0
Y0
Y0
VDD0
S1
23
22
21
20
19
EN
1
18
S0
VDDPECL
2
17
VDD1
IN
3
16
Y1
IN
4
15
Y1
VDDPECL
5
14
VDD1
VBB
6
13
VSS
(1)
7
8
9
10
11
12
VDD2
Y2
Y2
VDD2
NC
VSS(1)
VSS
The CDCP1803 has three control terminals, S0, S1,
and S2, to select different output mode settings; see
Table 1 for details. The CDCP1803 is characterized
for operation from –40°C to 85°C. For use in singleended driver applications, the CDCP1803 also
provides a VBB output terminal that can be directly
connected to the unused input as a common-mode
voltage reference.
24
RTH PACKAGE
(TOP VIEW)
The CDCP1803 clock driver distributes one pair of
differential clock inputs to three pairs of LVPECL
differential clock outputs Y[2:0] and Y[2:0] with
minimum skew for clock distribution. The CDCP1803
is specifically designed for driving 50-Ω transmission
lines.
Thermal pad must be connected to VSS.
P0025-02
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
CDCP1803
SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
Y0
IN
LVPECL
Y0
IN
Y1
LVPECL
Div 1
Div 2
Div 4
Div 8
Div 16
Y1
Y2
LVPECL
Y2
VBB
Bias
Generator
VDD − 1.3 V
(Imax < 1.5 mA)
Control
S1
S2
S0
EN
B0059-02
2
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TERMINAL FUNCTIONS
TERMINAL
NAME
EN
IN, IN
NO.
1
3, 4
I/O
I
(with 60-kΩ pullup)
I (differential)
DESCRIPTION
ENABLE: Enables or disables all outputs simultaneously.
EN = 1: outputs on according to S[2:0] settings
EN = 0: outputs Y[2:0] off (high impedance)
See Table 1 for details.
Differential input clock. Input stage is sensitive and has a wide common-mode range.
Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS,
CML, HSTL). Because the input is high-impedance, it is recommended to terminate the
PCB transmission line before the input (e.g., with 100 Ω across input). Input can also be
driven by a single-ended signal if the complementary input is tied to VBB. A moreadvanced scheme for single-ended signals is given in the Application Information
section near the end of this document.
The inputs employ an ESD structure protecting the inputs in case of an input voltage
exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through these inputs
is possible and must be prevented by limiting the input voltage < VDD.
NC
S[2:0]
VBB
12
No connect. Leave this terminal open or tie to ground.
24, 19, 18
I
(with 60-kΩ pullup)
Select mode of operation. Defines the output configuration of Y[2:0], see Table 1 for
configuration.
6
O
Bias voltage output can be used to bias unused complementary input IN for singleended input signals.
The output voltage of VBB is VDD – 1.3 V. When driving a load, the output current drive
is limited to about 1.5 mA.
VDDPECL
VDD[2:0]
2, 5
Supply
Supply voltage PECL input + internal logic
8, 11, 14,
17, 20, 23
Supply
PECL output supply voltage for output Y[2:0]. Each output can be disabled by pulling
the corresponding VDDx to GND.
CAUTION: In this mode, no voltage from outside may be forced, because internal
diodes could be forced in forward direction. Thus, it is recommended to disconnect the
output if it is not being used.
VSS
Y[2:0]
Y[2:0]
7, 13
Supply
9, 15, 21
10, 16, 22
O (LVPECL)
Device ground
LVPECL clock outputs. These outputs provide low-skew copies of IN or down-divided
copies of clock IN based on selected mode of operation S[2:0]. If an output is unused,
the output can simply be left open to save power and minimize noise impact to the
remaining outputs.
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CONTROL TERMINAL SETTINGS
The CDCP1803 has three control terminals (S0, S1, and S2) and an enable terminal (EN) to select different
output mode settings.
Setting for Mode 20:
EN = 1
S2 = 1
S1 = 0
S0 = 1
CDCP1803
REN = Open
EN
RS2 = Open
S2
RS1 = 0 Ω
S1
RS0 = Open
S0
S0084-02
Figure 1. Control Terminal Setting for Example
4
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Table 1. Selection Mode Table
LVPECL (1)
(1)
MODE
EN
S2
S1
S0
Y0
Y1
Y2
0
0
x
x
x
1
1
0
0
0
÷1
÷1
÷1
2
1
0
0
VDD/2
÷1
Off (high-z)
Off (high-z)
3
1
0
0
1
÷1
÷1
Off (high-z)
4
1
0
VDD/2
0
÷1
÷2
Off (high-z)
5
1
0
VDD/2
VDD/2
÷1
÷4
Off (high-z)
6
1
0
VDD/2
1
÷1
÷8
Off (high-z)
7
1
0
1
0
÷1
Off (high-z)
÷1
8
1
0
1
1
÷1
÷2
÷1
9
1
VDD/2
0
0
÷1
÷4
÷1
10
1
VDD/2
0
VDD/2
÷1
÷8
÷1
11
1
VDD/2
0
1
÷1
Off (high-z)
÷2
12
1
VDD/2
VDD/2
0
÷1
÷1
÷2
13
1
VDD/2
VDD/2
VDD/2
÷1
÷2
÷2
14
1
VDD/2
VDD/2
1
÷1
÷4
÷2
15
1
VDD/2
1
0
÷1
÷8
÷2
16
1
VDD/2
1
VDD/2
÷1
Off (high-z)
÷4
17
1
VDD/2
1
1
÷1
÷1
÷4
18
1
1
0
0
÷1
÷2
÷4
19
1
1
0
VDD/2
÷1
÷4
÷4
20
1
1
0
1
÷1
÷8
÷4
21
1
1
VDD/2
0
÷1
Off (high-z)
÷8
22
1
1
VDD/2
VDD/2
÷1
÷1
÷8
23
1
1
VDD/2
1
÷1
÷2
÷8
24
1
1
1
0
÷1
÷4
÷8
25
1
1
1
VDD/2
÷1
÷8
÷8
26
1
1
1
1
÷1
Off (high-z)
÷ 16
27
VDD/2
0
0
0
÷1
÷1
÷ 16
28
VDD/2
0
0
VDD/2
÷1
÷2
÷ 16
29
VDD/2
0
0
1
÷1
÷4
÷ 16
Off (high-z)
30
VDD/2
0
VDD/2
0
÷1
÷8
÷ 16
Rsv
VDD/2
1
VDD/2
1
Reserved
Reserved
Reserved
Rsv
VDD/2
1
1
0
N/A
Low
Low
The LVPECL outputs are open-emitter stages. Thus, if the unused LVPECL outputs Y0, Y1, or Y2 are left unconnected, then the current
consumption is minimized and noise impact to remaining outputs is neglectable. Also, each output can be individually disabled by
connecting the corresponding VDD input to GND.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
VDD
Supply voltage
–0.3 V to 3.8 V
VI
Input voltage
–0.2 V to (VDD + 0.2 V)
VO
Output voltage
–0.2 V to (VDD + 0.2 V)
Differential short-circuit current, Yn, Yn, IOSD
Continuous
Electrostatic discharge (HBM 1.5 kΩ, 100 pF), ESD
>2000 V
Moisture level 24-terminal QFN package (solder reflow temperature of 235°C) MSL
Tstg
Storage temperature
TJ
Maximum junction temperature
(1)
2
–65°C to 150°C
125°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VDD
Supply voltage
TA
Operating free-air temperature
MIN
TYP
MAX
3
3.3
3.6
V
85
°C
–40
UNIT
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
LVPECL INPUT IN, IN
MAX
UNIT
fclk
Input frequency
PARAMETER
0
800
MHz
VCM
High-level input common mode
1
VDD – 0.3
VIN
TYP
(1)
500
1300
Input voltage swing between IN and IN
(2)
125
1300
Input current
RIN
Input impedance
CI
Input capacitance at IN, IN
6
MIN
Input voltage swing between IN and IN
IIN
(1)
(2)
TEST CONDITIONS
VI = VDD or 0 V
±10
300
V
mV
μA
kΩ
1
pF
Is required to maintain ac specifications
Is required to maintain device functionality
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
LVPECL OUTPUT DRIVER Y[2:0], Y[2:0]
PARAMETER
MAX
UNIT
0
800
MHz
Termination with 50 Ω to VDD – 2 V
VDD – 1.18
VDD – 0.81
V
Low-level output voltage
Termination with 50 Ω to VDD – 2 V
VDD – 1.98
VDD – 1.55
V
Output voltage swing between Y and Y,
see Figure 3.
Termination with 50 Ω to VDD – 2 V
500
fclk
Output frequency, see Figure 3.
VOH
High-level output voltage
VOL
VO
IOZL
Output 3-state current
IOZH
TEST CONDITIONS
TYP
mV
VDD = 3.6 V, VO = 0 V
5
VDD = 3.6 V, VO = VDD – 0.8 V
tr/tf
Rise and fall times
20% to 80% of VOUTPP, see Figure 7.
tskpecl(o)
Output skew between any LVPECL
output Y[2:0] and Y[2:0]
See Note A in Figure 6.
tDuty
Output duty-cycle distortion (1)
Crossing point-to-crossing point
distortion
tsk(pp)
Part-to-part skew
Any Y, see Note B in Figure 6.
CO
Output capacitance
VO = VDD or GND
LOAD
Expected output load
(1)
MIN
10
200
15
–50
50
μA
350
ps
30
ps
50
ps
300
ps
1
pF
50
Ω
For an 800-MHz signal, the 50-ps error would result in a duty cycle distortion of ±4% when driven by an ideal clock input signal.
LVPECL INPUT-TO-LVPECL OUTPUT PARAMETERS
MAX
UNIT
tpd(lh)
Propagation delay, rising edge
PARAMETER
VOX to VOX
TEST CONDITIONS
MIN
320
TYP
600
ps
tpd(hl)
Propagation delay, falling edge
VOX to VOX
320
600
ps
tsk(p)
LVPECL pulse skew
VOX to VOX, see Note C in Figure 6.
100
ps
MAX
UNIT
JITTER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
JITTER CHARACTERISTICS
tjitterLVPECL
Additive phase jitter from input to
LVPECL output Y[2:0], see Figure 2.
12 kHz to 20 MHz,
fout = 250 MHz to 800 MHz,
divide-by-1 mode
0.15
50 kHz to 40 MHz,
fout = 250 MHz to 800 MHz,
divide-by-1 mode
0.25
ps rms
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ADDITIVE PHASE NOISE
vs
FREQUENCY OFFSET FROM CARRIER – LVPECL
LVPECL OUTPUT SWING
vs
FREQUENCY
0.90
−110
−120
0.85
−125
−130
−135
−140
−145
0.75
0.70
VDD = 3 V
0.65
0.60
0.55
−150
0.50
−155
0.45
−160
10
100
VDD = 3.6 V
0.80
LVPECL Output Swing − V
Additive Phase Noise − dBc/Hz
−115
VDD = 3.3 V
TA = 25°C
f = 622 MHz
÷1 Mode
1k
10k
100k
1M
10M
0.40
0.1
100M
VDD = 3.3 V
TA = 25°C
Load = 50 Ω to VDD − 2 V
0.3
0.5
0.7
0.9
1.1
1.3
1.5
f − Frequency − GHz
f − Frequency Offset From Carrier − Hz
G002
G001
Figure 2.
Figure 3.
SUPPLY CURRENT ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
IDDZ
8
MIN
Full load
No load
Outputs enabled, no output load, f = 800 MHz for LVPECL
outputs, VDD = 3.6 V
Supply current
IDD
TEST CONDITIONS
All outputs enabled and terminated with 50 Ω to
VDD – 2 V on LVPECL outputs, f = 800 MHz for LVPECL
outputs, VDD = 3.3 V
Supply current saving per LVPECL
output stage disabled, no load
f = 800 MHz for LVPECL output, VDD = 3.3 V
Supply current, 3-state
All outputs in high-impedance state by control logic,
f = 0 Hz, VDD = 3.6 V
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TYP MAX
UNIT
140
90
mA
0.5
mA
10
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SUPPLY CURRENT
vs
FREQUENCY
150
I DD − Supply Current − mA
VDD = 3.3 V,
TA = 255C,
50 W to VDD −2 V for LVPECL
145
3 LVPECL Outputs(P1) Running
140
135
130
100
300
500
700
900
1100
1300
1500
f − Frequency − MHz
G003
Figure 4.
PACKAGE THERMAL RESISTANCE
PARAMETER
RθJA-1
QFN-24 package thermal resistance
RθJA-2
QFN-24 package thermal resistance
with thermal vias in PCB (1)
(1)
TEST CONDITIONS
(1)
4-layer JEDEC test board (JESD51-7),
airflow = 0 ft/min
4-layer JEDEC test board (JESD51-7) with four
thermal vias of 22-mil diameter each,
airflow = 0 ft/min
MIN
TYP
MAX
UNIT
106.6
°C/W
55.4
°C/W
It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good
heat sink.
Example:
Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:
TChassis = 85°C (temperature of the chassis)
Peffective = Imax × Vmax = 90 mA × 3.6 V = 324 mW (max power consumption inside the package)
θTJunction = θJA-2 × Peffective = 55.45°C/W × 324 mW = 17.97°C
TJunction = θTJunction + TChassis = 17.97°C + 85°C = 103°C (the maximum junction temperature of
Tdie-max = 125°C is not violated)
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CONTROL INPUT CHARACTERISTICS
over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
tsu
Setup time, S0, S1, S2, and EN terminals before clock IN
th
Hold time, S0, S1, S2, and EN terminals after clock IN
t(disable)
Time between latching the EN low transition and when all
outputs are disabled (how much time is required until the
outputs turn off)
t(enable)
Time between latching the EN low-to-high transition and when
outputs are enabled based on control settings (how much time
passes before the outputs carry valid signals)
Rpullup
Internal pullup resistor on S[2:0] and EN input
VIH(H)
Three-level input high, S0, S1, S2, and EN terminals (1)
VIL(L)
Three-level low, S0, S1, S2, and EN terminals
IIH
(1)
TYP
MAX
ns
0
ns
42
10
ns
1
μs
60
78
kΩ
V
0.1 VDD
V
–5
μA
85
μA
MAX
UNIT
VI = VDD
VI = GND
UNIT
25
0.9 VDD
Input current, S0, S1, S2, and EN terminals
IIL
MIN
38
Leaving this terminal floating automatically pulls the logic level high to VDD through an internal pullup resistor of 60 kΩ.
BIAS VOLTAGE VBB
over operating free-air temperature range
PARAMETER
VBB
TEST CONDITIONS
Output reference voltage
MIN
VDD = 3 V–3.6 V, IBB = –0.2 mA
VDD – 1.4
TYP
VDD – 1.2
V
OUTPUT REFERENCE VOLTAGE (VBB)
vs
LOAD
4.0
VDD = 3.3 V
VBB − Output Reference Voltage − V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−5
0
5
10
15
20
25
30
35
I − Load − mA
G004
Figure 5.
10
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PARAMETER MEASUREMENT INFORMATION
IN
IN
Y0
Y0
tpd(LH1)
Y1
Y1
tpd(LH2)
Y2
Y2
NOTES: A. Output skew , tsk(o), is calculated as the greater of:
− The difference between the fastest and the slowest tpd(LH)n (n = 0…2)
− The difference between the fastest and the slowest tpd(HL)n (n = 0…2)
B. Part-to-part skew , tsk(pp), is calculated as the greater of:
− The difference between the fastest and the slowest tpd(LH)n ( (n = 0…2 for LVPECL across multiple devices
− The difference between the fastest and the slowest tpd(HL)n ( (n = 0…2 for LVPECL across multiple devices
C.
Pulseskew , tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL) and the low-to-high
(tpd(LH) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = | tpd(HL) − tpd(LH) |. Pulse skew
is sometimes referred to as pulse width distortion or duty cycle skew.
T0067-02
Figure 6. Waveforms for Calculation of tsk(o) and tsk(pp)
Yn
VOH
Yn
VOL
80%
VOUT(pp)
0V
20%
|Yn*Yn|
tr
tf
T0058-02
Figure 7. LVPECL Differential Output Voltage and Rise/Fall Time
PCB DESIGN FOR THERMAL FUNCTIONALITY
It is recommended to take special care of the PCB design for good thermal flow from the QFN 24-terminal
package to the PCB.
Due to the three LVPECL outputs, the current consumption of the CDCP1803 is fixed.
JEDEC JESD51-7 specifies thermal conductivity for standard PCB boards.
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PARAMETER MEASUREMENT INFORMATION (continued)
Modeling the CDCP1803 with a standard 4-layer JEDEC board results in a 59.5°C maximum temperature with
RθJA of 106.62°C/W for 25°C ambient temperature.
When deploying four thermal vias (one per quadrant), the thermal flow improves significantly, yielding 42.9°C
maximum temperature with RθJA of 55.4°C/W for 25°C ambient temperature.
To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications enabling all
four outputs at once.
Package Thermal Pad
(Underside)
Thermal Via
Dia 0.020 In.
Top Side
Island
Heat
Dissipation
VSS Copper Plane
VSS Copper Plane
M0029-01
Figure 8. Recommended Thermal Via Placement
See the Quad Flatpack No-Lead Logic Packages (SCBA017) and QFN/SON PCB Attachment (SLUA271)
application reports for further package-related information.
12
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APPLICATION INFORMATION
LVPECL RECEIVER INPUT TERMINATION
The input of the CDCP1803 has a high impedance and comes with a large common-mode voltage range.
For optimized noise performance, it is recommended to properly terminate the PCB trace (transmission line). If a
differential signal drives the CDCP1803, then a 100-Ω termination resistor is recommended to be placed as close
as possible across the input terminals. An even better approach is to install 2 × 50-Ω resistors, with the center
tap connected to a capacitor (C) to terminate odd-mode noise and make up for transmission line mismatches.
The VBB output can also be connected to the center tap to bias the input signal to (VDD – 1.3 V) (see Figure 9).
CDCP1803
CAC
IN
50 Ω
LVPECL
50 Ω
150 Ω
50 Ω
CAC
IN
50 Ω
VBB
150 Ω
C
S0085-02
Figure 9. Recommended AC-Coupling LVPECL Receiver Input Termination
CDCP1803
130 Ω
IN
50 Ω
LVPECL
83 Ω
130 Ω
IN
50 Ω
83 Ω
S0086-02
Figure 10. Recommended DC-Coupling LVPECL Receiver Input Termination
The CDCP1803 can also be driven by single-ended signals. Typically, the input signal becomes connected to
one input, while the complementary input must be properly biased to the center voltage of the incoming input
signal. For LVCMOS signals, this would be VCC/2, realized by a simple voltage divider (e.g., two 10-kΩ resistors).
The best option (especially if the dc offset of the input signal might vary) is to ac-couple the input signal and then
rebias the signal using the VBB reference output. See Figure 11.
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CDCP1803
SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013
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CDCP1803
CAC
IN
CLK
Rdc
IN
VBB
CCT
NOTE: CAC − AC-coupling capacitor (e.g., 10 nF)
CCT − Capacitor keeps voltage at IN constant (e.g., 10 nF)
Rdc − Load and correct duty cycle (e.g., 50 Ω)
VBB − Bias voltage output
S0087-02
Figure 11. Typical Application Setting for Single-Ended Input Signals Driving the CDCP1803
DEVICE BEHAVIOR DURING RESET AND CONTROL-TERMINAL SWITCHING
Output Behavior From Enabling the Device (EN = 0 → 1)
In disable mode (EN = 0), all output drivers are switched in high-Z mode. The S[2:0] control inputs are also
switched off. In the same mode, all flip-flops are reset. The typical current consumption is below 500 μA.
When the device is enabled again, it takes typically 1 μs for the settling of the reference voltage and currents.
During this time, the outputs Y[2:0] and Y[2:0] drive a high signal. After the settle time, the outputs go into the low
state. Due to the synchronization of each output driver signal with the input clock, the state of the waveforms
after enabling the device is as shown in Figure 12. The inverting input and output signal is not included. The Y:/1
waveform is the undivided output driver state.
14
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CDCP1803
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SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013
1 µs
EN
IN
Y:/1
High-Z
Undefined
Y:/2
High-Z
Undefined
Y:/4
High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = Low)
1 µs
Undivided State is Valid After the First
Positive Transition of the Input Clock
EN
IN
Y:/1
High-Z
Undefined
Y:/2
High-Z
Undefined
Y:/4
High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = High)
T0068-01
Figure 12. Waveforms
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Enabling a Single Output Stage
If a single output stage becomes enabled:
• Y[2:0] is either low or high (undefined).
• Y[2:0] is the inverted signal of Y[2:0].
With the first positive clock transition, the undivided output becomes the input clock state. The divided output
states are equal to the actual internal divider. The internal divider is not reset while enabling single output drivers.
ENABLE Yx:
Disabled
Enabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
IN
Yx:/1
High-Z
Undefined
Yx:/x
High-Z
Undefined
Divider State
T0069-01
Figure 13. Signal State After an Output Driver Becomes Enabled While IN = 0
ENABLE Yx:
Disabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
Enabled
IN
Yx:/1
High-Z
Undefined
Yx:/x
High-Z
Undefined
Divider State
T0070-01
Figure 14. Signal State After an Output Driver Becomes Enabled While IN = 1
spacer
REVISION HISTORY
Changes from Revision E (January 2007) to Revision F
Page
•
Changed tsk(pp) Part-to-part skew - included a MAX value of 300 ps .................................................................................... 7
•
Changed Note B in Figure 6 From: (n = 0…2 for LVPECL, n = 3 for LVCMOS) To: (n = 0…2 for LVPECLS) across ..... 11
16
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCP1803RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CDCP
1803
CDCP1803RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CDCP
1803
CDCP1803RGETG4
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CDCP
1803
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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