CLC409AJ-QML

CLC409 Very Wideband, Low Distortion Monolithic Op Amp General Description Features The CLC409 is a very wideband, DC coupled monolithic operational amplifier designed specifically for wide dynamic range systems requiring exceptional signal fidelity. Benefiting from National’s current feedback architecture, the CLC409 offers a gain range of ± 1 to ± 10 while providing stable, oscillation free operation without external compensation, even at unity gain. With its 350MHz small signal bandwidth (VOUT = 2VPP), 10-bit distortion levels through 20MHz (RL = 100Ω), 8-bit input referred distortion levels through 60MHz, 2.2nV/ noise and 13.5mA supply current, the CLC409 is the ideal driver or buffer for high speed flash A/D and D/A converters. n n n n n n n Wide dynamic range systems such as radar and communication receivers requiring a wideband amplifier offering exceptional signal purity will find the CLC409’s low input referred noise and low harmonic and intermodulation distortion make it an attractive high speed solution. Constructed using an advanced, complimentary bipolar process and National’s proven current feedback architecture, the CLC409 is available in several versions to meet a variety of requirements. 350MHz small signal bandwidth -65/−72dBc 2nd/3rd harmonics (20MHz) Low noise 8ns settling to 0.1% 1200V/µs slew rate 13.5mA supply current ( ± 5V) 60mA output current Applications n n n n n n n Flash A/D driver D/A transimpedance buffer Wide dynamic range IF amp Radar/communication receivers DDS post-amps Wideband inverting summer Line driver Harmonic Distortion vs. Load and Frequency Enhanced Solutions (Military/Aerospace) SMD Number: 5962-92034 Space level versions also available. For more information, visit http://www.national.com/mil 01274804 Connection Diagrams 01274815 01274814 Pinout DIP & SOIC © 2002 National Semiconductor Corporation Pinout SOT23-5 DS012748 www.national.com CLC409 Very Wideband, Low Distortion Monolithic Op Amp September 2002 CLC409 Absolute Maximum Ratings Operating Temperature Range (Note 1) Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. −40˚C to +85˚C −65˚C to +150˚C Lead Solder Duration (+300˚C) 10 sec ESD rating (human body model) 1000V ± 7V Supply Voltage (VCC) IOUT Output is short circuit protected to ground, but maximum reliability will be maintained if IOUT does not exceed... 60mA MDIP Common Mode Input Voltage ± VCC Operating Ratings Thermal Resistance Package Differential Input Voltage Junction Temperature 10V (θJC) (θJA) 95˚C/W 115˚C/W SOIC 75˚C/W 160˚C/W SOT23-5 115˚C/W 185˚C/W +150˚C Electrical Characteristics AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω; unless specified Symbol Parameter Ambient Temperature Conditions CLC409AJ Typ Max/Min (Note 2) Units +25˚C −40˚C +25˚C +85˚C VOUT < 2VPP 350 110 > 250 > 90 > 250 > 90 > 200 > 80 MHz VOUT < 5VPP < 0.4 < 0.8 < 1.0 < 2.0 < 0.8 < 0.07 < 0.07 < 0.02 < 0.02 < 0.4 < 0.8 < 1.0 < 2.2 < 0.8 < 0.06 < 0.06 < 0.02 < 0.02 < 0.4 < 0.8 < 1.0 < 3.0 < 1.0 < 0.06 < 0.06 < 0.02 < 0.02 dB < 1.6 < 4.2 < 12 < 15 > 1000 < 1.6 < 4.2 < 12 < 18 > 1000 < 1.6 < 4.6 < 12 < 18 > 1000 < −78 < −56 < −41 < −76 < −65 < −52 < −81 < −56 < −44 < −76 < −65 < −52 < −81 < −56 < −44 < −76 < −65 < −52 < 2.8 < 18 < 4.0 < −155 < 47 < 2.8 < 18 < 4.0 < −155 < 47 < 3.1 < 20 < 4.5 < −154 < 52 Frequency Domain Performance SSBW -3dB Bandwidth LSBW Gain Flatness VOUT GFPL Peaking DC to 75MHz 0 GFPH Peaking > 75MHz 0 GFR1 Rolloff DC to 125MHz 0.2 @ 200MHz 1.0 LPD Linear Phase Deviation DC to 100MHz 0.3 DG1 Differential Gain RL =150Ω, 3.58MHz 0.03 RL =150Ω, 4.43MHz 0.03 Differential Phase RL = 150Ω, 3.58MHz 0.01 RL =150Ω, 4.43MHz 0.01 2V Step 1.3 5V Step 3.5 8 GFR2 Rolloff DG2 DP1 DP2 MHz < 0.5VPP dB dB dB deg % % deg deg Time Domain Response TRS Rise and Fall Time TRL TS Settling Time to ± 0.1% 2V Step OS Overshoot 2V Step SR Slew Rate 5 1200 ns ns ns % V/µs Distortion And Noise Response HD2L 2VPP, 5MHz −86 HD2 2VPP, 20MHz −65 HD2H 2VPP, 60MHz −49 2VPP, 5MHz −84 HD3 2VPP, 20MHz −72 HD3H 2VPP, 60MHz −59 2.2 HD3L 2nd Harmonic Distortion 3rd Harmonic Distortion dBc dBc dBc dBc dBc dBc Equivalent Input Noise VN Non-Inverting Voltage ICN Inverting Current NCN Non-Inverting Current SNF Total Noise Floor > 1MHz > 1MHz > 1MHz > 1MHz INV Total Integrated Noise 1MHz to 150MHz www.national.com 14.3 3.2 −157 2 38 nV/ pA/ pA/ dBm1Hz µV CLC409 Electrical Characteristics (Continued) AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω; unless specified Symbol Parameter Conditions Typ Max/Min (Note 2) Units Static, DC Performance VIO DVIO IBN DIBN IBI DIBI Input Offset Voltage (Note 3) 0.5 Average Temperature Coefficient Input Bias Current (Note 3) 25 Non Inverting 10 Average Temperature Coefficient Input Bias Current (Note 3) 100 Inverting 10 Average Temperature Coefficient 100 PSRR Power Supply Rejection Ratio 50 CMRR Common Mode Rejection Ratio 50 ICC Supply Current (Note 3) No Load 13.5 < 8.5 < 50 < 44 < 275 < 36 < 200 > 45 > 45 < 14.2 < 4.5 > 45 > 45 < 14.2 < 9.5 < 50 < 22 < 125 < 30 < 100 > 45 > 45 < 14.2 > 250 ± 3.0 > 500 ± 3.2 > 1000 ± 3.2 kΩ ± 1.5 ± 2.0 ± 2.0 V 36 50 50 mA - < 22 - < 20 - mV µV/˚C µA nA/˚C µA nA/˚C dB dB mA Miscellaneous Performance RIN Non-Inverting Input Resistance CIN Non-Inverting Input Capacitance 1000 RO Output Impedance DC VO Output Voltage Range RL = 100Ω CMIR Common Mode Input Range IO Output Current 1 0.1 ± 3.5 ± 2.2 60 pF Ω V Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Ordering Information Package Temperature Range Industrial Part Number Package Marking NSC Drawing 8-pin plastic DIP −40˚C to +85˚C CLC409AJP CLC409AJP N08E 8-pin plastic SOIC −40˚C to +85˚C CLC409AJE CLC409AJE M08A 5-pin SOT −40˚C to +85˚C CLC409AJM5 A18 MA05A 3 www.national.com CLC409 Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC = ± 5V, RL = 100Ω, Rf = 500Ω; Unless Specified). Non-Inverting Frequency Response Inverting Frequency Response 01274801 01274802 Frequency Response for Various RLS Small Signal Pulse Response 01274803 01274816 Short-Term Settling Response Long-Term Settling Time 01274817 01274818 www.national.com 4 Harmonic Distortion vs. Load and Frequency 2-Tone, 3rd Order Spurious Levels 01274805 01274804 Settling Time vs. Capacitive Load 2nd Harmonic Distortion vs. POUT 01274807 01274806 3rd Harmonic Distortion vs. POUT Typical D.C. Errors vs. Temperature 01274808 01274819 5 www.national.com CLC409 Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC = ±5V, RL = 100Ω, Rf = 500Ω; Unless Specified). (Continued) CLC409 Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC = ±5V, RL = 100Ω, Rf = 500Ω; Unless Specified). (Continued) Equivalent Input Noise PSRR, CMRR, and Closed Loop RO 01274809 01274810 Open-Loop Transimpedance Gain, Z(s) 01274811 www.national.com 6 CLC409 Application Division 01274812 FIGURE 1. Recommended Non-Inverting Gain Circuit 01274813 FIGURE 2. Recommended Inverting Gain Circuit Harmonic Distortion The CLC409 has been optimized for exceptionally low harmonic distortion while driving very demanding resistive or capacitive loads. Generally, when used as the input amplifier to very high speed flash ADCs, the distortions introduced by the converter will dominate over the low CLC409 distortions shown on the plots on the previous page. The 0.01µF capacitor (Css) shown across the supplies in Figure 1 and Figure 2 is critical to achieving the lowest 2nd harmonic distortion. The 2-tone, 3rd order spurious plot shows a relatively constant difference between the test power level and the spurious level with that difference depending on frequency. The Feedback Resistor The CLC409 achieves its excellent pulse and distortion performance by using the current feedback topology pioneered by Comlinear Corporation. The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the feedback resistor value. The CLC409 is optimized for use with a 250Ω feedback resistor. Using lower values can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth. Application Note OA-13 discusses this in detail along with the occasions where a different Rf might be advantageous. 7 www.national.com CLC409 Application Division through from the convert signal. Also, Cin is oftentimes a voltage dependent capacitance. This input impedance non-linearity will induce distortion terms that will increase as Rs is increased. Only slight adjustments up or down from the recommended Rs value should therefore be attempted in optimizing system performance. (Continued) CLC409 does not show an intercept type performance. (where the relative spurious levels change at a 2X rate vs. the test tone powers), due to an internal full power bandwidth enhancement circuit that boosts the performance as the output swing increases while dissipating negligible quiescent power under low output power conditions. This feature enhances the distortion performance and full power bandwidth to match that of much higher quiescent supply current parts. DC Accuracy and Noise The CLC409 offers an improved offset voltage over the pin compatible CLC400 low gain amplifier. The offset adjustment available on the CLC400 was therefore not included in this part. The Output Offset equation below shows the output offset computation equation for the non-inverting configuration with an example using the typical bias current and offset specifications for AV = +2. Output Offset VO =( ± IbnRin ± Vio)(1+Rf/Rg) ± IbiRf Example Computation for AV =+2, Rf =250Ω, Rin =25Ω: VO =( ± 10µA (25Ω) ± 0.5mV)2 ± 10µA (250Ω)= ± 3.25mV This low output offset voltage is a marked improvement over earlier very high speed amplifiers. Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in Application Note OA-7. The two input bias currents are physically unrelated in both magnitude and polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the source impedance for the two inputs (as is commonly done for matched input bias current devices). The total output noise is computed in a similar fashion to output offset voltage. Using the input noise voltage and two input noise currents, the output noise is developed through the same gain equations for each term but combined as the square root of the sum of squared contributing elements. See Application Note OA-12 for a full discussion of noise calculations for current feedback amplifiers. Printed Circuit Layout 01274820 FIGURE 3. Input Amplifier to ADC Figure 3 shows a typical application using the CLC409 to drive an ADC. The series resistor, Rs, between the amplifier output and the ADC input is critical to achieving best system performance. This load capacitance, if applied directly to the output pin, can quickly lead to unacceptable levels of ringing in the pulse response. The plot of Rs and settling time vs. CL on the previous page is an excellent starting point for setting Rs. The value derived in that plot minimizes the step settling time into a fixed discrete capacitive load. Several additional constraints should be considered, however, in driving the capacitive input or an ADC. There is an option to increase Rs, bandlimiting at the ADC input for either noise or Nyquist bandlimiting purposes. Increasing Rs too much, however, can induce an unacceptably large input glitch due to switching transients coupling www.national.com As with any high speed component, a careful attention to the board layout is necessary for optimum performance. Evaluation PC boards (CLC730013-DIP, CLC730027-SOIC, and CLC730068-SOT) for the CLC409 are available. This additional supply bypassing capacitor, Css, can easily be added to the board if desired. Further layout suggestions can be found in Application Note OA-15. 8 CLC409 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin MDIP NS Package Number N08E 8-Pin SOIC NS Package Number M08A 9 www.national.com CLC409 Very Wideband, Low Distortion Monolithic Op Amp Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 5-Pin SOT23 NS Package Number MA05A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.