CLC502AE-QML

CLC502 Clamping, Low Gain Op Amp with Fast 14-bit Settling General Description Features The CLC502 is an operational amplifier designed for low gain applications requiring output voltage clamping. This feature allows the designer to set maximum positive and negative output voltage levels for the amplifier – thus allowing the CLC502 to protect downstream circuitry, such as delicate converter systems from destructive transients or signals which would otherwise cause saturation. The overload recovery time of only 8ns permits systems to resume operation quickly after overdrive. High accuracy systems will also benefit from the CLC502’s fast, accurate settling. Settling to 0.0025% in 25ns (32ns guaranteed over temperature), the CLC502 is ideal as the input amplifier in high accuracy (12 bits and above) A/D systems. Unlike most other high speed op amps, the CLC502 is free of settling tails. And, as the settling plots show, settling to 0.01% accuracy is an even faster 18ns typical. The CLC502 is also useful in other applications which require low gain amplification ( ± 1 to ± 8) and the clamping or overload recovery features. For example, even low resolution imaging circuits, which often have to cope with overloading signal levels, can benefit from clamping and overload recovery. The CLC502 is available in several versions to meet a variety of requirements. A three-letter suffix determines the version: Enhanced Solutions (Military/Aerospace) SMD Number: 5962-91743 n n n n Output clamping with fast recovery 0.0025% settling in 25ns (32ns max) Low power, 170mW Low distortion. −50dBc at 20MHz Applications n n n n Output clamping applications High accuracy A/D systems (12-14 bits) High accuracy D/A converters Pulse amplitude modulation systems Clamped Pulse Response (8x Overdrive) DS012754-1 *Space level versions also available. *For more information, visit http://www.national.com/mil Connection Diagram DS012754-2 Pinout DIP & SOIC Ordering Information Package Temperature Range Industrial Part Number Package Marking 8-pin Plastic DIP −40˚C to +85˚C CLC502AJP CLC502AJP N08E 8-pin Plastic SOIC −40˚C to +85˚C CLC502AJE CLC502AJE M08A © 2001 National Semiconductor Corporation DS012754 NSC Drawing www.national.com CLC502 Clamping, Low Gain Op Amp with Fast 14-bit Settling January 2001 CLC502 Absolute Maximum Ratings (Note 1) Operating Temperature Range Storage Temperature Range Lead Solder Duration (+300˚C) ESD (Human Body Model) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) IOUT Output is short circuit protected to ground, but maximum reliability will be maintained if IOUT does not exceed... Common Mode Input Voltage Junction Temperature ± 7V −40˚C to +85˚C −65˚C to +150˚C 10 sec 1000V Operating Ratings Thermal Resistance Package MDIP SOIC 60mA ± VCC +150˚C θJA 120˚C/W 140˚C/W θJC 65˚C/W 60˚C/W Electrical Characteristics (AV = +2, VCC = ± 5V, RL =100Ω, Rf = 250Ω, VH = +3V, VL = −3V) Symbol Parameter Ambient Temperature Conditions Typ CLC502AJ Max/Min Ratings (Note 2) Units +25˚C −40˚C +25˚C +85˚C VOUT < 0.5VPP 150 65 > 110 > 40 > 100 > 40 MHz VOUT < 5VPP > 100 > 40 < 0.4 < 0.7 < 1.0 < 1.2 < 0.3 < 0.5 < 1.0 < 1.0 < 0.4 < 0.7 < 1.0 < 1.2 dB < 3.5 500 < 3.2 500 < 3.5 500 Frequency Domain Performance SSBW -3dB Bandwidth LSBW Gain Flatness GFPL Peaking DC to 25MHz GFPH Peaking > 25MHz GFR Rolloff (Note 5) DC to 50MHz 0.5 DC to 50MHz 0.4 LPD Linear Phase Deviation MHz VOUT < 0.5VPP 0 0 dB dB deg Time Domain Performance TRS Rise and Fall Time TRL TS14 Settling Time to ± 0.0025% ± 0.01% ± 0.1% TSP TSS OS Overshoot SR Slew Rate 0.5V Step 2.7 5V Step 5.0 2V Step 25 2V Step 18 2V Step 10 0.5V Step 0 800 ns ns ns ns ns % V/µs Distortion And Noise Performance HD2 2nd Harmonic Distortion 2VPP, 20MHz −50 3rd Harmonic Distortion 2VPP, 20MHz −60 < −38 < −53 < −43 < −53 < −43 < −53 dBc HD3 dBc Equivalent Input Noise SNF Noise Floor > 1MHz −157 < −155 < −155 < −155 dBm (1Hz) INV Integrated Noise 1MHz to 150MHz 40 < 49 < 49 < 49 µV DG Differential Gain (Note 4) 0.01 – – – % DP Differential Phase (Note 4) 0.05 – – – deg Clamp performance OVC Overshoot in Clamp 2x Overdrive 5 – % Overload Recovery from Clamp 2x Overdrive 8 ± 0.2 20 < 15 < ± 0.3 < 35 ns 2x Overdrive < 15 < ± 0.3 < 75 < 10 < 15 < ± 0.3 < 35 – TSO µA 50 – – – MHz < ± 3.0 < ± 3.3 < ± 3.3 V < 2.6 < 1.6 < 2.8 mV VOC Clamp Accuracy(Note 3) ICL Input Bias Current on VH, or VL CBW −3dB Bandwidth VL or VH = 2VPP CMC Clamp Voltage Range VH or VL V Static, DC Performance VIO Input Offset Voltage (Note 3) www.national.com 0.5 2 CLC502 Electrical Characteristics (Continued) (AV = +2, VCC = ± 5V, RL =100Ω, Rf = 250Ω, VH = +3V, VL = −3V) Symbol Parameter Conditions Typ Max/Min Ratings (Note 2) Units Static, DC Performance 3 < 12 – < 12 µV/˚C 10 < 45 < 250 < 25 < 35 < 100 nA/˚C < 50 < 250 < 30 – < 40 < 100 nA/˚C > 55 > 55 < 23 > 60 > 60 < 23 > 60 > 60 < 23 > 50 < 5.5 < 0.2 > 2.0 > ± 3.0 > ± 25 > 85 < 5.5 < 0.2 > 2.5 > ± 3.2 > ± 45 > 85 < 5.5 < 0.2 > 2.5 > ± 3.2 > ± 45 DVIO Average Temperature Coefficient IBN Input Bias Current (Note 3) DIBN Average Temperature Coefficient IBI Input Bias current (Note 3) DIBI Average Temperature Coefficient 100 PSRR Power Supply Rejection Ratio 68 CMRR Common Mode Rejection Ratio ICC Supply Current (Note 3) Non-Inverting 100 Inverting 10 65 No Load 17 Resistance 150 – µA µA dB dB mA Miscellaneous Performance RIN Non-Inverting Input CIN RO Output Impedance CMIR Common Mode Input Range VO Output Voltage Range IO Output Current Capacitance 35 at DC 0.1 3.0 ± 3.5V ± 55 No Load kΩ pF Ω V V mA Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Note 4: Differential gain and phase measure at Av = +2V, R = 250Ω Note 5: RL = 150Ω, 1VPP equivalent video signal, 0-100 IRE, 40 IREPP 0 IRE = 0 volts, at 75Ω load and 3.58 MHz Typical Performance Characteristics (TA = 25˚, AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω, VH = +3V, VL = −3V) Inverting Frequency Response Non-Inverting Frequency Response DS012754-5 DS012754-3 3 www.national.com CLC502 Typical Performance Characteristics (TA = 25˚, AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω, VH = +3V, VL = −3V)) (Continued) Frequency Response for Various RLs Open-Loop Transimpedance Gain, Z(s) DS012754-5 DS012754-6 2nd and 3rd Harmonic Distortion 2-Tone, 3rd Order Intermodulation Intercept DS012754-8 DS012754-7 Equivalent Input Noise CMRR and PSRR DS012754-9 www.national.com DS012754-10 4 (TA = 25˚, AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω, VH = +3V, VL = −3V)) (Continued) Clamped Pulse Response (8x Overdrive) Settling, Clamped (4x overdrive) DS012754-11 DS012754-12 Long-Term Settling, Clamped (4x overdrive) Nonlinearity Near Clamp Voltage DS012754-14 DS012754-13 Settling, Umclamped Long-Term Settling, Unclamped DS012754-15 DS012754-16 5 www.national.com CLC502 Typical Performance Characteristics CLC502 Typical Performance Characteristics (TA = 25˚, AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 250Ω, VH = +3V, VL = −3V)) (Continued) Settling Time vs. Capacitive Load DS012754-17 Application Division DS012754-18 FIGURE 1. Recommended Non-Inverting Gain Circuit www.national.com 6 CLC502 Application Division (Continued) DS012754-19 FIGURE 2. Recommended Inverting Gain Circuit DS012754-20 FIGURE 3. Location of Damping Resistors (RQ) 7 www.national.com CLC502 Application Division longer trying to drive the output voltage above the clamp voltage. When this occurs, there is typically a 5-10ns “overload recovery from clamp,” which is the time it takes for the op amp to resume linear operation. The normal op amp parameters, such as the rise time, apply when the op amp is in linear operation. (Continued) Clamp Operation The maximum positive or negative excursion of the output voltage is determined by voltages applied to the clamping pins, VH and VL. VH determines the positive clamping level; VL determines the negative level. For example, if VH is set at +2V and VL is set at −0.5V the output voltage is restricted within this −0.5V to +2V range. When the output voltage tries to exceed this level, the amplifier goes into “clamp mode” and the output voltage limits at the clamp voltage. Clamp Accuracy and Amplifier Linearity Ideally, the clamped output voltage and the clamp voltage should be identical. In practice, however, there are two sources of clamp inaccuracy: the inherent clamp accuracy (which is shown in the specification page) and resistor divider action of open-loop output resistance of 10Ω and the load resistor. Or, in equation form, Optimizing Settling Time Performance To obtain the best possible settling time performance for the CLC502, some additional design criteria must be considered, particularly when driving loads of less than 500Ω. When driving a 100Ω load, a step of a few volts on the output will create a large step of current in the power supplies. In some cases, this step will cause a small ringing on the power supply due to the bypass capacitor (.1µF) oscillating with the inductance in the power supply trace. The critical trace is the power supply trace between the two capacitors (a trace inductance of 20nH will be enough to degrade settling time performance). The frequency of the ring can be determined by (1) When settling the clamp voltages, the designer should also recognize that within about 200mV of the clamp voltages, amplifier linearity begins to deteriorate. (See plot on previous page.) Biasing VH and VL (3) and any reduction in this frequency will improve performance due to better power supply rejection at lower frequencies . To obtain the best performance, small resistor, RQ, may be added in the trace to dampen the circuit (SeeFigure 3). An RQ of 5-10Ω will result in excellent settling performance and will have only minor impact on other performance characteristics. No provision for RQ has been made on the evaluation board available from National as part #730013. It can, however, be easily added by cutting a trace and adding a 5- 10Ω resistor, as shown in Figure 3, for both supplies. DC Accuracy and Notes Since the two inputs for the CLC502 are quite dissimilar, the noise and offset error performance differs somewhat from that of a standard differential input amplifier. The two input bias currents are physically unrelated rendering bias current cancellation through matching of the inverting and non-inverting source resistance ineffective. In Equation 3, the output offset is the algebraic sum of the equivalent input voltage and current sources that influence DC operation. Output noise is determine similarly except that a root-sum-of-squares replaces the algebraic sum. Rs is the non-inverting pin source resistance. Output Offset Vo = ± IBN x Rs (1 + Rf/Rg) ± Each of the clamping pins is buffered internally so simple resistive voltage divider circuits work well in providing the clamp voltages. VL and VH can be set by choosing the divider resistors using: (2) As a general guideline, let R1 + R2 ≅ R3 + R4 ≅5kΩ. VH should be biased more positively than VL. VH may be biased below 0V; however, with this biasing, the output voltage will actually clamp at 0V unless a simple pull down circuit is added to the op amp output (when clamped against VH, the output cannot sink current). An analogous situation and design solution exists for VL when it is biased above 0V, but in this case, a pull up circuit is used to source current when the amplifier is clamped against VL. The clamp voltage range rating is that for normal operation. Problems in over driven linearity may occur if the clamps are set outside this range so this is not suggested under any conditions. If the clamping capability is not required, the CLC402 (low gain op amp with fast 14-bit settling) may be a more appropriate part. The clamps, which have a bandwidth of about 50MHz, may be driven by high frequency signal source. This allows the clamping level to be modulated, which is useful in many applications such as pulse amplitude modulation. The source resistance of the signal source should be less than 500Ω to ensure stability. Clamp-Mode Dynamics As can be seen in the clamped pulse response plot, clamping is virtually instantaneous. Note, however, that there can be a small amount of overshoot, as indicated on the specification page. The output voltage stays at the clamp voltage level as long as the product of the input voltage and the gain setting exceeds the clamp voltage. When the input voltage decreases, it will eventually reach a point where it is no www.national.com VIO (1+ Rf /Rg) ± IBI x Rf Printed Circuit Layout As with any high frequency device, a good PCB layout will enhance performance. Ground plane construction and good power supply bypassing close to the package are critical to achieving full performance. In the non-inverting configuration, the amplifier is sensitive to stray capacitance to ground at the inverting input. Hence, the inverting node connections should be small with minimal coupling to the ground plane. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. The device is also very sensitive to parasitic capacitance on the output pin. The plots include a suggested series RS to de-couple this effect. Evaluation boards (part number 730013 for through-hole and 730027 for SOIC) for the CLC502 are available. 8 CLC502 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 8-Pin MDIP NS Package Number N08E 9 www.national.com CLC502 Clamping, Low Gain Op Amp with Fast 14-bit Settling Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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