CLC5958SLB

OBSOLETE CLC5958 www.ti.com SNWS003C – JUNE 1999 – REVISED APRIL 2013 CLC5958 14-Bit, 52 MSPS A/D Converter Check for Samples: CLC5958 FEATURES DESCRIPTION • • • • • The CLC5958 is a monolithic 14-bit, 52 MSPS analog-to-digital converter. The ultra-wide dynamic range and high sample rate of the device make it an excellent choice for wideband receivers found in multi-channel base-stations. The CLC5958 integrates a low distortion track-and-hold amplifier and a 14-bit multi-stage quantizer on a single die. Other features include differential analog inputs, low jitter differential clock inputs, an internal bandgap voltage reference, and CMOS/TTL compatible outputs. The CLC5958 is fabricated on the ABIC-V 0.8 micron BiCMOS process. 1 2 Ultra-wide Dynamic Range Excellent Performance to Nyquist IF Sampling Capability Very Small Package: 48-pin PLGA Programmable Output Levels: 3.3V to 5V KEY SPECIFICATIONS • • • Sample Rate 52 MSPS SFDR 90 dB Noise Floor −72 dBFS APPLICATIONS • • • • • Multi-channel Basestations Multi-standard Basestations: – GSM, WCDMA, DAMPS, etc. Smart Antenna Systems Wireless Local Loop Wideband Digital Communications The CLC5958 features a 90 dB spurious free dynamic range (SFDR) and 70 dB signal-to-noise ratio (SNR). The balanced differential analog inputs ensure low even-order distortion, while the differential clock inputs permit the use of balanced clock signals to minimize clock jitter. The 48-pin PLGA package provides an extremely small footprint for applications where space is a critical consideration. The package also provides a very low thermal resistance to ambient. The CLC5958 may be operated with a single +5V power supply. Alternatively, an additional supply may be used to program the digital output levels over the range of +3.3V to +5V. Operation over the industrial temperature range of −40°C to +85°C is ensured. National Semiconductor tests each part to verify compliance with the ensured specifications. Block Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated OBSOLETE CLC5958 SNWS003C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Pin Configuration Figure 1. 48 Pin PLGA See Package Number NPB PIN DESCRIPTIONS Pin Name Pin No. Description AIN, AIN 13, 14 Differential inputs. Self biased at a common mode voltage of +3.25V. The ADC full scale input is 2.048 VPP differential. ENCODE, ENCODE 9, 10 Differential clock inputs. ENCODE initiates a new data conversion cycle on each rising edge. Clock signals may be sinusoidal or square waves with PECL encode levels. The falling edge of ENCODE clocks internal pipeline stages. 28–34, 39–45 Digital data outputs. CMOS and TTL compatible. D0 is the LSB and D13 is the inverted MSB. Output coding is two's complement. D0–D13 DAV 27 Data valid. The rising edge of this signal occurs when output data is valid and may be used to latch data into following circuitry. VCM 21 Internal analog input common mode voltage reference. Nominally +3.25V. Can be used to establish the analog input common mode voltage for DC coupled applications (DC coupling not recommended, see CLC5958 Application Information). GND 1–4, 8, 11, 12, 15, 19, 20, 23–26, 35, 36, 47, 48 and vias VCC 5–7, 16–18, 22, 46 DVCC 37, 38 Circuit ground. +5V power supply. Bypass each group of supply pins to ground with a 0.01 µF capacitor. +3.3V to +5V power supply for the digital outputs. Establishes the high output level for the digital outputs. Bypass to ground with a 0.1 µF capacitor. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5958 OBSOLETE CLC5958 www.ti.com SNWS003C – JUNE 1999 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −0.5V to +6V Positive Supply Voltage (VCC) Differential Voltage between any Two Grounds 183°C: 75 sec Solder Temperature: 215°C (max solder temperature): 235°C Dwell Time @ Max. Temp: 5 sec Ramp Down: 2°C/sec Minimum Conversion Rate This ADC is optimized for high-speed operation. The internal bipolar track and hold circuits will cause droop errors at low sample rates. The point at which these errors cause a degradation of performance is listed on the specifications page as the minimum conversion rate. If a lower sample rate is desired, the ADC should be clocked at a higher rate, and the output data should be decimated. For example, to obtain a 10MSPS output, the ADC should be clocked at 20MHz, and every other output sample should be used. No significant power savings occurs at lower sample rates, since most of the power is used in analog circuits rather than digital circuits. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5958 13 OBSOLETE CLC5958 SNWS003C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Evaluation Board Figure 28. Evaluation Board Schematic 14 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5958 OBSOLETE CLC5958 www.ti.com SNWS003C – JUNE 1999 – REVISED APRIL 2013 Figure 29. CLC5958PCASM Layer 1 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5958 15 OBSOLETE CLC5958 SNWS003C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Figure 30. CLC5958PCASM Layer 2 16 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5958 OBSOLETE CLC5958 www.ti.com SNWS003C – JUNE 1999 – REVISED APRIL 2013 Figure 31. CLC5958PCASM Layer 3 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5958 17 OBSOLETE CLC5958 SNWS003C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Figure 32. CLC5958PCASM Layer 4 Evaluation Printed Circuit Board The CLC5958 evaluation printed circuit board provides a convenient test bed for rapid evaluation of the CLC5958. It illustrates the proper approach to layout in order to achieve best performance, and provides a performance benchmark. Analog Input The CLC5958 evaluation board is configured to be driven by a single-ended signal at the AIN SMA connector (the AIN connector is disconnected). The AIN SMA connector should be driven from a 50Ω source impedance. A full scale input is approximately 1.4 VPP (7 dBm). The single-ended input is converted to a differential input by an on-board transformer. When performing sine wave testing, it is critical that the input sine wave be filtered to remove harmonics and source noise. 18 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5958 OBSOLETE CLC5958 www.ti.com SNWS003C – JUNE 1999 – REVISED APRIL 2013 Encode Input The CLK SMA connector is the encode input and should also be driven from a 50Ω source. A low jitter 16 dBm sine wave should be applied at this input. In some cases it may be necessary to band-pass filter the sine wave in order to achieve low jitter. The single-ended clock input is converted to a differential signal by an on-board transformer and buffered by an ECL buffer. Digital Outputs The digital outputs are available at the Eurocard connector (J1). Data bits D0 through D13 are available at J1 pins 18B through 5B. The data ready signal (labeled DR in the schematic) is available at J1 pin 20B. These outputs are also available at the HP 01650-63203 termination adapter for direct connection to an HP logic analyzer (see Figure 28). The outputs are buffered by 3.3V digital latches. The falling edge of the data ready signal may be used to latch the output data. Supply Voltages Power is sourced to the board through the Eurocard connector. A 5V supply should be connected at J1 pins 32A and 32B. A 3.3V supply should be connected at J1 pins 31A and 31B. The ground return for these supplies is at J1 pins 27A, 27B, 28A, and 28B. It is recommended that low noise linear supplies be used. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5958 19 OBSOLETE CLC5958 SNWS003C – JUNE 1999 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 20 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 19 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5958 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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