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DAC7811
SBAS337E – APRIL 2005 – REVISED MARCH 2018
DAC7811 12-Bit, Serial Input, Multiplying Digital-to-Analog Converter
1 Features
3 Description
•
•
•
•
•
•
The DAC7811 is a CMOS, 12-bit, current output
digital-to-analog converter (DAC). This device
operates from a 2.7-V to 5.5-V power supply, making
it suitable for battery-powered and many other
applications.
1
•
•
•
•
•
•
•
2.7-V to 5.5-V Supply Operation
50-MHz Serial Interface
10-MHz Multiplying Bandwidth
±15-V Reference Input
Low Glitch Energy: 5 nV-s
Extended Temperature Range:
–40°C to +125°C
10-Pin VSSOP Package
12-Bit Monotonic
4-Quadrant Multiplication
Power-On Reset With Brownout Detection
Daisy-Chain Mode
Readback Function
Industry-Standard Pin Configuration
This DAC uses a double-buffered 3-wire serial
interface that is compatible with SPI, QSPI™,
MICROWIRE, and most DSP interface standards. In
addition, a serial data out pin (SDO) allows for daisychaining when multiple devices are used. Data
readback allows the user to read the contents of the
DAC register via the SDO pin. On power-up, the
internal shift register and latches are filled with zeroes
and the DAC outputs are at zero scale.
The
DAC7811
offers
excellent
4-quadrant
multiplication characteristics, with large signal
multiplying bandwidth of 10 MHz. The applied
external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback
resistor (RFB) provides temperature tracking and fullscale voltage output when combined with an external
current-to-voltage precision amplifier.
2 Applications
•
•
•
•
•
•
•
•
Portable Battery-Powered Instruments
Waveform Generators
Analog Processing
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
The DAC7811 is available in a 10-lead VSSOP
package.
Device Information(1)
PART NUMBER
DAC7811
PACKAGE
VSSOP (10)
BODY SIZE (NOM)
3.00 mm 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Block Diagram
VDD
VREF
R
DAC7811
RFB
12-Bit
R-2R DAC
IOUT 1
IOUT 2
DAC Register
Power-On
Reset
Input Latch
SYNC
SCLK
SDIN
Control Logic and
Input Shift Register
SDO
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC7811
SBAS337E – APRIL 2005 – REVISED MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Typical Characteristics: VDD = 5 V............................ 6
Typical Characteristics: VDD = 2.7 V......................... 9
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 19
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2016) to Revision E
•
Changed Figure 28 SDO pin timing to remove Hi-Z ............................................................................................................ 14
Changes from Revision C (July 2007) to Revision D
•
2
Page
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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SBAS337E – APRIL 2005 – REVISED MARCH 2018
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
MSOP PACKAGE
(TOP VIEW)
IOUT1
1
10
IOUT2
2
9
GND
3
8
VDD
SCLK
4
5
7
6
SDO
SDIN
RFB
VREF
SYNC
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
IOUT1
O
DAC Current Output
2
IOUT2
O
DAC Analog Ground. This pin is normally tied to the analog ground of the system.
3
GND
G
Ground pin.
4
SCLK
I
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the
serial clock input. Alternatively, by means of the serial control bits, the device may be configured such
that data is clocked into the shift register on the rising edge of SCLK.
5
SDIN
I
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock
input. By default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The
control bits allow the user to change the active edge to the rising edge.
I
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is
loaded to the shift register on the active edge of the following clocks (power-on default is falling clock
edge). In stand-alone mode, the serial interface counts the clocks and data is latched to the shift
register on the 16th active clock edge.
SDO
O
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into
the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data will always be
clocked out on the alternate edge to loading data to the shift register. Writing the Readback control
word to the shift register makes the DAC register contents available for readback on the SDO pin,
clocked out on the opposite edges to the active clock edge.
8
VDD
I
Positive Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
9
VREF
I
DAC Reference Voltage Input
10
RFB
O
DAC Feedback Resistor pin. Establish voltage output for the DAC by connecting to external amplifier
output.
6
7
SYNC
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD to GND
–0.3
7
V
Digital input voltage to GND
–0.3
VDD + 0.3
V
IOUT1, IOUT2 to GND
–0.3
VDD + 0.3
V
Operating temperature
–40
125
°C
150
°C
150
°C
Junction temperature, (TJ max)
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Supply voltage to GND
2.7
5.5
V
VREF
Reference voltage
–15
15
V
0.6
V
0.8
V
VIL
VDD = 2.7 V
Input low voltage
VDD = 5 V
VDD = 2.7 V
2.1
VDD = 5 V
2.4
VIH
Input high voltage
TA
Operating ambient temperature
V
V
–40
125
°C
6.4 Thermal Information
DAC7811
THERMAL METRIC
(1)
DGS (VSSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
165.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.4
°C/W
RθJB
Junction-to-board thermal resistance
85.6
°C/W
ψJT
Junction-to-top characterization parameter
6.2
°C/W
ψJB
Junction-to-board characterization parameter
84.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBAS337E – APRIL 2005 – REVISED MARCH 2018
6.5 Electrical Characteristics
VDD = 2.7 V to 5.5 V; IOUT1 = Virtual GND; IOUT2 = 0V; VREF = 10 V; TA = full operating temperature. All specifications –40°C to
125°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±1
LSB
±1
LSB
±5
nA
STATIC PERFORMANCE
Resolution
12
Bits
Relative accuracy
Differential nonlinearity
Output leakage current
Data = 0000h, TA = 25°C
Output leakage current
Data = 0000h, TA = TMAX
Full-scale gain error
All ones loaded to DAC register
±5
Full-scale tempco (1)
Output capacitance
(1)
Code dependent
±25
nA
±10
mV
±5
ppm/°C
5
pF
REFERENCE INPUT
Input resistance
8
10
12
kΩ
RFB resistance
8
10
12
kΩ
LOGIC INPUTS AND OUTPUT (1)
IIL
Input leakage current
10
µA
CIL
Input capacitance
10
pF
50
MHz
INTERFACE TIMING (see Figure 28)
fCLK
tC
Clock period
20
ns
tCH
tCC
Clock pulse width high
8
ns
Clock pulse width low
8
ns
tCSS
SYNC falling edge to SCLK
active edge setup time
13
ns
tCST
SCLK active edge to SYNC
rising edge hold time
5
ns
tDS
Data setup time
5
ns
tDH
Data hold time
3
ns
tSH
SYNC high time
tDDS
SYNC inactive edge to SDO
valid
30
ns
VDD = 2.7 V
25
35
ns
VDD = 5 V
20
30
ns
POWER REQUIREMENTS
IDD (normal operation)
Logic inputs = 0 V
5
µA
VDD = 4.5 V to 5.5 V
VIH = VDD and VIL = GND
0.8
5
µA
VDD = 2.7 V to 3.6 V
VIH = VDD and VIL = GND
0.4
2.5
µA
0.2
µs
AC CHARACTERISTICS (1)
Output voltage settling time
Reference multiplying BW
VREF = 7 VPP, Data = FFFh
10
MHz
DAC glitch impulse
VREF = 0 V to 10 V,
Data = 7FFh to 800h to 7FFh
5
nV-s
Feedthrough error VOUT/VREF
Data = 000h, VREF = 100 kHz
–60
Digital feedthrough
2
Total harmonic distortion
–105
Output spot noise voltage
(1)
18
dB
nV-s
dB
nV/√Hz
Specified by design and characterization; not production tested.
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6.6 Typical Characteristics: VDD = 5 V
At TA = 25°C, unless otherwise noted.
1.0
1.0
0.8
TA = +25°C
0.6
VREF = +10V
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1.0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 1. Linearity Error vs Digital Input Code
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 2. Differential Linearity Error vs Digital Input Code
1.0
1.0
0.8
TA = -40°C
0.8
TA = -40°C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
INL (LSB)
0.2
-0.6
0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 3. Linearity Error vs Digital Input Code
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 4. Differential Linearity Error vs Digital Input Code
1.0
1.0
0.8
TA = +125°C
0.8
TA = +125°C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
INL (LSB)
0.6
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 5. Linearity Error vs Digital Input Code
6
TA = +25°C
VREF = +10V
0.4
DNL (LSB)
INL (LSB)
0.4
0.8
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 6. Differential Linearity Error vs Digital Input Code
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Typical Characteristics: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted.
0.9
6
0
-6
-12
-18
-24
-30
-36
-42
-48
-56
-60
-66
-72
-78
-84
-90
-96
-102
VDD = +5.0V
Attenuation (dB)
0.7
0xFFF
0x800
0x400
0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
0.6
0.5
0.4
0.3
0.2
VDD = +3.0V
0.1
0
0
1.0
2.0
3.0
4.0
5.0
Digital Code
Supply Current (mA)
0.8
0x000
10
100
10k
1k
100k
1M
10M
100M
Bandwidth (Hz)
Logic Input Voltage (V)
Figure 7. Supply Current vs Logic Input Voltage
Output Voltage (50mV/div)
Output Voltage (50mV/div)
Figure 8. Reference Multiplying Bandwidth
Code 2047 to 2048
DAC Update
Code 2048 to 2047
DAC Update
Time (50ns/div)
Time (50ns/div)
Figure 9. Midscale DAC Glitch
Figure 10. Midscale DAC Glitch
0
VREF = +10V
-0.2
Small Signal Settling
Gain Error (mV)
Output Voltage (%)
90
10
-0.4
DAC Update
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
Time (20ns/div)
-2.0
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 11. DAC Settling Time
Figure 12. Gain Error vs Temperature
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Typical Characteristics: VDD = 5 V (continued)
At TA = 25°C, unless otherwise noted.
2.0
VREF = +10V
1.4
1.6
Output Leakage (nA)
Quiescent Current (mA)
1.6
VREF = +10V
1.8
1.4
1.2
1.0
VDD = +5.0V
0.8
0.6
VDD = +3.0V
0.4
1.2
1.0
0.8
0.6
0.4
0.2
0.2
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
Temperature (°C)
20
40
60
80
100
120
Temperature (°C)
Figure 13. Supply Current vs Temperature
8
0
Figure 14. Output Leakage vs Temperature
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6.7 Typical Characteristics: VDD = 2.7 V
At TA = 25°C, unless otherwise noted.
1.0
1.0
0.8
TA = +25°C
0.8
TA = +25°C
0.6
RREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
INL (LSB)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 15. Linearity Error vs Digital Input Code
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 16. Differential Linearity Error vs Digital Input Code
1.0
1.0
0.8
TA = -40°C
0.6
VREF = +10V
0.8
TA = -40°C
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
INL (LSB)
0
-0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 17. Linearity Error vs Digital Input Code
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 18. Differential Linearity Error vs Digital Input Code
1.0
1.0
0.8
TA = +125°C
0.8
TA = +125°C
0.6
VREF = +10V
0.6
VREF = +10V
0.4
DNL (LSB)
0.4
INL (LSB)
0.2
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 19. Linearity Error vs Digital Input Code
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 20. Differential Linearity Error vs Digital Input Code
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Typical Characteristics: VDD = 2.7 V (continued)
Output Voltage (50mV/div)
Output Voltage (50mV/div)
At TA = 25°C, unless otherwise noted.
Code 2048 to 2047
Code 2047 to 2048
DAC Update
DAC Update
Time (50ns/div)
Time (50ns/div)
Figure 21. Midscale DAC Glitch
0
Figure 22. Midscale DAC Glitch
1.6
VREF = +10V
-0.2
Output Leakage (nA)
-0.4
Gain Error (mV)
VREF = +10V
1.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
1.2
1.0
0.8
0.6
0.4
0.2
-1.8
0
-2.0
-40
-20
0
20
40
60
80
100
120
-40
-20
Figure 23. Gain Error vs Temperature
10
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 24. Output Leakage vs Temperature
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7 Detailed Description
7.1 Overview
The DAC7811 is a CMOS, 12-bit, current output digital-to-analog converter (DAC). This device operates from a
2.7-V to 5.5-V power supply, making it suitable for battery-powered and many other applications. This DAC uses
a double-buffered 3-wire serial interface that is compatible with SPI, QSPI™, MICROWIRE, and most DSP
interface standards. In addition, a serial data out pin (SDO) allows for daisy-chaining when multiple devices are
used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the
internal shift register and latches are filled with zeroes and the DAC outputs are at zero scale.
7.2 Functional Block Diagram
VDD
VREF
R
DAC7811
RFB
IOUT 1
12-Bit
R-2R DAC
IOUT 2
DAC Register
Power-On
Reset
Input Latch
SYNC
SCLK
SDIN
Control Logic and
Input Shift Register
SDO
GND
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7.3 Feature Description
The DAC7811 is a single channel, current output, 12-bit digital-to-analog converter (DAC). The architecture,
illustrated in Figure 25, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to IOUT1 or the IOUT2 terminal. The IOUT1 terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input VREF that determines the DAC full-scale current. The R-2R ladder presents a code independent load
impedance to the external reference of 10kΩ ±20%. The external reference voltage can vary over a range of
–15V to +15V, thus providing bipolar IOUT current operation. By using an external I/V converter and the DAC7811
RFB resistor, output voltage ranges of –VREF to VREF can be generated.
R
R
R
R
VREF
2R
2R
2R
2R
R
RFB
IOUT1
IOUT2
DB11
(MSB)
DB10
DB9
DB0
(LSB)
Figure 25. Equivalent R-2R DAC Circuit
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Feature Description (continued)
When using an external I/V converter and the DAC7811 RFB resistor, the DAC output voltage is given by
Equation 1:
VOUT
§ CODE ·
VREF u ¨
¸
© 4096 ¹
(1)
Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output
impedance as seen looking into the IOUT1 terminal changes versus code, the external I/V converter noise gain
will also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage
such that the amplifier offset is not modulated by the DAC IOUT1 terminal impedance change. External op amps
with large offset voltages can produce INL errors in the transfer function of the DAC7811 due to offset
modulation versus DAC code.
For best linearity performance of the DAC7811, a low offset voltage op amp (such as the OPA277) is
recommended (see Figure 26). This circuit allows VREF swinging from –10 V to 10 V.
V DD
15V
V DD
R FB
DAC7811
V REF
GND
V+
I OUT 1
I OUT 2
V OUT
OPA277
V
15V
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Voltage Output Configuration
7.4 Device Functional Modes
7.4.1 Serial Interface
The DAC7811 has a 3-wire serial interface (SYNC, SCLK, and SDIN), which is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most Digital Signal Processor (DSP) devices. See the Serial Write
Operation timing diagram (Figure 28) for an example of a typical write sequence. The write sequence begins by
bringing the SYNC line low. Data from the DIN line are clocked into the 16-bit shift register on the falling edge of
SCLK. The serial clock frequency can be as high as 50MHz, making the DAC7811 compatible with high-speed
DSPs. The SDIN and SCLK input buffers are gated off while SYNC is high which minimizes the power
dissipation of the digital interface. After SYNC goes low, the digital interface will respond to the SDIN and SCLK
input signals and data can now be shifted into the device. If an inactive clock edge occurs after SYNC goes low,
but before the first active clock edge, it will be ignored. If the SDO pin is being used then SYNC must remain low
until after the inactive clock edge that follows the 16th active clock edge.
7.4.2 Input Shift Register
The input shift register is 16 bits wide, as shown in Figure 27. The four MSBs are the control bits C3–C0; these
bits determine which function will be executed at the rising edge of SYNC in daisy-chain mode or the 16th active
clock edge in stand-alone mode. The remaining 12 bits are the data bits. On a load and update command
(C3–C0 = 0001) these 12 data bits will be transferred to the DAC register; otherwise, they have no effect.
Table 1 shows serial shift register and DAC register operation with CLK and SYNC pin settings.
12
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Device Functional Modes (continued)
4 CONTROL BITS
B15
(MSB)
C3
B14
C2
B13
C1
12 DATA BITS
B12
C0
B11
DB11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
(LSB)
DB0
Figure 27. Contents of the 16-Bit Input Shift Register
Table 1. Control Logic Truth Table (1)
CLK
SYNC
X
H
No effect
Latched
↓–
L
Shift register data advanced one bit
Latched
↑+
In daisy-chain mode, the function as determined by C3C0 is executed.
In daisy-chain mode, the contents may change as
determined by C3-C0.
X
(1)
SERIAL SHIFT REGISTER
DAC REGISTER
↓– Negative logic transition, default CLK mode;↑+ Positive logic transition; X = Do not care.
7.4.3 SYNC Interrupt (Stand-Alone Mode)
In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is
updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an
interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an
update of the DAC register contents nor a change in the operating mode occurs.
7.4.4 Daisy-Chain
The DAC7811 powers up in the daisy-chain mode which must be used when two or more devices are connected
in tandem. The SCLK and SYNC signals are shared across all devices while the SDO output of the first device
connects to the SDIN input of the following device, and so forth. In this configuration 16 SCLK cycles for each
DAC7811 in the chain are required. Please refer to the timing diagram of Figure 28.
For n devices in a daisy-chain configuration, 16n SCLK cycles are required to shift in the entire input data
stream. After 16n active SCLK edges are received following a falling SYNC, the data stream becomes complete,
and SYNC can brought high to update n devices simultaneously.
When SYNC is brought high, each device will execute the function defined by the four DAC control bits C3-C0 in
its input shift register. For example, C3-C0 must be 0001 for each DAC in the chain that is to be updated with
new data, and C3-C0 must be 0000 for each DAC in the chain whose contents are to remain unchanged.
A continuous stream containing the exact number of SCLK cycles may be sent first while the SYNC signal is held
low, and then raise SYNC at a later time. Nothing happens until the rising edge of SYNC, and then each
DAC7811 in the chain will execute the function defined by the four DAC control bits C3-C0 in its input shift
register.
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tC
SCLK
tCST
tCC
tCSS
tCH
tSH
SYNC
tDH
tDS
DB15
(N)
SDIN
DB0
(N)
DB15
(N + 1)
DB0
(N + 1)
tDDS
DB15
(N)
SDO
DB0
(N)
Figure 28. DAC7811 Timing Diagram
7.4.5 Control Bits C3 to C0
Control Bits C3 to C0 allow control of various functions of the DAC; see Table 2. Default settings of the DAC on
powering up are as follows: Data clocked into shift register on falling clock edges; daisy-chain mode is enabled.
The device powers on with zero-scale loaded into the DAC register and IOUT lines. The DAC control bits allow the
user to adjust certain features as part of an initialization sequence; for example, daisy-chaining may be disabled
if not in use, active clock edge may be changed to rising edge, and DAC output may be cleared to either zero or
midscale. The user may also initiate a readback of the DAC register contents for verification purposes.
Table 2. Serial Input Register Data Format, Data Loaded MSB First
14
C3
C2
C1
C0
0
0
0
0
No operation (power-on default)
FUNCTION IMPLEMENTED
0
0
0
1
Load and update
0
0
1
0
Initiate readback
0
0
1
1
Reserved
0
1
0
0
Reserved
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
Reserved
1
0
0
1
Daisy-chain disable
1
0
1
0
Clock data to shift register on rising edge
1
0
1
1
Clear DAC output to zero
1
1
0
0
Clear DAC output to midscale
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The 2.7-V to 5.5-V supply operation makes the DAC7811 a viable candidate for battery operated applications,
such as waveform generators, programmable amplifiers, and any mobile platforms that may require analog
outputs and processing. Additionally, the large signal multiplying bandwidth of the DAC7811 makes it an
excellent choice for programmable filters and oscillators.
8.1.1 Unipolar Operation Using DAC7811
To generate a positive voltage output, a negative reference is input to the DAC7811. This design is suggested
instead of using an inverting amp to invert the output as a result of resistor tolerance errors. For a negative
reference, VOUT and GND of the reference are level-shifted to a virtual ground and a –2.5-V input to the
DAC7811 with an op amp.
+2.5V Reference
V OUT
V DD
V IN
GND
V DD
V REF
R FB
DAC7811
OPA277
C1
I OUT 1
- 2.5V
GND
I OUT 2
V OUT
OPA277
0 to 2.5V
Copyright © 2016, Texas Instruments Incorporated
Figure 29. Positive Voltage Output Circuit
8.1.2 Bipolar Operation Using the DAC7811
The DAC7811, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 30,
external op amp U3 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A 4quadrant multiplying circuit is implemented by using a 2.5-V offset of the reference voltage to bias U3. According
to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full-scale produces output
voltages of VOUT = –2.5 V to VOUT = +2.5 V
éæ D ö ù
VOUT = êç 11 ÷ - 1ú ´ VREF
ëè 2 ø û
(2)
External resistance mismatching is the significant error in Figure 30.
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Application Information (continued)
10 NŸ
10 NŸ
C2
VDD
5 NŸ
RFB
VDD
+2.5 V
VREF DAC7811 IOUT1
VOUT
-2.5 V to 2.5 V
U2
OPA277
IOUT2
GND
U3
OPA277
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Bipolar Output Circuit
8.1.3 Stability Circuit
For a current-to-voltage design (see Figure 31), the DAC7811 current output (IOUT) and the connection with the
inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)
layout design practices. For each code change, there is a step function. If the gain bandwidth product (GBP) of
the op amp is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible.
Therefore, for circuit stability, a compensation capacitor C1 (1pF to 5pF typ) can be added to the design, as
shown in Figure 31.
V DD
U1
V DD
V REF
V REF
GND
R FB
C1
I OUT 1
V OUT
I OUT 2
U2
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Gain Peaking Prevention Circuit With Compensation Capacitor
8.1.4 Amplifier Selection
There are many choices and many differences in selecting the proper operational amplifier for a multiplying DAC
(MDAC). Making the analog signal out of the MDAC is one critical aspect. However, there are also other issues
to take into account such as amplifier noise, input bias current, and offset voltage, as well as MDAC resolution
and glitch energy. Table 3 and Table 4 suggest some suitable operational amplifiers for low power, fast settling,
and high-speed applications. A greater selection of operational amplifiers can be found at www.ti.com/amplifier.
16
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Application Information (continued)
Table 3. Suitable Precision Operational Amplifiers from Texas Instruments
IQ
PER
GBW
CHANNEL (typ)
(max)
(MHz)
(mA)
TOTAL
SUPPLY
VOLTAGE
(V) (min)
TOTAL
SUPPLY
VOLTAGE
(V) (max)
SLEW
RATE
(typ)
(V/μs)
OFFSET
DRIFT
(typ)
(μV/°C)
IIB
(max)
(pA)
CMRR
(min)
(dB)
PACKAGE/
LEAD
DESCRIPTION
OPA703
4
12
0.2
1
0.6
4
10
70
SOT5-23,
PDIP-8,
SOIC-8
12V, CMOS, Rail-to-Rail I/O,
Operational Amplifier
OPA735
2.7
12
0.75
1.6
1.5
0.01
200
115
SOT5-23,
SOIC-8
0.05μV/°C (max), SingleSupply CMOS Zero-Drift
Series Operational Amplifier
OPA344
2.7
5.5
0.25
1
1
2.5
10
80
SOT5-23,
PDIP-8,
SOIC-8
Low Power, Single-Supply,
Rail-To-Rail Operational
Amplifiers MicroAmplifier
Series
OPA348
2.1
5.5
0.065
1
0.5
2
10
70
SC5-70,
SOT5-23,
SOIC-8
1MHz, 45μA, Rail-to-Rail I/O,
Single Op Amp
OPA277
4
36
0.825
1
0.8
0.1
1000
130
PDIP-8,
SOIC-8,
SON-8
High Precision Operational
Amplifiers
OPA350
2.7
5.5
7.5
38
22
4
10
76
MSOP-8,
PDIP-8,
SOIC-8
High-Speed, Single-Supply,
Rail-to-Rail Operational
Amplifiers MicroAmplifier
Series
OPA727
4
12
6.5
20
30
0.6
500
86
MSOP-8,
SON-8
e-trim 20MHz, High Precision
CMOS Operational Amplifier
OPA227
5
36
3.8
8
2.3
0.1
10000
120
PDIP-8,
SOIC-8
High Precision, Low Noise
Operational Amplifiers
PRODUCT
LOW POWER
FAST SETTLING
Table 4. Suitable High Speed Operational Amplifiers from Texas Instruments (Multiple Channel Options)
SUPPLY
VOLTAGE
(V)
PRODUCT
GBW
PRODUCT
(MHz)
VOLTAGE
NOISE
nV/√Hz
GBW
(typ)
(MHz)
SLEW
RATE
(V/μs)
VOS
(typ)
(μV)
VOS
(max)
(μV)
CMRR
(min)
(dB)
PACKAGE/
LEAD
DESCRIPTION
SINGLE CHANNEL
THS4281
±2.7 to ±15
38
12.5
35
500
3500
500
1000
SOT5-23,
MSOP-8,
SOIC-8
Very Low-Power High Speed
Rail-To-Rail Input/Output
Voltage Feedback
Operational Amplifier
THS4031
±4.5 to ±16.5
200
1.6
100
500
3000
3000
8000
CDIP-8,
MSOP-8,
SOIC-8
100-MHz Low Noise VoltageFeedback Amplifier
THS4631
±4.5 to ±16.5
210
7
900
260
2000
50pA
2
SOIC-8,
MSOP-8
High Speed FET-Input
Operational Amplifier
OPA656
±4 to ±6
230
7
290
250
2600
2pA
5pA
SOIC-8,
SOT5-23
Wideband, Unity Gain Stable
FET-Input Operational
Amplifier
OPA820
±2.5 to ±6
280
2.5
240
200
1200
900
23,000
SOIC-8,
SOT5-23
Unity Gain Stable, Low Noise,
Voltage Feedback
Operational Amplifier
THS4032
±4.5 to ±16.5
200
1.6
100
500
3000
3000
8000
SOIC-8,
MSOP-8
100-MHz Low Noise VoltageFeedback Amplifier, Dual
OPA2822
±2 to ±6.3
220
2
170
200
1200
9600
12000
SOIC-8,
MSOP-8
SpeedPlus Dual Wideband,
Low-Noise Operational
Amplifier
DUAL CHANNEL
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8.1.5 Programmable Current Source Circuit
A DAC7811 can be integrated into the circuit in Figure 32 to implement an improved Howland current pump for
precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of
the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 3:
IL
(R2 R3) / R1
D
u VREF u
R3
4096
(3)
The value of R3 in Equation 3 can be reduced to increase the output current drive of U3. U3 can drive ±20mA in
both directions with voltage compliance limited up to 15V by the U3 voltage supply. Elimination of the circuit
compensation capacitor C1 in the circuit is not suggested as a result of the change in the output impedance ZO,
according to Equation 4:
ZO
R1'R3(R1 R2)
R1(R2' R3') R1'(R2 R3)
(4)
As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems
are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a
value of several pF is suggested.
R2c
15k:
C1
10pF
R1c
150k:
VDD
VDD
VREF
R3c
50:
U3
OPA277
RFB
U1
IOUT1
DAC7811
I
OUT2
GND
U2
OPA277
R1
150k:
R2
15k:
VOUT
R3
50:
IL
LOAD
Copyright © 2016, Texas Instruments Incorporated
Figure 32. Programmable Bidirectional Current Source Circuit
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8.2 Typical Application
8.2.1 Single Supply Unipolar Multiplying DAC
5.5 V
5.5 V
VIN
REF5050 VOUT
5.5 V
REFIN AVDD
RFB
5.5 V
VREF
+
IOUT1
DAC7811
OPA376
IOUT2
+
VOUT (0 to 2.5 V)
OPA376
5.5 V
10 NŸ
VBIAS
+
OPA376
10 NŸ
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Complete Circuit Schematic
8.2.1.1 Design Requirements
This multiplying DAC (MDAC) circuit outputs unipolar voltages from 0 V to 2.5 V. This design does not require
dual supplies to realize a unipolar, positive output voltage. This design removes the need for a negative supply
rail by applying a bias voltage the output transimpedance stage.
8.2.1.2 Detailed Design Procedure
The DAC7811 output current is converted into a voltage by including an op-amp in a transimpedance
configuration at the DAC7811 current output terminal. The transimpedance stage creates an output voltage with
opposite polarity to that of VREF and subsequently requires dual supplies. This circuit removes the need of dual
power supplies and uses a single supply to power the circuit.
The transfer function from digital code to output voltage is shown in Equation 5.
VOUT (Code) = VBIAS -
(VREF - VBIAS ) ´ Code
2bits
(5)
More information regarding this design can be found in Single-Supply Unipolar Multiplying DAC Reference
Design (TIDU300).
8.2.1.3 Application Curve
The Absolute error (TUE) in %FSR is shown the following graph, Figure 34. The plot below represents data
ranging from code 30 to 4050. The figure shows the absolute error (TUE) has a maximum value of about 0.05%
FSR.
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Typical Application (continued)
0.10
0.08
0.06
Error (%FSR)
0.04
0.02
0.00
±0.02
±0.04
board1
board4
board7
board10
±0.06
±0.08
±0.10
30
530
1030
board2
board5
board8
1530
2030
2530
board3
board6
board9
3030
3530
Code
4030
C001
Figure 34. Absolute Error (TUE) in %FSR
9 Power Supply Recommendations
The DAC7811 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to VDD
should be well regulated and low noise. Switching power supplies and DC-DC converters often have high
frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar highfrequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. To further minimize noise from the power supply, a strong
recommendation is to include a 1-µF to 10-µF capacitor and 0.1-µF bypass capacitor. The required supply
current vs Logic Input voltage or temperature is displayed in Typical Characteristics. The power supply must
meet the aforementioned current requirements.
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10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, the list below provides some insight into good layout
practices.
• All Power Supply pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical
recommended bypass capacitance is 0.1 to 0.22-µF ceramic with a X7R or NP0 dielectric.
• Power supplies and VREF bypass capacitors should be placed close to terminals or planes to minimize
inductance and optimize performance.
• A high-quality ceramic type NP0 or X7R is recommended for its optimal performance across temperature, and
very low dissipation factor.
• The digital and analog sections should have proper placement with respect to the digital pins and analog pins
of the DAC9881 device. The separation of analog and digital blocks will allow for better design and practice
as it will ensure less coupling into neighboring blocks, and will minimize the interaction between analog and
digital return currents.
10.2 Layout Example
VREF
Bypass Capacitor
VDD
Bypass Capacitors
1
2
3
4
5
GND
10
9
8
7
6
VREF
DAC7811
ANALOG SIDE
DIGITAL SIDE
DIGITAL
Figure 35. DAC7811 Example Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• TI Designs – Precision: Verified Design Voltage Mode Multiplying DAC Reference Design (TIDUAF0)
• TI Designs – Precision: Verified Design Single Supply Unipolar Multiplying DAC Reference Design (TIDU300)
• Interfacing the DAC7811 to the MSP430F449 (SLAA372)
• DAC7811EVM (SLAU163)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
QSPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
DAC7811IDGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
Samples
DAC7811IDGSG4
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
Samples
DAC7811IDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
Samples
DAC7811IDGSRG4
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
Samples
DAC7811IDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
7811
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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