DS42BR400-EVK

DS42BR400 www.ti.com SNLS221J – MARCH 2006 – REVISED APRIL 2013 DS42BR400 Quad 4.25 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization Check for Samples: DS42BR400 FEATURES DESCRIPTION • The DS42BR400 is a quad 250 Mbps – 4.25 Gbps CML transceiver, or 8-channel buffer, for use in backplane and cable applications. With operation down to 250 Mbps, the DS42BR400 can be used in applications requiring both low and high frequency data rates. Each input stage has a fixed equalizer to reduce ISI distortion from board traces. The equalizers are grouped in fours and are enabled through two control pins. These control pins provide customers flexibility where ISI distortion may vary from one direction to another. 1 2 • • • • • • • 250 Mbps – 4.25 Gbps Fully Differential Data Paths Optional Fixed Input Equalization Selectable Output De-emphasis Individual Loopback Controls On-Chip Termination Lead-less WQFN-60 Pin Package (9 mm x 9 mm x 0.8 mm, 0.5 mm Pitch) −40°C to +85°C Industrial Temperature Range 6 kV ESD Rating, HBM APPLICATIONS • • Backplane Driver or Cable Driver Signal Repeating, Buffering and Conditioning Applications All output drivers have four selectable steps of deemphasis to compensate against transmission loss across long FR4 backplanes. The de-emphasis blocks are also grouped in fours. In addition, the DS42BR400 also has loopback control capability on four channels. All CML drivers have 50Ω termination to VCC. All receivers are internally terminated with differential 100Ω. OA0 OA1 OA2 OA3 OB0 OB1 OB2 OB3 IB0 IB1 IB2 IB3 PreA_0 PreA_1 PreB_0 PreB_1 Connector FPGA IA0 IA1 IA2 IA3 Connector Simplified Application Diagram IA0 IA1 IA2 IA3 OA0 OA1 OA2 OA3 OB0 OB1 OB2 OB3 IB0 IB1 IB2 IB3 PreA_0 PreA_1 PreB_0 PreB_1 Lossy Backplane or Cable Interconnect EQA EQB FPGA EQA EQB 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated DS42BR400 SNLS221J – MARCH 2006 – REVISED APRIL 2013 www.ti.com Functional Block Diagram EQB Port 0/1 OB_0+- EQB IB_0+- EQB IB_1+- PreB OB_1+PreB EQB LB0 EQA OA_0+IA_0+- EQA PreA OA_1+- IA_1+- EQA PreA LB1 EQA EQB Port 2/3 OB_2+- EQB IB_2+- EQB IB_3+- PreB OB_3+PreB EQB LB2 EQA OA_2+IA_2+- EQA PreA OA_3+- IA_3+- EQA PreA LB3 EQA PreA PreB EQA EQB VDD PreA_0 PreA_1 PreB_0 Pre-Emphasis Control Equalizer Enable Control RSV PreB_1 EQA 2 GND EQB Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 DS42BR400 www.ti.com SNLS221J – MARCH 2006 – REVISED APRIL 2013 EQA RSV IA_0+ IA_0- VCC OB_0+ OB_0- GND IB_0- IB_0+ VCC OA_0- OA_0+ GND LB0 Connection Diagram 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 PreA_1 1 45 PreB_1 GND 2 44 LB1 OB_1+ 3 43 IB_1+ OB_1- 4 42 IB_1- VCC 5 41 VCC IA_1+ 6 40 OA_1+ IA_1- 7 39 OA_1- 38 GND 37 OA_2- GND 60 Pin WQFN 8 Top View IA_2- 9 DAP = GND IB_2+ GND 14 32 LB2 PreA_0 15 31 PreB_0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LB3 33 GND 13 OA_3+ OB_2+ OA_3- IB_2- VCC 34 IB_3+ 12 IB_3- OB_2- GND VCC OB_3- 35 OB_3+ 11 VCC VCC IA_3- OA_2+ IA_3+ 36 GND 10 EQB IA_2+ Figure 1. Leadless WQFN-60 Pin Package (9 mm x 9 mm x 0.8 mm, 0.5 mm pitch) See Package Number NKA0060A Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 3 DS42BR400 SNLS221J – MARCH 2006 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS Pin Name Pin Number I/O (1) Description DIFFERENTIAL I/O IB_0+ IB_0− 51 52 I Inverting and non-inverting differential inputs of port_0. IB_0+ and IB_0− are internally connected to a reference voltage through a 50Ω resistor. Refer to Figure 8. OA_0+ OA_0− 48 49 O Inverting and non-inverting differential outputs of port_0. OA_0+ and OA_0− are connected to VCC through a 50Ω resistor. IB_1+ IB_1− 43 42 I Inverting and non-inverting differential inputs of port_1. IB_1+ and IB_1− are internally connected to a reference voltage through a 50Ω resistor. Refer to Figure 8. OA_1+ OA_1− 40 39 O Inverting and non-inverting differential outputs of port_1. OA_1+ and OA_1− are connected to VCC through a 50Ω resistor. IB_2+ IB_2− 33 34 I Inverting and non-inverting differential inputs of port_2. IB_2+ and IB_2− are internally connected to a reference voltage through a 50Ω resistor. Refer to Figure 8. OA_2+ OA_2− 36 37 O Inverting and non-inverting differential outputs of port_2. OA_2+ and OA_2− are connected to VCC through a 50Ω resistor. IB_3+ IB_3− 25 24 I Inverting and non-inverting differential inputs of port_3. IB_3+ and IB_3− are internally connected to a reference voltage through a 50Ω resistor. Refer to Figure 8. OA_3+ OA_3− 28 27 O Inverting and non-inverting differential outputs of port_3. OA_3+ and OA_3− are connected to VCC through a 50Ω resistor. IA_0+ IA_0− 58 57 I Inverting and non-inverting differential inputs of port_0. IA_0+ and IA_0− are internally connected to a reference voltage through a 50Ω resistor. Refer to Figure 8. OB_0+ OB_0− 55 54 O Inverting and non-inverting differential outputs of port_0. OB_0+ and OB_0− are connected to VCC through a 50Ω resistor. IA_1+ IA_1− 6 7 I Inverting and non-inverting differential inputs of port_1. IA_1+ and IA_1− are internally connected to a reference voltage through a 50Ω resistor. Refer to Figure 8. OB_1+ OB_1− 3 4 O Inverting and non-inverting differential outputs of port_1. OB_1+ and OB_1− are connected to VCC through a 50Ω resistor. IA_2+ IA_2− 10 9 I Inverting and non-inverting differential inputs of port_2. IA_2+ and IA_2− are internally connected to a reference voltage through a 50Ω resistor. Refer to Figure 8. OB_2+ OB_2− 13 12 O Inverting and non-inverting differential outputs of port_2. OB_2+ and OB_2− are connected to VCC through a 50Ω resistor. IA_3+ IA_3− 18 19 I Inverting and non-inverting differential inputs of port_3. IA_3+ and IA_3− are internally connected to a reference voltage through a 50Ω resistor. Refer to Figure 8. OB_3+ OB_3− 21 22 O Inverting and non-inverting differential outputs of port_3. OB_3+ and OB_3− are connected to VCC through a 50Ω resistor. CONTROL (3.3V LVCMOS) EQA 60 I This pin is active LOW. A logic LOW at EQA enables equalization for input channels IA_0±, IA_1±, IA_2±, and IA_3±. By default, this pin is internally pulled high and equalization is disabled. EQB 16 I This pin is active LOW. A logic LOW at EQB enables equalization for input channels IB_0±, IB_1±, IB_2±, and IB_3±. By default, this pin is internally pulled high and equalization is disabled. PreA_0 PreA_1 15 1 I PreA_0 and PreA_1 select the output de-emphasis levels (OA_0±, OA_1±, OA_2±, and OA_3±). PreA_0 and PreA_1 are internally pulled high. Please see Table 2 for de-emphasis levels. PreB_0 PreB_1 31 45 I PreB_0 and PreB_1 select the output de-emphasis levels (OB_0±, OB_1±, OB_2±, and OB_3±). PreB_0 and PreB_1 are internally pulled high. Please see Table 2 for de-emphasis levels. LB0 46 I This pin is active LOW. A logic LOW at LB0 enables the internal loopback path from IB_0± to OA_0±. LB0 is internally pulled high. Please see Table 1 for more information. LB1 44 I This pin is active LOW. A logic LOW at LB1 enables the internal loopback path from IB_1± to OA_1±. LB1 is internally pulled high. Please see Table 1 for more information. LB2 32 I This pin is active LOW. A logic LOW at LB2 enables the internal loopback path from IB_2± to OA_2±. LB2 is internally pulled high. Please see Table 1 for more information. LB3 30 I This pin is active LOW. A logic LOW at LB3 enables the internal loopback path from IB_3± to OA_3±. LB3 is internally pulled high. Please see Table 1 for more information. RSV 59 I Reserve pin to support factory testing. This pin can be left open, tied to GND, or tied to GND through an external pull-down resistor. (1) 4 Note: I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 DS42BR400 www.ti.com SNLS221J – MARCH 2006 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin Name (1) Pin Number I/O Description VCC 5, 11, 20, 26, 35, 41, 50, 56 P VCC = 3.3V ± 5%. Each VCC pin should be connected to the VCC plane through a low inductance path, typically with a via located as close as possible to the landing pad of the VCC pin. It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin to ground plane. GND 2, 8, 14, 17, 23, 29, 38, 47, 53 P Ground reference. Each ground pin should be connected to the ground plane through a low inductance path, typically with a via located as close as possible to the landing pad of the GND pin. GND DAP P DAP is the metal contact at the bottom side, located at the center of the WQFN-60 pin package. It should be connected to the GND plane with at least 4 via to lower the ground impedance and improve the thermal performance of the package. POWER Functional Description Table 1. Logic Table for Loopback Controls LB0 Loopback Function 0 Enable loopback from IB_0± to OA_0±. 1 (default) Normal mode. Loopback disabled. LB1 Loopback Function 0 Enable loopback from IB_1± to OA_1±. 1 (default) Normal mode. Loopback disabled. LB2 Loopback Function 0 Enable loopback from IB_2± to OA_2±. 1 (default) Normal mode. Loopback disabled. LB3 Loopback Function 0 Enable loopback from IB_3± to OA_3±. 1 (default) Normal mode. Loopback disabled. Table 2. De-Emphasis Controls Default VOD Level in mVPP (VODB) De-Emphasis Level in mVPP (VODPE) 00 1200 1200 0 01 1200 850 −3 10 1200 600 −6 1 1 (Default) 1200 426 −9 Default VOD Level in mVPP (VODB) De-Emphasis Level in mVPP (VODPE) De-Emphasis in dB (VODPE/VODB) 00 1200 1200 0 01 1200 850 −3 10 1200 600 −6 1 1 (Default) 1200 426 −9 PreA_[1:0] PreB_[1:0] De-Emphasis in dB (VODPE/VODB) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 5 DS42BR400 SNLS221J – MARCH 2006 – REVISED APRIL 2013 www.ti.com De-emphasis is the primary signal conditioning function for use in compensating against backplane transmission loss. The DS42BR400 provides four steps of de-emphasis ranging from 0, −3, −6 and −9 dB, user-selectable dependent on the loss profile of the backplane. Figure 2 shows a driver de-emphasis waveform. The deemphasis duration is nominal 200 ps, corresponding to 85% bit-width at 4.25 Gbps. The high speed inputs are self-biased to about 1.3V and are designed for AC coupling allowing the DS42BR400 to be directly inserted into the datapath without any limitation. The ideal AC coupling capacitor value is often based on the lowest frequency component embedded within the serial link. A typical AC coupling capacitor value rages between 100 and 1000nF, some specifications with scrambled data may require a larger coupling capacitor for optimal performance. To reduce unwanted parasitics around and within the AC coupling capacitor, a body size of 0402 is recommended. Figure 7 shows the AC coupling capacitor placement in an AC test circuit. Input Equalization Each differential input of the DS42BR400 has a fixed equalizer front-end stage. It is designed to provide fixed equalization for short board traces with transmission losses of approximately 5 dB between 375 MHz to 1.875 GHz. Programmable de-emphasis together with input equalization ensures an acceptable eye opening for a 40inch FR-4 backplane. The differential input equalizer for inputs on Channel A and inputs on Channel B can be bypassed by using EQA and EQB, respectively. By default, the equalizers are internally pulled high and disabled. Therefore, EQA and EQB must be asserted LOW to enable equalization. 1-bit 1 to N bits 1-bit 1 to N bits 0 dB -3 dB -6 dB VODB -9 dB VODPE3 0V VODPE2 VODPE1 Figure 2. Driver De-Emphasis Differential Waveform (showing all 4 de-emphasis steps) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 DS42BR400 www.ti.com SNLS221J – MARCH 2006 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −0.3V to 4V Supply Voltage (VCC) CMOS/TTL Input Voltage −0.3V to (VCC +0.3V) CML Input/Output Voltage −0.3V to (VCC +0.3V) Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature Soldering, 4 sec +260°C Thermal Resistance, θJA 22.3°C/W Thermal Resistance, θJC 3.2°C/W Thermal Resistance, ΦJB 10.3°C/W ESD Ratings (3) HBM 6kV CDM 1kV MM (1) (2) (3) 350V “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. Operation of the device beyond the maximum Operating Ratings is not recommended. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. ESD tests conform to the following standards:Human Body Model (HBM) applicable standard: MIL-STD-883, Method 3015.7Machine Model (MM) applicable standard: JESD22-A115-A (ESD MM std. of JEDEC)Field -Induced Charge Device Model (CDM) applicable standard: JESD22-C101-C (ESD FICDM std. of JEDEC) Recommended Operating Ratings Supply Voltage (VCC-GND) Supply Noise Amplitude Min Typ Max 3.135 3.3 3.465 V 100 mVPP +85 °C 100 °C 10 Hz to 2 GHz −40 Ambient Temperature Case Temperature Units Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 7 DS42BR400 SNLS221J – MARCH 2006 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (1) (2) Over recommended operating supply and temperature ranges unless otherwise specified. Parameter Test Conditions Min Typ (3) Max Units LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC +0.3 V VIL Low Level Input Voltage −0.3 0.8 V IIH High Level Input Current −10 10 µA IIL Low Level Input Current VIN = GND RPU Pull-High Resistance VIN = VCC 75 94 124 35 µA kΩ RECEIVER SPECIFICATIONS VID Differential Input Voltage Range AC Coupled Differential Signal. Below 1.25 Gb/s At 1.25 Gbps–3.125 Gbps Above 3.125 Gbps This parameter is not production tested. VICM Common Mode Voltage Measured at receiver inputs reference to ground. at Receiver Inputs RITD Input Differential Termination 100 100 100 1750 1560 1200 1.3 mVP-P mVP-P mVP-P V On-chip differential termination between IN+ or IN−.SeeFigure 8 84 100 116 Ω Output Differential Voltage Swing without De-Emphasis RL = 100Ω ±1% PreA_1 = 0; PreA_0 = 0 PreB_1 = 0; PreB_0 = 0 Driver de-emphasis disabled. Running K28.7 pattern at 4 Gbps. See(Figure 7) 1000 1200 1400 mVP-P Output De-Emphasis Voltage Ratio 20*log(VODPE/VODB) RL = 100Ω ±1% Running K28.7 pattern at 4.25 Gbps PreX_[1:0] = 00 PreX_[1:0] = 01 PreX_[1:0] = 10 PreX_[1:0] = 11 X = A/B channel de-emphasis drivers See(Figure 2/ Figure 7) De-Emphasis Width Tested at −9 dB de-emphasis level, PreX[1:0] = 11 X = A/B channel de-emphasis drivers See Figure 6 on measurement condition. 125 200 250 ps 42 50 58 Ω DRIVER SPECIFICATIONS VODB VPE tPE ROTSE Output Termination On-chip termination from OUT+ or OUT− to VCC ROTD Output Differential Termination On-chip differential termination between OUT+ and OUT− ΔROTSE Mis-Match in Output Termination Resistors Mis-match in output termination resistors VOCM Output Common Mode Voltage 0 −3 −6 −9 dB dB dB dB Ω 100 5 2.7 % V POWER DISSIPATION PD (1) (2) (3) 8 Power Dissipation VDD = 3.465V All outputs terminated by 100Ω ±1%. PreB_[1:0] = 0, PreA_[1:0] = 0 Running PRBS 27-1 pattern at 4.25 Gbps 1.3 W IN+ and IN− are generic names that refer to one of the many pairs of complementary inputs of the DS42BR400. OUT+ and OUT− are generic names that refer to one of the many pairs of the complementary outputs of the DS42BR400. Differential input voltage VID is defined as |IN+ – IN−|. Differential output voltage VOD is defined as |OUT+ – OUT−|. K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000}K28.5 pattern is a 20-bit repeating pattern of +K28.5 and −K28.5 code groups {110000 0101 001111 1010} Typical specifications are at TA=25 C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 DS42BR400 www.ti.com SNLS221J – MARCH 2006 – REVISED APRIL 2013 Electrical Characteristics(1)(2) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Parameter Test Conditions Min Typ (3) Max Units AC CHARACTERISTICS tR Differential Low to High Transition Time tF Differential High to Low Transition Time Measured with a clock-like pattern at 4.25 Gbps, between 20% and 80% of the differential output voltage. De-emphasis disabled. Transition time is measured with the fixture shown in Figure 7 adjusted to reflect the transition time at the output pins. tPLH Differential Low to High Propagation Delay Measured at 50% differential voltage from input to output. tPHL Differential High to Low Propagation Delay tSKP Pulse Skew tSKO Output Skew (4) tSKPP tLB Part-to-Part Skew (4) Loopback Delay Time 80 ps 80 ps 1 ns 1 ns |tPHL–tPLH| 20 ps Difference in propagation delay between channels on the same part (Channel-to-Channel Skew) (4) 100 ps Difference in propagation delay between devices across all channels operating under identical conditions 165 ps 4 ns Delay from enabling loopback mode to signals appearing at the differential outputs SeeFigure 5 RJ Device Random Jitter (5) At 0.25 Gbps At 1.5 Gbps At 4.25 Gbps Alternating-10 pattern. De-emphasis disabled. See(Figure 7) 2 2 2 ps rms ps rms ps rms DJ Device Deterministic Jitter (6) At 0.25 Mbps, PRBS7 pattern At 1.5 Gbps, K28.5 pattern At 4.25 Gbps, K28.5 pattern At 4.25 Gbps, PRBS7 pattern De-emphasis disabled. See(Figure 7) 25 25 25 25 ps ps ps ps DR Data Rate (7) Alternating-10 pattern (4) (5) (6) (7) 0.25 4.25 pp pp pp pp Gbps tSKO is the magnitude difference in propagation delays between all data paths on one device. This is channel-to-channel skew. tSKPP is the worst case difference in propagation delay across multiple devices on all channels and operating under identical conditions. For example, for two devices operating under the same conditions, tSKPP is the magnitude difference between the shortest propagation delay measurement on one device to the longest propagation delay measurement on another device. Device output random jitter is a measurement of random jitter contributed by the device. It is derived by the equation SQRT[(RJOUT)2 – (RJIN)2], where RJOUT is the total random jitter measured at the output of the device in ps(rms), RJIN is the random jitter of the pattern generator driving the device. Below 400 Mbps, system jitter and device jitter could not be separated. The 250 Mbps specification includes system random jitter. Please see Figure 7 for the AC test circuit. Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJOUT - DJIN), where DJOUT is the total peak-to-peak deterministic jitter measured at the output of the device in ps(p-p). DJIN is the peak-to-peak deterministic jitter at the input of the test board. Please see Figure 7 for the AC test circuit. This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 9 DS42BR400 SNLS221J – MARCH 2006 – REVISED APRIL 2013 www.ti.com TIMING DIAGRAMS 80% 80% VODB 0V 20% 20% tR tF Figure 3. Driver Output Transition Time 50% VID IN tPLH tPHL 50% VOD OUT Figure 4. Propagation Delay Loopback Enable 50% tLB 50% Data Output Data Input Figure 5. Loopback Delay Timing 1-bit 1 to N bits 1-bit 1 to N bits tPE 20% -9 dB 80% 0V VODB VODPE3 Figure 6. Output De-Emphasis Duration 10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 DS42BR400 www.ti.com SNLS221J – MARCH 2006 – REVISED APRIL 2013 DS42BR400 Test Fixture Pattern Generator DC Block INPUT TL VCC DS42BR400 50: TL Oscilloscope or Jitter Measurement Instrument Coax Coax D+ IN+ M U X R EQ DIN- 50+-1% OUT+ < 2" D OUT- Coax 1000 mVpp Differential DC Block Coax INPUT TL GND 50: TL 50 +-1% Figure 7. AC Test Circuit VCC 5k IN + 50 EQ 50 IN 3.9k 180 pF Figure 8. Receiver Input Termination Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 11 DS42BR400 SNLS221J – MARCH 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision I (April 2013) to Revision J • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS42BR400 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DS42BR400TSQ/NOPB ACTIVE WQFN NKA 60 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 DS42BR400 TSQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of