EMB1499QMHE/NOPB

EMB1499Q www.ti.com SNOSCV7B – NOVEMBER 2011 – REVISED SEPTEMBER 2013 EMB1499Q Bidirectional Current DC-DC Controller Check for Samples: EMB1499Q FEATURES DESCRIPTION • • • • • • The EMB1499Q bidirectional current dc/dc controller IC works in conjunction with the EMB1428 switch matrix gate driver IC to support TI’s switch matrix based active cell balancing scheme for a battery management system. The EMB1499Q provides three PWM MOSFET gate signals to a bidirectional forward converter so that its output current, either positive or negative, is regulated around a user-defined magnitude. This inductor current is channeled by the EMB1428 through the switch matrix to the cell that needs to be charged or discharged. In a typical scheme, the EMB1499Q-based forward converter exchanges energy between a single cell and the battery stack to which it belongs, with a maximum stack voltage of up to 60 V. The switching frequency is fixed at 250 kHz. The EMB1499Q senses cell voltage, inductor current and stack current and provides protection from abnormal conditions during balancing. 1 • • 60-V Maximum Stack Operating Voltage Bidirectional Balancing Current Fully Synchronous Operation Active Clamp Signal 250-kHz Switching Frequency Fault Detection Includes Two Separate UVLO Cells (One for Each External Supply), Primary and Secondary Side Current Limit, OVP/UVP Sense on Cell Being Charged, Thermal Shutdown, and Watchdog Timer Balancing Current User-selectable Through External Voltage EMB1499Q is an Automotive Grade Product that is AEC-Q100 Grade 1 Qualified (–40°C to +125°C Operating Junction Temperature) APPLICATIONS • • • Li-Ion Battery Management Systems Hybrid and Electric Vehicles Grid Storage The EMB1499Q also provides an active clamp timing signal to control an external FET driver for the primary-side active clamp FET. The EMB1499Q is enabled and disabled by the EMB1428. Fault conditions detected by the EMB1499Q are communicated to the EMB1428 through the DONE and FAULT pins. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated EMB1499Q SNOSCV7B – NOVEMBER 2011 – REVISED SEPTEMBER 2013 www.ti.com Typical Application Vstack Vstack ­ ° 7-Cell HalfStack EMB1499 ® GATE_LS GATE_HS2 GATE_HS1 VSENSE_LS VSENSE_HS PWM_CLAMP CELLPLUS VINA VINP VINF PVINF MOSFET DRIVER +12V Floating 12V Supply PGNDF GNDF ° ¯ VSET EMB1428 SOURCE[11..0] GATE[11..0] VDDCP EN DIR DIR_RT DONE FAULT2 FAULT1 FAULT0 DAC EN DIR DIR_RT DONE FAULT2 FAULT1 FAULT0 CEXT2 GNDA GNDP CEXT1 SPI BUS CS SD0 SDI SCLK VSTACK VDD12V VDDP +12V +5V +3.3V TO OTHER BALANCING CIRCUIT CPU OR MCU VDD5V FAULT_INT VDDIO RST GNDP GND Figure 1. Typical Application Connection Diagram VSENSE_HS CELLPLUS LOR TM GNDA VSET WDOR EN DIR DIR_RT DONE FAULT0 FAULT1 FAULT2 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 EMB1499 (Top View) 21 9 20 10 19 11 18 12 17 13 16 14 15 VINF GNDF N/C GATE_HS2 PGNDF GATE_HS1 PVINF VINP GNDP GATE_LS PWM_CLAMP GNDA VINA VSENSE_LS Figure 2. 28-Pin HTSSOP See PWP Package 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: EMB1499Q EMB1499Q www.ti.com SNOSCV7B – NOVEMBER 2011 – REVISED SEPTEMBER 2013 PIN DESCRIPTIONS Pin Name 1 VSENSE_HS 2 CELLPLUS 3 LOR Description Application Information Secondary side current sense input Connect to transformer side of secondary sense resistor Senses the cell voltage, used for OVP/UVP fault detection Connect to top of secondary side of the converter. This is the top of the cell being charged. Fault latch override input Grounded for normal operation. 4 TM Test mode input Grounded for normal operation. 5, 17 GNDA IC signal ground Connect to module ground at board level. 6 VSET Control voltage for adjusting the balancing current This voltage is set by the user. 7 WDOR Watchdog timer override Grounded for normal operation. 8 EN Input from EMB1428, signals charge or discharge cycle to begin. Rising edge of this signal clears all fault latches, the DONE latch, and initiates charge or discharge current. Falling edge of this signal causes the charge current to ramp down to zero, then asserts the DONE signal, causing shutdown. 9 DIR Input from EMB1428, determines the direction of the converter output current "High" indicates charge mode, "Low" indicates discharge mode. 10 DIR_RT Output to EMB1428, inverted copy of the DIR signal Used as a handshake signal to ensure DIR signal has been received correctly. 11 DONE Output to EMB1428, indicates that the balancing current has ramped down towards zero. When the EMB1499Q is disabled by toggling the EN pin low, the chip goes into a 'soft shutdown', ramping the charging current down within several hundred microseconds. When the current has ramped down, the EMB1499Q shuts down and the DONE signal latches high. The DONE latch is cleared at the next rising edge of the EN signal. 12,13,14 FAULT[0,1,2] Outputs to EMB1428, three bit digital fault If a fault condition is detected, the proper three bit word is code latched into the FAULT pins and the EMB1499Q is shut down. The FAULT pins are cleared by the rising edge of the EN input. 15 VSENSE_LS Primary side current sense input Connect to transformer side of primary sense resistor. 16 VINA External 12V supply Powers all internal circuitry besides the primary gate side driver. VINA and VINP should be connected together at the board level. 18 PWM_CLAMP 19 GATE_LS 20 GNDP IC power ground Provides ground return for primary side gate driver. Connect to board level ground. 21 VINP External 12V supply Powers the primary side gate driver. VINP and VINA should be connected together at the board level. 22 PVINF External floating 12V supply This floating supply must be referenced to the bottom of the transformer secondary. Supplies power to the secondary side gate drivers. PVINF and VINF should be connected together at the board level. 23 GATE_HS1 24 PGNDF 25 GATE_HS2 Output, PWM signal used to control primary side active clamp (external driver required) Output, gate signal for external primary side power FET Output, gate signal for external secondary side power FET Floating power ground Connect to secondary side of converter. Provides the ground return for the secondary side gate drivers. Output, gate signal for external secondary side power FET 26 N/C No connect No connect pin. Do not connect 27 GNDF Floating signal ground Connected to secondary side of converter. Provides ground reference for all internal circuitry that floats with the transformer secondary except the secondary side gate drivers. 28 VINF External floating 12V supply This floating supply must be referenced to the bottom of the transformer secondary. Supplies power to all internal circuitry that floats with the transformer secondary except the secondary side gate drivers. PVINF and VINF should be connected together at the board level. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: EMB1499Q 3 EMB1499Q SNOSCV7B – NOVEMBER 2011 – REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) VINA, VINP to GND -0.5V to 15V VINF, PVINF to GNDF -0.5V to 15V GNDF to GND -0.5V to 60V VSENSE_LS to GND -0.5V to 0.5V VSENSE_HS to GNDF -0.5V to 0.5V VSET to GND -0.5V to 7.5V CELLPLUS to GNDF -0.5V to 7.5V All other inputs to GND -0.5V to 15V ESD Rating (2) Human Body Model ±2kV Soldering Information Junction Temperature 150°C Storage Temperature -65°C to 150°C (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/ or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be operated beyond such conditions. The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22–A114. OPERATING RATINGS VINA, VINP to GND 10V to 14V VINF, PVINF to GNDF 10V to 14V GNDF to GND 0V to 56V VSENSE_LS to GND -0.2V to 0.2V VSENSE_HS to GNDF -0.2V to 0.2V VSET to GND 1V to 2.2V CELLPLUS to GNDF 0V to 6V All other inputs to GND 0V to 14V Junction Temperature (TJ) -40°C to 125°C 4 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: EMB1499Q EMB1499Q www.ti.com SNOSCV7B – NOVEMBER 2011 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. For all tests, VINA = VINP = VINF = PVINF = 12V unless otherwise specified. Symbol Parameter Conditions Min Typ (1) Max Units VSET = 2V 45 50 55 mV VSET = 1.2V 24 30 36 mV 220 250 290 kHz Feedback Voltage VSENSE_HS Feedback Voltage Switching Parameters FSW Switching Frequency DMAX Maximum Duty Cycle DMIN Minimum Duty Cycle Charge Direction 91 % Discharge Direction 91 % Charge Direction 4 % Discharge Direction 3 % Operating Thresholds UVLO Under-voltage Lockout VINA, VINP, VINF, PVINF Rising VINA, VINP, VINF, PVINF Falling VEN_TH Enable Threshold VDIR_TH Direction Threshold 10.8 5 V EN Rising EN Falling 1.55 V 0.45 V DIR Rising DIR Falling V 2.75 V 2.2 V Quiescent Currents IQ_VINA VINA Quiescent Current (Operating) VSET = 2V, VSENSE_HS = 0V 2 2.8 mA VINA Quiescent Current (Shutdown) EN = 0V