ESD321
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ESD321 采用 0402 和 SOD-523 封装的
低电容(小于 1pF)单通道 30kV ESD 保护二极管
1 特性
3 说明
• IEC 61000-4-2 级 4 ESD 保护
– ±30kV 接触放电
– ±30kV 空气间隙放电
• IEC 61000-4-4 EFT 保护
– 80A (5/50ns)
• IEC 61000-4-5 浪涌保护
– 6A (8µs/20µs)
• IO 电容:0.9pF(典型值)
• 直流击穿电压:4.5V(最小值)
• 低漏电流:0.1nA(典型值)
• 极低 ESD 钳位电压
– 在 16A TLP 下为 6.8V(I/O 至 GND)
– RDYN:0.13Ω(I/O 至 GND)
• 工业温度范围:–40°C 至 +125°C
• 业界通用的 0402 (DFN1006P2) 和 SOD-523 封装
ESD321 是一款单向 TVS ESD 保护二极管,具有低动
态电阻和低钳位电压。ESD321 的额定 ESD 冲击消散
值高达 ±30kV,符合 IEC 61000-4-2 国际标准(高于 4
级)。
超低动态电阻 (0.13Ω) 和极低钳位电压(16A TLP 时
为 6.8V)可针对瞬态事件提供系统级保护。该器件具
有 0.9pF 的低 IO 电容,适合用于保护 USB 2.0 和以太
网 10/100/1000Mbps 等接口。
ESD321 采用业界通用的 0402 (DPY/DFN1006P2) 和
SOD-523 (DYA) 封装。
封装信息(1)
器件型号
ESD321
2 应用
(1)
• 终端设备:
– 可穿戴设备
– 工业和服务机器人
– 便携式计算机和台式机
– 手机和平板电脑
– 机顶盒
– DVR 和 NVR
– 电视和监视器
– EPOS(电子销售点)
• 接口:
– USB 2.0/1.1
– 通用输入/输出 (GPIO)
– 以太网 10/100/1000Mbps
– 按钮
– 音频
封装
封装尺寸(标称值)
DPY(X1SON,2)
0.60mm x 1.00mm
DYA(SOD-532,
2)
0.80mm × 1.20mm
如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
5-V Source
VBUS
D±
USB Transceiver
D+
1
1
ESD321
ESD321
GND
2
2
USB 2.0 典型应用原理图
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSEN8
ESD321
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ZHCSIK7A – JULY 2018 – REVISED DECEMBER 2022
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings – JEDEC Specifications.......................4
6.3 ESD Ratings – IEC Specifications.............................4
6.4 Recommended Operating Conditions.........................4
6.5 Thermal Information....................................................4
6.6 Electrical Characteristics.............................................5
6.7 Typical Characteristics................................................ 6
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................8
8 Application and Implementation.................................... 9
8.1 Application Information............................................... 9
8.2 Typical Application...................................................... 9
9 Power Supply Recommendations................................11
10 Layout...........................................................................12
10.1 Layout Guidelines................................................... 12
10.2 Layout Example...................................................... 12
11 Device and Documentation Support..........................13
11.1 Documentation Support.......................................... 13
11.2 接收文档更新通知................................................... 13
11.3 支持资源..................................................................13
11.4 Trademarks............................................................. 13
11.5 Electrostatic Discharge Caution.............................. 13
11.6 术语表..................................................................... 13
12 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (July 2018) to Revision A (December 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式......................................................................................... 1
• 向数据表添加了 DYA 封装.................................................................................................................................. 1
2
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5 Pin Configuration and Functions
1
2
图 5-1. DPY Package, 2-Pin X1SON (Top View)
ID Area
1
2
图 5-2. DYA Package, 2-Pin SOD-523 (Top View)
表 5-1. Pin Functions
PIN
NAME
(1)
TYPE(1)
NO.
DPY
DYA
IO
1
2
I/O
GND
2
1
GND
DESCRIPTION
ESD Protected Channel. Connect to the line being protected.
Connect to ground
I = input, O = output, GND = ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
Electrical Fast
Transient
Surge Pulse
MAX
UNIT
IEC 61000-4-4 Peak Current at 25 °C
80
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Power at 25 °C
40
W
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Current at 25 °C
6
A
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
155
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings – JEDEC Specifications
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2500
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings – IEC Specifications
VALUE
V(ESD)
Electrostatic discharge
IEC 61000-4-2 Contact Discharge, all pins
±30000
IEC 61000-4-2 Air Discharge, all pins
±30000
UNIT
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
TA
Operating Free Air Temperature
NOM
MAX
UNIT
0
3.6
V
–40
125
°C
6.5 Thermal Information
ESD321
THERMAL METRIC (1)
DPY (X1SON)
UNIT
2 Pins
2 Pins
RθJA
Junction-to-ambient thermal resistance
774.7
437.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
462.3
249.5
°C/W
RθJB
Junction-to-board thermal resistance
541.1
169.2
°C/W
ΨJT
Junction-to-top characterization parameter
164.4
99.3
°C/W
ΨJB
Junction-to-board characterization parameter
534.6
168.6
°C/W
(1)
4
DYA (SOD-523)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
At TA = 25°C unless otherwise noted
PARAMETER
VRWM
Reverse stand-off voltage
ILEAKAGE
Leakage current at 3.6 V
TEST CONDITIONS
VIO = 3.6 V, I/O to GND
Breakdown voltage, I/O to GND
VFWD
Forward Voltage, GND to I/O (1)
VCLAMP
RDYN
(2)
(2)
Clamping voltage
Dynamic resistance
CLINE
(1)
Holding voltage, I/O to GND
TYP
IIO < 50 nA, across operating
temperature range
VBRF
VHOLD
MIN
Line capacitance, IO to GND
(1)
IIO = 1 mA
0.1
4.5
MAX
UNIT
3.6
V
10
nA
7.5
V
IIO = 1 mA
0.8
V
IIO = 1 mA
5.1
V
IPP = 6 A (8/20 µs Surge), I/O to GND
6.3
V
IPP = 16 A (100 ns TLP), I/O to GND
6.8
V
IPP = 16 A (100 ns TLP), GND to I/O
4.7
V
I/O to GND, 100 ns TLP, between 10
to 20 A IPP
0.13
GND to I/O , 100 ns TLP, between 10
to 20 A IPP
0.2
VIO = 0 V, Vp-p = 30 mV, f = 1 MHz
0.9
Ω
1.1
pF
VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the
snapback state
VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
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6.7 Typical Characteristics
32
4
28
0
24
-4
-8
Current (A)
Current (A)
20
16
12
-12
-16
8
-20
4
-24
0
-28
-4
0
1
2
3
4
5
6
Volatge (V)
7
8
9
-32
-8
10
-7
-6
-5
D001
-4
-3
Voltage (V)
D001_TLP_IO_GND.grf
10
50
0
40
-10
20
-30
-40
0
-50
0
10
20
30
40
50
Time (ns)
60
70
80
D002
-20
10
-10
-10
-60
-10
90
0
10
20
30
D003
40
50
Time (ns)
60
80
90
D004_8kV_neg.grf
图 6-4. 8-kV IEC 61000-4-2 Clamping Voltage Waveform, GND to
I/O Pin
45
0.001
Current (A)
Power (W)
Current (A), Voltage (V)
40
0.0005
Current (A)
70
D004
D003_8kV_pos.grf
图 6-3. 8-kV IEC 61000-4-2 Clamping Voltage Waveform, I/O Pin
to GND
0
图 6-2. TLP I-V Curve, GND to I/O Pin (tp = 100 ns)
60
30
-1
D002_TLP_GND_IO.grf
Voltage (V)
Voltage (V)
图 6-1. TLP I-V Curve, I/O Pin to GND (tp = 100 ns)
-2
0
-0.0005
35
30
25
20
15
10
5
0
-0.001
-1
0
1
2
3
4
Voltage (V)
5
6
7
-5
-20
D005
D005_DC_Plot.grf
图 6-5. DC Voltage Sweep I-V Curve, I/O Pin to GND
6
0
20
40
60
80 100
Time (Ps)
120
140
160
180
D006
D006_Surge.grf
图 6-6. Surge Curve (IEC 61000-4-5, tp=8/20 µs), I/O Pin to GND
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6.7 Typical Characteristics (continued)
20
2
-40
25
85
18
16
14
Current (nA)
Capacitance (pF)
1.6
1.2
0.8
12
10
8
6
4
0.4
2
0
-40
0
0
0.4
0.8
1.2
1.6
2
2.4
Bias Voltage (V)
2.8
3.2
3.6
4
-20
0
D007
20
40
60
80
Temperature (°C)
100
120
140
D008
D008_Leakage_Temp.grf
D007_Cap_Bias.grf
图 6-7. Capacitance vs. Bias Voltage For Different Temperatures
(°C)
图 6-8. Leakage Current (at 3.6 V Bias) Across Temperature, I/O
Pin to GND
0.5
0
-0.5
S21 (dB)
-1
-1.5
-2
-2.5
-3
-3.5
0.1
0.2
0.3
0.5 0.7 1
2
Frequency (GHz)
3
4 5 6 7 8 10
D009
D009_S21.grf
图 6-9. Insertion Loss vs. Frequency
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7 Detailed Description
7.1 Overview
The ESD321 is a low capacitance uni-directional ESD Protection Diode with a low clamping voltage. This device
can dissipate ESD strikes up to ±30 kV (Contact and Air) per the IEC 61000-4-2 Standard. The low clamping
makes this device suitable for protecting any ESD sensitive devices.
7.2 Functional Block Diagram
7.3 Feature Description
ESD321 provides ESD protection up to ±30-kV contact and ±30-kV air gap per IEC 61000-4-2 standard. During
an ESD event, ESD diode connected to the I/O pin turns on and diverts the current to ground. Additionally,
ESD321 also provides protection against IEC 61000-4-5 Surge currents up to 6 A (8/20 µs waveform) and up to
80 A per IEC 61000-4-4 (5/50 ns waveform, 4 kV with 50-Ω impedance) electrical fast transient (EFT) standard.
The capacitance between the I/O pin and ground is 0.9 pF (typical) and 1.1 pF (maximum). The device features
a low leakage current of 0.1 nA (typical) and 50 nA (maximum, across operating temperature range) with a bias
of 3.6 V. The ESD diode at the I/O pin protects the ESD-sensitive devices by clamping the voltage to a low value
of 6.8 V (IPP = 16 A 100 ns TLP ). The layout of this device makes it simple and easy to add protection to an
existing layout. The package offers flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The ESD321 is a passive integrated circuit that triggers when voltages are above VBRF or below VFWD. During
ESD events, voltages as high as ±30 kV (contact or air) can be directed to ground via the internal diode network.
When the voltages on the protected line fall below the trigger levels of ESD321 (usually within 10s of nanoseconds) the device reverts to passive.
8
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8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The ESD321 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on highspeed signal lines between a human interface connector and a system. As the current from ESD passes through
the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
5-V Source
VBUS
D±
USB Transceiver
D+
1
1
ESD321
ESD321
GND
2
2
图 8-1. USB 2.0 ESD Schematic
8.2.1 Design Requirements
For this design example, two ESD321 devices are being used in a USB 2.0 application. This provides a
complete ESD protection scheme.
Given the USB 2.0 application, the parameters listed in 表 8-1 are known.
表 8-1. Design Parameters
DESIGN PARAMETER
VALUE
Signal range on DP-DM lines
0 V to 3.6 V
Operating frequency on DP-DM lines
up to 240 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The ESD321 supports signal ranges between 0 V and 3.6 V, which supports the USB 2.0 signal pair on the USB
2.0 application.
8.2.2.2 Operating Frequency
The ESD321 has a 0.9 pF (typical) capacitance, which supports the USB 2.0 data rates of 480 Mbps.
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8.2.3 Application Curve
0.5
0
-0.5
S21 (dB)
-1
-1.5
-2
-2.5
-3
-3.5
0.1
0.2
0.3
0.5 0.7 1
2
Frequency (GHz)
3
4 5 6 7 8 10
D009
D009_S21.grf
图 8-2. Insertion Loss Vs. Frequency
10
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9 Power Supply Recommendations
The ESD321 is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (0 V to 3.6 V) to ensure the device functions properly.
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10 Layout
10.1 Layout Guidelines
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
VBUS
To power supply
ESD321
D-
To USB transceiver
D+
ESD321
Legend
Pin to GND
GND
USB2.0 Connector
图 10-1. USB 2.0 ESD Layout
12
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Generic ESD Device Evaluation Module
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ESD321DPYR
ACTIVE
X1SON
DPY
2
10000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
DD
Samples
ESD321DYAR
ACTIVE
SOT-5X3
DYA
2
3000
RoHS & Green
SN
Level-3-260C-168 HR
-55 to 150
1L8
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of