LM5100MX

NRND LM5100, LM5101 www.ti.com SNVS267C – MAY 2004 – REVISED MARCH 2005 LM5100 /LM5101 High Voltage High Side and Low Side Gate Driver Check for Samples: LM5100, LM5101 FEATURES PACKAGE • • • 1 2 • • • • • • • • Drives Both a High Side and Low Side NChannel MOSFET Independent High and Low Driver Logic Inputs (TTL for LM5101 or CMOS for LM5100) Bootstrap Supply Voltage Range up to 118V DC Fast Propagation Times (25 ns Typical) Drives 1000 pF Load with 15 ns Rise and Fall Times Excellent Propagation Delay Matching (3 ns Typical) Supply Rail Under-voltage Lockouts Low Power Consumption Pin Compatible with HIP2100/HIP2101 TYPICAL APPLICATIONS • • • • • Current Fed Push-pull Converters Half and Full Bridge Power Converters Synchronous Buck Converters Two Switch Forward Power Converters Forward with Active Clamp Converters SOIC-8 WSON-10 (4 mm x 4 mm) DESCRIPTION The LM5100/LM5101 High Voltage Gate Drivers are designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of operating with supply voltages up to 100V. The outputs are independently controlled with CMOS input thresholds (LM5100) or TTL input thresholds (LM5101). An integrated high voltage diode is provided to charge the high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Under-voltage lockout is provided on both the low side and the high side power rails. This device is available in the standard SOIC-8 pin and the WSON-10 pin packages. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated NRND LM5100, LM5101 SNVS267C – MAY 2004 – REVISED MARCH 2005 www.ti.com Simplified Block Diagram HV HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LO DRIVER LI VSS Connection Diagrams VDD 1 8 LO HB 2 7 VSS HO 3 6 LI HS 4 5 HI SOIC-8 2 VDD 1 10 HB 2 9 VSS HO 3 8 LI HS 4 7 HI NC 5 6 NC Submit Documentation Feedback WSON-10 LO Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 NRND LM5100, LM5101 www.ti.com SNVS267C – MAY 2004 – REVISED MARCH 2005 PIN DESCRIPTION (1) Pin # (1) Name Description Application Information SO-8 WSON10 1 1 VDD Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor located as close to IC as possible. 2 2 HB High side gate driver bootstrap rail Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The Bootstrap capacitor should be place as close to IC as possible. 3 3 HO High side gate driver output Connect to gate of high side MOSFET with a short low inductance path. 4 4 HS High side MOSFET source connection Connect to bootstrap capacitor negative terminal and the source of the high side MOSFET. 5 7 HI High side driver control input The LM5100 inputs have CMOS type thresholds. The LM5101 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. 6 8 LI Low side driver control input The LM5100 inputs have CMOS type thresholds. The LM5101 inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. 7 9 VSS Ground return All signals are referenced to this ground. 8 10 LO Low side gate driver output Connect to the gate of the low side MOSFET with a short low inductance path. Note: For WSON-10 package, it is recommended that the exposed pad on the bottom of the LM5100 / LM5101 be soldered to ground plane on the PC board, and the ground plane should extend out from beneath the IC to help dissipate the heat. Pins 5 and 6 have no connection. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 3 NRND LM5100, LM5101 SNVS267C – MAY 2004 – REVISED MARCH 2005 www.ti.com Absolute Maximum Ratings (1) (2) −0.3V to +18V VDD to VSS −0.3V to +18V VHB to VHS LI or HI Inputs −0.3V to VDD +0.3V LO Output −0.3V to VDD +0.3V HO Output VHS −0.3V to VHB +0.3V VHS to VSS −1V to +100V VHB to VSS 118V Junction Temperature +150°C −55°C to +150°C Storage Temperature Range ESD Rating HBM (3) (1) (2) (3) 2 kV Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are rated at 500V. Recommended Operating Conditions VDD +9V to +14V HS −1V to 100V HB VHS +8V to VHS +14V HS Slew Rate < 50 V/ns −40°C to +125°C Junction Temperature Electrical Characteristics Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO . Symbol Parameter Typ Max (1) LI = HI = 0V (LM5100) 0.1 0.2 LI = HI = 0V (LM5101) 0.25 0.4 Conditions Min (1) Units SUPPLY CURRENTS IDD VDD Quiescent Current mA IDDO VDD Operating Current f = 500 kHz 1.5 3 mA IHB Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA IHBO Total HB Operating Current f = 500 kHz 1.3 3 mA IHBS HB to VSS Current, Quiescent VHS = VHB = 100V 0.05 10 IHBSO HB to VSS Current, Operating f = 500 kHz 0.08 mA µA INPUT PINS VIL Low Level Input Voltage Threshold (LM5100) 3 5.0 V VIL Low Level Input Voltage Threshold (LM5101) 0.8 1.8 V VIH High Level Input Voltage Threshold (LM5100) 5.5 8 V VIH High Level Input Voltage Threshold (LM5101) 1.8 2.2 V VIHYS Input Voltage Hysteresis (LM5100) RI Input Pulldown Resistance 0.5 V 100 200 500 kΩ 6.0 6.9 7.4 V UNDER VOLTAGE PROTECTION VDDR (1) 4 VDD Rising Threshold Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 NRND LM5100, LM5101 www.ti.com SNVS267C – MAY 2004 – REVISED MARCH 2005 Electrical Characteristics (continued) Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO . Symbol Parameter VDDH VDD Threshold Hysteresis VHBR HB Rising Threshold VHBH HB Threshold Hysteresis Conditions Min (1) Typ Max (1) Units 0.5 5.7 6.6 V 7.1 V 0.4 V BOOT STRAP DIODE VDL Low-Current Forward Voltage IVDD-HB = 100 µA 0.6 0.9 V VDH High-Current Forward Voltage IVDD-HB = 100 mA 0.85 1.1 V RD Dynamic Resistance IVDD-HB = 100 mA 0.8 1.5 Ω LO GATE DRIVER VOLL Low-Level Output Voltage ILO = 100 mA 0.23 0.4 V VOHL High-Level Output Voltage ILO = −100 mA, VOHL = VDD–VLO 0.35 0.55 V IOHL Peak Pullup Current VLO = 0V 1.6 A IOLL Peak Pulldown Current VLO = 12V 1.8 A HO GATE DRIVER VOLH Low-Level Output Voltage IHO = 100 mA 0.23 0.4 V VOHH High-Level Output Voltage IHO = −100 mA VOHH = VHB–VHO 0.35 0.55 V IOHH Peak Pullup Current VHO = 0V 1.6 A IOLH Peak Pulldown Current VHO = 12V 1.8 A SOIC-8 170 WSON-10 (3) 40 THERMAL RESISTANCE θJA (2) (2) (3) Junction to Ambient °C/W The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187 (SNOA401). Switching Characteristics Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Symbol Parameter Conditions Min (1) Typ Max (1) Units LM5100 tLPHL Lower Turn-Off Propagation Delay (LI Falling to LO Falling) 24 45 ns tHPHL Upper Turn-Off Propagation Delay (HI Falling to HO Falling) 24 45 ns tLPLH Lower Turn-On Propagation Delay (LI Rising to LO Rising) 24 45 ns tHPLH Upper Turn-On Propagation Delay (HI Rising to HO Rising) 24 45 ns tMON Delay Matching: Lower Turn-On and Upper Turn-Off 2 10 ns tMOFF Delay Matching: Lower Turn-Off and Upper Turn-On 2 10 ns tRC, tFC Either Output Rise/Fall Time CL = 1000 pF 15 ns tR, tF Either Output Rise/Fall Time (3V to 9V) CL = 0.1 µF 0.6 µs tPW Minimum Input Pulse Width that Changes the Output 50 ns (1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 5 NRND LM5100, LM5101 SNVS267C – MAY 2004 – REVISED MARCH 2005 www.ti.com Switching Characteristics (continued) Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Symbol tBS Parameter Conditions Bootstrap Diode Turn-Off Time IF = 20 mA, IR = 200 mA Min (1) Typ Max (1) 50 Units ns LM5101 tLPHL Lower Turn-Off Propagation Delay (LI Falling to LO Falling) 25 56 ns tHPHL Upper Turn-Off Propagation Delay (HI Falling to HO Falling) 25 56 ns tLPLH Lower Turn-On Propagation Delay (LI Rising to LO Rising) 25 56 ns tHPLH Upper Turn-On Propagation Delay (HI Rising to HO Rising) 25 56 ns tMON Delay Matching: Lower Turn-On and Upper Turn-Off 2 10 ns tMOFF Delay Matching: Lower Turn-Off and Upper Turn-On 2 10 ns tRC, tFC Either Output Rise/Fall Time CL = 1000 pF 15 ns tR, tF Either Output Rise/Fall Time (3V to 9V) CL = 0.1 µF 0.6 µs tPW Minimum Input Pulse Width that Changes the Output 50 ns tBS Bootstrap Diode Turn-Off Time 50 ns 6 IF = 20 mA, IR = 200 mA Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 NRND LM5100, LM5101 www.ti.com SNVS267C – MAY 2004 – REVISED MARCH 2005 Typical Performance Characteristics LM5100 IDD vs Frequency LM5101 IDD vs Frequency 100000 100000 VDD = 12V CL = 4400 pF CURRENT (PA) CL = 2200 pF 10000 CURRENT (PA) VDD = 12V CL = 4400 pF CL = 1000 pF 1000 CL = 2200 pF 10000 CL = 1000 pF 1000 100 CL = 0 pF 10 0.1 CL = 470 pF 1 10 100 CL = 0 pF CL = 470 pF 100 0.1 1000 1 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 1. Figure 2. LM5100/LM5101 Operating Current vs Temperature IHB vs Frequency 100000 1.20 1.15 HB = 12V, HS = 0V IDDO (LM5101) 1.10 CURRENT (PA) 1.05 1.00 IDDO (LM5100) 0.95 0.90 IHBO (LM5100, LM5101) 0.85 CL = 4400 pF CL = 2200 pF 10000 CURRENT (mA) 10 CL = 1000 pF 1000 100 0.80 CL = 0 pF 0.75 0.70 -50 -25 0 25 50 10 0.1 75 100 125 150 CL = 470 pF 1 TEMPERATURE (°C) 100 1000 FREQUENCY (kHz) Figure 3. Figure 4. Quiescent Current vs Supply Voltage LM5100/LM5101 Quiescent Current vs Temperature 400 350 350 300 IDD (LM5101) IDD (LM5101) 300 250 CURRENT (PA) CURRENT (PA) 10 250 200 IDD (LM5100) 150 200 150 100 100 IDD (LM5100) 50 50 IHB (LM5100, LM5101) IHB (LM5100, LM5101) 0 8 10 12 14 16 18 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) VDD, VHB (V) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 7 NRND LM5100, LM5101 SNVS267C – MAY 2004 – REVISED MARCH 2005 www.ti.com Typical Performance Characteristics (continued) Undervoltage Rising Thresholds vs Temperature LM5100 Undervoltage Threshold Hysteresis vs Temperature 7.30 0.60 7.20 0.55 VDDH 7.00 VDDR HYSTERESIS (V) THRESHOLD (V) 7.10 6.90 6.80 6.70 VHBR 6.60 6.50 0.50 0.45 VHBH 0.40 0.35 6.40 6.30 -50 -25 0 25 50 0.30 -50 75 100 125 150 -25 0_ 25 50_ 75_100_125_150_ TEMPERATURE (oC) TEMPERATURE (°C) Figure 7. Figure 8. Bootstrap Diode Forward Voltage HO and LO Peak Output Current vs Output Voltage 2.00 1.00E-01 1.60 CURRENT (A) 1.00E-02 T = 25°C ID (A) 1.00E-03 VDD = VHB = 12V, HS = 0V 1.80 T = 150°C 1.00E-04 1.40 1.20 SOURCING 1.00 0.80 SINKING 0.60 T = -40°C 1.00E-05 0.40 0.20 1.00E-06 0.2 0.00 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 2 4 8 10 12 Figure 9. Figure 10. LO and HO Gate Drive—High Level Output Voltage vs Temperature LO and HO Gate Drive—Low Level Output Voltage vs Temperature 0.400 0.700 0.350 0.600 VDD = VHB = 8V VDD = VHB = 8V 0.300 VDD = VHB = 12V VOL (V) VOH (V) 0.500 0.400 VDD = VHB = 12V 0.250 0.200 0.300 VDD = VHB = 16V VDD = VHB = 16V 0.150 0.200 0.100 -50 -25 0 25 50 75 100 125 150 0.100 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. 8 6 HO, LO (V) VD (V) Figure 12. Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 NRND LM5100, LM5101 www.ti.com SNVS267C – MAY 2004 – REVISED MARCH 2005 Typical Performance Characteristics (continued) LM5100 Propagation Delay vs Temperature LM5101 Propagation Delay vs Temperature 35 35 tHPHL tHPHL tLPLH 30 DELAY (ns) DELAY (ns) 30 tHPLH 25 20 tLPLH 25 tLPHL 20 tHPLH tLPHL 15 -50 -25 0 25 50 15 -50 75 100 125 150 -25 0 TEMPERATURE (°C) 25 50 75 100 125 150 TEMPERATURE (°C) Figure 13. Figure 14. Timing Diagram LI LI HI tHPLH tLPLH HI tHPHL tLPHL LO LO HO HO tMON tMOFF Figure 15. Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 9 NRND LM5100, LM5101 SNVS267C – MAY 2004 – REVISED MARCH 2005 www.ti.com LAYOUT CONSIDERATIONS The optimum performance of high and low side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. A low ESR / ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding Considerations: – a) The first priority in designing grounding connections is to confine the high peak currents from charging and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. – b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: PDGATES = 2 • f • CL • VDD2 There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equation. This plot can be used to approximate the power losses due to the gate drivers. 1.000 CL = 4400 pF CL = 2200 pF POWER (W) 0.100 CL = 1000 pF 0.010 CL = 470 pF CL = 0 pF 0.001 0.1 _ 1.0 _ 10.0_ 100.0 1000.0_ SWITCHING FREQUENCY (kHz) Figure 16. Gate Driver Power Dissipation (LO + HO) VCC = 12V, Neglecting Diode Losses 10 Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 NRND LM5100, LM5101 www.ti.com SNVS267C – MAY 2004 – REVISED MARCH 2005 The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. 1.000 POWER (W) CL = 4400 pF 0.100 CL = 0 pF 0.010 0.001 1.0 10.0 100.0 1000.0 SWITCHING FREQUENCY (kHz) Figure 17. Diode Power Dissipation VIN = 80V 1.000 POWER (W) CL = 4400 pF 0.100 CL = 0 pF 0.010 0.001 1.0 10.0 100.0 1000.0 SWITCHING FREQUENCY (kHz) Figure 18. Diode Power Dissipation VIN = 40V The total IC power dissipation can be estimated from the previous plots by summing the gate drive losses with the bootstrap diode losses for the intended application. Because the diode losses can be significant, an external diode placed in parallel (refer to Figure 19) with the internal bootstrap diode can be helpful in removing power from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series inductance and have a significantly lower forward voltage drop than the internal diode. Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 11 NRND LM5100, LM5101 SNVS267C – MAY 2004 – REVISED MARCH 2005 www.ti.com (Optional external fast recovery diode) VIN VCC RGATE HB VDD HO VDD CBOOT PWM CONTROLLER OUT1 OUT2 GND HS HI LM5101 T1 LO LI VSS Figure 19. LM5101 Driving MOSFETs Connected in Half-Bridge Configuration 12 Submit Documentation Feedback Copyright © 2004–2005, Texas Instruments Incorporated Product Folder Links: LM5100 LM5101 PACKAGE OPTION ADDENDUM www.ti.com 1-Oct-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking TBD Call TI Call TI 5100 M (4/5) LM5100MX/NOPB OBSOLETE SOIC D 8 LM5101M/NOPB NRND SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 5101 M LM5101MX/NOPB NRND SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 5101 M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM5101MX/NOPB Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 5.4 2.0 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5101MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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