LMC6044
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SNOS612D – NOVEMBER 1994 – REVISED MARCH 2013
LMC6044 CMOS Quad Micropower Operational Amplifier
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FEATURES
APPLICATIONS
1
•
•
•
•
•
2
Low Supply Current: 10 μA/Amp (Typ)
Operates from 4.5V to 15.5V Single Supply
Ultra Low Input Current: 2 fA (Typ)
Rail-to-Rail Output Swing
Input Common-Mode Range Includes Ground
•
•
•
•
•
•
•
Battery Monitoring and Power Conditioning
Photodiode and Infrared Detector Preamplifier
Silicon Based Transducer Systems
Hand-Held Analytic Instruments
pH Probe Buffer Amplifier
Fire and Smoke Detection Systems
Charge Amplifier for Piezoelectric Transducers
DESCRIPTION
Ultra-low power consumption and low input-leakage current are the hallmarks of the LMC6044. Providing input
currents of only 2 fA typical, the LMC6044 can operate from a single supply, has output swing extending to each
supply rail, and an input voltage range that includes ground.
The LMC6044 is ideal for use in systems requiring ultra-low power consumption. In addition, the insensitivity to
latch-up, high output drive, and output swing to ground without requiring external pull-down resistors make it
ideal for single-supply battery-powered systems.
Other applications for the LMC6044 include bar code reader amplifiers, magnetic and electric field detectors, and
hand-held electrometers.
This device is built with National's advanced Double-Poly Silicon-Gate CMOS process.
See the LMC6041 for a single, and the LMC6042 for a dual amplifier with these features.
Connection Diagram
14-Pin PDIP/SOIC
Instrumentation Amplifier
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1994–2013, Texas Instruments Incorporated
LMC6044
SNOS612D – NOVEMBER 1994 – REVISED MARCH 2013
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Absolute Maximum Ratings (1) (2)
Differential Input Voltage
±Supply Voltage
Supply Voltage (V+ − V−)
16V
Output Short Circuit to V+
See (3)
Output Short Circuit to V−
See (4)
Lead Temperature (Soldering, 10 sec.)
260°C
Current at Input Pin
±5 mA
Current at Output Pin
±18 mA
Current at Power Supply Pin
35 mA
Power Dissipation
See (5)
−65°C to +150°C
Storage Temperature Range
Junction Temperature
(5)
110°C
ESD Tolerance (6)
500V
+0.3V, (V−) −0.3V
Voltage at I/O Pin (V+)
(1)
(2)
(3)
(4)
(5)
(6)
Absolute Maximum Ratings indicate limts beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 110°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(max) − TA)/θJA.
Human body model, 1.5 kΩ in series with 100 pF.
Operating Ratings
Temperature Range
Thermal Resistance (θJA) (1)
LMC6044AI, LMC6044I
Supply Voltage
−40°C ≤ TJ ≤ +85°C
4.5V ≤ V+ ≤ 15.5V
14-Pin PDIP
85°C/W
14-Pin SOIC
115°C/W
See (2)
Power Dissipation
(1)
(2)
2
All numbers apply for packages soldered directly into a PC poard.
For operating at elevated temperatures, the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA.
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Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ =
5V, V− = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified.
Symbol
VOS
Parameter
Conditions
Typical (1)
1
Input Offset Voltage
LMC6044AI
Limit (2)
LMC6044I
Limit (2)
3
6
mV
3.3
6.3
max
TCVOS
Input Offset Voltage
Average Drift
IB
Input Bias Current
0.002
4
4
IOS
Input Offset Current
0.001
2
2
RIN
Input Resistance
CMRR
Common Mode Rejection
Ratio
0V ≤ VCM ≤ 12.0V
V+ = 15V
75
Positive Power Supply
Rejection Ratio
5V ≤ V+ ≤ 15V
VO = 2.5V
75
Negative Power Supply
Rejection Ratio
0V ≤ V− ≤ −10V
VO = 2.5V
94
+PSRR
−PSRR
>10
V = 5V & 15V
For CMRR ≥ 50 dB
pA max
TeraΩ
68
62
dB
66
60
min
68
62
dB
66
60
min
84
74
dB
83
73
min
−0.4
−0.1
−0.1
V
0
0
max
V+ − 1.9V
V+ − 2.3V
V+ − 2.3V
V
V+ − 2.5V
V+ − 2.4V
min
400
300
V/mV
300
200
min
180
90
V/mV
120
70
min
200
100
V/mV
160
80
min
250
100
50
V/mV
60
40
min
4.987
4.970
4.940
V
4.950
4.910
min
0.030
0.060
V
0.050
0.090
max
4.920
4.870
V
4.870
4.820
min
0.080
0.130
V
0.130
0.180
max
14.920
14.880
V
14.880
14.820
min
0.030
0.060
V
0.050
0.090
max
14.900
14.850
V
14.850
14.800
min
0.100
0.150
V
0.150
0.200
max
+
AV
Sourcing
RL = 100 kΩ (3)
Sinking
Large Signal Voltage Gain
Sourcing
RL = 25 kΩ (3)
Sinking
VO
1000
500
1000
+
V = 5V
RL = 100 kΩ to 2.5V
0.004
4.980
+
V = 5V
RL = 25 kΩ to 2.5V
Output Swing
0.010
14.970
+
V = 15V
RL = 100 kΩ to V+/2
0.007
14.950
V+ = 15V
RL = 25 kΩ to V+/2
(1)
(2)
(3)
μV/°C
1.3
CMR
Input Common-Mode
Voltage Range
Units
(Limit)
0.022
Typical Values represent the most likely parametric norm.
All limits are guaranteed at room temperature (standard type face) or at operating temperature extremes (bold face type).
V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
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Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ =
5V, V− = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified.
Symbol
Parameter
ISC
Conditions
Typical (1)
LMC6044AI
Limit (2)
LMC6044I
Limit (2)
22
16
13
mA
10
8
min
16
13
mA
8
8
min
15
15
mA
10
10
min
39
24
21
mA
8
8
min
Four Amplifiers
VO = 1.5V
40
65
75
μA
72
82
max
Four Amplifiers
V+ = 15V
52
Sourcing, VO = 0V
Output Current
V+ = 5V
21
Sinking, VO = 5V
ISC
40
Sourcing, VO = 0V
Output Current
V+ = 15V
IS
Sinking, VO = 13V (4)
Supply Current
(4)
Units
(Limit)
85
98
μA
94
107
max
Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TA = TJ = 25°C. Boldface limits apply at the temperature extremes. V+ =
5V, V− = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified.
Symbol
SR
Parameter
Slew Rate
GBW
Gain-Bandwidth Product
φm
Phase Margin
Conditions
See (3)
Typical (1)
LMC6044AI
Limit (2)
LMC6044I
Limit (2)
Units
(Limit)
0.02
0.015
0.010
V/μs
0.010
0.007
min
0.10
MHz
60
Deg
Amp-to-Amp Isolation
See (4)
115
dB
en
Input-Referred Voltage Noise
F = 1 kHz
83
nV/√Hz
in
Input-Referred Current Noise
F = 1 kHz
0.0002
pA/√Hz
Total Harmonic Distortion
F = 1 kHz, AV = −5
RL = 100 kΩ, VO = 2 Vpp
±5V Supply
0.01
%
T.H.D.
(1)
(2)
(3)
(4)
4
Typical Values represent the most likely parametric norm.
All limits are guaranteed at room temperature (standard type face) or at operating temperature extremes (bold face type).
V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified in the slower of the positive and negative slew rates.
Input referred V+ = 15V and RL = 100 kΩ connected to V+/2. Each amp excited in turn with 100 Hz to produce VO = 12 VPP.
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Typical Performance Characteristics
VS = ±7.5V, TA = 25°C unless otherwise specified
Supply Current vs
Supply Voltage
Offset Voltage vs
Temperature of Five
Representative Units
Figure 1.
Figure 2.
Input Bias Current
vs Temperature
Input Bias Current vs
Input Common-Mode
Voltage
Figure 3.
Figure 4.
Input Common-Mode
Voltage Range vs
Temperature
Output Characteristics
Current Sinking
Figure 5.
Figure 6.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
6
Output Characteristics
Current Sourcing
Output Characteristics
vs Frequency
Figure 7.
Figure 8.
Crosstalk Rejection vs
Frequency
CMRR
vs
Frequency
Figure 9.
Figure 10.
CMRR
vs
Temperature
Power Supply Rejection
Ratio
vs
Frequency
Figure 11.
Figure 12.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Open-Loop Voltage Gain
vs Temperature
Open-Loop
Frequency Response
Figure 13.
Figure 14.
Gain and Phase
Responses
vs
Load
Capacitance
Gain and Phase
Responses vs
Temperature
Figure 15.
Figure 16.
Gain Error
(VOS
vs
VOUT)
Common-Mode Error vs
Common-Mode Voltage of
Three Representative Units
Figure 17.
Figure 18.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
8
Non-Inverting Slew
Rate
vs
Temperature
Inverting Slew Rate
vs Temperature
Figure 19.
Figure 20.
Non-Inverting Large
Signal Pulse Response
(AV = +1)
Non-Inverting Small
Signal Pulse Response
Figure 21.
Figure 22.
Inverting Large-Signal
Pulse Response
Inverting Small Signal
Pulse Response
Figure 23.
Figure 24.
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Typical Performance Characteristics (continued)
VS = ±7.5V, TA = 25°C unless otherwise specified
Stability
vs
Capacitive Load
Stability
vs
Capacitive Load
Figure 25.
Figure 26.
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APPLICATION HINTS
AMPLIFIER TOPOLOGY
The LMC6044 incorporates a novel op-amp design topology that enables it to maintain rail to rail output swing
even when driving a large load. Instead of relying on a push-pull unity gain outupt buffer stage, the output stage
is taken directly from the internal integrator, which provides both low output impedance and large gain. Special
feed-forward compensation design techniques are incorporated to maintain stability over a wider range of
operating conditions than traditional micropower op-amps. These features make the LMC6044 both easier to
design with, and provide higher speed than products typically found in this ultra-low power class.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance with amplifiers with ultra-low input current, like the
LMC6044.
Although the LMC6044 is highly stable over a wide range of operating conditions, certain precautions must be
met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and
even small values of input capacitance, due to transducers, photodiodes, and circuits board parasitics, reduce
phase margins.
When high input impedance are demanded, guarding of the LMC6044 is suggested. Guarding input lines will not
only reduce leakage, but lowers stray input capacitance as well. (See PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK.)
Figure 27. Canceling the Effect of Input Capacitance
The effect of input capacitance can be compensated for by adding a capacitor. Adding a capacitor, Cf, around
the feedback resistor (as in Figure 27) such that:
(1)
or
R1 CIN ≤ R2 Cf
(2)
Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on
compensating for input capacitance.
CAPACITIVE LOAD TOLERANCE
Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created
by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the
unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.
With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 28.
10
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Figure 28. LMC6044 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 28, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the
overall feedback loop.
Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 29). Typically, a pull up
resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).
Figure 29. Compensating for Large Capacitive Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6044, typically less than 2 fA, it is essential to have an excellent layout. Fortunately, the techniques of
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
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Figure 30. Example of Guard Ring in P.C. Board Layout
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6044's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs, as in Figure 30. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifer
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the
LMC6044's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 33 for typical connections of guard
rings for standard op-amp configurations.
Figure 31. Inverting Amplifier Typical Connections of Guard Rings
Figure 32. Non-Inverting Amplifier Typical Connections of Guard Rings
Figure 33. Follower Typical Connections of Guard Rings
12
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The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 34.
Typical Single-Supply Applications
(V+ = 5.0 VDC)
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 34. Air Wiring
The extremely high input impedance, and low power consumption, of the LMC6044 make it ideal for applications
that require battery-powered instrumentation amplifiers. Examples of these type of applications are hand-held pH
probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure
transducers.
The circuit in Figure 35 is recommended for applications where the common-mode input range is relatively low
and the differential gain will be in the range of 10 to 1000. This two op-amp instrumentation amplifier features an
independent adjustment of the gain and common-mode rejection trim, and a total quiescent supply current of less
than 40 μA. To maintain ultra-high input impedance, it is advisable to use ground rings and consider PC board
layout an important part of the overall system design (see PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGHIMPEDANCE WORK). Referring to Figure 35, the input voltages are represented as a common-mode input VCM
plus a differential input VD. Rejection of the common-mode component of the input is accomplished by making
the ratio of R1/R2 equal to R3/R4. So that where,
(3)
A suggested design guideline is to minimize the difference of value between R1 through R4. This will often result
in improved resistor tempco, amplifier gain, and CMRR over temperature. If RN = R1 = R2 = R3 = R4 then the
gain equation can be simplified:
(4)
Due to the “zero-in, zero-out” performance of the LMC6044, and output swing rail-rail, the dynamic range is only
limited to the input common-mode range of 0V to VS–2.3V, worst case at room temperature. This feature of the
LMC6044 makes it an ideal choice for low-power instrumentation systems.
A complete instrumentation amplifier designed for a gain of 100 is shown in Figure 36. Provisions have been
made for low sensitivity trimming of CMRR and gain.
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(V+ = 5.0 VDC)
Figure 35. Two Op-Amp Instrumentation Amplifier
Figure 36. Low-Power Two-Op-Amp Instrumentation Amplifier
Figure 37. Low-Leakage Sample-and-Hold
Figure 38. Instrumentation Amplifier
14
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(V+ = 5.0 VDC)
Figure 39. 1 Hz Square-Wave Oscillator
Figure 40. AC Coupled Power Amplifier
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Aug-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMC6044-MDC
ACTIVE
DIESALE
Y
0
100
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-40 to 85
LMC6044AIM
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
-40 to 85
LMC6044
AIM
LMC6044AIM/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC6044
AIM
LMC6044AIMX
NRND
SOIC
D
14
TBD
Call TI
Call TI
-40 to 85
LMC6044
AIM
LMC6044AIMX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC6044
AIM
LMC6044IM
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
-40 to 85
LMC6044IM
LMC6044IM/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC6044IM
LMC6044IMX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC6044IM
LMC6044IN/NOPB
ACTIVE
PDIP
NFF
14
25
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
-40 to 85
LMC6044IN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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(4)
10-Aug-2016
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
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(6)
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMC6044AIMX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LMC6044IMX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMC6044AIMX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LMC6044IMX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NFF0014A
N0014A
N14A (Rev G)
www.ti.com
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