LPC661AIMX

National Semiconductor is now part of Texas Instruments. Search http://www.ti.com/ for the latest technical information and details on our current products and services. LPC661 Low Power CMOS Operational Amplifier General Description The LPC661 CMOS operational amplifier is ideal for operation from a single supply. It features a wide range of operating supply voltage from +5V to +15V, rail-to-rail output swing and an input common-mode range that includes ground. Performance limitations that have plagued CMOS amplifiers in the past are not a problem with this design. Input VOS, drift, and broadband noise as well as voltage gain (into 100 kΩ and 5 kΩ) are all equal to or better than widely accepted bipolar equivalents, while the supply current requirement is typically 55 µA. This chip is built with National’s advanced Double-Poly Silicon-Gate CMOS process. See the LPC660 datasheet for a Quad CMOS operational amplifier or the LPC662 data sheet for a Dual CMOS operational amplifier with these same features. Features (Typical unless otherwise noted) n Rail-to-rail output swing n n n n n n n n n n Low supply current 55 µA Specified for 100 kΩ and 5 kΩ loads High voltage gain 120 dB Low input offset voltage 3 mV Low offset voltage drift 1.3 µV/˚C Ultra low input bias current 2 fA Input common-mode range includes GND Operating range from +5V to +15V Low distortion 0.01% at 1 kHz Slew rate 0.11 V/µs Applications n n n n n n n High-impedance buffer Precision current-to-voltage converter Long-term integrator High-impedance preamplifier Active filter Sample-and-Hold circuit Peak detector Application Circuits 10 Hz Bandpass Filter 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only) DS011227-21 fO = 10 Hz Q = 2.1 Gain = 18.9 dB © 2000 National Semiconductor Corporation DS011227-23 DS011227 www.national.com LPC661 Low Power CMOS Operational Amplifier August 2000 LPC661 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V+ − V−) Differential Input Voltage Output Short Circuit to V+ Output Short Circuit to V− Storage Temperature Range Lead Temperature (Soldering, 10 sec.) Junction Temperature (Note 3) Power Dissipation ESD Rating (C=100 pF, R=1.5 kΩ) Current at Input Pin ± 18 mA (V+) +0.3V, (V−) −0.3V 35 mA Current at Output Pin Voltage Input/Output Pin Current at Power Supply Pin Operating Ratings (Note 1) 16V ± Supply Voltage (Notes 2, 9) (Note 2) −65˚C to +150˚C Supply Voltage Junction Temperature Range LPC661AM LPC661AI LPC661I Power Dissipation Thermal Resistance (θJA) (Note 8) 8-Pin DIP 8-Pin SO 260˚C 150˚C (Note 3) 4.75V ≤ V+ ≤ 15.5V −55˚C ≤ TJ ≤ +125˚C −40˚C ≤ TJ ≤ +85˚C −40˚C ≤ TJ ≤ +85˚C (Note 7) 101˚C/W 165˚C/W 1000V ± 5 mA DC Electrical Characteristics The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25˚C. Symbol VOS TCVOS Parameter Conditions Typ Input Offset Voltage LPC661AM LPC661AI LPC661I Limit Limit Limit (Note 4) (Note 4) (Note 4) 1 Input Offset Voltage 3 3 6 3.5 3.3 6.3 1.3 Units (Limit) mV µV/˚C Average Drift IB Input Bias Current 0.002 20 pA 100 IOS Input Offset Current 0.001 4 20 Input Resistance CMRR Common Mode +PSRR 83 Rejection Ratio V = 15V 5V ≤ V+ ≤ 15V 70 63 dB 68 68 61 min 70 70 63 dB 68 68 61 min 94 84 84 74 dB 82 83 73 min −0.4 −0.1 −0.1 −0.1 V 0 0 0 max V+ − 2.3 V+ − 2.3 V+ − 2.3 V V+ − 2.5 min 83 0V ≤ V− ≤ −10V Rejection Ratio VCM Input Common Mode V+ = 5V and 15V Voltage Range for CMRR ≥ 50 dB V+ − 1.9 + V − 2.6 AV Large Signal Sourcing Voltage Gain RL = 100 kΩ (Note 5) 1000 Sinking 400 300 V/mV 300 200 min 180 180 90 V/mV 70 120 70 min 1000 200 200 100 V/mV 150 160 80 min 250 100 100 50 V/mV 35 60 40 min RL = 5 kΩ (Note 5) RL = 5 kΩ (Note 5) www.national.com 2 V − 2.5 400 500 Sinking + 250 RL = 100 kΩ (Note 5) Sourcing max 70 + Positive Power Supply Negative Power Supply 2 Tera Ω Rejection Ratio −PSRR 2 >1 0V ≤ VCM ≤ 12.0V max pA 100 RIN 4 (Continued) The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25˚C. Symbol VO Parameter Output Swing Conditions LPC661AM LPC661AI LPC661I Limit Limit Limit (Note 4) (Note 4) (Note 4) 4.970 4.970 4.940 V 4.950 4.950 4.910 min 0.004 0.030 0.030 0.060 V 0.050 0.050 0.090 max 4.940 4.850 4.850 4.750 V 4.750 4.750 4.650 min 0.040 0.150 0.150 0.250 V 0.250 0.250 0.350 max 14.970 14.920 14.920 14.880 V 14.880 14.880 14.820 min 0.030 0.030 0.060 V 0.050 0.050 0.090 max 14.680 14.680 14.580 V 14.600 14.600 14.480 min 0.220 0.220 0.320 V 0.300 0.300 0.400 max 16 16 13 mA 12 14 11 min 16 16 13 mA 12 14 11 min 19 28 23 mA 19 25 20 min 19 28 23 mA 19 24 19 min 60 60 70 µA 70 70 85 max 75 75 90 µA 85 85 105 max Typ + V = 5V 4.987 RL = 100 kΩ to 2.5V V+ = 5V RL = 5 kΩ to 2.5V V+ = 15V RL = 100 kΩ to 7.5V 0.007 V+ = 15V 14.840 RL = 5 kΩ to 7.5V 0.110 IO Output Current Sourcing, VO = 0V 22 Sinking, VO = 5V 21 + V = 5V IO Output Current Sourcing, VO = 0V 40 Sinking, VO = 13V 39 + V = 15V (Note 9) IS Supply Current V+ = 5V, VO = 1.5V 55 V+ = 15V, VO = 1.5V 58 Units (Limit) AC Electrical Characteristics The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25˚C. LPC661AM LPC661AI Symbol SR Parameter Slew Rate Conditions Typ (Note 6) 0.11 LPC661I Units (Limit) Limit Limit Limit (Note 4) (Note 4) (Note 4) 0.07 0.07 0.05 V/µs 0.04 0.05 0.03 min GBW Gain-Bandwidth Product 350 kHz φm Phase Margin 50 Deg GM Gain Margin en Input Referred Voltage Noise 17 dB F = 1 kHz 42 nV/√Hz 0.0002 pA/√Hz in Input Referred Current Noise F = 1 kHz T.H.D. Total Harmonic Distortion F = 1 kHz, AV = −10 0.01 RL = 100 kΩ, VO = 8 VPP % + V = 15V 3 www.national.com LPC661 DC Electrical Characteristics LPC661 AC Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of ± 30 mA over long term may adversely affect reliability. Note 3: The maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max)–TA)/θJA. Note 4: Limits are guaranteed by testing or correlation. Note 5: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For sourcing tests, 7.5V ≤ VO ≤ 11.5V. For sinking tests, 2.5V ≤ VO ≤ 7.5V. Note 6: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Note 7: For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA. Note 8: All numbers apply for packages soldered directly into a PC board. Note 9: Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. Typical Performance Characteristics VS = ± 7.5V, TA = 25˚C unless otherwise specified Supply Current vs Supply Voltage Input Bias Current vs Temperature DS011227-26 Common-Mode Voltage Range vs Temperature DS011227-27 Output Characteristics Current Sinking DS011227-28 www.national.com DS011227-29 4 VS = ± 7.5V, TA = 25˚C unless otherwise specified (Continued) Output Characteristics Current Sourcing Input Voltage Noise vs Frequency DS011227-30 CMRR vs Frequency DS011227-31 CMRR vs Temperature DS011227-32 Power Supply Rejection Ratio vs Frequency DS011227-33 Open-Loop Voltage Gain vs Temperature DS011227-35 DS011227-34 5 www.national.com LPC661 Typical Performance Characteristics LPC661 Typical Performance Characteristics VS = ± 7.5V, TA = 25˚C unless otherwise specified (Continued) Open-Loop Frequency Response Gain and Phase Responses vs Load Capacitance DS011227-36 DS011227-37 Gain and Phase Responses vs Temperature Gain Error (VOSvs VOUT) DS011227-38 Non-Inverting Slew Rate vs Temperature DS011227-39 Inverting Slew Rate vs Temperature DS011227-40 www.national.com DS011227-41 6 VS = ± 7.5V, TA = 25˚C unless otherwise specified (Continued) Large-Signal Pulse Non-Inverting Response (AV = +1) Non-Inverting Small Signal Pulse Response (AV = +1) DS011227-42 Inverting Large-Signal Pulse Response DS011227-43 Inverting Small-Signal Pulse Response DS011227-44 DS011227-45 7 www.national.com LPC661 Typical Performance Characteristics LPC661 Typical Performance Characteristics VS = ± 7.5V, TA = 25˚C unless otherwise specified (Continued) Stability vs Capacitive Load Stability vs Capacitive Load DS011227-4 DS011227-5 Note: Avoid resistive loads of less than 500Ω, as they may cause instability. Application Hints ing load resistance of 5 kΩ or less, the gain will be reduced as indicated in the Electrical Characteristics. The op amp can drive load resistance as low as 500Ω without instability. AMPLIFIER TOPOLOGY The topology chosen for the LPC661 is unconventional (compared to general-purpose op amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now fall to the integrator. As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain stages with two fed forward. COMPENSATING INPUT CAPACITANCE Refer to the LMC660 or LMC662 datasheets to determine whether or not a feedback capacitor will be necessary for compensation and what the value of that capacitor would be. CAPACITIVE LOAD TOLERANCE Like many other op amps, the LPC661 may oscillate when its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain follower. See the Typical Performance Characteristics. The load capacitance interacts with the op amp’s output resistance to create an additional pole. If this pole frequency is sufficiently low, it will degrade the op amp’s phase margin so that the amplifier is no longer stable at low gains. The addition of a small resistor (50Ω to 100Ω) in series with the op amp’s output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near the threshold for oscillation. DS011227-6 FIGURE 1. LPC661 Circuit Topology The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, for load resistance of at least 5 kΩ. The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, when drivwww.national.com 8 LPC661 Application Hints (Continued) DS011227-24 FIGURE 3. Compensating for Large Capacitive Loads with A Pull Up Resistor DS011227-7 FIGURE 2. Rx, Cx Improve Capacitive Load Tolerance PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LPC661, typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LPC661’s inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp’s inputs. See Figure 4. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the LPC660’s actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier’s performance. See Figures 5, 6, 7 for typical connections of guard rings for standard op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide some protection; see Figure 8. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 3). Typically a pull up resistor conducting 50 µA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). 9 www.national.com LPC661 Application Hints (Continued) DS011227-8 FIGURE 4. Example of Guard Ring in P.C. Board Layout, Using the LPC660 DS011227-9 FIGURE 5. Inverting Amplifier Guard Ring Connections DS011227-12 FIGURE 8. Howland Current Pump Guard Ring Connections The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don’t insert the amplifier’s input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 9. DS011227-10 FIGURE 6. Non-Inverting Amplifier Guard Ring Connections DS011227-11 FIGURE 7. Follower Guard Ring Connections www.national.com 10 LPC661 Application Hints (Continued) DS011227-13 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.) DS011227-14 FIGURE 9. Air Wiring FIGURE 10. Simple Input Bias Current Test Circuit BIAS CURRENT TESTING The test method of Figure 10 is appropriate for bench-testing bias current with reasonable accuracy. To understand its operation, first close switch S2 momentarily. When S2 is opened, then A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When determining the magnitude of I−, the leakage of the capacitor and socket must be taken into account. Switch S2 should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors. Similarly, if S1 is shorted momentarily (while leaving S2 shorted) where Cx is the stray capacitance at the + input. Typical Single-Supply Applications (V+ = 5.0 VDC) Photodiode Current-toVoltage Converter Micropower Current Source DS011227-16 DS011227-15 Note: A 5V bias on the photodiode can cut its capacitance by a factor of 2 or 3, leading to improved response and lower noise. However, this bias on the photodiode will cause photodiode leakage (also known as its dark current). (Upper limit of output range dictated by input common-mode range; lower limit dictated by minimum current requirement of LM385.) 11 www.national.com LPC661 Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued) Low-Leakage Sample-and-Hold DS011227-17 Sine-Wave Oscillator DS011227-18 Oscillator frequency is determined by R1, R2, C1, and C2: fOSC = 1/2πRC where R = R1 = R2 and C = C1 = C2. This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V 1 Hz Square-Wave Oscillator Power Amplifier DS011227-20 DS011227-19 www.national.com 12 LPC661 Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued) 10 Hz Bandpass Filter 10 Hz High-Pass Filter (2 dB Dip) DS011227-22 DS011227-21 fO = 10 Hz Q = 2.1 Gain = 18.9 dB fc = 10 Hz d = 0.895 Gain = 1 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only) DS011227-23 Connection Diagram 8-Pin DIP/SO DS011227-1 Ordering Information Package Temperature Range Military −55˚C to +125˚C 8-Pin Molded DIP NSC Drawing Transport Media M08A Tape and Reel N08E Rail −40˚C to +85˚C LPC661AIM Small Outline 8-Pin Industrial LPC661IM LPC661AMN LPC661AIN Rail LPC661IN 13 www.national.com LPC661 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin Small Outline Molded Package (M) Order Number LPC661AIM or LPC661IM NS Package Number M08A 8-Pin Molded Dual-In-Line Package (N) Order Number LPC661AIN, LPC661IN or LPC661AMN NS Package Number N08E www.national.com 14 LPC661 Low Power CMOS Operational Amplifier Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.