NN325-Q1
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Multisensing Touch Manager
FEATURES
1
•
•
•
2
•
•
•
•
•
•
•
Qualified for Automotive Applications
Low Supply Voltage Range: 1.8 V to 3.6 V
Ultra-Low-Power Consumption
– Active Mode: 270 µA at 1 MHz, 2.2 V
– Standby Mode: 0.7 µA
– Off Mode (RAM Retention): 0.1 µA
Ultra-Fast Wakeup From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
– Internal Very-Low-Power Low-Frequency
Oscillator
– 32-kHz Crystal
– High-Frequency (HF) Crystal up to 16 MHz
– Resonator
– External Digital Clock Source
– External Resistor
16-Bit Timer_A With Three Capture/Compare
Registers
16-Bit Timer_B With Three Capture/Compare
Registers
Universal Serial Communication Interface
(USCI)
– Enhanced UART With Auto-Baudrate
Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C
10-Bit 200-ksps Analog-to-Digital Converter
(ADC) With Internal Reference, Sample-andHold, Autoscan, and Data Transfer Controller
•
•
•
•
•
•
•
Brownout Detector
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
Bootstrap Loader (BSL)
On-Chip Emulation Module
Family Members Include:
– NN325
– 32KB + 256B Flash Memory
– 1KB RAM
Available in a 40-Pin QFN Package (RHA)
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide (SLAU144)
APPLICATIONS
•
Optical Touch Screen
DESCRIPTION
The NN325 device is an ultra-low-power multisensing
touch manager that includes optimized peripherals
dedicated for high-performance touch-sensing
applications. The device is optimized for ultra-low
power operation using five low-power modes. The
embedded powerful 16-bit RISC core based on a
MSP430™ architecture offers 16-bit registers and
constant generators to achieve maximum code
efficiency. The digitally controlled oscillator (DCO)
allows wakeup from low-power modes to active mode
in less than 1 µs. The ultra-low-power core comes
together with two built-in 16-bit timers, a universal
serial communication interface (USCI), a 10-bit ADC
with integrated reference and data transfer controller
(DTC), and 32 I/O pins.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
NN325-Q1
SLAS824 – DECEMBER 2013
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Functional Block Diagram
VCC
P1.x/P2.x
VSS
2x8
P3.x/P4.x
2x8
XOUT
XIN
Basic Clock
System+
ADC10
10-Bit
ACLK
Flash
RAM
32kB
1kB
SMCLK
MCLK
16MHz
CPU
incl. 16
Registers
Ports P1/P2
Ports P3/P4
2x8 I/O
Interrupt
capability,
pullup/down
resistors
12
Channels,
Autoscan,
DTC
2x8 I/O
pullup/down
resistors
MAB
MDB
Emulation
(2BP)
JTAG
Interface
Timer_B3
Brownout
Protection
Watchdog
WDT+
15/16−Bit
Timer_A3
3 CC
Registers
Spy−Bi Wire
3 CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
RST/NMI
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Device Pinout
P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI
TEST/SBWTCK
DVCC
DVCC
P2.5/ROSC
RHA PACKAGE
(TOP VIEW)
39 38 37 36 35 34 33 32
DVSS
1
30
P1.1/TA0
XOUT/P2.7
2
29
P1.0/TACLK/ADC10CLK
XIN/P2.6
3
28
P2.4/TA2/A4/VREF+/VeREF+
DVSS
4
27
P2.3/TA1/A3/VREF−/VeREF−
RST/NMI/SBWTDIO
5
26
P3.7/A7
P2.0/ACLK/A0
6
25
P3.6/A6
P2.1/TAINCLK/SMCLK/A1
7
24
P3.5/UCA0RXD/UCA0SOMI
P2.2/TA0/A2
8
23
P3.4/UCA0TXD/UCA0SIMO
P3.0/UCB0STE/UCA0CLK/A5
9
22
P4.7/TBCLK
21
P4.6/TBOUTH/A15
P3.1/UCB0SIMO/UCB0SDA
10
P4.5/TB2/A14
P4.4/TB1/A13
P4.3/TB0/A12
P4.2/TB2
P4.1/TB1
P4.0/TB0
AVCC
AVSS
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
12 13 14 15 16 17 18 19
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Table 1. Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
RHA
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK
29
I/O
Timer_A, clock signal TACLK input
ADC10, conversion clock
General-purpose digital I/O pin
P1.1/TA0
30
I/O
Timer_A, capture: CCI0A input, compare: OUT0 output
BSL transmit
P1.2/TA1
31
I/O
P1.3/TA2
32
I/O
P1.4/SMCLK/TCK
33
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin
P1.5/TA0/TMS
34
I/O
Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin
P1.6/TA1/TDI/TCLK
35
I/O
Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin
P1.7/TA2/TDO/TDI (1)
36
I/O
Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin
P2.0/ACLK/A0
6
I/O
ACLK output
ADC10, analog input A0
General-purpose digital I/O pin
Timer_A, clock signal at INCLK
P2.1/TAINCLK/SMCLK/A1
7
I/O
SMCLK signal output
ADC10, analog input A1
General-purpose digital I/O pin
Timer_A, capture: CCI0B input, compare: OUT0 output
P2.2/TA0/A2
8
I/O
BSL receive
ADC10, analog input A2
General-purpose digital I/O pin
Timer_A, capture CCI1B input, compare: OUT1 output
P2.3/TA1/A3/ VREF-/VeREF-
27
I/O
ADC10, analog input A3
Negative reference voltage output/input
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
P2.4/TA2/A4/ VREF+/VeREF+
28
I/O
ADC10, analog input A4
Positive reference voltage output/input
(1)
4
TDO or TDI is selected via JTAG instruction.
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Table 1. Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
RHA
P2.5/ROSC
40
I/O
XIN/P2.6
3
I/O
XOUT/P2.7
2
I/O
General-purpose digital I/O pin
Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
General-purpose digital I/O pin
Output terminal of crystal oscillator
General-purpose digital I/O pin (2)
General-purpose digital I/O pin
P3.0/UCB0STE/UCA0CLK/A5
9
I/O
USCI_B0 slave transmit enable
USCI_A0 clock input/output
ADC10, analog input A5
General-purpose digital I/O pin
P3.1/UCB0SIMO/UCB0SDA
10
I/O
USCI_B0 slave in, master out (SPI mode)
USCI_B0 SDA I2C data (I2C mode)
General-purpose digital I/O pin
P3.2/UCB0SOMI/UCB0SCL
11
I/O
USCI_B0 slave out, master in (SPI mode)
USCI_B0 SCL I2C clock (I2C mode)
General-purpose digital I/O pin
P3.3/UCB0CLK/UCA0STE
12
I/O
USCI_B0 clock input/output
USCI_A0 slave transmit enable
General-purpose digital I/O pin
P3.4/UCA0TXD/UCA0SIMO
23
I/O
USCI_A0 transmit data output (UART mode)
USCI_A0 slave in, master out (SPI mode)
General-purpose digital I/O pin
P3.5/UCA0RXD/UCA0SOMI
24
I/O
USCI_A0 receive data input in UART mode
USCI_A0 slave out/master in SPI mode
General-purpose digital I/O pin
P3.6/A6
25
I/O
P3.7/A7
26
I/O
P4.0/TB0
15
I/O
P4.1/TB1
16
I/O
P4.2/TB2
17
I/O
P4.3/TB0/A12
18
I/O
ADC10 analog input A6
General-purpose digital I/O pin
ADC10 analog input A7
General-purpose digital I/O pin
Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
General-purpose digital I/O pin
P4.4/TB1/A13
19
I/O
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
(2)
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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Table 1. Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
RHA
General-purpose digital I/O pin
P4.5/TB2/A14
20
I/O
Timer_B, compare: OUT2 output
ADC10 analog input A14
General-purpose digital I/O pin
P4.6/TBOUTH/A15
21
I/O
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
P4.7/TBCLK
22
I/O
RST/NMI/SBWTDIO
5
I
TEST/SBWTCK
37
I
General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to
TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC
38, 39
Digital supply voltage
AVCC
14
Analog supply voltage
DVSS
1, 4
Digital ground reference
AVSS
13
QFN Pad
6
Pad
Analog ground reference
NA
QFN package pad; connection to DVSS recommended.
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Short-Form Description
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
Instruction Set
General-Purpose Register
R11
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 2 shows examples of the three types of
instruction formats; Table 3 shows the address
modes.
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
Table 2. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
INSTRUCTION FORMAT
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, unconditional/conditional
Table 3. Address Mode Descriptions
ADDRESS MODE
D
(2)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) → M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) → M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
(1)
(2)
S
(1)
OPERATION
S = source
D = destination
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Operating Modes
The NN325-Q1 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active. MCLK is disabled.
• Low-power mode 1 (LPM1)
– CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.
– DCO dc-generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator remains enabled.
– ACLK remains active.
• Low-power mode 3 (LPM3)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– ACLK remains active.
• Low-power mode 4 (LPM4)
– CPU is disabled.
– ACLK is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– Crystal oscillator is stopped.
8
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 4. Interrupt Vector Addresses
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
Timer_B3
TBCCR0 CCIFG (4)
maskable
0FFFAh
29
Timer_B3
TBCCR1 and TBCCR2 CCIFGs,
TBIFG (2) (4)
maskable
0FFF8h
28
0FFF6h
27
Watchdog Timer
WDTIFG
maskable
0FFF4h
26
Timer_A3
TACCR0 CCIFG (see Note 3)
maskable
0FFF2h
25
Timer_A3
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG (2) (4)
maskable
0FFF0h
24
USCI_A0/USCI_B0 Receive
UCA0RXIFG, UCB0RXIFG (2)
maskable
0FFEEh
23
USCI_A0/USCI_B0 Transmit
UCA0TXIFG, UCB0TXIFG (2)
maskable
0FFECh
22
ADC10
ADC10IFG (4)
maskable
0FFEAh
21
0FFE8h
20
(1)
(2)
(3)
(4)
(5)
(6)
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7
(2) (4)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7 (2) (4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
(5)
0FFDEh
15
(6)
0FFDCh to 0FFC0h
14 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
Interrupt flags are located in the module.
This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw
rw-0, 1
rw-(0), (1)
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 5. Interrupt Enable 1
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
Table 6. Interrupt Enable 2
Address
7
6
5
4
01h
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
USCI_A0 receive-interrupt enable
USCI_A0 transmit-interrupt enable
USCI_B0 receive-interrupt enable
USCI_B0 transmit-interrupt enable
Table 7. Interrupt Flag Register 1
Address
7
6
5
02h
WDTIFG
OFIFG
RSTIFG
PORIFG
NMIIFG
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
Power-on reset interrupt flag. Set on VCC power up.
Set via RST/NMI pin
Table 8. Interrupt Flag Register 2
Address
7
6
03h
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
10
5
4
3
2
1
0
UCB0TXIFG
UCB0RXIFG
UCA0TXIFG
UCA0RXIFG
rw-1
rw-0
rw-1
rw-0
USCI_A0 receive-interrupt flag
USCI_A0 transmit-interrupt flag
USCI_B0 receive-interrupt flag
USCI_B0 transmit-interrupt flag
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Memory Organization
Table 9. Memory Organization
NN325
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB Flash
0FFFFh-0FFC0h
0FFFFh-08000h
Information memory
Size
Flash
256 Byte
010FFh-01000h
Boot memory
Size
ROM
1KB
0FFFh-0C00h
Size
1KB
05FFh-0200h
16-bit
8-bit
8-bit SFR
01FFh-0100h
0FFh-010h
0Fh-00h
RAM
Peripherals
Bootstrap Loader (BSL)
The bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface.
Access to the NN325-Q1 memory via the BSL is protected by user-defined password. For complete description
of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader
User’s Guide (SLAU319).
Table 10. BSL Function Pins
BSL FUNCTION
RHA PACKAGE PINS
Data transmit
30 - P1.1
Data receive
8 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and
a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in
less than 1 µs. The basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal verylow-power LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 11. DCO Calibration Data
(Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY
1 MHz
8 MHz
12 MHz
16 MHz
CALIBRATION REGISTER
SIZE
ADDRESS
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
CALBC1_8MHZ
byte
010FDh
CALDCO_8MHZ
byte
010FCh
CALBC1_12MHZ
byte
010FBh
CALDCO_12MHZ
byte
010FAh
CALBC1_16MHZ
byte
010F9h
CALDCO_16MHZ
byte
010F8h
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and
write data is ignored.
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
12
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. Timer_A3 Signal Connections
INPUT PIN NUMBER
RHA
29 - P1.0
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE BLOCK
MODULE OUTPUT
SIGNAL
TACLK
TACLK
Timer
NA
ACLK
ACLK
CCR0
TA0
OUTPUT PIN
NUMBER
RHA
SMCLK
SMCLK
7 - P2.1
TAINCLK
INCLK
30 - P1.1
TA0
CCI0A
8 - P2.2
TA0
CCI0B
8 - P2.2
VSS
GND
34 - P1.5
30 - P1.1
VCC
VCC
31 - P1.2
TA1
CCI1A
27 - P2.3
TA1
CCI1B
27 - P2.3
VSS
GND
35 - P1.6
VCC
VCC
32 - P1.3
CCR1
CCR2
TA1
TA2
31 - P1.2
TA2
CCI2A
ACLK (internal)
CCI2B
32 - P1.3
28 - P2.4
VSS
GND
36 - P1.7
VCC
VCC
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Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 13. Timer_B3 Signal Connections
INPUT PIN NUMBER
RHA
22 - P4.7
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE BLOCK
MODULE OUTPUT
SIGNAL
TBCLK
TBCLK
Timer
NA
ACLK
ACLK
CCR0
TB0
SMCLK
SMCLK
22 - P4.7
TBCLK
INCLK
15 - P4.0
TB0
CCI0A
18 - P4.3
TB0
CCI0B
VSS
GND
VCC
VCC
16 - P4.1
TB1
CCI1A
19 - P4.4
TB1
CCI1B
VSS
GND
VCC
VCC
17 - P4.2
TB2
CCI2A
ACLK (internal)
CCI2B
VSS
GND
VCC
VCC
OUTPUT PIN
NUMBER
RHA
15 - P4.0
18 - P4.3
CCR1
TB1
16 - P4.1
19 - P4.4
CCR2
TB2
17 - P4.2
20 - P4.5
Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.
14
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Peripheral File Map
Table 14. Peripherals With Word Access
MODULE
ADC10
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
ADC10SA
1BCh
ADC memory
ADC10MEM
1B4h
ADC control register 1
ADC10CTL1
1B2h
ADC control register 0
ADC10CTL0
1B0h
ADC analog enable 0
ADC10AE0
04Ah
ADC data transfer start address
ADC analog enable 1
Timer_B
ADC10AE1
04Bh
ADC data transfer control register 1
ADC10DTC1
049h
ADC data transfer control register 0
ADC10DTC0
048h
Capture/compare register
TBCCR2
0196h
Capture/compare register
TBCCR1
0194h
Capture/compare register
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control
TBCCTL2
0186h
Capture/compare control
TBCCTL1
0184h
Capture/compare control
TBCCTL0
0182h
Timer_B control
Timer_A
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Capture/compare register
TACCR2
0176h
Capture/compare register
TACCR1
0174h
Capture/compare register
TACCR0
0172h
TAR
0170h
Capture/compare control
TACCTL2
0166h
Capture/compare control
TACCTL1
0164h
Capture/compare control
TACCTL0
0162h
TACTL
0160h
Timer_A register
Timer_A control
Timer_A interrupt vector
Flash Memory
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
FCTL1
0128h
WDTCTL
0120h
Flash control 1
Watchdog Timer+
Watchdog/timer control
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Table 15. Peripherals With Byte Access
MODULE
USCI_B0
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
USCI_B0 transmit buffer
UCB0TXBUF
06Fh
USCI_B0 receive buffer
UCB0RXBUF
06Eh
UCB0STAT
06Dh
UCB0BR1
06Bh
USCI_B0 bit rate control 0
UCB0BR0
06Ah
USCI_B0 control 1
UCB0CTL1
069h
USCI_B0 control 0
UCB0CTL0
068h
USCI_B0 I2C slave address
UCB0SA
011Ah
USCI_B0 I2C own address
UCB0OA
0118h
USCI_A0 transmit buffer
UCA0TXBUF
067h
USCI_A0 receive buffer
UCA0RXBUF
066h
USCI_A0 status
UCA0STAT
065h
USCI_A0 modulation control
UCA0MCTL
064h
USCI_A0 baud rate control 1
UCA0BR1
063h
USCI_A0 baud rate control 0
UCA0BR0
062h
USCI_A0 control 1
UCA0CTL1
061h
USCI_A0 control 0
UCA0CTL0
060h
USCI_B0 status
USCI_B0 bit rate control 1
USCI_A0
Basic Clock System+
Port P4
USCI_A0 IrDA receive control
UCA0IRRCTL
05Fh
USCI_A0 IrDA transmit control
UCA0IRTCTL
05Eh
USCI_A0 auto baud rate control
UCA0ABCTL
05Dh
Basic clock system control 3
BCSCTL3
053h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P4 resistor enable
P4REN
011h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
P4IN
01Ch
Port P4 input
Port P3
Port P3 resistor enable
P3REN
010h
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
P3IN
018h
Port P3 input
Port P2
Port P2 resistor enable
P2REN
02Fh
Port P2 selection
P2SEL
02Eh
P2IE
02Dh
Port P2 interrupt edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
P2IN
028h
Port P2 interrupt enable
Port P2 input
16
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Table 15. Peripherals With Byte Access (continued)
MODULE
Port P1
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
Port P1 resistor enable
P1REN
027h
Port P1 selection
P1SEL
026h
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
Port P1 interrupt enable
Special Function
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
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Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
Voltage applied to any pin
-0.3 V to 4.1 V
(2)
-0.3 V to VCC + 0.3 V
Diode current at any device terminal
Storage temperature, Tstg
(1)
±2 mA
(3)
Unprogrammed device
-55°C to 150°C
Programmed device
-55°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
(3)
Recommended Operating Conditions (1) (2)
MIN
VCC
Supply voltage
Supply voltage
TA
Operating free-air temperature
fSYSTEM
Processor frequency
(maximum MCLK frequency) (1) (2)
(see Figure 1)
(1)
(2)
MAX
UNIT
During program
execution
1.8
3.6
V
During program/erase
flash memory
2.2
3.6
V
T version
-40
105
°C
VCC = 1.8 V, Duty cycle = 50% ±10%
dc
4.15
VCC = 2.7 V, Duty cycle = 50% ±10%
dc
12
VCC ≥ 3.3 V, Duty cycle = 50% ±10%
dc
16
AVCC = DVCC = VCC
VSS
NOM
AVSS = DVSS = VSS
0
V
MHz
The CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified
maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency −MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage −V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Operating Area
18
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Active Mode Supply Current (into DVCC + AVCC) Excluding External Current
(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IAM,1MHz
IAM,1MHz
IAM,4kHz
IAM,100kHz
TEST CONDITIONS
TA
MIN
TYP
MAX
2.2 V
270
390
Active mode (AM)
current (1 MHz)
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
3V
390
550
2.2 V
240
Active mode (AM)
current (1 MHz)
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
3.3 V
340
Active mode (AM)
current (4 kHz)
fMCLK = fSMCLK = fACLK = 32768 Hz/8 =
4096 Hz,
fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current (100 kHz)
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0, CPUOFF = 0,
SCG0 = 0, SCG1 = 0, OSCOFF = 1
-40°C to
85°C
2.2 V
5
105°C
-40°C to
85°C
-40°C to
85°C
µA
µA
9
µA
6
10
3V
20
2.2 V
60
105°C
-40°C to
85°C
UNIT
18
105°C
105°C
(1)
(2)
VCC
85
95
3V
72
µA
95
105
All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
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Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC)
ACTIVE-MODE CURRENT
vs
SUPPLY VOLTAGE
TA = 25°C
ACTIVE-MODE CURRENT
vs
DCO FREQUENCY
8.0
5.0
f DCO = 16 MHz
7.0
TA = 85 °C
Active Mode Current − mA
Active Mode Current − mA
4.0
6.0
f DCO = 12 MHz
5.0
4.0
f DCO = 8 MHz
3.0
2.0
TA = 25 °C
3.0
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
1.0
0.0
1.5
VCC = 2.2 V
f DCO = 1 MHz
2.0
2.5
3.0
3.5
4.0
0.0
0.0
VCC − Supply Voltage − V
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 2.
20
4.0
Figure 3.
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Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current
(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ILPM0,1MHz
ILPM0,100kHz
ILPM2
ILPM3,LFXT1
TEST CONDITIONS
TA
(1)
(2)
(3)
(4)
(5)
TYP
MAX
2.2 V
75
90
Low-power mode 0
(LPM0) current (3)
3V
90
120
2.2 V
37
48
Low-power mode 0
(LPM0) current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 1
3V
41
65
22
29
Low-power mode 2
(LPM2) current (4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
Low-power mode 3
(LPM3) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
-40°C to
85°C
Low-power mode 3
current, (LPM3) (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator
(VLO),
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
Low-power mode 4
(LPM4) current (5)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
2.2 V
105°C
-40°C to
85°C
31
3V
25
105°C
0.7
1.4
0.7
1.4
2.4
3.3
105°C
5
10
-40°C
0.9
1.5
0.9
1.5
2.6
3.8
105°C
6
12
-40°C
0.4
1
25°C
0.5
1
1.8
2.9
25°C
85°C
2.2 V
3V
2.2 V
105°C
4.5
9
-40°C
0.5
1.2
0.6
1.2
2.1
3.3
25°C
3V
105°C
5.5
11
-40°C
0.1
0.5
0.1
0.5
1.5
3
4.5
9
25°C
85°C
105°C
µA
µA
µA
34
25°C
85°C
UNIT
32
-40°C
85°C
ILPM4
MIN
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
85°C
ILPM3,VLO
VCC
2.2 V,
3V
µA
µA
µA
All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
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Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIT+
TEST CONDITIONS
Positive-going input threshold voltage
VCC
MIN
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ - VIT- )
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
MAX
0.45 VCC
0.75 VCC
1
1.65
1.35
2.25
0.25 VCC
0.55 VCC
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.1
1
3V
0.3
1
3V
20
2.2 V
3V
VIT-
TYP
35
50
5
UNIT
V
V
V
kΩ
pF
Inputs (Ports P1, P2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
External interrupt timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External trigger
pulse width to set interrupt flag (1)
VCC
2.2 V, 3 V
MIN
TYP
MAX
20
UNIT
ns
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int) .
Leakage Current (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
22
High-impedance leakage current
TEST CONDITIONS
(1) (2)
VCC
2.2 V, 3 V
MIN
TYP
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
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Outputs (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH(max) = -1.5 mA
VOH
High-level output voltage
IOH(max) = -6 mA
(2)
IOH(max) = -1.5 mA (1)
IOH(max) = -6 mA (2)
IOL(max) = 1.5 mA
VOL
Low-level output voltage
(2)
2.2 V
3V
(1)
2.2 V
IOL(max) = 6 mA (2)
IOL(max) = 1.5 mA (1)
IOL(max) = 6 mA (2)
(1)
VCC
(1)
3V
MIN
MAX
VCC - 0.25
VCC
VCC - 0.6
VCC
VCC - 0.25
VCC
VCC - 0.6
VCC
VSS
VSS + 0.25
VSS
VSS + 0.6
VSS
VSS + 0.25
VSS
VSS + 0.6
UNIT
V
V
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency (Ports P1, P2, P3, and P4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency (with load)
P1.4/SMCLK, CL = 20 pF,
RL = 1 kΩ against VCC/2 (1) (2)
fPort_CLK
Clock output frequency
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (2)
(1)
(2)
VCC
MIN
TYP
MAX
2.2 V
10
3V
12
2.2 V
12
3V
16
UNIT
MHz
MHz
Alternatively, a resistive divider with two 2-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap
of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics - Outputs
One output loaded at a time.
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC = 2.2 V
P4.5
TA = 25°C
20.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
25.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P4.5
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
0.5
VOL − Low-Level Output V oltage − V
Figure 4.
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
2.0
2.5
3.0
3.5
0.0
VCC = 2.2 V
P4.5
−5.0
−10.0
−15.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
VCC = 3 V
P4.5
−10.0
−20.0
−30.0
−40.0
−50.0
0.0
VOH − High-Level Output V oltage − V
Figure 6.
24
1.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−25.0
0.0
1.0
VOL − Low-Level Output V oltage − V
Figure 5.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−20.0
TA = 25°C
40.0
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TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output V oltage − V
Figure 7.
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POR/Brownout Reset (BOR)
(1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(start)
See Figure 8
dVCC /dt ≤ 3 V/s
V(B_IT-)
See Figure 8 through Figure 10
dVCC /dt ≤ 3 V/s
Vhys(B_IT-)
See Figure 8
dVCC /dt ≤ 3 V/s
td(BOR)
See Figure 8
t(reset)
Pulse length needed at RST/NMI pin
to accepted reset internally
(1)
(2)
VCC
MIN
TYP
MAX
0.7 ×
V(B_IT-)
70
3V
130
UNIT
V
1.71
V
210
mV
2000
µs
2
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-) is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-) . The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics - POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
t pw − Pulse Width − µs
t pw − Pulse Width − µs
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
1000
tf
tr
t pw − Pulse Width − µs
t pw − Pulse Width − µs
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
26
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Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO .
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
UNIT
VCC
Supply voltage range
3.0
3.6
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V, 3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V, 3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V, 3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V, 3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V, 3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V, 3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V, 3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V, 3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V, 3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V, 3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V, 3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V, 3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V, 3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V, 3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V, 3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V, 3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO)
2.2 V, 3 V
1.55
ratio
SDCO
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO)
2.2 V, 3 V
1.05
1.08
1.12
ratio
Duty cycle
Measured at P1.4/SMCLK
2.2 V, 3 V
40
50
60
RSELx = 15
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Calibrated DCO Frequencies - Tolerance at Calibration
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
-1
±0.2
+1
%
25°C
3V
0.990
1
1.010
MHz
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3V
15.84
16
16.16
MHz
MAX
UNIT
Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
28
TA
VCC
1-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±0.5
+2.5
%
8-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1.0
+2.5
%
12-MHz tolerance over
temperature
0°C to 85°C
3V
-2.5
±1.0
+2.5
%
16-MHz tolerance over
temperature
0°C to 85°C
3V
-3
±2.0
+3
%
2.2 V
0.97
1
1.03
3V
0.975
1
1.025
3.6 V
0.97
1
1.03
2.2 V
7.76
8
8.4
3V
7.8
8
8.2
3.6 V
7.6
8
8.24
2.2 V
11.7
12
12.3
3V
11.7
12
12.3
3.6 V
11.7
12
12.3
3V
15.52
16
16.48
15
16
16.48
1-MHz calibration value
8-MHz calibration value
12-MHz calibration value
16-MHz calibration value
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
0°C to 85°C
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3.6 V
MIN
TYP
MHz
MHz
MHz
MHz
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Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
1-MHz tolerance over VCC
25°C
8-MHz tolerance over VCC
25°C
12-MHz tolerance over VCC
16-MHz tolerance over VCC
UNIT
1.8 V to 3.6 V
-3
±2
+3
%
1.8 V to 3.6 V
-3
±2
+3
%
25°C
2.2 V to 3.6 V
-3
±2
+3
%
25°C
3 V to 3.6 V
-6
±2
+3
%
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
0.97
1
1.03
MHz
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
25°C
1.8 V to 3.6 V
7.76
8
8.24
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
25°C
2.2 V to 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
25°C
3 V to 3.6 V
15
16
16.48
MHz
MIN
TYP
MAX
UNIT
Calibrated DCO Frequencies - Overall Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
1-MHz tolerance
overall
-40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
8-MHz tolerance
overall
-40°C to 105°C
1.8 V to 3.6 V
-5
±2
+5
%
12-MHz
tolerance overall
-40°C to 105°C
2.2 V to 3.6 V
-5
±2
+5
%
16-MHz
tolerance overall
-40°C to 105°C
3 V to 3.6 V
-6
±3
+6
%
fCAL(1MHz)
BCSCTL1 = CALBC1_1MHZ,
1-MHz
DCOCTL = CALDCO_1MHZ,
calibration value
Gating time: 5 ms
-40°C to 105°C
1.8 V to 3.6 V
0.95
1
1.05
MHz
fCAL(8MHz)
BCSCTL1 = CALBC1_8MHZ,
8-MHz
DCOCTL = CALDCO_8MHZ,
calibration value
Gating time: 5 ms
-40°C to 105°C
1.8 V to 3.6 V
7.6
8
8.4
MHz
fCAL(12MHz)
BCSCTL1 = CALBC1_12MHZ,
12-MHz
DCOCTL = CALDCO_12MHZ,
calibration value
Gating time: 5 ms
-40°C to 105°C
2.2 V to 3.6 V
11.4
12
12.6
MHz
fCAL(16MHz)
BCSCTL1 = CALBC1_16MHZ,
16-MHz
DCOCTL = CALDCO_16MHZ,
calibration value
Gating time: 2 ms
-40°C to 105°C
3 V to 3.6 V
15
16
17
MHz
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Typical Characteristics - Calibrated 1-MHz DCO Frequency
CALIBRATED 1-MHz FREQUENCY
vs
TEMPERATURE
CALIBRATED 1-MHz FREQUENCY
vs
SUPPLY VOLTAGE
1.03
1.03
1.02
1.02
Frequency − MHz
1.00
VCC = 2.2 V
VCC = 3.0 V
0.99
Frequency − MHz
VCC = 1.8 V
1.01
TA = 105 °C
1.01
TA = 85 °C
1.00
TA = 25 °C
0.99
TA = −40 °C
VCC = 3.6 V
0.98
0.98
0.97
−50.0
−25.0
0.0
25.0
50.0
75.0
100.0
0.97
1.5
30
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 12.
TA − Temperature − °C
Figure 11.
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Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
tDCO,LPM3/4
BCSCTL1 = CALBC1_8MHZ,
DCO clock wake-up time DCOCTL = CALDCO_8MHZ
from LPM3/4 (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
(1)
(2)
UNIT
2
2.2 V, 3 V
1.5
µs
1
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
tCPU,LPM3/4
MAX
3V
1
CPU wake-up time from
LPM3/4 (2)
1 / fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
CLOCK WAKE-UP TIME FROM LPM3
vs
DCO FREQUENCY
DCO Wake-Up Time − µs
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 13.
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DCO With External Resistor ROSC (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fDCO,ROSC
DCO output frequency with ROSC
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0,
TA = 25°C
DT
Temperature drift
DV
Drift with VCC
(1)
VCC
MIN
TYP
MAX
UNIT
2.2 V
1.8
3V
1.95
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V, 3 V
±0.1
%/°C
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V, 3 V
10
%/V
MHz
ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
Typical Characteristics - DCO With External Resistor ROSC
DCO FREQUENCY
vs
ROSC
VCC = 2.2 V, TA = 25°C
DCO FREQUENCY
vs
ROSC
VCC = 3 V, TA = 25°C
10.00
DCO Frequency − MHz
DCO Frequency − MHz
10.00
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
RSELx = 4
1000.00
10000.00
ROSC − External Resistor − kW
Figure 15.
DCO FREQUENCY
vs
TEMPERATURE
VCC = 3 V
DCO FREQUENCY
vs
SUPPLY VOLTAGE
TA = 25°C
2.50
2.25
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
DCO Frequency − MHz
ROSC = 100k
2.00
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
0.50
ROSC = 1M
0.25
−25.0
0.0
25.0
50.0
75.0
ROSC = 1M
0.25
100.0
0.00
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 17.
TA − Temperature − C
Figure 16.
32
100.00
ROSC − External Resistor − kW
Figure 14.
2.25
DCO Frequency − MHz
0.10
0.01
10.00
10000.00
2.50
0.00
−50.0
1.00
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Crystal Oscillator LFXT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
Integrated effective load
capacitance, LF mode (2)
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
TYP
1.8 V to 3.6 V
1.8 V to 3.6 V
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V, 3 V
30
Oscillator fault frequency,
LF mode (3)
XTS = 0, LFXT1Sx = 3 (4)
2.2 V, 3 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the crystal that is used.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TA
-40°C to 85°C
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift
dfVLO/dVCC
VLO frequency supply voltage drift
(1)
(2)
105°C
(1)
(2)
VCC
2.2 V, 3 V
-40°C to 105°C
2.2 V, 3 V
25°C
1.8 V to 3.6 V
MIN
TYP
MAX
4
12
20
22
UNIT
kHz
0.5
%/°C
4
%/V
Calculated using the box method:
I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
T version: [MAX(-40...105°C) - MIN(-40...105°C)]/MIN(-40...105°C)/[105°C - (-40°C)]
Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
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Crystal Oscillator LFXT1, High-Frequency Mode (1)
PARAMETER
VCC
MIN
XTS = 1, LFXT1Sx = 0
1.8 V to 3.6 V
LFXT1 oscillator crystal
frequency, HF mode 1
XTS = 1, LFXT1Sx = 1
LFXT1 oscillator crystal
frequency, HF mode 2
XTS = 1, LFXT1Sx = 2
fLFXT1,HF0
LFXT1 oscillator crystal
frequency, HF mode 0
fLFXT1,HF1
fLFXT1,HF2
TEST CONDITIONS
MAX
UNIT
0.4
1
MHz
1.8 V to 3.6 V
1
4
MHz
1.8 V to 3.6 V
2
10
2.2 V to 3.6 V
2
12
3 V to 3.6 V
fLFXT1,HF,logic
OAHF
CL,eff
LFXT1 oscillator logic-level
square-wave input frequency, HF XTS = 1, LFXT1Sx = 3
mode
Oscillation allowance for HF
crystals (see Figure 18 and
Figure 19)
Integrated effective load
capacitance, HF mode (2)
Duty cycle, HF mode
fFault,HF
(1)
(2)
(3)
(4)
(5)
34
Oscillator fault frequency (4)
TYP
2
16
1.8 V to 3.6 V
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
XTS = 1, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz,
CL,eff = 15 pF
2700
XTS = 1, LFXT1Sx = 1,
fLFXT1,HF = 4 MHz,
CL,eff = 15 pF
800
XTS = 1, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz,
CL,eff = 15 pF
300
XTS = 1 (3)
XTS = 1,
Measured at P2.0/ACLK,
fLFXT1,HF = 10 MHz
XTS = 1,
Measured at P2.0/ACLK,
fLFXT1,HF = 16 MHz
XTS = 1, LFXT1Sx = 3 (5)
50
pF
60
2.2 V, 3 V
%
40
2.2 V, 3 V
MHz
Ω
1
40
MHz
30
50
60
300
kHz
To improve EMI on the XT1 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
OSCILLATION ALLOWANCE
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
OSCILLATOR SUPPLY CURRENT
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
800.0
100000.00
LFXT1Sx = 3
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 1
LFXT1Sx = 2
XT Oscillator Supply Current − uA
Oscillation Allowance − Ohms
700.0
600.0
500.0
400.0
300.0
LFXT1Sx = 2
200.0
100.0
LFXT1Sx = 1
10.00
0.10
1.00
10.00
100.00
0.0
0.0
Crystal Frequency − MHz
4.0
8.0
12.0
16.0
20.0
Crystal Frequency − MHz
Figure 19.
Figure 18.
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TA0, TA1, TA2
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V, 3 V
20
UNIT
MHz
ns
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B clock frequency
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
tTB,cap
Timer_B capture timing
TB0, TB1, TB2
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V, 3 V
20
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UNIT
MHz
ns
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USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
tτ
UART receive deglitch time (1)
(1)
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2.2 V, 3 V
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
150
600
3V
50
100
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 20 and Figure 21)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
(1)
TEST CONDITIONS
VCC
MIN
TYP
SMCLK, ACLK
Duty cycle = 50% ± 10%
UCLK edge to SIMO valid,
CL = 20 pF
2.2 V
110
3V
75
2.2 V
0
3V
0
MAX
UNIT
fSYSTEM
MHz
ns
ns
2.2 V
30
3V
20
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
USCI (SPI Slave Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 22 and Figure 23)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
tSTE,LEAD
STE lead time, STE low to clock
2.2 V, 3 V
tSTE,LAG
STE lag time, Last clock to STE high
2.2 V, 3 V
tSTE,ACC
STE access time, STE low to SOMI data out
2.2 V, 3 V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
2.2 V, 3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
(1)
36
UCLK edge to SOMI valid,
CL = 20 pF
50
UNIT
ns
10
2.2 V
20
3V
15
2.2 V
10
3V
10
ns
ns
ns
2.2 V
75
110
3V
50
75
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached slave.
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1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 20. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 21. SPI Master Mode, CKPH = 1
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 22. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 23. SPI Slave Mode, CKPH = 1
38
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3 V
0
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
tSU,STO
Setup time for STOP
2.2 V, 3 V
4
µs
tSP
Pulse width of spikes suppressed by input filter
2.2 V
50
150
600
3V
50
100
600
2.2 V, 3 V
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
2.2 V, 3 V
2.2 V, 3 V
0
4
µs
0.6
4.7
µs
0.6
ns
ns
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 24. I2C Mode Timing
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10-Bit ADC, Power Supply and Input Range Conditions (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
Analog supply voltage
range
VSS = 0 V
VAx
Analog input voltage
range (2)
All Ax terminals,
Analog inputs selected in
ADC10AE register
ADC10 supply current (3)
fADC10CLK = 5 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1,
ADC10SHT1 = 0,
ADC10DIV = 0
IADC10
IREF+
Reference supply
current, reference buffer
disabled (4)
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
TA
-40°C to 105°C
VCC
MAX
UNIT
2.2
3.6
V
0
VCC
V
0.52
1.05
3V
0.6
1.2
2.2 V, 3 V
0.25
0.4
-40°C to 105°C
mA
mA
3V
0.25
0.4
1.1
1.4
fADC10CLK = 5 MHz
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
-40°C to 85°C
2.2 V, 3 V
105°C
2.2 V, 3 V
Reference buffer supply
IREFB,1 current with
ADC10SR = 1 (4)
fADC10CLK = 5 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
-40°C to 85°C
2.2 V, 3 V
105°C
2.2 V, 3 V
CI
Input capacitance
Only one terminal Ax selected at
a time
-40°C to 105°C
RI
Input MUX ON
resistance
0 V ≤ VAx ≤ VCC
-40°C to 105°C
40
TYP
2.2 V
Reference buffer supply
IREFB,0 current with
ADC10SR = 0 (4)
(1)
(2)
(3)
(4)
MIN
2.2 V, 3 V
1.8
0.5
mA
0.7
0.8
mA
27
pF
2000
Ω
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC,REF+
TEST CONDITIONS
VCC
MIN
IVREF+ ≤ 1 mA, REF2_5V = 0
Positive built-in
reference analog
IVREF+ ≤ 0.5 mA, REF2_5V = 1
supply voltage range
IVREF+ ≤ 1 mA, REF2_5V = 1
VREF+
Positive built-in
reference voltage
ILD,VREF+
Maximum VREF+
load current
VREF+ load
regulation
TYP
MAX
UNIT
2.2
2.8
V
2.9
IVREF+ ≤ IVREF+max, REF2_5V = 0
2.2 V, 3 V
1.41
1.5
1.59
IVREF+ ≤ IVREF+max, REF2_5V = 1
3V
2.35
2.5
2.65
2.2 V
V
±0.5
3V
±1
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
2.2 V, 3 V
±2
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
3V
mA
LSB
±2
VREF+ load
regulation response
time
IVREF+ = 100 µA to 900 µA,
VAx ≈ 0.5 x VREF+,
Error of conversion result
≤1 LSB
CVREF+
Maximum
capacitance at pin
VREF+ (1)
IVREF+ ≤ ±1 mA,
REFON = 1, REFOUT = 1
2.2 V, 3 V
100
pF
TCREF+
Temperature
coefficient
IVREF+ = constant with
0 mA ≤ IVREF+ ≤ 1 mA
2.2 V, 3 V
±100
ppm/°C
tREFON
Settling time of
internal reference
voltage (2)
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 to 1
tREFBURST
(1)
(2)
Settling time of
reference buffer (2)
ADC10SR = 0
ADC10SR = 1
IVREF+ = 0.5 mA,
REF2_5V = 0,
REFON = 1,
REFBURST = 1
ADC10SR = 0
IVREF+ = 0.5 mA,
REF2_5V = 1,
REFON = 1,
REFBURST = 1
ADC10SR = 0
ADC10SR = 1
ADC10SR = 1
400
3V
3.6 V
ns
2000
30
µs
1
2.2 V
2.5
2
3V
µs
4.5
The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA 2/A4/VREF+/ VeREF+ (REFOUT = 1),
must be limited; the reference buffer may become unstable otherwise.
The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
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10-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Positive external reference input
voltage range (2)
VeREF+
MIN
MAX
VeREF+ > VeREF-,
SREF1 = 1, SREF0 = 0
1.4
VCC
VeREF- ≤ VeREF+ ≤ VCC - 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
1.4
3
0
1.2
V
1.4
VCC
V
VeREF-
Negative external reference input
voltage range (4)
VeREF+ > VeREF-
ΔVeREF
Differential external reference
input voltage range
ΔVeREF = VeREF+ - VeREF-
VeREF+ > VeREF- (5)
IVeREF+
Static input current into VeREF+
IVeREF(1)
(2)
(3)
(4)
(5)
Static input current into VeREF-
0 V ≤ VeREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
VCC
UNIT
V
±1
0 V ≤ VeREF+ ≤ VCC - 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
0 V ≤ VeREF- ≤ VCC
2.2 V, 3 V
µA
0
2.2 V, 3 V
±1
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in oscillator
frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn on settling time of
the ADC (1)
(1)
42
ADC10SR = 1
fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSELx ≠ 0
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
2.2 V, 3 V
3.7
6.3
2.2 V, 3 V
2.06
3.51
2.2 V, 3 V
13 × ADC10DIVx ×
1 / fADC10CLK
100
UNIT
MHz
MHz
µs
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
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10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral linearity error
2.2 V, 3 V
±1
LSB
ED
Differential linearity error
2.2 V, 3 V
±1
LSB
EO
Offset error
2.2 V, 3 V
±1
LSB
EG
Gain error
ET
(1)
Total unadjusted error
Source impedance RS < 100 Ω
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
2.2 V
±1.1
±2
SREFx = 010, unbuffered external reference,
VeREF+ = 2.5 V
3V
±1.1
±2
SREFx = 011, buffered external reference (1),
VeREF+ = 1.5 V
2.2 V
±1.1
±4
SREFx = 011, buffered external reference (1),
VeREF+ = 2.5 V
3V
±1.1
±3
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
2.2 V
±2
±5
SREFx = 010, unbuffered external reference,
VeREF+ = 2.5 V
3V
±2
±5
SREFx = 011, buffered external reference (1),
VeREF+ = 1.5 V
2.2 V
±2
±7
SREFx = 011, buffered external reference (1),
VeREF+ = 2.5 V
3V
±2
±6
TYP
MAX
2.2 V
40
120
3V
60
160
LSB
LSB
The reference buffer offset adds to the gain and total unadjusted error.
10-Bit ADC, Temperature Sensor and Built-In VMID
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISENSOR
Temperature sensor supply
current (1)
REFON = 0, INCHx = 0Ah,
TA = 25°C
ADC10ON = 1, INCHx = 0Ah (2)
TCSENSOR
VOffset,Sensor
TEST CONDITIONS
Sensor offset voltage
ADC10ON = 1, INCHx = 0Ah
VCC
2.2 V, 3 V
(2)
Sensor output voltage (3)
3.44
3.55
-100
Temperature sensor voltage at
TA = 105°C (T version only)
VSENSOR
MIN
100
1365
1465
1195
1295
1395
Temperature sensor voltage at TA = 25°C
985
1085
1185
Temperature sensor voltage at TA = 0°C
895
995
1095
2.2 V, 3 V
tSENSOR(sample)
Sample time required if
channel 10 is selected (4)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11 (4)
ADC10ON = 1, INCHx = 0Bh
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≈ 0.5 × VCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
tVMID(sample)
Sample time required if
channel 11 is selected (5)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
(1)
(2)
(3)
(4)
(5)
2.2 V, 3 V
µA
3.66 mV/°C
1265
Temperature sensor voltage at TA = 85°C
UNIT
30
mV
mV
µs
2.2 V
N/A
3V
N/A
µA
V
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high).When REFON = 1, ISENSOR is included in IREF+.When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
No additional current is needed. The VMID is used during sampling.
The on time, tVMID(on), is included in the sampling time, tVMID(sample); no additional on time is needed.
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC (PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V, 3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V, 3.6 V
1
7
mA
10
ms
(1)
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time
2.2 V, 3.6 V
2.2 V, 3.6 V
20
104
Program/Erase endurance
ms
105
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
(2)
30
tFTG
tBlock,
Block program time for first byte or word
(2)
25
tFTG
Block program time for each additional
byte or word
(2)
18
tFTG
Block program end-sequence wait time
(2)
6
tFTG
Mass erase time
(2)
10593
tFTG
Segment erase time
(2)
4819
tFTG
0
tBlock, 1-63
tBlock,
End
tMass Erase
tSeg
(1)
(2)
Erase
15
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
44
RAM retention supply voltage
(1)
TEST CONDITIONS
CPU halted
MIN
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
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JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V, 3 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V, 3 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V, 3 V
15
100
2.2 V
0
5
MHz
3V
0
10
MHz
2.2 V, 3 V
25
90
kΩ
fTCK
TCK input frequency (2)
RInternal
Internal pulldown resistance on TEST
(1)
(2)
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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Application Information
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Table 16. Port P1 (P1.0 to P1.3) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
0
0
1
ADC10CLK
1
1
P1.1 (1) (I/O)
I: 0; O: 1
0
0
1
P1.0 (1)
P1.0/TACLK/ADC10CLK
P1.1/TA0
0
1
Timer_A3.TACLK
Timer_A3.CCI0A
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI1A
0
1
Timer_A3.TA1
1
1
P1.2 (1) (I/O)
P1.2/TA1
2
P1.3
P1.3/TA2
(1)
46
3
CONTROL BITS/SIGNALS
(1)
I: 0; O: 1
0
Timer_A3.CCI2A
(I/O)
0
1
Timer_A3.TA2
1
1
Default after reset (PUC/POR)
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Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access
Features
Pad Logic
P1REN.x
P1DIR.x
0
P1OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
To JTAG
From JTAG
Table 17. Port P1 (P1.4 to P1.6) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.4
P1.4/SMCLK/TCK
4
(2)
(I/O)
5
(1)
(2)
(3)
6
P1SEL.x
4-Wire JTAG
I: 0; O: 1
0
0
1
1
0
TCK
X
X
1
I: 0; O: 1
0
0
Timer_A3.TA0
1
1
0
TMS
X
X
1
I: 0; O: 1
0
0
P1.6 (2) (I/O)
P1.6/TA1/TDI/TCLK
P1DIR.x
SMCLK
P1.5 (2) (I/O)
P1.5/TA0/TMS
CONTROL BITS/SIGNALS (1)
Timer_A3.TA1
1
1
0
TDI/TCLK (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Function controlled by JTAG
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Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features
Pad Logic
P1REN.7
P1DIR.7
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.7
DVSS
DVCC
P1.7/TA2/TDO/TDI
Bus
Keeper
P1SEL.7
EN
P1IN.7
EN
Module X IN
D
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
Set
Interrupt
Edge
Select
P1SEL.7
P1IES.7
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Table 18. Port P1 (P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.7 (2) (I/O)
P1.7/TA2/TDO/TDI
7
Timer_A3.TA2
TDO/TDI
(1)
(2)
(3)
48
(3)
CONTROL BITS/SIGNALS (1)
P1DIR.x
P1SEL.x
4-Wire JTAG
I: 0; O: 1
0
0
1
1
0
X
X
1
X = Don't care
Default after reset (PUC/POR)
Function controlled by JTAG
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Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = y
ADC10AE0.y
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
P2.0/ACLK/A0
P2.2/TA0/A2
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
P2IFG.x
Set
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Table 19. Port P2 (P2.0, P2.2) Pin Functions
Pin Name (P2.x)
x
y
FUNCTION
P2.0 (2) (I/O)
P2.0/ACLK/A0
0
0
ACLK
A0
(3)
P2.2 (2) (I/O)
P2.2/TA0/A2
(1)
(2)
(3)
2
2
Timer_A3.CCI0B
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
0
1
0
Timer_A3.TA0
1
1
0
A2 (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 1
ADC10AE0.1
P2REN.1
P2DIR.1
0
P2OUT.1
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P2.1/TAINCLK/SMCLK/A1
Bus
Keeper
P2SEL.1
EN
P2IN.1
EN
Module X IN
D
P2IE.1
P2IRQ.1
EN
Q
P2IFG.1
Set
Interrupt
Edge
Select
P2SEL.1
P2IES.1
Table 20. Port P2 (P2.1) Pin Functions
PIN NAME (P2.x)
x
y
FUNCTION
P2.1 (2) (I/O)
P2.1/TAINCLK/SMCLK/
A1
(1)
(2)
(3)
50
1
1
Timer_A3.INCLK
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
0
1
0
SMCLK
1
1
0
A1 (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger
SREF2
Pad Logic
VSS
0
To ADC 10 VR−
1
To ADC 10
INCHx = 3
ADC10AE0.3
P2REN.3
P2DIR.3
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.3
DVSS
DVCC
P2.3/TA1/
A3/VREF−/VeREF−
Bus
Keeper
P2SEL.3
EN
P2IN.3
EN
Module X IN
D
P2IE.3
EN
P2IRQ.3
Q
Set
P2IFG.3
Interrupt
Edge
Select
P2SEL.3
P2IES.3
Table 21. Port P2 (P2.3) Pin Functions
PIN NAME (P2.x)
x
y
FUNCTION
P2.3
P2.3/TA1/A3/VREF/VeREF-
(1)
(2)
(3)
3
3
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
Timer_A3.CCI1B
0
1
0
Timer_A3.TA1
1
1
0
A3/VREF-/VeREF- (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger
Pad Logic
To /from ADC10
positive reference
To ADC 10
INCHx = 4
ADC10AE0.4
P2REN.4
P2DIR.4
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.4
DVSS
P2.4/TA2/
A4/VREF+/VeREF+
Bus
Keeper
P2SEL.4
EN
P2IN.4
EN
Module X IN
D
P2IE.4
P2IRQ.4
EN
Q
Set
P2IFG.4
P2SEL.4
P2IES.4
Interrupt
Edge
Select
Table 22. Port P2 (P2.4) Pin Functions
PIN NAME (P2.x)
x
y
FUNCTION
P2.4 (2) (I/O)
P2.4/TA2/A4/VREF+/
VeREF+
4
4
Timer_A3.TA2
A4/VREF+/VeREF+
(1)
(2)
(3)
52
(3)
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
1
1
0
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
Pad Logic
To DCO
DCOR
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
DVCC
P2.5/ROSC
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Table 23. Port P2 (P2.5) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.5
P2.5/ROSC
(1)
(2)
(3)
5
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
DCOR
I: 0; O: 1
0
0
N/A (3)
0
1
0
DVSS
1
1
0
ROSC
X
X
1
X = Don't care
Default after reset (PUC/POR)
N/A = Not available or not applicable
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Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
Pad Logic
P2SEL.7
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
DVCC
P2.6/XIN
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
Table 24. Port P2 (P2.6) Pin Functions
PIN NAME (P2.x)
P2.6/XIN
(1)
(2)
54
x
6
FUNCTION
P2.6 (I/O)
XIN (2)
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
I: 0; O: 1
0
X
1
X = Don't care
Default after reset (PUC/POR)
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Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
P2.6/XIN
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
DVCC
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
P2SEL.7
P2IES.7
Set
Interrupt
Edge
Select
Table 25. Port P2 (P2.7) Pin Functions
PIN NAME (P2.x)
XOUT/P2.7
(1)
(2)
(3)
x
7
FUNCTION
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
P2.7 (I/O)
I: 0; O: 1
0
XOUT (2)
X
1
(3)
X = Don't care
Default after reset (PUC/POR)
If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this
pin after reset.
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Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 5
ADC10AE0.5
P3REN.0
P3DIR.0
USCI Direction
Control
0
P3OUT.0
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.0/UCB0STE/UCA0CLK/A5
Bus
Keeper
P3SEL.0
EN
P3IN.0
EN
Module X IN
D
Table 26. Port P3 (P3.0) Pin Functions
PIN NAME (P1.x)
x
y
FUNCTION
P3.0 (2) (I/O)
P3.0/UCB0STE/
UCA0CLK/A5
0
5
UCB0STE/UCA0CLK (3)
A5
(1)
(2)
(3)
(4)
(5)
56
(4)
(5)
CONTROL BITS/SIGNALS (1)
P3DIR.x
P3SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
X
1
0
X
X
1
X = Don't care
Default after reset (PUC/POR)
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P3REN.x
P3DIR.x
USCI Direction
Control
0
P3OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
Bus
Keeper
P3SEL.x
EN
P3IN.x
EN
Module X IN
D
Table 27. Port P3 (P3.1 to P3.5) Pin Functions
PIN NAME (P3.x)
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
(1)
(2)
(3)
(4)
x
1
2
3
4
5
FUNCTION
P3.1
(2)
(I/O)
UCB0SIMO/UCB0SDA (3)
P3.2 (2) (I/O)
UCB0SOMI/UCB0SCL
(3)
P3.3 (2) (I/O)
UCB0CLK/UCA0STE (3)
P3.4
(2)
(4)
(I/O)
UCA0TXD/UCA0SIMO (3)
P3.5 (2) (I/O)
UCA0RXD/UCA0SOMI (3)
CONTROL BITS/SIGNALS (1)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
Default after reset (PUC/POR)
The pin direction is controlled by the USCI module.
UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode even if 4-wire SPI mode is selected.
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Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = y
ADC10AE0.y
P3REN.x
P3DIR.x
0
P3OUT.x
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
DVSS
DVSS
P3.6/A6
P3.7/A7
Bus
Keeper
P3SEL.x
EN
P3IN.x
EN
Module X IN
D
Table 28. Port P3 (P3.6, P3.7) Pin Functions
PIN NAME (P3.x)
P3.6/A6
P3.7/A7
(1)
(2)
(3)
58
x
6
7
y
6
7
FUNCTION
P3.6 (2) (I/O)
A6 (3)
P3.7
(2)
(I/O)
A7 (3)
CONTROL BITS/SIGNALS (1)
P3DIR.x
P3SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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SLAS824 – DECEMBER 2013
Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0
P4.1/TB1
P4.2/TB2
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Table 29. Port P4 (P4.0 to P4.2) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.0 (1) (I/O)
P4.0/TB0
0
Timer_B3.CCI0A
Timer_B3.TB0
P4.1 (1) (I/O)
P4.1/TB1
1
Timer_B3.CCI1A
Timer_B3.TB1
(1)
2
P4DIR.x
P4SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
Timer_B3.CCI2A
0
1
Timer_B3.TB2
1
1
P4.2 (1) (I/O)
P4.2/TB2
CONTROL BITS/SIGNALS
Default after reset (PUC/POR)
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Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC 10
†
INCHx = 8+y
ADC10AE1.y
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
DVCC
Bus
Keeper
P4SEL.x
P4.3/TB0/A12
P4.4/TB1/A13
EN
P4IN.x
EN
Module X IN
60
D
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SLAS824 – DECEMBER 2013
Table 30. Port P4 (P4.3 to P4.4) Pin Functions
PIN NAME (P4.x)
x
y
FUNCTION
P4.3
P4.3/TB0/A12
3
4
4
5
ADC10AE1.y
0
0
0
1
0
Timer_B3.TB0
1
1
0
A12 (3)
X
X
1
I: 0; O: 1
0
0
Timer_B3.CCI1B
0
1
0
Timer_B3.TB1
1
1
0
X
X
1
A13
(1)
(2)
(3)
P4SEL.x
I: 0; O: 1
(2)
(I/O)
P4DIR.x
Timer_B3.CCI0B
P4.4
P4.4/TB1/A13
(2)
CONTROL BITS/SIGNALS (1)
(I/O)
(3)
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC 10
INCHx = 14
ADC10AE1.6
P4REN.5
P4DIR.5
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.5
DVSS
P4.5/TB3/A14
Bus
Keeper
P4SEL.5
EN
P4IN.5
EN
Module X IN
D
Table 31. Port P4 (P4.5) Pin Functions
PIN NAME (P4.x)
x
y
FUNCTION
P4.5 (2) (I/O)
P4.5/TB3/A14
5
6
Timer_B3.TB2
A14
(1)
(2)
(3)
62
(3)
CONTROL BITS/SIGNALS (1)
P4DIR.x
P4SEL.x
ADC10AE1.y
I: 0; O: 1
0
0
1
1
0
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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NN325-Q1
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SLAS824 – DECEMBER 2013
Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 15
ADC10AE1.7
P4REN.6
P4DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.6
DVSS
P4.6/TBOUTH/A15
Bus
Keeper
P4SEL.6
EN
P4IN.6
EN
Module X IN
D
Table 32. Port P4 (P4.6) Pin Functions
PIN NAME (P4.x)
x
y
FUNCTION
P4.6 (2) (I/O)
P4.6/TBOUTH/A15
(1)
(2)
(3)
6
7
TBOUTH
CONTROL BITS/SIGNALS (1)
P4DIR.x
P4SEL.x
ADC10AE1.y
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
A15 (3)
X
X
1
X = Don't care
Default after reset (PUC/POR)
Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P4REN.x
P4DIR.x
0
P4OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P4.7/TBCLK
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Table 33. Port P4 (Pr.7) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.7
P4.7/TBCLK
(1)
64
7
(1)
(I/O)
CONTROL BITS/SIGNALS
P4DIR.x
P4SEL.x
I: 0; O: 1
0
Timer_B3.TBCLK
0
1
DVSS
1
1
Default after reset (PUC/POR)
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SLAS824 – DECEMBER 2013
JTAG Fuse Check Mode
NN325-Q1 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 25). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITF
ITEST
Figure 25. Fuse Check Mode Current
NOTE
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit
bootloader access key is used. Also, see the Bootstrap Loader section for more
information.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
NN325TRHARQ1
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
NN325
TQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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