OPA2634
OPA
263
4
www.ti.com
Dual, Wideband, Single-Supply
OPERATIONAL AMPLIFIER
TM
FEATURES
DESCRIPTION
●
●
●
●
●
●
●
The OPA2634 is a dual, low-power, voltage-feedback,
high-speed operational amplifier designed to operate
on +3V or +5V single-supply voltage. Operation on
±5V or +10V supplies is also supported. The input
range extends below ground and to within 1.2V of the
positive supply. Using complementary common-emitter outputs provides an output swing to within 30mV
of ground and 140mV of positive supply.
Low distortion operation is ensured by the high gain
bandwidth product (140MHz) and slew rate
(250V/µs). This makes the OPA2634 an ideal differential input buffer stage to 3V and 5V CMOS converters. Unlike other low-power, single-supply operational
amplifiers, distortion performance improves as the
signal swing is decreased. A low 5.6nV/√Hz input
voltage noise supports wide dynamic-range operation.
The OPA2634 is available in an industry-standard dual
pinout SO-8 package. Where a single-channel, singlesupply operational amplifier is required, consider the
OPA634 and OPA635. Where lower supply current
and speed are required, consider the OPA2631.
HIGH BANDWIDTH: 150MHz (G = +2)
+3V TO +10V OPERATION
INPUT RANGE INCLUDES GROUND
4.8V OUTPUT SWING ON +5V SUPPLY
HIGH OUTPUT CURRENT: 80mA
HIGH SLEW RATE: 250V/µs
LOW INPUT VOLTAGE NOISE: 5.6nV/√HZ
APPLICATIONS
●
●
●
●
●
DIFFERENTIAL RECEIVERS/DRIVERS
ACTIVE FILTERS
MATCHED I AND Q CHANNEL AMPLIFIERS
CCD IMAGING CHANNELS
LOW-POWER ULTRASOUND
+3V
2.26kΩ
+3V
374Ω
Q
1/2
OPA2634
100Ω
ADS900
10-Bit
20Msps
RELATED PRODUCTS
22pF
562Ω
750Ω
+3V
2.26kΩ
DESCRIPTION
SINGLES
DUALS
Medium Speed, No Disable
With Disable
OPA631
OPA632
OPA2631
—
High Speed, No Disable
With Disable
OPA634
OPA635
OPA2634
—
+3V
374Ω
I
1/2
OPA2634
100Ω
ADS900
10-Bit
20Msps
22pF
562Ω
750Ω
Copyright © 1999, Texas Instruments Incorporated
SBOS098A
Printed in U.S.A. February, 2001
SPECIFICATIONS: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1).
OPA2634U
TYP
PARAMETER
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
NTSC Differential Gain
NTSC Differential Phase
Channel-to-Channel Crosstalk
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Offset Current Drift
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: U
Thermal Resistance
U
SO-8
GUARANTEED
CONDITIONS
+25°C
+25°C
0°C to
70°C
–40°C to
+85°C
UNITS
MIN/
MAX
TEST
LEVEL(1)
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
VO ≤ 0.5Vp-p
G = +2, 2V Step
0.5V Step
0.5V Step
G = +2, 1V Step
VO = 2Vp-p, f = 5MHz
f > 1MHz
f > 1MHz
150
36
16
140
5
250
2.4
2.4
15
63
5.6
2.8
0.10
0.16
< –90
100
24
11
100
—
170
3.4
3.5
19
56
6.2
3.8
—
—
—
84
20
10
82
—
125
4.7
4.5
22
51
7.3
4.2
—
—
—
78
18
8
75
—
115
5.2
4.8
23
50
7.7
5
—
—
—
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dB
nV/√Hz
pA/√Hz
%
degrees
dB
min
min
min
min
typ
min
max
max
max
min
max
max
typ
typ
typ
B
B
B
B
C
B
B
B
B
B
B
B
C
C
C
63
53
±10
4.6
84
±4.5
15
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
A
A
B
Input Referred, 5MHz
RL = 150Ω
66
±3
—
25
±0.6
—
—
47
±2.25
—
60
±8
—
57
±2.6
—
–0.24
3.8
78
–0.1
3.5
73
–0.05
3.45
71
–0.01
3.4
63
V
V
dB
max
min
min
B
A
A
10 || 2.1
400 || 1.2
—
—
—
—
—
—
kΩ || pF
kΩ || pF
typ
typ
C
C
G = +2, f ≤ 100kHz
0.03
0.1
4.86
4.65
80
100
100
0.2
0.09
0.16
4.8
4.55
50
73
—
—
0.10
0.17
4.75
4.5
45
59
—
—
0.11
0.24
4.7
4.4
20
18
—
—
V
V
V
V
mA
mA
mA
Ω
max
max
min
min
min
min
typ
typ
A
A
A
A
A
A
C
C
VS = +5V, Each Channel
VS = +5V, Each Channel
Input Referred
—
—
12
12
55
2.7
10.5
12.7
11.3
52
2.7
10.5
13.2
9.75
50
2.7
10.5
13.5
8.5
49
V
V
mA
mA
dB
min
max
max
min
min
B
A
A
A
A
–40 to +85
—
—
—
°C
typ
C
125
—
—
—
°C/W
typ
C
VCM = 2.0V
VCM = 2.0V
Input Referred
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
±7
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
2
OPA2634
SBOS098A
SPECIFICATIONS: VS = +3V
At TA = 25°C, G = +2 and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
OPA2634U
TYP
PARAMETER
AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
Channel-to-Channel Crosstalk
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Offset Current Drift
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: U
Thermal Resistance
U
SO-8
GUARANTEED
CONDITIONS
+25°C
+25°C
0°C to
70°C
–40°C to
+85°C
UNITS
MIN/ TEST
MAX LEVEL(1)
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
VO ≤ 0.5Vp-p
1V Step
0.5V Step
0.5V Step
1V Step
VO = 1Vp-p, f = 5MHz
f > 1MHz
f > 1MHz
Input Referred, 5MHz
110
39
16
150
5
215
2.8
3.0
14
65
5.6
2.8
< –90
77
24
12
100
—
160
4.3
4.4
30
56
6.2
3.7
—
65
20
10
85
—
123
4.5
4.6
32
52
7.3
4.2
—
58
19
8
80
—
82
6.3
6.0
38
47
7.7
4.4
—
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dB
nV/√Hz
pA/√Hz
dB
min
min
min
min
typ
min
max
max
max
min
max
max
typ
B
B
B
B
C
B
B
B
B
B
B
B
C
RL = 150Ω
65
±1.5
—
25
±0.6
—
61
—
45
±2
—
59
±5
—
59
±2.3
—
55
±6
46
64
±4
40
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
A
A
B
–0.25
1.8
75
–0.1
1.6
65
–0.05
1.55
62
–0.01
1.5
59
V
V
dB
max
min
min
B
A
A
10 || 2.1
400 || 1.2
—
—
—
—
—
—
kΩ || p
kΩ || p
typ
typ
C
C
Figure 2, f < 100kHz
0.03
0.08
2.9
2.8
45
65
100
0.2
0.07
0.16
2.86
2.7
35
30
—
—
0.08
0.19
2.85
2.67
30
27
—
—
0.09
0.43
2.45
2.2
12
10
—
—
V
V
V
V
mA
mA
mA
Ω
max
max
min
min
min
min
typ
typ
A
A
A
A
A
A
C
C
VS = +3V, Each Channel
VS = +3V, Each Channel
Input Referred
—
—
10.8
10.8
50
2.7
10.5
11.5
10.1
47
2.7
10.5
11.8
8.6
44
2.7
10.5
12.0
8.0
43
V
V
mA
mA
dB
min
max
max
min
min
B
A
A
A
A
–40 to +85
—
—
—
°C
typ
C
125
—
—
—
°C/W
typ
C
VCM = 1.0V
VCM = 1.0V
Input Referred
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
±4
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C)
Typical value only for information.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product
for use in life support devices and/or systems.
OPA2634
SBOS098A
3
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATIONS
Power Supply ................................................................................ +11VDC
Internal Power Dissipation .................................... See Thermal Analysis
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ..................................................... –0.5 to +VS +0.3V
Storage Temperature Range ......................................... –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
Top View
SO
OPA2634
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
Out A
1
8
+VS
–In A
2
7
Out B
+In A
3
6
–In B
GND
4
5
+In B
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
OPA2634U
SO-8 Surface-Mount
182
–40°C to +85°C
OPA2634U
"
"
"
"
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
OPA2634U
OPA2634U/2K5
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “OPA2634U/2K5” will get a single 2500-piece Tape and Reel.
4
OPA2634
SBOS098A
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1).
LARGE-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
12
6
VO = 0.2Vp-p
9
6
0
G = +5
–3
Gain (dB)
Normalized Gain (dB)
VO = 0.2Vp-p
G = +2
3
–6
–9
G = +10
–12
3
0
VO = 1Vp-p
–3
VO = 2Vp-p
–6
VO = 4Vp-p
–9
–15
–12
–18
1
10
100
300
1
VO
VIN
VO
VIN
Time (10ns/div)
Time (10ns/div)
CHANNEL-TO-CHANNEL CROSSTALK
OUTPUT SWING vs LOAD RESISTANCE
1.0
Maximum VO
0.9
0.8
0.7
4.6
0.6
4.5
0.5
4.4
0.4
4.3
Right Scale
4.2
Minimum VO
4.1
4.0
50
SBOS098A
0.2
–50
–60
–70
–80
–90
0.1
0.0
1000
100
RL (Ω)
OPA2634
0.3
Input-Referred Crosstalk (dB)
Maximum Output Voltage (V)
Left Scale
–40
Minimum Output Voltage (V)
5.0
4.7
300
VO = 2Vp-p
Input and Output Voltage (500mV/div)
Input and Output Voltage (50mV/div)
VO = 200mVp-p
4.8
100
LARGE-SIGNAL PULSE RESPONSE
SMALL-SIGNAL PULSE RESPONSE
4.9
10
Frequency (MHz)
Frequency (MHz)
–100
1
10
100
Frequency (MHz)
5
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
HARMONIC DISTORTION vs OUTPUT VOLTAGE
HARMONIC DISTORTION vs NON-INVERTING GAIN
–50
–50
VO = 2Vp-p
f = 5MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
f = 5MHz
–60
3rd Harmonic
–70
2nd Harmonic
–80
–90
3rd Harmonic
–60
2nd Harmonic
–70
–80
–90
0.1
1
1
4
10
Gain Magnitude (V/V)
Output Voltage (Vp-p)
HARMONIC DISTORTION vs INVERTING GAIN
HARMONIC DISTORTION vs FREQUENCY
–50
–50
VO = 2Vp-p
3rd Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2Vp-p
f = 5MHz
–60
2nd Harmonic
–70
–80
–60
3rd Harmonic
–70
–80
2nd Harmonic
–90
–90
1
10
0.1
1
Gain Magnitude (V/V)
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
–50
–50
VO = 2Vp-p
fO = 5MHz
VO = 2Vp-p
fO = 5MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
10
Frequency (MHz)
–60
–70
2nd Harmonic
–80
–60
3rd Harmonic
–70
2nd Harmonic
–80
3rd Harmonic
–90
–90
100
1000
RL (Ω)
6
3
4
5
6
7
8
9
10
Supply Voltage (V)
OPA2634
SBOS098A
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
CMRR AND PSRR vs FREQUENCY
80
Rejection Ratio, Input Referred (dB)
–45
fO = 20MHz
–50
fO = 10MHz
–55
–60
–65
–70
–75
fO = 5MHz
–80
Load Power at
Matched 50Ω Load
–85
CMRR
75
70
65
PSRR
60
55
50
45
40
35
30
–90
–16 –14
–12
–10
–8
–6
–4
–2
100
0
1k
10k
Single-Tone Load Power (dBm)
INPUT NOISE DENSITY vs FREQUENCY
Voltage Noise, eni = 5.6nV/√Hz
Open-Loop Gain (dB)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
10
Current Noise, ini = 2.8pA/√Hz
1
1k
10k
100k
1M
100
90
80
70
60
50
40
30
20
10
0
–10
–20
10M
0
–30
–60
–90
–120
–150
–180
–210
–240
–270
–300
–330
–360
Open-Loop Gain
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
1000
CL = 1000pF
1
VO = 0.2Vp-p
0
CL = 10pF
–1
100
CL = 100pF
–2
RS (Ω)
Normalized Gain (dB)
10M
Open-Loop Phase
Frequency (Hz)
2
1M
OPEN-LOOP GAIN AND PHASE
100
100
100k
Frequency (Hz)
Open-Loop Phase (°)
3rd-Order Spurious Level (dBc)
–40
–3
–4
1/2
OPA2634
–5
RS
CL
–6
–7
10
VO
1kΩ
+VS/2
1
–8
1
10
Frequency (MHz)
OPA2634
SBOS098A
100
300
1
10
100
1000
Capacitive Load (pF)
7
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
INPUT DC ERRORS vs TEMPERATURE
5.0
50
Input Offset Voltage (mV)
10
1
40
3.5
35
3.0
30
2.5
25
Input Bias Current
2.0
20
1.5
15
10X Input Offset Current
1.0
10
0.5
5
0.0
0.1
1k
10k
100k
1M
10M
0
–40
100M
–20
0
16
140
100
Sourcing Output Current
8
80
6
60
4
40
2
20
0
20
40
60
80
125
Slew Rate
200
100
150
75
100
50
50
25
0
0
0
100
150
250
Slew Rate (V/µs)
120
Output Current (mA)
12
–20
80
Gain Bandwidth Product
Power-Supply Current
–40
60
300
160
Sinking Output Current
10
40
SLEW RATE AND GAIN BANDWIDTH PRODUCT
vs SUPPLY VOLTAGE
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
14
20
Temperature (°C)
Frequency (Hz)
Power-Supply Current (mA/chan)
45
Input Offset Voltage
4.0
0
3
100
Gain Bandwidth Product (MHz)
Output Impedance (Ω)
4.5
Input Bias Current (µA)
10x Input Offset Current (µA)
100
4
5
6
7
8
9
10
Supply Voltage (V)
Temperature (°C)
SUPPLY AND OUTPUT CURRENTS
vs SUPPLY VOLTAGE
180
16
160
Quiescent-Supply Current
14
140
12
120
10
100
8
80
Output Current, Sourcing
6
60
Output Current, Sinking
4
Output Current (mA)
Quiescent-Supply Current (mA/chan)
18
40
2
20
0
0
3
4
5
6
7
8
9
10
Supply Voltage (V)
8
OPA2634
SBOS098A
TYPICAL PERFORMANCE CURVES: VS = +3V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
6
12
VO = 0.2Vp-p
VO = 0.2Vp-p
G = +2
9
0
6
G = +5
–3
Gain (dB)
–6
–9
G = +10
–12
3
VO = 1Vp-p
0
VO = 2Vp-p
–3
–6
–15
–9
–18
–12
1
10
100
300
1
10
Frequency (MHz)
3.0
–45
2.9
fO = 20MHz
–55
–60
fO = 10MHz
–65
–70
–75
–80
fO = 5MHz
–85
Load Power at
Matched 50Ω Load
1.0
Maximum VO
2.7
–12
–10
–8
–6
0.7
0.6
2.5
0.5
2.4
0.4
2.3
Right Scale
2.2
–4
0.3
0.2
Minimum VO
50
0.1
0.0
1000
100
Single-Tone Load Power (dBm)
RL (Ω)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
1000
2
CL = 1000pF
1
VO = 0.2Vp-p
0
CL = 10pF
–1
100
–2
CL = 100pF
–3
–4
1/2
OPA2634
–5
RS
–6
–7
10
VO
CL
RS (Ω)
Normalized Gain (dB)
0.8
2.6
2.0
–14
0.9
Left Scale
2.8
2.1
–90
–16
300
OUTPUT SWING vs LOAD RESISTANCE
–40
Maximum Output Voltage (V)
3rd-Order Spurious Level (dBc)
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
–50
100
Frequency (MHz)
Minimum Output Voltage (V)
Normalized Gain (dB)
3
1kΩ
+VS/2
1
–8
1
10
Frequency (MHz)
OPA2634
SBOS098A
100
300
1
10
100
1000
Capacitive Load (pF)
9
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE FEEDBACK OPERATION
The OPA2634 is a unity-gain stable, very high-speed, voltage-feedback op amp designed for single-supply operation
(+3V to +10V). The input stage supports input voltages
below ground, and to within 1.2V of the positive supply. The
complementary common-emitter output stage provides an
output swing to within 30mV of ground and 140mV of the
positive supply. It is compensated to provide stable operation with a wide range of resistive loads.
Figure 1 shows the AC-coupled, gain of +2 configuration
used for the +5V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Voltage swings reported in the
Specifications are taken directly at the input and output pins.
For the circuit of Figure 1, the total effective load on the
output at high frequencies is 150Ω || 1500Ω. The 1.50kΩ
resistors at the non-inverting input provide the commonmode bias voltage. Their parallel combination equals the DC
resistance at the inverting input, minimizing the DC offset.
+VS = 5V
6.8µF
+
1.50kΩ
VIN
1.50kΩ
1/2
OPA2634
VOUT
RL
150Ω
0.1µF
RG
750Ω
6.8µF
+
0.1µF
2.26kΩ
374Ω
VIN
1/2
OPA2634
57.6Ω
VOUT
RL
150Ω
RG
562Ω
RF
750Ω
+VS
2
FIGURE 2. DC-Coupled Signal—Resistive Load to Supply
Midpoint.
ADC and its driver. The OPA2634 provides excellent performance in this demanding application. Its large input and
output voltage ranges, and low distortion, support converters
such as the ADS900 shown in this figure. The input levelshifting circuitry was designed so that VIN can be between
0V and 0.5V, while producing a 1V to 2V at the output pin
for the ADS900.
0.1µF
0.1µF
53.6Ω
+VS = 3V
RF
750Ω
ANTI-ALIASING FILTER
Figure 3 shows an anti-aliasing filter, with a 5th-order
Inverse Chebyshev response, based on a single OPA2634.
This filter cascades two 2nd-order Sallen-Key sections with
transmission zeros, and a real pole section followed by a
simple real pole at the output. It has a –3dB frequency of
5MHz, and a –60dB stopband starting at 12MHz.
+VS
2
1% Resistors
5% Capacitors
680pF
FIGURE 1. AC-Coupled Signal—Resistive Load to Supply
Midpoint.
Figure 2 shows the DC-coupled, gain of +2 configuration
used for the +3V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Though not strictly a “rail-to-rail”
design, this part comes very close, while maintaining excellent performance. It will deliver up to 2.8Vp-p on a single
+3V supply with > 60MHz bandwidth. The 374Ω and
2.26kΩ resistors at the input level-shift VIN so that VOUT is
within the allowed output voltage range when VIN = 0. See
the typical performance curves for information on driving
capacitive loads.
100Ω
215Ω
56pF
VIN
680pF
10pF 20Ω
1/2
OPA2634
210Ω
68.1Ω
330pF
115Ω
191Ω
VOUT
1/2
OPA2634
220pF
20Ω
93.1Ω
18pF
330pF
150pF
205Ω
SINGLE-SUPPLY ADC INTERFACE
The front page shows a DC-coupled, single-supply, dual
ADC (Analog-to-Digital Converter) driver circuit. Many
systems are now requiring +3V supply capability of both the
10
48.7Ω
FIGURE 3. Inverse Chebyshev Anti-Aliasing Filter.
OPA2634
SBOS098A
This filter works well on +5V or ±5V supplies, and with an
Analog-to-Digital (A/D) converter at 20MSPS (e.g.,
ADS900). VIN needs to be a very low impedance source,
such as an op amp.
The filter transfer function was designed using Burr-Brown’s
FilterPro 42 design program (available at www.ti.com) with
a nominal stopband attenuation of 60dB. Table I gives the
results (H0 = DC gain, fP = pole frequency, QP = pole
quality, and fZ = zero frequency). Note that the parameters
were generated at f–3dB = 5Hz, and then scaled to f–3dB =
5MHz.
R2
R1
VIN
1/2
OPA2634
R3
FILTER SECTION
H0
fP
QP
fZ
1
1V/V
5.04MHz
1.77
12.6MHz
2
1V/V
5.31MHz
0.64
20.4MHz
3
1V/V
5.50MHz
—
—
TABLE I. Nominal Filter Parameters.
VOUT
R4
FIGURE 5. DC Level-Shifting Circuit.
The components were chosen to give this transfer function.
The 20Ω resistors isolate the amplifier outputs from capacitive
loading, but affect the response at very high frequencies only.
Figure 4 shows the nominal response simulated by SPICE; it
is very close to the ideal response.
0
–10
–20
Gain (dB)
+VS
Make sure that VIN and VOUT stay within the specified input
and output voltage ranges.
The front-page circuit is a good example of this type of application.
It was designed to take VIN between 0V and 0.5V, and produce
VOUT between 1V and 2V, when using a +3V supply. This means
G = 2, and ∆VOUT = 1.50V – G • 0.25V = 1.00V. Plugging into
the above equations (with R4 = 750Ω) gives: NG = 2.33,
R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The resistors were
changed to the nearest standard values.
–30
–40
–50
–60
–70
–80
1
10
100
Frequency (MHz)
FIGURE 4. Nominal Filter Response.
DC LEVEL-SHIFTING
Figure 5 shows a DC-coupled, non-inverting amplifier that
level-shifts the input up to accommodate the desired output
voltage range. Given the desired signal gain (G), and the
amount VOUT needs to be shifted up (∆VOUT) when VIN is at
the center of its range, the following equations give the
resistor values that produce the desired performance. Start
by setting R4 between 200Ω and 1.5kΩ:
NON-INVERTING AMPLIFIER WITH
REDUCED PEAKING
Figure 6 shows a non-inverting amplifier that reduces peaking at low gains. The resistor RC compensates the OPA2634
to have higher Noise Gain (NG), which reduces the AC
response peaking (typically 5dB at G = +1 without RC)
without changing the DC gain. VIN needs to be a low
impedance source, such as an op amp. The resistor values
are low to reduce noise. Using both RT and RF helps
minimize the impact of parasitic impedances.
RT
VIN
RC
1/2
OPA2634
VOUT
NG = G + ∆VOUT/VS
R1 = R4/G
RG
RF
R2 = R4/(NG – G)
R3 = R4/(NG –1)
where:
NG = 1 + R4/R3 (Noise Gain)
FIGURE 6. Compensated Non-Inverting Amplifier.
VOUT = (G)VIN + (NG – G)VS
OPA2634
SBOS098A
11
The noise gain can be calculated as follows:
G1 = 1 +
RF
RG
G2 = 1 +
R T + R F /G1
RC
NG = G1G 2
A unity-gain buffer can be designed by selecting
RT = RF = 20.0Ω and RC = 40.2Ω (do not use RG ). This gives
a noise gain of 2, therefore, its response will be similar to the
typical performance curves with G = +2. Decreasing RC to
20.0Ω will increase the noise gain to 3, which typically gives
a flat frequency response, but with less bandwidth.
The circuit in Figure 2 can be redesigned to have less peaking
by increasing the noise gain to 3. This is accomplished by
adding RC = 2.55kΩ between the op amp’s inputs.
DESIGN-IN TOOLS
made with a 20Ω resistor, not a direct short. This will isolate
the inverting input capacitance from the output pin and
improve the frequency response flatness. Usually, for G > 1
application, the feedback resistor value should be between
200Ω and 1.5kΩ. Below 200Ω, the feedback network will
present additional output loading which can degrade the
harmonic-distortion performance. Above 1.5kΩ, the typical
parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional bandlimiting in the
amplifier response.
A good rule of thumb is to target the parallel combination of
RF and RG (Figure 6) to be less than approximately 400Ω.
The combined impedance (RF || RG) interacts with the inverting input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 3pF total parasitic on the inverting node, holding RF || RG < 400Ω will keep this pole above 130MHz. By
itself, this constraint implies that the feedback resistor (RF)
can increase to several kΩ at high gains. This is acceptable
as long as the pole formed by RF, and any parasitic capacitance appearing in parallel, is kept out of the frequency
range of interest.
DEMONSTRATION BOARDS
A PC board is available to assist in the initial evaluation of
circuit performance using the OPA2634U. It is available
free as an unpopulated PC board delivered with descriptive
documentation. The summary information for this board is
shown in Table II.
PRODUCT
PACKAGE
BOARD
PART
NUMBER
OPA2634U
SO-8
DEM-OPA268xU
LITERATURE
REQUEST
NUMBER
MKT-352
TABLE II. Demo Board Summary Information.
Contact the Texas Instruments Technical Applications Support Line at 1-972-644-5580 to request this board.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA2634 is a voltage-feedback op amp, a wide
range of resistor values may be used for the feedback and
gain setting resistors. The primary limits on these values are
set by dynamic range (noise and distortion) and parasitic
capacitance considerations. For a non-inverting unity-gain
follower application, the feedback connection should be
12
BANDWIDTH VERSUS GAIN: NON-INVERTING OPERATION
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the Specifications. Ideally, dividing GBP
by the non-inverting signal gain (also called the Noise Gain,
or NG) will predict the closed-loop bandwidth. In practice,
this only holds true when the phase margin approaches 90°,
as it does in high-gain configurations. At low gains (increased feedback factors), most amplifiers will exhibit a
more complex response with lower phase margin. The
OPA2634 is compensated to give a slightly peaked response
in a non-inverting gain of 2 (Figure 1). This results in a
typical gain of +2 bandwidth of 150MHz, far exceeding that
predicted by dividing the 140MHz GBP by 2. Increasing the
gain will cause the phase margin to approach 90° and the
bandwidth to more closely approach the predicted value of
(GBP/NG). At a gain of +10, the 16MHz bandwidth shown
in the Specifications is close to that predicted using the
simple formula and the typical GBP.
The OPA2634 exhibits minimal bandwidth reduction going
to +3V single-supply operation as compared with +5V
supply. This is because the internal bias control circuitry
retains nearly constant quiescent current as the total supply
voltage between the supply pins is changed.
OPA2634
SBOS098A
INVERTING AMPLIFIER OPERATION
Since the OPA2634 is a general-purpose, wideband voltagefeedback op amp, all of the familiar op amp application
circuits are available to the designer. Figure 7 shows a
typical inverting configuration where the I/O impedances
and signal gain from Figure 1 are retained in an inverting
circuit configuration. Inverting operation is one of the more
common requirements and offers several performance benefits. The inverting configuration shows improved slew rate
and distortion. It also biases the input at VS/2 for the best
headroom. The output voltage can be independently moved
with bias-adjustment resistors connected to the inverting input.
+5V
0.1µF
2RT
1.50kΩ
0.1µF
50Ω
0.1µF
Source
2RT
1.50kΩ
RG
374Ω
1/2
OPA2634
+
6.8µF
RO
50Ω
50Ω Load
RF
750Ω
RM
57.6Ω
resistor (RM) to ground. The total input impedance becomes
the parallel combination of RG and RM.
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence, influences the
bandwidth. For the example in Figure 7, the RM value
combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of
50Ω || 57.6Ω = 26.8Ω. This impedance is added in series
with RG for calculating the noise gain. The resultant is 2.87
for Figure 7, as opposed to only 2 if RM could be eliminated
as discussed above. The bandwidth will, therefore, be lower
for the gain of –2 circuit of Figure 7 (NG = +2.87) than for
the gain of +2 circuit of Figure 1.
The third important consideration in inverting amplifier design
is setting the bias current cancellation resistors on the noninverting input (parallel combination of RT = 750Ω). If this
resistor is set equal to the total DC resistance looking out of the
inverting node, the output DC error, due to the input bias
currents, will be reduced to (Input Offset Current) • RF. Because
of the 0.1µF capacitor, the inverting input’s bias current flows
through RF. Thus, RT = 750Ω = 1.50kΩ || 1.50kΩ is needed for
the minimum output offset voltage. To reduce the additional
high-frequency noise introduced by RT, and power-supply
feedthrough, it is bypassed with a 0.1µF capacitor. At a
minimum, the OPA2634 should see a source resistance of at
least 50Ω to damp out parasitic-induced peaking—a direct
short to ground on the non-inverting input runs the risk of a very
high-frequency instability in the input stage.
OUTPUT CURRENT AND VOLTAGE
FIGURE 7. Gain of –2 Example Circuit.
In the inverting configuration, three key design consideration must be noted. The first is that the gain resistor (RG)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long
PC board trace, or other transmission line conductor), RG
may be set equal to the required termination value and RF
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting RG to
50Ω for input matching eliminates the need for RM but
requires a 100Ω feedback resistor. This has the interesting
advantage of the noise gain becoming equal to 2 for a 50Ω
source impedance—the same as the non-inverting circuits
considered above. However, the amplifier output will now
see the 100Ω feedback resistor in parallel with the external
load. In general, the feedback resistor should be limited to
the 200Ω to 1.5kΩ range. In this case, it is preferable to
increase both the RF and RG values, as shown in Figure 7,
and then achieve the input matching impedance with a third
OPA2634
SBOS098A
The OPA2634 provides outstanding output voltage capability. Under no-load conditions at +25°C, the output voltage
typically swings closer than 140mV to either supply rail; the
guaranteed over temperature swing is within 300mV of
either rail (VS = +5V).
The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold start-up will the
output current and voltage decrease to the numbers shown in
the guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
VBE’s (increasing the available output voltage swing) and
increasing their current gains (increasing the available output current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications, since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem, since most applications include a series
matching resistor at the output that will limit the internal
power dissipation if the output side of this resistor is shorted
to ground.
13
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional
external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA2634 can be very susceptible to
decreased stability and closed-loop response peaking when
a capacitive load is placed directly on the output pin. When
the primary considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest and
most effective solution is to isolate the capacitive load from
the feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
The Typical Performance Curves show the recommended
RS versus capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA2634.
Long PC board traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series
resistor as close as possible to the output pin (see Board
Layout Guidelines section).
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms (2.8pA/√Hz), combine to
give low output noise under a wide variety of operating
conditions. Figure 8 shows the op amp noise analysis model
with all the noise terms included. In this model, all noise
terms are taken to be noise voltage or current density terms
in either nV/√Hz or pA/√Hz.
ENI
1/2
OPA2634
RS
ERS
RF
√ 4kTRS
IBI
RG
4kT
RG
FIGURE 8. Noise Analysis Model.
DISTORTION PERFORMANCE
EO =
NOISE PERFORMANCE
High slew rate, unity gain stable, voltage-feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 5.6nV/√Hz input voltage noise for
the OPA2634 is, however, much lower than comparable
14
√ 4kTRF
4kT = 1.6E –20J
at 290°K
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a gain of
+2, the frequency response at the output pin is already
slightly peaked without the capacitive load, requiring relatively high values of RS to flatten the response at the load.
Increasing the noise gain will also reduce the peaking,
reducing the required RS value (see Figure 6).
The OPA2634 provides good distortion performance into a
150Ω load. Relative to alternative solutions, it provides
exceptional performance into lighter loads and/or operating
on a single +3V supply. Generally, until the fundamental
signal reaches very high frequency or power levels, the 2nd
harmonic will dominate the distortion with a negligible 3rd
harmonic component. Focusing then on the 2nd harmonic,
increasing the load impedance improves distortion directly.
Remember that the total load includes the feedback network;
in the non-inverting configuration (Figure 1) this is sum of
RF + RG, while in the inverting configuration, only RF needs
to be included in parallel with the actual load.
EO
IBN
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 8.
(1)
(E
NI
2
)
+ ( I BN R S ) + 4kTR S NG 2 + ( I BI R F ) + 4kTR F NG
2
2
Dividing this expression by the noise gain (NG = (1 + RF/RG))
will give the equivalent input-referred spot noise voltage at
the non-inverting input, as shown in Equation 2.
(2)
I R 2 4kTR F
2
E N = E NI 2 + ( I BN R S ) + 4kTR S + BI F +
NG
NG
Evaluating these two equations for the circuit and component values shown in Figure 1 will give a total output spot
noise voltage of 12.5nV/√Hz and a total equivalent input
spot noise voltage of 6.3nV/√Hz. This is including the noise
added by the resistors. This total input-referred spot noise
voltage is not much higher than the 5.6nV/√Hz specification
for the op amp voltage noise alone. This will be the case as
long as the impedances appearing at each op amp input are
limited to the previously recommend maximum value of
400Ω, and the input attenuation is low.
OPA2634
SBOS098A
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage-feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power-supply current trim for the OPA2634
gives even tighter control than comparable products. Although the high-speed input stage does require relatively
high input bias current (typically 25µA out of each input
terminal), the close matching between them may be used to
reduce the output DC error caused by this current. This is
done by matching the DC source resistances appearing at the
two inputs. Evaluating the configuration of Figure 1 (which
has matched DC input resistances), using worst-case +25°C
input offset voltage and current specifications, gives a worstcase output offset voltage equal to (NG = non-inverting
signal gain at DC):
±(NG • VOS(MAX)) ± (RF • IOS(MAX))
= ±(1 • 7.0mV) ± (750Ω • 2.25µA)
= ±8.7mV [Output Offset Range for Figure 1]
A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques are based on adding a DC
current through the feedback resistor. In selecting an offset
trim method, one key consideration is the impact on the
desired signal path frequency response. If the signal path is
intended to be non-inverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
inverting, applying the offset control to the non-inverting
input may be considered. Bring the DC offsetting current
into the inverting input node through resistor values that are
much larger than the signal path resistors. This will insure
that the adjustment circuit has minimal effect on the loop
gain and hence the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below.
In no case should the maximum junction temperature be
allowed to exceed 175°C.
Operating junction temperature (TJ) is given by TA + PD•θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for resistive load
connected to mid-supply (VS/2), be at a maximum when the
output is fixed at a voltage equal to VS/4 or 3VS/4. Under this
condition, PDL = VS2/(16 • RL), where RL includes feedback
network loading.
OPA2634
SBOS098A
Note that it is the power in the output stage, and not into the
load, that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using
the circuit of Figure 1 operating at the maximum specified
ambient temperature of +85°C and driving a 150Ω load at
mid-supply, for both channels:
PD = 2 (10V • 13.5mA + 52/(16 • (150Ω || 1500Ω))) = 289mW
Maximum TJ = +85°C + (0.29W • 125°C/W) = 121°C
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. The highest
possible internal dissipation will occur if the load requires
current to be forced into the output at high output voltages
or sourced from the output at low output voltages. This puts
a high current through a large internal voltage drop in the
output transistors.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA2634 requires careful attention to
board layout parasitics and external component types. Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbroken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. Each power-supply
connection should always be decoupled with one of these
capacitors. An optional supply decoupling capacitor (0.1µF)
across the two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These
may be placed somewhat farther from the device and may be
shared among several devices in the same area of the PC
board.
c) Careful selection and placement of external components will preserve the high frequency performance.
Resistors should be a very low reactance type. Surfacemount resistors work best and allow a tighter overall layout.
Metal film or carbon composition axially-leaded resistors
can also provide good high-frequency performance. Again,
15
keep their leads and PC board traces as short as possible.
Never use wirewound type resistors in a high frequency
application. Since the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position
the feedback and series output resistor, if any, as close as
possible to the output pin. Other network components, such
as non-inverting input termination resistors, should also be
placed close to the package. Where double-side component
mounting is allowed, place the feedback resistor directly
under the package on the other side of the board between the
output and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors, excessively high
resistor values can create significant time constants that can
degrade performance. Good axial metal film or surfacemount resistors have approximately 0.2pF in shunt with the
resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can
effect circuit operation. Keep resistor values as low as
possible consistent with load driving considerations. The
750Ω feedback used in the typical performance specifications is a good starting point for design.
input impedance of the destination device; this total effective impedance should be set to match the trace impedance.
If the 6dB attenuation of a doubly-terminated transmission
line is unacceptable, a long trace can be series-terminated at
the source end only. Treat the trace as a capacitive load in
this case and set the series resistor value as shown in the
typical performance curve “Recommended RS vs Capacitive
Load”. This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation
due to the voltage divider formed by the series output into
the terminating impedance.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RS from the
typical performance curve “Recommended RS vs Capacitive
Load”. Low parasitic capacitive loads (< 5pF) may not need
an RS since the OPA2634 is nominally compensated to
operate with a 2pF parasitic load. Higher parasitic capacitive
loads without an RS are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long trace is
required, and the 6dB signal loss intrinsic to a doublyterminated transmission line is acceptable, implement a
matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a
higher impedance environment will improve distortion as
shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material
and trace dimensions), a matching series resistor into the
trace from the output of the OPA2634 is used as well as a
terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and the
The OPA2634 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with
internal ESD protection diodes to the power supplies, as
shown in Figure 9.
16
e) Socketing a high-speed part is not recommended. The
additional lead length and pin-to-pin capacitance introduced
by the socket can create an extremely troublesome parasitic
network which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are obtained
by soldering the OPA2634 onto the board.
INPUT AND ESD PROTECTION
+V CC
External
Pin
Internal
Circuitry
–V CC
FIGURE 9. Internal ESD Protection.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply
parts driving into the OPA2634), current-limiting series
resistors should be added into the two inputs. Keep these
resistor values as low as possible, since high values degrade
both noise performance and frequency response.
OPA2634
SBOS098A
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
工商网监
湘ICP备2023018690号
