OPA2650P

® OPA OPA 265 0 265 0 OPA2650 Dual Wideband, Low Power Voltage Feedback OPERATIONAL AMPLIFIER FEATURES q LOW POWER: 50mW/Chan. q UNITY GAIN STABLE BANDWIDTH: 360MHz q FAST SETTLING TIME: 20ns to 0.01% q LOW HARMONICS: –77dBc at 5MHz q DIFFERENTIAL GAIN/PHASE ERROR: 0.01%/0.025° q HIGH OUTPUT CURRENT: 85mA DESCRIPTION The OPA2650 is a dual, low power, wideband voltage feedback operational amplifier. It features a high bandwidth of 360MHz as well as a 12-bit settling time of only 20ns. The low distortion allows its use in communications applications, while the wide bandwidth and true differential input stage make it suitable for use in a variety of active filter applications. Its low distortion gives exceptional performance for telecommunications, medical imaging and video applications. The OPA2650 is internally compensated for unitygain stability. This amplifier has a fully symmetrical differential input due to its “classical” operational amplifier circuit architecture. Its unusual combination of speed, accuracy and low power make it an outstanding choice for many portable, multi-channel and other high speed applications, where power is at a premium. The OPA2650 is also available in single (OPA650) and quad (OPA4650) configurations. APPLICATIONS q HIGH RESOLUTION VIDEO q BASEBAND AMPLIFIER q CCD IMAGING AMPLIFIER q ULTRASOUND SIGNAL PROCESSING q ADC/DAC GAIN AMPLIFIER q ACTIVE FILTERS q HIGH SPEED INTEGRATORS q DIFFERENTIAL AMPLIFIER +VS Non-Inverting Input Output Stage Inverting Input Current Mirror CC Output –VS NOTE: Diagram shows only one-half of the OPA2650. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1994 Burr-Brown Corporation PDS-1266C 1 OPA2650 Printed in U.S.A. June, 1997 SPECIFICATIONS At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1. OPA2650P, U, E PARAMETER FREQUENCY RESPONSE Closed-Loop Bandwidth(2) CONDITIONS G = +1 G = +2 G = +5 G = +10 G ≥ +5 G = +2 G = +1, 2V Step G = +1, 0.2V Step G = +1, 0.2V Step G = +1, 2V Step G = +1, 2V Step G = +1, 2V Step G = +1, f = 5.0MHz, VO = 2Vp-p RL = 100Ω RL = 402Ω G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω Input Referred, 5MHz, Channel-to-Channel VCM = 0V Input Referred, VS = ±4.5V to ±5.5V 60 47 MIN TYP 360 108 32 16 160 21 240 220 1 1 20 11 6.7 72 77 0.01 0.025 –84 ±1 ±3 76 54 5 0.5 ±5 70 50 20 30 1 3 MAX OPA2650PB, UB MIN TYP T(1) T T T T T T T T T T T T T T T T ±1 T T T T 0.2 ±3 MAX UNITS MHz MHz MHz MHz MHz MHz V/µs V/µs ns ns ns ns ns dB dB % Degrees dB mV µV/°C dB dB µA µA µA µA Gain Bandwidth Product Bandwidth for 0.1dB Flatness(2) Slew Rate(3) Over Temperature Range Rise Time Fall Time Settling Time 0.01% 0.1% 1% Spurious Free Dynamic Range Differential Gain Differential Phase Crosstalk(2) INPUT OFFSET VOLTAGE Input Offset Voltage Average Drift Power Supply Rejection (+VS) (–VS) INPUT BIAS CURRENT Input Bias Current Over Temperature Range Input Offset Current Over Temperature Range INPUT NOISE Input Voltage Noise Noise Density, f = 100Hz f = 10kHz f ≥ 1MHz Integrated Noise fB = 10Hz to 100MHz Input Bias Current Noise Noise Density, f ≥ 0.1MHz INPUT VOLTAGE RANGE Common-Mode Input Range Over Temperature Range Common-Mode Rejection INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain Over Temperature Range OUTPUT Voltage Output Over Temperature Range VCM = 0V VCM = 0V 10 20 0.5 2 43 9.4 8.4 84 1.2 ±2.8 90 15 || 1 16 || 1 VO = ±2V, RL = 100Ω 45 43 51 47 45 T 70 T T T T T T T T T T nV/√Hz nV/√Hz nV/√Hz µVrms pA/√Hz V V dB KΩ || pF MΩ || pF dB dB Input Referred, VCM = ±0.5V ±2.2 65 No Load RL = 250Ω RL = 100Ω Output Current, Sourcing Over Temperature Range Output Current, Sinking Over Temperature Range Short Circuit Current Output Resistance POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current Over Temperature Range THERMAL CHARACTERISTICS Temperature Range Thermal Resistance, θJA P 8-Pin DIP U SO-8 E MSOP-8 ±2.2 ±2.2 ±2.0 75 65 65 35 ±3.0 ±2.5 ±2.3 110 85 150 0.08 ±5 ±11 ±2.4 ±2.4 ±2.2 T T T T T T T T T T T T f < 100kHz, G = +1 V V V mA mA mA mA mA Ω V V mA mA °C °C/W °C/W °C/W Both Channels, VS = ±5V ±4.5 ±5.5 ±15.5 ±17.5 +85 T T T T T T T T ±13.5 ±16 T Specification: P, U, E, PB, UB Junction to Ambient –40 100 125 150 NOTES: (1) An asterisk (T) specifies the same value as the grade to the left. (2) Frequency response can be strongly influenced by PC board parasitics. The demonstration boards show low parasitic layouts for this part. Refer to the demonstration board layout for details. (3) Slew rate is rate of change from 10% to 90% of output voltage step. ® OPA2650 2 ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................................................................. ±5.5V Internal Power Dissipation ........................... See Thermal Characteristics Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: P, PB, U, UB, E ............ –40 °C to +125°C Lead Temperature (DIP, soldering, 10s) ...................................... +300°C (SO-8 and MSOP-8, soldering, 3s) ................ +260°C Junction Temperature (TJ ) ............................................................ +175°C ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION Top View DIP/SO-8/MSOP-8 Output 1 –Input 1 +Input 1 –VS 1 2 3 4 8 7 6 5 +VS Output 2 –Input 2 +Input 2 PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 006 006 182 182 337 TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C PACKAGE MARKING(2) OPA2650P OPA2650PB OPA2650U OPA2650UB B50 ORDERING NUMBER(3) OPA2650P OPA2650PB OPA2650U OPA2650UB OPA2650E-250 OPA2650E-2500 PRODUCT OPA2650P OPA2650PB OPA2650U OPA2650UB OPA2650E PACKAGE 8-Pin Plastic DIP 8-Pin Plastic DIP SO-8 Surface Mount SO-8 Surface Mount MSOP-8 NOTE: (1) For detailed drawing and dimension table, see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) The “B” grade will be marked with a “B” by pin 8. (3) The MSOP-8 is available on 7" tape and reel with 250 parts, and on 14" tape and reel with 2500 parts. For example, ordering 250 pieces of “OPA2650E250” will get a single 250 piece tape and reel. Refer to Appendix B of Burr-Brown IC Data Book for detailed Tape and Reel Mechanical information. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA2650 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1. COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 100 AOL, PSR AND CMRR vs TEMPERATURE 100 AOL, PSR and CMRR (dB) Common Mode-Rejection (dB) 90 80 70 PSR– 60 50 40 AOL CMRR 90 80 PSR+ 70 60 –4 –3 –2 –1 0 1 2 3 4 Common-Mode Voltage (V) –50 –25 0 25 50 75 125 Temperature (°C) INPUT BIAS CURRENT vs TEMPERATURE 6 IB Input Bias Current (µA) 3 SUPPLY CURRENT vs TEMPERATURE 12 5 2 Supply Current (mA) Offset Voltage (mV) 11 4 VOS 1 10 IQ 3 –50 0 –25 0 25 50 75 100 Temperature (°C) 9 –75 –50 –25 0 25 50 75 100 125 Temperature (°C) OUTPUT CURRENT vs TEMPERATURE 110 Input Voltage Noise (nV/√Hz) Input Current Noise (pA/√Hz) INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY 100 Outrput Current (±mA) 100 IO + 90 Voltage Noise 10 80 – IO Non-inverting and Inverting Current Noise 1 100 1k 10k Frequency (Hz) 100k 1M 70 –50 –25 0 25 50 75 100 Temperature (°C) ® OPA2650 4 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25° C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1. RECOMMENDED ISOLATION RESISTANCE vs CAPACITIVE LOAD 40 SMALL SIGNAL TRANSIENT RESPONSE (G = +1) 200 160 Isolation Resistance, RISO (Ω) Output Voltage (mV) CL 1kΩ 30 25Ω 120 80 40 0 –40 –80 –120 –160 20 RISO OPA2650 10 0 0 20 40 60 L –200 80 100 Time (5ns/div) Capacitive Load, C (pF) LARGE SIGNAL TRANSIENT RESPONSE (G = +1) 2.0 1.6 1.2 Output Voltage (V) CLOSED-LOOP BANDWIDTH (G = +1) 6 3 DIP Bandwidth = 366MHz 0.8 0 –0.4 –0.8 –1.2 –1.6 –2.0 Time (5ns/div) Gain (dB) 0.4 0 –3 SO-8 Bandwidth = 331MHz –6 MSOP-8 Bandwidth = 281MHz 1M 10M Frequency (Hz) 100M 1G –9 CLOSED-LOOP BANDWIDTH (G = +2) 9 MSOP-8/SO-8/DIP Bandwidth = 108MHz 6 3 Gain (dB) CLOSED-LOOP BANDWIDTH (G = +5) 20 17 MSOP-8/SO-8/DIP Bandwidth = 31MHz 14 Gain (dB) 0 –3 –6 –9 1M 10M 100M 1G Frequency (Hz) 11 8 5 2 1M 10M Frequency (Hz) 100M ® 5 OPA2650 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1. CLOSED-LOOP BANDWIDTH (G = +10) 26 23 20 Gain (dB) 60 50 40 OPEN-LOOP GAIN AND PHASE vs FREQUENCY +45 0 –45 Phase –90 –135 –180 –225 1k 10k 100k 1M 10M Frequency (Hz) 100M 1G MSOP-8/SO-8/DIP Bandwidth = 16MHz Gain Gain (dB) 14 11 8 5 2 1M 10M Frequency (Hz) 100M 30 20 10 0 HARMONIC DISTORTION vs FREQUENCY (G = +1, VO = 2Vp-p) –45 –50 HARMONIC DISTORTION vs TEMPERATURE (G = +1, fO = 5MHz) –60 Harmonic Distortion (dBc) –55 –60 –65 –70 –75 –80 –85 –90 –95 100k 3fO 2fO 1M 10M Frequency (Hz) 100M Harmonic Distortion (dBc) –65 3fO –70 2fO –75 –80 –75 –50 –25 0 25 50 75 100 125 Temperature (°C) 5MHz HARMONIC DISTORTION vs OUTPUT SWING –60 G = +2 –50 10MHz HARMONIC DISTORTION vs OUTPUT SWING G = +2 Harmonic Distortion (dBc) –70 Harmonic Distortion (dBc) –60 3fO 2fO –80 3fO 2fO –70 –90 –80 –100 0.1 1 Output Swing (Vp-p) 10 –90 0.1 1 Output Swing (Vp-p) 10 ® OPA2650 6 Phase (°) 17 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25° C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1. HARMONIC DISTORTION vs GAIN (f = 5MHZ, VO = 2Vp-p) –40 3fO –50 Harmonic Distortion (dBc) –60 –70 2fO –80 1 2 3 4 5 6 7 8 9 10 Non-Inverting Gain (V/V) APPLICATIONS INFORMATION DISCUSSION OF PERFORMANCE The OPA2650 is a dual low power, wideband voltage feedback operational amplifier. Each channel is internally compensated to provide unity gain stability. The OPA2650’s voltage feedback architecture features true differential and fully symmetrical inputs. This minimizes offset errors, making the OPA2650 well suited for implementing filter and instrumentation designs. As a dual operational amplifier, OPA2650 is an ideal choice for designs requiring multiple channels where reduction of board space, power dissipation and cost are critical. Its AC performance is optimized to provide a gain bandwidth product of 160MHz and a fast 0.1% settling time of 11ns, which is an important consideration in high speed data conversion applications. Along with its excellent settling characteristics, the low DC input offset of ±1mV and drift of ±3µV/°C support high accuracy requirements. In applications requiring a higher slew rate and wider bandwidth, such as video and high bit rate digital communications, consider the dual current feedback OPA2658. CIRCUIT LAYOUT AND BASIC OPERATION Achieving optimum performance with a high frequency amplifier like the OPA2650 requires careful attention to layout parasitics and selection of external components. Recommendations for PC board layout and component selection include: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the two power pins to high frequency 0.1µF decoupling capacitors. At the pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA2650. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high frequency performance. Again, keep their leads as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and the inverting input pin are most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the package pins. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Even with a low parasitic capacitance shunting the resistor, excessively high resistor values can create significant time constants and degrade performance. Good metal film or surface mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this adds a pole and/or zero below 500MHz that can affect circuit ® 7 OPA2650 operation. Keep resistor values as low as possible consistent with output loading considerations. The 402Ω feedback used for the Typical Performance Plots is a good starting point for design. Note that a 25Ω feedback resistor, rather than a direct short, is suggested for a unity gain follower. This effectively reduces the Q of what would otherwise be a parasitic inductance (the feedback wire) into the parasitic capacitance at the inverting input. d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended RISO vs capacitive load. Low parasitic loads may not need an RISO since the OPA2650 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required and the 6dB signal loss intrinsic to doubly terminated transmission lines is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the distortion vs load plot. With a characteristic impedance defined based on board material and desired trace dimensions, a matching series resistor into the trace from the output of the amplifier is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; the total effective impedance should match the trace impedance. Multiple destination devices are best handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation loss of a doubly terminated line is unacceptable, a long trace can be series-terminated at the source end only. This will help isolate the line capacitance from the op amp output, but will not preserve signal integrity as well as a doubly terminated line. If the shunt impedance at the destination end is finite, there will be some signal attenuation due to the voltage divider formed by the series and shunt impedances. e) Sockets are not recommended for high speed parts like the OPA2650. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable response. Best results are obtained by soldering the part onto the board. If socketing for the DIP package is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. SUPPLY VOLTAGES The OPA2650 is nominally specified for operation using ±5V power supplies. A 10% tolerance on the supplies, or an ECL –5.2V for the negative supply, is within the maximum speci® fied total supply voltage of 11V. Higher supply voltages can break down internal junctions possibly leading to catastrophic failure. Single supply operation is possible as long as common mode voltage constraints are observed. The common mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow non-standard or single supply operation. Figure 1 shows one approach to single-supply operation. +VS R VAC R VS 2 +VS VOUT = VS + 2•VAC 2 ROUT 1/2 OPA2650 RL 402Ω 402Ω FIGURE 1. Single Supply Operation. OFFSET VOLTAGE ADJUSTMENT If additional offset adjustment is needed, the circuit in Figure 2 can be used without degrading offset drift with temperature. Avoid external adjustment whenever possible since extraneous noise, such as power supply noise, can be inadvertently coupled into the amplifier’s inverting input terminal. Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible, match the impedance seen by both inputs as is shown with R3. This will reduce the output offset voltage caused by the amplifier’s input offset current. +VCC R2 RTrim 47kΩ 1/2 OPA2650 20kΩ –VCC NOTE: (1) R3 is optional and can be used to cancel offset errors due to input bias currents. 0.1µF R1 (1) R3 = R1 || R2 VIN or Ground Output Trim Range ≅ +VCC R2 RTrim to –VCC R2 RTrim FIGURE 2. Offset Voltage Trim. OPA2650 8 ESD PROTECTION ESD damage has been well recognized for MOSFET devices, but any semiconductor device is vulnerable to this potentially damaging source. This is particularly true for very high speed, fine geometry processes. ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, ESD handling precautions are strongly recommended when handling the OPA2650. OUTPUT DRIVE CAPABILITY The OPA2650 has been optimized to drive 75Ω and 100Ω resistive loads. The device can drive 2Vp-p into a 75Ω load. This high-output drive capability makes the OPA2650 an ideal choice for a wide range of RF, IF, and video applications. In many cases, additional buffer amplifiers are unneeded. Many demanding high-speed applications such as driving A/D converters require op amps with low wideband output impedance. For example, low output impedance is essential when driving the signal-dependent capacitances at the inputs of flash A/D converters. As shown in Figure 3, the OPA2650 maintains very low-closed loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain decreases with frequency. SMALL-SIGNAL OUTPUT IMPEDANCE vs FREQUENCY 1k G = +1 Output Impedance (Ω) supply current for both channels times the total supply voltage across the part. PDL1 and PDL2 will depend on the required output signals and loads. For a grounded resistive loads, and equal bipolar supplies, they would be at a maximum when the outputs are fixed at a voltage equal to 1/2 either supply voltage. Under this condition, PDL1 = VS2/ (4•RL1) where RL1 includes feedback network loading. P DL2 is calculated the same way. Note that it is the power in the output stages, and not into the loads, that determines internal power dissipation. Operating junction temperature (TJ) is given by TA + PD θJA, where TA is the ambient temperature. As an example, compute the maximum TJ for an OPA2650U where both op amps are at G = +2, RL = 100Ω, RFB = 402Ω, ±VS = ±5V, and at the specified maximum TA = +85°C. This gives: P DQ = (10V •17.5mA ) = 175mW P DL1 = P DL2 = 4 • (100 Ω || 804 Ω ) (5V )2 = 70mW P D = 175mW + 2 ( 70mW ) = 315mW T J = 85° C + 0.315W •125° C / W = 124° C CAPACITIVE LOADS The OPA2650’s output stage has been optimized to drive low resistive loads. Capacitive loads, however, will decrease the amplifier’s phase margin which may cause high frequency peaking or oscillations. Capacitive loads greater than 10pF should be isolated by connecting a small resistance, usually 15Ω to 30Ω, in series with the output as shown in Figure 4. This is particularly important when driving high capacitance loads such as flash A/D converters. Increasing the gain from +1 will improve the capacitive load drive due to increased phase margin. In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if the cable is properly terminated. The capacitance of coax cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable or transmission line is terminated in its characteristic impedance. 100 10 1 0.1 0.01 10k 100k 1M Frequency (Hz) 10M 100M FIGURE 3. Small-Signal Output Impedance vs Frequency. 25Ω (RISO typically 15Ω to 30Ω) THERMAL CONSIDERATIONS The OPA2650 will not require heatsinking under most operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. The total internal power dissipation (PD) is a the sum of quiescent power (PDQ) and additional power dissipated in the two output stages (PDL1 and PDL2) while delivering load power. Quiescent power is simply the specified no-load RISO OPA2650 RL CL FIGURE 4. Driving Capacitive Loads. ® 9 OPA2650 FREQUENCY RESPONSE COMPENSATION Each channel of the OPA2650 is internally compensated to be stable at unity gain with a nominal 60° phase margin. This lends itself well to wideband integrator and buffer applications. Phase margin and frequency response flatness will improve at higher gains. Recall that an inverting gain of –1 is equivalent to a gain of +2 for bandwidth purposes, i.e., noise gain = 2. The external compensation techniques developed for voltage feedback op amps can be applied to this device. For example, in the non-inverting configuration, placing a capacitor across the feedback resistor will reduce the gain to +1 starting at f = (1/2πRFCF). Alternatively, in the inverting configuration, the bandwidth may be limited without modifying the inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing the noise gain at high frequencies, thereby limiting the bandwidth for the inverting input signal through the gain-bandwidth product. At higher gains, the gain-bandwidth of this voltage feedback topology will limit bandwidth according to the open-loop frequency response curve. For applications requiring a wider bandwidth at higher gains, consider the dual current feedback model, OPA2658. In applications where a large feedback resistor is required (such as photodiode transimpedance circuits), precautions must be taken to avoid gain peaking due to the pole formed by the feedback resistor and the capacitance on the inverting input. This pole can be compensated by connecting a small capacitor in parallel with the feedback resistor, creating a cancelling zero term. In other high-gain applications, use of a three-resistor “T” connection will reduce the feedback network impedance which reacts with the parasitic capacitance at the summing node. PULSE SETTLING TIME High speed amplifiers like the OPA2650 are capable of extremely fast settling time with a pulse input. Excellent frequency response flatness and phase linearity are required to get the best settling times. As shown in the specifications table, settling time for a 2V step at a gain of +1 for the OPA2650 is extremely fast. The specification is defined as the time required, after the input transition, for the output to settle within a specified error band around its final value. For a 2V step, 1% settling corresponds to an error band of ±20mV, 0.1% to an error band of ±2mV, and 0.01% to an error band of ±0.2mV. For the best settling times, particularly into an ADC capacitive load, little or no peaking in the frequency response can be allowed. Using the recommended RISO for capacitive loads will limit this peaking and reduce the settling times. Fast, extremely fine scale settling (0.01%) requires close attention to ground return currents in the supply decoupling capacitors. For highest performance, consider the OPA642 which offers considerably higher open loop DC gain. DIFFERENTIAL GAIN AND PHASE Differential Gain (dG) and Differential Phase (dP) are among the more important specifications for video applications. ® The percentage change in closed-loop gain over a specified change in output voltage level is defined as dG. dP is defined as the change in degrees of the closed-loop phase over the same output voltage change. dG and dP are both specified at the NTSC sub-carrier frequency of 3.58MHz. dG and dP increase closed-loop gain and output voltage transition. All measurements were performed using a Tektronix model VM700 Video Measurement Set. DISTORTION The OPA2650’s harmonic distortion characteristics into a 100Ω load are shown versus frequency and power output in the typical performance curves. Distortion can be significantly improved by increasing the load resistance as illustrated in Figure 5. Remember to include the contribution of the feedback resistance when calculating the effective load resistance seen by the amplifier. –60 (G = +1, fO = 5MHz) Harmonic Distortion (dBc) –70 2fO –80 3fO –90 10 20 50 100 200 500 1k Load Resistance (Ω) FIGURE 5. 5MHz Harmonic Distortion vs Load Resistance. CROSSTALK Crosstalk is the undesired result of the signal of one channel mixing with and reproducing itself in the output of the other channel. Crosstalk occurs in most multichannel integrated circuits. In dual devices, the effect of crosstalk is measured by driving one channel and observing the output of the undriven channel over various frequencies. The magnitude of this effect is referenced in terms of channel-to-channel crosstalk and expressed in decibels. “Input referred” points to the fact that there is a direct correlation between gain and crosstalk, therefore at increased gain, crosstalk also increases by a factor equal to that of the gain. Figure 6 illustrates the measured effect of crosstalk in the OPA2650U. SPICE MODELS Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. SPICE models are available on a disk from the Burr-Brown Applications Department. OPA2650 10 0 –10 –20 Crosstalk (dB) G = +1 –30 –40 –50 –60 –70 –80 –90 –100 1M 10M Frequency (Hz) 100M 400M DEMONSTRATION BOARDS Demonstration boards are available for each OPA2650 package style. These boards implement a very low parasitic layout that will produce the excellent frequency and pulse responses shown in the Typical Performance Curves. For each package style, the recommended demonstration boards are: DEMONSTRATION BOARD DEM-OPA265xP DEM-OPA265xU DEM-OPA26xxE PACKAGE 8-Pin DIP SO-8 MSOP-8 PRODUCT OPA2650P OPA2650PB OPA2650U OPA2650UB OPA2650E FIGURE 6. Channel-to-Channel Crosstalk. Contact your local Burr-Brown sales office or distributor to order demonstration boards. TYPICAL APPLICATION 402Ω 402Ω 75Ω Transmission Line 1/2 OPA2650 Video Input 75Ω 75Ω VOUT 75Ω FIGURE 7. Low Distortion Video Amplifier. ® 11 OPA2650 J5 –InB R11 R12 R13 R16 C3 2.2µF C1 0.1µF 1 2 P1 +5V GND 6 J4 +InB R8 R10 R9 5 8 1/2 OPA2650 7 R14 J6 OutB J2 –InA R2 R3 R4 R15 2 J3 +InA R5 R6 3 1/2 OPA2650 4 C2 0.1µF C4 2.2µF 1 R1 J1 OutA 1 GND –5V P2 R7 2 FIGURE 8. Circuit Detail for DEM-OPA265xP Demonstration Board. DEM-OPA265xP Demonstration Board Layout (A) (B) (C) (D) FIGURE 9. Evaluation Board Silkscreen (Solder Side). 9b. Evaluation Board Silkscreen (Component Side). 9c. Evaluation Board Layout (Solder Side). 9d. Evaluation Board (Component Side). ® OPA2650 12