OPA694IDBVTG4

OP A6 94 OP A6 94 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 Wideband, Low-Power, Current Feedback Operational Amplifier Check for Samples: OPA694 FEATURES 1 • • • • • • 2 • UNITY GAIN STABLE BANDWIDTH: 1.5GHz HIGH GAIN OF 2V/V BANDWIDTH: 690MHz LOW SUPPLY CURRENT: 5.8mA HIGH SLEW RATE: 1700V/msec HIGH FULL-POWER BANDWIDTH: 675MHz LOW DIFFERENTIAL GAIN/PHASE: 0.03%/0.015° Pb-FREE AND GREEN SOT23-5 PACKAGE APPLICATIONS • • • • • WIDEBAND VIDEO LINE DRIVER MATRIX SWITCH BUFFER DIFFERENTIAL RECEIVER ADC DRIVER IMPROVED REPLACEMENT FOR OPA658 DESCRIPTION The OPA694 is an ultra-wideband, low-power, current feedback operational amplifier featuring high slew rate and low differential gain/phase errors. An improved output stage provides ±80mA output drive with < 1.5V output voltage headroom. Low supply current with > 500MHz bandwidth meets the requirements of high-density video routers. Being a current feedback design, the OPA694 holds its bandwidth to very high gains—at a gain of 10, the OPA694 will still provide 200MHz bandwidth. RF applications can use the OPA694 as a low-power SAW pre-amplifier. Extremely high 3rd-order intercept is provided through 70MHz at much lower quiescent power than many typical RF amplifiers. The OPA694 is available in an industry-standard pinout in both SO-8 and SOT23-5 packages. +5V OPA694 RELATED PRODUCTS SINGLES DUALS TRIPLES QUADS FEATURES — OPA2694 — — Dual Version OPA683 OPA2683 — — Low-Power, CFBPlus OPA684 OPA2684 OPA3684 OPA4684 Low-Power, CFBPlus OPA691 OPA2691 OPA3691 — High Output OPA695 OPA2695 OPA3695 — High Intercept VIN 75W VLOAD RG-59 OPA694 75W 75W 402W 402W -5V Gain 2V/V Video Line Driver 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2010, Texas Instruments Incorporated OPA694 SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA694 SO-8 D -40°C to +85°C OPA694 OPA694 SOT23-5 DBV -40°C to +85°C BIA (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA694ID Rails, 100 OPA694IDR Tape and Reel, 2500 OPA694IDBVT Tape and Reel, 250 OPA694IDBVR Tape and Reel, 3000 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Power Supply Internal Power Dissipation OPA694 UNIT ±6.5 VDC See Thermal Characteristics Differential Input Voltage ±1.2 Input Voltage Range ±VS V –65 to +125 °C Storage Temperature Range: D, DBV Junction Temperature (TJ) ESD Ratings: (1) V +150 °C Human Body Model (HBM) 1500 V Charge Device Model (CDM) 1000 V Machine Model (MM) 100 V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. D PACKAGE SO-8 (TOP VIEW) DRB PACKAGE SOT23-5 (TOP VIEW) 1 8 NC Inverting Input 2 7 +VS Noninverting Input 3 6 Output -VS 4 5 NC Output 1 -VS 2 Noninverting Input 3 5 +VS 4 Inverting Input 4 5 NC 3 2 1 BIA Pin Orientation/Package Marking 2 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. OPA694ID, IDBV MIN/MAX OVER TEMPERATURE TYP 0°C to +70°C ( PARAMETER +25°C (2) 3) TEST CONDITIONS +25°C G = +1, VO = 0.5VPP, RF = 430Ω 1500 G = +2, VO = 0.5VPP, RF = 402Ω 690 350 340 G = +5, VO = 0.5VPP, RF = 318Ω 250 200 180 G = +10, VO = 0.5VPP, RF = 178Ω 200 150 130 G = +1, VO = 0.5VPP, RF = 430Ω 90 -40°C to +85°C (3) UNIT MIN/ MAX TEST LEVELS (1) MHz typ C 330 MHz min B 160 MHz min B 120 MHz min B MHz typ C AC Performance (see Figure 31) Small-Signal Bandwidth Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 VO ≤ 0.1VPP, RF = 430Ω 2 dB typ C Large-Signal Bandwidth G = +2, VO = 2VPP 675 MHz typ C G = +2, 2V Step 1700 V/ms min B G = +2, VO = 0.2V Step 0.8 ns typ C Settling Time to 0.01% G = +2, VO = 2V Step 20 ns typ C Settling Time to 0.1% G = +2, VO = 2V Step 13 ns typ C — — — Slew Rate Rise Time and Fall Time 1300 1275 1250 Harmonic Distortion G = +2, f = 5MHz, VO = 2VPP xx x 2nd-Harmonic RL = 100Ω –68 –63 –62 –61 dBc max B RL ≥ 500Ω –92 –87 –85 –83 dBc max B RL = 100Ω –72 –69 –67 –66 dBc max B RL ≥ 500Ω –93 –88 –86 –84 dBc max B Input Voltage Noise Density f > 1MHz 2.1 2.4 2.8 3.0 nV/√Hz max B Inverting Input Current Noise Density f > 1MHz 22 24 26 28 pA/√Hz max B Noninverting Input Current Noise Density f > 1MHz 24 26 28 30 pA/√Hz max B xx x 3rd-Harmonic NTSC Differential Gain NTSC Differential Phase VO - 1.4VPP, RL = 150Ω 0.03 % max C VO - 1.4VPP, RL = 37.5Ω 0.05 % max C G = +2, VO - 1.4VPP, RL = 150Ω 0.015 ° typ C VO - 1.4VPP, RL = 37.5Ω 0.16 ° typ C DC PERFORMANCE (4) Open-Loop Transimpedance VO = 0V, RL = 100Ω 145 90 65 60 kΩ min A Input Offset Voltage VCM = 0V ±0.5 ±3.0 ±3.7 ±4.1 mV max A Average Input Offset Voltage Drift VCM = 0V 12 15 mV/°C max B Noninverting Input Bias Current VCM = 0V ±26 ±31 mA max A Average Input Bias Current Drift VCM = 0V ±100 ±150 nA/°C max B Inverting Input Bias Current VCM = 0V ±26 ±38 mA max A Average Input Bias Current Drift VCM = 0V ±150 ±200 nA/°C max B ±5 ±2 ±20 ±18 INPUT Common-mode Input Voltage (5) (CMIR) Common-Mode Rejection Ratio (CMRR) VCM = 0V Noninverting Input Impedance Inverting Input Resistance (1) (2) (3) (4) (5) Open-Loop ±2.5 ±2.3 ±2.2 ±2.1 V min A 60 55 53 51 dB min A 280 | | 1.2 kΩ | | pF typ C 30 Ω typ C Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over temperature specifications. Current is considered positive out of node. VCM is the input common-mode voltage. Tested < 3dB below minimum specified CMRR at ±CMIR limits. 3 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. OPA694ID, IDBV MIN/MAX OVER TEMPERATURE TYP 0°C to +70°C ( PARAMETER TEST CONDITIONS +25°C +25°C (2) 3) -40°C to +85°C (3) UNIT MIN/ MAX TEST LEVELS (1) OUTPUT Voltage Output Voltage No Load ±4 ±3.8 ±3.7 ±3.6 V min A RL = 100Ω ±3.4 ±3.1 ±3.1 ±3.0 V min A Output Current VO = 0V ±80 ±60 ±58 ±50 mA min A Short-Circuit Output Current VO = 0V ±200 mA min C G = +2, f =100kHz 0.02 Ω typ C ±5 V typ C Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range ±6.3 ±6.3 ±6.3 V max A Minimum Operating Voltage Range ±3.5 ±3.5 ±3.5 V max B Maximum Quiescent Current VS = ±5V 5.8 6.0 6.2 6.3 mA max A Minimum Quiescent Current VS = ±5V 5.8 5.6 5.3 5.0 mA min A Power-Supply Rejection Ratio (PSRR) Input-Referred 58 54 52 50 dB min A THERMAL CHARACTERISTICS Specification: ID, IDBV -40 to +85 °C typ C — — — — xx x D xxxx x SO-8 125 °C/W typ C xx x DBV xxx SOT23 150 °C/W typ C Thermal Resistance, q JA Junction-to-Ambient 4 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS: VS = ±5V At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE INVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 3 -3 -6 G = +10V/V RF = 178W G = +5V/V RF = 318W -9 G = -5V/V RF = 318W 0 Normalized Gain (dB) G = +2V/V RF = 402W 0 Normalized Gain (dB) VO = 0.5VPP RL = 100W G = -1V/V RF = 430W -3 -6 G = -10V/V RF = 500W -9 -12 G = -2V/V RF = 402W -15 See Figure 31 See Figure 32 -18 -12 0 200 400 600 800 1000 0 200 400 600 800 1000 Frequency (MHz) Frequency (MHz) Figure 1. Figure 2. NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE INVERTING LARGE−SIGNAL FREQUENCY RESPONSE 9 9 VO = 1VPP 6 G = +2V/V RF = 402W 6 VO = 4VPP V = 2V O PP 3 Gain (dB) Gain (dB) 3 0 VO = 2VPP -3 -6 0 VO = 1VPP -3 VO = 7VPP -6 VO = 7VPP VO = 4VPP -9 G = -2V/V RF = 402W See Figure 32 -9 See Figure 31 -12 -12 0 200 400 600 800 1000 0 Figure 4. 0.2 0 -0.2 -2 -0.4 -0.6 2 Output Voltage (1V/div) 0.4 -1 -3 0.6 See Figure 32 G = -2V/V 1 0 Large Signal, 5VPP Left Scale Small Signal, 0.5VPP Right Scale 0.4 0.2 0 -1 -0.2 -2 -0.4 -3 Time (5ns/div) Output Voltage (200mV/div) Small Signal, 0.5VPP Right Scale 1000 INVERTING PULSE RESPONSE See Figure 31 Large Signal, 5VPP Left Scale 800 3 0.6 Output Voltage (200mV/div) 0 600 Figure 3. G = +2V/V 1 400 Frequency (MHz) NONINVERTING PULSE RESPONSE 2 200 Frequency (MHz) 3 Output Voltage (1V/div) VO = 0.5VPP RL = 100W -0.6 Time (5ns/div) Figure 5. Figure 6. 5 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5V (continued) At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE G = +2V/V f = 5MHz VO = 2VPP Harmonic Distortion (dBc) -70 -75 2nd Harmonic -80 -85 3rd Harmonic -90 -60 Harmonic Distortion (dBc) -65 HARMONIC DISTORTION vs SUPPLY VOLTAGE G = +2V/V f = 5MHz RL = 100W VO = 2VPP -65 2nd Harmonic -70 3rd Harmonic -75 -95 See Figure 31 -100 100 See Figure 31 -80 1000 3.5 4.0 Load Resistance (W) Figure 8. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE Harmonic Distortion (dBc) Harmonic Distortion (dBc) -65 G = +2V/V RL = 100W VO = 2VPP 2nd Harmonic -70 -80 3rd Harmonic -90 G = +2V/V RL = 100W f = 5MHz -70 5.5 6.0 2nd Harmonic -75 3rd Harmonic -80 See Figure 31 See Figure 31 -100 -85 0.1 1 10 20 0.1 1 Frequency (MHz) 10 Output Voltage Swing (VPP) Figure 9. Figure 10. HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN -60 -60 RL = 100W f = 5MHz VO = 2VPP Harmonic Distortion (dBc) Harmonic Distortion (dBc) 5.0 Figure 7. -50 -60 4.5 Supply Voltage (±VS) -65 2nd Harmonic -70 3rd Harmonic RL = 100W f = 5MHz VO = 2VPP 2nd Harmonic -65 -70 3rd Harmonic See Figure 31 See Figure 32 -75 -75 1 10 1 Gain (V/V) 10 Gain (|V/V|) Figure 11. Figure 12. 6 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. TWO−TONE, THIRD−ORDER INTERMODULATION INTERCEPT INPUT VOLTAGE AND CURRENT NOISE 55 1k 50W PI Intercept Point (+dBm) Voltage Noise (nV/ÖHz) Current Noise (pA/ÖHz) 50 Noninverting Current Noise (24pA/ÖHz) 100 Inverting Current Noise (22pA/ÖHz) 10 PO OPA694 50W 50W 402W 45 402W 40 35 30 Voltage Noise (2.1nV/ÖHz) 25 20 1 10 100 1k 10k 100k 1M 10M 100M 0 10 20 30 Frequency (Hz) 40 50 60 70 90 Figure 13. Figure 14. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 100 3 60 CL = 10pF 0dB Peaking Targeted 0 Normalized Gain (dB) 50 40 RS (W) 80 Frequency (MHz) 30 20 CL = 22pF CL = 100pF -3 CL = 47pF -6 RS VI -9 -15 0 -18 CL 402W -12 10 VO OPA694 50W 1kW (1) 402W NOTE: (1) 1kW load is optional 10 1M 100 10M 100M 1G Frequency (Hz) Capacitive Load (pF) Figure 15. Figure 16. COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs FREQUENCY OPEN−LOOP ZOL GAIN AND PHASE 70 120 30 110 0 100 -30 60 CMRR (dB) PSRR (dB) 50 40 -PSRR 30 20 < ZOL 80 20 log |ZOL| 60 1k 10k 100k 1M 10M 100M 40 100 Frequency (Hz) Figure 17. -60 -90 -120 70 -150 -180 50 10 0 100 90 Open-Loop ZOL Phase (°) +PSRR Open-Loop ZOL Gain (dBW) CMRR -210 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) Figure 18. 7 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5V (continued) At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE (No Pulldown) 0.08 TYPICAL DC DRIFT OVER TEMPERATURE 0.08 dG Negative Video 0.02 0.04 Input Offset Voltage (mV) Differential Gain (%) 0.04 Differential Phase (°) 0.12 dG Positive Video Input Offset Voltage (VOS) Left Scale 0.5 Inverting Input Bias Current (IBI) Right Scale 0 5 0 Noninverting Input Bias Current (IBN) Right Scale -5 -0.5 dP Negative Video 0 -1.0 -50 0 1 2 3 4 -25 0 +25 Figure 19. 1W Internal Power Limit 90 RL = 50W RL = 25W 0 Output Current (mA) RL = 100W Output Current Limit Output Current Limit 80 8 Sinking Output Current Left Scale 70 7 Supply Current 60 6 Right Scale 50 -3 1W Internal Power Limit -4 -200 -100 0 100 40 -50 200 5 -25 Output Current (mA) 0 +25 NONINVERTING OVERDRIVE RECOVERY 4 4 Output Voltage (V) 2 2 Input Right Scale 0 0 Output Left Scale -2 -2 -4 -4 Input Voltage (V) 0 Input Voltage (V) Output Left Scale -4 4 +125 RL = 100W G = -1V/V RL = 100W G = +2V/V 2 0 +100 INVERTING OVERDRIVE RECOVERY 4 4 +75 Figure 22. 8 Input Right Scale +50 Ambient Temperature (°C) Figure 21. Output Voltage (V) 9 Left Scale Supply Current (mA) Output Voltage (V) 10 Sourcing Output Current 1 -2 -10 +125 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 100 3 -1 +100 Figure 20. OUTPUT VOLTAGE AND CURRENT LIMITATIONS 2 +75 Ambient Temperature (°C) Video Loads 4 +50 Input Bias and Offset Current (mA) dP Positive Video 0.06 10 1.0 0.16 -2 See Figure 32 See Figure 31 -8 -4 Time (10ns/div) Time (10ns/div) Figure 23. Figure 24. 8 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. DIFFERENTIAL PERFORMANCE TEST CIRCUIT DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE 3 VO = 2VPP RL = 400W +5V Normalized Gain (dB) 0 OPA694 RG RF RG RF VI RT RL 400W VO GD = 1 GD = 2 RF = 430W R = 402W F -3 -6 GD = 5 RF = 330W -9 OPA694 VO VI = RF RG GD = 10 RF = 250W -12 0 = GD 50 100 150 200 250 300 350 400 450 500 Frequency (MHz) -5V Figure 25. Figure 26. DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE -60 9 Harmonic Distortion (dBc) GD = 2 RL = 400W 6 Gain (dB) VO = 12VPP 3 0 VO = 5VPP VO = 16VPP -3 VO = 8VPP VO = 4VPP f = 5MHz GD = 2 -65 3rd Harmonic -70 -75 -80 -85 2nd Harmonic -90 -6 0 50 100 150 200 250 300 350 400 450 10 500 100 Figure 27. Figure 28. DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE -65 GD = 2 VO = 4VPP RL = 400W 3rd Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) -55 -65 1000 Resistance (W) Frequency (MHz) -75 2nd Harmonic -85 -95 -105 GD = 2 f = 5MHz RL = 400W -70 -75 3rd Harmonic -80 -85 -90 2nd Harmonic -95 1 10 20 0.1 Frequency (MHz) 1 10 100 Output Voltage Swing (VPP) Figure 29. Figure 30. 9 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 www.ti.com APPLICATION INFORMATION WIDEBAND CURRENT FEEDBACK OPERATION The OPA694 provides exceptional AC performance for a wideband, low-power, current-feedback operational amplifier. Requiring only 5.8mA quiescent current, the OPA694 offers a 690MHz bandwidth at a gain of +2, along with a 1700V/ms slew rate. An improved output stage provides ±80mA output drive, along with < 1.5V output voltage headroom. This combination of low power and high bandwidth can benefit high-resolution video applications. Figure 31 shows the DC-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±5V Electrical Characteristics table and Typical Characteristic curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the Electrical Characteristics are taken directly at the input and output pins, while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 31, the total effective load will be 100Ω || 804Ω = 89Ω. One optional component is included in Figure 31. In addition to the usual power-supply decoupling capacitors to ground, a 0.1mF capacitor is included between the two power-supply pins. In practical printed circuit board (PCB) layouts, this optional added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. 0.1mF +5V +VS +5V +VS + 0.1mF VO 50W Optional 0.01mF VO 50W 50W Load RG 200W RF 402W VI OPA694 0.1mF 50W Load OPA694 50W Source 50W 6.8mF 20W 6.8mF + 50W Source VI rate for inverting operation is higher and the distortion performance is slightly improved. An additional input resistor, RT, is included in Figure 32 to set the input impedance equal to 50Ω. The parallel combination of RT and RG sets the input impedance. Both the noninverting and inverting applications of Figure 31 and Figure 32 will benefit from optimizing the feedback resistor (RF) value for bandwidth (see the discussion in the Setting Resistor Values to Optimize Bandwidth section). The typical design sequence is to select the RF value for best bandwidth, set RG for the gain, then set RT for the desired input impedance. As the gain increases for the inverting configuration, a point will be reached where RG will equal 50Ω, where RT is removed and the input match is set by RG only. With RG fixed to achieve an input match to 50Ω, RF is simply increased, to increase gain. This will, however, quickly reduce the achievable bandwidth, as shown by the inverting gain of –10 frequency response in the Typical Characteristic curves. For gains > 10V/V (14dB at the matched load), noninverting operation is recommended to maintain broader bandwidth. RT 66.5W 0.1mF + 6.8mF -VS -5V RF 402W Figure 32. DC-Coupled, G = −2V/V, Bipolar-Supply Specification and Test Circuit RG 402W -VS -5V + 6.8mF 0.1mF ADC DRIVER Figure 31. DC-Coupled, G = +2, Bipolar-Supply Specification and Test Circuit Figure 32 shows the DC-coupled, gain of −2V/V, dual power-supply circuit used as the basis of the inverting Typical Characteristic curves. Inverting operation offers several performance benefits. Since there is no common-mode signal across the input stage, the slew Most modern, high-performance analog-to-digital converters (ADCs) require a low-noise, low-distortion driver. The OPA694 combines low-voltage noise (2.1nV/√Hz) with low harmonic distortion. See Figure 33 for an example of a wideband, AC-coupled, 12-bit ADC driver. 10 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 Two OPA694s are used in the circuit of Figure 33 to form a differential driver for a 12-bit ADC. The two OPA694s offer > 250MHz bandwidth at a differential gain of 5V/V, with a 2VPP output swing. A 2nd-order RLC filter is used in order to limit the noise from the amplifier and provide some attenuation for higher-frequency harmonic distortion. have been adjusted to maintain both maximum bandwidth and input impedance matching. If each RF signal is assumed to be driven from a 50Ω source, the NG for this circuit will be [1 + 100Ω/(100Ω/5)] = 6. The total feedback impedance (from VO to the inverting error current) is the sum of RF + (RI • NG), where RI is the impedance looking into the inverting input from the summing junction (see the Setting Resistor Values to Optimize Performance section). Using 100Ω feedback (to get a signal gain of –2 from each input to the output pin) requires an additional 30Ω in series with the inverting input to increase the feedback impedance. With this resistor added to the typical internal RI = 30Ω, the total feedback impedance is 100Ω + (60Ω • 6) = 460Ω, which is equal to the required value to get a maximum bandwidth flat frequency response for NG = 6. WIDEBAND INVERTING SUMMING AMPLIFIER Since the signal bandwidth for a current-feedback op amp can be controlled independently of the noise gain (NG, which is normally the same as the noninverting signal gain), wideband inverting summing stages may be implemented using the OPA694. The circuit in Figure 34 shows an example inverting summing amplifier, where the resistor values +5V Power-supply decoupling not shown. C1 25W 1:2 R1 L OPA694 100W V+ 500W C R2 VI 50W 12-Bit ADC VCM 500W 100W 0.1mF R2 C1 Single-to-Differential Gain of 10 R1 L V- OPA694 25W -5V Figure 33. Wideband, AC-Coupled, Low-Power ADC Driver +5V 50W V1 50W 50W VO = -(V1 + V2 + V3 + V4 + V5) OPA694 V2 RG-58 50W 50W 30W V3 100W 50W 100MHz, -1dB Compression = 15dBm V4 50W -5V V5 Figure 34. 200MHz RF Summing Amplifier 11 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 www.ti.com SAW FILTER BUFFER One common requirement in an IF strip is to buffer the output of a mixer with enough gain to recover the insertion loss of a narrowband SAW filter. Figure 35 shows one possible configuration driving a SAW filter. The Two-Tone, Third-Order Intermodulation Intercept plot (Figure 14) is shown in the Typical Characteristics curves. Operating in the inverting mode at a voltage gain of –8V/V, this circuit provides a 50Ω input match using the gain set resistor, has the feedback optimized for maximum bandwidth (250MHz in this case), and drives through a 50Ω output resistor into the matching network at the input of the SAW filter. If the SAW filter gives a 12dB insertion loss, a net gain of 0dB to the 50Ω load at the output of the SAW (which could be the input impedance of the next IF amplifier or mixer) will be delivered in the passband of the SAW filter. Using the OPA694 in this application will isolate the first mixer from the impedance of the SAW filter and provide very low two-tone, 3rd-order spurious levels in the SAW filter bandwidth. small-signal frequency response for the unity gain buffer of Figure 31 compared to the improved approach shown in Figure 36. Either approach gives a low-power unity-gain buffer with > 1.56GHz bandwidth. +5V RO VO 50W OPA694 RG 430W RF 430W VI RM 50W -5V Figure 36. Improve Unity Gain Buffer 3 G = +1, Figure 1 +12V 5kW 50W 1000pF 0.1mF 5kW Matching Network OPA694 PO 50W SAW Filter 50W Source 1000pF 50W G = +1, Figure 6 -3 -6 -9 400W PO PI Normalized Gain (dB) 0 PI = 12dB - (SAW Loss) -12 10M 100M Figure 35. IF Amplifier Driving SAW Filter WIDEBAND UNITY GAIN BUFFER WITH IMPROVED FLATNESS The unity gain buffer configuration of Figure 31 shows a peaking in the frequency response exceeding 2dB. This gives the slight amount of overshoot and ringing apparent in the gain of +1V/V pulse response curves. A similar circuit that holds a flatter frequency response, giving improved pulse fidelity, is shown in Figure 36. This circuit removes the peaking by bootstrapping out any parasitic effects on RG. The input impedance is still set by RM as the apparent impedance looking into RG is very high. RM may be increased to show a higher input impedance, but larger values will start to impact DC output offset voltage. This circuit creates an additional input offset voltage as the difference in the two input bias currents times the impedance to ground at VI. Figure 37 shows a comparison of 1G 3G Frequency (Hz) Figure 37. Gain of +1 Frequency Response DESIGN-IN TOOLS DEMONSTRATION FIXTURES Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA694 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered with a user’s guide. The summary information for these fixtures is shown in Table 1. Table 1. Demonstration Fixtures by Package ORDERING NUMBER LITERATURE NUMBER SO-8 DEM-OPASO-1B SBOU026 SOT23-5 DEM-OPASOT-1B SBOU027 PRODUCT PACKAGE OPA694ID OPA694IDBV 12 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA694 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA694 is available through the TI web site (www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/df characteristics. These models do not attempt to distinguish between package types in their small-signal AC performance. OPERATING SUGGESTIONS space SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH A current-feedback op amp like the OPA694 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values. This is shown in the Typical Characteristic curves; the small-signal bandwidth decreases only slightly with increasing gain. Those curves also show that the feedback resistor has been changed for each gain setting. The resistor values on the inverting side of the circuit for a current-feedback op amp can be treated as frequency response compensation elements while their ratios set the signal gain. Figure 38 shows the small-signal frequency response analysis circuit for the OPA694. VI a VO RI iERR Z(S) iERR RF RG Figure 38. Recommended Feedback Resistor Versus Noise Gain The key elements of this current-feedback op amp model are: a → Buffer gain from the noninverting input to the inverting input RI → Buffer output impedance iERR → Feedback error current signal Z(s) → Frequency-dependent, open-loop transimpedance gain from iERR to VO The buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. It will, however, set the CMRR for a single op amp differential amplifier configuration. For a buffer gain a < 1.0, the CMRR = –20 × log (1– a) dB. RI, the buffer output impedance, is a critical portion of the bandwidth control equation. RI for the OPA694 is typically about 30Ω. A current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. The Typical Characteristics show this open-loop transimpedance response. This is analogous to the open-loop voltage gain curve for a voltage-feedback op amp. Developing the transfer function for the circuit of Figure 38 gives Equation 1: R a 1+ F RG VO aNG = = VI RF + RI·NG R RF + RI 1 + F RG Z(s) 1+ Z(s) (1) ( ( ( ( where: ( NG = 1 + RF RG ( This is written in a loop-gain analysis format, where the errors arising from a noninfinite open-loop gain are shown in the denominator. If Z(s) were infinite over all frequencies, the denominator of Equation 1 would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. The fraction in the denominator of Equation 1 determines the frequency response. Equation 2 shows this as the loop-gain equation: Z(s) = Loop Gain RF + RI·NG (2) If 20 × log(RF + NG × RI) were drawn on top of the open-loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. Eventually, Z(s) rolls off to equal the denominator of Equation 2, at which point the loop 13 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 www.ti.com gain reduces to 1 (and the curves intersect). This point of equality is where the amplifier closed-loop frequency response given by Equation 1 starts to roll off, and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage-feedback op amp. The difference here is that the total impedance in the denominator of Equation 2 may be controlled somewhat separately from the desired signal gain (or NG). The OPA694 is internally compensated to give a maximally flat frequency response for RF = 402Ω at NG = 2 on ±5V supplies. Evaluating the denominator of Equation 2 (which is the feedback transimpedance) gives an optimal target of 462Ω. As the signal gain changes, the contribution of the NG × RI term in the feedback transimpedance will change, but the total can be held constant by adjusting RF. Equation 3 gives an approximate equation for optimum RF over signal gain: RF = 462W - NG · RI (3) As the desired signal gain increases, this equation will eventually predict a negative RF. A somewhat subjective limit to this adjustment can also be set by holding RG to a minimum value of 20Ω. Lower values will load both the buffer stage at the input and the output stage, if RF gets too low, actually decreasing the bandwidth. Figure 39 shows the recommended RF versus NG for ±5V operation. The values for RF versus gain shown here are approximately equal to the values used to generate the Typical Characteristics. They differ in that the optimized values used in the Typical Characteristics are also correcting for board parasitics not considered in the simplified analysis leading to Equation 2. The values shown in Figure 39 give a good starting point for design where bandwidth optimization is desired. 450 Feedback Resistor (W) 400 350 300 250 200 150 0 5 10 15 20 Noise Gain Figure 39. Feedback Resistor vs Noise Gain bandwidth. Inserting a series resistor between the inverting input and the summing junction will increase the feedback impedance (denominator of Equation 1), decreasing the bandwidth. This approach to bandwidth control is used for the inverting summing circuit on the front page. The internal buffer output impedance for the OPA694 is slightly influenced by the source impedance looking out of the noninverting input terminal. High source resistors will have the effect of increasing RI, decreasing the bandwidth. OUTPUT CURRENT AND VOLTAGE The OPA694 provides output voltage and current capabilities that are not usually found in wideband amplifiers. Under no-load conditions at +25°C, the output voltage typically swings closer than 1.2V to either supply rail; the +25°C swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is tested to deliver more than ±60mA. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the (voltage × current), or V-I product, which is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot (Figure 21) in the Typical Characteristics. The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA694 output drive capabilities, noting that the graph is bounded by a Safe Operating Area of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA694 can drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.4V output swing capability, as shown in the Electrical Characteristics. The minimum specified output voltage and current over-temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristic tables. As the output transistors deliver power, the junction temperatures will increase, decreasing both VBE (increasing the available output voltage swing) and increasing the current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications, since the output stage junction temperatures will be higher than the minimum specified operating ambient. The total impedance going into the inverting input may be used to adjust the closed-loop signal 14 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA694 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open−loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS vs Capacitive Load (Figure 15) and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA694. Long PCB traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA694 output pin (see the Board Layout Guidelines section). DISTORTION PERFORMANCE The OPA694 provides good distortion performance into a 100Ω load on ±5V supplies. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration (see Figure 31), this is the sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply decoupling capacitor (0.1mF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate, while the 3rd-harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the 2nd-harmonic increases by less than the expected 6dB, while the 3rd-harmonic increases by less than the expected 12dB. This also shows up in the two-tone, third-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. NOISE PERFORMANCE Wideband, current-feedback op amps generally have a higher output noise than comparable voltage-feedback op amps. The OPA694 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (24pA/√Hz) is significantly lower than earlier solutions, while the input voltage noise (2.1nV/√Hz) is lower than most unity-gain stable, wideband, voltage-feedback op amps. This low input voltage noise was achieved at the price of higher noninverting input current noise (22pA/√Hz). As long as the AC source impedance looking out of the noninverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 40 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI EO OPA694 RS IBN ERS RF Ö4kTRS 4kT RG RG IBI Ö4kTRF 4kT = 1.6 ´ 10 at 290K -20 J Figure 40. Op Amp Noise Analysis Model 15 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 www.ti.com The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 4 shows the general form for the output noise voltage using the terms shown in Figure 40. EO = (E 2 NI ( + (IBNRS)2 + 4kTRS NG2 + (IBIRF)2 + 4kTRFNG (4) Dividing this expression by the noise gain [NG = (1 + RF/RG)] will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 5. 2 EN = ENI2 + (IBNRS)2 + 4kTRS + ( INGR ( + 4kTR NG BI F F DC ACCURACY AND OFFSET CONTROL A current-feedback op amp like the OPA694 provides exceptional bandwidth in high gains, giving fast pulse settling, but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed, voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband, current-feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 31, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: where NG = noninverting signal gain space xx = ±6mV + 1mV ±7.24mV = ±14.24mV A fine-scale, output offset null, or DC operating point adjustment, is sometimes required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most simple adjustment techniques do not correct for temperature drift. It is possible to combine a lower speed, precision op amp with the OPA694 to get the DC accuracy of the precision op amp along with the signal bandwidth of the OPA694. Figure 41 shows a noninverting G = +10 circuit that holds an output offset voltage less than ±7.5mV over-temperature with > 150MHz signal bandwidth. (5) Evaluating these two equations for the OPA694 circuit and component values (see Figure 31) gives a total output spot noise voltage of 11.2nV/√Hz and a total equivalent input spot noise voltage of 5.6nV/√Hz. This total input-referred spot noise voltage is higher than the 2.1nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. If the feedback resistor is reduced in high-gain configurations (as suggested previously), the total input-referred voltage noise given by Equation 5 will approach just the 2.1nV/√Hz of the op amp itself. For example, going to a gain of +10 using RF = 178Ω will give a total input-referred noise of 2.36nV/√Hz. ±(NG × VOS) ± (IBN × RS/2 × NG) ± (IBI × RF) xx = ±(2 × 3mV) ± (20mA × 25Ω × 2) ± (402Ω × 18mA) Power-supply decoupling not shown. +5V VI OPA694 VO 1.8kW +5V 2.86kW -5V 180W OPA237 20W -5V 18kW 2kW Figure 41. Wideband, DC-Connected Composite Circuit This DC-coupled circuit provides very high signal bandwidth using the OPA694. At lower frequencies, the output voltage is attenuated by the signal gain and compared to the original input voltage at the inputs of the OPA237 (this is a low-cost, precision voltage-feedback op amp with 1.5MHz gain bandwidth product). If these two do not agree (due to DC offsets introduced by the OPA694), the OPA237 sums in a correction current through the 2.86kΩ inverting summing path. Several design considerations will allow this circuit to be optimized. First, the feedback to the OPA237 noninverting input must be precisely matched to the high-speed signal gain. Making the 2kΩ resistor to ground an adjustable resistor would allow the low- and high-frequency gains to be precisely matched. Second, the crossover frequency region where the OPA237 passes control to the OPA694 must occur with exceptional phase linearity. These two issues reduce to designing for pole/zero cancellation in the overall transfer function. Using the 2.86kΩ resistor will nominally satisfy this space 16 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 requirement for the circuit in Figure 41. Perfect cancellation over process and temperature is not possible. However, this initial resistor setting and precise gain matching will minimize long-term pulse settling tails. THERMAL ANALYSIS Due to the high output power capability of the OPA694, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation, as described below. In no case should the maximum junction temperature be allowed to exceed +150°C. Operating junction temperature (TJ) is given by TA + PD × qJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS 2/(4 × RL) where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA694IDBV (SOT23-5 package) in the circuit of Figure 31 operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load to +2.5V DC: PD = 10V × 6.0mA + 52/[4 × (20Ω || 804Ω)] = 380mΩ Maximum TJ = +85°C + (0.38W × (150°C/W) = 142°C Although this is still below the specified maximum junction temperature, system reliability considerations may require lower junction temperatures. Remember, this is a worst-case internal power dissipation—use your actual signal and load to compute PDL. The highest possible internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The Output Voltage and Current Limitations plot (Figure 21) shown in the Typical Characteristics includes a boundary for 1W maximum internal power dissipation under these conditions. space space space BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA694 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25in, or 0.635cm) from the power-supply pins to high-frequency 0.1mF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2mF to 6.8mF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA694. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PCB trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value, as described previously. Increasing its value will reduce the bandwidth, while decreasing it will give a more peaked frequency response. The 402Ω feedback 17 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 www.ti.com resistor used in the Electrical Characteristic tables at a gain of +2 on ±5V supplies is a good starting point for design. Note that a 430Ω feedback resistor, rather than a direct short, is recommended for the unity-gain follower application. A current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils, or 1,270mm to 2,540mm) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load (Figure 15). Low parasitic capacitive loads (< 5pF) may not need an RS, since the OPA694 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary onboard, and in fact, a higher impedance environment will improve distortion, as shown in the Distortion versus Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA694 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA694 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA694 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA694 onto the board.. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA694 onto the board. INPUT AND ESD PROTECTION The OPA694 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 42. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA694), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, since high values degrade both noise performance and frequency response. +VCC Internal Circuitry External Pin -VCC Figure 42. Internal ESD Protection 18 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 OPA694 www.ti.com SBOS319G – SEPTEMBER 2004 – REVISED JANUARY 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (August, 2008) to Revision G Page • Updated document format to current standards ................................................................................................................... 1 • Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2 • Revised ADC Driver section to remove references to TI ADS522x devices ...................................................................... 10 • Changed Figure 33 ............................................................................................................................................................. 11 • Updated Figure 34 .............................................................................................................................................................. 11 • Changed Figure 36 ............................................................................................................................................................. 12 • Updated Figure 41 .............................................................................................................................................................. 16 REVISION HISTORY Changes from Revision E (March, 2006) to Revision F • Page Changed Storage Temperature minimum value from −40°C to −65°C ................................................................................ 2 19 Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): OPA694 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) OPA694ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 694 OPA694IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BIA OPA694IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BIA OPA694IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 694 OPA694IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 694 OPA694IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 694 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of