PCIE16X-800EVK/NOPB

PCIE16X-800EVK User Guide PCIe 16X Lane Card Evaluation Kit General Description: The PCIE16X-800EVK is a PCIe add-in riser card for PCIe 16x applications. It provides a complete platform to evaluate 4 - DS80PCI800SQ, 8 channels PCIe repeater for PCIe system protocol and lane negotiation validation. The card has a 16X PCIe edge fingers at J1 which plugs into a motherboard that has a PCIe 16X connector. The card also has a PCIe 16X connector at J2 for endpoint connection (PCIe graphic card or SATA/SAS raid controller card). Features: ■ 8 channel PCIe repeater up to 8 Gbps (GEN 3) ■ Low power consumption, with option to power down unused channels ■ Adjustable receive equalization ■ Adjustable transmit VOD and De-emphasis ■ IDLE detection — squelch function auto mutes the output ■ Programmable via pin selection or SMBus interface ■ Single supply operation: VIN = 3.3V±10% or VDD = 2.5V ±5% ■ -40°C to +85°C Operation ■ >6 kV HBM ESD Rating ■ High speed signal flow–thru pin-out package - SQA54A: 54-pin LLP (10 mm x 5.5 mm, 0.5 mm pitch) Applications: ■ Extends FR-4 Backplane Trace for PCIe Applications PCIE16X-800EVK Demo Kit Contents: ■ End User License Agreement ■ PCIE16X-800EVK User Guide Rev 1.2 ■ PCIE16X-800EVK Board Ordering Information: DEVICE: DS80PCI800SQE: QTY = 250, DS80PCI800SQ: QTY = 2,000 SMA Evaluation Kit: PCIE16X-800EVK Page 1 of 8 © Texas Instruments 2011 www.ti.com Figure 1. PCIE16X-800EVK Evaluation Board Page 2 of 8 © Texas Instruments 2011 www.ti.com Table 1. Switches to set the 4-level input control pins Setting for 3 pin switches (3-2-1) 4 – level Input Settings 0 – Tie 249 ohm to GND ON – OFF – OFF R – Tie 5k ohm to GND OFF – ON – OFF F – FLOAT (open) OFF – OFF – OFF 1 – Tie 249 ohm to VIH OFF – OFF – ON The following switches are used to set the input condition for the 4-level inputs: SW1, SW2, SW3, SW5, SW6, SW10, SW11. There are 3 switches connected to an input signal pin. Each switch when set to the ON position sets the pin to one of the 4-level setting. The 6 pin switches are assigned similar to the 3 pin switches. The only difference is 2 signal pins are connected and thus 6-5-4 is for the one signal pin and 3-2-1 is for another signal pin. Please note only 1 switch at the ON position is allowed. Table 2. Connection and Control Description Function Component Name J1 PCIE TX/RX High speed differential TX/RX from/to Root Complex J2 PCIE TX/RX High speed differential TX/RX to/from End Point J3, J5 3.3V to VIN 3.3V DC Power – VIN to DS80PCI800SQ Jumper ON = 3.3V mode operation Jumper OFF = 2.5V mode operation J4, J6 2.5V to VDD 2.5V DC Power – VDD to DS80PCI800SQ Jumper ON (1-2, 3-4) = 2.5V mode operation Jumper OFF (1-2, 3-4) = 3.3V mode operation J7 VIN or VDD Jumper VIH: set 1-2 = VIN (3.3V) or set 2-3 = VDD (2.5V) J8 SDA, SCL Optional SMBUS access pins. See the datasheet for additional information on SMBUS. J9 EEPROM Optional socket for EEPROM SW1 EQB[1:0] or AD[3:2] SW2 ENSMB SW3 DEMA[1:0] SW4 SDA/SCL SW5 DEMB[1:0] or AD[1:0] SW6 SD_TH and LPBK - RES SD_TH – Signal detect threshold level (FLOAT = Default level) LPBK function for PCI402 and RESERVED for PCI800 (FLOAT = Normal operation) SW7 VDD_SEL1_2 VDD_SEL3_4 VDD_SEL – Enable or disable the internal 3.3V to 2.5V regulator for U1 and U2. ON connects to GND to enable the internal LDO regulator for 3.3V mode operation. SW8 READ_EN, RD_EN2, RD_EN3 and RD_EN4 For manual control of loading the external EEPROM and daisy chain the READ_EN to the ALL_DONE pins. Pin1 = ON connects the SW13 push button to the READ_EN of U1. Pin2,3,4 = OFF SW9 A_D1 to RD_EN2 … A_D3 to RD_EN4 SW10 RXDET and RATE SW11 EQA[1:0] Pin1 = ON connects the ALL_DONE of U1 to READ_EN of U2. Pin2 = ON connects the ALL_DONE of U2 to READ_EN of U3. Pin3 = ON connects the ALL_DONE of U3 to READ_EN of U4. Pin4 = OFF RXDET – Input internal 50 ohm to VDD terminations RXDET = F (AUTO RX Detect), RXDET = 1 (50 ohm input termination). RATE = 0 (GEN1,2) = 2.5G / 5.0G. RATE = R (GEN3) = 8.0G. RATE = F (AUTO Detect). The RATE auto detect circuit requires the idle and active signal which occurs during the link training negotiation. PIN MODE – EQ control for channel A inputs PIN MODE – EQ control for channel B inputs SMBUS MODE – AD[3:2] device address bits ENSMB = LOW – PIN MODE ENSMB = HIGH – SMBUS (slave mode) ENSMB = FLOAT – SMBUS (master mode – load configuration from EEPROM) PIN MODE – DE control for channel A outputs “ON” position connects SDA and SCL lines to the device pin. PIN MODE – DE control for channel B outputs SMBUS MODE – AD[1:0] device address bits Page 3 of 8 © Texas Instruments 2011 www.ti.com SW12 SDA/SCL to SMCLK/SMDAT SW13 READ_EN SW14 PRSNT “ON” connect the SDA/SCL bus to the PCIe SMCLK and SMDAT bus. Default is “OFF”. ENSMB = FLOAT – SMBUS (master mode – load configuration from EEPROM) SW6: SD_TH becomes the READ_EN pin. To start the loading at power up, set SW6 pin 3 to “ON” position (pull to GND). To manually control the start, set SW6 to “OFF” position and set SW8 pin1 to “ON” and pin2 to “OFF” position and push the SW13 button for the high to low transition to start the loading. When the loading is complete the LEDs – D1 thru D4 light should turn OFF. “ON” connects the PCIe PRSNT signal to the device PRSNT pin. For 16X, set all the switches to the “ON” position. Quick Start User Guide: 1. Connect J1 – PCIe 16x edge finger to the motherboard (root complex) 2. Connect J2 - PCIe 16x connector to an add-in card (end point). 3. For 3.3V mode operation, set J3 jumper to ON and do not use J4 (leave jumper OFF). For 2.5V mode operation, set J3 jumper to OFF and set J4 jumper to ON (1-2 and 3-4). 4. Set jumper – J7 for VIH connection to VIN (3.3V) or VDD (2.5V). Default is 1-2 set to ON for VIH = 3.3V. 5. Set SW7 – VDD_SEL1_2 and VDD_SEL3_4 to “ON” position for 3.3V mode operation. 6. Set the control pins for normal operation SW10 – RXDET = F (continuous receiver detection): set switches (3-2-1) = (OFF-OFF-OFF). RXDET = 1 (50 ohm input termination): set switches (3-2-1) = (OFF-OFF-ON). SW10 – RATE = F (enable rate detection): set switches (6-5-4) to (OFF-OFF-OFF). RATE = R (GEN3 mode): set switches (6-5-4) = (OFF-ON-OFF). RATE = 0 (GEN1,2 mode): set switches (6-5-4) = (ON-OFF-OFF). SW6 – SD_TH = F (default signal detect threshold level): set switches (3-2-1) = (OFF-OFF-OFF). SW6 – LPBK - RES = F (normal operation): set switches (6-5-4) = (OFF-OFF-OFF). SW8: Set switches to “OFF” position. SW9: Set switches to “OFF” position. SW14 – PRSNT = GND (enables the device): set switches to “ON” position. 5. Set the input equalization level. For external pin mode control of the equalization level: Set ENSMB = 0 (1kohm to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF). SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected. Refer to Table 1 for information on the 3 switch settings for the 4 level input. Example: Set EQB[1:0] with SW1 for the B bank of inputs (top 2 left inputs of DS80PCI800). SW1 (6-5-4),(3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQB[1:0] = R,R = 14.6 dB at 4 GHz (level 6). Set EQA[1:0] with SW11 for the A bank of inputs (bottom 2 left inputs of DS80PCI800). SW8 (6-5-4),(3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQA[1:0] = R,R = 14.6 dB at 4 GHz (level 6). The table below is the 16 possible EQ settings when in pin mode. SW1 - EQB[1:0] Level EQA/B[1:0] SW11 - EQA[1:0] EQ (dB) at 4 GHz 6 5 4 3 2 1 ON ON 1 0, 0 OFF OFF OFF OFF 4.9 ON ON 2 0, R OFF OFF OFF OFF 7.9 ON 3 0, F OFF OFF OFF OFF OFF 9.9 ON ON 4 0, 1 OFF OFF OFF OFF 11.0 ON ON 5 R, 0 OFF OFF OFF OFF 14.3 ON ON 6 R, R OFF OFF OFF OFF 14.6 ON 7 R, F OFF OFF OFF OFF OFF 17.0 Page 4 of 8 © Texas Instruments 2011 www.ti.com 8 9 10 11 12 13 14 15 16 R ,1 F ,0 F, R F, F F, 1 1, 0 1, R 1, F 1, 1 OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON OFF ON OFF OFF OFF ON OFF OFF OFF OFF OFF ON OFF OFF OFF ON OFF OFF ON OFF OFF OFF ON OFF OFF OFF ON 18.5 18.0 22.0 24.4 25.8 27.4 29.0 31.4 32.7 6. Set the output VOD and De-emphasis level. For external pin mode control for the VOD and De-emphasis level (Gen1&2 only): Set ENSMB = 0 (1kohm to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF). SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected. Refer to Table 1 for information on the 3 switch settings for the 4 level input. Example: Set DEMB[1:0] with SW5 for the B bank of outputs (top 2 right outputs of DS80PCI800). SW5 (6-5-4),(3-2-1) = (ON-OFF-OFF), (OFF-OFF-ON) = DEMB[1:0] = 0,1 (VOD=1.0V, DE=0 dB). Set DEMA[1:0] with SW3 for the A bank of outputs (bottom 2 right outputs of DS80PCI800). SW3 (6-5-4),(3-2-1) = (ON-OFF-OFF), (OFF-OFF-ON) = DEMA1:0] = 0,1 (VOD=1.0V, DE=0 dB). The table below is the 16 possible settings of VOD and DE when in pin mode. In Gen 1/2, the de-emphasis level can be set with the DEMx[1:0] pins, but is not available in Gen 3. SW5 - DEMB[1:0] SW3 - DEMA[1:0] Level DEMA/B[1:0] GEN1,2 6 5 4 3 2 1 VOD (Vp-p) DE (dB)  0  ON ON 1 0, 0 OFF OFF OFF OFF 0.8 0  ON ON 2 0, R OFF OFF OFF OFF 0.9 ‐3.5  ON 3 0, F OFF OFF OFF OFF OFF 0.9 0  ON ON 4 0, 1 OFF OFF OFF OFF 1.0 ‐3.5  ON ON 5 R, 0 OFF OFF OFF OFF 1.0 ‐6  ON ON 6 R, R OFF OFF OFF OFF 1.0 0  ON 7 R, F OFF OFF OFF OFF OFF 1.1 ‐3.5  ON ON 8 R ,1 OFF OFF OFF OFF 1.1 ‐6  ON 9 F ,0 OFF OFF OFF OFF OFF 1.1 0  ON 10 F, R OFF OFF OFF OFF OFF 1.2 ‐3.5  11 F, F OFF OFF OFF OFF OFF OFF 1.2 ‐6  ON 12 F, 1 OFF OFF OFF OFF OFF 1.2 0  ON ON 13 1, 0 OFF OFF OFF OFF 1.3 ‐3.5  ON ON 14 1, R OFF OFF OFF OFF 1.3 ‐6  ON 15 1, F OFF OFF OFF OFF OFF 1.3 ‐9  ON ON 16 1, 1 OFF OFF OFF OFF 1.3 For SMBUS mode control of the EQ, VOD and De-emphasis level: Set ENSMB = 1 (1kohm to VIH) by using the SW2 (3-2-1) = (OFF-OFF-ON). Set SW4 pin1,2 to the ON position so the SMBUS signals are connected. Set SW3 pin1 thru pin6 switches to the OFF position so they do not connect to the SDA and SCL line. Set the SW1 and SW5 for the AD[3:0] pins. AD[3:0]=0000 sets device slave address = B0’hex. Connect SDA, SCL and GND to J17. Please refer to datasheet for register map for EQ, VOD and DEM. Page 5 of 8 © Texas Instruments 2011 www.ti.com Bill of Materials for PCIE16X-800EVK: Item Qty 1 20 Reference Digikey PN Manufacture PN C1,C2,C3,C4,C5,C6,C7,C8, 445-4711-1-ND C0603X5R0J104M Descriptions CAP CER .10UF 6.3V X5R 0201 C9,C10,C11,C12,C13,C14, C15,C16,C17,C18,C19,C20 2 4 C21,C22,C27,C28 445-3448-1-ND C1608Y5V0J106Z CAP CER 10UF 6.3V Y5V 0603 3 2 C23,C24 587-1966-1-ND AMK105BJ475MV-F 4 2 C25,C26 445-5515-1-ND C0402X5R0J103K 5 2 C29,C30 490-1261-1-ND GRM033R71C102KD01D 6 2 C160,C161 445-4998-1-ND C1005X5R0J105K 7 128 C31,C32,C33,C34,C35,C36, 587-2483-1-ND LMK063BJ224MP-F CAP CER 4.7UF 4V X5R 0402 CAP CER 0.01UF 6.3V X5R 01005 CAP CER 1000PF 16V 10% X7R 0201 CAP CER 1.0UF 6.3V X5R 0402 CAP CER .22UF 10V X5R 20% 0201 D1,D2,D3,D4 511-1592-1-ND SML-P12PTT86 LED GREEN 0.2MM 13MCD 0402 SMD J1 NA NA C37,C38,C39,C40,C41,C42, C43,C44,C45,C46,C47,C48, C49,C50,C51,C52,C53,C54, C55,C56,C57,C58,C59,C60, C61,C62,C63,C64,C65,C66, C67,C68,C69,C70,C71,C72, C73,C74,C75,C76,C77,C78, C79,C80,C81,C82,C83,C84, C85,C86,C87,C88,C89,C90, C91,C92,C93,C94,C95,C96, C97,C98,C99,C100,C101, C102,C103,C104,C105,C106, C107,C108,C109,C110,C111, C112,C113,C114,C115,C116, C117,C118,C119,C120,C121, C122,C123,C124,C125,C126, C127,C128,C129,C130,C131, C132,C133,C134,C135,C136, C137,C138,C139,C140,C141, C142,C143,C144,C145,C146, C147,C148,C149,C150,C151, C152,C153,C154,C155,C156, C157,C158 8 4 9 10 1 J2 S2806-ND NWE82DHRN-T9410 11 2 J3, J5 WM6502-ND 22-28-4023 12 1 J7 WM6503-ND 22-28-4033 13 3 J4,J6,J8 WM6504-ND 22-28-4043 14 1 J9 3M5473-ND 4808-3004-CP Page 6 of 8 © Texas Instruments 2011 www.ti.com PCIE EDGE FINGERS CONN PCI EXPRESS 164POS VERT PCB CONN HEADER 2POS .100 VERT GOLD CONN HEADER 3POS .100 VERT GOLD CONN HEADER 4POS .100 VERT GOLD SOCKET IC OPEN FRAME 8POS .3" 15 2 R1,R4 P1.50KLCT-ND ERJ-2RKF1501X 16 7 R2,R5,R50,R51,R52,R53, P1.00KLCT-ND ERJ-2RKF1001X RES 1.50K OHM 1/10W 1% 0402 SMD RES 1.00K OHM 1/10W 1% 0402 SMD R54 17 2 R3, R6 P51.0KLCT-ND ERJ-2RKF5102X 18 4 R7,R8,R9,R10 P220LCT-ND ERJ-2RKF2200X 19 26 R11,R13,R14,R16,R17,R19, P249LCT-ND ERJ-2RKF2490X RES 51.0K OHM 1/10W 1% 0402 SMD RES 220 OHM 1/10W 1% 0402 SMD RES 249 OHM 1/10W 1% 0402 SMD P4.99KLCT-ND ERJ-2RKF4991X RES 4.99K OHM 1/10W 1% 0402 SMD R55,R56 P2.00KLCT-ND ERJ-2RKF2001X SW1,SW3,SW5,SW6,SW10, CT2196MST-ND 219-6MST R20,R22,R23,R25,R26,R28, R29,R31,R32,R34,R35,R37, R38,R40,R41,R43,R44,R46, R47,R49 20 13 R12,R15,R18,R21,R24,R27, R30,R33,R36,R39,R42,R45, R48 21 2 22 6 RES 2.00K OHM 1/10W 1% 0402 SMD SWITCH TAPE SEAL 6 POS SMD SW11 23 1 SW2 CT2193MST-ND 219-3MST 24 3 SW4,SW7,SW12 CT2192MST-ND 219-2MST 25 3 SW8,SW9,SW14 CT2194MST-ND 219-4MST 26 1 SW13 P12225SCT-ND EVQ-21505R SWITCH TAPE SEAL 3 POS SMD SWITCH TAPE SEAL 2 POS SMD SWITCH TAPE SEAL 4 POS SMD SWITCH LT 6MM 160GF 5MM HEIGHT 27 4 U1,U2,U3,U4 DS80PCI800SQ PCIE REPEATER 28 2 U5,U6 NA LP3878MRADJCT-ND LP3878MR-ADJ/NOPB IC VREG 800MA ADJ 8-PSOP Page 7 of 8 © Texas Instruments 2011 www.ti.com Document ID: PCIE16X-800EVK User Guide Date: November, 2011 Rev: 1.2 Page 8 of 8 © Texas Instruments 2011 www.ti.com 5 4 3 2 1 J2 GND PERp14 PERn14 PERp15 PERn15 55 EQB0/AD3 EQB1/AD2 ENSMB DEMA0/SDA DEMA1/SCL VDD /PRSNT DEMB0/AD1 DEMB1/AD0 DAP U2 DS80PCI800 ALL_DONE SD_TH/RD_EN VDD_SEL VIN RES RXDET RATE EQA0 EQA1 VDD2 14 36 41 51 PLACE CLOSE TO PIN 9 C6 C7 C8 C9 C10 GND 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 4 PERp0 PERn0 PERp1 PERn1 VDD3 PERp2 PERn2 PERp3 PERn3 VDD3 PERp4 PERn4 PERp5 PERn5 PERp6 PERn6 PERp7 PERn7 1 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 GND 3_3V 1 2 3 4 C24 4.7uF 9 BYPASS S_DWN NC1 NC2 GND ADJ INPUT OUTPUT C28 GND R6 51k 8 7 6 5 3_3V VIN3_4 1 2 C22 C161 GND 10uF 1uF 10uF C30 1nF R5 1k R4 1.5k VDD3 VDD4 J6 4 HEADER GND LP3878-ADJ D2 SML-P12PTT86 R8 220 A_D2 RD_EN2 VDD_SEL1_2 VIN1_2 RES RXDET RATE EQA0 EQA1 EQB0_AD3 EQB1_AD2 ENSMB DEMA0_SDA DEMA1_SCL PRSNT DEMB0_AD1 DEMB1_AD0 EQA1 EQA0 RATE RXDET RES VDD_SEL1_2 VDD_SEL3_4 3_3V 1 2 3 4 VOUT3_4 GND J4 4 HEADER GND 27 26 25 24 23 22 21 20 19 DAP C26 0.01uF 2 2 OB_0+ OB_0OB_1+ OB_1VDD OB_2+ OB_2OB_3+ OB_3VDD OA_0+ OA_0OA_1+ OA_1OA_2+ OA_2OA_3+ OA_3IB_0+ IB_0IB_1+ IB_1IB_2+ IB_2IB_3+ IB_3VDD IA_0+ IA_0IA_1+ IA_1VDD IA_2+ IA_2IA_3+ IA_31 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PERp0_C PERn0_C PERp1_C PERn1_C PERp2_C PERn2_C PERp3_C PERn3_C VDD3 PERp4_C PERn4_C PERp5_C PERn5_C VDD3 PERp6_C PERn6_C PERp7_C PERn7_C 1 PETp8_C PETn8_C PETp9_C PETn9_C VDD2 PETp10_C PETn10_C PETp11_C PETn11_C VDD2 PETp12_C PETn12_C PETp13_C PETn13_C PETp14_C PETn14_C PETp15_C PETn15_C EQB0_AD3 46 EQB1_AD2 47 ENSMB 48 DEMA0_SDA49 DEMA1_SCL50 VDD2 51 PRSNT 52 DEMB0_AD153 DEMB1_AD054 VOUT1_2 VDD1 VOUT1_2 VDD2 PERp10 PERn10 PERp13 PERn13 R1 1.5k LP3878-ADJ PERp9 PERn9 PERp12 PERn12 VOUT1_2 R2 1k GND PERp8 PERn8 PERp11 PERn11 U6 C29 1nF J5 (U3,U4): 1-2 (ON) FOR 3.3V, 1-2 (OFF) FOR 2.5V. J6 (U3,U4): 1-2, 3-4 (ON) FOR 2.5V, J5 1-2, 3-4 (OFF) FOR 2 HEADER 3.3V. D4 SML-P12PTT86 EQB0_AD3 46 EQB1_AD2 47 ENSMB 48 DEMA0_SDA49 DEMA1_SCL50 VDD4 51 PRSNT 52 DEMB0_AD153 DEMB1_AD054 EQB0/AD3 EQB1/AD2 ENSMB DEMA0/SDA DEMA1/SCL VDD /PRSNT DEMB0/AD1 DEMB1/AD0 ALL_DONE SD_TH/RD_EN VDD_SEL VIN RES RXDET RATE EQA0 EQA1 1 C23 4.7uF 8 7 6 5 U3 DS80PCI800 R10 220 27 26 25 24 23 22 21 20 19 A_D4 RD_EN4 VDD_SEL3_4 VIN3_4 RES RXDET RATE EQA0 EQA1 2 GND 3_3V BYPASS S_DWN NC1 NC2 GND ADJ INPUT OUTPUT DAP VDD3 14 36 41 51 PLACE CLOSE TO PIN 9 C11 C12 C13 C14 C15 GND C21 C160 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND GND 3_3V 10uF 1uF 10uF A_D3 RD_EN3 VDD_SEL3_4 VIN3_4 RES RXDET RATE EQA0 EQA1 27 26 25 24 23 22 21 20 19 ALL_DONE SD_TH/RD_EN VDD_SEL VIN RES RXDET RATE EQA0 EQA1 PERp8 PERn8 PERp9 PERn9 VDD4 PERp10 PERn10 PERp11 PERn11 VDD4 PERp12 PERn12 PERp13 PERn13 PERp14 PERn14 PERp15 PERn15 1 2 3 4 R3 51k EQB0/AD3 EQB1/AD2 ENSMB DEMA0/SDA DEMA1/SCL VDD /PRSNT DEMB0/AD1 DEMB1/AD0 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 PERp7 PERn7 U5 C25 0.01uF R9 220 3_3V VIN1_2 1 2 C27 GND 55 D3 SML-P12PTT86 OB_0+ OB_0OB_1+ OB_1VDD OB_2+ OB_2OB_3+ OB_3VDD OA_0+ OA_0OA_1+ OA_1OA_2+ OA_2OA_3+ OA_3- PERp6 PERn6 VDD1 14 36 41 51 PLACE CLOSE TO PIN 9 C1 C2 C3 C4 C5 GND 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND 3_3V GND J3 (U1,U2): 1-2 (ON) FOR 3.3V, 1-2 (OFF) FOR 2.5V. J4 (U1,U2): 1-2, 3-4 (ON) FOR 2.5V, J3 1-2, 3-4 (OFF) FOR 3.3V. 2 HEADER 1 PERp5 PERn5 EQB0_AD3 46 EQB1_AD2 47 ENSMB 48 DEMA0_SDA49 DEMA1_SCL50 VDD3 51 PRSNT 52 DEMB0_AD153 DEMB1_AD054 GND IB_0+ IB_0IB_1+ IB_1IB_2+ IB_2IB_3+ IB_3VDD IA_0+ IA_0IA_1+ IA_1VDD IA_2+ IA_2IA_3+ IA_3- U1 DS80PCI800 SMCLK SMDAT SD_TH RD_EN2 RD_EN3 RD_EN4 A_D1 A_D2 A_D3 A_D4 GND 55 DAP EQB0_AD3 EQB1_AD2 ENSMB U4 DEMA0_SDA DS80PCI800 DEMA1_SCL PRSNT DEMB0_AD1 DEMB1_AD0 EQA1 EQA0 VDD4 RATE 14 36 41 51 PLACE CLOSE TO PIN 9 RXDET C16 C17 C18 C19 C20 RES GND VDD_SEL1_2 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VDD_SEL3_4 3_3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DAP DAP PERp4 PERn4 RSVD5 GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND 55 PERp3 PERn3 RSVD3 RSVD4 GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 2 PERp2 PERn2 A_D1 SD_TH VDD_SEL1_2 VIN1_2 RES RXDET RATE EQA0 EQA1 IB_0+ IB_0IB_1+ IB_1IB_2+ IB_2IB_3+ IB_3VDD IA_0+ IA_0IA_1+ IA_1VDD IA_2+ IA_2IA_3+ IA_3- PERp1 PERn1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 RSVD GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND GND 0.22uF 0.22uF GND 27 26 25 24 23 22 21 20 19 ALL_DONE SD_TH/RD_EN VDD_SEL VIN RES RXDET RATE EQA0 EQA1 PETp0 PETn0 PETp1 PETn1 PETp2 PETn2 PETp3 PETn3 VDD1 PETp4 PETn4 PETp5 PETn5 VDD1 PETp6 PETn6 PETp7 PETn7 PERp0 PERn0 EQB0/AD3 EQB1/AD2 ENSMB DEMA0/SDA DEMA1/SCL VDD /PRSNT DEMB0/AD1 DEMB1/AD0 9 REFCLKp REFCLKn J1 PCIE_16X_EDGE_FINGER 5 PETp0_C PETn0_C PETp1_C PETn1_C VDD1 PETp2_C PETn2_C PETp3_C PETn3_C VDD1 PETp4_C PETn4_C PETp5_C PETn5_C PETp6_C PETn6_C PETp7_C PETn7_C PERST EQB0_AD3 46 EQB1_AD2 47 ENSMB 48 DEMA0_SDA49 DEMA1_SCL50 VDD1 51 PRSNT 52 DEMB0_AD153 DEMB1_AD054 R7 220 OB_0+ OB_0OB_1+ OB_1VDD OB_2+ OB_2OB_3+ OB_3VDD OA_0+ OA_0OA_1+ OA_1OA_2+ OA_2OA_3+ OA_3- 3_3V 3_3V GND 0.22uF 0.22uF GND D1 SML-P12PTT86 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 JTAG2 JTAG3 JTAG4 JTAG5 GND GND 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 A12 A13 A14 A15 A16C63 A17C64 A18 A19 A20 A21C65 A22C66 A23 A24 A25C67 A26C68 A27 A28 A29C69 A30C70 A31 A32 A33 A34 A35C71 A36C72 A37 A38 A39C73 A40C74 A41 A42 A43C75 A44C76 A45 A46 A47C77 A48C78 A49 A50 A51 A52C79 A53C80 A54 A55 A56C81 A57C82 A58 A59 A60C83 A61C84 A62 A63 A64C85 A65C86 A66 A67 A68C87 A69C88 A70 A71 A72C89 A73C90 A74 A75 A76C91 A77C92 A78 A79 A80C93 A81C94 A82 PRSNT2_1 PRSNT2_2 PRSNT2_3 PRSNT2_4 OB_0+ OB_0OB_1+ OB_1VDD OB_2+ OB_2OB_3+ OB_3VDD OA_0+ OA_0OA_1+ OA_1OA_2+ OA_2OA_3+ OA_3- A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 PRSNT1 12V 12V GND SMCLK SMDAT SD_TH RD_EN2 RD_EN3 RD_EN4 A_D1 A_D2 A_D3 A_D4 PERp8_C PERn8_C PERp9_C PERn9_C PERp10_C PERn10_C PERp11_C PERn11_C VDD4 PERp12_C PERn12_C PERp13_C PERn13_C VDD4 PERp14_C PERn14_C PERp15_C PERn15_C A B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 IB_0+ IB_0IB_1+ IB_1IB_2+ IB_2IB_3+ IB_3VDD IA_0+ IA_0IA_1+ IA_1VDD IA_2+ IA_2IA_3+ IA_3- B RSVD1 B12 GND B13 PETp0 C31 0.22uFB14 PETn0 C32 0.22uFB15 GND B16 PRSNT2_1 B17 GND B18 PETp1 C33 0.22uFB19 PETn1 C34 0.22uFB20 GND B21 GND B22 PETp2 C35 0.22uFB23 PETn2 C36 0.22uFB24 GND B25 GND B26 PETp3 C37 0.22uFB27 PETn3 C38 0.22uFB28 GND B29 RSV2 B30 PRSNT2_2 B31 GND B32 PETp4 C39 0.22uFB33 PETn4 C40 0.22uFB34 GND B35 GND B36 PETp5 C41 0.22uFB37 PETn5 C42 0.22uFB38 GND B39 GND B40 PETp6 C43 0.22uFB41 PETn6 C44 0.22uFB42 GND B43 GND B44 PETp7 C45 0.22uFB45 PETn7 C46 0.22uFB46 GND B47 PRSNT2_3 B48 GND B49 PETp8 C47 0.22uFB50 PETn8 C48 0.22uFB51 GND B52 GND B53 PETp9 C49 0.22uFB54 PETn9 C50 0.22uFB55 GND B56 GND B57 PETp10C51 0.22uFB58 PETn10C52 0.22uFB59 GND B60 GND B61 PETp11C53 0.22uFB62 PETn11C54 0.22uFB63 GND B64 GND B65 PETp12C55 0.22uFB66 PETn12C56 0.22uFB67 GND B68 GND B69 PETp13C57 0.22uFB70 PETn13C58 0.22uFB71 GND B72 GND B73 PETp14C59 0.22uFB74 PETn14C60 0.22uFB75 GND B76 GND B77 PETp15C61 0.22uFB78 PETn15C62 0.22uFB79 GND B80 PRSNT2_4 B81 RSVD2 B82 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 B10 A10 B11 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 C B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 PETp8 PETn8 PETp9 PETn9 PETp10 PETn10 PETp11 PETn11 VDD2 PETp12 PETn12 PETp13 PETn13 VDD2 PETp14 PETn14 PETp15 PETn15 D 12V 12V 12V GND SMCLK SMDAT GND 3_3V JTAG1 3_3VAUX WAKE PRSNT2_1 PRSNT2_2 PRSNT2_3 PRSNT2_4 3 2 NWE82DHRN-T9410 12V B1 12V B2 12V B3 GND B4 SMCLK B5 SMDAT B6 GND B7 3_3V B8 JTAG1 B9 3_3VAUX B10 WAKE B11 RSVD1 B12 GND B13 PETp0_C C95 0.22uFB14 PETn0_C C96 0.22uFB15 GND B16 PRSNT2_1 B17 GND B18 PETp1_C C97 0.22uFB19 PETn1_C C98 0.22uFB20 GND B21 GND B22 PETp2_C C99 0.22uFB23 PETn2_C C1000.22uFB24 GND B25 GND B26 PETp3_C C1010.22uFB27 PETn3_C C1020.22uFB28 GND B29 RSV2 B30 PRSNT2_2 B31 GND B32 PETp4_C C1030.22uFB33 PETn4_C C1040.22uFB34 GND B35 GND B36 PETp5_C C1050.22uFB37 PETn5_C C1060.22uFB38 GND B39 GND B40 PETp6_C C1070.22uFB41 PETn6_C C1080.22uFB42 GND B43 GND B44 PETp7_C C1090.22uFB45 PETn7_C C1100.22uFB46 GND B47 PRSNT2_3 B48 GND B49 PETp8_C C1110.22uFB50 PETn8_C C1120.22uFB51 GND B52 GND B53 PETp9_C C1130.22uFB54 PETn9_C C1140.22uFB55 GND B56 GND B57 PETp10_CC1150.22uFB58 PETn10_CC1160.22uFB59 GND B60 GND B61 PETp11_CC1170.22uFB62 PETn11_CC1180.22uFB63 GND B64 GND B65 PETp12_CC1190.22uFB66 PETn12_CC1200.22uFB67 GND B68 GND B69 PETp13_CC1210.22uFB70 PETn13_CC1220.22uFB71 GND B72 GND B73 PETp14_CC1230.22uFB74 PETn14_CC1240.22uFB75 GND B76 GND B77 PETp15_CC1250.22uFB78 PETn15_CC1260.22uFB79 GND B80 PRSNT2_4 B81 RSVD2 B82 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 B10 A10 B11 A11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 PRSNT1 12V 12V GND JTAG2 JTAG3 JTAG4 JTAG5 3_3V 3_3V PERST GND A12 REFCLKp A13 REFCLKn A14 GND A15 A16C1270.22uF PERp0_C A17C1280.22uF PERn0_C GND A18 RSVD A19 GND A20 A21C1290.22uF PERp1_C PERn1_C A22C1300.22uF GND A23 GND A24 A25C1310.22uF PERp2_C A26C1320.22uF PERn2_C GND A27 GND A28 A29C1330.22uF PERp3_C A30C1340.22uF PERn3_C GND A31 RSVD3 A32 RSVD4 A33 GND A34 A35C1350.22uF PERp4_C C1360.22uF PERn4_C A36 GND A37 GND A38 A39C1370.22uF PERp5_C PERn5_C C1380.22uF A40 GND A41 GND A42 A43C1390.22uF PERp6_C A44C1400.22uF PERn6_C GND A45 GND A46 A47C1410.22uF PERp7_C A48C1420.22uF PERn7_C GND A49 RSVD5 A50 GND A51 A52C1430.22uF PERp8_C A53C1440.22uF PERn8_C GND A54 GND A55 A56C1450.22uF PERp9_C A57C1460.22uF PERn9_C GND A58 GND A59 A60C1470.22uF PERp10_C PERn10_C C1480.22uF A61 GND A62 GND A63 A64C1490.22uF PERp11_C A65C1500.22uF PERn11_C GND A66 GND A67 A68C1510.22uF PERp12_C A69C1520.22uF PERn12_C GND A70 GND A71 A72C1530.22uF PERp13_C A73C1540.22uF PERn13_C GND A74 GND A75 A76C1550.22uF PERp14_C A77C1560.22uF PERn14_C GND A78 GND A79 A80C1570.22uF PERp15_C A81C1580.22uF PERn15_C GND A82 Title PCIE16X_800EVK Size B Date: Document Number DS80PCI800 PCIE 16X CARD PAGE 1 Thursday, December 09, 2010 Rev A Sheet 1 1 of 1 D C B A 5 4 3 J7 3 HEADER D EQB0_AD3 EQB1_AD2 ENSMB DEMA0_SDA DEMA1_SCL PRSNT DEMB0_AD1 DEMB1_AD0 EQA1 EQA0 RATE RXDET RES VDD_SEL1_2 VDD_SEL3_4 VOUT1_2 3_3V 1 2 3 3_3V VIH VOUT1_2 SW7 OFF EQB0_AD3 EQB1_AD2 ENSMB DEMA0_SDA DEMA1_SCL PRSNT DEMB0_AD1 DEMB1_AD0 EQA1 EQA0 RATE RXDET RES VDD_SEL1_2 VDD_SEL3_4 VOUT1_2 3_3V C VIH GND GND VIH GND GND R11 R12 R13 R14 R15 R16 VIH 219-2MST SW6 OFF ON 249 4.99k 249 249 4.99k 249 D VDD_SEL1_2 VDD_SEL3_4 PLACE ALL Rs CLOSE TO SW SW IN THE OFF POSITION = OPEN VIH GND GND VIH GND GND EQB0_AD3 EQB1_AD2 R32 R33 R34 R35 R36 R37 ON 249 4.99k 249 249 4.99k 249 SW8 OFF R53 1k ON SD_TH GND RD_EN2 RD_EN3 RD_EN4 RES SW13 EVQ-21505R PIN MODE SETTINGS: SW1 - EQB0, EQB1 SW2 - ENSMB = 1K TO GND SW3 - DEMA0, DEMA1 SW4 - OFF POSITION SW5 - DEMB0, DEMB1 SW6 - SD_TH, RES SW7 - ON (GND) FOR 3.3V SW8 - RD_EN2-4=ON (SD_TH) SW9 - OFF POSTION SW10 - RXDET, RATE SW11 - EQA0, EQA1 SW12 - OFF POSITION SW13 - OFF POSITION SW14 - PRSNT2_4=ON 219-4MST SMCLK SMDAT SD_TH RD_EN2 RD_EN3 RD_EN4 A_D1 A_D2 A_D3 A_D4 219-6MST SW9 OFF SW2 OFF VIH GND GND ON R17 249 R18 4.99k R19 249 VIH GND GND VIH GND GND ENSMB R38 R39 R40 R41 R42 R43 249 4.99k 249 249 4.99k 249 PRSNT2_1 PRSNT2_2 PRSNT2_3 PRSNT2_4 ON RD_EN2 RD_EN3 RD_EN4 PRSNT SW10 OFF ON 219-3MST PRSNT2_1 PRSNT2_2 PRSNT2_3 PRSNT2_4 ON GND GND SW1 OFF 1 PIN 1-2 FOR 3.3V PIN 2-3 FOR 2.5V 219-6MST SMCLK SMDAT SD_TH RD_EN2 RD_EN3 RD_EN4 A_D1 A_D2 A_D3 A_D4 2 A_D1 A_D2 A_D3 A_D4 RXDET 219-4MST RATE SW12 OFF ON 219-6MST SMCLK SMDAT SW3 OFF VIH GND GND VIH GND GND R20 R21 R22 R23 R24 R25 SW11 OFF ON ON 249 4.99k 249 249 4.99k 249 SCL SDA SW4 OFF ON DEMA0_SDA DEMA1_SCL SDA SCL VIH GND GND VIH GND GND R44 R45 R46 R47 R48 R49 249 4.99k 249 249 4.99k 249 219-2MST J8 4 HEADER EQA0 219-2MST 219-6MST GND 1 2 3 4 EQA1 SCL SDA VIH 219-6MST B R54 1k R55 R56 2k 2k J9 SW5 OFF VIH GND GND VIH GND GND R26 R27 R28 R29 R30 R31 R50 1k R51 1k R52 1k GND ON 249 4.99k 249 249 4.99k 249 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 SCL SDA C SMBUS SLAVE MODE SETTINGS: SW1 - AD3, AD2 SW2 - ENSMB = 1K TO VDD SW3 - OFF POSTION SW4 - ON POSTION (SDA, SCL) SW5 - AD1, AD0 SW6 - SD_TH, RES SW7 - ON (GND) FOR 3.3V SW8 - RD_EN2-4=ON (SD_TH) SW9 - OFF POSTION SW10 - RXDET, RATE SW11 - EQA0, EQA1 SW12 - OFF POSITION WHEN USING SPA BOARD SW13 - OFF POSTION SW14 - PRSNT2_4=ON B DEMB0_AD1 SMBUS MASTER (READ EEPROM) MODE SETTINGS: SW1 - AD3, AD2 SW2 - ENSMB = FLOAT SW3 - OFF POSTION SW4 - ON POSTION (SDA, SCL) SW5 - AD1, AD0 SW6 - OFF POSITION SW7 - ON (GND) FOR 3.3V SW8 - SD_TH=ON, RD_EN2-4=OFF SW9 - ON POSTION (ALL_DONE TO RD_EN, ALL_DONE4 TO PRSNT) SW10 - RXDET, RATE SW11 - EQA0, EQA1 SW12 - OFF POSITION SW13 - GND TO START THE READ PROCESS SW14 - OFF POSITION 4808-3004-CP DEMB1_AD0 SW14 OFF ON PRSNT2_1 PRSNT2_2 PRSNT2_3 PRSNT2_4 219-6MST FOR 16X LANES SET PRSNT TO PRSNT2_4 PRSNT 219-4MST A Title PCIE16X_800EVK Size B Date: 5 4 3 2 Document Number DS80PCI800 PCIE 16X CARD PAGE 2 Thursday, January 06, 2011 Rev A Sheet 1 1 of 1 A