Not Recommend for New Designs
PTMA403033
PTMA402050
PTMA401120
www.ti.com
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
10-W, 36-V to 75-V INPUT, 1500-V ISOLATION, DC/DC CONVERTERS
FEATURES
APPLICATIONS
•
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•
•
•
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Input Voltage: 36 V to 75 V
10-W Total Output Power
Output Voltages: 3.3 V, 5 V, and 12 V
Output Voltage Trim ±10%
Up To 87% Efficiency
Overcurrent Protection
Input Undervoltage Lockout
Output Overvoltage Protection
Positive or Negative Logic
Enable Control Option
Synchronization Option
Space-Saving, Industry Standard Footprint
(1.1 in x 1.0 in) / (27.94 mm × 24.38 mm)
Industry Standard Pinout
Surface Mount Package
1500-Vdc Isolation
Agency Approvals:
UL/IEC/CSA-C22.2 60950-1
Intermediate Bus Architectures
Telecom, High-End Computing Platforms
Power Over Ethernet Applications
Multi-Rail Power Systems
DESCRIPTION
The PTMA40XX is a series of 10-W rated isolated dc/dc converters, designed to operate from a standard -48-V
telecom central office supply. Housed in an industry standard 1.1 in × 1.0 in (27.94 mm × 24.38 mm) package,
this series of isolated modules is set to one of the common intermediate bus voltages of 3.3 V, 5 V, or 12 V.
The PTMA40XX series includes many features expected of high-performance dc/dc converter modules.
Operational features include an input undervoltage lockout (UVLO) and a dual-logic output enable control or
synchronization option. Overcurrent protection ensures survival against load faults.
Typical applications include distributed power architectures in both telecom and computing environments, power
over ethernet, and particularly complex digital systems requiring multiple power supply rails.
TYPICAL APPLICATION
1
CI
47 µF
(optional)
VO+ 4
VI+
PTMA40XXXX
2
VI−
RTRIM(down)
(optional)
Trim 5
RTRIM(up)
(optional)
3 Enable/Sync
CO
47 µF
(optional)
VO− 6
UDG−06003
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
www.ti.com
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see
the TI website at www.ti.com.
PART NUMBERING SCHEME
Input
Voltage
Output
Current
4
02
4 = 48 V
01 = 1 A
033 = 3.3 V
A = None
1 = None
D = Through-hole, Pb-free
Blank = Tray
02 = 2 A
050 = 5.0 V
N = Negative
2 = VO Adjust
S = SMD, SnPb solder ball
T = Tape and Reel
03 = 3 A
120 = 12.0 V
P = Positive
3 = VO Adjust &
Syncronization
Z = SMD, SnAgCu solder
ball
PTMA
Output
Voltage
050
Enable
Electrical
Options
P
2
Pin Style
A
Shipping
Package
D
T
ABSOLUTE MAXIMUM RATINGS
UNIT
Continuous
VI
Input Voltage
TA
Operating temperature range
Over VI range
TWAVE
Wave solder temperature
Surface temperature of module or pins
(20 seconds)
TREFLOW
Solder reflow temperature
Surface temperature of module or pins
(20 seconds)
TSTG
Storage temperature
PO
Output Power
(1)
(2)
Surge, 1 s max
75 V
100 V
(1)
–40°C to 85°C
AD suffix
260°C
(2)
AS suffix
235°C
(2)
AZ suffix
260°C
(2)
–55°C to 125°C
10 W
The converter's internal protection circuitry may cause the output to turn off when the applied input voltage is greater than 75 V.
During solder reflow of SMD package version, do not elevate the module PCB, pins, or internal component temperatures beyond this
peak temperature.
PACKAGE SPECIFICATIONS
UNITS
Weight
Flammability
Meets UL94V-O
Mechanical shock
Per Mil-STD-883D, Method 2002.3, 1 ms,
1/2 Sine, mounted
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20-2000 Hz,
PCB mounted
Reliability
Telcordia SR-332 50% stress, TA = 40°C, ground benign
(1)
2
6.5 grams
Qualification limit.
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500 G
(1)
Horizontal SMD
(Suffix AS & AZ)
500 G
(1)
Horizontal T/H (Suffix AD)
20 G
(1)
Horizontal SMD
(Suffix AS & AZ)
10 G
(1)
Horizontal T/H (Suffix AD)
MTBF
7.3 106 Hr
PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
www.ti.com
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
PTMA403033 ELECTRICAL CHARACTERISTICS
TA = 25°C, VI = 48 V, VO = 3.3 V, CI = 0 µF, CO = 0 µF, and IO = IOmax (Unless otherwise stated)
PARAMETER
PO
Output power
PTMA403033
TEST CONDITIONS
MIN
Output current
Over VI range
ILIM
Current Limit Threshold
Shutdown, followed by autorecovery
VI
Input voltage range
Over IO range
0.1
(1)
3
36
W
(2)
A
75
V
A
48
±2
UNIT
10
4.25
Set-point voltage tolerance
η
MAX
Over VI range
IO
VO
TYP
(3)
%VO
Temperature variation
-40°C ≤ TA ≤ 85°C
±1
%VO
Line regulation
Over VI range
±3
mV
Load regulation
Over IO range
±10
Total output voltage variation
Includes set-point, line, load, –40°C ≤ TA ≤ 85°C
Trim adjust range
Over VI range
Efficiency
PO = POmax
VO Ripple (peak-to-peak)
20-MHz bandwidth
Transient response
0.1 A/µs load step,
50% to 100%
IOmax
Referenced to VI–
Output enable input (pin 3)
3
3.0
(3)
3.6
%VO
V
82%
65
mVpp
Recovery time
750
µs
VO over/undershoot
±150
Input high voltage (VIH)
4.5
Input low voltage (VIL)
–0.2
mV
Open
(4)
0.8
Input low current (IIL)
Standby input current
mV
5
1
Pin 3 open
V
mA
8
mA
UVLO
Undervoltage lockout
32
34
V
OVP
Output Overvoltage Protection
3.7
5.4
V
ƒS
Switching frequency
300
350
kHz
(5)
250
Sync switching frequency
SYNC
Over VI and IO ranges (non-Sync option)
250
Free-running
180
Synchronization range
250
(5)
3.5
6
V
0.5
V
25
0
CO
External output capacitance
0
VISO
Isolation voltage
CISO
Isolation capacitance
RISO
Isolation resistance
(5)
(6)
kHz
–0.3
External input capacitance
(4)
(5)
low-level input voltage
clock duty cycle
(2)
(3)
350
high-level input voltage
CI
(1)
215
75
47
(6)
1,500
Primary-Secondary
1000
µF
Vdc
1,100
10
%
µF
47
pF
MΩ
The converter requires a minimum load current for proper operation. However, the converter is not damaged when operated under a
no-load condition.
See temperature derating curves for safe operating area (SOA), to determine output current derating at elevated ambient temperatures.
The set-point voltage tolerance is affected by the tolerance and stability of RTRIM. The stated limit is unconditionally met if RTRIM has a
tolerance of ≤1%, with ≤100 ppm/°C temperature stability.
The Enable input (pin 3) has an internal pullup resistor. Do not place an external pullup resistor on this input pin. If the enable feature is
not used, for a positive enable device this input should be left open circuit and a negative enable device should be permanently
connected to VI– (pin 2). A discrete MOSFET or bipolar transistor is recommended for the enable control. The open-circuit voltage is
typically less than 5 V. See the Application Information for a more detailed description.
A device with the synchronization option has a reduced switching frequency of 215 kHz typical. The synchronization frequency can only
be adjusted to a higher frequency, up to 350 kHz maximum.
An output capacitor is not required for proper operation. However, additional capacitance at the load improves the transient response.
Submit Documentation Feedback
3
PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
www.ti.com
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
PTMA402050 ELECTRICAL CHARACTERISTICS
TA = 25°C, VI = 48 V, VO = 5 V, CI = 0 µF, CO = 0 µF, and IO = IOmax (Unless otherwise stated)
PARAMETER
PO
Output power
PTMA402050
TEST CONDITIONS
MIN
Output current
Over VI range
ILIM
Current Limit Threshold
Shutdown, followed by autorecovery
VI
Input voltage range
Over IO range
0.1
(1)
2
36
%VO
mV
Over VI range
5
10
Load regulation
Over IO range
Total output voltage variation
Includes set-point, line, load, –40°C ≤ TA ≤ 85°C
Trim adjust range
Over VI range
Efficiency
PO = POmax
VO Ripple (peak-to-peak)
20-MHz bandwidth
Transient response
0.1 A/µs load step,
50% to 100%
IOmax
3
4.5
mV
5
(3)
5.5
%VO
V
85%
55
mVpp
Recovery time
250
µs
VO over/undershoot
±150
Input high voltage (VIH)
4.5
Input low voltage (VIL)
–0.2
mV
Open
(4)
0.8
Input low current (IIL)
1
Pin 3 open
V
mA
8
mA
UVLO
Undervoltage lockout
32
34
V
OVP
Output Overvoltage Protection
5.6
7.9
V
ƒS
Switching frequency
300
350
kHz
(5)
250
Sync switching frequency
SYNC
Over VI range
250
Free-running
180
Synchronization range
250
(5)
6
V
0.5
V
25
CO
External output capacitance
0
VISO
Isolation voltage
CISO
Isolation capacitance
RISO
Isolation resistance
(5)
(6)
kHz
3.5
0
(4)
(5)
–0.3
External input capacitance
(2)
(3)
350
low-level input voltage
CI
(1)
215
high-level input voltage
clock duty cycle
4
V
%VO
Line regulation
Standby input current
75
±1
-40°C ≤ TA ≤ 85°C
Referenced to VI–
A
(3)
Temperature variation
Output enable input (pin 3)
W
(2)
A
48
±2
UNIT
10
3
Set-point voltage tolerance
η
MAX
Over VI range
IO
VO
TYP
75
47
(6)
1,500
Primary-Secondary
1000
µF
Vdc
1,100
10
%
µF
47
pF
MΩ
The converter requires a minimum load current for proper operation. However, the converter is not damaged when operated under a
no-load condition.
See temperature derating curves for safe operating area (SOA), to determine output current derating at elevated ambient temperatures.
The set-point voltage tolerance is affected by the tolerance and stability of RTRIM. The stated limit is unconditionally met if RTRIM has a
tolerance of ≤1%, with ≤100 ppm/°C temperature stability.
The Enable input (pin 3) has an internal pullup resistor. Do not place an external pullup resistor on this input pin. If the enable feature is
not used, for a positive enable device this input should be left open circuit and a negative enable device should be permanently
connected to VI– (pin 2). A discrete MOSFET or bipolar transistor is recommended for the enable control. The open-circuit voltage is
typically less than 5 V. See the Application Information for a more detailed description.
A device with the synchronization option has a reduced switching frequency of 215 kHz typical. The synchronization frequency can only
be adjusted to a higher frequency, up to 350 kHz maximum.
An output capacitor is not required for proper operation. However, additional capacitance at the load will improve the transient response.
Submit Documentation Feedback
PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
www.ti.com
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
PTMA401120 ELECTRICAL CHARACTERISTICS
TA = 25°C, VI = 48 V, VO = 12 V, CI = 0 µF, CO = 0 µF, and IO = IOmax (Unless otherwise stated)
PARAMETER
PO
Output power
PTMA401120
TEST CONDITIONS
MIN
Output current
Over VI range
ILIM
Current Limit Threshold
Shutdown, followed by autorecovery
VI
Input voltage range
Over IO range
0.1
(1)
1
36
(3)
%VO
%VO
Line regulation
Over VI range
10
mV
Load regulation
Over IO range
3
Total output voltage variation
Includes set-point, line, load, –40°C ≤ TA ≤ 85°C
3
Trim adjust range
Over VI range
Efficiency
PO = POmax
VO Ripple (peak-to-peak)
20-MHz bandwidth
Transient Response
0.1 A/µs load step,
50% to 100%
IOmax
Standby input current
UVLO
Undervoltage lockout
OVP
Output Overvoltage Protection
ƒS
Switching frequency
Sync switching frequency
10.8
13.2
%VO
V
85
mVpp
400
µs
VO over/undershoot
±250
Input high voltage (VIH)
4.5
Input low voltage (VIL)
–0.2
(4)
0.8
1
Pin 3 open
V
mA
8
mA
32
34
V
13.5
17.5
V
300
350
kHz
(5)
250
Over VI range
250
Free-running
180
Synchronization range
mV
Open
250
215
(5)
350
(5)
kHz
high-level input voltage
3.5
6
V
low-level input voltage
–0.3
0.5
V
25
75
External input capacitance
0
47
CO
External output capacitance
0
47 (6)
VISO
Isolation voltage
CISO
Isolation capacitance
RISO
Isolation resistance
(6)
(3)
Recovery time
clock duty cycle
(5)
mV
5
87%
CI
(4)
V
±1
Input low current (IIL)
(2)
(3)
75
-40°C ≤ TA ≤ 85°C
Referenced to VI–
(1)
A
Temperature variation
Output enable input (pin 3)
SYNC
W
(2)
A
48
±2
UNIT
12
1.5
Set-point voltage tolerance
η
MAX
Over VI range
IO
VO
TYP
1,500
Primary-Secondary
220
µF
Vdc
1,100
10
%
µF
pF
MΩ
The converter requires a minimum load current for proper operation. The converter is not damaged when operated under a no-load
condition.
See temperature derating curves for safe operating area (SOA), to determine output current derating at elevated ambient temperatures.
The set-point voltage tolerance is affected by the tolerance and stability of RTRIM. The stated limit is unconditionally met if RTRIM has a
tolerance of 1%, with 100 ppm/°C temperature stability.
The Enable input (pin 3) has an internal pullup resistor. Do not place an external pullup resistor on this input pin. If the enable feature is
not used, for a positive enable device this input should be left open circuit and a negative enable device should be permanently
connected to VI– (pin 2). A discrete MOSFET or bipolar transistor is recommended for the enable control. The open-circuit voltage is
typically less than 5 V. See the Application Information for a more detailed description.
A device with the synchronization option has a reduced switching frequency of 215 kHz typical. The synchronization frequency can only
be adjusted to a higher frequency, up to 350 kHz maximum.
An output capacitor is not required for proper operation. However, additional capacitance at the load will improve the transient response.
Submit Documentation Feedback
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PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
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SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
TERMINAL FUNCTIONS
TERMINAL
NAME
Enable/Sync
VI– (1)
VI+
(1)
VO+
DESCRIPTION
NO.
(1)
3
The Enable input is an open-base logic input that is referenced to VI–. Two ON/OFF enable options are available,
positve logic and negative logic. Positive logic devices are enabled by applying a logic high voltage (Open) and
are disabled by applying a logic low voltage (VI–). Negative logic devices are enabled by applying a logic low
voltage (VI–) and are disabled by applying a logic high voltage (Open). See the Application Information section for
more detailed information.
This pin also has the option of a synchronization input. A module that has the synchronization option does not
have ON/OFF enable control. A 5-V logic signal greater than the free-running frequency but ≤ 350 kHz is required
for synchronization control. See the Application Information section for more detailed information.
2
The negative input supply for the module, and the 0-V reference for the Enable/Sync inputs. When powering the
module from a positive source, this input is connected to the input source return.
1
The positive input for the module with respect to VI–. When powering the module from a negative input voltage,
this input is connected to the input source ground.
4
This is the positive power output with respect to VO–. It is dc isolated from the input power pins.
Trim
5
This pin allows the output voltage set point of the module to be increased or decreased up to ± 10 %. Connecting
a resistor between this terminal and VO+ decreases the output voltage set point. Connecting a resistor between
this terminal and VO– increases the output voltage set point. A 0.05-W rated resistor may be used, with tolerance
and temperature stability of 1% and 100 ppm/°C, respectively. If left open circuit, the converter output voltage
defaults to its nominal value. The specification table gives the standard resistor values for the most common
output voltages.
VO–
6
This is the output power return for the VO+ bus. This terminal should be connected to the common of the load
circuit.
(1)
These functions indicate signals electrically common with the input.
3
6
2
1
PTMA40XXXX
(Top View)
5
4
6
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PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
www.ti.com
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
TYPICAL CHARACTERISTICS
PTMA403033 Characteristic Data (VO = 3.3 V)
(1) (2)
EFFICIENCY
vs OUTPUT CURRENT
POWER DISSIPATION
vs OUTPUT CURRENT
85
3.0
VIN = 48 V
VIN = 36 V
η Efficiency − %
75
VIN = 60 V
70
65
VIN = 75 V
60
VIN = 36 V
2.5
PD − Power Dissipation −W
80
2.0
1.5
VIN = 75 V
1.0
VIN = 48 V
0.5
VIN = 60 V
55
0
0
0.5
1.0
1.5
2.5
2.0
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
IO − Output Current − A
IO − Output Current − A
Figure 1.
Figure 2.
OUTPUT VOLTAGE RIPPLE
vs OUTPUT CURRENT
TEMPERATURE DERATING
vs OUTPUT CURRENT
60
90
80
50
VIN = 48 V
40
30
VIN = 60 V
20
VIN = 75 V
10
TA − Ambient Temperature − °C
VO − Output Voltage Ripple − VPP mV
VIN = 36 V
200 LFM
70
60
50
40
30
0
20
0
0.5
1.0
1.5
2.0
IO − Output Current − A
2.5
0
(2)
0.5
1.0
1.5
2.0
2.5
3.0
IO − Output Current − A
Figure 3.
(1)
Natural
Convection
Figure 4.
All data listed in Figure 1, Figure 2, and Figure 3 have been developed from actual products tested at 25°C. This data is considered
typical data for the dc-dc converter.
The temperature derating curves represent operating conditions at which internal components are at or below manufacturer's maximum
rated operating temperature. Derating limits apply to modules soldered directly to a 100–mm × 100–mm, double-sided PCB with 2 oz.
copper. For surface mount packages, multiple vias (plated through holes) are required to add thermal paths around the power pins.
Please refer to the mechanical specification for more information. Applies to Figure 4.
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PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
www.ti.com
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
PTMA402050 Characteristic Data (VO = 5 V)
(3) (4)
EFFICIENCY
vs OUTPUT CURRENT
POWER DISSIPATION
vs OUTPUT CURRENT
2.0
85
VIN = 48 V
PD − Power Dissipation −W
VIN = 36 V
80
η Efficiency − %
75
VIN = 60 V
70
65
1.6
VIN = 75 V
1.2
VIN = 60 V
VIN = 75 V
60
VIN = 48 V
0.4
55
0
0.5
1.0
1.5
2.5
2.0
0
3.0
0.5
IO − Output Current − A
Figure 6.
OUTPUT VOLTAGE RIPPLE
vs OUTPUT CURRENT
TEMPERATURE DERATING
vs OUTPUT CURRENT
80
VIN = 48 V
VIN = 36 V
40
30
VIN = 60 V
20
VIN = 75 V
10
TA − Ambient Temperature − °C
VO − Output Voltage Ripple − VPP mV
50
Natural
Convection
70
60
50
40
30
20
0
0.5
1.0
1.5
2.0
0
IO − Output Current − A
Figure 7.
8
2.0
90
0
(4)
1.0
1.5
IO − Output Current − A
Figure 5.
60
(3)
VIN = 36 V
0.8
0.5
1.0
1.5
IO − Output Current − A
2.0
Figure 8.
All data listed in Figure 5, Figure 7, and Figure 6 have been developed from actual products tested at 25°C. This data is considered
typical data for the dc-dc converter.
The temperature derating curves represent operating conditions at which internal components are at or below manufacturer's maximum
rated operating temperature. Derating limits apply to modules soldered directly to a 100–mm × 100–mm, double-sided PCB with 2 oz.
copper. For surface mount packages, multiple vias (plated through holes) are required to add thermal paths around the power pins.
Please refer to the mechanical specification for more information. Applies to Figure 8.
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PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
www.ti.com
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
PTMA401120 Characteristic Data (VO = 12 V)
(5) (6)
EFFICIENCY
vs OUTPUT CURRENT
POWER DISSIPATION
vs OUTPUT CURRENT
90
2
VIN = 36 V
85
VIN = 48 V
VIN = 60 V
1.6
PD − Power Dissipation − W
η − Efficiency − %
VIN = 60 V
80
VIN = 75 V
75
70
VIN = 75 V
1.2
VIN = 48 V
0.8
65
VIN = 36 V
60
0
0.2
0.4
0.6
0.8
0.4
0
1
0.2
Figure 9.
Figure 10.
OUTPUT VOLTAGE RIPPLE
vs OUTPUT CURRENT
TEMPERATURE DERATING
vs OUTPUT CURRENT
0.8
1
0.8
1
90
70
80
VIN = 60 V
VIN = 48 V
o
60
Ambient Temperature − C
VO − Output Voltage Ripple − VPP (mW)
80
VIN = 36 V
50
40
VIN = 75 V
30
20
Natural
Convection
70
60
50
40
30
20
10
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
IO − Output Current − A
IO − Output Current − A
Figure 11.
(6)
0.6
IO − Output Current − A
IO − Output Current − A
(5)
0.4
Figure 12.
All data listed in Figure 9, Figure 10, and Figure 11 have been developed from actual products tested at 25°C. This data is considered
typical data for the dc-dc converter.
The temperature derating curves represent operating conditions at which internal components are at or below manufacturer's maximum
rated operating temperature. Derating limits apply to modules soldered directly to a 100–mm × 100–mm, double-sided PCB with 2 oz.
copper. For surface mount packages, multiple vias (plated through holes) are required to add thermal paths around the power pins.
Please refer to the mechanical specification for more information. Applies to Figure 12.
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9
PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
www.ti.com
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
APPLICATION INFORMATION
Operating Features and System Considerations for the PTMA40XX DC/DC Converters
Primary-Secondary Isolation
These converters incorporate electrical isolation between the input terminals (primary) and the output terminals
(secondary). All converters are tested to a withstand voltage of 1500 Vdc. This complies with UL/cUL 60950 and
EN 60950 and the requirements for functional isolation. It allows the converter to be configured for either a
positive or negative input voltage source. The data sheet Terminal Functions table provides guidance as to the
correct reference that must be used for the external control signals.
Undervoltage Lockout
The undervoltage lockout (UVLO) is designed to prevent the operation of the converter until the input voltage is
close to the minimum operating voltage. The converter is held off when the input voltage is below the UVLO
threshold, and turns on when the input voltage rises above the threshold. This prevents high start-up current
during normal power up of the converter, and minimizes the current drain from the input source during low input
voltage conditions. The converter meets full specifications when the minimum specified input voltage is reached.
The UVLO circuitry also overrides the operation of the enable or synchronization controls. Only when the input
voltage is above the UVLO threshold does this input become functional.
Output Overvoltage Clamp
The module is protected from an overvoltage on the output using an internal clamp. This protects against a
break in the feedback path as well as a ground fault on the external Trim resistor, which would cause the output
voltage to increase.
Overcurrent Protection
To protect against load faults, these converters incorporate output overcurrent protection. Applying a load to the
output that exceeds the converter overcurrent threshold (see applicable specification) causes the output voltage
to momentarily fold back, and then shut down. Following shutdown, the module periodically attempts to
automatically recover by initiating a soft-start power up. This is often described as a hiccup mode of operation,
whereby the module continues in the cycle of successive shutdown and power up until the load fault is removed.
Once the fault is removed, the converter automatically recovers and returns to normal operation.
Soft-Start Power Up
When the converter is first powered, the internal soft-start circuit limits how fast the output voltage can rise. The
soft-start circuit functions after a valid input source is applied and the output is enabled, after the converter
output is enabled using the Enable input, or on a recovery from a load fault. The purpose of the soft-start feature
is to limit the surge of current drawn from the input source when the converter begins to operate. By limiting the
rate at which the output voltage rises, the magnitude of current required to charge up the load circuit
capacitance is significantly reduced.
Figure 13 shows the power-up characteristic of a PTMA403033 converter. The output voltage is 3.3 V. The
soft-start circuit causes a slow, soft rise of the output voltage. The output voltage will begin to rise after a time
delay (typically 85 ms-100 ms) once a valid input voltage is applied. The output then progressively rises to the
voltage set-point. The waveforms were recorded with a resistive load of 3 A.
10
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PTMA402050
PTMA401120
Not Recommend for New Designs
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SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
APPLICATION INFORMATION (continued)
VIN (10 V/div)
VOUT
(1 V/div)
IIN (100 mA/div)
t − Time − 20 ms/div
Figure 13. Power-up Waveforms
Output Voltage Trim Adjustment
An external resistor is required to increase or decrease the output voltage set point of the module by ± 10 %.
The resistor, RTRIM, must be connected between the TRIM pin (pin 5) and VO+ (pin 4) to decrease the output
voltage, or between the TRIM pin and VO– (pin 6) to increase the output voltage. A 0.05-W rated resistor can be
used. The tolerance should be 1%, with a temperature stability of 100 ppm/°C (or better). Place the resistor
close to the converter and connect it using dedicated PCB traces (see Figure 14). Table 1 gives the nearest
standard value of external resistor for the common voltages within each model's adjust range.
Table 1. Standard Values of RTRIM for Common Output Voltages
PTMA403033
VO
(required)
PTMA402050
RTRIM (kΩ)
down
up
3.0 V
118
—
3.1 V
187
—
3.2 V
392
3.3 V
VO
(required)
PTMA401120
RTRIM (kΩ)
down
up
4.5 V
18.7
—
4.6 V
24.9
—
—
4.7 V
35.7
open
open
4.8 V
57.6
3.4 V
—
249
4.9 V
121
—
3.5 V
—
124
5.0 V
open
open
3.6 V
—
82.5
5.1 V
—
124
—
—
—
5.2 V
—
—
—
—
5.3 V
—
—
—
—
5.4 V
—
—
—
—
—
—
—
—
—
VO
(required)
RTRIM (kΩ)
down
up
10.8 V
64.9
—
11.0 V
80.6
—
—
11.2 V
105
—
—
11.4 V
143
—
11.6 V
221
—
11.8 V
464
—
12.0 V
open
open
61.9
12.2 V
—
118
40.2
12.4 V
—
57.6
—
29.4
12.6 V
—
36.5
5.5 V
—
23.2
12.8 V
—
26.1
—
—
—
13.0 V
—
19.6
—
—
—
13.2 V
—
15.8
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11
PTMA403033
PTMA402050
PTMA401120
Not Recommend for New Designs
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SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
For other output voltages, the value of the required trim resistor may be calculated using Equation 1 to adjust
the voltage up or Equation 2 to adjust the voltage down.
RO V R
R TRIM(up) +
* RP (kW)
ǒVO * VSETǓ
(1)
RO ǒVO * VRǓ
R TRIM(dwn) +
* R P (kW)
ǒVSET * VOǓ
(2)
Table 2 gives the required RTRIM equation constants for the converter model selected. To calculate the required
value of RTRIM, simply locate the applicable constants and substitute these into the formula along with the
desired output voltage.
Table 2. Trim Adjust Equation Constants
Constants
PTMA403033
PTMA402050
PTMA401120
VR (V)
1.24
2.50
2.50
RO (Ω)
20
5.11
10
RP (Ω)
1.0
2.05
5.11
VSET (V)
3.3
5.0
12.0
VO(V)
Desired Output Voltage
Desired Output Voltage
Desired Output Voltage
VO +
VO +
4
TRIM
5
RTRIM
VO +
VO +
4
TRIM
5
CO
CO
RTRIM
VO −
6
VO −
6
VO −
VO −
(a) TRIM DOWN
(b) TRIM UP
Figure 14. Output Voltage Adjustment
Thermal Considerations
Airflow may be necessary to ensure that the module can supply the desired load current in environments with
elevated ambient temperatures. The required airflow rate is determined from the safe operating area (SOA). The
SOA is the area beneath the applicable airflow rate curve on the graph of temperature derating vs output
current. (See the Typical Characteristics.) Operating the converter within the SOA limits ensures that all the
internal components are at or below their stated maximum operating temperatures.
On/Off Enable Controls
On/Off enable options include positive logic or negative logic. A positive logic device enables the module's
output when a logic high voltage is present on the Enable pin (pin 3) and disables the output with a logic low
voltage. A negative logic device disables the output when a logic high voltage is present on the Enable pin and
enables the output during a logic low voltage. See the Electrical Characteristics table for logic high and logic low
limits. The Enable pin is ideally controlled with an open-collector (or open-drain) discrete transistor. See
Figure 15 below for a typical On/Off Enable control circuit. For automatic start-up, the Enable pin should be left
open for a positive logic module and should be shorted to VI– (pin 2) for a negative logic module. Both inputs are
electrically referenced to VI– on the primary (input) side of the converter. Do not place an external pull-up
resistor on this input pin.
12
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PTMA403033
PTMA402050
PTMA401120
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
Enable Control Schematic
VI +
1
VI +
3 ENABLE/SYNC
On/Off Control
2
VI −
VI −
Figure 15. Typical On/Off Enable Control Circuit
On/Off Enable Turn-On Time
Once enabled, the converter executes a soft-start power up. The converter exibits a short delay of approximately
100 µs, measured from the transition of the enable signal to the instance the VO Bus output begins to rise. The
output is in regulation within 1.5 ms.
VOUT (1 V/div)
IIN (100 mA/div)
VENABLE (5 V/div)
t − Time − 1 ms/div
Figure 16. Output Enable Power-Up Characteristic
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PTMA402050
PTMA401120
Not Recommend for New Designs
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SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
Synchronization
The Synchronization option allows multiple power modules to be synchronized to a common frequency. Driving
the Sync pin (pin 3) with an external clock set to the desired frequency, synchronizes all connected modules to
that frequency. Modules with the synchronization option have a reduced free-running switching frequency of
215 kHz typical. The synchronization frequency can only be adjusted to a higher frequency, up to 350 kHz. A
5-V logic signal is recommended for control. See Figure 17. See the Electrical Characteristics table for
synchronization limits.
VI +
1
VI +
2
VI −
VI −
3
ENABLE/SYNC
Sync
Control
Figure 17. Synchronization Control
MECHANICALS
Tape and Reel
TOLERANCES UNLESS
OTHERWISE SPECIFIED
.XX = ±0.005 HOLES = ±0.001
.XXX = ±0.003 ANGLES = ± 1/2”
©
This Document and the information
contained herein is confidential and
proprietary to Texas Instrumants, and
may not be reproduced or used for any
purpose without the expressed written
permission of Texas Instruments.
14
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PTMA403033
PTMA402050
PTMA401120
SLTS259B – FEBRUARY 2006 – REVISED MAY 2007
MECHANICALS (continued)
Tray
©
This Document and the information
contained herein is confidential and
proprietary to Texas Instrumants, and
may not be reproduced or used for any
purpose without the expressed written
permission of Texas Instruments.
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
(4/5)
(6)
PTMA401120A1AD
NRND
ThroughHole Module
EEP
4
30
RoHS (In
Work) & Green
(In Work)
SN
N / A for Pkg Type
PTMA401120A1AZ
NRND
Surface
Mount Module
BET
4
30
RoHS (In
Work) & Green
(In Work)
SNAGCU
Level-3-260C-168 HR
PTMA401120A2AD
NRND
ThroughHole Module
EEV
5
30
RoHS (In
Work) & Green
(In Work)
SN
N / A for Pkg Type
PTMA401120N1AD
NRND
ThroughHole Module
EEP
5
30
RoHS (In
Work) & Green
(In Work)
SN
N / A for Pkg Type
PTMA401120N2AD
NRND
ThroughHole Module
EEP
6
30
RoHS (In
Work) & Green
(In Work)
SN
N / A for Pkg Type
PTMA401120P1AD
NRND
ThroughHole Module
EEP
5
30
RoHS (In
Work) & Green
(In Work)
SN
N / A for Pkg Type
PTMA401120P2AD
NRND
ThroughHole Module
EEP
6
30
RoHS (In
Work) & Green
(In Work)
SN
N / A for Pkg Type
PTMA401120P2AZ
NRND
Surface
Mount Module
BET
6
30
RoHS (In
Work) & Green
(In Work)
SNAGCU
Level-3-260C-168 HR
PTMA402050A1AD
NRND
ThroughHole Module
EEP
4
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
PTMA402050A1AZ
NRND
Surface
Mount Module
BET
4
30
RoHS (In Work)
& non-Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
PTMA402050A2AD
NRND
ThroughHole Module
EEV
5
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
PTMA402050A3AD
NRND
ThroughHole Module
EEP
6
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
PTMA402050N2AD
NRND
ThroughHole Module
EEP
6
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
Addendum-Page 1
Device Marking
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
7-Oct-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
(4/5)
(6)
PTMA402050N2AS
NRND
Surface
Mount Module
EET
6
30
Non-RoHS
& non-Green
PTMA402050N2AST
NRND
Surface
Mount Module
EET
6
250
Non-RoHS
& non-Green
PTMA402050N2AZ
NRND
Surface
Mount Module
BET
6
30
RoHS (In Work)
& non-Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
PTMA402050P2AD
NRND
ThroughHole Module
EEP
6
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
PTMA402050P2AZ
NRND
Surface
Mount Module
BET
6
30
RoHS (In Work)
& non-Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
PTMA403033A1AD
NRND
ThroughHole Module
EEP
4
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
PTMA403033A1AZ
NRND
Surface
Mount Module
BET
4
30
RoHS (In Work)
& non-Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
PTMA403033A3AD
NRND
ThroughHole Module
EEP
6
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
PTMA403033A3AZ
NRND
Surface
Mount Module
BET
6
30
RoHS (In Work)
& non-Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
PTMA403033N1AD
NRND
ThroughHole Module
EEP
5
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
PTMA403033N1AZT
NRND
Surface
Mount Module
BET
5
250
RoHS (In Work)
& non-Green
PTMA403033N2AD
NRND
ThroughHole Module
EEP
6
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
PTMA403033N2AZ
NRND
Surface
Mount Module
BET
6
30
RoHS (In Work)
& non-Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
PTMA403033N2AZT
NRND
Surface
Mount Module
BET
6
250
RoHS (In Work)
& non-Green
PTMA403033P1AD
NRND
ThroughHole Module
EEP
5
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
PTMA403033P2AD
NRND
ThroughHole Module
EEP
6
30
RoHS (In Work)
& non-Green
SN
N / A for Pkg Type
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 2
SNPB
Level-1-235C-UNLIM/
Level-3-260C-168HRS
Device Marking
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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