S5LS20206ASPGEQQ1

Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 TMS570LS Series 16/32-BIT RISC Flash Microcontroller 1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller 1.1 Features 1 • High-Performance Automotive Grade Microcontroller for Safety Critical Applications – Dual CPUs running in Lockstep – ECC on Flash and SRAM – CPU and Memory BIST (Built-In Self Test) – Error Signaling Module (ESM) w/ Error Pin • ARM® Cortex™-R4F 32-Bit RISC CPU – Efficient 1.6 DMIPS/MHz with 8-stage pipeline – Floating Point Unit with Single/Double Precision – Memory Protection Unit (MPU) – Open Architecture With Third-Party Support • Operating Features – Up to 160-MHz System Clock – Core Supply Voltage (VCC): 1.5 V – I/O Supply Voltage (VCCIO): 3.3 V • Integrated Memory – 1M-Byte or 2M-Byte Flash with ECC – 128K-Byte or 160K-Byte RAM with ECC • Multiple Communication interfaces including FlexRay, CAN, and LIN • NHET Timer and 2x 12-bit ADCs • External Memory Interface (EMIF) – 16bit Data, 22bit Address, 4 Chip Selects • Common TMS470/570 Platform Architecture – Consistent Memory Map across the family – Real-Time Interrupt (RTI) OS Timer – Vectored Interrupt Module (VIM) – Cyclic Redundancy Checker (CRC, 2 Channels) • Direct Memory Access (DMA) Controller – 32 DMA requests and 16 Channels/ Control Packets – Parity on Control Packet Memory – Dedicated Memory Protection Unit (MPU) • Frequency-Modulated Zero-Pin Phase-Locked Loop (FMzPLL)-Based Clock Module – Oscillator and PLL clock monitor • Up to 115 Peripheral IO pins – 16 Dedicated GIO - 8 w/ External Interrupts – Programmable External Clock (ECLK) • Communication Interfaces – Three Multi-buffered Serial Peripheral Interface (MibSPI) each with: – Four Chip Selects and one Enable pin – 128 buffers with parity – One with parallel mode – Two UART (SCI) interfaces with Local Interconnect Network Interface (LIN 2.0) – Three CAN (DCAN) Controller – Two with 64 mailboxes, one with 32 – Parity on mailbox RAM – Dual Channel FlexRay™ Controller – 8K-Byte message RAM with parity – Transfer Unit with MPU and parity • High-End Timer (NHET) – 32 Programmable I/O Channels – 128 Words High-End Timer RAM with parity – Transfer Unit with MPU and parity • Two 12-Bit Multi-Buffered ADCs (MibADC) – 24 total ADC Input channels – Each has 64 Buffers with parity • Trace and Calibration Interfaces – Embedded Trace Module (ETMR4) – Data Modification Module (DMM) – RAM Trace Port (RTP) – Parameter Overlay Module (POM) • On-Chip emulation logic including IEEE 1149.1 JTAG, Boundary Scan and ARM Coresight components • Full Development Kit Available – Development Boards – Code Composer Studio Integrated Development Environment (IDE) – HaLCoGen Code Generation Tool – HET Assembler and Simulator – nowFlash Flash Programming Tool • Packages Supported – 144-Pin Quad Flat Pack (PGE) [Green] – 337-Pin Ball Grid Array (ZWT) [Green] • Community Resources – TI E2E™ Online Community 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 1.2 www.ti.com Description The TMS570LS series is a high performance automotive grade microcontroller family. The safety architecture includes Dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic, ECC on both the Flash and the data SRAM, parity on peripheral memories, and loop back capability on peripheral IOs. The TMS570LS family integrates the ARM® Cortex™-R4F Floating Point CPU which offers an efficient 1.6 DMIPS/MHz, and has configurations which can run up to 160 MHz providing more than 250 DMIPS. The TMS570LS series also provides different Flash (1MB or 2MB) and data SRAM (128KB or 160KB) options with single bit error correction and double bit error detection. The TMS570LS devices feature peripherals for real-time control-based applications, including up to 32 nHET timer channels and two 12-bit A to D converters supporting up to 24 inputs. There are multiple communication interfaces including a 2-channel FlexRay, 3 CAN controllers supporting 64 mailboxes each, and 2 LIN/UART controllers. With integrated safety features and a wide choice of communication and control peripherals, the TMS570LS series is an ideal solution for high performance real time control applications with safety critical requirements. The devices included in the TMS570LS series and described in this document are: • TMS570LS20216 • TMS570LS20206 • TMS570LS10216 • TMS570LS10206 • TMS570LS10116 • TMS570LS10106 The TMS570LS series microcontrollers contain the following: • Dual TMS570 16/32-Bit RISC (ARM Cortex™-R4F) in Lockstep • Up to 2M-Byte Program Flash with ECC • Up to 160K-Byte Static RAM (SRAM) with ECC • Real-Time Interrupt (RTI) Operating System Timer • Vectored Interrupt Module (VIM) • Cyclic Redundancy Checker (CRC) with Parallel Signature Analysis (PSA) • Direct Memory Access (DMA) Controller • Frequency-Modulated Phase-Locked Loop (FMzPLL)-Based Clock Module With Prescaler • Three Multi-buffered Serial Peripheral Interfaces (MibSPI) • Two UARTs (SCI) with Local Interconnect Network Interfaces (LIN) • Three CAN Controllers (DCAN) • High-End Timer (NHET) with dedicated Transfer Unit (HTU) • Available FlexRay Controller with dedicated PLL and Transfer Unit (FTU) • External Clock Prescale (ECP) Module • Two 16-Channel 12-Bit Multi-Buffered ADCs (MibADC) - 8 shared channels between the two ADCs • Address Bus Parity with Failure Detection • Error Signaling Module (ESM) with external error pin • Voltage Monitor (VMON) with out of range reset assertion • Embedded Trace Module (ETMR4) • Data Modification Module (DMM) • RAM Trace Port (RTP) • Parameter Overlay Module (POM) 2 TMS570LS Series 16/32-BIT RISC Flash Microcontroller Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com • • • SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 16 Dedicated General-Purpose I/O (GIO) Pins for ZWT; 8 Dedicated GIO Pins for PGE 115 Total Peripheral I/Os for ZWT; 68 Total Peripheral I/Os for PGE 16-Bit External Memory Interface (EMIF) The devices utilize the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. The device memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, halfword, and word modes. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3V supply input (same level as I/O supply) for all read, program and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 160 MHz. The device has nine communication interfaces: three MibSPIs, two LIN/SCIs, three DCANs and one FlexRay™ controller (optional). The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The FlexRay uses a dual channel serial, fixed time base multimaster communication protocol with communication rates of 10 megabits per second (Mbps) per channel. A FlexRay Transfer Unit (FTU) enables autonomous transfers of FlexRay data to and from main CPU memory. Transfers are protected by a dedicated, built-in Memory Protection Unit (MPU). The NHET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The NHET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer Transfer Unit (HET-TU) provides features to transfer NHET data to or from main memory. A Memory Protection Unit (MPU) is built into the HET-TU to protect against erroneous transfers. The device has two 12-bit-resolution MibADCs with 24 total channels and 64 words of parity protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Eight channels are shared between the two ADCs. There are three separate groupings, two of which are triggerable by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. The frequency-modulated phase-locked loop (FMzPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler. The function of the FMzPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMzPLL provides one of the six possible clock source inputs to the global clock module (GCM). The GCM module provides system clock (HCLK), real-time interrupt clock (RTICLK1), CPU clock (GCLK), NHET clock (VCLK2), DCAN clock (AVCLK1), and peripheral interface clock (VCLK) to all other peripheral modules. The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. The Direct Memory Access Controller (DMA) has 32 DMA requests, 16 Channels/ Control Packets and parity protection on its memory. The DMA provides memory to memory transfer capabilities without CPU interaction. A Memory Protection Unit (MPU) is built into the DMA to protect memory against erroneous transfers. The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or external Error pin is triggered when a fault is detected. TMS570LS Series 16/32-BIT RISC Flash Microcontroller Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 3 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com The External Memory Interface (EMIF) provides a memory extension to asynchronous memories or other slave devices. Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built in ARM Cortex™-R4F CoreSight™ debug features, an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port Module (RTP) is implemented to support high-speed output of RAM accesses by the CPU or any other master. A Direct Memory Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can re-route Flash accesses to the EMIF, thus avoiding the reprogramming steps necessary for parameter updates in Flash. 4 TMS570LS Series 16/32-BIT RISC Flash Microcontroller Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 1.3 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Functional Block Diagram ETMDATA[31:0] ETMTRACECTL DAP ETM CCM-R4 ETMTRACECLKOUT ETMTRACECLKIN VCCP1 FLTP1 FLTP2 RAM Flash 2.0MB with ECC 160kB Cortex-R4F with MPU P O M with ECC Cortex-R4F with MPU STC LBIST 32 Regions DMMENA DMMSYNC DMMCLK DMMDATA[1:0] DMMDATA[15:2]* FlexRay HET TU 8 DCP TU 16 Channels 1 Port with Parity with MPU with MPU with Parity SCR1 ERROR LIN1 LIN2 FlexRay 8k Byte Msg RAM with Parity 128 Words with Parity SYS MiBSPI1 8 Transfer Groups Primary SCR 128 Buffers with Parity EMIFDQM[1:0] EMIFDATA[15:0] EMIFADD[21:0] EMIFBADD[1:0] EMIFCS[3:0] EMIFWE EMIFOE OSCIN OSCOUT Kelvin_GND SCR CRC Periph Bridge 2 Channel EMIF PCR MiBSPI3 8 Transfer Groups 128 Buffers with Parity MiBSPIP5 OSC Clock Monitor 8 Transfer Groups FMzPLL RTI FPLL VIM for FlexRay 64 Channel with Parity 128 Buffers with Parity DCAN1 64 Messages with Parity DCAN2 64 Messages with Parity 64 Words 64 Words with Parity 12Bit 64 Words with Parity 12Bit 2 RAM blocks AD2IN[7:0] AD2EVT MiBADC2 VCCAD VSSAD ADREFHI ADREFLO VMON MiBADC1 RTPENA RTPSYNC RTPCLK RTPDATA[15:0] VccIO RTP AD1IN[7:0] AD1EVT ADSIN[15:8] Vcc FRAYRX1 FRAYTX1 FRAYTXEN1 FRAYRX2 FRAYTX2 FRAYTXEN2 NHET[31:0] with MPU with Parity SCR2 ESM RTCK TDI TDO LIN1RX LIN1TX LIN2RX LIN2TX NHET DMA DMM with ICEPick TRST TMS TCK DCAN3 32 Messages with Parity GIO RST PORRST TEST ECLK MIBSPI1SIMO MIBSPI1SOMI MIBSPI1CLK MIBSPI1SCS[3:0] MIBSPI1ENA MIBSPI3SIMO MIBSPI3SOMI MIBSPI3CLK MIBSPI3SCS[3:0] MIBSPI3ENA MIBSPI5SIMO[3:0]* MIBSPI5SOMI[3:0]* MIBSPI5CLK* MIBSPI5SCS[3:0]* MIBSPI5ENA* CAN1RX CAN1TX CAN2RX CAN2TX CAN3RX CAN3TX GIOA[7:0]/INT[7:0] GIOB[7:0] Note: Priorities SCR : round robin SCR1 : 1=DMA, 2=DMM, 3=DAP SCR2 : round robin * MIBSPIP5 pins are multiplexed with DMMDATA[15:2] pins TMS570LS Series 16/32-BIT RISC Flash Microcontroller Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 5 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table of Contents 1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller ........................................... 1 1.1 Features .............................................. 1 1.2 Description ............................................ 2 ........................... 5 Device Overview ......................................... 7 2.1 Terms and Acronyms ................................. 7 2.2 Device Characteristics ................................ 8 2.3 Memory ............................................... 9 2.4 Pin Assignments .................................... 18 2.5 Terminal Functions .................................. 23 2.6 Device Support ...................................... 36 Reset / Abort Sources ................................. 38 3.1 Reset / Abort Sources............................... 38 Peripherals............................................... 41 4.1 Error Signaling Module (ESM) ...................... 41 4.2 Direct Memory Access (DMA) ...................... 44 4.3 High End Timer Transfer Unit (HET-TU) ............ 45 4.4 Vectored Interrupt Manager (VIM) .................. 46 4.5 MIBADC Event Trigger Sources .................... 48 4.6 MIBSPI .............................................. 49 4.7 ETM ................................................. 51 4.8 Debug Scan Chains ................................. 52 4.9 CCM ................................................. 53 4.10 LPM ................................................. 54 4.11 Voltage Monitor ..................................... 54 4.12 CRC ................................................. 54 4.13 System Module Access ............................. 54 4.14 Debug ROM ......................................... 55 4.15 CPU Self Test Controller: STC / LBIST ............. 56 Device Registers ....................................... 58 5.1 Device Identification Code Register................. 58 1.3 2 3 4 5 6 6 Functional Block Diagram Table of Contents 7 5.2 Die-ID Registers..................................... 60 5.3 PLL Registers ....................................... 61 Device Electrical Specifications ..................... 62 6.1 6.2 Operating Conditions ................................ 62 Absolute Maximum Ratings Over Operating FreeAir Temperature Range (unless otherwise noted) .. 62 6.3 6.4 Device Recommended Operating Conditions....... 62 Electrical Characteristics Over Operating Free-Air Temperature Range ................................ 63 Peripheral and Electrical Specifications........... 67 7.1 8 9 Clocks ............................................... 67 7.2 ECLK Specification .................................. 71 7.3 RST And PORRST Timings ......................... 72 7.4 TEST Pin Timing .................................... 74 7.5 DAP - JTAG Scan Interface Timing ................. 75 7.6 Output Timings ...................................... 76 7.7 Input Timings ........................................ 77 7.8 Flash Timings ....................................... 78 7.9 SPI Master Mode Timing Parameters ............... 79 7.10 SPI Slave Mode Timing Parameters ................ 83 7.11 CAN Controller Mode Timings 7.12 SCI/LIN Mode Timings .............................. 87 7.13 FlexRay Controller Mode Timings ................... 87 7.14 EMIF Timings........................................ 88 7.15 ETM Timings ........................................ 90 7.16 RTP Timings 7.17 DMM Timings........................................ 94 7.18 MibADC ...................... ........................................ ............................................. 87 92 95 Revision History ...................................... 101 Mechanical Packaging and Orderable Information ............................................. 102 ...................................... 9.1 Thermal Data 9.2 Packaging Information ............................. 102 102 Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 2 Device Overview 2.1 Terms and Acronyms Table 2-1. Terms and Acronyms Terms and Acronyms Description ADC Analog To Digital Converter AHB Advanced High-performance Bus CCM-R4 CPU Compare Module for CortexTM-R4F CRC Cyclic Redundancy Check Controller DAP Debug Access Port DCAN Controller Area Network DMA Direct Memory Access DMM Data Modification Module ECC Error Correction Code EMIF External Memory Interface ESM Error Signaling Module ETM Embedded Trace Module FMzPLL Frequency-Modulated Zero-Pin Phase-Locked Loop Comments Part of the R4 core DAP is an implementation of an ARM Debug Interface. FPLL FlexRay Phase-Locked Loop GIO General-Purpose Input/Output HET High-End Timer ICEPICK In Circuit Emulation TAP (Test Access Port) Selection Module ICEPick can connect or isolate a module level TAP to or from a higher level chip TAP. ICEPick was designed with both emulation and test requirements in mind. JTAG Joint Test Access Group IEEE Committee responsible for Test Access Ports LBIST Logic Built-In Self Test Test the integrity of R4 CPU LIN Local Interconnect Network VIM Vectored Interrupt Manager MibSPI Multi-Buffered Serial Peripheral Interface MPU Memory Protection Unit OSC Oscillator PBIST Programmable Built-In Self Test PCR Peripheral Central Resource POM Parameter Overlay Module PSA Parallel Signature Analysis RTI Real-Time Interrupt RTP RAM Trace Port Test the integrity of SRAM The POM provides a mechanism to redirect accesses to nonvolatile memory into a volatile memory external to the device. SCR Switch Central Resource SCI Serial Communication Interface SECDED Single Error Correction and Double Error Detection STC Self Test Controller SYS System Module TU Transfer Unit VBUS Virtual Bus One of the protocols that comprises CBA (Common Bus Architecture) VBUSP Virtual Bus-Pipelined One of the protocols that comprises CBA (Common Bus Architecture) VMON Voltage Monitor Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 7 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 2.2 www.ti.com Device Characteristics The table below shows the different configurations options offered in the TMS570LS series of devices: Table 2-2. Characteristics of the TMS570LS Series Devices Feature Package TMS570LS20216 337 BGA 144 QFP TMS570LS20206 337 BGA 144 QFP TMS570LS10216 337 BGA 144 QFP TMS570LS10206 337 BGA 144 QFP TMS570LS10116 337 BGA 144 QFP TMS570LS10106 337 BGA 144 QFP Type (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) (ZWT) (PGE) Speed 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz Flash Size 2MB 2MB 2MB 2MB 1MB 1MB 1MB 1MB 1MB 1MB 1MB 1MB RAM Size 160KB 160KB 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB FlexRay 2ch 2ch - - 2ch 2ch - - 2ch 2ch - - CAN 3 2 3 2 3 2 3 2 3 2 3 2 8 MibSPI 3 3 3 3 3 3 3 3 3 3 3 3 UART / LIN 2 2 2 2 2 2 2 2 2 2 2 2 NHET Channels 32 25 32 25 32 25 32 25 32 25 32 25 12-Bit ADC Channels 24 20 24 20 24 20 24 20 24 20 24 20 EMIF 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - GIO 16 8 16 8 16 8 16 8 16 8 16 8 ETM 32-bit - 32-bit - 32-bit - 32-bit - 32-bit - 32-bit - RTP 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - DMM 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - 16-bit - Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 2.3 2.3.1 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Memory Memory Map The memory map, including all available Flash and RAM memory configurations for the device family, are shown below. Figure 2-1 applies to TMS570LS20216 and TMS570LS20206. Figure 2-2 applies to TMS570LS10216 and TMS570LS10206. Figure 2-3 applies to TMS570LS10106 and TMS570LS10116. 0xFFFFFFFF 0xFFF80000 0xFFF7FFFF 0xFF000000 0xFEFFFFFF 0xFE000000 SYSTEM Modules Peripherals CRC RESERVED 0x6FFFFFFF 0x60000000 0x204FFFFF CS3 CS2 CS1 CS0 EMIF (256MB) POM (4MB) RESERVED 0x603FFFFF 0x60000000 0x204FFFFF Flash - ECC 0x20400000 (2MB Mirrored Image) RESERVED 0x201FFFFF Flash (2MB) 0x20400000 0x201FFFFF (Mirrored Image) 0x20000000 0x20000000 RESERVED 0x08427FFF RAM - ECC (160kB) 0x08400000 0x08427FFF 0x08400000 RESERVED 0x08027FFF 0x08027FFF RAM (160kB) 0x08000000 0x08000000 RESERVED 0x004FFFFF Flash - ECC 0x004FFFFF (2MB) 0x00400000 0x00400000 RESERVED 0x001FFFFF 0x001FFFFF Flash (2MB) 0x00000000 0x00000000 Figure 2-1. Memory Map of TMS570LS20216 and TMS570LS20206 Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 9 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 0xFFFFFFFF 0xFFF80000 0xFFF7FFFF 0xFF000000 0xFEFFFFFF 0xFE000000 www.ti.com SYSTEM Modules Peripherals CRC RESERVED 0x6FFFFFFF 0x60000000 CS3 CS2 CS1 CS0 EMIF (256MB) POM (4MB) RESERVED 0x2047FFFF 0x603FFFFF 0x60000000 0x2047FFFF Flash - ECC 0x20400000 0x200FFFFF (1MB Mirrored Image) RESERVED Flash (1MB) 0x20400000 0x200FFFFF (Mirrored Image) 0x20000000 0x20000000 RESERVED 0x08427FFF RAM - ECC (160kB) 0x08400000 0x08427FFF 0x08400000 RESERVED 0x08027FFF 0x08027FFF RAM (160kB) 0x08000000 0x08000000 RESERVED 0x0047FFFF 0x00400000 Flash - ECC 0x0047FFFF (1MB) RESERVED 0x000FFFFF 0x00400000 0x000FFFFF Flash (1MB) 0x00000000 0x00000000 Figure 2-2. Memory Map of TMS570LS10216 and TMS570LS10206 10 Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 0xFFFFFFFF 0xFFF80000 0xFFF7FFFF 0xFF000000 0xFEFFFFFF 0xFE000000 SYSTEM Modules Peripherals CRC RESERVED 0x6FFFFFFF 0x60000000 0x2047FFFF CS3 CS2 CS1 CS0 EMIF (256MB) POM (4MB) RESERVED 0x603FFFFF 0x60000000 0x2047FFFF Flash - ECC 0x20400000 (1MB Mirrored Image) 0x20400000 RESERVED 0x200FFFFF 0x200FFFFF Flash (1MB) (Mirrored Image) 0x20000000 0x20000000 RESERVED 0x0841FFFF RAM - ECC (128kB) 0x08400000 0x0841FFFF 0x08400000 RESERVED 0x0801FFFF 0x0801FFFF RAM (128kB) 0x08000000 0x08000000 RESERVED 0x0047FFFF 0x0047FFFF Flash - ECC (1MB) 0x00400000 0x00400000 RESERVED 0x000FFFFF 0x000FFFFF Flash (1MB) 0x00000000 0x00000000 Figure 2-3. Memory Map of TMS570LS10116 and TMS570LS10106 The Parameter Overlay memory space maps to the lower 4MB of the EMIF CS0 memory space. ECC must be disabled by software via the CPU CP15 register if POM is used to overlay the program memory to the EMIF space; otherwise ECC errors will be generated. The contents of memory connected to the EMIF are not guaranteed after a power on reset. The addressable EMIF memory range is limited to the lower 32MB of each EMIF chip select for 16bit memories, and to the lower 16MB of each EMIF chip select for 8bit memories. The default EMIF data width is 16bit. The EMIF pins do not have GIO functionality. Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 11 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 2.3.2 www.ti.com Flash Memory The F035 (130nm Flash Process) Flash memory is a nonvolatile electrically erasable and programmable memory. The Flash has a state machine for simplifying the program and erase functions. This device’s 2M-Byte flash memory contains four 512K-Byte memory arrays (or banks) consisting of 22 total sectors. 1M-Byte versions of the device contain only the first two 512K-Byte banks (Bank 0 and Bank 1) and have a total of 14 sectors. The bank and sector configurations are shown in Flash Memory Banks and Sectors . When in pipeline mode, the Flash operates with a system clock frequency of up to 160MHz (versus a system clock in non-pipeline mode of up to 36MHz). The flash in pipeline mode is capable of accessing 128 bits at a time and provides two 64-bit pipelined words to the CPU. The minimum size for an erase operation is one sector. A single program operation can program either one 32-bit word or one 16bit half word at a time. Table 2-3. Flash Memory Banks and Sectors Sector NO. Segment Low Address High address 0 32K Bytes 0x0000_0000 0x0000_7FFF 1 32K Bytes 0x0000_8000 0x0000_FFFF 2 32K Bytes 0x0001_0000 0x0001_7FFF 3 8K Bytes 0x0001_8000 0x0001_9FFF 4 8K Bytes 0x0001_A000 0x0001_BFFF 5 16K Bytes 0x0001_C000 0x0001_FFFF 6 64K Bytes 0x0002_0000 0x0002_FFFF 7 64K Bytes 0x0003_0000 0x0003_FFFF 8 128K Bytes 0x0004_0000 0x0005_FFFF 9 128K Bytes 0x0006_0000 0x0007_FFFF 0 128K Bytes 0x0008_0000 0x0009_FFFF 1 128K Bytes 0x000A_0000 0x000B_FFFF 2 128K Bytes 0x000C_0000 0x000D_FFFF 3 128K Bytes 0x000E_0000 0x000F_FFFF 0 128K Bytes 0x0010_0000 0x0011_FFFF 1 128K Bytes 0x0012_0000 0x0013_FFFF 2 128K Bytes 0x0014_0000 0x0015_FFFF 3 128K Bytes 0x0016_0000 0x0017_FFFF 0 128K Bytes 0x0018_0000 0x0019_FFFF 1 128K Bytes 0x001A_0000 0x001B_FFFF 2 128K Bytes 0x001C_0000 0x001D_FFFF 3 128K Bytes 0x001E_0000 0x001F_FFFF MEMORY ARRAYS (OR BANKS) Bank 0: 512K Bytes BANK0 (512K Bytes) Bank 1: 512K Bytes BANK1 (512K Bytes) Bank 2: 512K Bytes BANK2 (512K Bytes) Bank 3: 512K Bytes 12 Device Overview BANK3 (512k Bytes) Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 NOTE • • • • The external flash pump voltage (VccP) is required for all flash operations (program, erase, and read). After a system reset, pipeline mode is disabled (FRDCNTL[2:0] is a "000"). In other words, the device powers up and comes out of reset in non-pipeline mode. The user must program proper ECC bits throughout the entire flash memory to avoid ECC errors due to Cortex R4 speculative fetches if flash ECC is enabled. The flash on this device does not support EEPROM emulation. Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 13 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 2.3.3 www.ti.com System Modules Assignment This table shows the memory map for the Cyclic Redundancy Check (CRC) module, the Cortex™-R4F CoreSight™ debug module, and the System modules. Table 2-4. System Modules Assignment Frame Name 14 Address Range Frame Start Address Frame Ending Address CRC 0xFE00_0000 0xFEFF_FFFF CoreSight Debug ROM Register 0xFFA0_0000 0xFFA0_0FFF Cortex-R4F Debug Register 0xFFA0_1000 0xFFA0_1FFF ETM-R4 Register 0xFFA0_2000 0xFFA0_2FFF CoreSight TPIU Register 0xFFA0_3000 0xFFA0_3FFF POM Register 0xFFA0_4000 0xFFA0_4FFF DMA RAM 0xFFF8_0000 0xFFF8_0FFF VIM RAM 0xFFF8_2000 0xFFF8_2FFF 0xFFF8_3FFF RTP RAM 0xFFF8_3000 Flash Wrapper Register 0xFFF8_7000 0xFFF8_7FFF PCR Register 0xFFFF_E000 0xFFFF_E0FF FlexRay PLL/STC CLK Register 0xFFFF_E100 0xFFFF_E1FF PBIST Register 0xFFFF_E400 0xFFFF_E5FF STC Register 0xFFFF_E600 0xFFFF_E6FF EMIF Register 0xFFFF_E800 0xFFFF_E8FF DMA Register 0xFFFF_F000 0xFFFF_F3FF ESM Register 0xFFFF_F500 0xFFFF_F5FF CCMR4 Register 0xFFFF_F600 0xFFFF_F6FF DMM Register 0xFFFF_F700 0xFFFF_F7FF RAM ECC even Register 0xFFFF_F800 0xFFFF_F8FF RAM ECC odd Register 0xFFFF_F900 0xFFFF_F9FF RTP Register 0xFFFF_FA00 0xFFFF_FAFF RTI Register 0xFFFF_FC00 0xFFFF_FCFF VIM Parity Register 0xFFFF_FD00 0xFFFF_FDFF VIM Register 0xFFFF_FE00 0xFFFF_FEFF System Register 0xFFFF_FF00 0xFFFF_FFFF Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 2.3.4 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Peripheral Selects The peripheral frame contains the memory map for the peripheral registers as well as the peripheral memories. The first table shows the memory map for the peripheral module registers and following table shows the memory map for the peripheral module memories. Table 2-5. Peripheral Select Assignment Peripheral Module Address Range Peripheral Selects Base Address Ending Address MIBSPIP5 0xFFF7_FC00 0xFFF7_FDFF PS[0] MIBSPI3 0xFFF7_F800 0xFFF7_F9FF PS[1] MIBSPI1 0xFFF7_F400 0xFFF7_F5FF PS[2] LIN2 0xFFF7_E500 0xFFF7_E5FF PS[6] 0xFFF7_E4FF LIN1 0xFFF7_E400 DCAN3 0xFFF7_E000 0xFFF7_E1FF PS[7] DCAN2 0xFFF7_DE00 0xFFF7_DFFF PS[8] DCAN1 0xFFF7_DC00 0xFFF7_DDFF FlexRay 0xFFF7_C800 0xFFF7_CFFF PS[12]+PS[13] MIBADC2 0xFFF7_C200 0xFFF7_C3FF PS[15] MIBADC1 0xFFF7_C000 0xFFF7_C1FF GIO 0xFFF7_BC00 0xFFF7_BCFF PS[16] NHET 0xFFF7_B800 0xFFF7_B8FF PS[17] HET TU 0xFFF7_A400 0xFFF7_A4FF PS[22] FlexRay TU 0xFFF7_A000 0xFFF7_A1FF PS[23] Table 2-6. Peripheral Memory Selects Peripheral Module Memory Address Range Base Address Peripheral Selects Ending Address MIBSPIP5 RAM 0xFF0A0000 0xFF0BFFFF PCS[5] MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF PCS[6] MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF PCS[7] DCAN3 RAM 0xFF1A0000 0xFF1BFFFF PCS[13] DCAN2 RAM 0xFF1C0000 0xFF1DFFFF PCS[14] DCAN1 RAM 0xFF1E0000 0xFF1FFFFF PCS[15] MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF PCS[29] MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF PCS[31] NHET RAM 0xFF460000 0xFF47FFFF PCS[35] HET TU RAM 0xFF4E0000 0xFF4FFFFF PCS[39] FlexRay TU RAM 0xFF500000 0xFF51FFFF PCS[40] Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 15 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 2.3.5 www.ti.com Memory Auto-Initialization This device allows some of the on-chip memories to be initialized via the memory hardware initialization control registers in the System module. The purpose of having the hardware initialization is to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC). The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized. Please refer to the Architecture chapter of the Technical Reference Manual (TRM) for more information. The mapping of the different memories to the specific bits in the MSINENA register is shown in the following table. Table 2-7. Memory Initialization Connecting Module Address Range Base Address Ending Address RAM 0x08000000 0x0801FFFF 0 MIBSPIP5 RAM 0xFF0A0000 0xF0BFFFFF 12 MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11 MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7 DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1 RAM 0xFF1E0000 FlexRay RAM (1) RAM Select 0xFF1FFFFF 5 9 (1) RAM is not visible MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14 MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8 NHET RAM 0xFF460000 0xFF47FFFF 3 HET TU RAM 0xFF4E0000 0xFF4FFFFF 4 DMA RAM 0xFFF80000 0xFFF80FFF 1 VIM RAM 0xFFF82000 0xFFF82FFF 2 FlexRay TU RAM 0xFF500000 0xFF51FFFF 13 reserved only; the FlexRay RAM has its own Initialization mechanism. The associated ECC RAM will get initialized as well, if the ECC functionality is enabled. The associated Parity RAM will get initialized as well, if the Parity functionality is enabled. NOTE The user must initialize entire SRAM with ECC bits to avoid ECC errors due to Cortex R4 speculative fetches if SRAM ECC is enabled. 16 Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 2.3.6 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 PBIST RAM Self Test The PBIST (Programmable Built-In Self Test) architecture provides a run-time-programmable memory BIST engine for varying levels of test coverage across the device’s embedded RAM memory. The PBIST architecture consists of a small CPU with an instruction set targeted specifically towards testing RAM memories. This CPU includes both control and instruction registers necessary to execute the individual memory algorithms. In order to minimize test load overhead, once an algorithm is loaded into the instruction registers, it can be run on multiple memories of different sizes or types. The memory configuration information and test algorithm code is stored in an on-chip ROM. The PBIST RAM groups implemented on this device are shown in the following table. More information about memory self test can be found in the PBIST chapter of the device TRM. Table 2-8. PBIST RAM Grouping RAM Module Group Memory Type RGS /RDS (1) Test Pattern (Algorithm) Triple slow read [ROM clock cycles] Triple fast read [ROM clock cycles] March 13N [HCLK/ VCLK (2) cycles] Down 1A [HCLK/ VCLK (2) cycles] Precharge [HCLK/ VCLK (2) cycles] Map column [HCLK/ VCLK (2) cycles] DTXN 2A [HCLK/ VCLK (2) cycles] PMOS open [HCLK/ VCLK (2) cycles] 1 PBIST ROM ROM 0/1 12290 4098 2 STC ROM ROM 13/1 24578 8194 3 DCAN1 SP 1/0..2 12600 2637 2064 1914 5490 11544 4 DCAN2 SP 2/0..2 12600 2637 2064 1914 5490 11544 5 DCAN3 SP 3/0..2 6360 1341 1104 1146 2754 5016 6 ESRAM SP, multi-strobe w/page mode 4/21..22 266320 52254 41120 33212 181260 409616 7 MibSPI SP 5/0..5 50160 10458 7968 6900 21924 52272 8 VIM SP 6/0 4200 879 688 638 1830 3848 9 MibADC 2P, sync write async read 7/0..1 8400 1758 1376 1276 3660 7696 10 DMA 2P, sync write async read 8/0..5 18960 4410 3072 2772 6084 Not Available 11 NHET 2P, sync write async read 9/0..11 25440 5940 4224 4008 8136 20064 12 HET TU 2P, sync write async read 10/0..5 6480 1530 1152 1236 2052 4272 13 RTP 2P, sync write async read 11/0..8 37800 8775 6048 5310 12150 34632 14 FlexRay SP 12/0..7 175040 34872 27296 22608 108912 246336 15 ESRAM SP, multi-strobe w/ page mode 4/20 133160 26127 20560 16606 90630 204808 SP = Single Port RAM; 2P = Two Port RAM (1) (2) RGS (RAM group select) and RDS (return data select) stand for an unique RAM select id. More information about the RGS and the RDS can be found in the technical reference manual (TRM) The test clock for ESRAM, DMA and RTP is HCLK; the test clock for other modules is VCLK. NOTE • • • The March13N test algorithm is recommended for application testing. The maximum PBIST test execution speed is limited to 100MHz. The supply current while performing PBIST self test is different than the device operating mode current. These values can be found in the Icc section of the device electrical specifications. Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 17 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 2.4 www.ti.com Pin Assignments 2.4.1 PGE QFP Package Pinout (144 pin) 75 74 73 78 77 76 85 84 83 82 81 80 79 95 94 93 92 91 90 89 88 87 86 97 96 99 98 100 102 101 72 109 110 71 70 69 68 67 66 65 64 63 62 61 60 59 58 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 57 56 55 54 53 52 51 50 131 49 48 47 46 45 44 43 42 41 40 39 38 37 132 133 134 135 136 137 138 139 140 141 142 36 34 35 32 33 30 31 24 25 26 27 28 29 21 22 23 18 19 20 ADSIN[11] ADSIN[12] ADSIN[13] ADSIN[14] ADSIN[15] VCCAD ADREFHI ADREFLO VSSAD AD2IN[3] AD2IN[2] AD2IN[1] AD2IN[0] AD2EVT TEST NHET[9] NHET[2] CAN2RX CAN2TX LIN1RX LIN1TX GIOA[7]/INT[7] CAN1TX CAN1RX NHET[6] VCC VSS NHET[20] NHET[5] NHET[24] NHET[1] NHET[3] VCCIO VSSIO VSS VCC VCCIO VSSIO MIBSPI3CLK MIBSPI3SIMO MIBSPI3SOMI nMIBSPI3ENA NMIBSPI3CS[0] NHET[12] NHET[22] NHET[18] NHET[21] NHET[23] MIBSPI1SOMI MIBSPI1SIMO VCCIO VSSIO MIBSPI1CLK nMIBSPI1ENA VCC OSCIN OSCOUT VSS nMIBSPI1CS[0] nMIBSPI1CS[1] nMIBSPI1CS[2] NHET[13] GIOA[6]/INT[6] nPORRST nTRST TCK VCC VSS TDO TDI RTCK TMS 1 143 144 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 NHET[7] GIOA[4]/INT[4] GIOA[5]/INT[5] NHET[8] NHET[15] VCC VSS NHET[10] NHET[11] GIOA[0]/INT[0] VCCIO VSSIO NHET[4] FLTP1 FLTP2 FRAYTX1 FRAYTXEN1 FRAYRX1 VSS VCCP FRAYTX2 FRAYTXEN2 FRAYRX2 VCCIO VSSIO GIOA[1]/INT[1] VCC VSS NHET[30] NHET[14] LIN2TX LIN2RX GIOA[2]/INT[2] NHET[16] nERROR GIOA[3]/INT[3] 106 105 104 103 108 107 VCCIO VSSIO NHET[28] NHET[0] VCC VSS DMMDATA[15]/MIBSPI5SOMI[3] DMMDATA[14]/MIBSPI5SOMI[2] DMMDATA[13]/MIBSPI5SOMI[1] DMMDATA[12]/MIBSPI5SOMI[0] DMMDATA[11]/MIBSPI5SIMO[3] DMMDATA[10]/MIBSPI5SIMO[2] DMMDATA[9]/MIBSPI5SIMO[1] DMMDATA[8]/MIBSPI5SIMO[0] DMMDATA[7]/nMIBSPI5ENA DMMDATA[6]/nMIBSPI5CS[1] DMMDATA[5]/nMIBSPI5CS[0] DMMDATA[4]/MIBSPI5CLK VCCIO VSSIO ECLK VCC VSS nRST AD1EVT AD1IN[0] AD1IN[1] AD1IN[2] AD1IN[3] AD1IN[4] AD1IN[5] AD1IN[6] AD1IN[7] ADSIN[8] ADSIN[9] ADSIN[10] (TOP VIEW) Figure 2-4. PGE Pinout (144 pin) [Top View] 18 Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 2.4.2 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 ZWT BGA Package Pinout (337 ball) A B C D E F G H J K L 19 VSS VSS TMS NHET [10] MIBSPI5 CS[0] MIBSPI1 SIMO MIBSPI1 ENA MIBSPI5 CLK MIBSPI5 SIMO[0] NHET [28] DMM DATA[0] 19 18 VSS TCK TDO TRST NHET [08] MIBSPI1 CLK MIBSPI1 SOMI MIBSPI5 ENA MIBSPI5 SOMI[0] NHET [0] DMM DATA[1] 18 17 TDI RST EMIF_ ADDR[21] EMIF _WE MIBSPI5 SOM[1] DMM CLK MIBSPI5 SIMO[3] MIBSPI5 SIMO[2] NHET [31] EMIF_ CS[1] EMIF_ CS[0] 17 16 RTCK FRAY TXEN1 EMIF_ ADDR[20] EMIF_ BA[1] MIBSPI5 SIMO[1] DMM ENA MIBSPI5 SOMI[3] MIBSPI5 SOMI[2] DMM SYNC EMIF_ DATA[0] EMIF_ DATA[1] 16 15 FRAY RX1 FRAY TX1 EMIF_ ADDR[19] EMIF_ ADDR[18] ETM DATA[06] ETM DATA[05] ETM DATA[04] ETM DATA[03] ETM DATA[02] ETM DATA[16] ETM DATA[17] 15 14 NHET [26] ERROR EMIF_ ADDR[17] EMIF_ ADDR[16] ETM DATA[07] VCCIO VCCIO VCCIO VCC VCC VCCIO 14 13 NHET [17] NHET [19] EMIF_ ADDR[15] EMIF_ BA[0] ETM DATA[12] VCCIO 12 ECLK NHET [04] EMIF_ ADDR[14] EMIF_ OE ETM DATA[13] 11 NHET [14] NHET [30] EMIF_ ADDR[13] EMIF_ DQM[1] ETM DATA[14] 10 CAN1 TX CAN1 RX EMIF_ ADDR[12] EMIF_ DQM[0] ETM DATA[15] A B C D E 13 VSS VSS VCC VSS 12 VCCIO VSS VSS VSS VSS 11 VCC VCC VSS VSS VSS 10 J K L VCCIO F G H Figure 2-5. ZWT Package Pinout Top Left Quadrant (337 ball) [Top View] Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 19 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com K L M N P R T 19 NHET [28] DMM DATA[0] CAN3 RX AD1 EVT ADS IN[15] AD2 IN[6] AD1 IN[6] ADS IN[11] VSSAD VSSAD 19 18 NHET [0] DMM DATA[1] CAN3 TX NC ADS IN[8] ADS IN[14] ADS IN[13] AD1 IN[4] AD1 IN[2] VSSAD 18 17 EMIF_ CS[1] EMIF_ CS[0] EMIF_ CS[2] EMIF_ CS[3] NC AD1 IN[5] AD1 IN[3] ADS IN[10] AD1 IN[1] ADS IN[9] 17 16 EMIF_ DATA[0] EMIF_ DATA[1] EMIF_ DATA[2] EMIF_ DATA[3] NC AD2 IN[7] ADS IN[12] AD2 IN[3] ADREF LO VSSAD 16 15 ETM DATA[16] ETM DATA [17] ETM DATA[18] ETM DATA[19] NC NC AD2 IN[5] AD2 IN[4] ADREF HI VCCAD 15 14 VCC VCCIO VCCIO VCCIO VCCIO NC NC AD2 IN[2] AD1 IN[7] AD1 IN[0] 14 VCCIO ETM DATA[1] NC AD2 IN[1] AD2 IN[0] AD2 EVT 13 13 U V W 12 VCC VSS VSS VCCIO ETM DATA[0] MIBSPI5 CS[3] RTP ENA LIN1 TX LIN1 RX 12 11 VSS VSS VSS VCC ETM TRACE CTL RTP SYNC RTP DATA[1] RTP DATA[0] RTP CLK 11 10 VSS VSS VCC VCC ETM TRACE CLKOUT RTP DATA[2] RTP DATA[3] MIBSPI3 CS[0] GIOB[3] 10 K L M P R T U V W N Figure 2-6. ZWT Package Pinout Top Right Quadrant (337 ball) [Top View] 20 Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 A B C D E F 10 CAN1TX CAN1RX EMIF_ ADDR[12] EMIF_ DQM[0] ETM_ DATA[15] 9 NHET [27] FRAY TXEN2 EMIF_ ADDR[11] EMIF_ ADDR[5] 8 FRAY RX2 FRAY TX2 EMIF_ ADDR[10] 7 LIN2 RX LIN2 TX 6 GIOA [4] 5 G H J K L VCC VCC VSS VSS VSS 10 ETM DATA[8] VCC VSS VSS VSS VSS 9 EMIF_ ADDR[4] ETM DATA[9] VCCP VSS VSS VCC VSS 8 EMIF_ ADDR[9] EMIF_ ADDR[3] ETM DATA[10] VCCIO MIBSPI5 CS[1] EMIF_ ADDR[8] EMIF_ ADDR[2] ETM DATA[11] VCCIO VCCIO GIOA [0] GIOA [5] EMIF_ ADDR[7] EMIF_ ADDR[1] ETM DATA[20] ETM DATA[21] DATA[22] NHET NHET EMIF_ EMIF_ EMIF_ EMIF_ [16] [12] ADDR[6] ADDR[0] DATA[4] DATA[5] 3 NHET [29] NHET [22] MIBSPI3 CS[3] NC NHET [11] MIBSPI1 CS[1] 2 VSS MIBSPI3 CS[2] GIOA [1] NC NC 1 VSS VSS GIOA [2] NC A B C D 4 7 VCCIO VCCIO FLTP2 FLTP1 EMIF_ NHET DATA[6] [21] NHET [23] MIBSPI1 CS[2] GIOA [6] GIOB [2] GIOB [5] CAN2 TX GIOA [3] GIOB [7] GIOB [4] CAN2 RX E F G H ETM VCC VCC 6 ETM ETM DATA[24] 5 DATA[23] EMIF_ EMIF_ DATA[7] DATA[8] MIBSPI1 CS[3] NC NC 3 GIOB [6] GIOB [1] KELVIN GND 2 NHET [18] OSCIN OSCOUT 1 J K 4 L Figure 2-7. ZWT Package Pinout Bottom Left Quadrant (337 ball) [Top View] Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 21 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com P R T U V W VCC VCC ETM TRACE CLKOUT RTP DATA[2] RTP DATA[3] MIBSPI3 CS[0] GIOB[3] 10 VSS VCCIO ETM TRACE CLKIN RTP DATA[4] RTP DATA[5] MIBSPI3 CLK MIBSPI3 ENA 9 VCCIO ETM DATA[31] EMIF_ DATA[15] RTP DATA[6] MIBSPI3 SOMI MIBSPI3 SIMO 8 VCCIO ETM DATA[30] EMIF_ DATA[14] RTP DATA[7] NHET [9] PORRST 7 MIBSPI5 CS[2] 6 K L M 10 VSS VSS 9 VSS VSS 8 VCC VSS N VSS 7 6 VCC VCC VCCIO VCCIO VCCIO ETM DATA[29] EMIF_ DATA[13] RTP DATA[8] NHET [5] 5 ETM DATA[23] ETM DATA[24] ETM DATA[25] ETM DATA[26] ETM DATA[27] ETM DATA[28] EMIF_ DATA[12] RTP DATA[9] MIBSPI3 CS[1] NHET [2] 5 4 EMIF_ DATA[7] EMIF_ DATA[8] EMIF_ DATA[9] EMIF_ DATA[10] EMIF_ DATA[11] NC RTP DATA[11] RTP DATA[10] VSS NC 4 3 NC NC NHET [25] NC NC RTP DATA[14] RTP RTP DATA[13] DATA[12] NHET [6] 3 2 GIOB [1] KELVIN GND GIOB [0] NHET [13] NHET [20] MIBSPI1 CS[0] RTP DATA[15] TEST NHET [1] VSS 2 1 OSCIN OSCOUT GIOA [7] NHET [15] NHET [24] NC NHET [7] NHET [3] VSS VSS 1 M N P R T U V W K L NC Figure 2-8. ZWT Package Pinout Bottom Right Quadrant (337 ball) [Top View] 22 Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 2.5 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Terminal Functions This following table describes the pins on the device. NOTE Table Abbreviations: PWR = power, GND = ground, REF = reference voltage, NC = no connect, IPD = Internal Pull Down, IPU = Internal Pull Up, I/O = Input/Output, I = Input, O = Output Table 2-9. Terminal Functions Terminal Name TMS570LSXXX16 337 144 TMS570LSXXX06 337 Type 144 Internal pullup/p ulldown Description HIGH-END TIMER (NHET) NHET[0] K18 105 K18 105 NHET[1] V2 42 V2 42 NHET[2] W5 56 W5 56 NHET[3] U1 41 U1 41 NHET[4] B12 121 B12 121 NHET[5] V6 44 V6 44 NHET[6] W3 48 W3 48 NHET[7] T1 109 T1 109 NHET[8] E18 112 E18 112 NHET[9] V7 57 V7 57 NHET[10] D19 116 D19 116 NHET[11] E3 117 E3 117 NHET[12] B4 8 B4 8 NHET[13] N2 26 N2 26 NHET[14] A11 138 A11 138 NHET[15] N1 113 N1 113 NHET[16] A4 142 A4 142 NHET[17] A13 NHET[18] J1 NHET[19] B13 A13 10 J1 10 3.3V I/O 2mA - z program mable IPD (20uA) Timer input capture or output compare. The applicable NHET pins can be programmed as general-purpose input/output (GIO) pins. NHET pins are high-resolution. The high-resolution (HR) SHARE feature allows even HR pins to share the next higher odd HR pin structures. The next higher odd HR pin structure is always implemented, even if the next higher odd HR pad and/or pin itself is not. The HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. NHET[0] provides SPI clock when used for SPI emulation. Each NHET pin is equipped with an input suppression filter that can be used to eliminate the sampling of pulses that are smaller than a programmable duration GIOA[0]/INT[0] is also connected to the NHET Pin Disable input of the NHET module. NHET pins can be programmed as a GIO pins when not used as NHET functional pins. B13 NHET[20] P2 45 P2 45 NHET[21] H4 11 H4 11 NHET[22] B3 9 B3 9 NHET[23] J4 12 J4 12 NHET[24] P1 43 P1 43 NHET[25] M3 M3 NHET[26] A14 A14 NHET[27] A9 NHET[28] K19 NHET[29] A3 NHET[30] B11 NHET[31] J17 A9 106 K19 106 A3 137 B11 137 J17 Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 23 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 2-9. Terminal Functions (continued) Terminal TMS570LSXXX16 Name 337 144 TMS570LSXXX06 337 Internal pullup/p ulldown Type 144 Description GENERAL-PURPOSE I/O (GIO) GIOA[0]/INT0 A5 118 A5 118 GIOA[1]/INT1 C2 134 C2 134 GIOA[2]/INT2 C1 141 C1 141 GIOA[3]/INT3 E1 144 E1 144 GIOA[4]/INT4 A6 110 A6 110 GIOA[5]/INT5 B5 111 B5 111 GIOA[6]/INT6 H3 27 H3 27 GIOA[7]/INT7 M1 51 M1 51 GIOB[0] M2 M2 GIOB[1] K2 K2 GIOB[2] F2 F2 GIOB[3] W10 W10 GIOB[4] G1 G1 GIOB[5] G2 G2 GIOB[6] J2 J2 GIOB[7] F1 F1 General-purpose input/output pin. GIOA[0]/INT[0] is an interrupt-capable pin. GIOA[0]/INT[0] is also connected to the NHET Pin Disable input of the NHET module. 3.3V I/O 2mA - z Program mable IPD (20uA) General-purpose input/output pins.GIOA[7:1]/INT[7:1] are interruptcapable pins. General-purpose input/output pins. FlexRay Controller (FLEXRAY) NOTE: Devices with out the FlexRay option should leave all FlexRay pins unconnected (NC) FRAYRX1 A15 126 FRAYTX1 B15 124 FRAYTXEN1 B16 125 FRAYRX2 A8 131 FRAYTX2 B8 129 FRAYTXEN2 B9 130 Program mable FlexRay data receive (channel 1) pin IPD (20uA) 3.3V I 3.3V O 8mA FlexRay transmit enable (channel 1) pin Program mable FlexRay data receive (channel 2) pin IPD(20u A) 3.3V I 3.3V O FlexRay data transmit (channel 1) pin 8mA 8mA FlexRay data transmit (channel 2) pin 8mA FlexRay transmit enable (channel 2) pin CAN Controller (DCAN1) CAN1TX A10 50 A10 50 CAN1RX B10 49 B10 49 3.3V I/O 2mA - z Program CAN1 transmit pin or GIO pin mable IPU CAN1 receive pin or GIO pin (20uA) CAN Controller (DCAN2) CAN2TX H2 CAN2RX H1 CAN3TX M18 54 55 H2 H1 54 55 3.3V I/O 2mA - z Program CAN2 transmit pin or GIO pin mable IPU CAN2 receive pin or GIO pin (20uA) CAN Controller (DCAN3) CAN3RX 24 M19 Device Overview M18 M19 3.3V I/O 2mA - z program mable IPU (20uA) CAN3 transmit pin or GIO pin CAN3 receive pin or GIO pin Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 2-9. Terminal Functions (continued) Terminal TMS570LSXXX16 Name 337 144 TMS570LSXXX06 337 Internal pullup/p ulldown Type 144 Description Serial Communications Interface (SCI)/Local Interconnect Network (LIN1) LIN1RX W12 53 W12 53 LIN1TX V12 52 V12 52 3.3V I/O 2mA - z Program LIN1 data receive pin or GIO pin mable IPU LIN1 data transmit pin or GIO pin (20uA) Serial Communications Interface (SCI)/Local Interconnect Network (LIN2) LIN2RX A7 140 A7 B7 140 LIN2TX B7 139 139 MIBSPI1CLK F18 17 F18 17 MIBSPI1CS[0] R2 23 R2 23 MIBSPI1CS[1] F3 24 F3 24 MIBSPI1CS[2] G3 25 G3 25 MIBSPI1CS[3] J3 MIBSPI1ENA G19 18 G19 18 MIBSPI1SIMO F19 14 F19 14 MIBSPI1SOMI G18 13 G18 13 MIBSPI3CLK V9 3 V9 3 MIBSPI3CS[0] V10 7 V10 7 MIBSPI3CS[1] V5 V5 MIBSPI3CS[2] B2 B2 MIBSPI3CS[3] C3 C3 MIBSPI3ENA W9 6 W9 6 MIBSPI3SIMO W8 4 W8 4 MIBSPI3SOMI V8 5 V8 5 3.3V I/O 2mA - z Program LIN2 data receive pin or GIO pin mable IPU LIN2 data transmit pin or GIO pin (20uA) Multibuffered Serial Peripheral Interface (MIBSPI1) J3 4mA 2mA - z 3.3V I/O 2mA - z 4mA MIBSPI1 clock pin or GIO pin MIBSPI1 slave chip select pins or GIO pins Program mable IPU (20uA) MIBSPI1 enable pin or GIO pin MIBSPI1 data stream - Slave in/master out pin or GIO pin MIBSPI1 data stream - Slave out/master in pin or GIO pin Multibuffered Serial Peripheral Interface (MIBSPI3) 4mA 2mA - z 3.3V I/O 2mA - z 4mA MIBSPI3 clock pin or GIO pin MIBSPI3 slave chip select pins or GIO pins Program mable IPU (20uA) MIBSPI3 enable pin or GIO pin MIBSPI3 data stream - Slave in/master out pin or GIO pin MIBSPI3 data stream - Slave out/master in pin or GIO pin Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 25 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 2-9. Terminal Functions (continued) Terminal TMS570LSXXX16 Name 337 144 TMS570LSXXX06 337 Internal pullup/p ulldown Type 144 Description Multibuffered Serial Peripheral Interface - Parallel (MIBSPIP5) MIBSPI5CLK/DM MDATA[4] H19 91 H19 91 MIBSPI5CS[0]/DM MDATA[5] E19 92 E19 92 MIBSPI5CS[1]/DM MDATA[6] B6 93 B6 93 MIBSPI5CS[2]/DM MDATA[2] W6 W6 MIBSPI5CS[3]/DM MDATA[3] T12 T12 MIBSPI5ENA/DM MDATA[7] H18 94 H18 94 MIBSPI5SIMO[0]/ DMMDATA[8] J19 95 J19 95 DMMDATA[9]/MIB SPI5SIMO[1] E16 96 E16 96 MIBSPI5SIMO[2]/ DMMDATA[10] H17 97 H17 97 MIBSPI5SIMO[3]/ DMMDATA[11] G17 98 G17 98 MIBSPI5SOMI[0]/ DMMDATA[12] J18 99 J18 99 MIBSPI5SOMI[1]/ DMMDATA[13] E17 100 E17 100 MIBSPI5SOMI[2]/ DMMDATA[14] H16 101 H16 101 MIBSPI5SOMI[3]/ DMMDATA[15]/ G16 102 G16 102 4mA 2mA - z MIBSPI5 clock pin or GIO pin; multiplexed with DMMDATA[4] pin MIBSPI5 slave chip select pins or GIO pins; multiplexed with DMMDATA pins MIBSPI5 enable pin or GIO pin; multiplexed with DMMDATA[7] pin Program mable IPU (20uA) MIBSPI5 data stream - Slave in/master out pins or GIO pins; multiplexed with DMMDATA pins 3.3V I/O 4mA MIBSPI5 data stream - Slave out/master in pins or GIO pins; multiplexed with DMMDATA pins Multibuffered Analog-To-Digital Converter (MIBADC1) AD1EVT N19 84 N19 84 AD1IN[0] W14 83 W14 83 AD1IN[1] V17 82 V17 82 AD1IN[2] V18 81 V18 81 AD1IN[3] T17 80 T17 80 AD1IN[4] U18 79 U18 79 AD1IN[5] R17 78 R17 78 AD1IN[6] T19 77 T19 77 AD1IN[7] V14 76 V14 76 26 Device Overview 3.3V I/O 3.3V I 2 mA - z Program mable MibADC1 event input pin or GIO pin IPD (20uA) MibADC1 analog input pins Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 2-9. Terminal Functions (continued) Terminal Name TMS570LSXXX16 337 144 TMS570LSXXX06 337 Type 144 Internal pullup/p ulldown Description Multibuffered Analog-To-Digital Converter (MIBADC2) AD2EVT W13 59 W13 59 AD2IN[0] V13 60 V13 60 AD2IN[1] U13 61 U13 61 AD2IN[2] U14 62 U14 62 AD2IN[3] U16 63 U16 63 AD2IN[4] U15 U15 AD2IN[5] T15 T15 AD2IN[6] R19 R19 AD2IN[7] R16 R16 ADSIN[8] P18 75 P18 75 ADSIN[9] W17 74 W17 74 ADSIN[10] U17 73 U17 73 ADSIN[11] U19 72 U19 72 ADSIN[12] T16 71 T16 71 ADSIN[13] T18 70 T18 70 ADSIN[14] R18 69 R18 69 ADSIN[15] P19 68 P19 68 ADREFHI V15 66 V15 ADREFLO V16 65 VCCAD W15 67 VSSAD V19 64 VSSAD W16 W16 VSSAD W18 W18 VSSAD W19 W19 3.3V I/O 2 mA - z 3.3 V I Program mable MibADC2 event input pin or GIO pin IPD (20uA) MibADC2 analog input pins Multibuffered Analog-To-Digital Converter - shared signals (MIBADC1, MIBADC2) 3.3 V I MibADC1, MibADC2 shared analog input pins 66 3.3-V REF MibADC1, MibADC2 module highvoltage reference input V16 65 GND REF MibADC1, MibADC2 module low-voltage reference input W15 67 3.3-V PWR MibADC1, MibADC2 analog supply voltage V19 64 GND MibADC1, MibADC2 analog ground reference Oscillator (OSC) OSCIN K1 20 K1 20 1.5V I Oscillator input connection pin or external clock input pin OSCOUT L1 21 L1 21 1.5V O Oscillator ouptut connection pin Kelvin_GND L2 L2 GND Kelvin_GND for oscillator Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 27 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 2-9. Terminal Functions (continued) Terminal Name TMS570LSXXX16 337 144 TMS570LSXXX06 337 Internal pullup/p ulldown Type 144 Description System Module (SYS) PORRST RST W7 B17 28 85 W7 B17 28 IPD (100µA) Power on Reset Pin. External power supply monitor circuitry must assert a power-on reset on this pin. 4mA IPU (100µA) Active Low Bidirectional Reset pin. An external device can assert a device reset on this pin. The output buffer on this pin is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this pin. 8mA IPD (20µA) External Clock Prescaler module output pin or GIO pin IPD (100uA) JTAG test clock pin. Clocks the JTAG debug logic. 3.3V I 85 3.3V I/O ECLK A12 88 A12 88 Tset/Debug (T/D) TCK B18 30 B18 30 3.3V I RTCK A16 35 A16 35 3.3V O JTAG return test clock pin. (JTAG) IPU (100uA) JTAG test data in pin. IPD (100uA) JTAG test data out pin. TDI A17 34 A17 34 TDO C18 33 C18 33 TMS C19 36 C19 36 IPU (100uA) JTAG serial input pin for controlling the state of the CPU test access port (TAP) controller. TRST D18 29 D18 29 IPD (100uA) JTAG test hardware reset to TAP. IEEE Standard 1149-1 (JTAG) Boundary-Scan Logic TEST U2 58 U2 58 IPD (100uA) Test enable pin. Reserved for internal TI use only. For proper operation, this pin must be connected to ground, e.g. using a external resistor. IPD (20uA) Error Signaling pin 3.3V I/O 8 mA 3.3V I Error Signaling Module (ESM) ERROR B14 143 B14 143 3.3V I/O 8mA Flash FLTP1 J5 122 J5 122 Flash Test Pad 1 pin. For proper operation this pin must connect only to a test pad or not be connected at all [no connect (NC)]. The test pad must not be exposed in the final product where it might be subjected to an ESD event. Flash Test Pad 2 pin. For proper operation this pin must connect only to a test pad or not be connected at all [no connect (NC)]. The test pad must not be exposed in the final product where it might be subjected to an ESD event. FLTP2 H5 123 H5 123 VCCP F8 128 F8 128 28 Device Overview 3.3V PWR Flash pump voltage supply (3.3 V). This pin is required for Flash read, program and erase operations. Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 2-9. Terminal Functions (continued) Terminal TMS570LSXXX16 Name 337 144 TMS570LSXXX06 337 Internal pullup/p ulldown Type 144 Description RAM Trace Port Module (RTP) RTPDATA[0] V11 V11 RTPDATA[1] U11 U11 RTPDATA[2] T10 T10 RTPDATA[3] U10 U10 RTPDATA[4] T9 T9 RTPDATA[5] U9 U9 RTPDATA[6] U8 U8 RTPDATA[7] U7 U7 RTPDATA[8] U6 U6 RTPDATA[9] U5 U5 RTPDATA[10] U4 U4 RTPDATA[11] T4 T4 RTPDATA[12] V3 V3 RTPDATA[13] U3 U3 RTPDATA[14] T3 T3 RTPDATA[15] T2 T2 RTPENA U12 U12 RTPSYNC T11 T11 RTPCLK W11 W11 8mA Program mable IPU (20uA) 3.3V I/O 2mA - z 8mA RAM Trace Port Output Data Signal pins or GIO pins Packet Handshake Signal pin or GIO pin Packet Synchronization Signal pin or GIO pin Packet Clock Signal pin or GIO pin Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 29 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 2-9. Terminal Functions (continued) Terminal TMS570LSXXX16 Name 337 144 TMS570LSXXX06 337 Internal pullup/p ulldown Type 144 Description Data Modification Module (DMM) DMMDATA[0] L19 L19 DMMDATA[1] L18 L18 DMMDATA[2]/MIB SPI5CS[2] W6 W6 DMMDATA[3]/MIB SPI5CS[3] T12 T12 DMMDATA[4]/MIB SPI5CLK H19 H19 DMMDATA[5]/MIB SPI5CS[0] E19 E19 DMMDATA[6]/MIB SPI5CS[1] B6 B6 DMMDATA[7]/MIB SPI5ENA H18 H18 DMMDATA[8]/MIB SPI5SIMO[0] J19 J19 DMMDATA[9]/MIB SPI5SIMO[1] E16 E16 DMMDATA[10]/MI BSPI5SIMO[2] H17 H17 DMMDATA[11]/MI BSPI5SIMO[3] G17 G17 DMMDATA[12]/MI BSPI5SOMI[0] J18 J18 DMMDATA[13]/MI BSPI5SOMI[1] E17 E17 DMMDATA[14]/MI BSPI5SOMI[2] H16 H16 DMMDATA[15]/MI BSPI5SOMI[3] G16 G16 DMMENA F16 F16 DMMSYNC J16 J16 DMMCLK F17 F17 30 DMM Data pins or GIO pins 2mA - z 4mA 2mA - z Program DMM Data pins or GIO pins; multiplexed mable with MIBSPI5 pins IPU (20uA) 3.3V I/O 4mA Device Overview 8mA 2mA - z DMM Handshake pin or GIO pin DMM Synchronization pin or GIO pin DMM Clock input pin or GIO pin Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 2-9. Terminal Functions (continued) Terminal TMS570LSXXX16 Name 337 144 TMS570LSXXX06 337 Internal pullup/p ulldown Type 144 Description External Memory Interface Module (EMIF) EMIFBADD[0] D13 D13 EMIFBADD[1] D16 D16 EMIFDATA[0] K16 K16 EMIFDATA[1] L16 L16 EMIFDATA[2] M16 M16 EMIFDATA[3] N16 N16 EMIFDATA[4] E4 E4 EMIFDATA[5] F4 F4 EMIFDATA[6] G4 G4 EMIFDATA[7] K4 K4 EMIFDATA[8] L4 L4 EMIFDATA[9] M4 M4 EMIFDATA[10] N4 N4 EMIFDATA[11] P4 P4 EMIFDATA[12] T5 T5 EMIFDATA[13] T6 T6 EMIFDATA[14] T7 T7 EMIFDATA[15] T8 T8 EMIFADD[0] D4 D4 EMIFADD[1] D5 D5 EMIFADD[2] D6 D6 EMIFADD[3] D7 D7 EMIFADD[4] D8 D8 EMIFADD[5] D9 D9 EMIFADD[6] C4 C4 EMIFADD[7] C5 C5 EMIFADD[8] C6 C6 EMIFADD[9] C7 C7 EMIFADD[10] C8 C8 EMIFADD[11] C9 C9 EMIFADD[12] C10 C10 EMIFADD[13] C11 C11 EMIFADD[14] C12 C12 EMIFADD[15] C13 C13 EMIFADD[16] D14 D14 EMIFADD[17] C14 C14 EMIFADD[18] D15 D15 EMIFADD[19] C15 C15 EMIFADD[20] C16 C16 EMIFADD[21] C17 C17 EMIFCS[0] L17 L17 EMIFCS[1] K17 K17 EMIFCS[2] M17 M17 EMIFCS[3] N17 N17 3.3V I/O 8mA EMIF Byte Address pins Program mable EMIF Data pins IPU (20uA) 3.3V I/O 8mA 3.3V I/O 8mA EMIF Address pins 3.3V I/O 8mA EMIF Chip Select pins Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 31 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 2-9. Terminal Functions (continued) Terminal TMS570LSXXX16 Name 337 144 TMS570LSXXX06 337 Internal pullup/p ulldown Type 144 Description EMIFWE D17 D17 3.3V I/O 8mA EMIF Write Enable pin EMIFOE D12 D12 3.3V I/O 8mA EMIF Output Enable pin EMIFDQM[0] D10 D10 EMIFDQM[1] D11 D11 3.3V I/O 8mA EMIF Byte Enable pins 32 Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 2-9. Terminal Functions (continued) Terminal TMS570LSXXX16 Name 337 144 TMS570LSXXX06 337 Internal pullup/p ulldown Type 144 Description Embedded Trace Module (ETM) ETMDATA[0] R12 R12 ETMDATA[1] R13 R13 ETMDATA[2] J15 J15 ETMDATA[3] H15 H15 ETMDATA[4] G15 G15 ETMDATA[5] F15 F15 ETMDATA[6] E15 E15 ETMDATA[7] E14 E14 ETMDATA[8] E9 E9 ETMDATA[9] E8 E8 ETMDATA[10] E7 E7 ETMDATA[11] E6 E6 ETMDATA[12] E13 E13 ETMDATA[13] E12 E12 ETMDATA[14] E11 E11 ETMDATA[15] E10 E10 ETMDATA[16] K15 K15 ETMDATA[17] L15 L15 ETMDATA[18] M15 M15 ETMDATA[19] N15 N15 ETMDATA[20] E5 E5 ETMDATA[21] F5 F5 ETMDATA[22] G5 G5 ETMDATA[23] K5 K5 ETMDATA[24] L5 L5 ETMDATA[25] M5 M5 ETMDATA[26] N5 N5 ETMDATA[27] P5 P5 ETMDATA[28] R5 R5 ETMDATA[29] R6 R6 ETMDATA[30] R7 R7 ETMDATA[31] R8 R8 ETMTRACECTL R11 R11 ETMTRACECLKO UT R10 R10 ETMTRACECLKIN R9 R9 3.3V O 8mA 3.3V O 8mA ETM Trace Data output pins ETM Control pin 3.3V I ETM Clock output pin IPU (20uA) ETM Clock input pin Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 33 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 2-9. Terminal Functions (continued) Terminal Name TMS570LSXXX16 337 144 TMS570LSXXX06 337 Type 144 Internal pullup/p ulldown Description Supply Voltage Digital I/O (3.3V) and Core (1.5V) VCCIO F6 1 F6 1 VCCIO F7 VCCIO F11 15 F7 15 40 F11 VCCIO 40 F12 90 F12 90 VCCIO F13 108 F13 108 VCCIO F14 119 F14 119 VCCIO G6 132 G6 132 VCCIO G14 G14 VCCIO H6 H6 VCCIO H14 H14 VCCIO J6 J6 VCCIO L14 L14 VCCIO M6 M6 VCCIO M14 M14 VCCIO N6 N6 VCCIO N14 N14 VCCIO P6 P6 VCCIO P7 P7 VCCIO P8 P8 VCCIO P9 P9 VCCIO P12 P12 VCCIO P13 P13 VCCIO P14 P14 3.3V PWR Digital I/O supply pins Note: All VccIO pads are connected to the BGA packages through the package substrate. There is not a direct ball to bond pad connection for this supply. 1.5V PWR Digital Core supply pins Note: All Vcc pads are connected to the BGA packages through the package substrate. There is not a direct ball to bond pad connection for this supply. VCCIO VCC F9 19 F9 19 VCC F10 31 F10 31 VCC H10 37 H10 37 VCC J14 47 J14 47 VCC K6 87 K6 87 VCC K8 104 K8 104 VCC K12 114 K12 114 VCC K14 135 K14 135 VCC L6 L6 VCC M10 M10 VCC P10 P10 VCC P11 P11 VCC 34 Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 2-9. Terminal Functions (continued) Terminal Name TMS570LSXXX16 TMS570LSXXX06 337 144 337 144 A1 2 A1 2 VSS A2 16 A2 16 VSS A18 22 A18 22 VSS A19 32 A19 32 VSS B1 38 B1 38 VSS B19 39 B19 39 VSS H8 46 H8 46 VSS H9 86 H9 86 VSS H11 89 H11 89 VSS H12 103 H12 103 VSS J8 107 J8 107 VSS J9 115 J9 115 VSS J10 120 J10 120 VSS J11 127 J11 127 VSS J12 133 J12 133 VSS K9 136 K9 136 VSS K10 K10 VSS K11 K11 VSS L8 L8 VSS L9 L9 VSS L10 L10 VSS L11 L11 VSS L12 L12 VSS M8 M8 Type Internal pullup/p ulldown Description Supply Ground VSS VSS M9 M9 VSS M11 M11 VSS M12 M12 VSS V1 V1 VSS W1 W1 VSS W2 W2 VSS V4 V4 GND Digital supply ground reference pins Note: All Vss pads are connected to the BGA packages through the package substrate. VSS VSS VSS VSS VSS Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 35 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 2.6 2.6.1 www.ti.com Device Support Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,TMS570LS20216ASPGEQQ1). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS Fully-qualified production device. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PGE), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in Mega Hertz. 36 Device Overview Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Full Part # TMS 570 LS 20 2 16 A S PGE Q Q1 R S 5 LS 20 2 16 A S PGE Q Q1 R Orderable Part # Prefix: TM S = Fully TMS Qualified P = TMP Prototype X = TMX Samples Core Technology: 5 = 570 Cortex R4 Architecture: LS = Lockstep CPUs Flash Memory Size: 20 = 2MB 10 = 1MB RAM Memory Size: 2 = 160kB 1 = 128kB Peripheral Set: 16 = FlexRay 06 = No FlexRay Die Revision: Blank = Initial Die A = 1st Die Revision B = 2nd Die Revision Technology/Core Voltage: S = F035 (130nm), 1.5 V nominal core voltage Package Type: PGE = 144p QFP Package [Green] ZWT = 337p BGA Package [Green] Temperature Range: Q = -40...+125oC Quality Designator: Q1 = Automotive Shipping Options: R = Tape and Reel A. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com). Figure 2-9. Device Numbering Conventions(A) Device Overview Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 37 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 3 Reset / Abort Sources 3.1 Reset / Abort Sources The device Resets and Aborts are handled as shown in the following table. The table shows the source of the error, the system mode, the type of error response and the corresponding Error Signaling Module (ESM) channel. Only standard ARM exception handlers and ESM errors are used. Table 3-1. Reset / Abort Sources Error Source System Mode Error Response ESM Hookup group channel Precise write error (Strongly Ordered) User/Privilege Precise Abort (CPU) n/a Precise read error (Device or Normal) User/Privilege Precise Abort (CPU) n/a Imprecise write error (Device or Normal) User/Privilege Imprecise Abort (CPU) n/a Illegal instruction User/Privilege Undefined Instruction Trap (CPU) (1) n/a MPU access violation User/Privilege Abort (CPU) n/a B0 Tightly Coupled Memory (TCM) (even) ECC single error (correctable) User/Privilege ESM 1.26 B0 TCM (even) ECC double error (non-correctable) User/Privilege Abort (CPU), ESM => nERROR 3.3 B0 TCM (even) uncorrectable error (i.e. redundant address decode) User/Privilege ESM => NMI 2.6 B0 TCM (even) address bus parity error User/Privilege ESM => NMI 2.10 B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28 B1 TCM (odd) ECC double error (non-correctable) User/Privilege Abort (CPU), ESM => nERROR 3.5 B1 TCM (odd) uncorrectable error (i.e. redundant address decode) User/Privilege ESM => NMI 2.8 B1 TCM (odd) address bus parity error User/Privilege ESM => NMI 2.12 1) CPU transactions 2) SRAM 3) Flash with ECC INTEGRATED INTO CPU ECC single error (correctable) User/Privilege ESM 1.6 ECC double error (noncorrectable) User/Privilege Abort (CPU), ESM => nERROR 3.7 Uncorrectable error (i.e. redundant address tag, redundant syndrome compare, address bus parity, etc.) User/Privilege ESM => NMI 2.4 External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5 External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13 4) DMA transactions (1) 38 The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the Code reaches the execute stage of the CPU. Reset / Abort Sources Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 3-1. Reset / Abort Sources (continued) System Mode Error Response ESM Hookup group channel Memory access permission violation Error Source User/Privilege ESM 1.2 Memory parity error User/Privilege ESM 1.3 External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5 External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13 External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5 External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13 NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM n/a External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM n/a Memory access permission violation User/Privilege ESM 1.9 Memory parity error User/Privilege ESM 1.8 User/Privilege ESM 1.7 MibSPI1 memory parity error User/Privilege ESM 1.17 MibSPI3 memory parity error User/Privilege ESM 1.18 MibSPIP5 memory parity error User/Privilege ESM 1.24 MibADC1 memory parity error User/Privilege ESM 1.19 MibADC2 memory parity error User/Privilege ESM 1.1 DCAN1 memory parity error User/Privilege ESM 1.21 DCAN2 memory parity error User/Privilege ESM 1.23 DCAN3 memory parity error User/Privilege ESM 1.22 User/Privilege ESM 1.10 User/Privilege ESM 1.11 5) DMM transactions 6) AHB-AP transactions 7) HET TU 8) NHET Memory parity error 9) MibSPI 10) MibADC 11) DCAN 12) PLL PLL slip error 13) Clock monitor Clock monitor interrupt 14) CCM Self test failure User/Privilege ESM 1.31 Compare failure User/Privilege ESM => NMI 2.2 User/Privilege ESM 1.12 User/Privilege Interrupt => VIM n/a 15) FlexRay Memory parity error 16) FlexRay TU NCNB (Strongly Ordered) transaction with slave error response Reset / Abort Sources Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 39 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 3-1. Reset / Abort Sources (continued) System Mode Error Response ESM Hookup group channel External imprecise error (Illegal transaction with ok response) Error Source User/Privilege Interrupt => VIM n/a Memory access permission violation User/Privilege ESM 1.16 Memory parity error User/Privilege ESM 1.14 User/Privilege ESM 1.15 n/a Reset n/a User/Privilege ESM 1.27 17) VIM Memory parity error 18) voltage monitor VMON out of voltage range 19) CPU Selftest (LBIST) CPU Selftest (LBIST) error 20) errors reflected in the SYSESR register Power-Up Reset; VCC out of voltage range n/a Reset n/a Oscillator fail / PLL slip (2) n/a Reset n/a Watchdog time limit exceeded n/a Reset n/a CPU Reset n/a Reset n/a Software Reset n/a Reset n/a External Reset n/a Reset n/a (2) 40 Oscillator fail/PLL slip can be configured in the system register PLLCTL1 to generate a reset. Reset / Abort Sources Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 4 Peripherals 4.1 Error Signaling Module (ESM) The Error Signaling Module (ESM) is used to indicate a severe device failure via interrupts and the external ERROR pin. The error pin is normally used by an external device to either reset the controller and/or keep the system in a fail safe state. The ESM module consists of three error groups with 32 inputs each. The generation of the interrupts and the activation of the ERROR Pin is shown in the following table. The next table shows the ESM error sources and their corresponding group and channel numbers. Table 4-1. ESM Groups Error Group Interrupt, Level Influence on ERROR pin Group1 maskable, low/high configurable Group2 non-maskable, high fixed Group3 none, none fixed Table 4-2. ESM Assignments ERROR Sources Group Channels Reserved Group1 0 MibADC2 - parity Group1 1 DMA - MPU Group1 2 DMA - parity Group1 3 Reserved Group1 4 DMA/DMM/AHB-AP - imprecise read error Group1 5 Flash (ATCM) - correctable error Group1 6 NHET - parity Group1 7 HET TU - parity Group1 8 HET TU - MPU Group1 9 PLL - slip Group1 10 Clock Monitor - interrupt Group1 11 FlexRay - parity Group1 12 DMA/DMM/AHB-AP - imprecise write error Group1 13 FlexRay TU - parity Group1 14 VIM RAM - parity Group1 15 FlexRay TU - MPU Group1 16 MibSPI1 - parity Group1 17 MibSPI3 - parity Group1 18 MibADC1 - parity Group1 19 Reserved Group1 20 DCAN1 - parity Group1 21 DCAN3 - parity Group1 22 DCAN2 - parity Group1 23 MibSPIP5 - parity Group1 24 Reserved Group1 25 RAM even bank (B0TCM) - correctable error Group1 26 CPU - selftest Group1 27 RAM odd bank (B1TCM) - correctable error Group1 28 Reserved Group1 29 Reserved Group1 30 Peripherals Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 41 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 4-2. ESM Assignments (continued) 42 ERROR Sources Group Channels CCM-R4 - selftest Group1 31 Reserved Group2 0 Reserved Group2 1 CCM-R4 - compare Group2 2 Reserved Group2 3 Flash (ATCM) - uncorrectable error Group2 4 Reserved Group2 5 RAM even bank (B0TCM) - uncorrectable error Group2 6 Reserved Group2 7 RAM odd bank (B1TCM) - uncorrectable error Group2 8 Reserved Group2 9 RAM even bank (B0TCM) - address bus parity error Group2 10 Reserved Group2 11 RAM odd bank (B1TCM) - address bus parity error Group2 12 Reserved Group2 13 Reserved Group2 14 Reserved Group2 15 Flash (ATCM) - ECC live lock detect Group2 16 Reserved Group2 17 Reserved Group2 18 Reserved Group2 19 Reserved Group2 20 Reserved Group2 21 Reserved Group2 22 Reserved Group2 23 Reserved Group2 24 Reserved Group2 25 Reserved Group2 26 Reserved Group2 27 Reserved Group2 28 Reserved Group2 29 Reserved Group2 30 Reserved Group2 31 Reserved Group3 0 Reserved Group3 1 Reserved Group3 2 RAM even bank (B0TCM) - ECC uncorrectable error Group3 3 Reserved Group3 4 RAM odd bank (B1TCM) - ECC uncorrectable error Group3 5 Reserved Group3 6 Flash (ATCM) - ECC uncorrectable error Group3 7 Reserved Group3 8 Reserved Group3 9 Reserved Group3 10 Reserved Group3 11 Reserved Group3 12 Reserved Group3 13 Peripherals Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 4-2. ESM Assignments (continued) ERROR Sources Group Channels Reserved Group3 14 Reserved Group3 15 Reserved Group3 16 Reserved Group3 17 Reserved Group3 18 Reserved Group3 19 Reserved Group3 20 Reserved Group3 21 Reserved Group3 22 Reserved Group3 23 Reserved Group3 24 Reserved Group3 25 Reserved Group3 26 Reserved Group3 27 Reserved Group3 28 Reserved Group3 29 Reserved Group3 30 Reserved Group3 31 Peripherals Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 43 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 4.2 www.ti.com Direct Memory Access (DMA) The direct-memory access (DMA) controller transfers data to and from any specified location in the device memory map. The DMA supports data transfer for both on-chip memories and peripherals. The DMA controller on this device supports 16 channels and 32 request lines. Each of the 32 DMA requests are assigned by default to one of the 16 available channels. For DMA requests multiplexed between multiple sources, the DMA controller cannot differentiate between the multiple sources and the user has to ensure that multiple sources are not enabled at the same time. Please refer to the DMA Specification in the TRM for more details. The DMA request configuration is shown in the following table. Table 4-3. DMA Request Line Connection (1) (2) 44 Modules DMA Request Sources DMA Request MIBSPI1 MIBSPI1[1] (1) DMAREQ[0] MIBSPI1 MIBSPI1[0] (2) DMAREQ[1] Reserved Reserved DMAREQ[2] Reserved Reserved DMAREQ[3] MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3 DMAREQ[4] MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2 DMAREQ[5] MIBSPIP5 / DCAN1 MIBSPIP5[2] / DCAN1 IF2 DMAREQ[6] MIBADC1 / MIBSPIP5 MIBADC1 event / MIBSPIP5[3] DMAREQ[7] MIBSPI1 / MIBSPI3 / DCAN1 MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1 DMAREQ[8] MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1 DMAREQ[9] MIBADC1 / MIBSPIP5 MIBADC1 G1 / MIBSPIP5[4] DMAREQ[10] MIBADC1 / MIBSPIP5 MIBADC1 G2 / MIBSPIP5[5] DMAREQ[11] RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6] DMAREQ[12] RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7] DMAREQ[13] MIBADC2 / MIBSPI3 / MIBSPIP5 MIBADC2 event / MIBSPI3[1] (1) / MIBSPIP5[6] DMAREQ[14] MIBSPI3 / MIBSPIP5 MIBSPI3[0]† / MIBSPIP5[7] DMAREQ[15] MIBADC2 / MIBSPI1 / MIBSPI3 / DCAN1 MIBADC2 G1 / MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 DMAREQ[16] MIBADC2 / MIBSPI1 / MIBSPI3 / DCAN3 MIBADC2 G2 / MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 DMAREQ[17] RTI / MIBSPIP5 RTI DMAREQ2 / MIBSPIP5[8] DMAREQ[18] RTI / MIBSPIP5 RTI DMAREQ3 / MIBSPIP5[9] DMAREQ[19] LIN2 / NHET / DCAN3 LIN2 receive / NHET DMAREQ[4] / DCAN3 IF2 DMAREQ[20] LIN2 / NHET / DCAN3 LIN2 transmit / NHET DMAREQ[5] / DCAN3 IF3 DMAREQ[21] MIBSPI1 / MIBSPI3 / MIBSPIP5 MIBSPI1[10] / MIBSPI3[10] / MIBSPIP5[10] DMAREQ[22] MIBSPI1 / MIBSPI3 / MIBSPIP5 MIBSPI1[11] / MIBSPI3[11] / MIBSPIP5[11] DMAREQ[23] NHET / MIBSPIP5 NHET DMAREQ[6] / MIBSPIP5[12] DMAREQ[24] NHET / MIBSPIP5 NHET DMAREQ[7] / MIBSPIP5[13] DMAREQ[25] CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12] DMAREQ[26] CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13] DMAREQ[27] LIN1 / MIBSPIP5 LIN1 receive / MIBSPIP5[14] DMAREQ[28] LIN1 / MIBSPIP5 LIN1 transmit / MIBSPIP5[15] DMAREQ[29] MIBSPI1 / MIBSPI3 / MIBSPIP5 MIBSPI1[14] / MIBSPI3[14] / MIBSPIP5[1] (1) DMAREQ[30] MIBSPI1 / MIBSPI3 / MIBSPIP5 MIBSPI1[15] / MIBSPI3[15] / MIBSPIP5[0] (2) DMAREQ[31] SPI1, SPI3, SPI5 receive in standard SPI/compatibility mode SPI1, SPI3, SPI5 transmit in standard SPI/compatibility mode Peripherals Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 4.3 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 High End Timer Transfer Unit (HET-TU) The High End Timer Transfer Unit (HET-TU) is a local Direct Memory Access (DMA) module. It is specifically designed to transfer High End Timer (NHET) data to (or from) the CPU data SRAM . The HET software controls which HET instructions generate transfer requests to the transfer unit. More information about the NHET and the HET-TU can be found in the technical reference manual (TRM). The HET-TU supports 8 channels. The HET-TU request assignment is shown in the following table. Table 4-4. NHET Request Line Connection Modules Request Source HET TRANSFER UNIT Request NHET HTUREQ[0] HET TU DCP[0] NHET HTUREQ[1] HET TU DCP[1] NHET HTUREQ[2] HET TU DCP[2] NHET HTUREQ[3] HET TU DCP[3] NHET HTUREQ[4] HET TU DCP[4] NHET HTUREQ[5] HET TU DCP[5] NHET HTUREQ[6] HET TU DCP[6] NHET HTUREQ[7] HET TU DCP[7] Peripherals Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 45 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 4.4 www.ti.com Vectored Interrupt Manager (VIM) The Vectored Interrupt Manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on the device. Interrupt requests originating from the device modules (i.e., SPI, LIN, SCI, etc.) are assigned to channels within the 64-channel VIM. Programming multiple interrupt sources to the same VIM channel effectively shares the VIM channel between sources. The VIM request channels are maskable so that individual channels can be selectively disabled. All interrupt requests can be programmed in the VIM to be of either type: • Fast interrupt request (FIQ)- The FIQ implemented in Cortex-R4F is Non-Maskable Fast Interrupts (NMFI). • Normal interrupt request (IRQ) The VIM prioritizes interrupts, whose precedence of request channels decrease with ascending channel order in the VIM (0 [highest] and 64[lowest] priority). For VIM default mapping, channel priorities, and their associated modules see the table below. More information on the VIM can be found in the technical reference manual (TRM). Table 4-5. Interrupt Request Assignments 46 Modules Interrupt Sources Default VIM Interrupt Request ESM ESM High level interrupt (NMI) 0 Reserved (NMI) 1 RTI RTI compare interrupt 0 2 RTI RTI compare interrupt 1 3 RTI RTI compare interrupt 2 4 RTI RTI compare interrupt 3 5 RTI RTI overflow interrupt 0 6 RTI RTI overflow interrupt 1 7 RTI RTI timebase 8 GIO GIO interrupt A 9 NHET NHET level 1 interrupt 10 HET TU HET TU level 1 interrupt 11 MIBSPI1 MIBSPI1 level 0 interrupt 12 LIN1 (incl. SCI) LIN1 level 0 interrupt 13 MIBADC1 MIBADC1 event group interrupt 14 MIBADC1 MIBADC1 sw group 1 interrupt 15 DCAN1 DCAN1 level 0 interrupt 16 Reserved Reserved 17 FlexRay FlexRay level 0 interrupt 18 CRC CRC Interrupt 19 ESM ESM Low level interrupt 20 SYSTEM Software interrupt (SSI) 21 CPU PMU Interrupt 22 GIO GIO interrupt B 23 NHET NHET level 2 interrupt 24 HET TU HET TU level 2 interrupt 25 MIBSPI1 MIBSPI1 level 1 interrupt 26 LIN1 (incl. SCI) LIN1 level 1 interrupt 27 MIBADC1 MIBADC1 sw group 2 interrupt 28 DCAN1 DCAN1 level 1 interrupt 29 Reserved Reserved 30 MIBADC1 MIBADC1 magnitude interrupt 31 Peripherals Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 4-5. Interrupt Request Assignments (continued) Modules Interrupt Sources Default VIM Interrupt Request FlexRay FlexRay level 1 interrupt 32 DMA FTCA interrupt 33 DMA LFSA interrupt 34 DCAN2 DCAN2 level 0 interrupt 35 DMM DMM level 0 interrupt 36 MIBSPI3 MIBSPI3 level 0 interrupt 37 MIBSPI3 MIBSPI3 level 1 interrupt 38 DMA HBCA interrupt 39 DMA BTCA interrupt 40 Reserved Reserved 41 DCAN2 DCAN2 level 1 interrupt 42 DMM DMM level 1 interrupt 43 DCAN1 DCAN1 IF3 interrupt 44 DCAN3 DCAN3 level 0 interrupt 45 DCAN2 DCAN2 IF3 interrupt 46 FPU FPU interrupt 47 FlexRay TU FlexRay TU Transfer Status interrupt 48 LIN2 (incl. SCI) LIN2 level 0 interrupt 49 MIBADC2 MIBADC2 event group interrupt 50 MIBADC2 MIBADC2 sw group 1 interrupt 51 FlexRay FlexRay T0C interrupt 52 MIBSPIP5 MIBSPIP5 level 0 interrupt 53 LIN2 (incl. SCI) LIN2 level 1 interrupt 54 DCAN3 DCAN3 level 1 interrupt 55 MIBSPIP5 MIBSPIP5 level 1 interrupt 56 MIBADC2 MIBADC2 sw group 2 interrupt 57 FlexRay TU FlexRay TU Error interrupt 58 MIBADC2 MIBADC2 magnitude interrupt 59 DCAN3 DCAN3 IF3 interrupt 60 Reserved Reserved 61 FlexRay FlexRay T1C interrupt 62 Reserved Reserved 63 Note: Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry. Peripherals Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 47 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 4.5 www.ti.com MIBADC Event Trigger Sources All three conversion groups can be configured for event-triggered operation, providing up to three event triggered groups. The trigger source and polarity can be selected individually for group 1, group 2 and the event group from the options identified in the first table following for MibADC1 and in the second table following for MibADC2. Table 4-6. MIBADC1 Event Trigger Sources Event # SOURCE SELECT BITS for G1, G2 or EVENT (G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0]) Hookup 1 000 AD1EVT 2 001 NHET[8] 3 010 NHET[10] 4 011 RTI compare 0 5 100 NHET[17] 6 101 NHET[19] 7 110 GIOB[0] 8 111 GIOB[1] NOTE The Trigger is present, even if the pin is not available. Table 4-7. MIBADC2 Event Trigger Sources Event # SOURCE SELECT BITS for G1, G2 or EVENT (G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0]) Hookup 1 000 AD2EVT 2 001 NHET[8] 3 010 NHET[10] 4 011 RTI compare 0 5 100 NHET[17] 6 101 NHET[19] 7 110 GIOB[0] 8 111 GIOB[1] NOTE The Trigger is present, even if the pin is not available. The application can generate the trigger condition using these signals by configuring the corresponding device pins as input pins and driving them from an external source, or by configuring them as output pins and driving them by software. The pin doesn't have to be present on the package to be able to be used as a trigger. The interrupt request signals (RTI compare 0) are driven HIGH when the interrupt condition occurs. So if the ADC is required to be triggered on the interrupt being asserted, select the rising edge for this trigger source. The ADC can be still triggered using the falling edge on the interrupt line. In this case, the falling edge occurs when the interrupt line is deasserted. 48 Peripherals Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 4.6 4.6.1 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 MIBSPI MIBSPI Event Trigger Sources The Multi-buffered Serial Peripheral Interfaces (MIBSPIs) have a programmable buffer memory that enables data transmission to be completed without CPU intervention. The buffers are combined in different Transfer Groups (TGs) that can be triggered by external events such as I/O activity, timers or by the internal tick counter. The internal tick counter supports the periodic trigger of events. Each buffer of the MibSPI can be associated with different DMA channels in different TGs, allowing the user to move data between internal memory and an external slave with minimal CPU interaction. Table 4-8. MIBSPI1 Event Trigger Sources Event TGxCTRL TRIGSRC[3:0] Hookup Disabled 0000 No trigger source EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 NHET[8] EVENT9 1010 NHET[10] EVENT10 1011 NHET[12] EVENT11 1100 NHET[14] EVENT12 1101 NHET[16] EVENT13 1110 NHET[18] EVENT14 1111 Internal Tick counter Table 4-9. MIBSPI3 Event Trigger Sources Event TGxCTRL TRIGSRC[3:0] Hookup Disabled 0000 No trigger source EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 NHET[8] EVENT9 1010 NHET[10] EVENT10 1011 NHET[12] EVENT11 1100 NHET[14] EVENT12 1101 NHET[16] EVENT13 1110 NHET[18] EVENT14 1111 Internal Tick counter Peripherals Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 49 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 4-10. MIBSPI5 Event Trigger Sources 4.6.2 Event TGxCTRL TRIGSRC[3:0] Hookup Disabled 0000 No trigger source EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 NHET[8] EVENT9 1010 NHET[10] EVENT10 1011 NHET[12] EVENT11 1100 NHET[14] EVENT12 1101 NHET[16] EVENT13 1110 NHET[18] EVENT14 1111 Internal Tick counter MIBSPIP5/DMM Pin Multiplexing The multiplexing of MIBSPIP5 and DMM pins are controlled by the status of the MIBSPIP5 module and the DMM module. The pins will have DMM functionality if the DMM module is enabled and the MIBSPIP5 module is disabled; if the MIBSPIP5 is enabled the pins will have MIBSPI functionality, regardless of the DMM module status. DMMCLK, DMMSYNC, DMMENA and DMMDATA[1:0] are always functional independent of the MIBSPIP5 configuration because they are not multiplexed. The related pin numbers can be found in the MIBSPI5 and the DMM section of the Terminal Functions chapter. The following table shows the MIBSPI5 and DMM Data pin multiplexing. Table 4-11. MIBSPIP5 Pin Multiplexing 50 Peripherals MIBSPIP5 enabled DMM enabled &MIBSPIP5 disabled MIBSPI5CLK DMMDATA[4] MIBSPI5CS[0] DMMDATA[5] MIBSPI5CS[1] DMMDATA[6] MIBSPI5CS[2] DMMDATA[2] MIBSPI5CS[3] DMMDATA[3] MIBSPI5ENA DMMDATA[7] MIBSPI5SIMO[0] DMMDATA[8] MIBSPI5SIMO[1] DMMDATA[9] MIBSPI5SIMO[2] DMMDATA[10] MIBSPI5SIMO[3] DMMDATA[11] MIBSPI5SOMI[0] DMMDATA[12] MIBSPI5SOMI[1] DMMDATA[13] MIBSPI5SOMI[2] DMMDATA[14] MIBSPI5SOMI[3] DMMDATA[15] Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 4.7 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 ETM The device contains an ARM Cortex™-R4F External Trace Macrocell (ETM-R4) with a 32bit data port. The ETM-R4 module is connected to a Test Port Interface Unit (TPIU) with a 32bit data bus. The ETM-R4 is CoreSight compliant and follows the ARM ETM v3 specification; for more details see ARM CoreSight™ ETM-R4 TRM specification Revr0p0. The ETM-R4 supports "half rate clocking" only. The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The selection is done by the EXTCTRLOUT[1:0] control bits of the TPIU; the default is '00'. Table 4-12. ETMTRACECLKIN Selection EXTCTRLOUT[1:0] TPIU/TRACECLKIN 00 tied-zero 01 VCLK 10 ETMTRACECLKIN 11 tied-zero Peripherals Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 51 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 4.8 www.ti.com Debug Scan Chains The device contains an ICEPICK module to access the debug scan chains. Debug scan chain #0 handles the access to the CPU, to the ETM-R4 (External Trace Macrocell), to the POM (Parameter Overlay Module) and to the TPIU (Test Port Interface Unit). Debug scan chain #1 handles the access to the Ram Trace Port (RTP) and the Data Modification Module (DMM) which each incorporate a dedicated TAP (Test Access Port) controller. Each module is selected via its scan chain number. The IcePick scan ID is 0x80206D05, which is the same number as the device ID. DAP ETM ICEPICK CPU TDI TPIU CoreSight debug scan chain #0 RTP TAP POM RTP 0 TDO DMM TAP DMM 1 debug scan chain #1 Boundary Scan boundary scan interface Figure 4-1. Debug Scan Chains 4.8.1 JTAG The 32bit JTAG ID code for this device is 0x0B7B302F. 52 Peripherals Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 4.9 4.9.1 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 CCM Dual Core Implementation The microcontroller has two Cortex-R4 cores, where the output signals of both CPUs are compared in the CCM-R4 (Core Compare Module). To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in the following figure. CCM-R4 1.5cycle delay CCM-R4 Compare CPU1CLK Compare Error CPU 2 CPU 1 1.5cycle delay CPU2CLK Figure 4-2. Dual Core Implementation 4.9.2 CCM-R4 To avoid an erroneous CCM-R4 compare error, the application software must ensure that the CPU registers of both CPUs are initialized with the same values before the 1st function call or other operation that pushes the CPU registers onto the stack. All CCM-R4 error forcing test modes are limited to 100MHz HCLK speed. Peripherals Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 53 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 4.10 LPM TMS570 Platform devices support multiple low power modes. These different modes allow the user to trade-off the amount of current consumption during low power mode versus functionality and wake-up time. Supported Low Power modes on this devices are Doze, Snooze and Sleep; for detailed description please refer to the Architecture section of the Technical Reference Manual. 4.11 Voltage Monitor A voltage monitor has been implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies. It also reduces the risk of corrupting memory or glitches on I/O pins during power-up, power-down or brown outs. The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the device is held in reset when the voltage supplies are out of range. The voltage monitor thresholds can be found in the Vmon section of the device electrical specifications. When the voltage monitor detects a low voltage on the I/O supply, it will assert a reset. When the voltage monitor detects a low voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a reset. The voltage monitor is disabled when the device is in halt mode. The voltage monitor has three filter functions: • It rejects short low-going glitches on the PORRST pin • It rejects noise on the VCCIO supply • It rejects noise on the VCC supply Please note that such glitches on VCC and VCCIO could still corrupt the system depending on many factors. The width of noise that can be filtered by the voltage monitor on the VCC and VCCIO supplies is shown in the table below. Glitches less than MIN will be filtered out, glitches greater than MAX are guaranteed to generate a reset. The duration of glitches that will be filtered on the PORRST pin can be found in Table 7-6, Timing Requirements for PORRST. Table 4-13. VMON Supply Glitch Filter Capability Parameter Min Max Width of glitch on VCC that can be filtered out 300ns 1us Width of glitch on VCCIO that can be filtered out 300ns 1us 4.12 CRC MCRC Controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the integrity of memory system. A signature representing the contents of the memory is obtained when the contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the signature for a set of data and then compare the calculated signature value against a predetermined good signature value. MCRC controller provides up to four channels to perform CRC calculation on multiple memories in parallel and can be used on any memory system. Channel 1 can also be put into data trace mode. In data trace mode, MCRC controller compresses each data being read through the CPU read data bus. When using the MCRC module in PSA mode while ECC is enabled, bus masters (e.g. FTU, HTU, DMA or CPU) should not write to the data RAM (TCRAM) to avoid corrupting the PSA value. 4.13 System Module Access The system module access modes and access rights are shown in the following table. 54 Peripherals Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 4-14. System Module Access Domain Module Access Mode Used by Module Access Rights Required to Access the Module RAMS System VIM n/a privilege mode (RWP) System RTP n/a privilege mode (RWP) privilege mode (RWP) System DMA user mode Peripheral HTU privilege mode privilege mode (RWP) Peripheral FTU user & privilege mode user & privilege mode (RW) 4.14 Debug ROM The Debug ROM stores the location of the components on the Debug APB bus. Table 4-15. Debug ROM Table Address Description Value 0x000 pointer to Cortex-R4 0x00001003 0x000 ETM 0x00002003 0x000 TPIU 0x00003003 0x000 POM 0x00004003 0x001 end of table 0x00000000 Components Table Peripherals Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 55 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 4.15 CPU Self Test Controller: STC / LBIST The CPU Self Test Controller (STC) is used to test the ARM CPU core using a Deterministic Logic BIST (LBIST) Controller as the test engine. The STC has the capability of dividing the complete test run into smaller independent test sets (intervals). The test coverage and number of test execution cycles for each test interval is shown in the table below. The maximum clock rate for the STC / LBIST is: • 53.333MHz when HCLK = 160MHz / VCLK = 80MHz on BGA package • 50MHz when HCLK = 100MHz / VCLK = 100MHz on QFP and BGA packages • 46.666MHz when HCLK = 140MHz / VCLK = 70MHz on QFP and BGA packages In order to achieve the proper clock rate during CPU self test a STC clock divider has been implemented. The clock divider is set by the CLKDIV bits in STCCLKDIV register in the secondary system module frame at location 0xFFFF E108. The default value of the CPU Self Test LBIST clock divider is set to 'divide-by-1’. NOTE The supply current while performing CPU self test is different than the device operating mode current. These values can be found in the Icc section of Section 6.4. Table 4-16. STC/LBIST Test Coverage and Duration 56 Intervals Test Coverage 0 0% 0 1 57.14% 1,555 2 65.82% 3,108 3 70.56% 4,661 4 73.56% 6,214 5 76.06% 7,767 6 78.07% 9,320 7 79.62% 10,873 8 80.92% 12,426 Peripherals Test Cycles (STC Clock Cycles) 9 82.1% 13,979 10 82.94% 15,532 11 83.76% 17,085 12 84.51% 18,638 13 85.12% 20,191 14 85.62% 21,744 15 86.19% 23,297 16 86.56% 24,850 17 86.97% 26,403 18 87.33% 27,956 19 87.67% 29,509 20 88.01% 31,062 21 88.31% 32,615 22 88.58% 34,168 23 88.87% 35,721 24 89.11% 37,274 25 89.34% 38,827 26 89.59% 40,380 27 89.82% 41,933 28 90.05% 43,486 Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 4-16. STC/LBIST Test Coverage and Duration (continued) Intervals Test Coverage Test Cycles (STC Clock Cycles) 29 90.26% 45,039 30 90.46% 46,592 31 90.64% 48,145 32 90.84% 49,698 Peripherals Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 57 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 5 Device Registers 5.1 Device Identification Code Register The device identification code register identifies several aspects of the device including the silicon version. The details of the device identification code register are shown in Figure 5-1. The device identification code register value for this device is: • Rev 0 = 0x80206D05 • Rev A = 0x80206D0D Figure 5-1. Device ID Bit Allocation Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CP-15 UNIQUE ID 16 R-1 R-00000 0000 10000 R-0 15 14 13 12 11 10 9 8 TECH I/O VOLT AGE PERIP HERA L PARIT Y FLASH ECC RAM ECC R-011 R-0 R-1 R-10 R-1 7 6 5 4 3 2 1 0 VERSION 1 0 1 R-1 R-1 R-0 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device dependent Table 5-1. Device ID Bit Allocation Register Field Descriptions Bit Field 31 CP15 30-17 UNIQUE ID 16-13 TECH Value Indicates the presence of coprocessor 15 0 CP15 not present 1 CP15 present 1 Silicon version (revision) bits This bitfield holds a unique number for a dedicated device configuration (die). Process technology on which the device is manufactured. 0000 C05 0001 F05 0010 C035 0011 F035 Others 12 11 10-9 8 7-3 58 I/O VOLTAGE I/O voltage of the device. I/O are 3.3v 1 I/O are 5v Peripheral Parity 0 No parity on peripherals 1 Parity on peripherals FLASH ECC Flash ECC 00 No error detection/correction 01 Program memory with parity 10 Program memory with ECC 11 Reserved RAM ECC Device Registers Reserved 0 PERIPHERA L PARITY REVISION Description Indicates if RAM memory ECC is present. 0 No ECC implemented 1 ECC implemented Revision of the Device. Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 5-1. Device ID Bit Allocation Register Field Descriptions (continued) Bit Field 2-0 101 Value Description The platform family ID is always 0b101 Device Registers Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 59 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 5.2 www.ti.com Die-ID Registers The two registers (DIEIDL and DIEIDH) form a 64-bit number that contains information about the device’s die lot number, wafer number and X, Y wafer coordinates. The die identification information will vary from unit to unit. This information is programmed by TI as part of the initial device test procedure. The data format of the Die-ID registers is shown here. Figure 5-2. DIEIDL Register (Location: 0xFFFF FF7C) 31 15 30 14 29 13 28 27 26 25 24 23 22 21 20 19 18 LOT (LOWER 10 BITS) WAFER # R-D R-D 12 11 10 9 8 7 6 5 4 3 2 Y WAFER COORDINATES X WAFER COORDINATES R-D R-D 17 16 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device dependent Figure 5-3. DIEIDH Register (Location: 0xFFFF FF80) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RESERVED R-D 15 14 13 RESERVED 12 11 10 9 8 7 LOT # (UPPER 14 BITS) R-D LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device dependent 60 Device Registers Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 5.3 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 PLL Registers The default values for the PLL (Phase Locked Loop) control registers are shown in this section. PLLCTL1 and PLLCTL2 are used to configure PLL1 (F035 FMzPLL) and PLLCTL3 is used to configure PLL2 (F035 FPLL). Figure 5-4. PLLCTL1 Register (Location: 0xFFFF FF70) 23 22 ROS 31 BPOS[1:0] PLLDIV[4:0] ROF RESV REFCLKDIV[5:0] R/WP0 R/WP-01 R/WP-01111 R/WP0 R-0 R/WP-000010 7 6 15 30 14 29 13 28 12 27 26 11 10 25 9 24 8 21 5 20 4 19 3 18 17 16 2 1 0 18 17 16 1 0 17 16 1 0 PLLMUL[15:0] R/WP-0101111100000000 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device specific PLLCTL1 Default = 0x2F025F00 Figure 5-5. PLLCTL2 Register (Location: 0xFFFF FF74) 31 30 29 28 27 26 25 24 23 22 21 20 19 FMEN A SPREADINGRATE[8:0] RESV EWADJ[8:4] R/WP0 R/WP-111111111 R-0 R/WP-00000 15 14 13 12 11 10 9 8 7 6 5 4 3 BWADJ[3:0] ODPLL SPR_AMOUNT[8:0] R/WP-0111 R/WP-001 R/WP-000000000 2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D = device specific PLLCTL2 Default = 0x7FC07200 NOTE There are several combinations of the modulation depth and modulation frequency that are not allowed. Valid settings for this device include the list in Table 7-2. Figure 5-6. PLLCTL3 Register (Location: 0xFFFF E100) 31 15 30 14 29 13 28 27 26 25 24 23 22 21 20 19 18 RESERVED OSC DIV RESERVED R/W-000000000 R/WP0 R/W-000000 12 11 10 9 8 7 6 5 4 3 2 RESERVED PLL_MUL[3:0] RESERVED PLL_DIV [2:0] R/W-000000 R/WP-011 R/W-00000 R/WP 111 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device specific PLLCTL3 Default = 0x00000307 Device Registers Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 61 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 6 Device Electrical Specifications 6.1 Operating Conditions 6.2 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted) (1) VCC (2) - 0.3 V to 2.1V VCCIO, VCCAD, VCCP (Flash pump) (2) - 0.3 V to 4.1V Input voltage range All input pins - 0.3 V to 4.1 V Input clamp current IIK(VI VCCIO) ±20 mA Supply voltage ranges All pins except AD1IN[7:0], AD2IN[7:0], ADSIN[15:8] IIK (VIVCCAD) Operating free-air temperature ranges, TA AD1IN[7:0], AD2IN[7:0], ADSIN[15:8] ±10 mA total ±40 mA Q version - 40°C to 125°C Operating junction temperature range, TJ -40°C to 150°C Storage temperature range, Tstg - 65°C to 150°C (1) (2) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability All voltage values are with respect to their associated grounds. Device Recommended Operating Conditions (1) 6.3 MIN VCC Digital logic supply voltage (Core) VCCIO VCCAD NOM MAX Unit 1.35 1.5 1.65 V Digital logic supply voltage (I/O) 3 3.3 3.6 V MibADC supply voltage 3 3.3 3.6 V VCCP Flash pump supply voltage 3 3.3 3.6 V VSS Digital logic supply ground VSSAD MibADC supply ground TA Operating free-air temperature TJ Operating junction temperature (1) All voltages are with respect to VSS except VCCAD is with respect to VSSAD. 62 Device Electrical Specifications 0 Q version V -0.1 0.1 V -40 125 °C -40 150 °C Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Electrical Characteristics Over Operating Free-Air Temperature Range (1) 6.4 Parameter Vhys Test Conditions Input hysteresis MIN TYP VIL Low-level input voltage All inputs VIH High-level input voltage All inputs VOL Low-level output voltage (2) High-level output voltage -0.3 0.8 V 2 VCCIO + 0.3 V 0.2 VCCIO V IOL = IOL MAX IOH = IOH MAX IOH = 50 µA Unit V IOL = 50 µA VOH MAX 0.15 0.2 0.8 VCCIO V VCCIO 0.2 VILoscin Low-level input voltage OSCIN -0.3 0.2 VCC V VIHoscin High-level input voltage OSCIN 0.8 VCC VCC + 0.3 V VMON Voltage monitoring threshold VCC low 1.0 1.2 1.35 V VCC high 1.7 2 2.38 2.0 2.4 3.0 VCCIO low IIC Input clamp current VI < VSSIO - 0.3 or VI > VCCIO + 0.3 -2 2 mA II Input current (I/O pins) IIL Pulldown VI = VSS -1 1 µA IIH Pulldown 20 uA VI = VCCIO 5 40 IIH Pulldown 100 uA VI = VCCIO 40 195 IIL Pullup 20 uA VI = VSS -40 -5 IIL Pullup 100 uA VI = VSS -195 -40 IIH Pullup VI = VCCIO -1 1 All other pins No pullup or pulldown -1 1 (1) (2) Source currents (out of the device) are negative while sink currents (into the device) are positive. This does not apply to PORRST pin. Device Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 63 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Electrical Characteristics Over Operating Free-Air Temperature Range(1) (continued) Parameter IOL Test Conditions Low-level output TDO current TDI MAX Unit VOL = VOL MAX MIN TYP 8 mA VOL = VOL MAX 4 mA TMS RTCK ECLK FRAYTX1 FRAYTXEN1 FRAYTX2 FRAYTXEN2 DMMENA ETMTRACECTL ETMTRACECLKOUT ETMDATA[31:0] RTPSYNC RTPCLK RTPDATA[15:0] EMIFWE EMIFOE EMIFCS[3:0] EMIFDATA[15:0] EMIFADD[21:0] EMIFBADD[1:0] EMIFDQM[1:0] ERROR IOL Low-level output RST current MIBSPI1CLK MIBSPI1SIMO MIBSPI1SOMI MIBSPI3CLK MIBSPI3SIMO MIBSPI3SOMI MIBSPI5CLK MIBSPI5SIMO[3:0] MIBSPI5SOMI[3:0] DMMDATA[15:8] DMMDATA[4] All other output pins 64 Device Electrical Specifications 2 Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Electrical Characteristics Over Operating Free-Air Temperature Range(1) (continued) Parameter IOH High-level output current Test Conditions TDO MAX Unit VOH = VOH MIN MIN TYP -8 mA VOH = VOH MIN -4 mA TDI TMS RTCK ECLK FRAYRX1 FRAYTX1 FRAYTXEN1 FRAYRX2 FRAYTX2 FRAYTXEN2 ETMTRACECTL ETMTRACECLKOUT ETMDATA[31:0] RTPSYNC RTPCLK RTPDATA[15:0] DMMENA EMIFWE EMIFOE EMIFCS[3:0] EMIFDATA[15:0] EMIFADD[21:0] EMIFBADD[1:0] EMIFDQM[1:0] ERROR IOH High-level output current RST MIBSPI1CLK MIBSPI1SIMO MIBSPI1SOMI MIBSPI3CLK MIBSPI3SIMO MIBSPI3SOMI MIBSPI5CLK MIBSPI5SIMO[3:0] MIBSPI5SOMI[3:0] DMMDATA[15:8] DMMDATA[4] All other output pins -2 Device Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 65 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Electrical Characteristics Over Operating Free-Air Temperature Range(1) (continued) Parameter ICC (3) ICCIO ICCAD ICCP Test Conditions VCC Digital supply current (Operating mode) All packages BGA packages VCC Digital supply current (CPU selftest mode: LBIST) (4) (5) All packages BGA packages VCC Digital supply current (Mem selftest mode: PBIST) (4) (6) All packages MAX Unit HCLK = 100MHz, VCLK = 100MHz MIN TYP 350 mA HCLK = 140MHz, VCLK= 70MHz 390 mA HCLK = 160MHz, VCLK = 80MHz 430 mA STCCLK = 46.666MHz Peak 510 mA STCCLK = 50.0MHz Peak 540 mA STCCLK = 53.333MHz Peak 580 mA HCLK=80MHz, VCLK=40MHz Peak 340 mA HCLK=100MHz, VLCK=100MHz Peak 430 mA VCC Digital supply current (doze mode) OSCIN = 6 MHz, VCC = 1.65 V (7) 35 mA VCC Digital supply current (snooze mode) All frequencies, VCC = 1.65 V (7) 30 mA (7) VCC Digital supply current (sleep mode) All frequencies, VCC = 1.65 V 25 mA VCCIO Digital supply current (operating mode) No DC load, VCCIO = 3.6 V (8) 15 mA VCCIO Digital supply current (doze mode) No DC load, VCCIO = 3.6 V (8) 700 µA VCCIO Digital supply current (snooze mode) No DC load, VCCIO = 3.6 V (8) 100 µA VCCIO Digital supply current (sleep mode) No DC load, VCCIO = 3.6 V (8) 100 µA VCCAD supply current (operating mode) All frequencies, VCCAD = 3.6 V 30 mA VCCAD supply current (doze mode) All frequencies, VCCAD = 3.6 V (7) 200 µA VCCAD supply current (snooze mode) All frequencies, VCCAD = 3.6 V (7) 200 µA (7) VCCAD supply current (sleep mode) All frequencies, VCCAD = 3.6 V 200 µA VCCP pump supply current VCCP = 3.6 V read operation 25 mA VCCP = 3.6 V program (9) 90 mA VCCP = 3.6 V erase 90 mA VCCP = 3.6 V doze mode (7) 5 µA VCCP = 3.6 V snooze mode (7) 5 µA VCCP = 3.6 V sleep mode (7) 5 µA CI Input capacitance (10) 2 pF CO Output capacitance 3 pF (3) (4) Typical values are at Vcc=1.5V and maximum values are at Vcc=1.65V The peak current is measured on the TI EVM board with two 10µF and thirteen 100nF capacitors on VCC domain. Running at a lower frequency consumes less current. (5) LBIST currents specified are for execution of LBIST with a certain STC clock. Lower current consumption can be achieved by configuring a slower STC Clock frequency. The current peak duration can last for the duration of 1 LBIST test interval. (6) PBIST currents specified are for execution of PBIST on all RAMs(Group 1- 14) and all the algrithms. Lower current consumption can be achieved by configuring a slower HCLK frequency. Different algorithms consume different current. For more information, please refer to Basic PBIST Configuration and influence on current consumption (SPNA128). (7) For Flash banks/pumps in sleep mode. (8) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO - 0.2 V. (9) This assumes reading from one bank while programming a different bank. (10) The maximum input capacitance CI of the FlexRay RX pin(s) is 10pF. 66 Device Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7 Peripheral and Electrical Specifications 7.1 Clocks 7.1.1 PLL And Clock Specifications Table 7-1. Timing Requirements For PLL Circuits Enabled Or Disabled MIN MAX Unit f(OSC) Input clock frequency 5 20 MHz tc(OSC) Cycle time, OSCIN 50 ns tw(OSCIL) Pulse duration, OSCIN low 15 ns tw(OSCIH) Pulse duration, OSCIN high 15 f(OSCRST) OSC FAIL frequency - upper level 20 50 MHz f(OSCRST) OSC FAIL frequency - lower level 1.5 5 MHz 7.1.2 ns External Reference Resonator/Crystal Oscillator Clock Option The oscillator is enabled by connecting the appropriate fundamental 5–20 MHz resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in section (a) of the figure below. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. NOTE TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes. An external oscillator source can be used by connecting a 1.5V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in section (b) of the figure below. OSCIN (see Note B) Kelvin_GND C1 OSCOUT OSCIN OSCOUT C2 External Clock Signal (toggling 0-1.5V) (see Note A) Crystal (a) (b) Figure 7-1. Recommended Crystal/Clock Connection NOTE In figure (a), The values of C1 and C2 should be provided by the resonator/crystal vendor. In figure (b), Kelvin_GND should not be connected to any other GND. 7.1.3 Validated FMPLL Setting The following table includes the validated FMPLL settings. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 67 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com Table 7-2. Validated FMPLL Settings OSC_IN Frequency (MHz) PLLCTL1 10 10 68 PLLCTL2 FMPLL Output Frequency(MHz) Modulation Bandwidth (KHz) Modulation Depth 0x20049500 0x82409253 150 100 0.5% 0x20049500 0x8300B240 150 77 0.5% 10 0x20048600 0x8240925C 135 100 0.5% 10 0x20048600 0x8300B247 135 77 0.5% 10 0x20048600 0x824092B9 135 100 1.0% 10 0x20048D80 0x8300B443 95 77 0.5% 10 0x20048D80 0x824094AF 95 100 1.0% 16 0x20079500 0x82409253 150 100 0.5% 16 0x20079500 0x8300B240 150 77 0.5% 16 0x20078600 0x8240925C 135 100 0.5% 16 0x20078600 0x8300B247 135 77 0.5% 16 0x20078600 0x824092B9 135 100 1.0% 16 0x20078D80 0x8300B443 95 77 0.5% 16 0x20078D80 0x824094AF 95 100 1.0% 20 0x20099500 0x82409253 150 100 0.5% 20 0x20099500 0x8300B240 150 77 0.5% 20 0x20098600 0x8240925C 135 100 0.5% 20 0x20098600 0x8300B247 135 77 0.5% 20 0x20098600 0x824092B9 135 100 1.0% 20 0x20098D80 0x8300B443 95 77 0.5% 20 0x20098D80 0x824094AF 95 100 1.0% Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 7.1.4 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 LPO And Clock Detection The LPOCLKDET module consists of a clock monitor (CLKDET) and 2 low power oscillators (LPO) - a low frequency (LF) and a high frequency (HF) oscillator. The CLKDET is a supervisor circuit for an externally supplied clock signal. In case the externally supplied clock frequency falls out of a frequency window, the clock detector flags this condition and switches to the HF LPO clock (limp mode). The OSCFAIL flag and clock switch-over remain, regardless of the behavior of the oscillator clock signal. The only way OSCFAIL can be cleared (and re-enable OSCIN as the clock source) is a power-on-reset. Table 7-3. LPO And Clock Detection Invalid frequency Parameter MIN MAX Unit lower threshold 1.5 Type 5 MHz upper threshold 20 50 MHz Limp mode frequency (HFosc) 7.9 10 14.4 MHz HFosc frequency 7.9 10 14.4 MHz LFosc frequency 62 80 113 kHz lowerthreshold guaranteed fail guaranteed pass upperthreshold guaranteed fail f[MHz] 1.5 5.0 20.0 50.0 Figure 7-2. LPO And Clock Detection Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 69 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.1.5 www.ti.com Switching Characteristics Over Recommended Operating Conditions For Clocks Table 7-4. Switching Characteristics Over Recommended Operating Conditions For Clocks Parameter f(HCLK) f(HCLK) Test Conditions MIN MAX Unit HCLK - System clock frequency (337 BGA packages) Pipeline mode enabled 160 MHz Pipeline mode disabled 36 MHz HCLK - System clock frequency (144pin QFP package) Pipeline mode enabled 140 MHz Pipeline mode disabled 36 MHz f(GCLK) GCLK - CPU clock frequency (ratio GCLK : HCLK = 1:1) f(HCLK) MHz f(RCLK) RCLK - Frequency out of PLL macro into Rdivider 160 MHz f(RTICLK) (1) RTICLK - clock frequency f(VCLK) MHz f(VCLK) VCLK - Primary peripheral clock frequency f(VCLK2) MHz f(VCLK2) VCLK2 - Secondary peripheral clock frequency 100 MHz f(AVCLK1) AVCLK1 - Primary asynchronous peripheral clock frequency f(VCLK) MHz f(AVCLK2) AVCLK2 - Secondary asynchronous peripheral clock frequency f(VCLK) MHz f(ECLK) (2) ECLK - External clock output frequency for ECP Module 80 MHz f(PROG/ERASE) System clock frequency - Flash programming/erase f(HCLK) MHz (1) (2) If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI clock needs to be at least three times slower than the VCLK. (ECLK) = f(VCLK) / N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the System module. Pipeline mode enabled or disabled is determined by the FRDCNTL[2:0]. 7.1.5.1 Timing - Wait States RAM 0 Address Waitstates 0MHz f(HCLK) Data Waitstates 0 f(HCLK) 0MHz Flash 0 Address Waitstates 1 0MHz Data Waitstates 0 0MHz f(HCLK) 100MHz 2 1 36MHz 72MHz 3 108MHz f(HCLK) Figure 7-3. Wait States NOTE If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not exceeded. The speed of the device clocks may need be derated to accommodate the modulation depth when FMzPLL frequency modulation is enabled. 70 Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 7.2 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 ECLK Specification 7.2.1 Switching Characteristics Over Recommended Operating Conditions For External Clocks Table 7-5. Switching Characteristics Over Recommended Operating Conditions For External Clocks (1) (2) NO. Parameter Test Conditions MIN MAX Unit 3 tw(EOL) Pulse duration, ECLK low under all prescale factor combinations (X and N) 0.5tc(ECLK) – tf ns 4 tw(EOH) Pulse duration, ECLK high under all prescale factor combinations (X and N) 0.5tc(ECLK) – tr ns (1) (2) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the VBUS interface clock divider ratio determined by the CLKCNTL.[19:16] bits in the SYS module. N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the System module. 4 ECLK 3 Figure 7-4. ECLK Timing Diagram Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 71 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.3 www.ti.com RST And PORRST Timings 7.3.1 Timing Requirements For PORRST Table 7-6. Timing Requirements For PORRST NO. MIN VCCPORL VCC low supply level when PORRST must be active during power up VCCPORH VCC high supply level when PORRST must remain active during power up and become active during power down VCCIOPORL VCCIO / VCCP low supply level when PORRST must be active during power up VCCIOPORH VCCIO / VCCP high supply level when PORRST must remain active during power up and become active during power down VIL(PORRST) Low-level input voltage of PORRST VCCIO > 2.5V Unit 0.5 V 1.35 V 1.1 V 3 V 0.2 VCCIO Low-level input voltage of PORRST VCCIO< 2.5V (1) MAX 0.5 V V 3 tsu(PORRST) Setup time, PORRST active before VCCIO and VCCP > VCCIOPORL during power up 0 ms 6 th(PORRST) Hold time, PORRST active after VCC > VCCPORH 1 ms 7 tsu(PORRST) Setup time, PORRST active before VCC VCCIOPORH 1 ms 9 th(PORRST) Hold time, PORRST active after VCC < VCCPORL 0 ms tf(PORRST) Filter time PORRST, pulses less than MIN will be filtered out, pulses greater than MAX are guaranteed to generate a reset (1) 20 150 ns tf(RST) Filter time RST, pulses less than MIN will be filtered out, pulses greater than MAX are guaranteed to generate a reset 20 150 ns A low pulse on the nPORRST pin which is just barely longer than the glitch filter implemented on this pin will result in a very short internal reset. This may result in unpredictable behavior as some parts of the device may be reset while other parts of the device are not. 3.3 V VCCIOPORH VCCIOPORH VCCIO / VCCP 8 1.5 V VCCPORH 6 VCC 7 VCCPORH 6 VCCIOPORL 7 VCCPORL VCCPORL VCCIOPORL VCC (1.5 V) 3 PORRST VIL(PORRST) 9 VIL VIL VIL VIL VIL(PORRST) Figure 7-5. PORRST Timing Diagram NOTE There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing. All requirements are to ensure PORRST is active when VCCIO or VCC is out of the normal operating range. 72 Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 7.3.2 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Switching Characteristics Over Recommended Operating Conditions For RST Table 7-7. Switching Characteristics Over Recommended Operating Conditions For RST (1) Parameter tv(RST) Valid time, RST active after PORRST inactive Valid time, RST active (all others) (1) MIN MAX 1048c(OSC) Unit ns 8tc(VCLK) Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load capacitance table. 7.3.3 IO Status During PORRST IO buffer condition during power-on-reset (nPORRST is low): All I/O pins, except nRST, are configured as High-impedance while nPORRST is low and immediately after nPORRST goes high. The FlexRay FRAYTX1 and FRAYTX2 pins are high impedance (high-Z) while nPORRST is low, and are output high at latest 1024 oscillator cycles after nPORRST goes high; the FlexRay FRAYTXEN1 and FRAYTXEN2 pins are high impedance (high-Z) while nPORRST is low, and output high immediately after nPORRST goes high. IO pullup/pulldown condition during power-on-reset: all internal pullups and pulldowns on input pins are disabled when nPORRST is low, and become active immediately after nPORRST goes high. Pins that are listed with "programmable" have programmable pullups or pulldowns. The default value after reset is listed underneath "programmable" in Table 2-9. The exceptions are nPORRST, nRST, nTRST and TEST pins. The pulls on these pins will be active during power-on-reset. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 73 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.4 www.ti.com TEST Pin Timing Table 7-8. TEST Pin Timing NO. Description tf(TEST) 74 Filter time TEST, pulses less than MIN will be filtered out, pulses greater than MAX are guaranteed to enter TEST mode Peripheral and Electrical Specifications MIN MAX Unit 10 80 ns Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 7.5 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 DAP - JTAG Scan Interface Timing 7.5.1 JTAG clock specification 12-MHz and 50-pF load on TDO output Table 7-9. JTAG Scan Interface Timing NO. MIN f(TCK) TCK frequency (at HCLKmax) MAX Unit 12 MHz f(RTCK) RTCK frequency (at TCKmax and HCLKmax) 1 td(TCK -RTCK) Delay time, TCK to RTCK 10 MHz 2 tsu(TDI/TMS - RTCKr) Setup time, TDI, TMS before RTCK rise (RTCKr) 15 ns 3 th(RTCKr -TDI/TMS) Hold time, TDI, TMS after RTCKr 0 ns 4 th(RTCKf -TDO) Hold time, TDO after RTCKf 0 5 td(RTCKf -TDO) Delay time, TDO valid after RTCK fall (RTCKf) 20 ns ns 10 ns Note: The timings in this table are measured with a 50pF and 50µA load. And they are measured at the 50% point, not 20% or 80% point. TCK RTCK 1 1 TMS TDI 2 3 TDO 4 5 Figure 7-6. JTAG timing Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 75 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.6 7.6.1 www.ti.com Output Timings Switching Characteristics For Output Timings Versus Load Capacitance (CL) Table 7-10. Switching Characteristics For Output Timings Versus Load Capacitance (C L) Parameter tr tf tr tf tr tf MIN 8mA pins 8mA pins 4mA pins 4mA pins 2mA-z pins 2mA-z pins MAX Unit CL = 15 pF 2.5 ns CL = 50 pF 5 CL = 100 pF 9 CL = 150 pF 12 CL = 15 pF 2.5 CL = 50 pF 5 CL = 100 pF 9 CL = 150 pF 12 CL = 15 pF 7 CL = 50 pF 13 CL = 100 pF 21 CL = 150 pF 29 CL = 15 pF 7 CL = 50 pF 13 CL = 100 pF 21 CL = 150 pF 29 CL = 15 pF 10 CL = 50 pF 17 CL = 100 pF 25 CL = 150 pF 35 CL = 15 pF 10 CL = 50 pF 17 CL = 100 pF 25 CL = 150 pF 35 tr 20% ns ns ns ns tf 80% Output ns VCCIO 80% 20% 0 Figure 7-7. CMOS-Level Outputs 76 Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 7.7 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Input Timings 7.7.1 Timing Requirements For Input Timings Table 7-11. Timing Requirements For Input Timings (1) MIN tpw (1) (2) MAX tc(VCLK) + 10 (2) Input minimum pulse width Unit ns tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK) The timing shown above is only valid for pin used in GIO mode tpw 80% Input 20% VCCIO 80% 20% 0 Figure 7-8. CMOS-Level Inputs Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 77 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.8 www.ti.com Flash Timings Table 7-12. Timing Requirements For Program Flash MIN NOM MAX Unit tprog(32-bit) Full word (32-bit) programming time 33 300 µs tprog(Total) 2M-byte programming time (1) -40°C to 125°C 17 74 s 0°C to 60°C, for first 25 cycles 17 25 s tprog ECC(16-bit) ECC programming time 33 300 µs tprog Total ECC bit programming time (256kbyte) -40°C to 125°C 4.3 15 s 0°C to 60°C, for first 25 cycles 4.3 7 s Sector erase time (including compaction) -40°C to 125°C ECC(total) terase(sector) terase(bank) twec (1) (2) 78 2 15 s 1.5 10 s Bank erase time (including Bank 0 compaction),0°C to 60°C, Bank 1 for first 25 cycles Bank 2 7.5 20 s 5.5 12 s 5.5 12 s Bank 3 5.5 0°C to 60°C, for first 25 cycles Write/erase cycles at TA = -40 to 125°C with 15 year Data Retention requirement (2) 12 s 1000 cycles This programming time includes overhead of state machine, but does not include data transfer time. Flash write/erase cycles and data retention specifications are based on a validated implementation of the TI flash API. Non-TI flash API implementation is not supported. For detailed description see the F035 Flash Validation Procedure (SPNA127). Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 7.9 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 SPI Master Mode Timing Parameters 7.9.1 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) Table 7-13. SPI Master Mode External Timing Parameters (1) (2) (3) NO. MIN MAX Unit 50 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 3 – tr 0.5tc(SPC)M + 5 ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 3 – tf 0.5tc(SPC)M + 5 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 3 – tf 0.5tc(SPC)M + 5 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 3 – tr 0.5tc(SPC)M + 5 td(SIMO-SPCL)M Delay time, SPISIMO valid before SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 td(SIMO-SPCH)M Delay time, SPISIMO valid before SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC) -7 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC) -7 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) tf(SPC) tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) tr(SPC) + 4 th(SPCL-SOMI)M Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) 10 th(SPCH-SOMI)M Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) 10 tC2TDELAY Setup time CS active until SPICLK high, assumes that SPInENA is low at tSPIENA (clock polarity = 0) (C2TDELAY+CSHOLD+ 2)*tc(VCLK) - tf(SPICS) + tr(SPC)- 9 (C2TDELAY+CSHOLD+ 2)*tc(VCLK) - tf(SPICS) + tr(SPC)+ 5 ns Setup time CS active until SPICLK low, assumes that SPInENA is low at tSPIENA (clock polarity = 1) (C2TDELAY+CSHOLD+ 2)*tc(VCLK) - tf(SPICS) + tf(SPC) - 9 (C2TDELAY+CSHOLD+ 2)*tc(VCLK) - tf(SPICS) + tf(SPC) + 5 ns Hold time SPICLK low until CS inactive (clock polarity = 0) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) tf(SPC) + tr(SPICS) - 5 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) tf(SPC) + tr(SPICS) + 10 ns Hold time SPICLK high until CS inactive (clock polarity = 1) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) tr(SPC) + tr(SPICS) - 5 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) tr(SPC) + tr(SPICS) + 10 ns C2TDELAY * tc(VCLK) tf(SPICS) - 20 C2TDELAY * tc(VCLK) ns (C2TDELAY+2)*tc(VCLK) ns 1 tc(SPC)M Cycle time, SPICLK 2 (5) tw(SPCH)M 3 (5) 4 (5) 5 (5) 6 (5) 7 (5) 8 (6) 9 (6) tT2CDELAY (4) 10 tSPIENA SPIENAn Sample point 11 tSPIENAW SPIENAn Sample point from write to buffer (1) (2) (3) (4) (5) (6) ns ns ns ns ns The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set. tc(VCLK) = interface clock cycle time = 1 / f(VCLK) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 50 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 50 ns. The external load on the SPICLK pin must be less than 60pF. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). C2TDELAY and T2CDELAY are programmed in the SPIDELAY register Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 79 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISIMO Master Out Data Is Valid 6 7 Master In Data Must Be Valid SPISOMI Figure 7-9. SPI Master Mode External Timing (CLOCK PHASE = 0) Write to buffer SPICLK (clock polarity = 0) SPICLK (clock polarity = 1) SPISIMO Master Out Data Is Valid 8 9 SPICSn 10 11 SPIENAn Figure 7-10. SPI Master Mode Chip Select timing (CLOCK PHASE = 0) 80 Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com 7.9.2 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) Table 7-14. SPI Master Mode External Timing Parameters (1) (2) (3) NO. Unit 256tc(VCLK) ns Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 3 – tr 0.5tc(SPC)M + 5 ns Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 3 – tf 0.5tc(SPC)M + 5 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 3 – tr 0.5tc(SPC)M + 5 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 3 – tf 0.5tc(SPC)M + 5 td(SIMO-SPCH)M Delay time, SPICLK high after SPISIMO data valid(clock polarity = 0) 0.5tc(SPC)M – 10 td(SIMO-SPCL)M Delay time, SPICLK low after SPISIMO data valid (clock polarity = 1) 0.5tc(SPC)M – 10 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high(clock polarity = 0) 0.5tc(SPC)M – tr(SPC) – 7 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low(clock polarity = 1) 0.5tc(SPC)M – tf(SPC) – 7 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) tr(SPC)+4 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) tf(SPC) tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 10 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 10 tC2TDELAY Setup time CS active until SPICLK high, assumes that SPInENA is low at tSPIENA (clock polarity = 0) (C2TDELAY+CSHOLD+ (C2TDELAY+CSHOLD+ 2)*tc(VCLK) +0.5*tc(SPC)M - 2)*tc(VCLK) +0.5*tc(SPC)M tf(SPICS) + tr(SPC) - 9 tf(SPICS) + tr(SPC) + 5 ns Setup time CS active until SPICLK low, assumes that SPInENA is low at tSPIENA (clock polarity = 1) (C2TDELAY+CSHOLD+ 2)*tc(VCLK) + 0.5*tc(SPC)M - tf(SPICS) + tf(SPC) - 9 (C2TDELAY+CSHOLD+ 2)*tc(VCLK) + 0.5*tc(SPC)M - tf(SPICS) + tf(SPC) + 5 ns Hold time SPICLK low until CS inactive (clock polarity = 0) T2CDELAY*tc(VCLK) + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) tc(VCLK) - tf(SPC) + tr(SPICS) -5 + 10 ns Cycle time, SPICLK (5) tw(SPCH)M tw(SPCL)M 3 (5) 4 (5) 5 (5) 6 (5) 7 (5) 8 (6) 9 (6) (5) (6) MAX 50 tc(SPC)M 2 (1) (2) (3) (4) MIN 1 tT2CDELAY (4) ns ns ns ns ns Hold time SPICLK high until CS inactive (clock polarity = 1) T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS)- 5 T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS)+ 10 ns C2TDELAY * tc(VCLK) tf(SPICS)- 20 C2TDELAY * tc(VCLK) ns (C2TDELAY+2)*tc(VCLK) ns 10 tSPIENA SPIENAn Sample Point 11 tSPIENAW SPIENAn Sample point from write to buffer The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set. tc(VCLK) = interface clock cycle time = 1 / f(VCLK) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 50 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 50 ns. The external load on the SPICLK pin must be less than 60pF. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). C2TDELAY and T2CDELAY are programmed in the SPIDELAY register Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 81 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 Data Valid Master Out Data Is Valid SPISIMO 6 7 Master In Data Must Be Valid SPISOMI Figure 7-11. SPI Master Mode External Timing (CLOCK PHASE = 1) Write to buffer SPICLK (clock polarity = 0) SPICLK (clock polarity = 1) SPISIMO Master Out Data Is Valid 8 9 SPICS 10 11 SPIENA Figure 7-12. SPI Master Mode Chip Select timing (CLOCK PHASE = 1) 82 Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.10 SPI Slave Mode Timing Parameters 7.10.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output) Table 7-15. SPI Slave Mode External Timing Parameters NO. 1 2 (5) 3 (5) 4 (5) 5 (5) 6 (5) 7 (5) 8 9 (1) (2) (3) (4) (5) (1) (2) (3) MIN MAX Unit tc(SPC)S Cycle time, SPICLK (4) 90 ns tw(SPCH)S Pulse duration, SPICLK high(clock polarity = 0) 30 ns tw(SPCL)S Pulse duration, SPICLK low(clock polarity = 1) 30 tw(SPCL)S Pulse duration, SPICLK low(clock polarity = 0) 30 tw(SPCH)S Pulse duration, SPICLK high(clock polarity = 1) 30 td(SPCH-SOMI)S Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) trf(SOMI) + 15 td(SPCL-SOMI)S Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) trf(SOMI) + 15 tV(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity =0) 0 tV(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity =1) 0 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low(clock polarity = 0) 4 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high(clock polarity = 1) 4 th(SPCL-SIMO)S Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0) 6 th(SPCH-SIMO)S Hold time, SPISIMO data valid after S PICLK high (clock polarity = 1) 6 td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+ 26 td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+ 26 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK) + tf(ENAn)+ 18 ns ns ns ns ns ns ns The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set. tc(VCLK) = interface clock cycle time = 1 /f(VCLK) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. When the SPI is in Slave mode, the following must be true: tc(SPC)S > 2tc(VCLK) and tc(SPC)S>= 90 ns. tw(SPCH)S > tc(VCLK) and tw(SPCL)S > tc(VCLK). The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 83 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 5 4 SPISOMI Data Is Valid SPISOMI 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 7-13. SPI Slave Mode External Timing (CLOCK PHASE = 0) SPICLK (clock polarity = 0) SPICLK (clock polarity = 1) 8 SPIENAn 9 SPICSn Figure 7-14. SPI Slave Mode Enable Timing (CLOCK PHASE = 0) 84 Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.10.2 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output) Table 7-16. SPI Slave Mode External Timing Parameters (1) (2) (3) NO. MIN Cycle time, SPICLK (4) 90 ns (5) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 30 ns tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 30 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 30 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 30 td(SOMI- Delay time, SPISOMI data valid after SPICLK low (clock polarity = 0) trf(SOMI)+15 Delay time, SPISOMI data valid after SPICLK high (clock polarity = 1) trf(SOMI)+15 3 (5) 4 (5) SPCL)S td(SOMISPCH)S 5 (5) tV(SPCLSOMI)S tV(SPCHSOMI)S 6 (5) tsu(SIMOSPCH)S tsu(SIMOSPCL)S 7 (5) th(SPCHSIMO)S th(SPCLSIMO)S 8 td(SPCHSENAH)S td(SPCLSENAH)S 9 td(SCSLSENAL)S 10 td(SCSLSOMI)S (5) Unit tc(SPC)S 2 (1) (2) (3) (4) MAX 1 ns ns Valid time, SPISOMI data valid after SPICLK high (clock polarity =0) 0 ns Valid time, SPISOMI data valid after SPICLK low (clock polarity =1) 0 Setup time, SPISIMO before SPICLK high (clock polarity = 0) 4 Setup time, SPISIMO before SPICLK low (clock polarity = 1) 4 Hold time, SPISIMO data valid after SPICLK high (clock polarity = 0) 6 Hold time, SPISIMO data valid after SPICLK low (clock polarity = 1) 6 Delay time, SPIENAn high after last SPICLK high (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+ 26 Delay time, SPIENAn high after last SPICLK low (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+ 26 Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK) + tf(ENAn)+ 18 ns Delay time, SOMI valid after SPICSn low (if new data has been written to the SPI buffer) tc(VCLK) 2tc(VCLK) + trf(SOMI)+ 20 ns ns ns ns The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set. tc(VCLK) = interface clock cycle time = 1 /f(VCLK) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. When the SPI is in Slave mode, the following must be true: tc(SPC)S > 2tc(VCLK) and tc(SPC)S>= 90 ns. tw(SPCH)S > tc(VCLK) and tw(SPCL)S > tc(VCLK). The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 85 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 Data Valid SPISOMI Data Is Valid SPISOMI 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 7-15. SPI Slave Mode External Timing (CLOCK PHASE = 1) SPICLK (clock polarity = 0) SPICLK (clock polarity = 1) 8 SPIENAn 9 SPICSn 10 SPISOMI Slave Out Data Is Valid Figure 7-16. SPI Slave Mode Enable Timing (CLOCK PHASE = 1) 86 Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.11 CAN Controller Mode Timings 7.11.1 Dynamic Characteristics For The CANnTX And CANnRX Pins Table 7-17. Dynamic Characteristics For The CANnTX And CANnRX Pins Parameter (1) MAX Unit td(CANnTX) Delay time, transmit shift register to CANnTX pin (1) MIN 15 ns td(CANnRX) Delay time, CANnRX pin to receive shift register 5 ns These values do not include rise/fall times of the output buffer. 7.12 SCI/LIN Mode Timings At 100MHz Peripheral Clock, 3.125 Mbits/s is the Max SCI Baud Rate achievable. 7.13 FlexRay Controller Mode Timings 7.13.1 Jitter Timing Table 7-18. Jitter Timing MIN MAX Unit tTx1bit clock jitter and signal symmetry Parameter 98 102 ns tTx10bit FlexRay BSS (byte start sequence) to BSS 999 1001 ns tTx10bitAvg average over 10000 samples 999.5 1000.5 ns tRxAsymDelay delay difference between rise and fall from Rx pin to sample point in FlexRay core - 2.5 ns Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 87 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 7.14 EMIF Timings Table 7-19. EMIF Read/Write Mode Switching Characteristics (1) (2) NO Parameter Description MIN MAX Unit (TA + 1) * E tr(CS) - 2 (TA + 1) * E tr(CS) + 3 ns (RS + RST + RH + TA +4) * E - tf(CS) - 3 (RS + RST + RH + TA +4) * E - tf(CS) + 3 ns Reads and Writes 1 td(TURNAROUND) Turn around time Reads 2 tc(EMRCYCLE) 3 tsu(EMCSL-EMOEL) Output setup time, EMIFCS[3:0] low to EMIFOE low (SS=0) (RS +1) * E tf(CS) + tf(OE) - 5 (RS +1) * E tf(CS) + tf(OE) + 5 ns Output setup time, EMIFCS[3:0] low to EMIFOE low (SS=1) - tf(CS) + tf(OE) 5 - tf(CS) + tf(OE) + 5 ns Output hold time, EMIFOE high to EMIFCS[3:0] high (SS=0) (RH +1) * E (RH +1) * E tr(OE) + tr(CS) - 4 tr(OE) + tr(CS) + 6 ns Output hold time, EMIFOE high to EMIFCS[3:0] high (SS=1) - tr(OE) + tr(CS) 4 - tr(OE) + tr(CS) + 6 ns (RS +1) * E trf(AD) + tf(OE) - 5 (RS +1) * E trf(AD) + tf(OE) + 5 ns (RH +1) * E tr(OE) - 5 (RH +1) * E tr(OE) + 5 ns (RS +1) * E trf(AD) + tf(OE) - 6 (RS +1) * E trf(AD) + tf(OE) + 6 ns 4 th(EMOEH-EMCSH) EMIF read cycle time 5 tsu(EMBAV-EMOEL) Output setup time, EMIFBADD[1:0] valid to EMIFOE low 6 th(EMOEH-EMBAIV) Output hold time, EMIFOE high to EMIFBADD[1:0] invalid 7 tsu(EMAV-EMOEL) Output setup time, EMIFADD[21:0] valid to EMIFOE low 8 th(EMOEH-EMAIV) Output hold time, EMIFOE high to EMIFADD[21:0] invalid (RH +1) * E tr(OE) - 5 (RH +1) * E tr(OE) + 6 ns 9 tw(EMOEL) EMIFOE active low width (RST +1) * E tf(OE) - 1 (RST +1) * E tf(OE) + 0 ns 10 tsu(EMDV-EMOEH) Setup time, EMIFD[15:0] valid before EMIFOE high tr(OE) + 9 11 th(EMOEH-EMDV) Hold time, EMIFD[15:0] valid after EMIFOE high - tr(OE) - 3 ns Writes 12 tc(EMWCYCLE) 13 tsu(EMCSL-EMWEL) Output setup time, EMIFCS[3:0] low to EMIFWE low (SS=0) 14 (1) (2) 88 EMIF write cycle time (WS + WST + WH + TA +4) * E - tf(CS) + 2 ns (WS +1) * E (WS +1) * E tf(CS) + tf(WE) - 5 tf(CS) + tf(WE) + 5 ns Output setup time, EMIFCS[3:0] low to EMIFWE low (SS=1) - tf(CS) + tf(WE) 5 - tf(CS) + tf(WE) + 5 ns th(EMWEH-EMCSH) Output hold time, EMIFWE high to EMIFCS[3:0] high (SS=0) (WH +1) * E tr(WE) + tr(CS) - 4 (WH +1) * E tr(WE) + tr(CS) + 5 ns Output hold time, EMIFWE high to EMIFCS[3:0] high (SS=1 - tr(WE) + tr(CS) 4 - tr(WE) + tr(CS) + 5 ns (WS +1) * E trf(AD) + tf(WE) - 5 (WS +1) * E trf(AD) + tf(WE) + 5 ns (WH +1) * E tr(WE) - 5 (WH +1) * E tr(WE) + 5 ns (WS +1) * E trf(AD) + tf(WE) - 6 (WS +1) * E trf(AD) + tf(WE) + 6 ns 15 tsu(EMBAV-EMWEL) Output setup time, EMIFBADD[1:0] valid to EMIFWE low 16 th(EMWEH-EMBAIV) Output hold time, EMIFWE high to EMBADD[1:0] invalid 17 tsu(EMAV-EMWEL) Output setup time, EMIFADD[21:0] valid to EMIFWE low (WS + WST + WH + TA +4) * E - tf(CS) - 3 RS = Read setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold, TA = Turn Around, SS= Strobe Select Mode E = VCLK period in ns. Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 Table 7-19. EMIF Read/Write Mode Switching Characteristics(1)(2) (continued) NO Parameter MIN MAX Unit 18 th(EMWEH-EMAIV) Output hold time, EMIFWE high to EMIFADD[21:0] invalid Description (WH +1) * E tr(WE) - 5 (WH +1) * E tr(WE) + 6 ns 19 tw(EMWEL) EMIFWE active low width (WST +1) * E tf(WE) - 1 (WST +1) * E tf(WE) + 1 20 tsu(EMDV-ENWEL) Output setup time, EMIFD[15:0] valid to EMIFWE low (WS +1) * E trf(DA) + tf(WE) - 6 (WS +1) * E trf(DA) + tf(WE) + 5 ns 21 th(EMWEH-EMDIV) Output hold time, EMIFD[15:0] valid after EMIFWE high (WH +1) * E tr(WE) - 5 (WH +1) * E tr(WE) + 5 ns 7.14.1 Read Timing (Asynchronous RAM) 2 1 EMIFCS[3:0] EMIFR/W EMIFBADD[1:0] EMIFADD[21:0] 8 6 4 3 5 7 9 EMIFOE 11 10 EMIFD[15:0] EMIFWE Figure 7-17. Asynchronous Memory Read Timing for EMIF Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 89 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 7.14.2 Write Timing (Asynchronous RAM) 12 1 EMIFCS[3:0] EMIFBADD[1:0] EMIFADD[21:0] 13 15 17 16 18 14 19 EMIFWE 20 21 EMIFD[15:0] EMIFOE Figure 7-18. Asynchronous Memory Write Timing for EMIF 7.15 ETM Timings 7.15.1 ETMTRACECLK Timing t(ETM)l t(ETM)h t(ETM)r t(ETM)f t(ETM)cyc Figure 7-19. ETMTRACECLK Timing Table 7-20. ETMTRACECLK Timing Parameter Minimum f(ETM)cyc 90 t(ETM)cyc 25ns Maximum Description 40MHz Clock frequency Clock period t(ETM)l 2ns Low pulse width t(ETM)h 2ns High pulse width t(ETM)r 3ns Clock and data rise time t(ETM)f 3ns Clock and data fall time Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.15.2 ETMDATA Timing ETMTRACECLK ETMDATA t(ETM)su t(ETM)ho t(ETM)su t(ETM)ho Figure 7-20. ETMDATA Timing Table 7-21. ETMDATA Timing Parameter Typical Description t(ETM)su 2.5ns Data setup time t(ETM)ho 1.5ns Data hold time Note: The timings in this table are measured with a 50pF and 50µA load. And they are measured at the 50% point, not 20% or 80% point. 'Typical' means 25°C and nominal voltage. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 91 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 7.16 RTP Timings 7.16.1 RTPCLK Timing t(RTP)l tr t(RTP)h tf t(RTP)cyc Figure 7-21. RTPCLK Timing Table 7-22. RTPCLK Timing Parameter Minimum Description t(RTP)cyc 10 ns Clock period (depending on HCLK divide ratio) t(RTP)h (t(RTP)cyc/2) - ((tr+tf)/2) -1.5 High pulse width (depending on HCLK divide ratio and load on pin) t(RTP)l (t(RTP)cyc/2) - ((tr+tf)/2) -1.5 Low pulse width (depending on HCLK divide ratio and load on pin) 7.16.2 RTPDATA Timing t(RTP)ssu t(RTP)sho RTPSYNC RTPCLK RTPDATA t(RTP)dsu t(RTP)dho Figure 7-22. RTPDATA Timing Table 7-23. RTPDATA Timing Parameter Minimum Description t(RTP)dsu 0.5 t(RTP)cyc-3ns Data setup time t(RTP)dho 0.5 t(RTP)cyc-2ns Data hold time t(RTP)ssu 0.5 t(RTP)cyc-3ns SYNC setup time t(RTP)sho 0.5 t(RTP)cyc-2ns SYNC hold time Note: The timings in this table are measured with a 50pF and 50µA load. And they are measured at the 50% point, not 20% or 80% point. 92 Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.16.3 RTPENABLE Timing t(RTP)enable t(RTP)enable tt(RTP)disable (RTP)disable 1 2 3 4 5 d1 d2 d3 6 7 8 9 10 11 12 13 14 15 16 HCLK RTPCLK RTPENA RTPSYNC RTPDATA RTPDATA d5 d4 d6 d7 d8 Divide by 1 Figure 7-23. RTPENABLE Timing Table 7-24. RTPENABLE Timing Parameter Minimum t(RTP)disable 1.5tc(HCLK) + tr(RTPSYNC) + 12ns t(RTP)enable 4.5tc(HCLK) + tr(RTPSYNC) Maximum Description Time that RTPENA must go high before the next scheduled RTPSYNC in order to suspend transmission for the packet following the scheduled RTPSYNC. 5.5tc(HCLK) + tr(RTPSYNC) + 12ns Time after RTPENA goes low before a packet that has been halted, resumes. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 93 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 7.17 DMM Timings 7.17.1 DMMCLK Timing t(DMM)l tr tf t(DMM)h t(DMM)cyc Figure 7-24. DMMCLK Timing Table 7-25. DMMCLK Timing Parameter Minimum Description t(DMM)cyc tc(HCLK) * 2 Clock period t(DMM)h t(DMM)cyc/2-(tr+tf)/2 High pulse width t(DMM)l t(DMM)cyc/2-(tr+tf)/2 Low pulse width 7.17.2 DMMDATA Timing t(DMM) ssu t(DMM) sho DMMSYNC DMMCLK DMMDATA t(DMM) dsu t(DMM)dho Figure 7-25. DMMDATA Timing Table 7-26. DMMDATA Timing 94 Parameter Minimum Description t(DMM)ssu 2ns SYNC active to clk falling edge setup time t(DMM)sho 3ns clk falling edge to SYNC deactive hold time t(DMM)dsu 2ns DATA to clk falling edge setup time t(DMM)dho 3ns clk falling edge to DATA hold time Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.17.3 DMMENA Timing HCLK DMMCLK DMMSYNC DMMDATA D00 D01 D10 D11 D20 D21 D30 D31 D40 D41 D50 DMMENA Figure 7-26. DMMENA Timing The above figure shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data width = 8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to filling up of the internal buffers. The DMMENA signal is shown asserted, after the first two packets have been received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets D4, D5, D6, D7. Packet D8 would result in an overflow. Once DMMENA is asserted, the DMM expects to stop receiving packets after 4 HCLK cycles; once DMMENA is de-asserted, the DMM can handle packets immediately (after 0 HCLK cycles). 7.18 MibADC 7.18.1 MibADC The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO unless otherwise noted. Table 7-27. MibADC Resolution 12 bits (4096 values) Monotonic Assured 00h to FFFh [00 for VAI ≤ADREFLO; FFF for VAI ≥ ADREFHI] Output conversion φcode 7.18.2 MibADC Recommended Operating Conditions Table 7-28. MibADC Recommended Operating Conditions (1) MIN MAX UNIT ADREFHI A-to-D high-voltage reference source 3 3.6 V ADREFLO A-to-D low-voltage reference source 0 0.3 V VAI Analog input voltage ADREFLO ADREFHI V IAIC Analog input clamp current (2) (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3) -2 2 mA (1) (2) For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table. Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 95 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 7.18.3 Operating Characteristics Over Full Ranges Of Recommended Operating Conditions Table 7-29. Operating Characteristics Over Full Ranges Of Recommended Operating Conditions (1) Parameter Rmux Analog input mux onresistance Rsamp ADC sample switch onresistance Cmux Input mux capacitance Csamp ADC sample capacitance 96 Min TYP 150 11 12 Max Unit 250 Ω 250 Ω 16 pF 13 pF –200 200 nA 5 mA 3 3.6 V IAIL Analog input leakage current Input leakage per ADC input pin IADREFHI ADREFHI input current ADREFHI = 3.6 V, ADREFLO = VSSAD Conversion range over which specified accuracy is maintained ADREFHI - ADREFLO EDNL Differential nonlinearity error Difference between the actual step width and the ideal value. ±2 LSB EINL Integral nonlinearity error Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error. ±2 LSB ETOT Total error/Absolute accuracy Maximum value of the difference between an analog value and the ideal midstep value. ± 4 (2) LSB ±8 LSB CR (1) (2) Description/Conditions Executing periodic internal calibration No calibration 1 LSB = (ADREFHI – ADREFLO)/ 212 for the MibADC An periodic internal offset calibration is required to achieve the absolute accuracy. Please refer to the Analog To Digital Converter (ADC) Module chapter of the TMS570LS Series Microcontroller Technical Reference Manual (SPNU489) and Interfacing the Embedded 12-bit ADC (SPNA129) for more information. Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.18.4 MibADC Input Model Pin Pin Smux Rmux Smux IAIL Pin Smux IAIL Rmux IAIL Rmux IAIL Ssamp Rsamp Cmux Csamp Figure 7-27. MibADC Input Equivalent Circuit Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 97 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 7.18.5 MibADC Timings Table 7-30. MibADC Timings Min NOm MAX Unit tc(ADCLK) Cycle time, MibADC clock 33 ns td(SH) Delay time, sample and hold time 200 ns td©) Delay time, conversion time 400 ns td(SHC) (1) Delay time, total sample/hold and conversion time 600 ns (1) 98 This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the prescale settings. Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 7.18.6 MibADC Nonlinearity Error The differential nonlinearity error shown in the figure below (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB. 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 0 ... 011 Differential Linearity Error (1/2 LSB) 1 LSB 0 ... 010 0 ... 001 Differential Linearity Error (–1/2 LSB) 1 LSB 0 ... 000 0 1 2 3 4 Analog Input Value (LSB) 5 Figure 7-28. Differential Nonlinearity (DNL) The integral nonlinearity error shown in the figure below (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. 0 ... 111 Digital Output Code 0 ... 110 Ideal Transition 0 ... 101 Actual Transition 0 ... 100 At Transition 011/100 (– 1/2 LSB) 0 ... 011 0 ... 010 End-Point Lin. Error 0 ... 001 At Transition 001/010 (– 1/4 LSB) 0 ... 000 0 1 2 3 4 5 6 7 Analog Input Value (LSB) Figure 7-29. Integral Nonlinearity (INL) Error Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 99 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 7.18.7 MibADC Total Error The absolute accuracy or total error of an MibADC as shown in the figure below is the maximum value of the difference between an analog value and the ideal midstep value. 0 ... 111 Digital Output Code 0 ... 110 0 ... 101 0 ... 100 Total Error At Step 0 ... 101 (–1 1/4 LSB) 0 ... 011 0 ... 010 Total Error At Step 0 ... 001 (1/2 LSB) 0 ... 001 0 ... 000 0 1 2 3 4 5 Analog Input Value (LSB) 6 7 Figure 7-30. Absolute Accuracy (Total) Error 100 Peripheral and Electrical Specifications Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 8 Revision History This data sheet revision history highlights the technical changes made to the device or the datasheet. Date Additions, Deletions, And Modifications March 2010 June 2010 Updated Memory Map section. Updated the MibADC Input Equivalent Circuit illustration. Revision A B Updated the ZWT Package Pinout illustration. August 2010 Updated the RTPDATA timing diagram. October 2010 Added notes of speculative fetches on flash ECC and Ram ECC. Updated the current consumption with characterization data. C Updated the timing requirement with characterization data. Added RCLK, test pin parameters, fixed the SPI timing fomulas. January 2011 July 2011 Updated the datasheet with characterization data. TMS release. D Updated DMA Channel control packets numbers. Switched description of SPI1CS and SPI1CLK. Switched description of SPI3CS and SPI3CLK. F Added table note to table 2-7 to specify the test clock for different RAMs. Modified the table note for table 7-6 to address Errata AnalogIP_F035.BTS_VMON _F035_33.2. October 2018 Removed all references to the SIL3 certification. Since this product is not recommended for new designs, Texas Instruments has chosen not to renew the SIL3 certification. No changes have been made to form, fit or function of this part. G Revision History Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 Copyright © 2010–2018, Texas Instruments Incorporated 101 Not Recommended for New Designs TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 SPNS141G – AUGUST 2010 – REVISED OCTOBER 2018 www.ti.com 9 Mechanical Packaging and Orderable Information The following table(s) show the thermal resistance for the PBGA-ZWT and PQFP-PGE mechanical packages. 9.1 9.1.1 Thermal Data PGE (S-PQFP-G144) plastic Quad Flat Pack Table 9-1. PGE (S-PQFP-G144) Thermal Resistance Characteristics 9.1.2 PARAMETER °C / W RΘJA 45 RΘJC 5 ZWT (S-PBGA-N337) Plastic ball grid array Table 9-2. ZWT (S-PBGA-N337) Thermal Resistance Characteristics PARAMETER 9.2 °C / W RΘJA 22 RΘJC 3.3 Packaging Information The following packaging information and addendum reflect the most current data available for the designated device(s). The data is subject to change without notice and without revision of this document. 102 Mechanical Packaging and Orderable Information Copyright © 2010–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) S5LS10106ASPGEQQ1 NRND LQFP PGE 144 60 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 10106ASPGEQQ1 TMS570LS S5LS10106ASZWTQQ1 NRND NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 LS10106ASZWTQQ1 S5LS10116ASPGEQQ1 NRND LQFP PGE 144 60 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 10116ASPGEQQ1 TMS570LS S5LS10116ASZWTQQ1 NRND NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 LS10116ASZWTQQ1 S5LS10206ASPGEQQ1 NRND LQFP PGE 144 60 TBD Call TI Call TI -40 to 125 S5LS10206ASZWTQQ1 NRND NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 LS10206ASZWTQQ1 S5LS10216ASPGEQQ1 NRND LQFP PGE 144 60 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 10216ASPGEQQ1 TMS570LS S5LS10216ASZWTQQ1 NRND NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 LS10216ASZWTQQ1 S5LS20206ASPGEQQ1 NRND LQFP PGE 144 60 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 20206ASPGEQQ1 TMS570LS S5LS20206ASPGEQQ1R NRND LQFP PGE 144 500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 20206ASPGEQQ1 TMS570LS S5LS20206ASZWTQQ1 NRND NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 LS20206ASZWTQQ1 S5LS20216ASPGEQQ1 NRND LQFP PGE 144 60 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 20216ASPGEQQ1 TMS570LS S5LS20216ASZWTQQ1 NRND NFBGA ZWT 337 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 125 TMS570 LS20216ASZWTQQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of