SN74ALVCH162244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES065F – JANUARY 1996 – REVISED OCTOBER 2004
FEATURES
•
•
•
•
•
•
•
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR.
DESCRIPTION
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.
The SN74ALVCH162244 is designed specifically to
improve the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and
undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162244 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2004, Texas Instruments Incorporated
SN74ALVCH162244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES065F – JANUARY 1996 – REVISED OCTOBER 2004
LOGIC SYMBOL(1)
1OE
2OE
1
48
25
3OE
4OE
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
24
47
EN1
EN2
EN3
EN4
1
1
2
46
3
44
5
43
6
41
8
40
1
2
9
38
11
37
12
36
35
1
3
13
14
33
16
32
17
30
19
1
4
29
20
27
22
26
23
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
SN74ALVCH162244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES065F – JANUARY 1996 – REVISED OCTOBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
-0.5
4.6
V
range (2)
-0.5
4.6
V
-0.5
VCC + 0.5
VI
Input voltage
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
V
-50
mA
-50
mA
±50
mA
±100
mA
DGG package
89
DL package
94
-65
UNIT
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
3
SN74ALVCH162244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES065F – JANUARY 1996 – REVISED OCTOBER 2004
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
4
V
0
VCC
V
0
VCC
V
VCC = 1.65 V
-2
VCC = 2.3 V
-6
VCC = 2.7 V
-8
mA
-12
VCC = 1.65 V
2
VCC = 2.3 V
6
VCC = 2.7 V
8
VCC = 3 V
(1)
V
0.35 × VCC
VCC = 3 V
IOL
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
mA
12
-40
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH162244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES065F – JANUARY 1996 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
VOH
1.65 V to 3.6 V
1.65 V
1.2
IOH = -4 mA
2.3 V
1.9
2.3 V
1.7
3V
2.4
IOH = -8 mA
2.7 V
2
IOH = -12 mA
3V
2
IOL = 100 µA
II(hold)
1.65 V to 3.6 V
0.2
1.65 V
0.45
IOL = 4 mA
2.3 V
0.4
2.3 V
0.55
3V
0.55
IOL = 8 mA
2.7 V
0.6
IOL = 12 mA
3V
0.8
±5
VI = VCC or GND
3.6 V
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
-25
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
VI = 0.8 V
3V
75
3V
-75
VI = 2 V
UNIT
V
IOL = 2 mA
IOL = 6 mA
II
MAX
VCC - 0.2
IOH = -2 mA
IOH = -6 mA
VOL
MIN TYP (1)
VCC
V
µA
µA
VI = 0 to 3.6 V (2)
3.6 V
±500
IOZ
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND,
IO = 0
3.6 V
40
µA
One input at VCC - 0.6 V,
Other inputs at VCC or GND
750
µA
∆ICC
Ci
Co
(1)
(2)
Control inputs
Data inputs
Outputs
3 V to 3.6 V
VI = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
3
pF
6
7
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
tpd
A
Y
ten
OE
PARAMETER
tdis
(1)
OE
TYP
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
UNIT
MIN
MAX
MIN MAX
(1)
1
4.9
4.7
1
4.2
ns
Y
(1)
1
6.8
6.7
1
5.6
ns
Y
(1)
1
6.3
5.7
1
5.5
ns
This information was not available at the time of publication.
5
SN74ALVCH162244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES065F – JANUARY 1996 – REVISED OCTOBER 2004
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd Power dissipation capacitance
(1)
6
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF,
This information was not available at the time of publication.
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
16
19
(1)
4
5
UNIT
pF
SN74ALVCH162244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES065F – JANUARY 1996 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
1 kΩ
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
7
SN74ALVCH162244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES065F – JANUARY 1996 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
500 Ω
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
SN74ALVCH162244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES065F – JANUARY 1996 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Open
GND
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
Input
1.5 V
1.5 V
1.5 V
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
2.7 V
1.5 V
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3V
1.5 V
VOL + 0.3 V
VOL
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
1.5 V
VOH − 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SN74ALVCH162244DGG
ACTIVE
TSSOP
DGG
48
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
ALVCH162244
Samples
SN74ALVCH162244DL
ACTIVE
SSOP
DL
48
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH162244
Samples
SN74ALVCH162244DLR
ACTIVE
SSOP
DL
48
1000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH162244
Samples
SN74ALVCH162244GR
ACTIVE
TSSOP
DGG
48
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH162244
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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