SN74ALVCH162373GR

SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A – JULY 2004 – REVISED OCTOBER 2004 FEATURES • • • • • DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE DESCRIPTION/ORDERING INFORMATION This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH162373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and undershoot. ORDERING INFORMATION PACKAGE (1) TA (1) TOP-SIDE MARKING SN74ALVCH162373DL Tape and reel SN74ALVCH162373LR TSSOP - DGG Tape and reel SN74ALVCH162373GR ALVCH162373 VFBGA - GQL Tape and reel SN74ALVCH162373KR VH2373 SSOP - DL -40°C to 85°C ORDERABLE PART NUMBER Tube ALVCH162373 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A – JULY 2004 – REVISED OCTOBER 2004 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. XXX GQL PACKAGE (TOP VIEW) 1 2 3 4 5 XXX TERMINAL ASSIGNMENTS (1) 6 1 2 3 4 5 6 A 1OE NC NC NC NC 1LE B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 VCC VCC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 E F 2Q1 2Q2 2D2 2D1 F G 2Q3 2Q4 GND GND 2D4 2D3 G H 2Q5 2Q6 VCC VCC 2D6 2D5 H J 2Q7 2Q8 GND GND 2D8 2D7 J K 2OE NC NC NC NC 2LE A B C D K (1) NC - No internal connection FUNCTION TABLE (each 8-bit section) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1LE 1D1 1 2OE 48 47 2LE C1 1D To Seven Other Channels Pin numbers shown are for the DGG and DL packages. 2 2 1Q1 24 25 C1 2D1 36 1D To Seven Other Channels 13 2Q1 SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A – JULY 2004 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.6 V VO Output voltage range (2) (3) -0.5 VCC + 0.5 IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 IO Continuous output current Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg (1) (2) (3) (4) mA -50 mA ±50 mA ±100 mA DGG package 70 DL package 63 GQL package 42 Storage temperature range -65 V -50 °C/W °C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) VCC MIN MAX 1.65 3.6 0.65 × VCC VCC VCC = 2.3 V to 2.7 V 1.7 VCC VCC = 2.7 V to 3.6 V 2 VCC VCC = 1.65 V to 1.95 V 0 0.35 × VCC VCC = 2.3 V to 2.7 V 0 0.7 VCC = 2.7 V to 3.6 V 0 0.8 0 VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage VIL Low-level input voltage VO Output voltage IOH High-level output current VCC = 1.65 V -2 VCC = 2.3 V -6 VCC = 2.7 V -8 VCC = 3 V IOL Low-level output current Input transition rise or fall rate TA Operating free-air temperature (1) V V V V mA -12 VCC = 1.65 V 2 VCC = 2.3 V 6 VCC = 2.7 V 8 VCC = 3 V ∆t/∆v UNIT mA 12 -40 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A – JULY 2004 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 µA VOH 1.65 V to 3.6 V 1.65 V 1.2 IOH = -4 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = -8 mA 2.7 V 2 IOH = -12 mA 3V 2 IOL = 100 µA II(hold) 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA 2.3 V 0.4 2.3 V 0.55 3V 0.55 IOL = 8 mA 2.7 V 0.6 IOL = 12 mA 3V 0.8 V ±5 VI = VCC or GND 3.6 V VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V -25 VI = 0.7 V 2.3 V 45 VI = 1.7 V 2.3 V -45 VI = 0.8 V 3V 75 3V -75 VI = 2 V UNIT V IOL = 2 mA IOL = 6 mA II TYP (1) MAX VCC - 0.2 IOH = -2 mA IOH = -6 mA VOL MIN µA µA VI = 0 to 3.6 V (2) 3.6 V ±500 IOZ VO = VCC or GND 3.6 V ±10 µA ICC VI = VCC or GND, IO = 0 3.6 V 40 µA One input at VCC - 0.6 V, Other inputs at VCC or GND 750 µA ∆ICC Ci Co (1) (2) Control inputs Data inputs Outputs 3 V to 3.6 V VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V 3 pF 6 7 pF All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V ± 0.15 V MIN MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX tw Pulse duration, LE high or low 3.3 3.3 3.3 3.3 ns tsu Setup time, data before LE↓ 1.1 1.1 1.1 1.1 ns th Hold time, data after LE↓ 1.1 1.1 1.1 1.1 ns 4 SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A – JULY 2004 – REVISED OCTOBER 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) D VCC = 1.8 V ± 0.15 V VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN MAX MIN MAX 1 6.3 1 5.3 1 4.5 1.1 4 1 6.6 1 5.6 1 5 1 4.2 Q LE VCC = 2.5 V ± 0.2 V UNIT MIN MAX ns ten OE Q 1 7.2 1 6.5 1.5 6 1 5 ns tdis OE Q 1 6.5 1 5.6 1.5 5.5 1.4 4.5 ns 0.5 ns tsk(o) 1 0.5 0.5 OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP 20 22 26 6 6.5 8 UNIT pF 5 SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES583A – JULY 2004 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V tw VI Timing Input VM VM VM 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VM VM 0V tPLH Output Control (low-level enabling) tPLZ VLOAD/2 VM tPZH VOH VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPHL VM VI VM tPZL VI Input VOLTAGE WAVEFORMS PULSE DURATION th VI Data Input VM 0V 0V tsu Output VI VM Input Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VOH VM VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SN74ALVCH162373DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162373 Samples SN74ALVCH162373GR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162373 Samples SN74ALVCH162373LR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH162373 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of