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SN74CBT3244
SCDS001O – NOVEMBER 1992 – REVISED SEPTEMBER 2015
SN74CBT3244 Octal FET Bus Switch
1 Features
3 Description
•
•
The SN74CBT3244 device provides eight bits of highspeed TTL-compatible bus switching. The SOIC,
SSOP, TSSOP, and TVSOP packages provide a
standard ’244 device pinout. The low ON-state
resistance of the switch allows connections to be
made with minimal propagation delay. The device is
organized as two 4-bit low-impedance switches with
separate output-enable (OE) inputs.
1
•
•
•
•
•
•
•
High-Bandwidth Data Path (Up to 200 MHz)
Control Inputs Can Be Driven by TTL or 5-V/3.3-V
CMOS Outputs
Low and Flat ON-State Resistance (ron)
Characteristics Over Operating Range
(ron= 5 Ω Typical)
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low Input/Output Capacitance Minimizes Loading
and Signal Distortion
(Cio(OFF) = 6 pF Typical)
Low Power Consumption (ICC = 50 µA Maximum)
VCC Operating Range From 4.5 V to 5 V
Data I/Os Support 0- to 5-V Signaling Levels (0.8
V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Standard ’244-Type Pinout
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74CBT3244RGY
VQFN (20)
3.35 mm x 4.35 mm
SN74CBT3244DW
SOIC (20)
9.97 mm x 12.60 mm
SN74CBT3244DB
SSOP (20)
5.80 mm x 8.55 mm
SN74CBT3244DBQ
SSOP (20)
8.65 mm × 3.90 mm
SN74CBT3244PW
TSSOP (20)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
Multi-Processor Communications
Test and Measurement Systems
Factory Automation Control Boards
Building Automation Control Boards
Simplified Schematic
2
18
1A1
1B1
8
12
1A4
1B4
1
1OE
11
9
2A1
2B1
17
2A4
3
2B4
19
2OE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74CBT3244
SCDS001O – NOVEMBER 1992 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information Package...................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 7
9
Application and Implementation .......................... 8
9.1 Application Information.............................................. 8
9.2 Typical Application ................................................... 8
10 Power Supply Recommendations ....................... 9
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 Device and Documentation Support ................. 11
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
11
13 Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
Changes from Revision N (September 2003) to Revision O
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Pin Configuration and Functions
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1B1
2A4
1B2
2A3
1B3
2A2
1B4
2A1
1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1
VCC
20
2
1
20
19 2OE
18 1B1
2
3
17 2A4
16 1B2
4
5
15 2A3
14 1B3
6
7
13 2A2
12 1B4
8
9
10
11
2A1
1
GND
1OE
1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1
GND
1OE
RGY Package
20-Pin VQFN
Top View
DB, DBQ, DGV, or PW Package
20-Pin SSOP, TVSOP, or TSSOP
Top View
Pin Functions
PIN
NAME
DB, DBQ, DGV, PW, SSOP,
TVSOP,TSSOP, VQFN
I/O
DESCRIPTION
1A1
2
I/O
Transceiver I/O pin
1A2
4
I/O
Transceiver I/O pin
1A3
6
I/O
Transceiver I/O pin
1A4
8
I/O
Transceiver I/O pin
2A1
11
I/O
Transceiver I/O pin
2A2
13
I/O
Transceiver I/O pin
2A3
15
I/O
Transceiver I/O pin
2A4
17
I/O
Transceiver I/O pin
1B1
18
I/O
Transceiver I/O pin
1B2
16
I/O
Transceiver I/O pin
1B3
14
I/O
Transceiver I/O pin
1B4
12
I/O
Transceiver I/O pin
2B1
9
I/O
Transceiver I/O pin
2B2
7
I/O
Transceiver I/O pin
2B3
5
I/O
Transceiver I/O pin
2B4
3
I/O
Transceiver I/O pin
1OE
1
I
Output Enable. When high A and B are disconnected, when Low A and B are connected
2OE
19
I
Output Enable. When high A and B are disconnected, when Low A and B are connected
GND
10
—
Ground
VCC
20
—
Power pin
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SCDS001O – NOVEMBER 1992 – REVISED SEPTEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC
Input voltage, VI
(2)
MIN
MAX
UNIT
–0.5
7
V
7
V
Continuous channel current
–0.5
128
mA
Clamp current, IK (VI/O < 0)
–50
mA
150
°C
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
TA
Operating free-air temperature
(1)
MIN
MAX
4.5
5.5
2
–40
UNIT
V
V
0.8
V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information Package
SN74CBT3244
THERMAL METRIC (1) (2)
RθJA
(1)
(2)
4
Junction-to-ambient thermal resistance
DB
(SSOP)
DBQ
(SSOP)
DGV
(TVSOP)
PW
(TSSOP)
RGY
(VQFN)
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
70
68
92
83
37
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VCC = 4.5 V
II = –18 mA
II
VCC = 5.5 V
VI = 5.5 V or GND
ICC
VCC = 5.5 V
IO = 0,
One input at 3.4 V,
ΔICC (2)
Control inputs
VCC = 5.5 V
Ci
Control inputs
VI = 3 V or 0
Cio(OFF)
VO = 3 V or 0
ron (3)
VCC = 4.5 V
VI = 0 V
MAX
UNIT
–1.2
V
±5
µA
VI = VCC or GND
50
µA
Other inputs at
VCC or GND
3.5
mA
OE = VCC
VI = 2.4 V
(1)
(2)
(3)
MIN TYP (1)
TEST CONDITIONS
3
pF
6
pF
II = 64 mA
5
II = 30 mA
5
7
7
II = 15 mA
10
15
Ω
All typical values are at VCC = 5 V, TA = 25°C.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
ten
OE
A or B
tdis
OE
A or B
tpd (1)
(1)
MIN
TYP
MAX
UNIT
0.25
ns
1
8.9
ns
1
7.4
ns
This propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
6.7 Typical Characteristics
0.1
0.095
ICC (PA)
0.09
0.085
0.08
0.075
0.07
-45
-30
-15
0
15
30
45
Temperature (qC)
60
75
90
D001
Note device variation mentioned in Electrical Characteristics
Figure 1. ICC variation With Temperature
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7 Parameter Measurement Information
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
500 Ω
3V
Output
Control
LOAD CIRCUIT
1.5 V
1.5 V
0V
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
1.5 V
tPLZ
3.5 V
1.5 V
1.5 V
VOL
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
VOH
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
6
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8 Detailed Description
8.1 Overview
The SN74CBT3244 has eight bits of high-speed TTL-compatible bus switching. The switches are grouped in the
2 groups of 4 bits each. Each group has output-enabled inputs to allow signals to pass between A and B ports.
The signals can travel from A port to B port or vice versa.
The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. The
device is ideal for switching high speed digital signals between microprocessors and peripheral devices which is
useful in test applications, measurement applications, and control boards for factory automation.
8.2 Functional Block Diagram
2
18
1A1
1B1
8
12
1A4
1B4
1
1OE
11
9
2A1
2B1
3
17
2A4
2B4
19
2OE
Figure 3. Simplified Schematic
8.3 Feature Description
The SN74CBT3244 device support same pin configuration as industry standard '244. This device has a near
zero propagation delay allowing high speed signal switching up to 200 Mhz. The signals see lower distortion
since the device has low ON-resistance (5 Ω) coupled with low-output capacitance (6 pF) . SN74CBT3244 has a
very low power consumption in idle state consuming ICC of 50 µA only allowing power-saving for the system. The
device supports signal inputs any where between 0 V to 5 V.
8.4 Device Functional Modes
The device is organized as two 4-bit low-impedance switches with separate output-enable (OE) inputs.The
Output Enable OE is active low, implying when low A port is connected to B port. This switch is bidirectional in
nature. Asserting OE high will disconnect A port from B port. To ensure the high-impedance state during power
up or power down, OE should be tied to VCC through a pullup resistor. The minimum value of the resistor is
determined by the current-sinking capability of the driver.
Table 1. Function Table
(Each 4-Bit Bus Switch)
INPUT OE
FUNCTION
L
A port = B port
H
Disconnect
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74CBT3244 device can be used to control up to 4 bits with 2 channels simultaneously. The application
shown in Figure 4 is a 8-bit bus being controlled. The OE pins are used to control the chip from the bus
controller. This is a generic example and can apply to many situations. If an application requires fewer than 8
bits, ensure that the A side is tied either high or low on unused channels.
9.2 Typical Application
1OE
1A1
1
ron
2
1A2
1A3
1A4
Bus
Controller
8
2OE
2A1
1B2
1B3
ron
8
1B4
12
8
19
Device
ron
11
2B1
9
2A2
2A3
2A4
1B1
18
2B2
2B3
ron
17
3
10
20
Gnd
2B4
VCC
0.1uF
Figure 4. Typical Application
9.2.1 Design Requirements
A 0.1-µF bypass capacitor should be placed between each VCC pin and GND. Each capacitor should be placed
as close as possible to the SN74CBT3244 device.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For specified high and low levels, see VIH and VIL in Electrical Characteristics
– Inputs and outputs are overvoltage tolerant, which allows them to go as high as 5.5 V at any valid VCC
2. Recommended output conditions:
– Load currents must not exceed ±64 mA per channel
3. Frequency selection criterion:
– Added trace resistance or capacitance can reduce maximum frequency capability; use layout practices as
directed in Layout Guidelines
8
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Typical Application (continued)
9.2.3 Application Curve
14
VI = 0
VI = 2.4 V
ON-Resistance (RON)
12
10
8
6
4
2
0
-45
-30
-15
0
15
30
45
Temperature (qC)
60
75
90
D002
Figure 5. ON-Resistance (Ron) Variation vs Temperature
(1)
Note device variation mentioned in Electrical Characteristics
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Absolute Maximum Ratings table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dualsupply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must be installed as close to
the power terminal as possible for best results.
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11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self-inductance of the trace, which results in the reflection. Not all PCB traces can be straight;
therefore, some traces must turn corners. Figure 6 shows progressively better techniques of rounding corners.
Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 6. Trace Example
10
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74CBT3244DBQR
ACTIVE
SSOP
DBQ
20
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CBT3244
Samples
SN74CBT3244DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU244
Samples
SN74CBT3244DGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU244
Samples
SN74CBT3244DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBT3244
Samples
SN74CBT3244DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CBT3244
Samples
SN74CBT3244PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU244
Samples
SN74CBT3244PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU244
Samples
SN74CBT3244PWRE4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU244
Samples
SN74CBT3244PWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU244
Samples
SN74CBT3244RGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CU244
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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